diff --git a/.gitignore b/.gitignore
index 265959544978..86d18059b4f9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -37,6 +37,7 @@
 *.o
 *.o.*
 *.patch
+*.rmeta
 *.s
 *.so
 *.so.dbg
@@ -97,6 +98,7 @@ modules.order
 !.gitattributes
 !.gitignore
 !.mailmap
+!.rustfmt.toml
 
 #
 # Generated include files
@@ -162,3 +164,6 @@ x509.genkey
 
 # Documentation toolchain
 sphinx_*/
+
+# Rust analyzer configuration
+/rust-project.json
diff --git a/.mailmap b/.mailmap
index 825fae8e6b7b..2ed1cf869175 100644
--- a/.mailmap
+++ b/.mailmap
@@ -10,6 +10,8 @@
 # Please keep this list dictionary sorted.
 #
 Aaron Durbin <adurbin@google.com>
+Abel Vesa <abelvesa@kernel.org> <abel.vesa@nxp.com>
+Abel Vesa <abelvesa@kernel.org> <abelvesa@gmail.com>
 Abhinav Kumar <quic_abhinavk@quicinc.com> <abhinavk@codeaurora.org>
 Adam Oldham <oldhamca@gmail.com>
 Adam Radford <aradford@gmail.com>
@@ -85,6 +87,7 @@ Christian Borntraeger <borntraeger@linux.ibm.com> <borntrae@de.ibm.com>
 Christian Brauner <brauner@kernel.org> <christian@brauner.io>
 Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com>
 Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
+Christian Marangi <ansuelsmth@gmail.com>
 Christophe Ricard <christophe.ricard@gmail.com>
 Christoph Hellwig <hch@lst.de>
 Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
@@ -165,6 +168,7 @@ Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
 Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
 Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
 Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
+Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
 Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
diff --git a/.rustfmt.toml b/.rustfmt.toml
new file mode 100644
index 000000000000..3de5cc497465
--- /dev/null
+++ b/.rustfmt.toml
@@ -0,0 +1,12 @@
+edition = "2021"
+newline_style = "Unix"
+
+# Unstable options that help catching some mistakes in formatting and that we may want to enable
+# when they become stable.
+#
+# They are kept here since they are useful to run from time to time.
+#format_code_in_doc_comments = true
+#reorder_impl_items = true
+#comment_width = 100
+#wrap_comments = true
+#normalize_comments = true
diff --git a/Documentation/ABI/stable/sysfs-block b/Documentation/ABI/stable/sysfs-block
index e8797cd09aff..cd14ecb3c9a5 100644
--- a/Documentation/ABI/stable/sysfs-block
+++ b/Documentation/ABI/stable/sysfs-block
@@ -260,6 +260,15 @@ Description:
 		for discards, and don't read this file.
 
 
+What:		/sys/block/<disk>/queue/dma_alignment
+Date:		May 2022
+Contact:	linux-block@vger.kernel.org
+Description:
+		Reports the alignment that user space addresses must have to be
+		used for raw block device access with O_DIRECT and other driver
+		specific passthrough mechanisms.
+
+
 What:		/sys/block/<disk>/queue/fua
 Date:		May 2018
 Contact:	linux-block@vger.kernel.org
diff --git a/Documentation/ABI/testing/procfs-smaps_rollup b/Documentation/ABI/testing/procfs-smaps_rollup
index a4e31c465194..b446a7154a1b 100644
--- a/Documentation/ABI/testing/procfs-smaps_rollup
+++ b/Documentation/ABI/testing/procfs-smaps_rollup
@@ -22,6 +22,7 @@ Description:
 			MMUPageSize:           4 kB
 			Rss:		     884 kB
 			Pss:		     385 kB
+			Pss_Dirty:	      68 kB
 			Pss_Anon:	     301 kB
 			Pss_File:	      80 kB
 			Pss_Shmem:	       4 kB
diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
index d4ccc68fdcf0..3e00d7f7ee22 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio
+++ b/Documentation/ABI/testing/sysfs-bus-iio
@@ -79,6 +79,11 @@ Description:
 		* "accel-base"
 		* "accel-display"
 
+		For devices where an accelerometer is housed in the swivel camera subassembly
+		(for AR application), the following standardized label is used:
+
+		* "accel-camera"
+
 What:		/sys/bus/iio/devices/iio:deviceX/current_timestamp_clock
 KernelVersion:	4.5
 Contact:	linux-iio@vger.kernel.org
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-vf610 b/Documentation/ABI/testing/sysfs-bus-iio-vf610
index 308a6756d3bf..491ead804488 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio-vf610
+++ b/Documentation/ABI/testing/sysfs-bus-iio-vf610
@@ -1,4 +1,4 @@
-What:		/sys/bus/iio/devices/iio:deviceX/conversion_mode
+What:		/sys/bus/iio/devices/iio:deviceX/in_conversion_mode
 KernelVersion:	4.2
 Contact:	linux-iio@vger.kernel.org
 Description:
diff --git a/Documentation/ABI/testing/sysfs-bus-usb b/Documentation/ABI/testing/sysfs-bus-usb
index 7efe31ed3a25..568103d3376e 100644
--- a/Documentation/ABI/testing/sysfs-bus-usb
+++ b/Documentation/ABI/testing/sysfs-bus-usb
@@ -253,6 +253,17 @@ Description:
 		only if the system firmware is capable of describing the
 		connection between a port and its connector.
 
+What:		/sys/bus/usb/devices/.../<hub_interface>/port<X>/disable
+Date:		June 2022
+Contact:	Michael Grzeschik <m.grzeschik@pengutronix.de>
+Description:
+		This file controls the state of a USB port, including
+		Vbus power output (but only on hubs that support
+		power switching -- most hubs don't support it). If
+		a port is disabled, the port is unusable: Devices
+		attached to the port will not be detected, initialized,
+		or enumerated.
+
 What:		/sys/bus/usb/devices/.../power/usb2_lpm_l1_timeout
 Date:		May 2013
 Contact:	Mathias Nyman <mathias.nyman@linux.intel.com>
diff --git a/Documentation/ABI/testing/sysfs-class-hwmon b/Documentation/ABI/testing/sysfs-class-hwmon
index 653d4c75eddb..7271781a23b2 100644
--- a/Documentation/ABI/testing/sysfs-class-hwmon
+++ b/Documentation/ABI/testing/sysfs-class-hwmon
@@ -938,3 +938,12 @@ Description:
 		- 1: enable
 
 		RW
+
+What:		/sys/class/hwmon/hwmonX/device/pec
+Description:
+		PEC support on I2C devices
+
+		- 0, off, n: disable
+		- 1, on, y: enable
+
+		RW
diff --git a/Documentation/ABI/testing/sysfs-class-typec b/Documentation/ABI/testing/sysfs-class-typec
index 75088ecad202..281b995beb05 100644
--- a/Documentation/ABI/testing/sysfs-class-typec
+++ b/Documentation/ABI/testing/sysfs-class-typec
@@ -141,6 +141,14 @@ Description:
 		- "reverse": CC2 orientation
 		- "unknown": Orientation cannot be determined.
 
+What:		/sys/class/typec/<port>/select_usb_power_delivery
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Lists the USB Power Delivery Capabilities that the port can
+		advertise to the partner. The currently used capabilities are in
+		brackets. Selection happens by writing to the file.
+
 USB Type-C partner devices (eg. /sys/class/typec/port0-partner/)
 
 What:		/sys/class/typec/<port>-partner/accessory_mode
diff --git a/Documentation/ABI/testing/sysfs-class-usb_power_delivery b/Documentation/ABI/testing/sysfs-class-usb_power_delivery
new file mode 100644
index 000000000000..ce2b1b563cb3
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-usb_power_delivery
@@ -0,0 +1,240 @@
+What:		/sys/class/usb_power_delivery
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Directory for USB Power Delivery devices.
+
+What:		/sys/class/usb_power_delivery/.../revision
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		File showing the USB Power Delivery Specification Revision used
+		in communication.
+
+What:		/sys/class/usb_power_delivery/.../version
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This is an optional attribute file showing the version of the
+		specific revision of the USB Power Delivery Specification. In
+		most cases the specification version is not known and the file
+		is not available.
+
+What:		/sys/class/usb_power_delivery/.../source-capabilities
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The source capabilities message "Source_Capabilities" contains a
+		set of Power Data Objects (PDO), each representing a type of
+		power supply. The order of the PDO objects is defined in the USB
+		Power Delivery Specification. Each PDO - power supply - will
+		have its own device, and the PDO device name will start with the
+		object position number as the first character followed by the
+		power supply type name (":" as delimiter).
+
+			/sys/class/usb_power_delivery/.../source_capabilities/<position>:<type>
+
+What:		/sys/class/usb_power_delivery/.../sink-capabilities
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The sink capability message "Sink_Capabilities" contains a set
+		of Power Data Objects (PDO) just like with source capabilities,
+		but instead of describing the power capabilities, these objects
+		describe the power requirements.
+
+		The order of the objects in the sink capability message is the
+		same as with the source capabilities message.
+
+Fixed Supplies
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:fixed_supply
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Devices containing the attributes (the bit fields) defined for
+		Fixed Supplies.
+
+		The device "1:fixed_supply" is special. USB Power Delivery
+		Specification dictates that the first PDO (at object position
+		1), and the only mandatory PDO, is always the vSafe5V Fixed
+		Supply Object. vSafe5V Object has additional fields defined for
+		it that the other Fixed Supply Objects do not have and that are
+		related to the USB capabilities rather than power capabilities.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/dual_role_power
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file contains boolean value that tells does the device
+		support both source and sink power roles.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/usb_suspend_supported
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file shows the value of the USB Suspend Supported bit in
+		vSafe5V Fixed Supply Object. If the bit is set then the device
+		will follow the USB 2.0 and USB 3.2 rules for suspend and
+		resume.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/unconstrained_power
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file shows the value of the Unconstrained Power bit in
+		vSafe5V Fixed Supply Object. The bit is set when an external
+		source of power, powerful enough to power the entire system on
+		its own, is available for the device.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/usb_communication_capable
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file shows the value of the USB Communication Capable bit in
+		vSafe5V Fixed Supply Object.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/dual_role_data
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file shows the value of the Dual-Role Data bit in vSafe5V
+		Fixed Supply Object. Dual role data means ability act as both
+		USB host and USB device.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/1:fixed_supply/unchunked_extended_messages_supported
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file shows the value of the Unchunked Extended Messages
+		Supported bit in vSafe5V Fixed Supply Object.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:fixed_supply/voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The voltage the supply supports in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../source-capabilities/<position>:fixed_supply/maximum_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum current of the fixed source supply in milliamperes.
+
+What:		/sys/class/usb_power_delivery/.../sink-capabilities/<position>:fixed_supply/operational_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Operational current of the sink in milliamperes.
+
+What:		/sys/class/usb_power_delivery/.../sink-capabilities/<position>:fixed_supply/fast_role_swap_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		This file contains the value of the "Fast Role Swap USB Type-C
+		Current" field that tells the current level the sink requires
+		after a Fast Role Swap.
+		0 - Fast Swap not supported"
+		1 - Default USB Power"
+		2 - 1.5A@5V"
+		3 - 3.0A@5V"
+
+Variable Supplies
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Variable Power Supply PDO.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply/maximum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:variable_supply/minimum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Minimum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../source-capabilities/<position>:variable_supply/maximum_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The maximum current in milliamperes that the source can supply
+		at the given Voltage range.
+
+What:		/sys/class/usb_power_delivery/.../sink-capabilities/<position>:variable_supply/operational_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The operational current in milliamperes that the sink requires
+		at the given Voltage range.
+
+Battery Supplies
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:battery
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Battery PDO.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:battery/maximum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:battery/minimum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Minimum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../source-capabilities/<position>:battery/maximum_power
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum allowable Power in milliwatts.
+
+What:		/sys/class/usb_power_delivery/.../sink-capabilities/<position>:battery/operational_power
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The operational power that the sink requires at the given
+		voltage range.
+
+Standard Power Range (SPR) Programmable Power Supplies
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Programmable Power Supply (PPS) Augmented PDO (APDO).
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/maximum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/minimum_voltage
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Minimum Voltage in millivolts.
+
+What:		/sys/class/usb_power_delivery/.../<capability>/<position>:programmable_supply/maximum_current
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		Maximum Current in milliamperes.
+
+What:		/sys/class/usb_power_delivery/.../source-capabilities/<position>:programmable_supply/pps_power_limited
+Date:		May 2022
+Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Description:
+		The PPS Power Limited bit indicates whether or not the source
+		supply will exceed the rated output power if requested.
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
new file mode 100644
index 000000000000..0a41afe0ab4c
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
@@ -0,0 +1,61 @@
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns the root entry hash for the static
+		region if one is programmed, else it returns the
+		string: "hash not programmed".  This file is only
+		visible if the underlying device supports it.
+		Format: string.
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns the root entry hash for the partial
+		reconfiguration region if one is programmed, else it
+		returns the string: "hash not programmed".  This file
+		is only visible if the underlying device supports it.
+		Format: string.
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns the root entry hash for the BMC image
+		if one is programmed, else it returns the string:
+		"hash not programmed".  This file is only visible if the
+		underlying device supports it.
+		Format: string.
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns a list of indices for canceled code
+		signing keys for the static region. The standard bitmap
+		list format is used (e.g. "1,2-6,9").
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns a list of indices for canceled code
+		signing keys for the partial reconfiguration region. The
+		standard bitmap list format is used (e.g. "1,2-6,9").
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns a list of indices for canceled code
+		signing keys for the BMC.  The standard bitmap list format
+		is used (e.g. "1,2-6,9").
+
+What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
+Date:		Sep 2022
+KernelVersion:	5.20
+Contact:	Russ Weight <russell.h.weight@intel.com>
+Description:	Read only. Returns number of times the secure update
+		staging area has been flashed.
+		Format: "%u".
diff --git a/Documentation/PCI/endpoint/index.rst b/Documentation/PCI/endpoint/index.rst
index 38ea1f604b6d..4d2333e7ae06 100644
--- a/Documentation/PCI/endpoint/index.rst
+++ b/Documentation/PCI/endpoint/index.rst
@@ -13,6 +13,8 @@ PCI Endpoint Framework
    pci-test-howto
    pci-ntb-function
    pci-ntb-howto
+   pci-vntb-function
+   pci-vntb-howto
 
    function/binding/pci-test
    function/binding/pci-ntb
diff --git a/Documentation/PCI/endpoint/pci-vntb-function.rst b/Documentation/PCI/endpoint/pci-vntb-function.rst
new file mode 100644
index 000000000000..cad8013e8839
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-vntb-function.rst
@@ -0,0 +1,126 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=================
+PCI vNTB Function
+=================
+
+:Author: Frank Li <Frank.Li@nxp.com>
+
+The difference between PCI NTB function and PCI vNTB function is
+
+PCI NTB function need at two endpoint instances and connect HOST1
+and HOST2.
+
+PCI vNTB function only use one host and one endpoint(EP), use NTB
+connect EP and PCI host
+
+.. code-block:: text
+
+
+  +------------+         +---------------------------------------+
+  |            |         |                                       |
+  +------------+         |                        +--------------+
+  | NTB        |         |                        | NTB          |
+  | NetDev     |         |                        | NetDev       |
+  +------------+         |                        +--------------+
+  | NTB        |         |                        | NTB          |
+  | Transfer   |         |                        | Transfer     |
+  +------------+         |                        +--------------+
+  |            |         |                        |              |
+  |  PCI NTB   |         |                        |              |
+  |    EPF     |         |                        |              |
+  |   Driver   |         |                        | PCI Virtual  |
+  |            |         +---------------+        | NTB Driver   |
+  |            |         | PCI EP NTB    |<------>|              |
+  |            |         |  FN Driver    |        |              |
+  +------------+         +---------------+        +--------------+
+  |            |         |               |        |              |
+  |  PCI BUS   | <-----> |  PCI EP BUS   |        |  Virtual PCI |
+  |            |  PCI    |               |        |     BUS      |
+  +------------+         +---------------+--------+--------------+
+      PCI RC                        PCI EP
+
+Constructs used for Implementing vNTB
+=====================================
+
+	1) Config Region
+	2) Self Scratchpad Registers
+	3) Peer Scratchpad Registers
+	4) Doorbell (DB) Registers
+	5) Memory Window (MW)
+
+
+Config Region:
+--------------
+
+It is same as PCI NTB Function driver
+
+Scratchpad Registers:
+---------------------
+
+  It is appended after Config region.
+
+  +--------------------------------------------------+ Base
+  |                                                  |
+  |                                                  |
+  |                                                  |
+  |          Common Config Register                  |
+  |                                                  |
+  |                                                  |
+  |                                                  |
+  +-----------------------+--------------------------+ Base + span_offset
+  |                       |                          |
+  |    Peer Span Space    |    Span Space            |
+  |                       |                          |
+  |                       |                          |
+  +-----------------------+--------------------------+ Base + span_offset
+  |                       |                          |      + span_count * 4
+  |                       |                          |
+  |     Span Space        |   Peer Span Space        |
+  |                       |                          |
+  +-----------------------+--------------------------+
+        Virtual PCI             Pcie Endpoint
+        NTB Driver               NTB Driver
+
+
+Doorbell Registers:
+-------------------
+
+  Doorbell Registers are used by the hosts to interrupt each other.
+
+Memory Window:
+--------------
+
+  Actual transfer of data between the two hosts will happen using the
+  memory window.
+
+Modeling Constructs:
+====================
+
+32-bit BARs.
+
+======  ===============
+BAR NO  CONSTRUCTS USED
+======  ===============
+BAR0    Config Region
+BAR1    Doorbell
+BAR2    Memory Window 1
+BAR3    Memory Window 2
+BAR4    Memory Window 3
+BAR5    Memory Window 4
+======  ===============
+
+64-bit BARs.
+
+======  ===============================
+BAR NO  CONSTRUCTS USED
+======  ===============================
+BAR0    Config Region + Scratchpad
+BAR1
+BAR2    Doorbell
+BAR3
+BAR4    Memory Window 1
+BAR5
+======  ===============================
+
+
diff --git a/Documentation/PCI/endpoint/pci-vntb-howto.rst b/Documentation/PCI/endpoint/pci-vntb-howto.rst
new file mode 100644
index 000000000000..b4a679144692
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-vntb-howto.rst
@@ -0,0 +1,161 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===================================================================
+PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
+===================================================================
+
+:Author: Frank Li <Frank.Li@nxp.com>
+
+This document is a guide to help users use pci-epf-vntb function driver
+and ntb_hw_epf host driver for NTB functionality. The list of steps to
+be followed in the host side and EP side is given below. For the hardware
+configuration and internals of NTB using configurable endpoints see
+Documentation/PCI/endpoint/pci-vntb-function.rst
+
+Endpoint Device
+===============
+
+Endpoint Controller Devices
+---------------------------
+
+To find the list of endpoint controller devices in the system::
+
+        # ls /sys/class/pci_epc/
+          5f010000.pcie_ep
+
+If PCI_ENDPOINT_CONFIGFS is enabled::
+
+        # ls /sys/kernel/config/pci_ep/controllers
+          5f010000.pcie_ep
+
+Endpoint Function Drivers
+-------------------------
+
+To find the list of endpoint function drivers in the system::
+
+	# ls /sys/bus/pci-epf/drivers
+	pci_epf_ntb  pci_epf_test  pci_epf_vntb
+
+If PCI_ENDPOINT_CONFIGFS is enabled::
+
+	# ls /sys/kernel/config/pci_ep/functions
+	pci_epf_ntb  pci_epf_test  pci_epf_vntb
+
+
+Creating pci-epf-vntb Device
+----------------------------
+
+PCI endpoint function device can be created using the configfs. To create
+pci-epf-vntb device, the following commands can be used::
+
+	# mount -t configfs none /sys/kernel/config
+	# cd /sys/kernel/config/pci_ep/
+	# mkdir functions/pci_epf_vntb/func1
+
+The "mkdir func1" above creates the pci-epf-ntb function device that will
+be probed by pci_epf_vntb driver.
+
+The PCI endpoint framework populates the directory with the following
+configurable fields::
+
+	# ls functions/pci_epf_ntb/func1
+	baseclass_code    deviceid          msi_interrupts    pci-epf-ntb.0
+	progif_code       secondary         subsys_id         vendorid
+	cache_line_size   interrupt_pin     msix_interrupts   primary
+	revid             subclass_code     subsys_vendor_id
+
+The PCI endpoint function driver populates these entries with default values
+when the device is bound to the driver. The pci-epf-vntb driver populates
+vendorid with 0xffff and interrupt_pin with 0x0001::
+
+	# cat functions/pci_epf_vntb/func1/vendorid
+	0xffff
+	# cat functions/pci_epf_vntb/func1/interrupt_pin
+	0x0001
+
+
+Configuring pci-epf-vntb Device
+-------------------------------
+
+The user can configure the pci-epf-vntb device using its configfs entry. In order
+to change the vendorid and the deviceid, the following
+commands can be used::
+
+	# echo 0x1957 > functions/pci_epf_vntb/func1/vendorid
+	# echo 0x0809 > functions/pci_epf_vntb/func1/deviceid
+
+In order to configure NTB specific attributes, a new sub-directory to func1
+should be created::
+
+	# mkdir functions/pci_epf_vntb/func1/pci_epf_vntb.0/
+
+The NTB function driver will populate this directory with various attributes
+that can be configured by the user::
+
+	# ls functions/pci_epf_vntb/func1/pci_epf_vntb.0/
+	db_count    mw1         mw2         mw3         mw4         num_mws
+	spad_count
+
+A sample configuration for NTB function is given below::
+
+	# echo 4 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/db_count
+	# echo 128 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/spad_count
+	# echo 1 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/num_mws
+	# echo 0x100000 > functions/pci_epf_vntb/func1/pci_epf_vntb.0/mw1
+
+Binding pci-epf-ntb Device to EP Controller
+--------------------------------------------
+
+NTB function device should be attached to PCI endpoint controllers
+connected to the host.
+
+	# ln -s controllers/5f010000.pcie_ep functions/pci-epf-ntb/func1/primary
+
+Once the above step is completed, the PCI endpoint controllers are ready to
+establish a link with the host.
+
+
+Start the Link
+--------------
+
+In order for the endpoint device to establish a link with the host, the _start_
+field should be populated with '1'. For NTB, both the PCI endpoint controllers
+should establish link with the host (imx8 don't need this steps)::
+
+	# echo 1 > controllers/5f010000.pcie_ep/start
+
+RootComplex Device
+==================
+
+lspci Output at Host side
+------------------------
+
+Note that the devices listed here correspond to the values populated in
+"Creating pci-epf-ntb Device" section above::
+
+	# lspci
+        00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01)
+        01:00.0 RAM memory: Freescale Semiconductor Inc Device 0809
+
+Endpoint Device / Virtual PCI bus
+=================================
+
+lspci Output at EP Side / Virtual PCI bus
+-----------------------------------------
+
+Note that the devices listed here correspond to the values populated in
+"Creating pci-epf-ntb Device" section above::
+
+        # lspci
+        10:00.0 Unassigned class [ffff]: Dawicontrol Computersysteme GmbH Device 1234 (rev ff)
+
+Using ntb_hw_epf Device
+-----------------------
+
+The host side software follows the standard NTB software architecture in Linux.
+All the existing client side NTB utilities like NTB Transport Client and NTB
+Netdev, NTB Ping Pong Test Client and NTB Tool Test Client can be used with NTB
+function device.
+
+For more information on NTB see
+:doc:`Non-Transparent Bridge <../../driver-api/ntb>`
diff --git a/Documentation/RCU/Design/Requirements/Requirements.rst b/Documentation/RCU/Design/Requirements/Requirements.rst
index 04ed8bf27a0e..a0f8164c8513 100644
--- a/Documentation/RCU/Design/Requirements/Requirements.rst
+++ b/Documentation/RCU/Design/Requirements/Requirements.rst
@@ -1844,10 +1844,10 @@ that meets this requirement.
 
 Furthermore, NMI handlers can be interrupted by what appear to RCU to be
 normal interrupts. One way that this can happen is for code that
-directly invokes rcu_irq_enter() and rcu_irq_exit() to be called
+directly invokes ct_irq_enter() and ct_irq_exit() to be called
 from an NMI handler. This astonishing fact of life prompted the current
-code structure, which has rcu_irq_enter() invoking
-rcu_nmi_enter() and rcu_irq_exit() invoking rcu_nmi_exit().
+code structure, which has ct_irq_enter() invoking
+ct_nmi_enter() and ct_irq_exit() invoking ct_nmi_exit().
 And yes, I also learned of this requirement the hard way.
 
 Loadable Modules
@@ -2195,7 +2195,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be:
    sections, and RCU believes this CPU to be idle, no problem. This
    sort of thing is used by some architectures for light-weight
    exception handlers, which can then avoid the overhead of
-   rcu_irq_enter() and rcu_irq_exit() at exception entry and
+   ct_irq_enter() and ct_irq_exit() at exception entry and
    exit, respectively. Some go further and avoid the entireties of
    irq_enter() and irq_exit().
    Just make very sure you are running some of your tests with
@@ -2226,7 +2226,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be:
 +-----------------------------------------------------------------------+
 | **Answer**:                                                           |
 +-----------------------------------------------------------------------+
-| One approach is to do ``rcu_irq_exit();rcu_irq_enter();`` every so    |
+| One approach is to do ``ct_irq_exit();ct_irq_enter();`` every so      |
 | often. But given that long-running interrupt handlers can cause other |
 | problems, not least for response time, shouldn't you work to keep     |
 | your interrupt handler's runtime within reasonable bounds?            |
diff --git a/Documentation/RCU/stallwarn.rst b/Documentation/RCU/stallwarn.rst
index 794837eb519b..e38c587067fc 100644
--- a/Documentation/RCU/stallwarn.rst
+++ b/Documentation/RCU/stallwarn.rst
@@ -97,12 +97,12 @@ warnings:
 	which will include additional debugging information.
 
 -	A low-level kernel issue that either fails to invoke one of the
-	variants of rcu_user_enter(), rcu_user_exit(), rcu_idle_enter(),
-	rcu_idle_exit(), rcu_irq_enter(), or rcu_irq_exit() on the one
+	variants of rcu_eqs_enter(true), rcu_eqs_exit(true), ct_idle_enter(),
+	ct_idle_exit(), ct_irq_enter(), or ct_irq_exit() on the one
 	hand, or that invokes one of them too many times on the other.
 	Historically, the most frequent issue has been an omission
 	of either irq_enter() or irq_exit(), which in turn invoke
-	rcu_irq_enter() or rcu_irq_exit(), respectively.  Building your
+	ct_irq_enter() or ct_irq_exit(), respectively.  Building your
 	kernel with CONFIG_RCU_EQS_DEBUG=y can help track down these types
 	of issues, which sometimes arise in architecture-specific code.
 
diff --git a/Documentation/admin-guide/cgroup-v1/memcg_test.rst b/Documentation/admin-guide/cgroup-v1/memcg_test.rst
index 45b94f7b3beb..a402359abb99 100644
--- a/Documentation/admin-guide/cgroup-v1/memcg_test.rst
+++ b/Documentation/admin-guide/cgroup-v1/memcg_test.rst
@@ -97,7 +97,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
 =============
 
 	Page Cache is charged at
-	- add_to_page_cache_locked().
+	- filemap_add_folio().
 
 	The logic is very clear. (About migration, see below)
 
diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst
index 176298f2f4de..ad9ba3ec90a5 100644
--- a/Documentation/admin-guide/cgroup-v2.rst
+++ b/Documentation/admin-guide/cgroup-v2.rst
@@ -1433,6 +1433,24 @@ PAGE_SIZE multiple when read back.
 	  workingset_nodereclaim
 		Number of times a shadow node has been reclaimed
 
+	  pgscan (npn)
+		Amount of scanned pages (in an inactive LRU list)
+
+	  pgsteal (npn)
+		Amount of reclaimed pages
+
+	  pgscan_kswapd (npn)
+		Amount of scanned pages by kswapd (in an inactive LRU list)
+
+	  pgscan_direct (npn)
+		Amount of scanned pages directly  (in an inactive LRU list)
+
+	  pgsteal_kswapd (npn)
+		Amount of reclaimed pages by kswapd
+
+	  pgsteal_direct (npn)
+		Amount of reclaimed pages directly
+
 	  pgfault (npn)
 		Total number of page faults incurred
 
@@ -1442,12 +1460,6 @@ PAGE_SIZE multiple when read back.
 	  pgrefill (npn)
 		Amount of scanned pages (in an active LRU list)
 
-	  pgscan (npn)
-		Amount of scanned pages (in an inactive LRU list)
-
-	  pgsteal (npn)
-		Amount of reclaimed pages
-
 	  pgactivate (npn)
 		Amount of pages moved to the active LRU list
 
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 2522b11e593f..f50e1fc6e51b 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -550,7 +550,7 @@
 			nosocket -- Disable socket memory accounting.
 			nokmem -- Disable kernel memory accounting.
 
-	checkreqprot	[SELINUX] Set initial checkreqprot flag value.
+	checkreqprot=	[SELINUX] Set initial checkreqprot flag value.
 			Format: { "0" | "1" }
 			See security/selinux/Kconfig help text.
 			0 -- check protection applied by kernel (includes
@@ -1439,7 +1439,7 @@
 			(in particular on some ATI chipsets).
 			The kernel tries to set a reasonable default.
 
-	enforcing	[SELINUX] Set initial enforcing status.
+	enforcing=	[SELINUX] Set initial enforcing status.
 			Format: {"0" | "1"}
 			See security/selinux/Kconfig help text.
 			0 -- permissive (log only, no denials).
@@ -1667,6 +1667,19 @@
 
 	hlt		[BUGS=ARM,SH]
 
+	hostname=	[KNL] Set the hostname (aka UTS nodename).
+			Format: <string>
+			This allows setting the system's hostname during early
+			startup. This sets the name returned by gethostname.
+			Using this parameter to set the hostname makes it
+			possible to ensure the hostname is correctly set before
+			any userspace processes run, avoiding the possibility
+			that a process may call gethostname before the hostname
+			has been explicitly set, resulting in the calling
+			process getting an incorrect result. The string must
+			not exceed the maximum allowed hostname length (usually
+			64 characters) and will be truncated otherwise.
+
 	hpet=		[X86-32,HPET] option to control HPET usage
 			Format: { enable (default) | disable | force |
 				verbose }
@@ -1722,9 +1735,11 @@
 			Built with CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y,
 			the default is on.
 
-			This is not compatible with memory_hotplug.memmap_on_memory.
-			If both parameters are enabled, hugetlb_free_vmemmap takes
-			precedence over memory_hotplug.memmap_on_memory.
+			Note that the vmemmap pages may be allocated from the added
+			memory block itself when memory_hotplug.memmap_on_memory is
+			enabled, those vmemmap pages cannot be optimized even if this
+			feature is enabled.  Other vmemmap pages not allocated from
+			the added memory block itself do not be affected.
 
 	hung_task_panic=
 			[KNL] Should the hung task detector generate panics.
@@ -3068,10 +3083,12 @@
 			[KNL,X86,ARM] Boolean flag to enable this feature.
 			Format: {on | off (default)}
 			When enabled, runtime hotplugged memory will
-			allocate its internal metadata (struct pages)
-			from the hotadded memory which will allow to
-			hotadd a lot of memory without requiring
-			additional memory to do so.
+			allocate its internal metadata (struct pages,
+			those vmemmap pages cannot be optimized even
+			if hugetlb_free_vmemmap is enabled) from the
+			hotadded memory which will allow to hotadd a
+			lot of memory without requiring additional
+			memory to do so.
 			This feature is disabled by default because it
 			has some implication on large (e.g. GB)
 			allocations in some configurations (e.g. small
@@ -3081,10 +3098,6 @@
 			Note that even when enabled, there are a few cases where
 			the feature is not effective.
 
-			This is not compatible with hugetlb_free_vmemmap. If
-			both parameters are enabled, hugetlb_free_vmemmap takes
-			precedence over memory_hotplug.memmap_on_memory.
-
 	memtest=	[KNL,X86,ARM,M68K,PPC,RISCV] Enable memtest
 			Format: <integer>
 			default : 0 <disable>
@@ -3659,6 +3672,9 @@
 			just as if they had also been called out in the
 			rcu_nocbs= boot parameter.
 
+			Note that this argument takes precedence over
+			the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option.
+
 	noiotrap	[SH] Disables trapped I/O port accesses.
 
 	noirqdebug	[X86-32] Disables the code which attempts to detect and
@@ -4557,6 +4573,9 @@
 			no-callback mode from boot but the mode may be
 			toggled at runtime via cpusets.
 
+			Note that this argument takes precedence over
+			the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option.
+
 	rcu_nocb_poll	[KNL]
 			Rather than requiring that offloaded CPUs
 			(specified by rcu_nocbs= above) explicitly
@@ -4666,6 +4685,34 @@
 			When RCU_NOCB_CPU is set, also adjust the
 			priority of NOCB callback kthreads.
 
+	rcutree.rcu_divisor= [KNL]
+			Set the shift-right count to use to compute
+			the callback-invocation batch limit bl from
+			the number of callbacks queued on this CPU.
+			The result will be bounded below by the value of
+			the rcutree.blimit kernel parameter.  Every bl
+			callbacks, the softirq handler will exit in
+			order to allow the CPU to do other work.
+
+			Please note that this callback-invocation batch
+			limit applies only to non-offloaded callback
+			invocation.  Offloaded callbacks are instead
+			invoked in the context of an rcuoc kthread, which
+			scheduler will preempt as it does any other task.
+
+	rcutree.nocb_nobypass_lim_per_jiffy= [KNL]
+			On callback-offloaded (rcu_nocbs) CPUs,
+			RCU reduces the lock contention that would
+			otherwise be caused callback floods through
+			use of the ->nocb_bypass list.	However, in the
+			common non-flooded case, RCU queues directly to
+			the main ->cblist in order to avoid the extra
+			overhead of the ->nocb_bypass list and its lock.
+			But if there are too many callbacks queued during
+			a single jiffy, RCU pre-queues the callbacks into
+			the ->nocb_bypass queue.  The definition of "too
+			many" is supplied by this kernel boot parameter.
+
 	rcutree.rcu_nocb_gp_stride= [KNL]
 			Set the number of NOCB callback kthreads in
 			each group, which defaults to the square root
diff --git a/Documentation/admin-guide/media/vivid.rst b/Documentation/admin-guide/media/vivid.rst
index 6d7175f96f74..4f680dc9661c 100644
--- a/Documentation/admin-guide/media/vivid.rst
+++ b/Documentation/admin-guide/media/vivid.rst
@@ -714,6 +714,20 @@ The Test Pattern Controls are all specific to video capture.
 
 	does the same for the EAV (End of Active Video) code.
 
+- Insert Video Guard Band
+
+	adds 4 columns of pixels with the HDMI Video Guard Band code at the
+	left hand side of the image. This only works with 3 or 4 byte RGB pixel
+	formats. The RGB pixel value 0xab/0x55/0xab turns out to be equivalent
+	to the HDMI Video Guard Band code that precedes each active video line
+	(see section 5.2.2.1 in the HDMI 1.3 Specification). To test if a video
+	receiver has correct HDMI Video Guard Band processing, enable this
+	control and then move the image to the left hand side of the screen.
+	That will result in video lines that start with multiple pixels that
+	have the same value as the Video Guard Band that precedes them.
+	Receivers that will just keep skipping Video Guard Band values will
+	now fail and either loose sync or these video lines will shift.
+
 
 Capture Feature Selection Controls
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/Documentation/admin-guide/mm/damon/index.rst b/Documentation/admin-guide/mm/damon/index.rst
index 61aff88347f3..53762770e0e4 100644
--- a/Documentation/admin-guide/mm/damon/index.rst
+++ b/Documentation/admin-guide/mm/damon/index.rst
@@ -14,3 +14,4 @@ optimize those.
    start
    usage
    reclaim
+   lru_sort
diff --git a/Documentation/admin-guide/mm/damon/lru_sort.rst b/Documentation/admin-guide/mm/damon/lru_sort.rst
new file mode 100644
index 000000000000..c09cace80651
--- /dev/null
+++ b/Documentation/admin-guide/mm/damon/lru_sort.rst
@@ -0,0 +1,294 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=============================
+DAMON-based LRU-lists Sorting
+=============================
+
+DAMON-based LRU-lists Sorting (DAMON_LRU_SORT) is a static kernel module that
+aimed to be used for proactive and lightweight data access pattern based
+(de)prioritization of pages on their LRU-lists for making LRU-lists a more
+trusworthy data access pattern source.
+
+Where Proactive LRU-lists Sorting is Required?
+==============================================
+
+As page-granularity access checking overhead could be significant on huge
+systems, LRU lists are normally not proactively sorted but partially and
+reactively sorted for special events including specific user requests, system
+calls and memory pressure.  As a result, LRU lists are sometimes not so
+perfectly prepared to be used as a trustworthy access pattern source for some
+situations including reclamation target pages selection under sudden memory
+pressure.
+
+Because DAMON can identify access patterns of best-effort accuracy while
+inducing only user-specified range of overhead, proactively running
+DAMON_LRU_SORT could be helpful for making LRU lists more trustworthy access
+pattern source with low and controlled overhead.
+
+How It Works?
+=============
+
+DAMON_LRU_SORT finds hot pages (pages of memory regions that showing access
+rates that higher than a user-specified threshold) and cold pages (pages of
+memory regions that showing no access for a time that longer than a
+user-specified threshold) using DAMON, and prioritizes hot pages while
+deprioritizing cold pages on their LRU-lists.  To avoid it consuming too much
+CPU for the prioritizations, a CPU time usage limit can be configured.  Under
+the limit, it prioritizes and deprioritizes more hot and cold pages first,
+respectively.  System administrators can also configure under what situation
+this scheme should automatically activated and deactivated with three memory
+pressure watermarks.
+
+Its default parameters for hotness/coldness thresholds and CPU quota limit are
+conservatively chosen.  That is, the module under its default parameters could
+be widely used without harm for common situations while providing a level of
+benefits for systems having clear hot/cold access patterns under memory
+pressure while consuming only a limited small portion of CPU time.
+
+Interface: Module Parameters
+============================
+
+To use this feature, you should first ensure your system is running on a kernel
+that is built with ``CONFIG_DAMON_LRU_SORT=y``.
+
+To let sysadmins enable or disable it and tune for the given system,
+DAMON_LRU_SORT utilizes module parameters.  That is, you can put
+``damon_lru_sort.<parameter>=<value>`` on the kernel boot command line or write
+proper values to ``/sys/modules/damon_lru_sort/parameters/<parameter>`` files.
+
+Below are the description of each parameter.
+
+enabled
+-------
+
+Enable or disable DAMON_LRU_SORT.
+
+You can enable DAMON_LRU_SORT by setting the value of this parameter as ``Y``.
+Setting it as ``N`` disables DAMON_LRU_SORT.  Note that DAMON_LRU_SORT could do
+no real monitoring and LRU-lists sorting due to the watermarks-based activation
+condition.  Refer to below descriptions for the watermarks parameter for this.
+
+commit_inputs
+-------------
+
+Make DAMON_LRU_SORT reads the input parameters again, except ``enabled``.
+
+Input parameters that updated while DAMON_LRU_SORT is running are not applied
+by default.  Once this parameter is set as ``Y``, DAMON_LRU_SORT reads values
+of parametrs except ``enabled`` again.  Once the re-reading is done, this
+parameter is set as ``N``.  If invalid parameters are found while the
+re-reading, DAMON_LRU_SORT will be disabled.
+
+hot_thres_access_freq
+---------------------
+
+Access frequency threshold for hot memory regions identification in permil.
+
+If a memory region is accessed in frequency of this or higher, DAMON_LRU_SORT
+identifies the region as hot, and mark it as accessed on the LRU list, so that
+it could not be reclaimed under memory pressure.  50% by default.
+
+cold_min_age
+------------
+
+Time threshold for cold memory regions identification in microseconds.
+
+If a memory region is not accessed for this or longer time, DAMON_LRU_SORT
+identifies the region as cold, and mark it as unaccessed on the LRU list, so
+that it could be reclaimed first under memory pressure.  120 seconds by
+default.
+
+quota_ms
+--------
+
+Limit of time for trying the LRU lists sorting in milliseconds.
+
+DAMON_LRU_SORT tries to use only up to this time within a time window
+(quota_reset_interval_ms) for trying LRU lists sorting.  This can be used
+for limiting CPU consumption of DAMON_LRU_SORT.  If the value is zero, the
+limit is disabled.
+
+10 ms by default.
+
+quota_reset_interval_ms
+-----------------------
+
+The time quota charge reset interval in milliseconds.
+
+The charge reset interval for the quota of time (quota_ms).  That is,
+DAMON_LRU_SORT does not try LRU-lists sorting for more than quota_ms
+milliseconds or quota_sz bytes within quota_reset_interval_ms milliseconds.
+
+1 second by default.
+
+wmarks_interval
+---------------
+
+The watermarks check time interval in microseconds.
+
+Minimal time to wait before checking the watermarks, when DAMON_LRU_SORT is
+enabled but inactive due to its watermarks rule.  5 seconds by default.
+
+wmarks_high
+-----------
+
+Free memory rate (per thousand) for the high watermark.
+
+If free memory of the system in bytes per thousand bytes is higher than this,
+DAMON_LRU_SORT becomes inactive, so it does nothing but periodically checks the
+watermarks.  200 (20%) by default.
+
+wmarks_mid
+----------
+
+Free memory rate (per thousand) for the middle watermark.
+
+If free memory of the system in bytes per thousand bytes is between this and
+the low watermark, DAMON_LRU_SORT becomes active, so starts the monitoring and
+the LRU-lists sorting.  150 (15%) by default.
+
+wmarks_low
+----------
+
+Free memory rate (per thousand) for the low watermark.
+
+If free memory of the system in bytes per thousand bytes is lower than this,
+DAMON_LRU_SORT becomes inactive, so it does nothing but periodically checks the
+watermarks.  50 (5%) by default.
+
+sample_interval
+---------------
+
+Sampling interval for the monitoring in microseconds.
+
+The sampling interval of DAMON for the cold memory monitoring.  Please refer to
+the DAMON documentation (:doc:`usage`) for more detail.  5ms by default.
+
+aggr_interval
+-------------
+
+Aggregation interval for the monitoring in microseconds.
+
+The aggregation interval of DAMON for the cold memory monitoring.  Please
+refer to the DAMON documentation (:doc:`usage`) for more detail.  100ms by
+default.
+
+min_nr_regions
+--------------
+
+Minimum number of monitoring regions.
+
+The minimal number of monitoring regions of DAMON for the cold memory
+monitoring.  This can be used to set lower-bound of the monitoring quality.
+But, setting this too high could result in increased monitoring overhead.
+Please refer to the DAMON documentation (:doc:`usage`) for more detail.  10 by
+default.
+
+max_nr_regions
+--------------
+
+Maximum number of monitoring regions.
+
+The maximum number of monitoring regions of DAMON for the cold memory
+monitoring.  This can be used to set upper-bound of the monitoring overhead.
+However, setting this too low could result in bad monitoring quality.  Please
+refer to the DAMON documentation (:doc:`usage`) for more detail.  1000 by
+defaults.
+
+monitor_region_start
+--------------------
+
+Start of target memory region in physical address.
+
+The start physical address of memory region that DAMON_LRU_SORT will do work
+against.  By default, biggest System RAM is used as the region.
+
+monitor_region_end
+------------------
+
+End of target memory region in physical address.
+
+The end physical address of memory region that DAMON_LRU_SORT will do work
+against.  By default, biggest System RAM is used as the region.
+
+kdamond_pid
+-----------
+
+PID of the DAMON thread.
+
+If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread.  Else,
+-1.
+
+nr_lru_sort_tried_hot_regions
+-----------------------------
+
+Number of hot memory regions that tried to be LRU-sorted.
+
+bytes_lru_sort_tried_hot_regions
+--------------------------------
+
+Total bytes of hot memory regions that tried to be LRU-sorted.
+
+nr_lru_sorted_hot_regions
+-------------------------
+
+Number of hot memory regions that successfully be LRU-sorted.
+
+bytes_lru_sorted_hot_regions
+----------------------------
+
+Total bytes of hot memory regions that successfully be LRU-sorted.
+
+nr_hot_quota_exceeds
+--------------------
+
+Number of times that the time quota limit for hot regions have exceeded.
+
+nr_lru_sort_tried_cold_regions
+------------------------------
+
+Number of cold memory regions that tried to be LRU-sorted.
+
+bytes_lru_sort_tried_cold_regions
+---------------------------------
+
+Total bytes of cold memory regions that tried to be LRU-sorted.
+
+nr_lru_sorted_cold_regions
+--------------------------
+
+Number of cold memory regions that successfully be LRU-sorted.
+
+bytes_lru_sorted_cold_regions
+-----------------------------
+
+Total bytes of cold memory regions that successfully be LRU-sorted.
+
+nr_cold_quota_exceeds
+---------------------
+
+Number of times that the time quota limit for cold regions have exceeded.
+
+Example
+=======
+
+Below runtime example commands make DAMON_LRU_SORT to find memory regions
+having >=50% access frequency and LRU-prioritize while LRU-deprioritizing
+memory regions that not accessed for 120 seconds.  The prioritization and
+deprioritization is limited to be done using only up to 1% CPU time to avoid
+DAMON_LRU_SORT consuming too much CPU time for the (de)prioritization.  It also
+asks DAMON_LRU_SORT to do nothing if the system's free memory rate is more than
+50%, but start the real works if it becomes lower than 40%.  If DAMON_RECLAIM
+doesn't make progress and therefore the free memory rate becomes lower than
+20%, it asks DAMON_LRU_SORT to do nothing again, so that we can fall back to
+the LRU-list based page granularity reclamation. ::
+
+    # cd /sys/modules/damon_lru_sort/parameters
+    # echo 500 > hot_thres_access_freq
+    # echo 120000000 > cold_min_age
+    # echo 10 > quota_ms
+    # echo 1000 > quota_reset_interval_ms
+    # echo 500 > wmarks_high
+    # echo 400 > wmarks_mid
+    # echo 200 > wmarks_low
+    # echo Y > enabled
diff --git a/Documentation/admin-guide/mm/damon/reclaim.rst b/Documentation/admin-guide/mm/damon/reclaim.rst
index 46306f1f34b1..6510baa91109 100644
--- a/Documentation/admin-guide/mm/damon/reclaim.rst
+++ b/Documentation/admin-guide/mm/damon/reclaim.rst
@@ -48,12 +48,6 @@ DAMON_RECLAIM utilizes module parameters.  That is, you can put
 ``damon_reclaim.<parameter>=<value>`` on the kernel boot command line or write
 proper values to ``/sys/modules/damon_reclaim/parameters/<parameter>`` files.
 
-Note that the parameter values except ``enabled`` are applied only when
-DAMON_RECLAIM starts.  Therefore, if you want to apply new parameter values in
-runtime and DAMON_RECLAIM is already enabled, you should disable and re-enable
-it via ``enabled`` parameter file.  Writing of the new values to proper
-parameter values should be done before the re-enablement.
-
 Below are the description of each parameter.
 
 enabled
diff --git a/Documentation/admin-guide/mm/damon/usage.rst b/Documentation/admin-guide/mm/damon/usage.rst
index 1bb7b72414b2..d822bf6355ce 100644
--- a/Documentation/admin-guide/mm/damon/usage.rst
+++ b/Documentation/admin-guide/mm/damon/usage.rst
@@ -264,6 +264,8 @@ that can be written to and read from the file and their meaning are as below.
  - ``pageout``: Call ``madvise()`` for the region with ``MADV_PAGEOUT``
  - ``hugepage``: Call ``madvise()`` for the region with ``MADV_HUGEPAGE``
  - ``nohugepage``: Call ``madvise()`` for the region with ``MADV_NOHUGEPAGE``
+ - ``lru_prio``: Prioritize the region on its LRU lists.
+ - ``lru_deprio``: Deprioritize the region on its LRU lists.
  - ``stat``: Do nothing but count the statistics
 
 schemes/<N>/access_pattern/
diff --git a/Documentation/admin-guide/mm/index.rst b/Documentation/admin-guide/mm/index.rst
index c21b5823f126..1bd11118dfb1 100644
--- a/Documentation/admin-guide/mm/index.rst
+++ b/Documentation/admin-guide/mm/index.rst
@@ -36,6 +36,7 @@ the Linux memory management.
    numa_memory_policy
    numaperf
    pagemap
+   shrinker_debugfs
    soft-dirty
    swap_numa
    transhuge
diff --git a/Documentation/admin-guide/mm/shrinker_debugfs.rst b/Documentation/admin-guide/mm/shrinker_debugfs.rst
new file mode 100644
index 000000000000..3887f0b294fe
--- /dev/null
+++ b/Documentation/admin-guide/mm/shrinker_debugfs.rst
@@ -0,0 +1,135 @@
+.. _shrinker_debugfs:
+
+==========================
+Shrinker Debugfs Interface
+==========================
+
+Shrinker debugfs interface provides a visibility into the kernel memory
+shrinkers subsystem and allows to get information about individual shrinkers
+and interact with them.
+
+For each shrinker registered in the system a directory in **<debugfs>/shrinker/**
+is created. The directory's name is composed from the shrinker's name and an
+unique id: e.g. *kfree_rcu-0* or *sb-xfs:vda1-36*.
+
+Each shrinker directory contains **count** and **scan** files, which allow to
+trigger *count_objects()* and *scan_objects()* callbacks for each memcg and
+numa node (if applicable).
+
+Usage:
+------
+
+1. *List registered shrinkers*
+
+  ::
+
+    $ cd /sys/kernel/debug/shrinker/
+    $ ls
+    dquota-cache-16     sb-devpts-28     sb-proc-47       sb-tmpfs-42
+    mm-shadow-18        sb-devtmpfs-5    sb-proc-48       sb-tmpfs-43
+    mm-zspool:zram0-34  sb-hugetlbfs-17  sb-pstore-31     sb-tmpfs-44
+    rcu-kfree-0         sb-hugetlbfs-33  sb-rootfs-2      sb-tmpfs-49
+    sb-aio-20           sb-iomem-12      sb-securityfs-6  sb-tracefs-13
+    sb-anon_inodefs-15  sb-mqueue-21     sb-selinuxfs-22  sb-xfs:vda1-36
+    sb-bdev-3           sb-nsfs-4        sb-sockfs-8      sb-zsmalloc-19
+    sb-bpf-32           sb-pipefs-14     sb-sysfs-26      thp-deferred_split-10
+    sb-btrfs:vda2-24    sb-proc-25       sb-tmpfs-1       thp-zero-9
+    sb-cgroup2-30       sb-proc-39       sb-tmpfs-27      xfs-buf:vda1-37
+    sb-configfs-23      sb-proc-41       sb-tmpfs-29      xfs-inodegc:vda1-38
+    sb-dax-11           sb-proc-45       sb-tmpfs-35
+    sb-debugfs-7        sb-proc-46       sb-tmpfs-40
+
+2. *Get information about a specific shrinker*
+
+  ::
+
+    $ cd sb-btrfs\:vda2-24/
+    $ ls
+    count            scan
+
+3. *Count objects*
+
+  Each line in the output has the following format::
+
+    <cgroup inode id> <nr of objects on node 0> <nr of objects on node 1> ...
+    <cgroup inode id> <nr of objects on node 0> <nr of objects on node 1> ...
+    ...
+
+  If there are no objects on all numa nodes, a line is omitted. If there
+  are no objects at all, the output might be empty.
+
+  If the shrinker is not memcg-aware or CONFIG_MEMCG is off, 0 is printed
+  as cgroup inode id. If the shrinker is not numa-aware, 0's are printed
+  for all nodes except the first one.
+  ::
+
+    $ cat count
+    1 224 2
+    21 98 0
+    55 818 10
+    2367 2 0
+    2401 30 0
+    225 13 0
+    599 35 0
+    939 124 0
+    1041 3 0
+    1075 1 0
+    1109 1 0
+    1279 60 0
+    1313 7 0
+    1347 39 0
+    1381 3 0
+    1449 14 0
+    1483 63 0
+    1517 53 0
+    1551 6 0
+    1585 1 0
+    1619 6 0
+    1653 40 0
+    1687 11 0
+    1721 8 0
+    1755 4 0
+    1789 52 0
+    1823 888 0
+    1857 1 0
+    1925 2 0
+    1959 32 0
+    2027 22 0
+    2061 9 0
+    2469 799 0
+    2537 861 0
+    2639 1 0
+    2707 70 0
+    2775 4 0
+    2877 84 0
+    293 1 0
+    735 8 0
+
+4. *Scan objects*
+
+  The expected input format::
+
+    <cgroup inode id> <numa id> <number of objects to scan>
+
+  For a non-memcg-aware shrinker or on a system with no memory
+  cgrups **0** should be passed as cgroup id.
+  ::
+
+    $ cd /sys/kernel/debug/shrinker/
+    $ cd sb-btrfs\:vda2-24/
+
+    $ cat count | head -n 5
+    1 212 0
+    21 97 0
+    55 802 5
+    2367 2 0
+    225 13 0
+
+    $ echo "55 0 200" > scan
+
+    $ cat count | head -n 5
+    1 212 0
+    21 96 0
+    55 752 5
+    2367 2 0
+    225 13 0
diff --git a/Documentation/admin-guide/mm/userfaultfd.rst b/Documentation/admin-guide/mm/userfaultfd.rst
index 6528036093e1..9bae1acd431f 100644
--- a/Documentation/admin-guide/mm/userfaultfd.rst
+++ b/Documentation/admin-guide/mm/userfaultfd.rst
@@ -17,7 +17,10 @@ of the ``PROT_NONE+SIGSEGV`` trick.
 Design
 ======
 
-Userfaults are delivered and resolved through the ``userfaultfd`` syscall.
+Userspace creates a new userfaultfd, initializes it, and registers one or more
+regions of virtual memory with it. Then, any page faults which occur within the
+region(s) result in a message being delivered to the userfaultfd, notifying
+userspace of the fault.
 
 The ``userfaultfd`` (aside from registering and unregistering virtual
 memory ranges) provides two primary functionalities:
@@ -34,12 +37,11 @@ The real advantage of userfaults if compared to regular virtual memory
 management of mremap/mprotect is that the userfaults in all their
 operations never involve heavyweight structures like vmas (in fact the
 ``userfaultfd`` runtime load never takes the mmap_lock for writing).
-
 Vmas are not suitable for page- (or hugepage) granular fault tracking
 when dealing with virtual address spaces that could span
 Terabytes. Too many vmas would be needed for that.
 
-The ``userfaultfd`` once opened by invoking the syscall, can also be
+The ``userfaultfd``, once created, can also be
 passed using unix domain sockets to a manager process, so the same
 manager process could handle the userfaults of a multitude of
 different processes without them being aware about what is going on
@@ -50,6 +52,38 @@ is a corner case that would currently return ``-EBUSY``).
 API
 ===
 
+Creating a userfaultfd
+----------------------
+
+There are two ways to create a new userfaultfd, each of which provide ways to
+restrict access to this functionality (since historically userfaultfds which
+handle kernel page faults have been a useful tool for exploiting the kernel).
+
+The first way, supported by older kernels, is the userfaultfd(2) syscall.
+Access to this is controlled in several ways:
+
+- By default, the userfaultfd will be able to handle kernel page faults. This
+  can be disabled by passing in UFFD_USER_MODE_ONLY.
+
+- If vm.unprivileged_userfaultfd is 0, then the caller must *either* have
+  CAP_SYS_PTRACE, or pass in UFFD_USER_MODE_ONLY.
+
+- If vm.unprivileged_userfaultfd is 1, then no particular privilege is needed to
+  use this syscall, even if UFFD_USER_MODE_ONLY is *not* set.
+
+The second way, added to the kernel more recently, is by opening and issuing a
+USERFAULTFD_IOC_NEW ioctl to /dev/userfaultfd. This method yields equivalent
+userfaultfds to the userfaultfd(2) syscall; its benefit is in how access to
+creating userfaultfds is controlled.
+
+Access to /dev/userfaultfd is controlled via normal filesystem permissions
+(user/group/mode for example), which gives fine grained access to userfaultfd
+specifically, without also granting other unrelated privileges at the same time
+(as e.g. granting CAP_SYS_PTRACE would do).
+
+Initializing up a userfaultfd
+-----------------------------
+
 When first opened the ``userfaultfd`` must be enabled invoking the
 ``UFFDIO_API`` ioctl specifying a ``uffdio_api.api`` value set to ``UFFD_API`` (or
 a later API version) which will specify the ``read/POLLIN`` protocol
diff --git a/Documentation/admin-guide/pm/cpuidle.rst b/Documentation/admin-guide/pm/cpuidle.rst
index aec2cd2aaea7..19754beb5a4e 100644
--- a/Documentation/admin-guide/pm/cpuidle.rst
+++ b/Documentation/admin-guide/pm/cpuidle.rst
@@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that use the ``ladder`` governor
 by default this way, for example.
 
 The other kernel command line parameters controlling CPU idle time management
-described below are only relevant for the *x86* architecture and some of
-them affect Intel processors only.
+described below are only relevant for the *x86* architecture and references
+to ``intel_idle`` affect Intel processors only.
 
 The *x86* architecture support code recognizes three kernel command line
 options related to CPU idle time management: ``idle=poll``, ``idle=halt``,
@@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computations performance as well as
 energy-efficiency.  Thus using it for performance reasons may not be a good idea
 at all.]
 
-The ``idle=nomwait`` option disables the ``intel_idle`` driver and causes
-``acpi_idle`` to be used (as long as all of the information needed by it is
-there in the system's ACPI tables), but it is not allowed to use the
-``MWAIT`` instruction of the CPUs to ask the hardware to enter idle states.
+The ``idle=nomwait`` option prevents the use of ``MWAIT`` instruction of
+the CPU to enter idle states. When this option is used, the ``acpi_idle``
+driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems
+running Intel processors, this option disables the ``intel_idle`` driver
+and forces the use of the ``acpi_idle`` driver instead. Note that in either
+case, ``acpi_idle`` driver will function only if all the information needed
+by it is in the system's ACPI tables.
 
 In addition to the architecture-level kernel command line options affecting CPU
 idle time management, there are parameters affecting individual ``CPUIdle``
diff --git a/Documentation/admin-guide/sysctl/vm.rst b/Documentation/admin-guide/sysctl/vm.rst
index 5c9aa171a0d3..e3a952d1fd35 100644
--- a/Documentation/admin-guide/sysctl/vm.rst
+++ b/Documentation/admin-guide/sysctl/vm.rst
@@ -565,9 +565,8 @@ See Documentation/admin-guide/mm/hugetlbpage.rst
 hugetlb_optimize_vmemmap
 ========================
 
-This knob is not available when memory_hotplug.memmap_on_memory (kernel parameter)
-is configured or the size of 'struct page' (a structure defined in
-include/linux/mm_types.h) is not power of two (an unusual system config could
+This knob is not available when the size of 'struct page' (a structure defined
+in include/linux/mm_types.h) is not power of two (an unusual system config could
 result in this).
 
 Enable (set to 1) or disable (set to 0) the feature of optimizing vmemmap pages
@@ -928,6 +927,9 @@ calls without any restrictions.
 
 The default value is 0.
 
+An alternative to this sysctl / the userfaultfd(2) syscall is to create
+userfaultfds via /dev/userfaultfd. See
+Documentation/admin-guide/mm/userfaultfd.rst.
 
 user_reserve_kbytes
 ===================
diff --git a/Documentation/arm/samsung-s3c24xx/cpufreq.rst b/Documentation/arm/samsung-s3c24xx/cpufreq.rst
index 2ddc26c03b1f..ed19ce1a4629 100644
--- a/Documentation/arm/samsung-s3c24xx/cpufreq.rst
+++ b/Documentation/arm/samsung-s3c24xx/cpufreq.rst
@@ -1,3 +1,4 @@
+.. SPDX-License-Identifier: GPL-2.0-only
 =======================
 S3C24XX CPUfreq support
 =======================
@@ -73,4 +74,3 @@ Document Author
 ---------------
 
 Ben Dooks, Copyright 2009 Simtec Electronics
-Licensed under GPLv2
diff --git a/Documentation/bpf/btf.rst b/Documentation/bpf/btf.rst
index 7940da9bc6c1..f49aeef62d0c 100644
--- a/Documentation/bpf/btf.rst
+++ b/Documentation/bpf/btf.rst
@@ -74,7 +74,7 @@ sequentially and type id is assigned to each recognized type starting from id
     #define BTF_KIND_ARRAY          3       /* Array        */
     #define BTF_KIND_STRUCT         4       /* Struct       */
     #define BTF_KIND_UNION          5       /* Union        */
-    #define BTF_KIND_ENUM           6       /* Enumeration  */
+    #define BTF_KIND_ENUM           6       /* Enumeration up to 32-bit values */
     #define BTF_KIND_FWD            7       /* Forward      */
     #define BTF_KIND_TYPEDEF        8       /* Typedef      */
     #define BTF_KIND_VOLATILE       9       /* Volatile     */
@@ -87,6 +87,7 @@ sequentially and type id is assigned to each recognized type starting from id
     #define BTF_KIND_FLOAT          16      /* Floating point       */
     #define BTF_KIND_DECL_TAG       17      /* Decl Tag     */
     #define BTF_KIND_TYPE_TAG       18      /* Type Tag     */
+    #define BTF_KIND_ENUM64         19      /* Enumeration up to 64-bit values */
 
 Note that the type section encodes debug info, not just pure types.
 ``BTF_KIND_FUNC`` is not a type, and it represents a defined subprogram.
@@ -101,10 +102,10 @@ Each type contains the following common data::
          * bits 24-28: kind (e.g. int, ptr, array...etc)
          * bits 29-30: unused
          * bit     31: kind_flag, currently used by
-         *             struct, union and fwd
+         *             struct, union, fwd, enum and enum64.
          */
         __u32 info;
-        /* "size" is used by INT, ENUM, STRUCT and UNION.
+        /* "size" is used by INT, ENUM, STRUCT, UNION and ENUM64.
          * "size" tells the size of the type it is describing.
          *
          * "type" is used by PTR, TYPEDEF, VOLATILE, CONST, RESTRICT,
@@ -281,10 +282,10 @@ modes exist:
 
 ``struct btf_type`` encoding requirement:
   * ``name_off``: 0 or offset to a valid C identifier
-  * ``info.kind_flag``: 0
+  * ``info.kind_flag``: 0 for unsigned, 1 for signed
   * ``info.kind``: BTF_KIND_ENUM
   * ``info.vlen``: number of enum values
-  * ``size``: 4
+  * ``size``: 1/2/4/8
 
 ``btf_type`` is followed by ``info.vlen`` number of ``struct btf_enum``.::
 
@@ -297,6 +298,10 @@ The ``btf_enum`` encoding:
   * ``name_off``: offset to a valid C identifier
   * ``val``: any value
 
+If the original enum value is signed and the size is less than 4,
+that value will be sign extended into 4 bytes. If the size is 8,
+the value will be truncated into 4 bytes.
+
 2.2.7 BTF_KIND_FWD
 ~~~~~~~~~~~~~~~~~~
 
@@ -493,7 +498,7 @@ the attribute is applied to a ``struct``/``union`` member or
 a ``func`` argument, and ``btf_decl_tag.component_idx`` should be a
 valid index (starting from 0) pointing to a member or an argument.
 
-2.2.17 BTF_KIND_TYPE_TAG
+2.2.18 BTF_KIND_TYPE_TAG
 ~~~~~~~~~~~~~~~~~~~~~~~~
 
 ``struct btf_type`` encoding requirement:
@@ -516,6 +521,32 @@ type_tag, then zero or more const/volatile/restrict/typedef
 and finally the base type. The base type is one of
 int, ptr, array, struct, union, enum, func_proto and float types.
 
+2.2.19 BTF_KIND_ENUM64
+~~~~~~~~~~~~~~~~~~~~~~
+
+``struct btf_type`` encoding requirement:
+  * ``name_off``: 0 or offset to a valid C identifier
+  * ``info.kind_flag``: 0 for unsigned, 1 for signed
+  * ``info.kind``: BTF_KIND_ENUM64
+  * ``info.vlen``: number of enum values
+  * ``size``: 1/2/4/8
+
+``btf_type`` is followed by ``info.vlen`` number of ``struct btf_enum64``.::
+
+    struct btf_enum64 {
+        __u32   name_off;
+        __u32   val_lo32;
+        __u32   val_hi32;
+    };
+
+The ``btf_enum64`` encoding:
+  * ``name_off``: offset to a valid C identifier
+  * ``val_lo32``: lower 32-bit value for a 64-bit value
+  * ``val_hi32``: high 32-bit value for a 64-bit value
+
+If the original enum value is signed and the size is less than 8,
+that value will be sign extended into 8 bytes.
+
 3. BTF Kernel API
 =================
 
diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst
index 1de6a57c7e1e..9e27fbdb2206 100644
--- a/Documentation/bpf/instruction-set.rst
+++ b/Documentation/bpf/instruction-set.rst
@@ -127,7 +127,7 @@ BPF_XOR | BPF_K | BPF_ALU64 means::
 Byte swap instructions
 ----------------------
 
-The byte swap instructions use an instruction class of ``BFP_ALU`` and a 4-bit
+The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit
 code field of ``BPF_END``.
 
 The byte swap instructions operate on the destination register
diff --git a/Documentation/core-api/index.rst b/Documentation/core-api/index.rst
index dedd4d853329..9ef37e985a40 100644
--- a/Documentation/core-api/index.rst
+++ b/Documentation/core-api/index.rst
@@ -36,6 +36,7 @@ Library functionality that is used throughout the kernel.
    kref
    assoc_array
    xarray
+   maple_tree
    idr
    circular-buffers
    rbtree
diff --git a/Documentation/core-api/maple_tree.rst b/Documentation/core-api/maple_tree.rst
new file mode 100644
index 000000000000..45defcf15da7
--- /dev/null
+++ b/Documentation/core-api/maple_tree.rst
@@ -0,0 +1,217 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+
+==========
+Maple Tree
+==========
+
+:Author: Liam R. Howlett
+
+Overview
+========
+
+The Maple Tree is a B-Tree data type which is optimized for storing
+non-overlapping ranges, including ranges of size 1.  The tree was designed to
+be simple to use and does not require a user written search method.  It
+supports iterating over a range of entries and going to the previous or next
+entry in a cache-efficient manner.  The tree can also be put into an RCU-safe
+mode of operation which allows reading and writing concurrently.  Writers must
+synchronize on a lock, which can be the default spinlock, or the user can set
+the lock to an external lock of a different type.
+
+The Maple Tree maintains a small memory footprint and was designed to use
+modern processor cache efficiently.  The majority of the users will be able to
+use the normal API.  An :ref:`maple-tree-advanced-api` exists for more complex
+scenarios.  The most important usage of the Maple Tree is the tracking of the
+virtual memory areas.
+
+The Maple Tree can store values between ``0`` and ``ULONG_MAX``.  The Maple
+Tree reserves values with the bottom two bits set to '10' which are below 4096
+(ie 2, 6, 10 .. 4094) for internal use.  If the entries may use reserved
+entries then the users can convert the entries using xa_mk_value() and convert
+them back by calling xa_to_value().  If the user needs to use a reserved
+value, then the user can convert the value when using the
+:ref:`maple-tree-advanced-api`, but are blocked by the normal API.
+
+The Maple Tree can also be configured to support searching for a gap of a given
+size (or larger).
+
+Pre-allocating of nodes is also supported using the
+:ref:`maple-tree-advanced-api`.  This is useful for users who must guarantee a
+successful store operation within a given
+code segment when allocating cannot be done.  Allocations of nodes are
+relatively small at around 256 bytes.
+
+.. _maple-tree-normal-api:
+
+Normal API
+==========
+
+Start by initialising a maple tree, either with DEFINE_MTREE() for statically
+allocated maple trees or mt_init() for dynamically allocated ones.  A
+freshly-initialised maple tree contains a ``NULL`` pointer for the range ``0``
+- ``ULONG_MAX``.  There are currently two types of maple trees supported: the
+allocation tree and the regular tree.  The regular tree has a higher branching
+factor for internal nodes.  The allocation tree has a lower branching factor
+but allows the user to search for a gap of a given size or larger from either
+``0`` upwards or ``ULONG_MAX`` down.  An allocation tree can be used by
+passing in the ``MT_FLAGS_ALLOC_RANGE`` flag when initialising the tree.
+
+You can then set entries using mtree_store() or mtree_store_range().
+mtree_store() will overwrite any entry with the new entry and return 0 on
+success or an error code otherwise.  mtree_store_range() works in the same way
+but takes a range.  mtree_load() is used to retrieve the entry stored at a
+given index.  You can use mtree_erase() to erase an entire range by only
+knowing one value within that range, or mtree_store() call with an entry of
+NULL may be used to partially erase a range or many ranges at once.
+
+If you want to only store a new entry to a range (or index) if that range is
+currently ``NULL``, you can use mtree_insert_range() or mtree_insert() which
+return -EEXIST if the range is not empty.
+
+You can search for an entry from an index upwards by using mt_find().
+
+You can walk each entry within a range by calling mt_for_each().  You must
+provide a temporary variable to store a cursor.  If you want to walk each
+element of the tree then ``0`` and ``ULONG_MAX`` may be used as the range.  If
+the caller is going to hold the lock for the duration of the walk then it is
+worth looking at the mas_for_each() API in the :ref:`maple-tree-advanced-api`
+section.
+
+Sometimes it is necessary to ensure the next call to store to a maple tree does
+not allocate memory, please see :ref:`maple-tree-advanced-api` for this use case.
+
+Finally, you can remove all entries from a maple tree by calling
+mtree_destroy().  If the maple tree entries are pointers, you may wish to free
+the entries first.
+
+Allocating Nodes
+----------------
+
+The allocations are handled by the internal tree code.  See
+:ref:`maple-tree-advanced-alloc` for other options.
+
+Locking
+-------
+
+You do not have to worry about locking.  See :ref:`maple-tree-advanced-locks`
+for other options.
+
+The Maple Tree uses RCU and an internal spinlock to synchronise access:
+
+Takes RCU read lock:
+ * mtree_load()
+ * mt_find()
+ * mt_for_each()
+ * mt_next()
+ * mt_prev()
+
+Takes ma_lock internally:
+ * mtree_store()
+ * mtree_store_range()
+ * mtree_insert()
+ * mtree_insert_range()
+ * mtree_erase()
+ * mtree_destroy()
+ * mt_set_in_rcu()
+ * mt_clear_in_rcu()
+
+If you want to take advantage of the internal lock to protect the data
+structures that you are storing in the Maple Tree, you can call mtree_lock()
+before calling mtree_load(), then take a reference count on the object you
+have found before calling mtree_unlock().  This will prevent stores from
+removing the object from the tree between looking up the object and
+incrementing the refcount.  You can also use RCU to avoid dereferencing
+freed memory, but an explanation of that is beyond the scope of this
+document.
+
+.. _maple-tree-advanced-api:
+
+Advanced API
+============
+
+The advanced API offers more flexibility and better performance at the
+cost of an interface which can be harder to use and has fewer safeguards.
+You must take care of your own locking while using the advanced API.
+You can use the ma_lock, RCU or an external lock for protection.
+You can mix advanced and normal operations on the same array, as long
+as the locking is compatible.  The :ref:`maple-tree-normal-api` is implemented
+in terms of the advanced API.
+
+The advanced API is based around the ma_state, this is where the 'mas'
+prefix originates.  The ma_state struct keeps track of tree operations to make
+life easier for both internal and external tree users.
+
+Initialising the maple tree is the same as in the :ref:`maple-tree-normal-api`.
+Please see above.
+
+The maple state keeps track of the range start and end in mas->index and
+mas->last, respectively.
+
+mas_walk() will walk the tree to the location of mas->index and set the
+mas->index and mas->last according to the range for the entry.
+
+You can set entries using mas_store().  mas_store() will overwrite any entry
+with the new entry and return the first existing entry that is overwritten.
+The range is passed in as members of the maple state: index and last.
+
+You can use mas_erase() to erase an entire range by setting index and
+last of the maple state to the desired range to erase.  This will erase
+the first range that is found in that range, set the maple state index
+and last as the range that was erased and return the entry that existed
+at that location.
+
+You can walk each entry within a range by using mas_for_each().  If you want
+to walk each element of the tree then ``0`` and ``ULONG_MAX`` may be used as
+the range.  If the lock needs to be periodically dropped, see the locking
+section mas_pause().
+
+Using a maple state allows mas_next() and mas_prev() to function as if the
+tree was a linked list.  With such a high branching factor the amortized
+performance penalty is outweighed by cache optimization.  mas_next() will
+return the next entry which occurs after the entry at index.  mas_prev()
+will return the previous entry which occurs before the entry at index.
+
+mas_find() will find the first entry which exists at or above index on
+the first call, and the next entry from every subsequent calls.
+
+mas_find_rev() will find the fist entry which exists at or below the last on
+the first call, and the previous entry from every subsequent calls.
+
+If the user needs to yield the lock during an operation, then the maple state
+must be paused using mas_pause().
+
+There are a few extra interfaces provided when using an allocation tree.
+If you wish to search for a gap within a range, then mas_empty_area()
+or mas_empty_area_rev() can be used.  mas_empty_area() searches for a gap
+starting at the lowest index given up to the maximum of the range.
+mas_empty_area_rev() searches for a gap starting at the highest index given
+and continues downward to the lower bound of the range.
+
+.. _maple-tree-advanced-alloc:
+
+Advanced Allocating Nodes
+-------------------------
+
+Allocations are usually handled internally to the tree, however if allocations
+need to occur before a write occurs then calling mas_expected_entries() will
+allocate the worst-case number of needed nodes to insert the provided number of
+ranges.  This also causes the tree to enter mass insertion mode.  Once
+insertions are complete calling mas_destroy() on the maple state will free the
+unused allocations.
+
+.. _maple-tree-advanced-locks:
+
+Advanced Locking
+----------------
+
+The maple tree uses a spinlock by default, but external locks can be used for
+tree updates as well.  To use an external lock, the tree must be initialized
+with the ``MT_FLAGS_LOCK_EXTERN flag``, this is usually done with the
+MTREE_INIT_EXT() #define, which takes an external lock as an argument.
+
+Functions and structures
+========================
+
+.. kernel-doc:: include/linux/maple_tree.h
+.. kernel-doc:: lib/maple_tree.c
diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst
index 5e89497ba314..dbe1aacc79d0 100644
--- a/Documentation/core-api/printk-formats.rst
+++ b/Documentation/core-api/printk-formats.rst
@@ -625,6 +625,16 @@ Examples::
 	%p4cc	Y10  little-endian (0x20303159)
 	%p4cc	NV12 big-endian (0xb231564e)
 
+Rust
+----
+
+::
+
+	%pA
+
+Only intended to be used from Rust code to format ``core::fmt::Arguments``.
+Do *not* use it from C.
+
 Thanks
 ======
 
diff --git a/Documentation/core-api/protection-keys.rst b/Documentation/core-api/protection-keys.rst
index ec575e72d0b2..bf28ac0401f3 100644
--- a/Documentation/core-api/protection-keys.rst
+++ b/Documentation/core-api/protection-keys.rst
@@ -4,31 +4,29 @@
 Memory Protection Keys
 ======================
 
-Memory Protection Keys for Userspace (PKU aka PKEYs) is a feature
-which is found on Intel's Skylake (and later) "Scalable Processor"
-Server CPUs. It will be available in future non-server Intel parts
-and future AMD processors.
-
-For anyone wishing to test or use this feature, it is available in
-Amazon's EC2 C5 instances and is known to work there using an Ubuntu
-17.04 image.
-
-Memory Protection Keys provides a mechanism for enforcing page-based
-protections, but without requiring modification of the page tables
-when an application changes protection domains.  It works by
-dedicating 4 previously ignored bits in each page table entry to a
-"protection key", giving 16 possible keys.
-
-There is also a new user-accessible register (PKRU) with two separate
-bits (Access Disable and Write Disable) for each key.  Being a CPU
-register, PKRU is inherently thread-local, potentially giving each
+Memory Protection Keys provide a mechanism for enforcing page-based
+protections, but without requiring modification of the page tables when an
+application changes protection domains.
+
+Pkeys Userspace (PKU) is a feature which can be found on:
+        * Intel server CPUs, Skylake and later
+        * Intel client CPUs, Tiger Lake (11th Gen Core) and later
+        * Future AMD CPUs
+
+Pkeys work by dedicating 4 previously Reserved bits in each page table entry to
+a "protection key", giving 16 possible keys.
+
+Protections for each key are defined with a per-CPU user-accessible register
+(PKRU).  Each of these is a 32-bit register storing two bits (Access Disable
+and Write Disable) for each of 16 keys.
+
+Being a CPU register, PKRU is inherently thread-local, potentially giving each
 thread a different set of protections from every other thread.
 
-There are two new instructions (RDPKRU/WRPKRU) for reading and writing
-to the new register.  The feature is only available in 64-bit mode,
-even though there is theoretically space in the PAE PTEs.  These
-permissions are enforced on data access only and have no effect on
-instruction fetches.
+There are two instructions (RDPKRU/WRPKRU) for reading and writing to the
+register.  The feature is only available in 64-bit mode, even though there is
+theoretically space in the PAE PTEs.  These permissions are enforced on data
+access only and have no effect on instruction fetches.
 
 Syscalls
 ========
diff --git a/Documentation/dev-tools/kmemleak.rst b/Documentation/dev-tools/kmemleak.rst
index 1c935f41cd3a..5483fd39ef29 100644
--- a/Documentation/dev-tools/kmemleak.rst
+++ b/Documentation/dev-tools/kmemleak.rst
@@ -174,7 +174,6 @@ mapping:
 
 - ``kmemleak_alloc_phys``
 - ``kmemleak_free_part_phys``
-- ``kmemleak_not_leak_phys``
 - ``kmemleak_ignore_phys``
 
 Dealing with false positives/negatives
diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
new file mode 100644
index 000000000000..d61408194998
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SoC based boards
+
+maintainers:
+  - Joel Stanley <joel@jms.id.au>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: AST2400 based boards
+        items:
+          - enum:
+              - facebook,galaxy100-bmc
+              - facebook,wedge100-bmc
+              - facebook,wedge40-bmc
+              - microsoft,olympus-bmc
+              - quanta,q71l-bmc
+              - tyan,palmetto-bmc
+              - yadro,vesnin-bmc
+          - const: aspeed,ast2400
+
+      - description: AST2500 based boards
+        items:
+          - enum:
+              - aspeed,ast2500-evb
+              - amd,ethanolx-bmc
+              - ampere,mtjade-bmc
+              - asrock,e3c246d4i-bmc
+              - asrock,romed8hm3-bmc
+              - bytedance,g220a-bmc
+              - facebook,cmm-bmc
+              - facebook,minipack-bmc
+              - facebook,tiogapass-bmc
+              - facebook,yamp-bmc
+              - facebook,yosemitev2-bmc
+              - facebook,wedge400-bmc
+              - hxt,stardragon4800-rep2-bmc
+              - ibm,mihawk-bmc
+              - ibm,mowgli-bmc
+              - ibm,romulus-bmc
+              - ibm,swift-bmc
+              - ibm,witherspoon-bmc
+              - ingrasys,zaius-bmc
+              - inspur,fp5280g2-bmc
+              - inspur,nf5280m6-bmc
+              - inspur,on5263m5-bmc
+              - intel,s2600wf-bmc
+              - inventec,lanyang-bmc
+              - lenovo,hr630-bmc
+              - lenovo,hr855xg2-bmc
+              - portwell,neptune-bmc
+              - qcom,centriq2400-rep-bmc
+              - supermicro,x11spi-bmc
+              - tyan,s7106-bmc
+              - tyan,s8036-bmc
+              - yadro,nicole-bmc
+              - yadro,vegman-n110-bmc
+              - yadro,vegman-rx20-bmc
+              - yadro,vegman-sx20-bmc
+          - const: aspeed,ast2500
+
+      - description: AST2600 based boards
+        items:
+          - enum:
+              - aspeed,ast2600-evb
+              - aspeed,ast2600-evb-a1
+              - facebook,bletchley-bmc
+              - facebook,cloudripper-bmc
+              - facebook,elbert-bmc
+              - facebook,fuji-bmc
+              - ibm,everest-bmc
+              - ibm,rainier-bmc
+              - ibm,tacoma-bmc
+              - inventec,transformer-bmc
+              - jabil,rbp-bmc
+              - nuvia,dc-scm-bmc
+              - quanta,s6q-bmc
+          - const: aspeed,ast2600
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
index 8b7e87fb6c34..958df32b4899 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
@@ -87,6 +87,13 @@ properties:
           - const: brcm,bcm53012
           - const: brcm,bcm4708
 
+      - description: BCM53015 based boards
+        items:
+          - enum:
+              - meraki,mr26
+          - const: brcm,bcm53015
+          - const: brcm,bcm4708
+
       - description: BCM53016 based boards
         items:
           - enum:
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
index 5fb455840417..b817051c491d 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
@@ -28,6 +28,90 @@ properties:
           - const: brcm,bcm47622
           - const: brcm,bcmbca
 
+      - description: BCM4912 based boards
+        items:
+          - enum:
+              - brcm,bcm94912
+          - const: brcm,bcm4912
+          - const: brcm,bcmbca
+
+      - description: BCM63146 based boards
+        items:
+          - enum:
+              - brcm,bcm963146
+          - const: brcm,bcm63146
+          - const: brcm,bcmbca
+
+      - description: BCM63148 based boards
+        items:
+          - enum:
+              - brcm,bcm963148
+          - const: brcm,bcm63148
+          - const: brcm,bcmbca
+
+      - description: BCM63158 based boards
+        items:
+          - enum:
+              - brcm,bcm963158
+          - const: brcm,bcm63158
+          - const: brcm,bcmbca
+
+      - description: BCM63178 based boards
+        items:
+          - enum:
+              - brcm,bcm963178
+          - const: brcm,bcm63178
+          - const: brcm,bcmbca
+
+      - description: BCM6756 based boards
+        items:
+          - enum:
+              - brcm,bcm96756
+          - const: brcm,bcm6756
+          - const: brcm,bcmbca
+
+      - description: BCM6813 based boards
+        items:
+          - enum:
+              - brcm,bcm96813
+          - const: brcm,bcm6813
+          - const: brcm,bcmbca
+
+      - description: BCM6846 based boards
+        items:
+          - enum:
+              - brcm,bcm96846
+          - const: brcm,bcm6846
+          - const: brcm,bcmbca
+
+      - description: BCM6855 based boards
+        items:
+          - enum:
+              - brcm,bcm96855
+          - const: brcm,bcm6855
+          - const: brcm,bcmbca
+
+      - description: BCM6856 based boards
+        items:
+          - enum:
+              - brcm,bcm96856
+          - const: brcm,bcm6856
+          - const: brcm,bcmbca
+
+      - description: BCM6858 based boards
+        items:
+          - enum:
+              - brcm,bcm96858
+          - const: brcm,bcm6858
+          - const: brcm,bcmbca
+
+      - description: BCM6878 based boards
+        items:
+          - enum:
+              - brcm,bcm96878
+          - const: brcm,bcm6878
+          - const: brcm,bcmbca
+
 additionalProperties: true
 
 ...
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index ef524378d449..a4a3621a8a85 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -321,6 +321,7 @@ properties:
           - enum:
               - toradex,apalis_imx6q-ixora      # Apalis iMX6Q/D Module on Ixora Carrier Board
               - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
+              - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
               - toradex,apalis_imx6q-eval       # Apalis iMX6Q/D Module on Apalis Evaluation Board
           - const: toradex,apalis_imx6q
           - const: fsl,imx6q
@@ -670,30 +671,30 @@ properties:
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
         items:
           - enum:
-              - toradex,colibri-imx6ull-aster     # Colibri iMX6ULL Module on Aster Carrier Board
-              - toradex,colibri-imx6ull-eval      # Colibri iMX6ULL Module on Colibri Evaluation Board V3
-              - toradex,colibri-imx6ull-iris      # Colibri iMX6ULL Module on Iris Carrier Board
-              - toradex,colibri-imx6ull-iris-v2   # Colibri iMX6ULL Module on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-aster     # Aster Carrier Board
+              - toradex,colibri-imx6ull-eval      # Colibri Evaluation Board V3
+              - toradex,colibri-imx6ull-iris      # Iris Carrier Board
+              - toradex,colibri-imx6ull-iris-v2   # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull        # Colibri iMX6ULL Module
           - const: fsl,imx6ull
 
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
         items:
           - enum:
-              - toradex,colibri-imx6ull-emmc-aster     # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
-              - toradex,colibri-imx6ull-emmc-eval      # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
-              - toradex,colibri-imx6ull-emmc-iris      # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
-              - toradex,colibri-imx6ull-emmc-iris-v2   # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-emmc-aster     # Aster Carrier Board
+              - toradex,colibri-imx6ull-emmc-eval      # Colibri Evaluation B. V3
+              - toradex,colibri-imx6ull-emmc-iris      # Iris Carrier Board
+              - toradex,colibri-imx6ull-emmc-iris-v2   # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull-emmc        # Colibri iMX6ULL 1GB (eMMC) Module
           - const: fsl,imx6ull
 
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
         items:
           - enum:
-              - toradex,colibri-imx6ull-wifi-eval     # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
-              - toradex,colibri-imx6ull-wifi-aster    # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
-              - toradex,colibri-imx6ull-wifi-iris     # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
-              - toradex,colibri-imx6ull-wifi-iris-v2  # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-wifi-eval     # Colibri Eval. B. V3
+              - toradex,colibri-imx6ull-wifi-aster    # Aster Carrier Board
+              - toradex,colibri-imx6ull-wifi-iris     # Iris Carrier Board
+              - toradex,colibri-imx6ull-wifi-iris-v2  # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull-wifi       # Colibri iMX6ULL Wi-Fi / BT Module
           - const: fsl,imx6ull
 
@@ -738,6 +739,8 @@ properties:
           - enum:
               - toradex,colibri-imx7s-aster     # Module on Aster Carrier Board
               - toradex,colibri-imx7s-eval-v3   # Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7s-iris      # Module on Iris Carrier Board
+              - toradex,colibri-imx7s-iris-v2   # Module on Iris Carrier Board V2
           - const: toradex,colibri-imx7s
           - const: fsl,imx7s
 
@@ -789,8 +792,10 @@ properties:
       - description: i.MX7D Boards with Toradex Colibri i.MX7D Module
         items:
           - enum:
-              - toradex,colibri-imx7d-aster   # Colibri iMX7D Module on Aster Carrier Board
-              - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-aster   # Aster Carrier Board
+              - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-iris    # Iris Carrier Board
+              - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2
           - const: toradex,colibri-imx7d
           - const: fsl,imx7d
 
@@ -799,6 +804,8 @@ properties:
           - enum:
               - toradex,colibri-imx7d-emmc-aster    # Module on Aster Carrier Board
               - toradex,colibri-imx7d-emmc-eval-v3  # Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-emmc-iris     # Module on Iris Carrier Board
+              - toradex,colibri-imx7d-emmc-iris-v2  # Module on Iris Carrier Board V2
           - const: toradex,colibri-imx7d-emmc
           - const: fsl,imx7d
 
@@ -914,6 +921,8 @@ properties:
       - description: i.MX8MP based Boards
         items:
           - enum:
+              - dh,imx8mp-dhcom-som       # i.MX8MP DHCOM SoM
+              - dh,imx8mp-dhcom-pdk2      # i.MX8MP DHCOM SoM on PDK2 board
               - fsl,imx8mp-evk            # i.MX8MP EVK Board
               - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board
               - toradex,verdin-imx8mp     # Verdin iMX8M Plus Modules
@@ -1020,6 +1029,12 @@ properties:
               - fsl,imx8ulp-evk           # i.MX8ULP EVK Board
           - const: fsl,imx8ulp
 
+      - description: i.MX93 based Boards
+        items:
+          - enum:
+              - fsl,imx93-11x11-evk       # i.MX93 11x11 EVK Board
+          - const: fsl,imx93
+
       - description:
           Freescale Vybrid Platform Device Tree Bindings
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
index 0886e2e335bb..661047d26e11 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -39,6 +39,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index c8c67c033f8c..b57cc2e69efb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -24,7 +24,6 @@ properties:
           - mediatek,mt8192-imp_iic_wrap_w
           - mediatek,mt8192-imp_iic_wrap_n
           - mediatek,mt8192-msdc_top
-          - mediatek,mt8192-msdc
           - mediatek,mt8192-mfgcfg
           - mediatek,mt8192-imgsys
           - mediatek,mt8192-imgsys2
@@ -107,13 +106,6 @@ examples:
         #clock-cells = <1>;
     };
 
-  - |
-    msdc: clock-controller@11f60000 {
-        compatible = "mediatek,mt8192-msdc";
-        reg = <0x11f60000 0x1000>;
-        #clock-cells = <1>;
-    };
-
   - |
     mfgcfg: clock-controller@13fbf000 {
         compatible = "mediatek,mt8192-mfgcfg";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 5705bcf1fe47..27f79175c678 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -29,6 +29,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 57a1503d95fe..95b6bdf99936 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -37,6 +37,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 5c06d1bfc046..02087bb1f698 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -38,6 +38,8 @@ description: |
         msm8992
         msm8994
         msm8996
+        msm8998
+        qcs404
         sa8155p
         sa8540p
         sc7180
@@ -46,10 +48,13 @@ description: |
         sc8280xp
         sdm630
         sdm632
+        sdm636
         sdm660
         sdm845
         sdx55
         sdx65
+        sm6125
+        sm6350
         sm7225
         sm8150
         sm8250
@@ -153,28 +158,50 @@ properties:
           - const: qcom,msm8974
 
       - items:
-          - enum:
-              - alcatel,idol347
-          - const: qcom,msm8916-mtp/1
           - const: qcom,msm8916-mtp
+          - const: qcom,msm8916-mtp/1
           - const: qcom,msm8916
 
       - items:
           - enum:
-              - longcheer,l8150
+              - alcatel,idol347
+              - asus,z00l
+              - huawei,g7
+              - longcheer,l8910
               - samsung,a3u-eur
               - samsung,a5u-eur
+              - samsung,j5
+              - samsung,serranove
+              - wingtech,wt88047
+          - const: qcom,msm8916
+
+      - items:
+          - const: longcheer,l8150
+          - const: qcom,msm8916-v1-qrd/9-v1
           - const: qcom,msm8916
 
+      - items:
+          - enum:
+              - lg,bullhead
+              - microsoft,talkman
+              - xiaomi,libra
+          - const: qcom,msm8992
+
       - items:
           - enum:
               - sony,karin_windy
+          - const: qcom,apq8094
+
+      - items:
+          - enum:
+              - huawei,angler
+              - microsoft,cityman
+              - sony,ivy-row
               - sony,karin-row
               - sony,satsuki-row
               - sony,sumire-row
               - sony,suzuran-row
-              - qcom,msm8994
-          - const: qcom,apq8094
+          - const: qcom,msm8994
 
       - items:
           - enum:
@@ -193,6 +220,20 @@ properties:
               - xiaomi,scorpio
           - const: qcom,msm8996
 
+      - items:
+          - enum:
+              - asus,novago-tp370ql
+              - fxtec,pro1
+              - hp,envy-x2
+              - lenovo,miix-630
+              - oneplus,cheeseburger
+              - oneplus,dumpling
+              - qcom,msm8998-mtp
+              - sony,xperia-lilac
+              - sony,xperia-maple
+              - sony,xperia-poplar
+          - const: qcom,msm8998
+
       - items:
           - enum:
               - qcom,ipq4019-ap-dk01.1-c1
@@ -241,11 +282,24 @@ properties:
               - qcom,sc8280xp-qrd
           - const: qcom,sc8280xp
 
+      - items:
+          - enum:
+              - sony,discovery-row
+              - sony,kirin-row
+              - sony,pioneer-row
+              - sony,voyager-row
+          - const: qcom,sdm630
+
       - items:
           - enum:
               - fairphone,fp3
           - const: qcom,sdm632
 
+      - items:
+          - enum:
+              - sony,mermaid-row
+          - const: qcom,sdm636
+
       - items:
           - enum:
               - xiaomi,lavender
@@ -269,6 +323,13 @@ properties:
               - qcom,ipq6018-cp01-c1
           - const: qcom,ipq6018
 
+      - items:
+          - enum:
+              - qcom,qcs404-evb-1000
+              - qcom,qcs404-evb-4000
+          - const: qcom,qcs404-evb
+          - const: qcom,qcs404
+
       - items:
           - enum:
               - qcom,sa8155p-adp
@@ -279,6 +340,31 @@ properties:
               - qcom,sa8295p-adp
           - const: qcom,sa8540p
 
+      - items:
+          - enum:
+              - lenovo,yoga-c630
+              - oneplus,enchilada
+              - oneplus,fajita
+              - qcom,sdm845-mtp
+              - shift,axolotl
+              - samsung,w737
+              - sony,akari-row
+              - sony,akatsuki-row
+              - sony,apollo-row
+              - thundercomm,db845c
+              - xiaomi,beryllium
+          - const: qcom,sdm845
+
+      - items:
+          - enum:
+              - sony,pdx201
+          - const: qcom,sm6125
+
+      - items:
+          - enum:
+              - sony,pdx213
+          - const: qcom,sm6350
+
       - items:
           - enum:
               - fairphone,fp4
@@ -286,19 +372,29 @@ properties:
 
       - items:
           - enum:
+              - microsoft,surface-duo
+              - qcom,sm8150-hdk
               - qcom,sm8150-mtp
+              - sony,bahamut-generic
+              - sony,griffin-generic
           - const: qcom,sm8150
 
       - items:
           - enum:
               - qcom,qrb5165-rb5
+              - qcom,sm8250-hdk
               - qcom,sm8250-mtp
+              - sony,pdx203-generic
+              - sony,pdx206-generic
           - const: qcom,sm8250
 
       - items:
           - enum:
+              - microsoft,surface-duo2
               - qcom,sm8350-hdk
               - qcom,sm8350-mtp
+              - sony,pdx214-generic
+              - sony,pdx215-generic
           - const: qcom,sm8350
 
       - items:
diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
deleted file mode 100644
index 1f80767da38b..000000000000
--- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml
+++ /dev/null
@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Renesas Product Register
-
-maintainers:
-  - Geert Uytterhoeven <geert+renesas@glider.be>
-  - Magnus Damm <magnus.damm@gmail.com>
-
-description: |
-  Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
-  Register that allows to retrieve SoC product and revision information.
-  If present, a device node for this register should be added.
-
-properties:
-  compatible:
-    enum:
-      - renesas,prr
-      - renesas,bsid
-  reg:
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-
-additionalProperties: false
-
-examples:
-  - |
-    prr: chipid@ff000044 {
-        compatible = "renesas,prr";
-        reg = <0xff000044 4>;
-    };
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index cf9eb1e8326a..7811ba64149c 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -554,6 +554,11 @@ properties:
           - const: vamrs,rk3399pro-vmarc-som
           - const: rockchip,rk3399pro
 
+      - description: Radxa ROCK Pi S
+        items:
+          - const: radxa,rockpis
+          - const: rockchip,rk3308
+
       - description: Radxa Rock2 Square
         items:
           - const: radxa,rock2-square
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml b/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml
index b5e26e41f88c..f04db802a732 100644
--- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml
+++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml
@@ -29,6 +29,13 @@ properties:
 
   ranges: true
 
+  gpio-controller:
+    deprecated: true
+
+  "#gpio-cells":
+    deprecated: true
+    const: 2
+
 additionalProperties: false
 
 patternProperties:
@@ -67,8 +74,7 @@ patternProperties:
 
 required:
   - compatible
-  - "#address-cells"
-  - "#size-cells"
+  - reg
 
 examples:
   - |
diff --git a/Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml b/Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml
new file mode 100644
index 000000000000..5b875af6a95a
--- /dev/null
+++ b/Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ChromeOS keyboard backlight LED driver.
+
+maintainers:
+  - Tzung-Bi Shih <tzungbi@kernel.org>
+
+properties:
+  compatible:
+    const: google,cros-kbd-led-backlight
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    spi0 {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      cros_ec: ec@0 {
+        compatible = "google,cros-ec-spi";
+        reg = <0>;
+
+        kbd-led-backlight {
+          compatible = "google,cros-kbd-led-backlight";
+        };
+      };
+    };
diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
index e79eeac5f086..17caf78f0ccf 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
@@ -28,6 +28,9 @@ properties:
       - items:
           - const: allwinner,sun8i-r40-de2-clk
           - const: allwinner,sun8i-h3-de2-clk
+      - items:
+          - const: allwinner,sun20i-d1-de2-clk
+          - const: allwinner,sun50i-h5-de2-clk
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/efm32-clock.txt b/Documentation/devicetree/bindings/clock/efm32-clock.txt
deleted file mode 100644
index 263d293f6a10..000000000000
--- a/Documentation/devicetree/bindings/clock/efm32-clock.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit
-
-Required properties:
-- compatible: Should be "efm32gg,cmu"
-- reg: Base address and length of the register set
-- interrupts: Interrupt used by the CMU
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock by having the clock ID in
-its "clocks" phandle cell. The header efm32-clk.h contains a list of available
-IDs.
diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
index f415845b38dd..0b02378a3a0c 100644
--- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
@@ -13,7 +13,6 @@ maintainers:
 properties:
   compatible:
     enum:
-      - allwinner,sun4i-a10-pll3-2x-clk
       - fixed-factor-clock
 
   "#clock-cells":
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 8880b834f264..d036675e0779 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -45,10 +45,9 @@ properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/r9a0*-cpg.h>
+        <dt-bindings/clock/r9a0*-cpg.h>,
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
-        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
-        <dt-bindings/clock/r9a09g011-cpg.h>.
+        a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
     const: 2
 
   '#power-domain-cells':
@@ -62,7 +61,7 @@ properties:
   '#reset-cells':
     description:
       The single reset specifier cell must be the module number, as defined in
-      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
+      <dt-bindings/clock/r9a0*-cpg.h>.
     const: 1
 
 required:
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
index 5073e569a47f..006d33a9e0f1 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
@@ -33,6 +33,7 @@ properties:
     enum:
       - samsung,exynos7885-cmu-top
       - samsung,exynos7885-cmu-core
+      - samsung,exynos7885-cmu-fsys
       - samsung,exynos7885-cmu-peri
 
   clocks:
@@ -88,6 +89,32 @@ allOf:
             - const: dout_core_cci
             - const: dout_core_g3d
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-fsys
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_FSYS bus clock (from CMU_TOP)
+            - description: MMC_CARD clock (from CMU_TOP)
+            - description: MMC_EMBD clock (from CMU_TOP)
+            - description: MMC_SDIO clock (from CMU_TOP)
+            - description: USB30DRD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_fsys_bus
+            - const: dout_fsys_mmc_card
+            - const: dout_fsys_mmc_embd
+            - const: dout_fsys_mmc_sdio
+            - const: dout_fsys_usb30drd
+
   - if:
       properties:
         compatible:
diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
index f8c474227807..242fe922b035 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
@@ -78,6 +78,7 @@ if:
       contains:
         enum:
           - st,stm32mp1-rcc-secure
+          - st,stm32mp13-rcc
 then:
   properties:
     clocks:
diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.yaml b/Documentation/devicetree/bindings/display/arm,pl11x.yaml
index b545c6d20325..6cc9045e5c68 100644
--- a/Documentation/devicetree/bindings/display/arm,pl11x.yaml
+++ b/Documentation/devicetree/bindings/display/arm,pl11x.yaml
@@ -159,25 +159,12 @@ examples:
     };
 
     panel {
-        compatible = "arm,rtsm-display", "panel-dpi";
-        power-supply = <&vcc_supply>;
+        compatible = "arm,rtsm-display";
 
         port {
             clcd_panel: endpoint {
                 remote-endpoint = <&clcd_pads>;
             };
         };
-
-        panel-timing {
-            clock-frequency = <25175000>;
-            hactive = <640>;
-            hback-porch = <40>;
-            hfront-porch = <24>;
-            hsync-len = <96>;
-            vactive = <480>;
-            vback-porch = <32>;
-            vfront-porch = <11>;
-            vsync-len = <2>;
-        };
     };
 ...
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
index 35a48515836e..4590186c4a0b 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
@@ -94,7 +94,22 @@ properties:
         $ref: /schemas/graph.yaml#/$defs/port-base
         unevaluatedProperties: false
         description:
-          Video port for MIPI DSI input.
+          MIPI DSI/DPI input.
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            type: object
+            additionalProperties: false
+
+            properties:
+              remote-endpoint: true
+
+              bus-type:
+                enum: [7]
+                default: 1
+
+              data-lanes: true
 
       port@1:
         $ref: /schemas/graph.yaml#/properties/port
@@ -143,6 +158,8 @@ examples:
                     reg = <0>;
                     anx7625_in: endpoint {
                         remote-endpoint = <&mipi_dsi>;
+                        bus-type = <7>;
+                        data-lanes = <0 1 2 3>;
                     };
                 };
 
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
new file mode 100644
index 000000000000..94543006f5de
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
+
+  The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
+  The CSR module, as a system controller, contains the LDB's configuration
+  registers.
+
+  For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
+  format and can map the input to VESA or JEIDA standards.  The two channels
+  cannot be used simultaneously, that is to say, the user should pick one of
+  them to use.  Two LDB channels from two LDB instances can work together in
+  LDB split mode to support a dual link LVDS display.  The channel indexes
+  have to be different.  Channel0 outputs odd pixels and channel1 outputs
+  even pixels.
+
+  For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
+  input color format.  The two channels can be used simultaneously, either
+  in dual mode or split mode.  In dual mode, the two channels output identical
+  data.  In split mode, channel0 outputs odd pixels and channel1 outputs even
+  pixels.
+
+  A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
+  the SoC reference manuals.  The pixel mapper uses logic of LDBs embedded in
+  i.MX6qdl/sx SoCs, i.e., it is essentially based on them.  To keep the naming
+  consistency, this binding calls it LDB.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qm-ldb
+      - fsl,imx8qxp-ldb
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: pixel clock
+      - description: bypass clock
+
+  clock-names:
+    items:
+      - const: pixel
+      - const: bypass
+
+  power-domains:
+    maxItems: 1
+
+  fsl,companion-ldb:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle which points to companion LDB which is used in LDB split mode.
+
+patternProperties:
+  "^channel@[0-1]$":
+    type: object
+    description: Represents a channel of LDB.
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+      reg:
+        description: The channel index.
+        enum: [ 0, 1 ]
+
+      phys:
+        description: A phandle to the phy module representing the LVDS PHY.
+        maxItems: 1
+
+      phy-names:
+        const: lvds_phy
+
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input port of the channel.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output port of the channel.
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+      - reg
+      - phys
+      - phy-names
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - clocks
+  - clock-names
+  - power-domains
+  - channel@0
+  - channel@1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qm-ldb
+    then:
+      properties:
+        fsl,companion-ldb: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    ldb {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx8qxp-ldb";
+        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+                 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+        clock-names = "pixel", "bypass";
+        power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+        channel@0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0>;
+            phys = <&mipi_lvds_0_phy>;
+            phy-names = "lvds_phy";
+
+            port@0 {
+                reg = <0>;
+
+                mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+                };
+            };
+        };
+
+        channel@1 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <1>;
+            phys = <&mipi_lvds_0_phy>;
+            phy-names = "lvds_phy";
+
+            port@0 {
+                reg = <0>;
+
+                mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
new file mode 100644
index 000000000000..50bae2122183
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Pixel Combiner
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
+  single display controller and manipulates the two streams to support a number
+  of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
+  either one screen, two screens, or virtual screens.  The pixel combiner is
+  also responsible for generating some of the control signals for the pixel link
+  output channel.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qm-pixel-combiner
+      - fsl,imx8qxp-pixel-combiner
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: apb
+
+  power-domains:
+    maxItems: 1
+
+patternProperties:
+  "^channel@[0-1]$":
+    type: object
+    description: Represents a display stream of pixel combiner.
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+      reg:
+        description: The display stream index.
+        enum: [ 0, 1 ]
+
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input endpoint of the display stream.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output endpoint of the display stream.
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+      - reg
+      - port@0
+      - port@1
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    pixel-combiner@56020000 {
+        compatible = "fsl,imx8qxp-pixel-combiner";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x56020000 0x10000>;
+        clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
+        clock-names = "apb";
+        power-domains = <&pd IMX_SC_R_DC_0>;
+
+        channel@0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
+                    remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
+                    remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
+                };
+            };
+        };
+
+        channel@1 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <1>;
+
+            port@0 {
+                reg = <0>;
+
+                dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
+                    remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
+                    remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
new file mode 100644
index 000000000000..38ecc7926fad
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Pixel Link
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
+  asynchronous linkage between pixel sources(display controller or
+  camera module) and pixel consumers(imaging or displays).
+  It consists of two distinct functions, a pixel transfer function and a
+  control interface.  Multiple pixel channels can exist per one control channel.
+  This binding documentation is only for pixel links whose pixel sources are
+  display controllers.
+
+  The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
+  firmware.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qm-dc-pixel-link
+      - fsl,imx8qxp-dc-pixel-link
+
+  fsl,dc-id:
+    $ref: /schemas/types.yaml#/definitions/uint8
+    description: |
+      u8 value representing the display controller index that the pixel link
+      connects to.
+
+  fsl,dc-stream-id:
+    $ref: /schemas/types.yaml#/definitions/uint8
+    description: |
+      u8 value representing the display controller stream index that the pixel
+      link connects to.
+    enum: [0, 1]
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The pixel link input port node from upstream video source.
+
+    patternProperties:
+      "^port@[1-4]$":
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The pixel link output port node to downstream bridge.
+
+    required:
+      - port@0
+      - port@1
+      - port@2
+      - port@3
+      - port@4
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qxp-dc-pixel-link
+    then:
+      properties:
+        fsl,dc-id:
+          const: 0
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qm-dc-pixel-link
+    then:
+      properties:
+        fsl,dc-id:
+          enum: [0, 1]
+
+required:
+  - compatible
+  - fsl,dc-id
+  - fsl,dc-stream-id
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    dc0-pixel-link0 {
+        compatible = "fsl,imx8qxp-dc-pixel-link";
+        fsl,dc-id = /bits/ 8 <0>;
+        fsl,dc-stream-id = /bits/ 8 <0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* from dc0 pixel combiner channel0 */
+            port@0 {
+                reg = <0>;
+
+                dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
+                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
+                };
+            };
+
+            /* to PXL2DPIs in MIPI/LVDS combo subsystems */
+            port@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+
+                dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
+                };
+
+                dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
+                    reg = <1>;
+                    remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
+                };
+            };
+
+            /* unused */
+            port@2 {
+                reg = <2>;
+            };
+
+            /* unused */
+            port@3 {
+                reg = <3>;
+            };
+
+            /* to imaging subsystem */
+            port@4 {
+                reg = <4>;
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
new file mode 100644
index 000000000000..e4e77fad05f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
+  interfaces the pixel link 36-bit data output and the DSI controller’s
+  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
+  used in LVDS mode, to remap the pixel color codings between those modules.
+  This module is purely combinatorial.
+
+  The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
+  The CSR module, as a system controller, contains the PXL2DPI's configuration
+  register.
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-pxl2dpi
+
+  fsl,sc-resource:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The SCU resource ID associated with this PXL2DPI instance.
+
+  power-domains:
+    maxItems: 1
+
+  fsl,companion-pxl2dpi:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle which points to companion PXL2DPI which is used by downstream
+      LVDS Display Bridge(LDB) in split mode.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The PXL2DPI input port node from pixel link.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The PXL2DPI output port node to downstream bridge.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - fsl,sc-resource
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    pxl2dpi {
+        compatible = "fsl,imx8qxp-pxl2dpi";
+        fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+        power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+
+                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
+                };
+
+                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
+                     reg = <1>;
+                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+                };
+            };
+
+            port@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+
+                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+                };
+
+                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+                    reg = <1>;
+                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
index 77f174eee424..2ebaa43eb62e 100644
--- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
@@ -24,6 +24,15 @@ properties:
   clock-names:
     const: ldb
 
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: ldb
+      - const: lvds
+
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
 
@@ -56,10 +65,15 @@ examples:
     #include <dt-bindings/clock/imx8mp-clock.h>
 
     blk-ctrl {
-        bridge {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        bridge@5c {
             compatible = "fsl,imx8mp-ldb";
             clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
             clock-names = "ldb";
+            reg = <0x5c 0x4>, <0x128 0x4>;
+            reg-names = "ldb", "lvds";
 
             ports {
                 #address-cells = <1>;
diff --git a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
index b8219eab4475..89490fdffeb0 100644
--- a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml
@@ -55,7 +55,6 @@ examples:
         compatible = "ingenic,jz4780-dw-hdmi";
         reg = <0x10180000 0x8000>;
         reg-io-width = <4>;
-        ddc-i2c-bus = <&i2c4>;
         interrupt-parent = <&intc>;
         interrupts = <3>;
         clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
diff --git a/Documentation/devicetree/bindings/display/bridge/sii902x.txt b/Documentation/devicetree/bindings/display/bridge/sii902x.txt
deleted file mode 100644
index 3bc760cc31cb..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/sii902x.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-sii902x HDMI bridge bindings
-
-Required properties:
-	- compatible: "sil,sii9022"
-	- reg: i2c address of the bridge
-
-Optional properties:
-	- interrupts: describe the interrupt line used to inform the host
-	  about hotplug events.
-	- reset-gpios: OF device-tree gpio specification for RST_N pin.
-	- iovcc-supply: I/O Supply Voltage (1.8V or 3.3V)
-	- cvcc12-supply: Digital Core Supply Voltage (1.2V)
-
-	HDMI audio properties:
-	- #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
-	   is wired, <1> if the both are wired. HDMI audio is
-	   configured only if this property is found.
-	- sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
-	   Each integer indicates which i2s pin is connected to which
-	   audio fifo. The first integer selects i2s audio pin for the
-	   first audio fifo#0 (HDMI channels 1&2), second for fifo#1
-	   (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s
-	   pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
-	   but there can be no gaps. E.g. an i2s pin must be mapped to
-	   fifo#0 and fifo#1 before mapping a channel to fifo#2. Default
-	   value is <0>, describing SD0 pin beiging routed to hdmi audio
-	   fifo #0.
-	- clocks: phandle and clock specifier for each clock listed in
-           the clock-names property
-	- clock-names: "mclk"
-	   Describes SII902x MCLK input. MCLK can be used to produce
-	   HDMI audio CTS values. This property follows
-	   Documentation/devicetree/bindings/clock/clock-bindings.txt
-	   consumer binding.
-
-	If HDMI audio is configured the sii902x device becomes an I2S
-	and/or spdif audio codec component (e.g a digital audio sink),
-	that can be used in configuring a full audio devices with
-	simple-card or audio-graph-card binding. See their binding
-	documents on how to describe the way the sii902x device is
-	connected to the rest of the audio system:
-	Documentation/devicetree/bindings/sound/simple-card.yaml
-	Documentation/devicetree/bindings/sound/audio-graph-card.yaml
-	Note: In case of the audio-graph-card binding the used port
-	index should be 3.
-
-Optional subnodes:
-	- video input: this subnode can contain a video input port node
-	  to connect the bridge to a display controller output (See this
-	  documentation [1]).
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-	hdmi-bridge@39 {
-		compatible = "sil,sii9022";
-		reg = <0x39>;
-		reset-gpios = <&pioA 1 0>;
-		iovcc-supply = <&v3v3_hdmi>;
-		cvcc12-supply = <&v1v2_hdmi>;
-
-		#sound-dai-cells = <0>;
-		sil,i2s-data-lanes = < 0 1 2 >;
-		clocks = <&mclk>;
-		clock-names = "mclk";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				bridge_in: endpoint {
-					remote-endpoint = <&dc_out>;
-				};
-			};
-		};
-	};
diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
new file mode 100644
index 000000000000..5a69547ad3d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silicon Image sii902x HDMI bridge
+
+maintainers:
+  - Boris Brezillon <bbrezillon@kernel.org>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - sil,sii9022-cpi # CEC Programming Interface
+              - sil,sii9022-tpi # Transmitter Programming Interface
+          - const: sil,sii9022
+      - const: sil,sii9022
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description: Interrupt line used to inform the host about hotplug events.
+
+  reset-gpios:
+    maxItems: 1
+
+  iovcc-supply:
+    description: I/O Supply Voltage (1.8V or 3.3V)
+
+  cvcc12-supply:
+    description: Digital Core Supply Voltage (1.2V)
+
+  '#sound-dai-cells':
+    enum: [ 0, 1 ]
+    description: |
+      <0> if only I2S or S/PDIF pin is wired,
+      <1> if both are wired.
+      HDMI audio is configured only if this property is found.
+      If HDMI audio is configured, the sii902x device becomes an I2S and/or
+      S/PDIF audio codec component (e.g. a digital audio sink), that can be
+      used in configuring full audio devices with simple-card or
+      audio-graph-card bindings. See their binding documents on how to describe
+      the way the
+      sii902x device is connected to the rest of the audio system:
+      Documentation/devicetree/bindings/sound/simple-card.yaml
+      Documentation/devicetree/bindings/sound/audio-graph-card.yaml
+      Note: In case of the audio-graph-card binding the used port index should
+      be 3.
+
+  sil,i2s-data-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 4
+    uniqueItems: true
+    items:
+      enum: [ 0, 1, 2, 3 ]
+    description:
+      Each integer indicates which I2S pin is connected to which audio FIFO.
+      The first integer selects the I2S audio pin for the first audio FIFO#0
+      (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
+      on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be
+      connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
+      mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
+      default value is <0>, describing SD0 pin being routed to HDMI audio
+      FIFO#0.
+
+  clocks:
+    maxItems: 1
+    description: MCLK input. MCLK can be used to produce HDMI audio CTS values.
+
+  clock-names:
+    const: mclk
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Parallel RGB input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: HDMI output port
+
+      port@3:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Sound input port
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        hdmi-bridge@39 {
+            compatible = "sil,sii9022";
+            reg = <0x39>;
+            reset-gpios = <&pioA 1 0>;
+            iovcc-supply = <&v3v3_hdmi>;
+            cvcc12-supply = <&v1v2_hdmi>;
+
+            #sound-dai-cells = <0>;
+            sil,i2s-data-lanes = < 0 1 2 >;
+            clocks = <&mclk>;
+            clock-names = "mclk";
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    bridge_in: endpoint {
+                        remote-endpoint = <&dc_out>;
+                    };
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml b/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
new file mode 100644
index 000000000000..542193d77cdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DLPC3433 MIPI DSI to DMD bridge
+
+maintainers:
+  - Jagan Teki <jagan@amarulasolutions.com>
+  - Christopher Vollo <chris@renewoutreach.org>
+
+description: |
+  TI DLPC3433 is a MIPI DSI based display controller bridge
+  for processing high resolution DMD based projectors.
+
+  It has a flexible configuration of MIPI DSI and DPI signal
+  input that produces a DMD output in RGB565, RGB666, RGB888
+  formats.
+
+  It supports upto 720p resolution with 60 and 120 Hz refresh
+  rates.
+
+properties:
+  compatible:
+    const: ti,dlpc3433
+
+  reg:
+    enum:
+      - 0x1b
+      - 0x1d
+
+  enable-gpios:
+    description: PROJ_ON pin, chip powers up PROJ_ON is high.
+
+  vcc_intf-supply:
+    description: A 1.8V/3.3V supply that power the Host I/O.
+
+  vcc_flsh-supply:
+    description: A 1.8V/3.3V supply that power the Flash I/O.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description: Video port for MIPI DSI input.
+
+        properties:
+          endpoint:
+            $ref: /schemas/media/video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                description: array of physical DSI data lane indexes.
+                minItems: 1
+                items:
+                  - const: 1
+                  - const: 2
+                  - const: 3
+                  - const: 4
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Video port for DMD output.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        bridge@1b {
+            compatible = "ti,dlpc3433";
+            reg = <0x1b>;
+            enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    bridge_in_dsi: endpoint {
+                        remote-endpoint = <&dsi_out_bridge>;
+                        data-lanes = <1 2 3 4>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    bridge_out_panel: endpoint {
+                        remote-endpoint = <&panel_out_bridge>;
+                    };
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
deleted file mode 100644
index 3fdad71210b4..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ /dev/null
@@ -1,87 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek mutex
-
-maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
-  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
-  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
-  data path or MDP data path.
-  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
-  the shadow register.
-  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
-
-properties:
-  compatible:
-    enum:
-      - mediatek,mt2701-disp-mutex
-      - mediatek,mt2712-disp-mutex
-      - mediatek,mt8167-disp-mutex
-      - mediatek,mt8173-disp-mutex
-      - mediatek,mt8183-disp-mutex
-      - mediatek,mt8186-disp-mutex
-      - mediatek,mt8192-disp-mutex
-      - mediatek,mt8195-disp-mutex
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  power-domains:
-    description: A phandle and PM domain specifier as defined by bindings of
-      the power controller specified by phandle. See
-      Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
-  clocks:
-    items:
-      - description: MUTEX Clock
-
-  mediatek,gce-events:
-    description:
-      The event id which is mapping to the specific hardware event signal
-      to gce. The event id is defined in the gce header
-      include/dt-bindings/gce/<chip>-gce.h of each chips.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - power-domains
-  - clocks
-
-additionalProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/clock/mt8173-clk.h>
-    #include <dt-bindings/power/mt8173-power.h>
-    #include <dt-bindings/gce/mt8173-gce.h>
-
-    soc {
-        #address-cells = <2>;
-        #size-cells = <2>;
-
-        mutex: mutex@14020000 {
-            compatible = "mediatek,mt8173-disp-mutex";
-            reg = <0 0x14020000 0 0x1000>;
-            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
-            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
-            clocks = <&mmsys CLK_MM_MUTEX_32K>;
-            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
-                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
-        };
-    };
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index cd05cfd76536..94bc6e1b6451 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: MSM Display Port Controller
 
 maintainers:
-  - Kuogee Hsieh <khsieh@codeaurora.org>
+  - Kuogee Hsieh <quic_khsieh@quicinc.com>
 
 description: |
   Device tree bindings for DisplayPort host controller for MSM targets
@@ -76,6 +76,9 @@ properties:
   "#sound-dai-cells":
     const: 0
 
+  vdda-0p9-supply: true
+  vdda-1p2-supply: true
+
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
     properties:
@@ -137,6 +140,9 @@ examples:
 
         power-domains = <&rpmhpd SC7180_CX>;
 
+        vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+        vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
+
         ports {
             #address-cells = <1>;
             #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt
deleted file mode 100644
index 5f90a40da51b..000000000000
--- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-Qualcomm adreno/snapdragon hdmi output
-
-Required properties:
-- compatible: one of the following
-   * "qcom,hdmi-tx-8996"
-   * "qcom,hdmi-tx-8994"
-   * "qcom,hdmi-tx-8084"
-   * "qcom,hdmi-tx-8974"
-   * "qcom,hdmi-tx-8660"
-   * "qcom,hdmi-tx-8960"
-- reg: Physical base address and length of the controller's registers
-- reg-names: "core_physical"
-- interrupts: The interrupt signal from the hdmi block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See ../clocks/clock-bindings.txt for details.
-- core-vdda-supply: phandle to supply regulator
-- hdmi-mux-supply: phandle to mux regulator
-- phys: the phandle for the HDMI PHY device
-- phy-names: the name of the corresponding PHY device
-
-Optional properties:
-- hpd-gpios: hpd pin
-- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
-- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
-- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
-- power-domains: reference to the power domain(s), if available.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-1: the "sleep" pinctrl state
-
-HDMI PHY:
-Required properties:
-- compatible: Could be the following
-  * "qcom,hdmi-phy-8660"
-  * "qcom,hdmi-phy-8960"
-  * "qcom,hdmi-phy-8974"
-  * "qcom,hdmi-phy-8084"
-  * "qcom,hdmi-phy-8996"
-- #phy-cells: Number of cells in a PHY specifier; Should be 0.
-- reg: Physical base address and length of the registers of the PHY sub blocks.
-- reg-names: The names of register regions. The following regions are required:
-  * "hdmi_phy"
-  * "hdmi_pll"
-  For HDMI PHY on msm8996, these additional register regions are required:
-    * "hdmi_tx_l0"
-    * "hdmi_tx_l1"
-    * "hdmi_tx_l3"
-    * "hdmi_tx_l4"
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- core-vdda-supply: phandle to vdda regulator device node
-
-Example:
-
-/ {
-	...
-
-	hdmi: hdmi@4a00000 {
-		compatible = "qcom,hdmi-tx-8960";
-		reg-names = "core_physical";
-		reg = <0x04a00000 0x2f0>;
-		interrupts = <GIC_SPI 79 0>;
-		power-domains = <&mmcc MDSS_GDSC>;
-		clock-names =
-		    "core",
-		    "master_iface",
-		    "slave_iface";
-		clocks =
-		    <&mmcc HDMI_APP_CLK>,
-		    <&mmcc HDMI_M_AHB_CLK>,
-		    <&mmcc HDMI_S_AHB_CLK>;
-		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
-		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
-		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
-		core-vdda-supply = <&pm8921_hdmi_mvs>;
-		hdmi-mux-supply = <&ext_3p3v>;
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
-		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
-
-		phys = <&hdmi_phy>;
-		phy-names = "hdmi_phy";
-	};
-
-	hdmi_phy: phy@4a00400 {
-		compatible = "qcom,hdmi-phy-8960";
-		reg-names = "hdmi_phy",
-			    "hdmi_pll";
-		reg = <0x4a00400 0x60>,
-		      <0x4a00500 0x100>;
-		#phy-cells = <0>;
-		power-domains = <&mmcc MDSS_GDSC>;
-		clock-names = "slave_iface";
-		clocks = <&mmcc HDMI_S_AHB_CLK>;
-		core-vdda-supply = <&pm8921_hdmi_mvs>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
new file mode 100644
index 000000000000..47e97669821c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon HDMI output
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-tx-8084
+      - qcom,hdmi-tx-8660
+      - qcom,hdmi-tx-8960
+      - qcom,hdmi-tx-8974
+      - qcom,hdmi-tx-8994
+      - qcom,hdmi-tx-8996
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  reg:
+    minItems: 1
+    maxItems: 3
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: core_physical
+      - const: qfprom_physical
+      - const: hdcp_physical
+
+  interrupts:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    enum:
+      - hdmi_phy
+      - hdmi-phy
+    deprecated: true
+
+  core-vdda-supply:
+    description: phandle to VDDA supply regulator
+
+  hdmi-mux-supply:
+    description: phandle to mux regulator
+    deprecated: true
+
+  core-vcc-supply:
+    description: phandle to VCC supply regulator
+
+  hpd-gpios:
+    maxItems: 1
+    description: hpd pin
+
+  qcom,hdmi-tx-mux-en-gpios:
+    maxItems: 1
+    deprecated: true
+    description: HDMI mux enable pin
+
+  qcom,hdmi-tx-mux-sel-gpios:
+    maxItems: 1
+    deprecated: true
+    description: HDMI mux select pin
+
+  qcom,hdmi-tx-mux-lpm-gpios:
+    maxItems: 1
+    deprecated: true
+    description: HDMI mux lpm pin
+
+  '#sound-dai-cells':
+    const: 1
+
+  ports:
+    type: object
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        description: |
+          Input endpoints of the controller.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        description: |
+          Output endpoints of the controller.
+
+    required:
+      - port@0
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - interrupts
+  - phys
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-tx-8960
+              - qcom,hdmi-tx-8660
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: core
+            - const: master_iface
+            - const: slave_iface
+        core-vcc-supplies: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-tx-8974
+              - qcom,hdmi-tx-8084
+              - qcom,hdmi-tx-8994
+              - qcom,hdmi-tx-8996
+    then:
+      properties:
+        clocks:
+          minItems: 5
+        clock-names:
+          items:
+            - const: mdp_core
+            - const: iface
+            - const: core
+            - const: alt_iface
+            - const: extp
+        hdmi-mux-supplies: false
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    hdmi: hdmi@4a00000 {
+      compatible = "qcom,hdmi-tx-8960";
+      reg-names = "core_physical";
+      reg = <0x04a00000 0x2f0>;
+      interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+      clock-names = "core",
+                    "master_iface",
+                    "slave_iface";
+      clocks = <&clk 61>,
+               <&clk 72>,
+               <&clk 98>;
+      hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
+      core-vdda-supply = <&pm8921_hdmi_mvs>;
+      hdmi-mux-supply = <&ext_3p3v>;
+      pinctrl-names = "default", "sleep";
+      pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
+      pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
+
+      phys = <&hdmi_phy>;
+    };
+  - |
+    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+    #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    hdmi@9a0000 {
+      compatible = "qcom,hdmi-tx-8996";
+      reg = <0x009a0000 0x50c>,
+            <0x00070000 0x6158>,
+            <0x009e0000 0xfff>;
+      reg-names = "core_physical",
+                  "qfprom_physical",
+                  "hdcp_physical";
+
+      interrupt-parent = <&mdss>;
+      interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+
+      clocks = <&mmcc MDSS_MDP_CLK>,
+               <&mmcc MDSS_AHB_CLK>,
+               <&mmcc MDSS_HDMI_CLK>,
+               <&mmcc MDSS_HDMI_AHB_CLK>,
+               <&mmcc MDSS_EXTPCLK_CLK>;
+      clock-names = "mdp_core",
+                    "iface",
+                    "core",
+                    "alt_iface",
+                    "extp";
+
+      phys = <&hdmi_phy>;
+      #sound-dai-cells = <1>;
+
+      pinctrl-names = "default", "sleep";
+      pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+      pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+      core-vdda-supply = <&vreg_l12a_1p8>;
+      core-vcc-supply = <&vreg_s4a_1p8>;
+
+      ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@0 {
+          reg = <0>;
+          endpoint {
+            remote-endpoint = <&mdp5_intf3_out>;
+          };
+        };
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/display/panel/arm,rtsm-display.yaml b/Documentation/devicetree/bindings/display/panel/arm,rtsm-display.yaml
new file mode 100644
index 000000000000..4ad484f09ba3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/arm,rtsm-display.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/arm,rtsm-display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm RTSM Virtual Platforms Display
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+  - $ref: panel-common.yaml#
+
+properties:
+  compatible:
+    const: arm,rtsm-display
+
+  port: true
+
+required:
+  - compatible
+  - port
+
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml b/Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
index 95acf9e96f1c..1cf84c8dd85e 100644
--- a/Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
+++ b/Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
@@ -35,7 +35,6 @@ required:
   - reg
   - avdd-supply
   - dvdd-supply
-  - reset-gpios
 
 additionalProperties: false
 
diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
index 563766d283f6..41ee3157a1cd 100644
--- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
@@ -46,6 +46,7 @@ properties:
 
   reg: true
   port: true
+  backlight: true
 
 required:
   - compatible
@@ -73,6 +74,7 @@ examples:
             vddpos-supply = <&lab>;
             vddneg-supply = <&ibb>;
 
+            backlight = <&pmi8998_wled>;
             reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
 
             port {
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
deleted file mode 100644
index e4a25cedc5cf..000000000000
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-NVIDIA Tegra MIPI pad calibration controller
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-mipi"
-- reg: Physical base address and length of the controller's registers.
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - mipi-cal
-- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
-  that need to be calibrated for a given device.
-
-User nodes need to contain an nvidia,mipi-calibrate property that has a
-phandle to refer to the calibration controller node and a bitmask of the pads
-that need to be calibrated.
-
-Example:
-
-	mipi: mipi@700e3000 {
-		compatible = "nvidia,tegra114-mipi";
-		reg = <0x700e3000 0x100>;
-		clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
-		clock-names = "mipi-cal";
-		#nvidia,mipi-calibrate-cells = <1>;
-	};
-
-	...
-
-	host1x@50000000 {
-		...
-
-		dsi@54300000 {
-			...
-
-			nvidia,mipi-calibrate = <&mipi 0x060>;
-
-			...
-		};
-
-		...
-	};
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
new file mode 100644
index 000000000000..d5ca8cf86e8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra MIPI pad calibration controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^mipi@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra114-mipi
+      - nvidia,tegra210-mipi
+      - nvidia,tegra186-mipi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: mipi-cal
+
+  power-domains:
+    maxItems: 1
+
+  "#nvidia,mipi-calibrate-cells":
+    description: The number of cells in a MIPI calibration specifier.
+      Should be 1. The single cell specifies a bitmask of the pads that
+      need to be calibrated for a given device.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    const: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#nvidia,mipi-calibrate-cells"
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra114-car.h>
+
+    mipi@700e3000 {
+        compatible = "nvidia,tegra114-mipi";
+        reg = <0x700e3000 0x100>;
+        clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
+        clock-names = "mipi-cal";
+        #nvidia,mipi-calibrate-cells = <1>;
+    };
+
+    dsia: dsi@54300000 {
+        compatible = "nvidia,tegra114-dsi";
+        reg = <0x54300000 0x00040000>;
+        clocks = <&tegra_car TEGRA114_CLK_DSIA>,
+                 <&tegra_car TEGRA114_CLK_DSIALP>,
+                 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
+        clock-names = "dsi", "lp", "parent";
+        resets = <&tegra_car 48>;
+        reset-names = "dsi";
+        nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
new file mode 100644
index 000000000000..7df2b355b19b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra DisplayPort AUX Interface
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
+  pins which can be assigned to either the DPAUX channel or to an I2C
+  controller.
+
+  When configured for DisplayPort AUX operation, the DPAUX controller
+  can also be used to communicate with a DisplayPort device using the
+  AUX channel.
+
+properties:
+  $nodename:
+    pattern: "^dpaux@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-dpaux
+          - nvidia,tegra210-dpaux
+          - nvidia,tegra186-dpaux
+          - nvidia,tegra194-dpaux
+
+      - items:
+          - const: nvidia,tegra132-dpaux
+          - const: nvidia,tegra124-dpaux
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: clock input for the DPAUX hardware
+      - description: reference clock
+
+  clock-names:
+    items:
+      - const: dpaux
+      - const: parent
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dpaux
+
+  power-domains:
+    maxItems: 1
+
+  i2c-bus:
+    description: Subnode where I2C slave devices are listed. This
+      subnode must be always present. If there are no I2C slave
+      devices, an empty node should be added. See ../../i2c/i2c.yaml
+      for more information.
+    type: object
+
+  vdd-supply:
+    description: phandle of a supply that powers the DisplayPort
+      link
+
+patternProperties:
+  "^pinmux-[a-z0-9]+$":
+    description:
+      Since only three configurations are possible, only three child
+      nodes are needed to describe the pin mux'ing options for the
+      DPAUX pads. Furthermore, given that the pad functions are only
+      applicable to a single set of pads, the child nodes only need
+      to describe the pad group the functions are being applied to
+      rather than the individual pads.
+    type: object
+    properties:
+      groups:
+        const: dpaux-io
+
+      function:
+        enum:
+          - aux
+          - i2c
+          - off
+
+    additionalProperties: false
+
+    required:
+      - groups
+      - function
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    dpaux: dpaux@545c0000 {
+        compatible = "nvidia,tegra210-dpaux";
+        reg = <0x545c0000 0x00040000>;
+        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
+                 <&tegra_car TEGRA210_CLK_PLL_DP>;
+        clock-names = "dpaux", "parent";
+        resets = <&tegra_car 181>;
+        reset-names = "dpaux";
+        power-domains = <&pd_sor>;
+        status = "disabled";
+
+        state_dpaux_aux: pinmux-aux {
+            groups = "dpaux-io";
+            function = "aux";
+        };
+
+        state_dpaux_i2c: pinmux-i2c {
+            groups = "dpaux-io";
+            function = "i2c";
+        };
+
+        state_dpaux_off: pinmux-off {
+            groups = "dpaux-io";
+            function = "off";
+        };
+
+        i2c-bus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
new file mode 100644
index 000000000000..0188baad0865
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
@@ -0,0 +1,206 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra SOR Output Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+  The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
+  and DP outputs.
+
+properties:
+  $nodename:
+    pattern: "^sor@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-sor
+          - nvidia,tegra210-sor
+          - nvidia,tegra210-sor1
+          - nvidia,tegra186-sor
+          - nvidia,tegra186-sor1
+          - nvidia,tegra194-sor
+
+      - items:
+          - const: nvidia,tegra132-sor
+          - const: nvidia,tegra124-sor
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 5
+    maxItems: 6
+
+  clock-names:
+    minItems: 5
+    maxItems: 6
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: sor
+
+  power-domains:
+    maxItems: 1
+
+  avdd-io-hdmi-dp-supply:
+    description: I/O supply for HDMI/DP
+
+  vdd-hdmi-dp-pll-supply:
+    description: PLL supply for HDMI/DP
+
+  hdmi-supply:
+    description: +5.0V HDMI connector supply
+
+  # Tegra186 and later
+  nvidia,interface:
+    description: index of the SOR interface
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,xbar-cfg:
+    description: 5 cells containing the crossbar configuration.
+      Each lane of the SOR, identified by the cell's index, is
+      mapped via the crossbar to the pad specified by the cell's
+      value.
+    $ref: "/schemas/types.yaml#/definitions/uint32-array"
+
+  # optional when driving an eDP output
+  nvidia,dpaux:
+    description: phandle to a DispayPort AUX interface
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-sor
+              - nvidia,tegra194-sor
+    then:
+      properties:
+        clocks:
+          items:
+            - description: clock input for the SOR hardware
+            - description: SOR output clock
+            - description: input for the pixel clock
+            - description: reference clock for the SOR clock
+            - description: safe reference clock for the SOR clock
+                during power up
+            - description: SOR pad output clock
+
+        clock-names:
+          items:
+            - const: sor
+            - enum:
+                - source # deprecated
+                - out
+            - const: parent
+            - const: dp
+            - const: safe
+            - const: pad
+    else:
+      properties:
+        clocks:
+          items:
+            - description: clock input for the SOR hardware
+            - description: SOR output clock
+            - description: input for the pixel clock
+            - description: reference clock for the SOR clock
+            - description: safe reference clock for the SOR clock
+                during power up
+
+        clock-names:
+          items:
+            - const: sor
+            - enum:
+                - source # deprecated
+                - out
+            - const: parent
+            - const: dp
+            - const: safe
+
+  - if:
+      not:
+        properties:
+          contains:
+            const: nvidia,panel
+    then:
+      required:
+        - hdmi-supply
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - avdd-io-hdmi-dp-supply
+  - vdd-hdmi-dp-pll-supply
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    sor0: sor@54540000 {
+        compatible = "nvidia,tegra210-sor";
+        reg = <0x54540000 0x00040000>;
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+                 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
+                 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
+                 <&tegra_car TEGRA210_CLK_PLL_DP>,
+                 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+        clock-names = "sor", "out", "parent", "dp", "safe";
+        resets = <&tegra_car 182>;
+        reset-names = "sor";
+        pinctrl-0 = <&state_dpaux_aux>;
+        pinctrl-1 = <&state_dpaux_i2c>;
+        pinctrl-2 = <&state_dpaux_off>;
+        pinctrl-names = "aux", "i2c", "off";
+        power-domains = <&pd_sor>;
+
+        avdd-io-hdmi-dp-supply = <&avdd_1v05>;
+        vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
+        hdmi-supply = <&vdd_hdmi>;
+
+        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
new file mode 100644
index 000000000000..37bb5ddc1963
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Image Composer
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^vic@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra124-vic
+          - nvidia,tegra210-vic
+          - nvidia,tegra186-vic
+          - nvidia,tegra194-vic
+
+      - items:
+          - const: nvidia,tegra132-vic
+          - const: nvidia,tegra124-vic
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: clock input for the VIC hardware
+
+  clock-names:
+    items:
+      - const: vic
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: vic
+
+  power-domains:
+    maxItems: 1
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    description: Description of the interconnect paths for the VIC;
+      see ../interconnect/interconnect.txt for details.
+    items:
+      - description: memory read client for VIC
+      - description: memory write client for VIC
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+      - const: write
+
+  dma-coherent: true
+
+additionalProperties: false
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
new file mode 100644
index 000000000000..265a60d79d89
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) Display Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^display@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra186-dc
+      - nvidia,tegra194-dc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: display controller pixel clock
+
+  clock-names:
+    items:
+      - const: dc
+
+  resets:
+    items:
+      - description: display controller reset
+
+  reset-names:
+    items:
+      - const: dc
+
+  power-domains:
+    maxItems: 1
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    description: Description of the interconnect paths for the
+      display controller; see ../interconnect/interconnect.txt
+      for details.
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read-0
+      - const: read-1
+
+  nvidia,outputs:
+    description: A list of phandles of outputs that this display
+      controller can drive.
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  nvidia,head:
+    description: The number of the display controller head. This
+      is used to setup the various types of output to receive
+      video data from the given head.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - nvidia,outputs
+  - nvidia,head
+
+# see nvidia,tegra186-display.yaml for examples
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
new file mode 100644
index 000000000000..8c0231345529
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
@@ -0,0 +1,310 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) Display Hub
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^display-hub@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra186-display
+      - nvidia,tegra194-display
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    items:
+      - description: display hub reset
+      - description: window group 0 reset
+      - description: window group 1 reset
+      - description: window group 2 reset
+      - description: window group 3 reset
+      - description: window group 4 reset
+      - description: window group 5 reset
+
+  reset-names:
+    items:
+      - const: misc
+      - const: wgrp0
+      - const: wgrp1
+      - const: wgrp2
+      - const: wgrp3
+      - const: wgrp4
+      - const: wgrp5
+
+  power-domains:
+    maxItems: 1
+
+  ranges:
+    maxItems: 1
+
+patternProperties:
+  "^display@[0-9a-f]+$":
+    type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra186-display
+    then:
+      properties:
+        clocks:
+          items:
+            - description: display core clock
+            - description: display stream compression clock
+            - description: display hub clock
+
+        clock-names:
+          items:
+            - const: disp
+            - const: dsc
+            - const: hub
+    else:
+      properties:
+        clocks:
+          items:
+            - description: display core clock
+            - description: display hub clock
+
+        clock-names:
+          items:
+            - const: disp
+            - const: hub
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra186-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra186-mc.h>
+    #include <dt-bindings/power/tegra186-powergate.h>
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    display-hub@15200000 {
+        compatible = "nvidia,tegra186-display";
+        reg = <0x15200000 0x00040000>;
+        resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
+                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
+        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+                      "wgrp3", "wgrp4", "wgrp5";
+        clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
+                 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
+                 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
+        clock-names = "disp", "dsc", "hub";
+        status = "disabled";
+
+        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x15200000 0x15200000 0x40000>;
+
+        display@15200000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15200000 0x10000>;
+            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
+            nvidia,head = <0>;
+        };
+
+        display@15210000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15210000 0x10000>;
+            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
+            nvidia,head = <1>;
+        };
+
+        display@15220000 {
+            compatible = "nvidia,tegra186-dc";
+            reg = <0x15220000 0x10000>;
+            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
+
+            nvidia,outputs = <&sor0 &sor1>;
+            nvidia,head = <2>;
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra194-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra194-mc.h>
+    #include <dt-bindings/power/tegra194-powergate.h>
+    #include <dt-bindings/reset/tegra194-reset.h>
+
+    display-hub@15200000 {
+        compatible = "nvidia,tegra194-display";
+        reg = <0x15200000 0x00040000>;
+        resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
+                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
+        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
+                      "wgrp3", "wgrp4", "wgrp5";
+        clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
+                 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
+        clock-names = "disp", "hub";
+        status = "disabled";
+
+        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x15200000 0x15200000 0x40000>;
+
+        display@15200000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15200000 0x10000>;
+            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <0>;
+        };
+
+        display@15210000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15210000 0x10000>;
+            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <1>;
+        };
+
+        display@15220000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15220000 0x10000>;
+            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <2>;
+        };
+
+        display@15230000 {
+            compatible = "nvidia,tegra194-dc";
+            reg = <0x15230000 0x10000>;
+            interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
+            clock-names = "dc";
+            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
+            reset-names = "dc";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
+            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
+                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+            interconnect-names = "dma-mem", "read-1";
+
+            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
+            nvidia,head = <3>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
new file mode 100644
index 000000000000..e5a6145c8c53
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra MIPI DSI pad controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^padctl@[0-9a-f]+$"
+
+  compatible:
+    const: nvidia,tegra186-dsi-padctl
+
+  reg:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dsi
+
+allOf:
+  - $ref: "/schemas/reset/reset.yaml"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    padctl@15880000 {
+        compatible = "nvidia,tegra186-dsi-padctl";
+        reg = <0x15880000 0x10000>;
+        resets = <&bpmp TEGRA186_RESET_DSI>;
+        reset-names = "dsi";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
new file mode 100644
index 000000000000..ac346af663cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Display Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^dc@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-dc
+          - nvidia,tegra30-dc
+          - nvidia,tegra114-dc
+          - nvidia,tegra124-dc
+          - nvidia,tegra210-dc
+
+      - items:
+          - const: nvidia,tegra124-dc
+          - const: nvidia,tegra132-dc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: display controller pixel clock
+      - description: parent clock # optional
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: dc
+      - const: parent # optional
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dc
+
+  interconnect-names: true
+  interconnects: true
+
+  iommus:
+    maxItems: 1
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+  nvidia,head:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The number of the display controller head. This is used to setup the various
+      types of output to receive video data from the given head.
+
+  nvidia,outputs:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: A list of phandles of outputs that this display controller can drive.
+
+  rgb:
+    type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-dc
+              - nvidia,tegra30-dc
+              - nvidia,tegra114-dc
+    then:
+      properties:
+        interconnects:
+          items:
+            - description: window A memory client
+            - description: window B memory client
+            - description: window B memory client (vertical filter)
+            - description: window C memory client
+            - description: cursor memory client
+
+        interconnect-names:
+          items:
+            - const: wina
+            - const: winb
+            - const: winb-vfilter
+            - const: winc
+            - const: cursor
+
+        rgb:
+          description: Each display controller node has a child node, named "rgb", that represents
+            the RGB output associated with the controller.
+          type: object
+          properties:
+            nvidia,ddc-i2c-bus:
+              $ref: /schemas/types.yaml#/definitions/phandle
+              description: phandle of an I2C controller used for DDC EDID probing
+
+            nvidia,hpd-gpio:
+              description: specifies a GPIO used for hotplug detection
+              maxItems: 1
+
+            nvidia,edid:
+              $ref: /schemas/types.yaml#/definitions/uint8-array
+              description: supplies a binary EDID blob
+
+            nvidia,panel:
+              $ref: /schemas/types.yaml#/definitions/phandle
+              description: phandle of a display panel
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra124-dc
+    then:
+      properties:
+        interconnects:
+          minItems: 4
+          items:
+            - description: window A memory client
+            - description: window B memory client
+            - description: window C memory client
+            - description: cursor memory client
+            - description: window D memory client
+            - description: window T memory client
+
+        interconnect-names:
+          minItems: 4
+          items:
+            - const: wina
+            - const: winb
+            - const: winc
+            - const: cursor
+            - const: wind
+            - const: wint
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    dc@54200000 {
+        compatible = "nvidia,tegra20-dc";
+        reg = <0x54200000 0x00040000>;
+        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+        clock-names = "dc";
+        resets = <&tegra_car 27>;
+        reset-names = "dc";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
new file mode 100644
index 000000000000..75546f250ad7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Display Serial Interface
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-dsi
+          - nvidia,tegra30-dsi
+          - nvidia,tegra114-dsi
+          - nvidia,tegra124-dsi
+          - nvidia,tegra210-dsi
+          - nvidia,tegra186-dsi
+
+      - items:
+          - const: nvidia,tegra132-dsi
+          - const: nvidia,tegra124-dsi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  clock-names:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: dsi
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    maxItems: 1
+
+  avdd-dsi-csi-supply:
+    description: phandle of a supply that powers the DSI controller
+
+  nvidia,mipi-calibrate:
+    description: Should contain a phandle and a specifier specifying
+      which pads are used by this DSI output and need to be
+      calibrated. See nvidia,tegra114-mipi.yaml for details.
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,ganged-mode:
+    description: contains a phandle to a second DSI controller to
+      gang up with in order to support up to 8 data lanes
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+allOf:
+  - $ref: "../dsi-controller.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-dsi
+              - nvidia,tegra30-dsi
+    then:
+      properties:
+        clocks:
+          items:
+            - description: DSI module clock
+            - description: input for the pixel clock
+
+        clock-names:
+          items:
+            - const: dsi
+            - const: parent
+    else:
+      properties:
+        clocks:
+          items:
+            - description: DSI module clock
+            - description: low-power module clock
+            - description: input for the pixel clock
+
+        clock-names:
+          items:
+            - const: dsi
+            - const: lp
+            - const: parent
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra186-dsi
+    then:
+      required:
+        - interrupts
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra186-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra186-powergate.h>
+    #include <dt-bindings/reset/tegra186-reset.h>
+
+    dsi@15300000 {
+        compatible = "nvidia,tegra186-dsi";
+        reg = <0x15300000 0x10000>;
+        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&bpmp TEGRA186_CLK_DSI>,
+                 <&bpmp TEGRA186_CLK_DSIA_LP>,
+                 <&bpmp TEGRA186_CLK_PLLD>;
+        clock-names = "dsi", "lp", "parent";
+        resets = <&bpmp TEGRA186_RESET_DSI>;
+        reset-names = "dsi";
+
+        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
new file mode 100644
index 000000000000..0d55e6206b5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Encoder Pre-Processor
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^epp@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-epp
+      - nvidia,tegra30-epp
+      - nvidia,tegra114-epp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: epp
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 4
+
+  interconnect-names:
+    maxItems: 4
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    epp@540c0000 {
+        compatible = "nvidia,tegra20-epp";
+        reg = <0x540c0000 0x00040000>;
+        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_EPP>;
+        resets = <&tegra_car 19>;
+        reset-names = "epp";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
new file mode 100644
index 000000000000..984a0de9b8a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA 2D graphics engine
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^gr2d@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-gr2d
+      - nvidia,tegra30-gr2d
+      - nvidia,tegra114-gr2d
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+      - description: memory client hotflush reset
+
+  reset-names:
+    items:
+      - const: 2d
+      - const: mc
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 4
+
+  interconnect-names:
+    maxItems: 4
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the HEG or core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gr2d@54140000 {
+        compatible = "nvidia,tegra20-gr2d";
+        reg = <0x54140000 0x00040000>;
+        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+        resets = <&tegra_car 21>;
+        reset-names = "2d";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
new file mode 100644
index 000000000000..4177d311899b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA 3D graphics engine
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^gr3d@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-gr3d
+      - nvidia,tegra30-gr3d
+      - nvidia,tegra114-gr3d
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 2
+    maxItems: 4
+
+  reset-names:
+    minItems: 2
+    maxItems: 4
+
+  iommus:
+    minItems: 1
+    maxItems: 2
+
+  interconnects:
+    minItems: 4
+    maxItems: 10
+
+  interconnect-names:
+    minItems: 4
+    maxItems: 10
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    minItems: 1
+    maxItems: 2
+
+  power-domain-names:
+    minItems: 2
+    maxItems: 2
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra20-gr2d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: module clock
+
+        clock-names:
+          items:
+            - const: 3d
+
+        resets:
+          items:
+            - description: module reset
+            - description: memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: mc
+
+        iommus:
+          maxItems: 1
+
+        interconnects:
+          minItems: 4
+          maxItems: 4
+
+        interconnect-names:
+          minItems: 4
+          maxItems: 4
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra30-gr3d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: primary module clock
+            - description: secondary module clock
+
+        clock-names:
+          items:
+            - const: 3d
+            - const: 3d2
+
+        resets:
+          items:
+            - description: primary module reset
+            - description: secondary module reset
+            - description: primary memory client hotflush reset
+            - description: secondary memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: 3d2
+            - const: mc
+            - const: mc2
+
+        iommus:
+          minItems: 2
+          maxItems: 2
+
+        interconnects:
+          minItems: 8
+          maxItems: 8
+
+        interconnect-names:
+          minItems: 8
+          maxItems: 8
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+            - description: phandle to the TD2 power domain
+
+        power-domain-names:
+          items:
+            - const: 3d0
+            - const: 3d1
+
+      dependencies:
+        power-domains: [ power-domain-names ]
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra114-gr2d
+    then:
+      properties:
+        clocks:
+          items:
+            - description: module clock
+
+        clock-names:
+          items:
+            - const: 3d
+
+        resets:
+          items:
+            - description: module reset
+            - description: memory client hotflush reset
+
+        reset-names:
+          items:
+            - const: 3d
+            - const: mc
+
+        iommus:
+          maxItems: 1
+
+        interconnects:
+          minItems: 10
+          maxItems: 10
+
+        interconnect-names:
+          minItems: 10
+          maxItems: 10
+
+        power-domains:
+          items:
+            - description: phandle to the TD power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+
+    gr3d@54180000 {
+        compatible = "nvidia,tegra20-gr3d";
+        reg = <0x54180000 0x00040000>;
+        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+        resets = <&tegra_car 24>;
+        reset-names = "3d";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
new file mode 100644
index 000000000000..035b9f1f2eb5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra HDMI Output Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^hdmi@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-hdmi
+          - nvidia,tegra30-hdmi
+          - nvidia,tegra114-hdmi
+          - nvidia,tegra124-hdmi
+
+      - items:
+          - const: nvidia,tegra132-hdmi
+          - const: nvidia,tegra124-hdmi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+      - description: parent clock
+
+  clock-names:
+    items:
+      - const: hdmi
+      - const: parent
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: hdmi
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+  hdmi-supply:
+    description: supply for the +5V HDMI connector pin
+
+  vdd-supply:
+    description: regulator for supply voltage
+
+  pll-supply:
+    description: regulator for PLL
+
+  nvidia,ddc-i2c-bus:
+    description: phandle of an I2C controller used for DDC EDID
+      probing
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  nvidia,hpd-gpio:
+    description: specifies a GPIO used for hotplug detection
+    maxItems: 1
+
+  nvidia,edid:
+    description: supplies a binary EDID blob
+    $ref: "/schemas/types.yaml#/definitions/uint8-array"
+
+  nvidia,panel:
+    description: phandle of a display panel
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  "#sound-dai-cells":
+    const: 0
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - pll-supply
+  - vdd-supply
+  - nvidia,ddc-i2c-bus
+  - nvidia,hpd-gpio
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra124-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+
+    hdmi@54280000 {
+        compatible = "nvidia,tegra124-hdmi";
+        reg = <0x54280000 0x00040000>;
+        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA124_CLK_HDMI>,
+                 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
+        clock-names = "hdmi", "parent";
+        resets = <&tegra_car 51>;
+        reset-names = "hdmi";
+
+        hdmi-supply = <&vdd_5v0_hdmi>;
+        pll-supply = <&vdd_hdmi_pll>;
+        vdd-supply = <&vdd_3v3_hdmi>;
+
+        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
deleted file mode 100644
index e61999ce54e9..000000000000
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ /dev/null
@@ -1,675 +0,0 @@
-NVIDIA Tegra host1x
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-host1x"
-- reg: Physical base address and length of the controller's registers.
-  For pre-Tegra186, one entry describing the whole register area.
-  For Tegra186, one entry for each entry in reg-names:
-    "vm" - VM region assigned to Linux
-    "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
-- interrupts: The interrupt outputs from the controller.
-- #address-cells: The number of cells used to represent physical base addresses
-  in the host1x address space. Should be 1.
-- #size-cells: The number of cells used to represent the size of an address
-  range in the host1x address space. Should be 1.
-- ranges: The mapping of the host1x address space to the CPU address space.
-- clocks: Must contain one entry, for the module clock.
-  See ../clocks/clock-bindings.txt for details.
-- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
-  - host1x
-  - mc
-
-Optional properties:
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-For each opp entry in 'operating-points-v2' table of host1x and its modules:
-- opp-supported-hw: One bitfield indicating:
-	On Tegra20: SoC process ID mask
-	On Tegra30+: SoC speedo ID mask
-
-	A bitwise AND is performed against the value and if any bit
-	matches, the OPP gets enabled.
-
-Each host1x client module having to perform DMA through the Memory Controller
-should have the interconnect endpoints set to the Memory Client and External
-Memory respectively.
-
-The host1x top-level node defines a number of children, each representing one
-of the following host1x client modules:
-
-- mpe: video encoder
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-mpe"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - mpe
-
-  Optional properties:
-  - interconnects: Must contain entry for the MPE memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to MPE power domain.
-
-- vi: video input
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-vi"
-  - reg: Physical base address and length of the controller registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - Tegra20/Tegra30/Tegra114/Tegra124:
-    - resets: Must contain an entry for each entry in reset-names.
-      See ../reset/reset.txt for details.
-    - reset-names: Must include the following entries:
-      - vi
-  - Tegra210:
-    - power-domains: Must include venc powergate node as vi is in VE partition.
-
-  ports (optional node)
-  vi can have optional ports node and max 6 ports are supported. Each port
-  should have single 'endpoint' child node. All port nodes are grouped under
-  ports node. Please refer to the bindings defined in
-  Documentation/devicetree/bindings/media/video-interfaces.txt
-
-  csi (required node)
-  Tegra210 has CSI part of VI sharing same host interface and register space.
-  So, VI device node should have CSI child node.
-
-    - csi: mipi csi interface to vi
-
-      Required properties:
-      - compatible: "nvidia,tegra210-csi"
-      - reg: Physical base address offset to parent and length of the controller
-        registers.
-      - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
-        See ../clocks/clock-bindings.txt for details.
-      - power-domains: Must include sor powergate node as csicil is in
-        SOR partition.
-
-      channel (optional nodes)
-      Maximum 6 channels are supported with each csi brick as either x4 or x2
-      based on hw connectivity to sensor.
-
-      Required properties:
-      - reg: csi port number. Valid port numbers are 0 through 5.
-      - nvidia,mipi-calibrate: Should contain a phandle and a specifier
-        specifying which pads are used by this CSI port and need to be
-	calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
-
-      Each channel node must contain 2 port nodes which can be grouped
-      under 'ports' node and each port should have a single child 'endpoint'
-      node.
-
-        ports node
-        Please refer to the bindings defined in
-        Documentation/devicetree/bindings/media/video-interfaces.txt
-
-        ports node must contain below 2 port nodes.
-        port@0 with single child 'endpoint' node always a sink.
-        port@1 with single child 'endpoint' node always a source.
-
-        port@0 (required node)
-        Required properties:
-        - reg: 0
-
-	  endpoint (required node)
-	  Required properties:
-	  - data-lanes: an array of data lane from 1 to 8. Valid array
-	    lengths are 1/2/4/8.
-	  - remote-endpoint: phandle to sensor 'endpoint' node.
-
-        port@1 (required node)
-        Required properties:
-        - reg: 1
-
-	  endpoint (required node)
-	  Required properties:
-	  - remote-endpoint: phandle to vi port 'endpoint' node.
-
-  Optional properties:
-  - interconnects: Must contain entry for the VI memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to VENC power domain.
-
-- epp: encoder pre-processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-epp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - epp
-
-  Optional properties:
-  - interconnects: Must contain entry for the EPP memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-- isp: image signal processor
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-isp"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - isp
-
-  Optional properties:
-  - interconnects: Must contain entry for the ISP memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - power-domains: Phandle to VENC or core power domain.
-
-- gr2d: 2D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr2d"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - 2d
-    - mc
-
-  Optional properties:
-  - interconnects: Must contain entry for the GR2D memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to HEG or core power domain.
-
-- gr3d: 3D graphics engine
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-gr3d"
-  - reg: Physical base address and length of the controller's registers.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    (This property may be omitted if the only clock in the list is "3d")
-    - 3d
-      This MUST be the first entry.
-    - 3d2 (Only required on SoCs with two 3D clocks)
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - 3d
-    - 3d2 (Only required on SoCs with two 3D clocks)
-    - mc
-    - mc2 (Only required on SoCs with two 3D clocks)
-
-  Optional properties:
-  - interconnects: Must contain entry for the GR3D memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandles to 3D or core power domain.
-
-- dc: display controller
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dc"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dc
-      This MUST be the first entry.
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dc
-  - nvidia,head: The number of the display controller head. This is used to
-    setup the various types of output to receive video data from the given
-    head.
-
-  Each display controller node has a child node, named "rgb", that represents
-  the RGB output associated with the controller. It can take the following
-  optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - interconnects: Must contain entry for the DC memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to core power domain.
-
-- hdmi: High Definition Multimedia Interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-hdmi"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - hdmi-supply: supply for the +5V HDMI connector pin
-  - vdd-supply: regulator for supply voltage
-  - pll-supply: regulator for PLL
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - hdmi
-      This MUST be the first entry.
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - hdmi
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-- tvo: TV encoder output
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-tvo"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain one entry, for the module clock.
-    See ../clocks/clock-bindings.txt for details.
-
-  Optional properties:
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-  - power-domains: Phandle to core power domain.
-
-- dsi: display serial interface
-
-  Required properties:
-  - compatible: "nvidia,tegra<chip>-dsi"
-  - reg: Physical base address and length of the controller's registers.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dsi
-      This MUST be the first entry.
-    - lp
-    - parent
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dsi
-  - avdd-dsi-supply: phandle of a supply that powers the DSI controller
-  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
-    which pads are used by this DSI output and need to be calibrated. See also
-    ../display/tegra/nvidia,tegra114-mipi.txt.
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
-    up with in order to support up to 8 data lanes
-  - operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-- sor: serial output resource
-
-  Required properties:
-  - compatible: Should be:
-    - "nvidia,tegra124-sor": for Tegra124 and Tegra132
-    - "nvidia,tegra132-sor": for Tegra132
-    - "nvidia,tegra210-sor": for Tegra210
-    - "nvidia,tegra210-sor1": for Tegra210
-    - "nvidia,tegra186-sor": for Tegra186
-    - "nvidia,tegra186-sor1": for Tegra186
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - sor: clock input for the SOR hardware
-    - out: SOR output clock
-    - parent: input for the pixel clock
-    - dp: reference clock for the SOR clock
-    - safe: safe reference for the SOR clock during power up
-
-    For Tegra186 and later:
-    - pad: SOR pad output clock (on Tegra186 and later)
-
-    Obsolete:
-    - source: source clock for the SOR clock (obsolete, use "out" instead)
-
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - sor
-
-  Required properties on Tegra186 and later:
-  - nvidia,interface: index of the SOR interface
-
-  Optional properties:
-  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
-  - nvidia,edid: supplies a binary EDID blob
-  - nvidia,panel: phandle of a display panel
-  - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
-    of the SOR, identified by the cell's index, is mapped via the crossbar to
-    the pad specified by the cell's value.
-
-  Optional properties when driving an eDP output:
-  - nvidia,dpaux: phandle to a DispayPort AUX interface
-
-- dpaux: DisplayPort AUX interface
-  - compatible : Should contain one of the following:
-    - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
-    - "nvidia,tegra210-dpaux": for Tegra210
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - dpaux: clock input for the DPAUX hardware
-    - parent: reference clock
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - dpaux
-  - vdd-supply: phandle of a supply that powers the DisplayPort link
-  - i2c-bus: Subnode where I2C slave devices are listed. This subnode
-    must be always present. If there are no I2C slave devices, an empty
-    node should be added. See ../../i2c/i2c.txt for more information.
-
-  See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
-  regarding the DPAUX pad controller bindings.
-
-- vic: Video Image Compositor
-  - compatible : "nvidia,tegra<chip>-vic"
-  - reg: Physical base address and length of the controller's registers.
-  - interrupts: The interrupt outputs from the controller.
-  - clocks: Must contain an entry for each entry in clock-names.
-    See ../clocks/clock-bindings.txt for details.
-  - clock-names: Must include the following entries:
-    - vic: clock input for the VIC hardware
-  - resets: Must contain an entry for each entry in reset-names.
-    See ../reset/reset.txt for details.
-  - reset-names: Must include the following entries:
-    - vic
-
-  Optional properties:
-  - interconnects: Must contain entry for the VIC memory clients.
-  - interconnect-names: Must include name of the interconnect path for each
-    interconnect entry. Consult TRM documentation for information about
-    available memory clients, see MEMORY CONTROLLER section.
-
-Example:
-
-/ {
-	...
-
-	host1x {
-		compatible = "nvidia,tegra20-host1x", "simple-bus";
-		reg = <0x50000000 0x00024000>;
-		interrupts = <0 65 0x04   /* mpcore syncpt */
-			      0 67 0x04>; /* mpcore general */
-		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
-		resets = <&tegra_car 28>;
-		reset-names = "host1x";
-		operating-points-v2 = <&dvfs_opp_table>;
-		power-domains = <&domain>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		ranges = <0x54000000 0x54000000 0x04000000>;
-
-		mpe {
-			compatible = "nvidia,tegra20-mpe";
-			reg = <0x54040000 0x00040000>;
-			interrupts = <0 68 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_MPE>;
-			resets = <&tegra_car 60>;
-			reset-names = "mpe";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		vi@54080000 {
-			compatible = "nvidia,tegra210-vi";
-			reg = <0x0 0x54080000 0x0 0x700>;
-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
-			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
-			operating-points-v2 = <&dvfs_opp_table>;
-
-			clocks = <&tegra_car TEGRA210_CLK_VI>;
-			power-domains = <&pd_venc>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ranges = <0x0 0x0 0x54080000 0x2000>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					imx219_vi_in0: endpoint {
-						remote-endpoint = <&imx219_csi_out0>;
-					};
-				};
-			};
-
-			csi@838 {
-				compatible = "nvidia,tegra210-csi";
-				reg = <0x838 0x1300>;
-				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
-						  <&tegra_car TEGRA210_CLK_CILCD>,
-						  <&tegra_car TEGRA210_CLK_CILE>,
-						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
-				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
-							 <&tegra_car TEGRA210_CLK_PLL_P>,
-							 <&tegra_car TEGRA210_CLK_PLL_P>;
-				assigned-clock-rates = <102000000>,
-						       <102000000>,
-						       <102000000>,
-						       <972000000>;
-
-				clocks = <&tegra_car TEGRA210_CLK_CSI>,
-					 <&tegra_car TEGRA210_CLK_CILAB>,
-					 <&tegra_car TEGRA210_CLK_CILCD>,
-					 <&tegra_car TEGRA210_CLK_CILE>,
-					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
-				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
-				power-domains = <&pd_sor>;
-
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				channel@0 {
-					reg = <0>;
-					nvidia,mipi-calibrate = <&mipi 0x001>;
-
-					ports {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						port@0 {
-							reg = <0>;
-							imx219_csi_in0: endpoint {
-								data-lanes = <1 2>;
-								remote-endpoint = <&imx219_out0>;
-							};
-						};
-
-						port@1 {
-							reg = <1>;
-							imx219_csi_out0: endpoint {
-								remote-endpoint = <&imx219_vi_in0>;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		epp {
-			compatible = "nvidia,tegra20-epp";
-			reg = <0x540c0000 0x00040000>;
-			interrupts = <0 70 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_EPP>;
-			resets = <&tegra_car 19>;
-			reset-names = "epp";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		isp {
-			compatible = "nvidia,tegra20-isp";
-			reg = <0x54100000 0x00040000>;
-			interrupts = <0 71 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_ISP>;
-			resets = <&tegra_car 23>;
-			reset-names = "isp";
-		};
-
-		gr2d {
-			compatible = "nvidia,tegra20-gr2d";
-			reg = <0x54140000 0x00040000>;
-			interrupts = <0 72 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
-			resets = <&tegra_car 21>;
-			reset-names = "2d";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		gr3d {
-			compatible = "nvidia,tegra20-gr3d";
-			reg = <0x54180000 0x00040000>;
-			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
-			resets = <&tegra_car 24>;
-			reset-names = "3d";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-		};
-
-		dc@54200000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54200000 0x00040000>;
-			interrupts = <0 73 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
-				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 27>;
-			reset-names = "dc";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-
-			interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
-					<&mc TEGRA20_MC_DISPLAY0B &emc>,
-					<&mc TEGRA20_MC_DISPLAY0C &emc>,
-					<&mc TEGRA20_MC_DISPLAYHC &emc>;
-			interconnect-names = "wina",
-					     "winb",
-					     "winc",
-					     "cursor";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		dc@54240000 {
-			compatible = "nvidia,tegra20-dc";
-			reg = <0x54240000 0x00040000>;
-			interrupts = <0 74 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
-				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "dc", "parent";
-			resets = <&tegra_car 26>;
-			reset-names = "dc";
-			operating-points-v2 = <&dvfs_opp_table>;
-			power-domains = <&domain>;
-
-			interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
-					<&mc TEGRA20_MC_DISPLAY0BB &emc>,
-					<&mc TEGRA20_MC_DISPLAY0CB &emc>,
-					<&mc TEGRA20_MC_DISPLAYHCB &emc>;
-			interconnect-names = "wina",
-					     "winb",
-					     "winc",
-					     "cursor";
-
-			rgb {
-				status = "disabled";
-			};
-		};
-
-		hdmi {
-			compatible = "nvidia,tegra20-hdmi";
-			reg = <0x54280000 0x00040000>;
-			interrupts = <0 75 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
-				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
-			clock-names = "hdmi", "parent";
-			resets = <&tegra_car 51>;
-			reset-names = "hdmi";
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-
-		tvo {
-			compatible = "nvidia,tegra20-tvo";
-			reg = <0x542c0000 0x00040000>;
-			interrupts = <0 76 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_TVO>;
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-
-		dsi {
-			compatible = "nvidia,tegra20-dsi";
-			reg = <0x54300000 0x00040000>;
-			clocks = <&tegra_car TEGRA20_CLK_DSI>,
-				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
-			clock-names = "dsi", "parent";
-			resets = <&tegra_car 48>;
-			reset-names = "dsi";
-			status = "disabled";
-			operating-points-v2 = <&dvfs_opp_table>;
-		};
-	};
-
-	...
-};
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
new file mode 100644
index 000000000000..4fd513efb0f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -0,0 +1,347 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra host1x controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description: The host1x top-level node defines a number of children, each
+  representing one of the host1x client modules defined in this binding.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nvidia,tegra20-host1x
+          - nvidia,tegra30-host1x
+          - nvidia,tegra114-host1x
+          - nvidia,tegra124-host1x
+          - nvidia,tegra210-host1x
+          - nvidia,tegra186-host1x
+          - nvidia,tegra194-host1x
+
+      - items:
+          - const: nvidia,tegra132-host1x
+          - const: nvidia,tegra124-host1x
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
+
+  interrupts:
+    items:
+      - description: host1x syncpoint interrupt
+      - description: host1x general interrupt
+    minItems: 1
+
+  interrupt-names:
+    items:
+      - const: syncpt
+      - const: host1x
+    minItems: 1
+
+  '#address-cells':
+    description: The number of cells used to represent physical base addresses
+      in the host1x address space.
+    enum: [1, 2]
+
+  '#size-cells':
+    description: The number of cells used to represent the size of an address
+      range in the host1x address space.
+    enum: [1, 2]
+
+  ranges:
+    maxItems: 1
+
+  clocks:
+    description: Must contain one entry, for the module clock. See
+      ../clocks/clock-bindings.txt for details.
+
+  clock-names:
+    items:
+      - const: host1x
+
+  resets:
+    minItems: 1 # MC reset is optional on Tegra186 and later
+    items:
+      - description: module reset
+      - description: memory client hotflush reset
+
+  reset-names:
+    minItems: 1 # MC reset is optional on Tegra186 and later
+    items:
+      - const: host1x
+      - const: mc
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    items:
+      - description: memory read client for host1x
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the HEG or core power domain
+
+required:
+  - compatible
+  - interrupts
+  - interrupt-names
+  - '#address-cells'
+  - '#size-cells'
+  - ranges
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+additionalProperties:
+  type: object
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-host1x
+              - nvidia,tegra194-host1x
+    then:
+      properties:
+        reg-names:
+          items:
+            - const: hypervisor
+            - const: vm
+
+        reg:
+          items:
+            - description: physical base address and length of the register
+                region assigned to the VM
+            - description: physical base address and length of the register
+                region used by the hypervisor
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          maxItems: 1
+
+      required:
+        - reg-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+
+    host1x@50000000 {
+        compatible = "nvidia,tegra20-host1x";
+        reg = <0x50000000 0x00024000>;
+        interrupts = <0 65 0x04   /* mpcore syncpt */
+                      0 67 0x04>; /* mpcore general */
+        interrupt-names = "syncpt", "host1x";
+        clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+        clock-names = "host1x";
+        resets = <&tegra_car 28>;
+        reset-names = "host1x";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x54000000 0x54000000 0x04000000>;
+
+        mpe@54040000 {
+            compatible = "nvidia,tegra20-mpe";
+            reg = <0x54040000 0x00040000>;
+            interrupts = <0 68 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_MPE>;
+            resets = <&tegra_car 60>;
+            reset-names = "mpe";
+        };
+
+        vi@54080000 {
+            compatible = "nvidia,tegra20-vi";
+            reg = <0x54080000 0x00040000>;
+            interrupts = <0 69 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_VI>;
+            resets = <&tegra_car 100>;
+            reset-names = "vi";
+        };
+
+        epp@540c0000 {
+            compatible = "nvidia,tegra20-epp";
+            reg = <0x540c0000 0x00040000>;
+            interrupts = <0 70 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_EPP>;
+            resets = <&tegra_car 19>;
+            reset-names = "epp";
+        };
+
+        isp@54100000 {
+            compatible = "nvidia,tegra20-isp";
+            reg = <0x54100000 0x00040000>;
+            interrupts = <0 71 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_ISP>;
+            resets = <&tegra_car 23>;
+            reset-names = "isp";
+        };
+
+        gr2d@54140000 {
+            compatible = "nvidia,tegra20-gr2d";
+            reg = <0x54140000 0x00040000>;
+            interrupts = <0 72 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+            resets = <&tegra_car 21>;
+            reset-names = "2d";
+        };
+
+        gr3d@54180000 {
+            compatible = "nvidia,tegra20-gr3d";
+            reg = <0x54180000 0x00040000>;
+            clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+            resets = <&tegra_car 24>;
+            reset-names = "3d";
+        };
+
+        dc@54200000 {
+            compatible = "nvidia,tegra20-dc";
+            reg = <0x54200000 0x00040000>;
+            interrupts = <0 73 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+            clock-names = "dc";
+            resets = <&tegra_car 27>;
+            reset-names = "dc";
+
+            rgb {
+            };
+        };
+
+        dc@54240000 {
+            compatible = "nvidia,tegra20-dc";
+            reg = <0x54240000 0x00040000>;
+            interrupts = <0 74 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_DISP2>;
+            clock-names = "dc";
+            resets = <&tegra_car 26>;
+            reset-names = "dc";
+
+            rgb {
+            };
+        };
+
+        hdmi@54280000 {
+            compatible = "nvidia,tegra20-hdmi";
+            reg = <0x54280000 0x00040000>;
+            interrupts = <0 75 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+            clock-names = "hdmi", "parent";
+            resets = <&tegra_car 51>;
+            reset-names = "hdmi";
+
+            hdmi-supply = <&vdd_5v0_hdmi>;
+            pll-supply = <&vdd_hdmi_pll>;
+            vdd-supply = <&vdd_3v3_hdmi>;
+
+            nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+            nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+        };
+
+        tvo@542c0000 {
+            compatible = "nvidia,tegra20-tvo";
+            reg = <0x542c0000 0x00040000>;
+            interrupts = <0 76 0x04>;
+            clocks = <&tegra_car TEGRA20_CLK_TVO>;
+        };
+
+        dsi@54300000 {
+            compatible = "nvidia,tegra20-dsi";
+            reg = <0x54300000 0x00040000>;
+            clocks = <&tegra_car TEGRA20_CLK_DSI>,
+                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+            clock-names = "dsi", "parent";
+            resets = <&tegra_car 48>;
+            reset-names = "dsi";
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/memory/tegra210-mc.h>
+
+    host1x@50000000 {
+        compatible = "nvidia,tegra210-host1x";
+        reg = <0x50000000 0x00024000>;
+        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
+                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
+        interrupt-names = "syncpt", "host1x";
+        clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
+        clock-names = "host1x";
+        resets = <&tegra_car 28>;
+        reset-names = "host1x";
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x54000000 0x54000000 0x01000000>;
+        iommus = <&mc TEGRA_SWGROUP_HC>;
+
+        vi@54080000 {
+            compatible = "nvidia,tegra210-vi";
+            reg = <0x54080000 0x00000700>;
+            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+            assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+            clocks = <&tegra_car TEGRA210_CLK_VI>;
+            power-domains = <&pd_venc>;
+
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            ranges = <0x0 0x54080000 0x2000>;
+
+            csi@838 {
+                compatible = "nvidia,tegra210-csi";
+                reg = <0x838 0x1300>;
+                assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+                                  <&tegra_car TEGRA210_CLK_CILCD>,
+                                  <&tegra_car TEGRA210_CLK_CILE>,
+                                  <&tegra_car TEGRA210_CLK_CSI_TPG>;
+                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+                                         <&tegra_car TEGRA210_CLK_PLL_P>,
+                                         <&tegra_car TEGRA210_CLK_PLL_P>;
+                assigned-clock-rates = <102000000>,
+                                       <102000000>,
+                                       <102000000>,
+                                       <972000000>;
+
+                clocks = <&tegra_car TEGRA210_CLK_CSI>,
+                         <&tegra_car TEGRA210_CLK_CILAB>,
+                         <&tegra_car TEGRA210_CLK_CILCD>,
+                         <&tegra_car TEGRA210_CLK_CILE>,
+                         <&tegra_car TEGRA210_CLK_CSI_TPG>;
+                clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+                power-domains = <&pd_sor>;
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
new file mode 100644
index 000000000000..3bc3b22e98e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra ISP processor
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    enum:
+      - nvidia,tegra20-isp
+      - nvidia,tegra30-isp
+      - nvidia,tegra210-isp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: isp
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    items:
+      - description: memory write client
+
+  interconnect-names:
+    items:
+      - const: dma-mem # write
+
+  power-domains:
+    items:
+      - description: phandle to the VENC or core power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    isp@54100000 {
+        compatible = "nvidia,tegra20-isp";
+        reg = <0x54100000 0x00040000>;
+        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_ISP>;
+        resets = <&tegra_car 23>;
+        reset-names = "isp";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
new file mode 100644
index 000000000000..4154ae01ad13
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Encoder
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^mpe@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-mpe
+      - nvidia,tegra30-mpe
+      - nvidia,tegra114-mpe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: mpe
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    minItems: 6
+    maxItems: 6
+
+  interconnect-names:
+    minItems: 6
+    maxItems: 6
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the MPE power domain
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mpe@54040000 {
+        compatible = "nvidia,tegra20-mpe";
+        reg = <0x54040000 0x00040000>;
+        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_MPE>;
+        resets = <&tegra_car 60>;
+        reset-names = "mpe";
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
new file mode 100644
index 000000000000..467b015e5700
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra TV Encoder Output
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^tvo@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra20-tvo
+      - nvidia,tegra30-tvo
+      - nvidia,tegra114-tvo
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tvo@542c0000 {
+        compatible = "nvidia,tegra20-tvo";
+        reg = <0x542c0000 0x00040000>;
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_TVO>;
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
new file mode 100644
index 000000000000..782a4b10150a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Video Input controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^vi@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - const: nvidia,tegra20-vi
+      - const: nvidia,tegra30-vi
+      - const: nvidia,tegra114-vi
+      - const: nvidia,tegra124-vi
+      - items:
+          - const: nvidia,tegra132-vi
+          - const: nvidia,tegra124-vi
+      - const: nvidia,tegra210-vi
+      - const: nvidia,tegra186-vi
+      - const: nvidia,tegra194-vi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: vi
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    minItems: 4
+    maxItems: 5
+
+  interconnect-names:
+    minItems: 4
+    maxItems: 5
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the VENC power domain
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges:
+    maxItems: 1
+
+  avdd-dsi-csi-supply:
+    description: DSI/CSI power supply. Must supply 1.2 V.
+
+patternProperties:
+  "^csi@[0-9a-f]+$":
+    type: object
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra20-vi
+              - nvidia,tegra30-vi
+              - nvidia,tegra114-vi
+              - nvidia,tegra124-vi
+    then:
+      required:
+        - resets
+        - reset-names
+    else:
+      required:
+        - power-domains
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vi@54080000 {
+        compatible = "nvidia,tegra20-vi";
+        reg = <0x54080000 0x00040000>;
+        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&tegra_car TEGRA20_CLK_VI>;
+        resets = <&tegra_car 100>;
+        reset-names = "vi";
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra210-car.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vi@54080000 {
+        compatible = "nvidia,tegra210-vi";
+        reg = <0x54080000 0x00000700>;
+        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+        clocks = <&tegra_car TEGRA210_CLK_VI>;
+        power-domains = <&pd_venc>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ranges = <0x0 0x54080000 0x2000>;
+
+        csi@838 {
+            compatible = "nvidia,tegra210-csi";
+            reg = <0x838 0x1300>;
+            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+                              <&tegra_car TEGRA210_CLK_CILCD>,
+                              <&tegra_car TEGRA210_CLK_CILE>,
+                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
+            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+                                     <&tegra_car TEGRA210_CLK_PLL_P>,
+                                     <&tegra_car TEGRA210_CLK_PLL_P>;
+            assigned-clock-rates = <102000000>,
+                                   <102000000>,
+                                   <102000000>,
+                                   <972000000>;
+
+            clocks = <&tegra_car TEGRA210_CLK_CSI>,
+                     <&tegra_car TEGRA210_CLK_CILAB>,
+                     <&tegra_car TEGRA210_CLK_CILCD>,
+                     <&tegra_car TEGRA210_CLK_CILE>,
+                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
+            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+            power-domains = <&pd_sor>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
new file mode 100644
index 000000000000..fa07a40d1004
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra CSI controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^csi@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra210-csi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+      - description: A/B lanes clock
+      - description: C/D lanes clock
+      - description: E lane clock
+      - description: test pattern generator clock
+
+  clock-names:
+    items:
+      - const: csi
+      - const: cilab
+      - const: cilcd
+      - const: cile
+      - const: csi_tpg
+
+  power-domains:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+# see nvidia,tegra20-vi.yaml for an example
diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Documentation/devicetree/bindings/dma/apple,admac.yaml
new file mode 100644
index 000000000000..bdc8c129c4f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/apple,admac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple Audio DMA Controller (ADMAC)
+
+description: |
+  Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
+  on SoCs from the "Apple Silicon" family.
+
+  The controller has been seen with up to 24 channels. Even-numbered channels
+  are TX-only, odd-numbered are RX-only. Individual channels are coupled to
+  fixed device endpoints.
+
+maintainers:
+  - Martin Povišer <povik+lin@cutebit.org>
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - apple,t6000-admac
+          - apple,t8103-admac
+      - const: apple,admac
+
+  reg:
+    maxItems: 1
+
+  '#dma-cells':
+    const: 1
+    description:
+      Clients specify a single cell with channel number.
+
+  dma-channels:
+    maximum: 24
+
+  interrupts:
+    minItems: 4
+    maxItems: 4
+    description:
+      Interrupts that correspond to the 4 IRQ outputs of the controller. Usually
+      only one of the controller outputs will be connected as an usable interrupt
+      source. The remaining interrupts will be left without a valid value, e.g.
+      in an interrupts-extended list the disconnected positions will contain
+      an empty phandle reference <0>.
+
+required:
+  - compatible
+  - reg
+  - '#dma-cells'
+  - dma-channels
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/apple-aic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    aic: interrupt-controller {
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+
+    admac: dma-controller@238200000 {
+      compatible = "apple,t8103-admac", "apple,admac";
+      reg = <0x38200000 0x34000>;
+      dma-channels = <24>;
+      interrupts-extended = <0>,
+                            <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
+                            <0>,
+                            <0>;
+      #dma-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
index 54d68fc688b5..19ea8dcbcbce 100644
--- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
@@ -22,6 +22,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt2712-uart-dma
+              - mediatek,mt8365-uart-dma
               - mediatek,mt8516-uart-dma
           - const: mediatek,mt6577-uart-dma
       - enum:
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
deleted file mode 100644
index 99ab5c4d331e..000000000000
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-* DMA40 DMA Controller
-
-Required properties:
-- compatible: "stericsson,dma40"
-- reg: Address range of the DMAC registers
-- reg-names: Names of the above areas to use during resource look-up
-- interrupt: Should contain the DMAC interrupt number
-- #dma-cells: must be <3>
-- memcpy-channels: Channels to be used for memcpy
-
-Optional properties:
-- dma-channels: Number of channels supported by hardware - if not present
-		the driver will attempt to obtain the information from H/W
-- disabled-channels: Channels which can not be used
-
-Example:
-
-	dma: dma-controller@801c0000 {
-		compatible = "stericsson,db8500-dma40", "stericsson,dma40";
-		reg = <0x801C0000 0x1000  0x40010000 0x800>;
-		reg-names = "base", "lcpa";
-		interrupt-parent = <&intc>;
-		interrupts = <0 25 0x4>;
-
-		#dma-cells = <2>;
-		memcpy-channels  = <56 57 58 59 60>;
-		disabled-channels  = <12>;
-		dma-channels = <8>;
-	};
-
-Clients
-Required properties:
-- dmas: Comma separated list of dma channel requests
-- dma-names: Names of the aforementioned requested channels
-
-Each dmas request consists of 4 cells:
-  1. A phandle pointing to the DMA controller
-  2. Device signal number, the signal line for single and burst requests
-     connected from the device to the DMA40 engine
-  3. The DMA request line number (only when 'use fixed channel' is set)
-  4. A 32bit mask specifying; mode, direction and endianness
-     [NB: This list will grow]
-        0x00000001: Mode:
-                Logical channel when unset
-                Physical channel when set
-        0x00000002: Direction:
-                Memory to Device when unset
-                Device to Memory when set
-        0x00000004: Endianness:
-                Little endian when unset
-                Big endian when set
-        0x00000008: Use fixed channel:
-                Use automatic channel selection when unset
-                Use DMA request line number when set
-        0x00000010: Set channel as high priority:
-                Normal priority when unset
-                High priority when set
-
-Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
-bidirectional, i.e. the same for RX and TX operations:
-
-0:  SPI controller 0
-1:  SD/MMC controller 0 (unused)
-2:  SD/MMC controller 1 (unused)
-3:  SD/MMC controller 2 (unused)
-4:  I2C port 1
-5:  I2C port 3
-6:  I2C port 2
-7:  I2C port 4
-8:  Synchronous Serial Port SSP0
-9:  Synchronous Serial Port SSP1
-10: Multi-Channel Display Engine MCDE RX
-11: UART port 2
-12: UART port 1
-13: UART port 0
-14: Multirate Serial Port MSP2
-15: I2C port 0
-16: USB OTG in/out endpoints 7 & 15
-17: USB OTG in/out endpoints 6 & 14
-18: USB OTG in/out endpoints 5 & 13
-19: USB OTG in/out endpoints 4 & 12
-20: SLIMbus or HSI channel 0
-21: SLIMbus or HSI channel 1
-22: SLIMbus or HSI channel 2
-23: SLIMbus or HSI channel 3
-24: Multimedia DSP SXA0
-25: Multimedia DSP SXA1
-26: Multimedia DSP SXA2
-27: Multimedia DSP SXA3
-28: SD/MM controller 2
-29: SD/MM controller 0
-30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
-31: MSP port 0 or SLIMbus channel 0
-32: SD/MM controller 1
-33: SPI controller 2
-34: i2c3 RX2 TX2
-35: SPI controller 1
-36: USB OTG in/out endpoints 3 & 11
-37: USB OTG in/out endpoints 2 & 10
-38: USB OTG in/out endpoints 1 & 9
-39: USB OTG in/out endpoints 8
-40: SPI controller 3
-41: SD/MM controller 3
-42: SD/MM controller 4
-43: SD/MM controller 5
-44: Multimedia DSP SXA4
-45: Multimedia DSP SXA5
-46: SLIMbus channel 8 or Multimedia DSP SXA6
-47: SLIMbus channel 9 or Multimedia DSP SXA7
-48: Crypto Accelerator 1
-49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
-50: Hash Accelerator 1 TX
-51: memcpy TX (to be used by the DMA driver for memcpy operations)
-52: SLIMbus or HSI channel 4
-53: SLIMbus or HSI channel 5
-54: SLIMbus or HSI channel 6
-55: SLIMbus or HSI channel 7
-56: memcpy (to be used by the DMA driver for memcpy operations)
-57: memcpy (to be used by the DMA driver for memcpy operations)
-58: memcpy (to be used by the DMA driver for memcpy operations)
-59: memcpy (to be used by the DMA driver for memcpy operations)
-60: memcpy (to be used by the DMA driver for memcpy operations)
-61: Crypto Accelerator 0
-62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
-63: Hash Accelerator 0 TX
-
-Example:
-
-	uart@80120000 {
-		compatible = "arm,pl011", "arm,primecell";
-		reg = <0x80120000 0x1000>;
-		interrupts = <0 11 0x4>;
-
-		dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
-		       <&dma 13 0 0x0>; /* Logical - MemToDev */
-		dma-names = "rx", "rx";
-
-	};
diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
new file mode 100644
index 000000000000..8bddfb3b6fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST-Ericsson DMA40 DMA Engine
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  "#dma-cells":
+    const: 3
+    description: |
+      The first cell is the unique device channel number as indicated by this
+      table for DB8500 which is the only ASIC known to use DMA40:
+
+      0:  SPI controller 0
+      1:  SD/MMC controller 0 (unused)
+      2:  SD/MMC controller 1 (unused)
+      3:  SD/MMC controller 2 (unused)
+      4:  I2C port 1
+      5:  I2C port 3
+      6:  I2C port 2
+      7:  I2C port 4
+      8:  Synchronous Serial Port SSP0
+      9:  Synchronous Serial Port SSP1
+      10: Multi-Channel Display Engine MCDE RX
+      11: UART port 2
+      12: UART port 1
+      13: UART port 0
+      14: Multirate Serial Port MSP2
+      15: I2C port 0
+      16: USB OTG in/out endpoints 7 & 15
+      17: USB OTG in/out endpoints 6 & 14
+      18: USB OTG in/out endpoints 5 & 13
+      19: USB OTG in/out endpoints 4 & 12
+      20: SLIMbus or HSI channel 0
+      21: SLIMbus or HSI channel 1
+      22: SLIMbus or HSI channel 2
+      23: SLIMbus or HSI channel 3
+      24: Multimedia DSP SXA0
+      25: Multimedia DSP SXA1
+      26: Multimedia DSP SXA2
+      27: Multimedia DSP SXA3
+      28: SD/MMC controller 2
+      29: SD/MMC controller 0
+      30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
+      31: MSP port 0 or SLIMbus channel 0
+      32: SD/MMC controller 1
+      33: SPI controller 2
+      34: i2c3 RX2 TX2
+      35: SPI controller 1
+      36: USB OTG in/out endpoints 3 & 11
+      37: USB OTG in/out endpoints 2 & 10
+      38: USB OTG in/out endpoints 1 & 9
+      39: USB OTG in/out endpoints 8
+      40: SPI controller 3
+      41: SD/MMC controller 3
+      42: SD/MMC controller 4
+      43: SD/MMC controller 5
+      44: Multimedia DSP SXA4
+      45: Multimedia DSP SXA5
+      46: SLIMbus channel 8 or Multimedia DSP SXA6
+      47: SLIMbus channel 9 or Multimedia DSP SXA7
+      48: Crypto Accelerator 1
+      49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
+      50: Hash Accelerator 1 TX
+      51: memcpy TX (to be used by the DMA driver for memcpy operations)
+      52: SLIMbus or HSI channel 4
+      53: SLIMbus or HSI channel 5
+      54: SLIMbus or HSI channel 6
+      55: SLIMbus or HSI channel 7
+      56: memcpy (to be used by the DMA driver for memcpy operations)
+      57: memcpy (to be used by the DMA driver for memcpy operations)
+      58: memcpy (to be used by the DMA driver for memcpy operations)
+      59: memcpy (to be used by the DMA driver for memcpy operations)
+      60: memcpy (to be used by the DMA driver for memcpy operations)
+      61: Crypto Accelerator 0
+      62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
+      63: Hash Accelerator 0 TX
+
+      The second cell is the DMA request line number. This is only used when
+      a fixed channel is allocated, and indicated by setting bit 3 in the
+      flags field (see below).
+
+      The third cell is a 32bit flags bitfield with the following possible
+      bits set:
+      0x00000001 (bit 0) - mode:
+        Logical channel when unset
+        Physical channel when set
+      0x00000002 (bit 1) - direction:
+        Memory to Device when unset
+        Device to Memory when set
+      0x00000004 (bit 2) - endianness:
+        Little endian when unset
+        Big endian when set
+      0x00000008 (bit 3) - use fixed channel:
+        Use automatic channel selection when unset
+        Use DMA request line number when set
+      0x00000010 (bit 4) - set channel as high priority:
+        Normal priority when unset
+        High priority when set
+
+  compatible:
+    items:
+      - const: stericsson,db8500-dma40
+      - const: stericsson,dma40
+
+  reg:
+    items:
+      - description: DMA40 memory base
+      - description: LCPA memory base
+
+  reg-names:
+    items:
+      - const: base
+      - const: lcpa
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  memcpy-channels:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Array of u32 elements indicating which channels on the DMA
+      engine are elegible for memcpy transfers
+
+required:
+  - "#dma-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - memcpy-channels
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/mfd/dbx500-prcmu.h>
+    dma-controller@801C0000 {
+      compatible = "stericsson,db8500-dma40", "stericsson,dma40";
+      reg = <0x801C0000 0x1000>, <0x40010000 0x800>;
+      reg-names = "base", "lcpa";
+      interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+      #dma-cells = <3>;
+      memcpy-channels = <56 57 58 59 60>;
+      clocks = <&prcmu_clk PRCMU_DMACLK>;
+    };
+...
diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml
new file mode 100644
index 000000000000..3e63f79890b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek mt8186 DSP core
+
+maintainers:
+  - Tinghan Shen <tinghan.shen@mediatek.com>
+
+description: |
+  MediaTek mt8186 SoC contains a DSP core used for
+  advanced pre- and post- audio processing.
+
+properties:
+  compatible:
+    const: mediatek,mt8186-dsp
+
+  reg:
+    items:
+      - description: Address and size of the DSP config registers
+      - description: Address and size of the DSP SRAM
+      - description: Address and size of the DSP secure registers
+      - description: Address and size of the DSP bus registers
+
+  reg-names:
+    items:
+      - const: cfg
+      - const: sram
+      - const: sec
+      - const: bus
+
+  clocks:
+    items:
+      - description: mux for audio dsp clock
+      - description: mux for audio dsp local bus
+
+  clock-names:
+    items:
+      - const: audiodsp
+      - const: adsp_bus
+
+  power-domains:
+    maxItems: 1
+
+  mboxes:
+    items:
+      - description: mailbox for receiving audio DSP requests.
+      - description: mailbox for transmitting requests to audio DSP.
+
+  mbox-names:
+    items:
+      - const: rx
+      - const: tx
+
+  memory-region:
+    items:
+      - description: dma buffer between host and DSP.
+      - description: DSP system memory.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - power-domains
+  - mbox-names
+  - mboxes
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8186-clk.h>
+    dsp@10680000 {
+        compatible = "mediatek,mt8186-dsp";
+        reg = <0x10680000 0x2000>,
+              <0x10800000 0x100000>,
+              <0x1068b000 0x100>,
+              <0x1068f000 0x1000>;
+        reg-names = "cfg", "sram", "sec", "bus";
+        clocks = <&topckgen CLK_TOP_AUDIODSP>,
+                 <&topckgen CLK_TOP_ADSP_BUS>;
+        clock-names = "audiodsp",
+                      "adsp_bus";
+        power-domains = <&spm 6>;
+        mbox-names = "rx", "tx";
+        mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+    };
diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
index b7e68b0dfa13..ca8d8661f872 100644
--- a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
+++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
@@ -50,13 +50,13 @@ properties:
 
   mboxes:
     items:
-      - description: ipc reply between host and audio DSP.
-      - description: ipc request between host and audio DSP.
+      - description: mailbox for receiving audio DSP requests.
+      - description: mailbox for transmitting requests to audio DSP.
 
   mbox-names:
     items:
-      - const: mbox0
-      - const: mbox1
+      - const: rx
+      - const: tx
 
   memory-region:
     items:
@@ -100,6 +100,6 @@ examples:
        memory-region = <&adsp_dma_mem_reserved>,
                        <&adsp_mem_reserved>;
        power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
-       mbox-names = "mbox0", "mbox1";
+       mbox-names = "rx", "tx";
        mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
     };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
index 378da2649e66..29c27eadbac8 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
@@ -11,7 +11,11 @@ maintainers:
 
 properties:
   compatible:
-    const: xlnx,zynq-gpio-1.0
+    enum:
+      - xlnx,zynq-gpio-1.0
+      - xlnx,zynqmp-gpio-1.0
+      - xlnx,versal-gpio-1.0
+      - xlnx,pmc-gpio-1.0
 
   reg:
     maxItems: 1
@@ -24,6 +28,11 @@ properties:
 
   gpio-controller: true
 
+  gpio-line-names:
+    description: strings describing the names of each gpio line
+    minItems: 58
+    maxItems: 174
+
   interrupt-controller: true
 
   "#interrupt-cells":
@@ -32,6 +41,54 @@ properties:
   clocks:
     maxItems: 1
 
+  power-domains:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,zynqmp-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 174
+          maxItems: 174
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,zynq-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 118
+          maxItems: 118
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,versal-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 58
+          maxItems: 58
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,pmc-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 116
+          maxItems: 116
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 85f8d4764740..78964c140b46 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -14,16 +14,21 @@ properties:
     pattern: '^gpu@[a-f0-9]+$'
 
   compatible:
-    items:
-      - enum:
-          - amlogic,meson-g12a-mali
-          - mediatek,mt8183-mali
-          - realtek,rtd1619-mali
-          - renesas,r9a07g044-mali
-          - renesas,r9a07g054-mali
-          - rockchip,px30-mali
-          - rockchip,rk3568-mali
-      - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
+    oneOf:
+      - items:
+          - enum:
+              - amlogic,meson-g12a-mali
+              - mediatek,mt8183-mali
+              - realtek,rtd1619-mali
+              - renesas,r9a07g044-mali
+              - renesas,r9a07g054-mali
+              - rockchip,px30-mali
+              - rockchip,rk3568-mali
+          - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
+      - items:
+          - enum:
+              - mediatek,mt8192-mali
+          - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
index e6485f7b046f..217c42874f41 100644
--- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
+++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
@@ -16,6 +16,7 @@ properties:
 
   compatible:
     enum:
+      - brcm,2711-v3d
       - brcm,7268-v3d
       - brcm,7278-v3d
 
diff --git a/Documentation/devicetree/bindings/hwmon/ibm,p8-occ-hwmon.txt b/Documentation/devicetree/bindings/hwmon/ibm,p8-occ-hwmon.txt
new file mode 100644
index 000000000000..5dc5d2e2573d
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ibm,p8-occ-hwmon.txt
@@ -0,0 +1,25 @@
+Device-tree bindings for I2C-based On-Chip Controller hwmon device
+------------------------------------------------------------------
+
+Required properties:
+ - compatible = "ibm,p8-occ-hwmon";
+ - reg = <I2C address>;			: I2C bus address
+
+Examples:
+
+    i2c-bus@100 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clock-frequency = <100000>;
+        < more properties >
+
+        occ-hwmon@1 {
+            compatible = "ibm,p8-occ-hwmon";
+            reg = <0x50>;
+        };
+
+        occ-hwmon@2 {
+            compatible = "ibm,p8-occ-hwmon";
+            reg = <0x51>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml
index b04657849852..e1719839faf0 100644
--- a/Documentation/devicetree/bindings/hwmon/national,lm90.yaml
+++ b/Documentation/devicetree/bindings/hwmon/national,lm90.yaml
@@ -16,6 +16,7 @@ properties:
       - adi,adm1032
       - adi,adt7461
       - adi,adt7461a
+      - adi,adt7481
       - dallas,max6646
       - dallas,max6647
       - dallas,max6649
@@ -50,6 +51,12 @@ properties:
   "#thermal-sensor-cells":
     const: 1
 
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
   vcc-supply:
     description: phandle to the regulator that provides the +VCC supply
 
@@ -61,6 +68,29 @@ required:
   - compatible
   - reg
 
+patternProperties:
+  "^channel@([0-2])$":
+    type: object
+    description: Represents channels of the device and their specific configuration.
+
+    properties:
+      reg:
+        description: The channel number. 0 is local channel, 1-2 are remote channels.
+        items:
+          minimum: 0
+          maximum: 2
+
+      label:
+        description: A descriptive name for this channel, like "ambient" or "psu".
+
+      temperature-offset-millicelsius:
+        description: Temperature offset to be added to or subtracted from remote temperature measurements.
+
+    required:
+      - reg
+
+    additionalProperties: false
+
 allOf:
   - if:
       not:
@@ -70,12 +100,84 @@ allOf:
               enum:
                 - adi,adt7461
                 - adi,adt7461a
+                - adi,adt7481
                 - ti,tmp451
                 - ti,tmp461
     then:
       properties:
         ti,extended-range-enable: false
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - dallas,max6646
+              - dallas,max6647
+              - dallas,max6649
+              - dallas,max6657
+              - dallas,max6658
+              - dallas,max6659
+              - dallas,max6695
+              - dallas,max6696
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adt7461
+              - adi,adt7461a
+              - adi,adt7481
+              - onnn,nct1008
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127750
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adm1032
+              - dallas,max6680
+              - dallas,max6681
+              - gmt,g781
+              - national,lm86
+              - national,lm89
+              - national,lm90
+              - national,lm99
+              - nxp,sa56004
+              - winbond,w83l771
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127875
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,tmp451
+              - ti,tmp461
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127937
+
 additionalProperties: false
 
 examples:
@@ -94,3 +196,32 @@ examples:
             #thermal-sensor-cells = <1>;
         };
     };
+  - |
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      sensor@4c {
+        compatible = "adi,adt7481";
+        reg = <0x4c>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        channel@0 {
+          reg = <0x0>;
+          label = "local";
+        };
+
+        channel@1 {
+          reg = <0x1>;
+          label = "front";
+          temperature-offset-millicelsius = <4000>;
+        };
+
+        channel@2 {
+          reg = <0x2>;
+          label = "back";
+          temperature-offset-millicelsius = <750>;
+        };
+      };
+    };
diff --git a/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml b/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml
new file mode 100644
index 000000000000..e58465d1b0c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/arm,i2c-versatile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I2C Controller on ARM Ltd development platforms
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    const: arm,versatile-i2c
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+...
+
diff --git a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt b/Documentation/devicetree/bindings/i2c/i2c-efm32.txt
deleted file mode 100644
index 3b30e54ae3c7..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Energymicro efm32 i2c controller
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : should be "energymicro,efm32-i2c"
- - interrupts : the interrupt number
- - clocks : reference to the module clock
-
-Recommended properties :
-
- - clock-frequency : maximal I2C bus clock frequency in Hz.
- - energymicro,location : Decides the location of the USART I/O pins.
-   Allowed range : [0 .. 6]
-
-Example:
-	i2c0: i2c@4000a000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "energymicro,efm32-i2c";
-		reg = <0x4000a000 0x400>;
-		interrupts = <9>;
-		clocks = <&cmu clk_HFPERCLKI2C0>;
-		clock-frequency = <100000>;
-		energymicro,location = <3>;
-
-		eeprom@50 {
-			compatible = "microchip,24c02";
-			reg = <0x50>;
-			pagesize = <16>;
-		};
-	};
-
diff --git a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
deleted file mode 100644
index 72065b0ff680..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-I2C for Nomadik based systems
-
-Required (non-standard) properties:
- - Nil
-
-Recommended (non-standard) properties:
- - clock-frequency : Maximum bus clock frequency for the device
-
-Optional (non-standard) properties:
- - Nil
-
-Example :
-
-i2c@80004000 {
-        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-        reg = <0x80004000 0x1000>;
-        interrupts = <0 21 0x4>;
-        #address-cells = <1>;
-        #size-cells = <0>;
-        v-i2c-supply = <&db8500_vape_reg>;
-
-        clock-frequency = <400000>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
deleted file mode 100644
index a37c9455b244..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-Device tree configuration for i2c-ocores
-
-Required properties:
-- compatible      : "opencores,i2c-ocores"
-                    "aeroflexgaisler,i2cmst"
-                    "sifive,fu540-c000-i2c", "sifive,i2c0"
-                    For Opencore based I2C IP block reimplemented in
-                    FU540-C000 SoC.
-                    "sifive,fu740-c000-i2c", "sifive,i2c0"
-                    For Opencore based I2C IP block reimplemented in
-                    FU740-C000 SoC.
-                    Please refer to sifive-blocks-ip-versioning.txt for
-                    additional details.
-- reg             : bus address start and address range size of device
-- clocks          : handle to the controller clock; see the note below.
-                    Mutually exclusive with opencores,ip-clock-frequency
-- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
-                    see the note below. Mutually exclusive with clocks
-- #address-cells  : should be <1>
-- #size-cells     : should be <0>
-
-Optional properties:
-- interrupts      : interrupt number.
-- clock-frequency : frequency of bus clock in Hz; see the note below.
-                    Defaults to 100 KHz when the property is not specified
-- reg-shift       : device register offsets are shifted by this value
-- reg-io-width    : io register width in bytes (1, 2 or 4)
-- regstep         : deprecated, use reg-shift above
-
-Note
-clock-frequency property is meant to control the bus frequency for i2c bus
-drivers, but it was incorrectly used to specify i2c controller input clock
-frequency. So the following rules are set to fix this situation:
-- if clock-frequency is present and neither opencores,ip-clock-frequency nor
-  clocks are, then clock-frequency specifies i2c controller clock frequency.
-  This is to keep backwards compatibility with setups using old DTB. i2c bus
-  frequency is fixed at 100 KHz.
-- if clocks is present it specifies i2c controller clock. clock-frequency
-  property specifies i2c bus frequency.
-- if opencores,ip-clock-frequency is present it specifies i2c controller
-  clock frequency. clock-frequency property specifies i2c bus frequency.
-
-Examples:
-
-	i2c0: ocores@a0000000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "opencores,i2c-ocores";
-		reg = <0xa0000000 0x8>;
-		interrupts = <10>;
-		opencores,ip-clock-frequency = <20000000>;
-
-		reg-shift = <0>;	/* 8 bit registers */
-		reg-io-width = <1>;	/* 8 bit read/write */
-
-		dummy@60 {
-			compatible = "dummy";
-			reg = <0x60>;
-		};
-	};
-or
-	i2c0: ocores@a0000000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "opencores,i2c-ocores";
-		reg = <0xa0000000 0x8>;
-		interrupts = <10>;
-		clocks = <&osc>;
-		clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
-
-		reg-shift = <0>;	/* 8 bit registers */
-		reg-io-width = <1>;	/* 8 bit read/write */
-
-		dummy@60 {
-			compatible = "dummy";
-			reg = <0x60>;
-		};
-	};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
index 924ad8c03464..166865e48849 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
@@ -7,6 +7,7 @@ PROPERTIES:
 	Value type: <string>
 	Definition: must be one of:
 		"qcom,msm8916-cci"
+		"qcom,msm8974-cci"
 		"qcom,msm8996-cci"
 		"qcom,sdm845-cci"
 		"qcom,sm8250-cci"
@@ -43,9 +44,9 @@ PROPERTIES:
 
 SUBNODES:
 
-The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
-sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and
-"i2c-bus@1".
+The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8974,
+msm8996, sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0"
+and "i2c-bus@1".
 
 PROPERTIES:
 
diff --git a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
deleted file mode 100644
index 361d31c51b6f..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-i2c Controller on ARM Versatile platform:
-
-Required properties:
-- compatible : Must be "arm,versatile-i2c";
-- reg
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
diff --git a/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt b/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt
deleted file mode 100644
index 5dc5d2e2573d..000000000000
--- a/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Device-tree bindings for I2C-based On-Chip Controller hwmon device
-------------------------------------------------------------------
-
-Required properties:
- - compatible = "ibm,p8-occ-hwmon";
- - reg = <I2C address>;			: I2C bus address
-
-Examples:
-
-    i2c-bus@100 {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        clock-frequency = <100000>;
-        < more properties >
-
-        occ-hwmon@1 {
-            compatible = "ibm,p8-occ-hwmon";
-            reg = <0x50>;
-        };
-
-        occ-hwmon@2 {
-            compatible = "ibm,p8-occ-hwmon";
-            reg = <0x51>;
-        };
-    };
diff --git a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
index 128444942aec..09d2591e1fa3 100644
--- a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
@@ -7,17 +7,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
 
 description: |
-  The NPCM750x includes sixteen I2C bus controllers. All Controllers support
-  both master and slave mode. Each controller can switch between master and slave
-  at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
-  RX.
+  I2C bus controllers of the NPCM series support both master and
+  slave mode. Each controller can switch between master and slave at run time
+  (i.e. IPMB mode). HW FIFO for TX and RX are supported.
 
 maintainers:
   - Tali Perry <tali.perry1@gmail.com>
 
 properties:
   compatible:
-    const: nuvoton,npcm750-i2c
+    enum:
+      - nuvoton,npcm750-i2c
+      - nuvoton,npcm845-i2c
 
   reg:
     maxItems: 1
@@ -36,6 +37,10 @@ properties:
     default: 100000
     enum: [100000, 400000, 1000000]
 
+  nuvoton,sys-mgr:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: The phandle of system manager register node.
+
 required:
   - compatible
   - reg
@@ -44,6 +49,15 @@ required:
 
 allOf:
   - $ref: /schemas/i2c/i2c-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nuvoton,npcm845-i2c
+
+    then:
+      required:
+        - nuvoton,sys-mgr
 
 unevaluatedProperties: false
 
@@ -57,6 +71,7 @@ examples:
         clock-frequency = <100000>;
         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
         compatible = "nuvoton,npcm750-i2c";
+        nuvoton,sys-mgr = <&gcr>;
     };
 
 ...
diff --git a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml
new file mode 100644
index 000000000000..85d9efb743ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OpenCores I2C controller
+
+maintainers:
+  - Peter Korsgaard <peter@korsgaard.com>
+  - Andrew Lunn <andrew@lunn.ch>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
+              - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
+          - const: sifive,i2c0
+      - enum:
+          - opencores,i2c-ocores
+          - aeroflexgaisler,i2cmst
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-frequency:
+    description: |
+      clock-frequency property is meant to control the bus frequency for i2c bus
+      drivers, but it was incorrectly used to specify i2c controller input clock
+      frequency. So the following rules are set to fix this situation:
+      - if clock-frequency is present and neither opencores,ip-clock-frequency nor
+        clocks are, then clock-frequency specifies i2c controller clock frequency.
+        This is to keep backwards compatibility with setups using old DTB. i2c bus
+        frequency is fixed at 100 KHz.
+      - if clocks is present it specifies i2c controller clock. clock-frequency
+        property specifies i2c bus frequency.
+      - if opencores,ip-clock-frequency is present it specifies i2c controller
+        clock frequency. clock-frequency property specifies i2c bus frequency.
+    default: 100000
+
+  reg-io-width:
+    description: |
+      io register width in bytes
+    enum: [1, 2, 4]
+
+  reg-shift:
+    description: |
+      device register offsets are shifted by this value
+    default: 0
+
+  regstep:
+    description: |
+      deprecated, use reg-shift above
+    deprecated: true
+
+  opencores,ip-clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Frequency of the controller clock in Hz. Mutually exclusive with clocks.
+      See the note above.
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+
+oneOf:
+  - required:
+      - opencores,ip-clock-frequency
+  - required:
+      - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c@a0000000 {
+      compatible = "opencores,i2c-ocores";
+      reg = <0xa0000000 0x8>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      interrupts = <10>;
+      opencores,ip-clock-frequency = <20000000>;
+
+      reg-shift = <0>;	/* 8 bit registers */
+      reg-io-width = <1>;	/* 8 bit read/write */
+    };
+
+    i2c@b0000000 {
+      compatible = "opencores,i2c-ocores";
+      reg = <0xa0000000 0x8>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      interrupts = <10>;
+      clocks = <&osc>;
+      clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
+
+      reg-shift = <0>;	/* 8 bit registers */
+      reg-io-width = <1>;	/* 8 bit read/write */
+    };
+...
diff --git a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml
new file mode 100644
index 000000000000..eec502c57047
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST Microelectronics Nomadik I2C Bindings
+
+description: The Nomadik I2C host controller began its life in the ST
+  Microelectronics STn8800 SoC, and was then inherited into STn8810 and
+  STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
+  DB8500 after the merge of these two companies wireless divisions.
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - st,nomadik-i2c
+  required:
+    - compatible
+
+properties:
+  compatible:
+    oneOf:
+      # The variant found in STn8815
+      - items:
+          - const: st,nomadik-i2c
+          - const: arm,primecell
+      # The variant found in DB8500
+      - items:
+          - const: stericsson,db8500-i2c
+          - const: st,nomadik-i2c
+          - const: arm,primecell
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    oneOf:
+      # Clock name in STn8815
+      - items:
+          - const: mclk
+          - const: apb_pclk
+      # Clock name in DB8500
+      - items:
+          - const: i2cclk
+          - const: apb_pclk
+
+  resets:
+    maxItems: 1
+
+  clock-frequency:
+    minimum: 1
+    maximum: 400000
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
+    #include <dt-bindings/arm/ux500_pm_domains.h>
+    i2c@80004000 {
+      compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
+      reg = <0x80004000 0x1000>;
+      interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+
+      #address-cells = <1>;
+      #size-cells = <0>;
+      v-i2c-supply = <&db8500_vape_reg>;
+
+      clock-frequency = <400000>;
+      clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
+      clock-names = "i2cclk", "apb_pclk";
+      power-domains = <&pm_domains DOMAIN_VAPE>;
+      resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
+    };
+
+    i2c@101f8000 {
+      compatible = "st,nomadik-i2c", "arm,primecell";
+      reg = <0x101f8000 0x1000>;
+      interrupt-parent = <&vica>;
+      interrupts = <20>;
+      clock-frequency = <100000>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      clocks = <&i2c0clk>, <&pclki2c0>;
+      clock-names = "mclk", "apb_pclk";
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
index 4fcbfd93e218..8d829ef878bc 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ADIS16240 Programmable Impact Sensor and Recorder driver
 
 maintainers:
-  - Alexandru Ardelean <alexandru.ardelean@analog.com>
+  - Alexandru Tachici <alexandru.tachici@analog.com>
 
 description: |
   ADIS16240 Programmable Impact Sensor and Recorder driver that supports
diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
index 11d32a288535..9bb039e2f533 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
@@ -55,7 +55,7 @@ examples:
         /* Example for a I2C device node */
         accelerometer@2a {
             compatible = "adi,adxl345";
-            reg = <0x53>;
+            reg = <0x2a>;
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
         };
diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml
index 911a1ae9c83f..272eb48eef5a 100644
--- a/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/bosch,bmi088.yaml
@@ -17,7 +17,9 @@ description: |
 properties:
   compatible:
     enum:
+      - bosch,bmi085-accel
       - bosch,bmi088-accel
+      - bosch,bmi090l-accel
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
index 55fd3548e3b6..f6e2a16a710b 100644
--- a/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/murata,sca3300.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - murata,sca3300
+      - murata,scl3300
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
index b5aed40d8a50..2d72ff6bcbc0 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
@@ -8,7 +8,6 @@ title: Analog Devices AD9467 and similar High-Speed ADCs
 
 maintainers:
   - Michael Hennerich <michael.hennerich@analog.com>
-  - Alexandru Ardelean <alexandru.ardelean@analog.com>
 
 description: |
   The AD9467 and the parts similar with it, are high-speed analog-to-digital
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
index 0924b2b4972b..8e25773d69be 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml
@@ -8,7 +8,6 @@ title: Analog Devices AXI ADC IP core
 
 maintainers:
   - Michael Hennerich <michael.hennerich@analog.com>
-  - Alexandru Ardelean <alexandru.ardelean@analog.com>
 
 description: |
   Analog Devices Generic AXI ADC IP core for interfacing an ADC device
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
new file mode 100644
index 000000000000..c8cbfd3444be
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC Round Robin ADC
+
+maintainers:
+  - Caleb Connolly <caleb.connolly@linaro.org>
+
+description: |
+  The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to
+  read the voltage, current and temperature for supported peripherals such as
+  the battery thermistor die temperature, charger temperature, USB and DC input
+  voltage / current and battery ID resistor.
+
+properties:
+  compatible:
+    enum:
+      - qcom,pmi8998-rradc
+      - qcom,pm660-rradc
+
+  reg:
+    maxItems: 1
+
+  qcom,batt-id-delay-ms:
+    description: Sets the hardware settling time for the battery ID resistor.
+    enum: [0, 1, 4, 12, 20, 40, 60, 80]
+
+  "#io-channel-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pmic {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      pmic_rradc: adc@4500 {
+          compatible = "qcom,pmi8998-rradc";
+          reg = <0x4500>;
+          #io-channel-cells  = <1>;
+      };
+    };
diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
index d66c24cae1e1..61c6157cf5a9 100644
--- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -19,6 +19,7 @@ properties:
   compatible:
     items:
       - enum:
+          - renesas,r9a07g043-adc   # RZ/G2UL
           - renesas,r9a07g044-adc   # RZ/G2L
           - renesas,r9a07g054-adc   # RZ/V2L
       - const: renesas,rzg2l-adc
@@ -76,16 +77,35 @@ patternProperties:
     properties:
       reg:
         description: |
-          The channel number. It can have up to 8 channels numbered from 0 to 7.
-        items:
-          - minimum: 0
-            maximum: 7
+          The channel number.
 
     required:
       - reg
 
     additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043-adc
+    then:
+      patternProperties:
+        "^channel@[2-7]$": false
+        "^channel@[0-1]$":
+          properties:
+            reg:
+              minimum: 0
+              maximum: 1
+    else:
+      patternProperties:
+        "^channel@[0-7]$":
+          properties:
+            reg:
+              minimum: 0
+              maximum: 7
+
 additionalProperties: false
 
 examples:
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
index fb2c48fc7ce4..24ac40180ac1 100644
--- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml
@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Analog Devices AD5770R DAC device driver
 
 maintainers:
-  - Mircea Caprioru <mircea.caprioru@analog.com>
+  - Alexandru Tachici <alexandru.tachici@analog.com>
 
 description: |
   Bindings for the Analog Devices AD5770R current DAC device. Datasheet can be
diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
index 714191724f7c..88298bc43b81 100644
--- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
@@ -21,6 +21,7 @@ properties:
       - ti,dac5573
       - ti,dac6573
       - ti,dac7573
+      - ti,dac121c081
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml
index 5dbe24be9925..dd29dc6c4c19 100644
--- a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Analog Devices ADIS16480 and similar IMUs
 
 maintainers:
-  - Alexandru Ardelean <alexandru.ardelean@analog.com>
+  - Alexandru Tachici <alexandru.tachici@analog.com>
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
index b8a6ee16854f..b3aa2ebf9661 100644
--- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
+++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml
@@ -126,6 +126,42 @@ properties:
       UINT_MAX (4294967295) represents infinite. Other values
       represent 1-1/N.
 
+  semtech,cs-idle-sleep:
+    description:
+      State of CS pins during sleep mode and idle time.
+    enum:
+      - hi-z
+      - gnd
+      - vdd
+
+  semtech,int-comp-resistor:
+    description:
+      Internal resistor setting for compensation.
+    enum:
+      - lowest
+      - low
+      - high
+      - highest
+
+  semtech,input-precharge-resistor-ohms:
+    default: 4000
+    multipleOf: 2000
+    minimum: 0
+    maximum: 30000
+    description:
+      Pre-charge input resistance in Ohm.
+
+  semtech,input-analog-gain:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 3
+    description: |
+      Defines the input antenna analog gain
+      0: x1.247
+      1: x1 (default)
+      2: x0.768
+      3: x0.552
+
 required:
   - compatible
   - reg
@@ -157,5 +193,8 @@ examples:
         semtech,ph01-proxraw-strength = <2>;
         semtech,ph23-proxraw-strength = <2>;
         semtech,avg-pos-strength = <64>;
+        semtech,int-comp-resistor = "lowest";
+        semtech,input-precharge-resistor-ohms = <2000>;
+        semtech,cs-idle-sleep = "gnd";
       };
     };
diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
index 63e1a1fd00d4..f088c5d2be99 100644
--- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
+++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
@@ -61,6 +61,14 @@ properties:
       UINT_MAX (4294967295) represents infinite. Other values
       represent 1-1/N.
 
+  semtech,input-precharge-resistor-ohms:
+    default: 0
+    multipleOf: 2000
+    minimum: 0
+    maximum: 30000
+    description:
+      Pre-charge input resistance in Ohm.
+
 required:
   - compatible
   - reg
@@ -85,5 +93,6 @@ examples:
         semtech,resolution = <256>;
         semtech,proxraw-strength = <2>;
         semtech,avg-pos-strength = <64>;
+        semtech,input-precharge-resistor-ohms = <4000>;
       };
     };
diff --git a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml
index 656460d9d8c8..322befc41de6 100644
--- a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml
+++ b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml
@@ -19,6 +19,11 @@ properties:
   interrupts:
     maxItems: 1
 
+  reset-gpios:
+    maxItems: 1
+
+  vdd-supply: true
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/input/elan,ekth6915.yaml b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml
new file mode 100644
index 000000000000..05e6f2df604c
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/elan,ekth6915.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/elan,ekth6915.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Elan eKTH6915 touchscreen controller
+
+maintainers:
+  - Douglas Anderson <dianders@chromium.org>
+
+description:
+  Supports the Elan eKTH6915 touchscreen controller.
+  This touchscreen controller uses the i2c-hid protocol with a reset GPIO.
+
+properties:
+  compatible:
+    items:
+      - const: elan,ekth6915
+
+  reg:
+    const: 0x10
+
+  interrupts:
+    maxItems: 1
+
+  reset-gpios:
+    description: Reset GPIO; not all touchscreens using eKTH6915 hook this up.
+
+  vcc33-supply:
+    description: The 3.3V supply to the touchscreen.
+
+  vccio-supply:
+    description:
+      The IO supply to the touchscreen. Need not be specified if this is the
+      same as the 3.3V supply.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - vcc33-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      ap_ts: touchscreen@10 {
+        compatible = "elan,ekth6915";
+        reg = <0x10>;
+
+        interrupt-parent = <&tlmm>;
+        interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+        reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+        vcc33-supply = <&pp3300_ts>;
+      };
+    };
diff --git a/Documentation/devicetree/bindings/input/fsl,mpr121-touchkey.yaml b/Documentation/devicetree/bindings/input/fsl,mpr121-touchkey.yaml
index 878464f128dc..5139af287d3e 100644
--- a/Documentation/devicetree/bindings/input/fsl,mpr121-touchkey.yaml
+++ b/Documentation/devicetree/bindings/input/fsl,mpr121-touchkey.yaml
@@ -57,7 +57,7 @@ examples:
         #address-cells = <1>;
         #size-cells = <0>;
 
-        mpr121@5a {
+        touchkey@5a {
             compatible = "fsl,mpr121-touchkey";
             reg = <0x5a>;
             interrupt-parent = <&gpio1>;
@@ -77,7 +77,7 @@ examples:
         #address-cells = <1>;
         #size-cells = <0>;
 
-        mpr121@5a {
+        touchkey@5a {
             compatible = "fsl,mpr121-touchkey";
             reg = <0x5a>;
             poll-interval = <20>;
diff --git a/Documentation/devicetree/bindings/input/gpio-keys.yaml b/Documentation/devicetree/bindings/input/gpio-keys.yaml
index 7fe1966ea28a..93f601c58984 100644
--- a/Documentation/devicetree/bindings/input/gpio-keys.yaml
+++ b/Documentation/devicetree/bindings/input/gpio-keys.yaml
@@ -127,13 +127,13 @@ examples:
         compatible = "gpio-keys";
         autorepeat;
 
-        up {
+        key-up {
             label = "GPIO Key UP";
             linux,code = <103>;
             gpios = <&gpio1 0 1>;
         };
 
-        down {
+        key-down {
             label = "GPIO Key DOWN";
             linux,code = <108>;
             interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
diff --git a/Documentation/devicetree/bindings/input/iqs269a.yaml b/Documentation/devicetree/bindings/input/iqs269a.yaml
index 9c154e5e1a91..d84d69f5455d 100644
--- a/Documentation/devicetree/bindings/input/iqs269a.yaml
+++ b/Documentation/devicetree/bindings/input/iqs269a.yaml
@@ -475,7 +475,7 @@ examples:
             #address-cells = <1>;
             #size-cells = <0>;
 
-            iqs269a@44 {
+            touch@44 {
                     #address-cells = <1>;
                     #size-cells = <0>;
 
diff --git a/Documentation/devicetree/bindings/input/iqs626a.yaml b/Documentation/devicetree/bindings/input/iqs626a.yaml
index 0cb736c541c9..dd727befe564 100644
--- a/Documentation/devicetree/bindings/input/iqs626a.yaml
+++ b/Documentation/devicetree/bindings/input/iqs626a.yaml
@@ -751,7 +751,7 @@ examples:
             #address-cells = <1>;
             #size-cells = <0>;
 
-            iqs626a@44 {
+            touch@44 {
                     #address-cells = <1>;
                     #size-cells = <0>;
 
diff --git a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml
index d5d6bced3148..96358b12f9b2 100644
--- a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml
+++ b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml
@@ -112,7 +112,7 @@ examples:
       #address-cells = <1>;
       #size-cells = <0>;
 
-      cap1188@28 {
+      touch@28 {
         compatible = "microchip,cap1188";
         interrupt-parent = <&gpio1>;
         interrupts = <0 0>;
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
new file mode 100644
index 000000000000..449c7c988229
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+  - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+  - Johnson Wang <johnson.wang@mediatek.com>
+
+description: |
+  MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
+  MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
+  hardware. It can also optimize the voltage to reduce the power consumption.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8183-cci
+      - mediatek,mt8186-cci
+
+  clocks:
+    items:
+      - description:
+          The multiplexer for clock input of the bus.
+      - description:
+          A parent of "bus" clock which is used as an intermediate clock source
+          when the original clock source (PLL) is under transition and not
+          stable yet.
+
+  clock-names:
+    items:
+      - const: cci
+      - const: intermediate
+
+  operating-points-v2: true
+  opp-table: true
+
+  proc-supply:
+    description:
+      Phandle of the regulator for CCI that provides the supply voltage.
+
+  sram-supply:
+    description:
+      Phandle of the regulator for sram of CCI that provides the supply
+      voltage. When it is present, the implementation needs to do
+      "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+      SoC specific needs. When absent, the voltage scaling flow is handled by
+      hardware, hence no software "voltage tracking" is needed.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - operating-points-v2
+  - proc-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    cci: cci {
+        compatible = "mediatek,mt8183-cci";
+        clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+        clock-names = "cci", "intermediate";
+        operating-points-v2 = <&cci_opp>;
+        proc-supply = <&mt6358_vproc12_reg>;
+    };
+
+    cci_opp: opp-table-cci {
+        compatible = "operating-points-v2";
+        opp-shared;
+        opp2_00: opp-273000000 {
+            opp-hz = /bits/ 64 <273000000>;
+            opp-microvolt = <650000>;
+        };
+        opp2_01: opp-338000000 {
+            opp-hz = /bits/ 64 <338000000>;
+            opp-microvolt = <687500>;
+        };
+        opp2_02: opp-403000000 {
+            opp-hz = /bits/ 64 <403000000>;
+            opp-microvolt = <718750>;
+        };
+        opp2_03: opp-463000000 {
+            opp-hz = /bits/ 64 <463000000>;
+            opp-microvolt = <756250>;
+        };
+        opp2_04: opp-546000000 {
+            opp-hz = /bits/ 64 <546000000>;
+            opp-microvolt = <800000>;
+        };
+        opp2_05: opp-624000000 {
+            opp-hz = /bits/ 64 <624000000>;
+            opp-microvolt = <818750>;
+        };
+        opp2_06: opp-689000000 {
+            opp-hz = /bits/ 64 <689000000>;
+            opp-microvolt = <850000>;
+        };
+        opp2_07: opp-767000000 {
+            opp-hz = /bits/ 64 <767000000>;
+            opp-microvolt = <868750>;
+        };
+        opp2_08: opp-845000000 {
+            opp-hz = /bits/ 64 <845000000>;
+            opp-microvolt = <893750>;
+        };
+        opp2_09: opp-871000000 {
+            opp-hz = /bits/ 64 <871000000>;
+            opp-microvolt = <906250>;
+        };
+        opp2_10: opp-923000000 {
+            opp-hz = /bits/ 64 <923000000>;
+            opp-microvolt = <931250>;
+        };
+        opp2_11: opp-962000000 {
+            opp-hz = /bits/ 64 <962000000>;
+            opp-microvolt = <943750>;
+        };
+        opp2_12: opp-1027000000 {
+            opp-hz = /bits/ 64 <1027000000>;
+            opp-microvolt = <975000>;
+        };
+        opp2_13: opp-1092000000 {
+            opp-hz = /bits/ 64 <1092000000>;
+            opp-microvolt = <1000000>;
+        };
+        opp2_14: opp-1144000000 {
+            opp-hz = /bits/ 64 <1144000000>;
+            opp-microvolt = <1025000>;
+        };
+        opp2_15: opp-1196000000 {
+            opp-hz = /bits/ 64 <1196000000>;
+            opp-microvolt = <1050000>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
new file mode 100644
index 000000000000..bbeb0541536b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect
+
+maintainers:
+  - Georgi Djakov <djakov@kernel.org>
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+  RPMh interconnect providers support system bandwidth requirements through
+  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+  able to communicate with the BCM through the Resource State Coordinator (RSC)
+  associated with each execution environment. Provider nodes must point to at
+  least one RPMh device child node pertaining to their RSC and each provider
+  can map to multiple RPMh resources.
+
+properties:
+  '#interconnect-cells':
+    enum: [ 1, 2 ]
+
+  qcom,bcm-voters:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      maxItems: 1
+    maxItems: 2
+    description:
+      List of phandles to qcom,bcm-voter nodes that are required by
+      this interconnect to send RPMh commands.
+
+  qcom,bcm-voter-names:
+    maxItems: 2
+    description:
+      Names for each of the qcom,bcm-voters specified.
+
+required:
+  - '#interconnect-cells'
+  - qcom,bcm-voters
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index 28b3516aa089..a429a1ed1006 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -18,6 +18,9 @@ description: |
    least one RPMh device child node pertaining to their RSC and each provider
    can map to multiple RPMh resources.
 
+allOf:
+  - $ref: qcom,rpmh-common.yaml#
+
 properties:
   reg:
     maxItems: 1
@@ -130,28 +133,13 @@ properties:
       - qcom,sm8450-pcie-anoc
       - qcom,sm8450-system-noc
 
-  '#interconnect-cells':
-    enum: [ 1, 2 ]
-
-  qcom,bcm-voters:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
-      maxItems: 1
-    description: |
-      List of phandles to qcom,bcm-voter nodes that are required by
-      this interconnect to send RPMh commands.
-
-  qcom,bcm-voter-names:
-    description: |
-      Names for each of the qcom,bcm-voters specified.
+  '#interconnect-cells': true
 
 required:
   - compatible
   - reg
-  - '#interconnect-cells'
-  - qcom,bcm-voters
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
new file mode 100644
index 000000000000..49eb156b08e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
+
+maintainers:
+  - Luca Weiss <luca.weiss@fairphone.com>
+
+description:
+  Qualcomm RPMh-based interconnect provider on SM6350.
+
+allOf:
+  - $ref: qcom,rpmh-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm6350-aggre1-noc
+      - qcom,sm6350-aggre2-noc
+      - qcom,sm6350-config-noc
+      - qcom,sm6350-dc-noc
+      - qcom,sm6350-gem-noc
+      - qcom,sm6350-mmss-noc
+      - qcom,sm6350-npu-noc
+      - qcom,sm6350-system-noc
+
+  reg:
+    maxItems: 1
+
+  '#interconnect-cells': true
+
+patternProperties:
+  '^interconnect-[a-z0-9\-]+$':
+    type: object
+    description:
+      The interconnect providers do not have a separate QoS register space,
+      but share parent's space.
+    $ref: qcom,rpmh-common.yaml#
+
+    properties:
+      compatible:
+        enum:
+          - qcom,sm6350-clk-virt
+          - qcom,sm6350-compute-noc
+
+      '#interconnect-cells': true
+
+    required:
+      - compatible
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    config_noc: interconnect@1500000 {
+        compatible = "qcom,sm6350-config-noc";
+        reg = <0x01500000 0x28000>;
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+    };
+
+    system_noc: interconnect@1620000 {
+        compatible = "qcom,sm6350-system-noc";
+        reg = <0x01620000 0x17080>;
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+
+        clk_virt: interconnect-clk-virt {
+            compatible = "qcom,sm6350-clk-virt";
+            #interconnect-cells = <2>;
+            qcom,bcm-voters = <&apps_bcm_voter>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
deleted file mode 100644
index e0062aebf025..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-RDA Micro RDA8810PL Interrupt Controller
-
-The interrupt controller in RDA8810PL SoC is a custom interrupt controller
-which supports up to 32 interrupts.
-
-Required properties:
-
-- compatible: Should be "rda,8810pl-intc".
-- reg: Specifies base physical address of the registers set.
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 2.
-
-The interrupt sources are as follows:
-
-ID	Name
-------------
-0:	PULSE_DUMMY
-1:	I2C
-2:	NAND_NFSC
-3:	SDMMC1
-4:	SDMMC2
-5:	SDMMC3
-6:	SPI1
-7:	SPI2
-8:	SPI3
-9:	UART1
-10:	UART2
-11:	UART3
-12:	GPIO1
-13:	GPIO2
-14:	GPIO3
-15:	KEYPAD
-16:	TIMER
-17:	TIMEROS
-18:	COMREG0
-19:	COMREG1
-20:	USB
-21:	DMC
-22:	DMA
-23:	CAMERA
-24:	GOUDA
-25:	GPU
-26:	VPU_JPG
-27:	VPU_HOST
-28:	VOC
-29:	AUIFC0
-30:	AUIFC1
-31:	L2CC
-
-Example:
-		apb@20800000 {
-			compatible = "simple-bus";
-			...
-			intc: interrupt-controller@0 {
-				compatible = "rda,8810pl-intc";
-				reg = <0x0 0x1000>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml
new file mode 100644
index 000000000000..96d6285d0087
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/rda,8810pl-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RDA Micro RDA8810PL interrupt controller
+
+maintainers:
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    const: rda,8810pl-intc
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    intc: interrupt-controller@0 {
+      compatible = "rda,8810pl-intc";
+      reg = <0x0 0x1000>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
+...
diff --git a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml
index 5d66c3e4def5..4c15693f7a01 100644
--- a/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml
+++ b/Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml
@@ -26,7 +26,8 @@ properties:
       - qcom,pm8150l-wled
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   default-brightness:
     description: |
@@ -171,6 +172,9 @@ allOf:
 
     then:
       properties:
+        reg:
+          maxItems: 1
+
         qcom,current-boost-limit:
           enum: [ 105, 385, 525, 805, 980, 1260, 1400, 1680 ]
           default: 805
@@ -189,6 +193,9 @@ allOf:
 
     else:
       properties:
+        reg:
+          minItems: 2
+
         qcom,current-boost-limit:
           enum: [ 105, 280, 450, 620, 970, 1150, 1300, 1500 ]
           default: 970
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index 440646e44c0d..d4e2051beeb6 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -17,20 +17,20 @@ description: |
 
   About the Decoder Hardware Block Diagram, please check below:
 
-    +---------------------------------+------------------------------------+
-    |                                 |                                    |
-    | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
-    |            ||                   |                     ||             |
-    +------------||-------------------+---------------------||-------------+
-              lat workqueue           |              core workqueue     <parent>
-    -------------||-----------------------------------------||------------------
-                 ||                                         ||          <child>
-                 \/ <----------------HW index-------------->\/
-           +------------------------------------------------------+
-           |                    enable/disable                    |
-           |           clk     power    irq    iommu              |
-           |                 (lat/lat soc/core0/core1)            |
-           +------------------------------------------------------+
+    +------------------------------------------------+-------------------------------------+
+    |                                                |                                     |
+    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
+    |            ||             ||                   |                     ||              |
+    +------------||-------------||-------------------+---------------------||--------------+
+                 ||     lat     ||                   |               core workqueue  <parent>
+    -------------||-------------||-------------------|---------------------||---------------
+                 ||<------------||----------------HW index---------------->||        <child>
+                 \/             \/                                         \/
+               +-------------------------------------------------------------+
+               |                          enable/disable                     |
+               |                 clk     power    irq    iommu               |
+               |                   (lat/lat soc/core0/core1)                 |
+               +-------------------------------------------------------------+
 
   As above, there are parent and child devices, child mean each hardware. The child device
   controls the information of each hardware independent which include clk/power/irq.
@@ -45,11 +45,19 @@ description: |
   For the smi common may not the same for each hardware, can't combine all hardware in one node,
   or leading to iommu fault when access dram data.
 
+  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
+  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
+  clock when lat start to work, don't have interrupt.
+
+  mt8195: lat soc HW + lat HW + core HW
+  mt8192: lat HW + core HW
+
 properties:
   compatible:
     enum:
       - mediatek,mt8192-vcodec-dec
       - mediatek,mt8186-vcodec-dec
+      - mediatek,mt8195-vcodec-dec
 
   reg:
     maxItems: 1
@@ -87,7 +95,9 @@ patternProperties:
 
     properties:
       compatible:
-        const: mediatek,mtk-vcodec-lat
+        enum:
+          - mediatek,mtk-vcodec-lat
+          - mediatek,mtk-vcodec-lat-soc
 
       reg:
         maxItems: 1
@@ -125,7 +135,6 @@ patternProperties:
     required:
       - compatible
       - reg
-      - interrupts
       - iommus
       - clocks
       - clock-names
@@ -196,6 +205,17 @@ required:
   - dma-ranges
   - ranges
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - mediatek,mtk-vcodec-lat
+
+then:
+  required:
+    - interrupts
+
 additionalProperties: false
 
 examples:
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 8bfdfdfaba59..4fd390c042a9 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -18,6 +18,7 @@ properties:
       - enum:
           - mediatek,mt2701-jpgenc
           - mediatek,mt8183-jpgenc
+          - mediatek,mt8186-jpgenc
       - const: mediatek,mtk-jpgenc
   reg:
     maxItems: 1
@@ -42,6 +43,11 @@ properties:
       Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
       Ports are according to the HW.
 
+  dma-ranges:
+    maxItems: 1
+    description: |
+      Describes the physical address space of IOMMU maps to memory.
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
index 338ab28d5f3b..b28c8e17f158 100644
--- a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
@@ -84,6 +84,13 @@ properties:
       - const: vfe0
       - const: vfe1
 
+  interconnects:
+    maxItems: 1
+
+  interconnect-names:
+    items:
+      - const: vfe-mem
+
   iommus:
     maxItems: 4
 
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index a98b359bf909..71bc5cefb49c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -32,6 +32,7 @@ properties:
           - mediatek,mt2701-smi-common
           - mediatek,mt2712-smi-common
           - mediatek,mt6779-smi-common
+          - mediatek,mt6795-smi-common
           - mediatek,mt8167-smi-common
           - mediatek,mt8173-smi-common
           - mediatek,mt8183-smi-common
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index c886681f62a7..59dcd163668f 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -20,6 +20,7 @@ properties:
           - mediatek,mt2701-smi-larb
           - mediatek,mt2712-smi-larb
           - mediatek,mt6779-smi-larb
+          - mediatek,mt6795-smi-larb
           - mediatek,mt8167-smi-larb
           - mediatek,mt8173-smi-larb
           - mediatek,mt8183-smi-larb
diff --git a/Documentation/devicetree/bindings/mfd/da9063.txt b/Documentation/devicetree/bindings/mfd/da9063.txt
deleted file mode 100644
index aa8b800cc4ad..000000000000
--- a/Documentation/devicetree/bindings/mfd/da9063.txt
+++ /dev/null
@@ -1,114 +0,0 @@
-* Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
-
-DA9063 consists of a large and varied group of sub-devices (I2C Only):
-
-Device                   Supply Names    Description
-------                   ------------    -----------
-da9063-regulator        :               : LDOs & BUCKs
-da9063-onkey            :               : On Key
-da9063-rtc              :               : Real-Time Clock (DA9063 only)
-da9063-watchdog         :               : Watchdog
-
-======
-
-Required properties:
-
-- compatible : Should be "dlg,da9063" or "dlg,da9063l"
-- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
-  modified to match the chip's OTP settings).
-- interrupts : IRQ line information.
-- interrupt-controller
-
-Sub-nodes:
-
-- regulators : This node defines the settings for the LDOs and BUCKs.
-  The DA9063(L) regulators are bound using their names listed below:
-
-    bcore1    : BUCK CORE1
-    bcore2    : BUCK CORE2
-    bpro      : BUCK PRO
-    bmem      : BUCK MEM
-    bio       : BUCK IO
-    bperi     : BUCK PERI
-    ldo1      : LDO_1	(DA9063 only)
-    ldo2      : LDO_2	(DA9063 only)
-    ldo3      : LDO_3
-    ldo4      : LDO_4	(DA9063 only)
-    ldo5      : LDO_5	(DA9063 only)
-    ldo6      : LDO_6	(DA9063 only)
-    ldo7      : LDO_7
-    ldo8      : LDO_8
-    ldo9      : LDO_9
-    ldo10     : LDO_10	(DA9063 only)
-    ldo11     : LDO_11
-
-  The component follows the standard regulator framework and the bindings
-  details of individual regulator device can be found in:
-  Documentation/devicetree/bindings/regulator/regulator.txt
-
-- rtc : This node defines settings for the Real-Time Clock associated with
-  the DA9063 only. The RTC is not present in DA9063L. There are currently
-  no entries in this binding, however compatible = "dlg,da9063-rtc" should
-  be added if a node is created.
-
-- onkey : This node defines the OnKey settings for controlling the key
-  functionality of the device. The node should contain the compatible property
-  with the value "dlg,da9063-onkey".
-
-  Optional onkey properties:
-
-  - dlg,disable-key-power : Disable power-down using a long key-press. If this
-    entry exists the OnKey driver will remove support for the KEY_POWER key
-    press. If this entry does not exist then by default the key-press
-    triggered power down is enabled and the OnKey will support both KEY_POWER
-    and KEY_SLEEP.
-
-- watchdog : This node defines settings for the Watchdog timer associated
-  with the DA9063 and DA9063L. The node should contain the compatible property
-  with the value "dlg,da9063-watchdog".
-
-  Optional watchdog properties:
-  - dlg,use-sw-pm: Add this property to disable the watchdog during suspend.
-  Only use this option if you can't use the watchdog automatic suspend
-  function during a suspend (see register CONTROL_B).
-
-Example:
-
-	pmic0: da9063@58 {
-		compatible = "dlg,da9063"
-		reg = <0x58>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-controller;
-
-		rtc {
-			compatible = "dlg,da9063-rtc";
-		};
-
-		wdt {
-			compatible = "dlg,da9063-watchdog";
-		};
-
-		onkey {
-			compatible = "dlg,da9063-onkey";
-			dlg,disable-key-power;
-		};
-
-		regulators {
-			DA9063_BCORE1: bcore1 {
-				regulator-name = "BCORE1";
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1570000>;
-				regulator-min-microamp = <500000>;
-				regulator-max-microamp = <2000000>;
-				regulator-boot-on;
-			};
-			DA9063_LDO11: ldo11 {
-				regulator-name = "LDO_11";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <3600000>;
-				regulator-boot-on;
-			};
-		};
-	};
-
diff --git a/Documentation/devicetree/bindings/mfd/dlg,da9063.yaml b/Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
new file mode 100644
index 000000000000..d71933460e90
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
+
+maintainers:
+  - Steve Twiss <stwiss.opensource@diasemi.com>
+
+description: |
+  For device-tree bindings of other sub-modules refer to the binding documents
+  under the respective sub-system directories.
+
+properties:
+  compatible:
+    enum:
+      - dlg,da9063
+      - dlg,da9063l
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  dlg,use-sw-pm:
+    type: boolean
+    description:
+      Disable the watchdog during suspend.
+      Only use this option if you can't use the watchdog automatic suspend
+      function during a suspend (see register CONTROL_B).
+
+  watchdog:
+    type: object
+    $ref: /schemas/watchdog/watchdog.yaml#
+    unevaluatedProperties: false
+    properties:
+      compatible:
+        const: dlg,da9063-watchdog
+
+  rtc:
+    type: object
+    $ref: /schemas/rtc/rtc.yaml#
+    unevaluatedProperties: false
+    properties:
+      compatible:
+        const: dlg,da9063-rtc
+
+  onkey:
+    type: object
+    $ref: /schemas/input/input.yaml#
+    unevaluatedProperties: false
+    properties:
+      compatible:
+        const: dlg,da9063-onkey
+
+      dlg,disable-key-power:
+        type: boolean
+        description: |
+          Disable power-down using a long key-press.
+          If this entry does not exist then by default the key-press triggered
+          power down is enabled and the OnKey will support both KEY_POWER and
+          KEY_SLEEP.
+
+  regulators:
+    type: object
+    patternProperties:
+      "^(ldo[1-11]|bcore[1-2]|bpro|bmem|bio|bperi)$":
+        $ref: /schemas/regulator/regulator.yaml
+        unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      pmic@58 {
+        compatible = "dlg,da9063";
+        reg = <0x58>;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gpio6>;
+        interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+        interrupt-controller;
+
+        rtc {
+          compatible = "dlg,da9063-rtc";
+        };
+
+        watchdog {
+          compatible = "dlg,da9063-watchdog";
+        };
+
+        onkey {
+          compatible = "dlg,da9063-onkey";
+          dlg,disable-key-power;
+        };
+
+        regulators {
+          regulator-bcore1 {
+            regulator-name = "BCORE1";
+            regulator-min-microvolt = <300000>;
+            regulator-max-microvolt = <1570000>;
+            regulator-min-microamp = <500000>;
+            regulator-max-microamp = <2000000>;
+            regulator-boot-on;
+          };
+          regulator-ldo11 {
+            regulator-name = "LDO_11";
+            regulator-min-microvolt = <900000>;
+            regulator-max-microvolt = <3600000>;
+            regulator-boot-on;
+          };
+        };
+      };
+    };
+...
diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
new file mode 100644
index 000000000000..f09577105b50
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+description: |
+  As a system controller, the Freescale i.MX8qm/qxp Control and Status
+  Registers(CSR) module represents a set of miscellaneous registers of a
+  specific subsystem.  It may provide control and/or status report interfaces
+  to a mix of standalone hardware devices within that subsystem.  One typical
+  use-case is for some other nodes to acquire a reference to the syscon node
+  by phandle, and the other typical use-case is that the operating system
+  should consider all subnodes of the CSR module as separate child devices.
+
+properties:
+  $nodename:
+    pattern: "^syscon@[0-9a-f]+$"
+
+  compatible:
+    items:
+      - enum:
+          - fsl,imx8qxp-mipi-lvds-csr
+          - fsl,imx8qm-lvds-csr
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: ipg
+
+patternProperties:
+  "^(ldb|phy|pxl2dpi)$":
+    type: object
+    description: The possible child devices of the CSR module.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qxp-mipi-lvds-csr
+    then:
+      required:
+        - pxl2dpi
+        - ldb
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,imx8qm-lvds-csr
+    then:
+      required:
+        - phy
+        - ldb
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    mipi_lvds_0_csr: syscon@56221000 {
+        compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+        reg = <0x56221000 0x1000>;
+        clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+        clock-names = "ipg";
+
+        mipi_lvds_0_pxl2dpi: pxl2dpi {
+            compatible = "fsl,imx8qxp-pxl2dpi";
+            fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+            power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                    reg = <0>;
+
+                    mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+                        reg = <0>;
+                        remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+                    };
+
+                    mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+                        reg = <1>;
+                        remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+                    };
+                };
+
+                port@1 {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                    reg = <1>;
+
+                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+                        reg = <0>;
+                        remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+                    };
+
+                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+                        reg = <1>;
+                        remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+                    };
+                };
+            };
+        };
+
+        mipi_lvds_0_ldb: ldb {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "fsl,imx8qxp-ldb";
+            clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+                     <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+            clock-names = "pixel", "bypass";
+            power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+            channel@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+                phys = <&mipi_lvds_0_phy>;
+                phy-names = "lvds_phy";
+
+                port@0 {
+                    reg = <0>;
+
+                    mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    /* ... */
+                };
+            };
+
+            channel@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <1>;
+                phys = <&mipi_lvds_0_phy>;
+                phy-names = "lvds_phy";
+
+                port@0 {
+                    reg = <0>;
+
+                    mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    /* ... */
+                };
+            };
+        };
+    };
+
+    mipi_lvds_0_phy: phy@56228300 {
+        compatible = "fsl,imx8qxp-mipi-dphy";
+        reg = <0x56228300 0x100>;
+        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+        clock-names = "phy_ref";
+        #phy-cells = <0>;
+        fsl,syscon = <&mipi_lvds_0_csr>;
+        power-domains = <&pd IMX_SC_R_MIPI_0>;
+    };
diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
index e25caf8ef9f4..04962bb29576 100644
--- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
+++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
@@ -90,6 +90,9 @@ properties:
   pwm:
     $ref: "/schemas/pwm/google,cros-ec-pwm.yaml#"
 
+  kbd-led-backlight:
+    $ref: "/schemas/chrome/google,cros-kbd-led-backlight.yaml#"
+
   keyboard-controller:
     $ref: "/schemas/input/google,cros-ec-keyb.yaml#"
 
diff --git a/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml b/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml
index f91acc42d652..fe13869e2c58 100644
--- a/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml
+++ b/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml
@@ -19,6 +19,7 @@ description: |
 properties:
   compatible:
     const: mps,mp2629
+    const: mps,mp2733
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
index 293db2a71ef2..d59063503b0d 100644
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -20,6 +20,7 @@ This document describes the binding for MFD device and its sub module.
 Required properties:
 compatible:
 	"mediatek,mt6323" for PMIC MT6323
+	"mediatek,mt6331" for PMIC MT6331 and MT6332
 	"mediatek,mt6358" for PMIC MT6358 and MT6366
 	"mediatek,mt6359" for PMIC MT6359
 	"mediatek,mt6397" for PMIC MT6397
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
deleted file mode 100644
index add61bcc3c74..000000000000
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-QCOM Top Control and Status Register
-
-Qualcomm devices have a set of registers that provide various control and status
-functions for their peripherals.  This node is intended to allow access to these
-registers via syscon.
-
-Required properties:
-- compatible:	Should contain:
-		"qcom,tcsr-ipq6018", "syscon", "simple-mfd" for IPQ6018
-		"qcom,tcsr-ipq8064", "syscon" for IPQ8064
-		"qcom,tcsr-apq8064", "syscon" for APQ8064
-		"qcom,tcsr-msm8660", "syscon" for MSM8660
-		"qcom,tcsr-msm8953", "syscon" for MSM8953
-		"qcom,tcsr-msm8960", "syscon" for MSM8960
-		"qcom,tcsr-msm8974", "syscon" for MSM8974
-		"qcom,tcsr-apq8084", "syscon" for APQ8084
-		"qcom,tcsr-msm8916", "syscon" for MSM8916
-- reg: Address range for TCSR registers
-
-Example:
-	tcsr: syscon@1a400000 {
-		compatible = "qcom,tcsr-msm8960", "syscon";
-		reg = <0x1a400000 0x100>;
-	};
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
new file mode 100644
index 000000000000..2f816fd0c9ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Top Control and Status Register
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+  Qualcomm devices have a set of registers that provide various control and
+  status functions for their peripherals.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - qcom,tcsr-apq8064
+              - qcom,tcsr-apq8084
+              - qcom,tcsr-ipq8064
+              - qcom,tcsr-mdm9615
+              - qcom,tcsr-msm8660
+              - qcom,tcsr-msm8916
+              - qcom,tcsr-msm8953
+              - qcom,tcsr-msm8960
+              - qcom,tcsr-msm8974
+          - const: syscon
+      - items:
+          - const: qcom,tcsr-ipq6018
+          - const: syscon
+          - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@1a400000 {
+        compatible = "qcom,tcsr-msm8960", "syscon";
+        reg = <0x1a400000 0x100>;
+    };
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index 10b330d42901..5b05b2ec1728 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -46,6 +46,21 @@ properties:
     minItems: 1
     maxItems: 7
 
+  interrupts:
+    oneOf:
+      - maxItems: 1
+      - maxItems: 4
+
+  interrupt-names:
+    oneOf:
+      - items:
+          - const: global
+      - items:
+          - const: brk
+          - const: up
+          - const: trg-com
+          - const: cc
+
   "#address-cells":
     const: 1
 
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index fa86691ebf16..73cffc45e056 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -48,6 +48,12 @@ patternProperties:
     description:
       This is the SERDES lane control mux.
 
+  "^clock-controller@[0-9a-f]+$":
+    type: object
+    $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
+    description:
+      Clock provider for TI EHRPWM nodes.
+
 required:
   - compatible
   - reg
@@ -79,5 +85,11 @@ examples:
                 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
                 /* SERDES4 lane0/1/2/3 select */
         };
+
+        clock-controller@4140 {
+            compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+            reg = <0x4140 0x18>;
+            #clock-cells = <1>;
+        };
     };
 ...
diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
index 5ecdac9de484..dead421e17d6 100644
--- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
+++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
@@ -10,9 +10,6 @@ maintainers:
   - Al Cooper <alcooperx@gmail.com>
   - Florian Fainelli <f.fainelli@gmail.com>
 
-allOf:
-  - $ref: mmc-controller.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -42,23 +39,46 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
-    description:
-      handle to core clock for the sdhci controller.
+    minItems: 1
+    items:
+      - description: handle to core clock for the sdhci controller
+      - description: handle to improved 150Mhz clock for sdhci controller (Optional clock)
 
   clock-names:
+    minItems: 1
     items:
       - const: sw_sdio
+      - const: sdio_freq # Optional clock
+
+  clock-frequency:
+    description:
+      Maximum operating frequency of sdio_freq sdhci controller clock
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 100000000
+    maximum: 150000000
 
   sdhci,auto-cmd12:
     type: boolean
     description: Specifies that controller should use auto CMD12
 
+allOf:
+  - $ref: mmc-controller.yaml#
+  - if:
+      properties:
+        clock-names:
+          contains:
+            const: sdio_freq
+
+    then:
+      required:
+        - clock-frequency
+
 required:
   - compatible
   - reg
   - interrupts
   - clocks
+  - clock-names
 
 unevaluatedProperties: false
 
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
deleted file mode 100644
index 753e9d7d8956..000000000000
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-* Samsung Exynos specific extensions to the Synopsys Designware Mobile
-  Storage Host Controller
-
-The Synopsys designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core Synopsys dw mshc controller properties described
-by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
-extensions to the Synopsys Designware Mobile Storage Host Controller.
-
-Required Properties:
-
-* compatible: should be
-	- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
-	  specific extensions.
-	- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
-	  specific extensions.
-	- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
-	  specific extensions.
-	- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
-	  specific extensions.
-	- "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
-	  specific extensions.
-	- "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
-	  specific extensions having an SMU.
-	- "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
-	  extensions.
-
-* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
-  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
-  ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
-
-* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
-  in transmit mode and CIU clock phase shift value in receive mode for single
-  data rate mode operation. Refer notes below for the order of the cells and the
-  valid values.
-
-* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
-  in transmit mode and CIU clock phase shift value in receive mode for double
-  data rate mode operation. Refer notes below for the order of the cells and the
-  valid values.
-* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
-  shift value for hs400 mode operation.
-
-  Notes for the sdr-timing and ddr-timing values:
-
-    The order of the cells should be
-      - First Cell: CIU clock phase shift value for tx mode.
-      - Second Cell: CIU clock phase shift value for rx mode.
-
-    Valid values for SDR and DDR CIU clock timing for Exynos5250:
-      - valid value for tx phase shift and rx phase shift is 0 to 7.
-      - when CIU clock divider value is set to 3, all possible 8 phase shift
-        values can be used.
-      - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
-        phase shift clocks should be 0.
-
-* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
-  (Latency value for delay line in Read path)
-
-Required properties for a slot (Deprecated - Recommend to use one slot per host):
-
-* gpios: specifies a list of gpios used for command, clock and data bus. The
-  first gpio is the command line and the second gpio is the clock line. The
-  rest of the gpios (depending on the bus-width property) are the data lines in
-  no particular order. The format of the gpio specifier depends on the gpio
-  controller.
-(Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)
-
-Example:
-
-  The MSHC controller node can be split into two portions, SoC specific and
-  board specific portions as listed below.
-
-	dwmmc0@12200000 {
-		compatible = "samsung,exynos5250-dw-mshc";
-		reg = <0x12200000 0x1000>;
-		interrupts = <0 75 0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	dwmmc0@12200000 {
-		cap-mmc-highspeed;
-		cap-sd-highspeed;
-		broken-cd;
-		fifo-depth = <0x80>;
-		card-detect-delay = <200>;
-		samsung,dw-mshc-ciu-div = <3>;
-		samsung,dw-mshc-sdr-timing = <2 3>;
-		samsung,dw-mshc-ddr-timing = <1 2>;
-		samsung,dw-mshc-hs400-timing = <0 2>;
-		samsung,read-strobe-delay = <90>;
-		bus-width = <8>;
-	};
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
deleted file mode 100644
index 5e74db69f581..000000000000
--- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-MMC/SD/SDIO slot directly connected to a SPI bus
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the mmc_spi driver.
-
-Required properties:
-- spi-max-frequency : maximum frequency for this device (Hz).
-
-Optional properties:
-- voltage-ranges : two cells are required, first cell specifies minimum
-  slot voltage (mV), second cell specifies maximum slot voltage (mV).
-  Several ranges could be specified. If not provided, 3.2v..3.4v is assumed.
-- gpios : may specify GPIOs in this order: Card-Detect GPIO,
-  Write-Protect GPIO. Note that this does not follow the
-  binding from mmc.txt, for historical reasons.
-
-Example:
-
-	mmc-slot@0 {
-		compatible = "fsl,mpc8323rdb-mmc-slot",
-			     "mmc-spi-slot";
-		reg = <0>;
-		gpios = <&qe_pio_d 14 1
-			 &qe_pio_d 15 0>;
-		voltage-ranges = <3300 3300>;
-		spi-max-frequency = <50000000>;
-		interrupts = <42>;
-		interrupt-parent = <&PIC>;
-	};
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml
new file mode 100644
index 000000000000..c45b91099325
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMC/SD/SDIO slot directly connected to a SPI bus
+
+maintainers:
+  - Ulf Hansson <ulf.hansson@linaro.org>
+
+allOf:
+  - $ref: "mmc-controller.yaml"
+  - $ref: /schemas/spi/spi-peripheral-props.yaml
+
+description: |
+  The extra properties used by an mmc connected via SPI.
+
+properties:
+  compatible:
+    const: mmc-spi-slot
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency: true
+
+  interrupts:
+    maxItems: 1
+
+  voltage-ranges:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: |
+      Two cells are required, first cell specifies minimum slot voltage (mV),
+      second cell specifies maximum slot voltage (mV).
+    items:
+      - description: |
+          value for minimum slot voltage in mV
+        default: 3200
+      - description: |
+          value for maximum slot voltage in mV
+        default: 3400
+
+  gpios:
+    description: |
+      For historical reasons, this does not follow the generic mmc-controller
+      binding.
+    minItems: 1
+    items:
+      - description: Card-Detect GPIO
+      - description: Write-Protect GPIO
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      mmc@0 {
+        compatible = "mmc-spi-slot";
+        reg = <0>;
+        gpios = <&gpio 14 GPIO_ACTIVE_LOW>, <&gpio 15 GPIO_ACTIVE_HIGH>;
+        voltage-ranges = <3300 3300>;
+        spi-max-frequency = <50000000>;
+        interrupts = <42>;
+        interrupt-parent = <&PIC>;
+      };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 9ac4986988c5..14945ebc31d2 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -56,11 +56,15 @@ properties:
               - renesas,sdhi-r8a77980  # R-Car V3H
               - renesas,sdhi-r8a77990  # R-Car E3
               - renesas,sdhi-r8a77995  # R-Car D3
-              - renesas,sdhi-r8a779a0  # R-Car V3U
               - renesas,sdhi-r9a07g043 # RZ/G2UL
               - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
               - renesas,sdhi-r9a07g054 # RZ/V2L
           - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
+      - items:
+          - enum:
+              - renesas,sdhi-r8a779a0  # R-Car V3U
+              - renesas,sdhi-r8a779f0  # R-Car S4-8
+          - const: renesas,rcar-gen4-sdhi # R-Car Gen4
 
   reg:
     maxItems: 1
@@ -141,6 +145,7 @@ allOf:
               enum:
                 - renesas,rcar-gen2-sdhi
                 - renesas,rcar-gen3-sdhi
+                - renesas,rcar-gen4-sdhi
       then:
         properties:
           clocks:
diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
new file mode 100644
index 000000000000..fdaa18481aa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
+  Storage Host Controller
+
+maintainers:
+  - Jaehoon Chung <jh80.chung@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos4210-dw-mshc
+      - samsung,exynos4412-dw-mshc
+      - samsung,exynos5250-dw-mshc
+      - samsung,exynos5420-dw-mshc
+      - samsung,exynos5420-dw-mshc-smu
+      - samsung,exynos7-dw-mshc
+      - samsung,exynos7-dw-mshc-smu
+      - axis,artpec8-dw-mshc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+    description:
+      Handle to "biu" and "ciu" clocks for the
+      bus interface unit clock and the card interface unit clock.
+
+  clock-names:
+    items:
+      - const: biu
+      - const: ciu
+
+  samsung,dw-mshc-ciu-div:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 7
+    description:
+      The divider value for the card interface unit (ciu) clock.
+
+  samsung,dw-mshc-ddr-timing:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - description: CIU clock phase shift value for tx mode
+        minimum: 0
+        maximum: 7
+      - description: CIU clock phase shift value for rx mode
+        minimum: 0
+        maximum: 7
+    description:
+      The value of CUI clock phase shift value in transmit mode and CIU clock
+      phase shift value in receive mode for double data rate mode operation.
+      See also samsung,dw-mshc-hs400-timing property.
+
+  samsung,dw-mshc-hs400-timing:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - description: CIU clock phase shift value for tx mode
+        minimum: 0
+        maximum: 7
+      - description: CIU clock phase shift value for rx mode
+        minimum: 0
+        maximum: 7
+    description: |
+      The value of CIU TX and RX clock phase shift value for HS400 mode
+      operation.
+      Valid values for SDR and DDR CIU clock timing::
+        - valid value for tx phase shift and rx phase shift is 0 to 7.
+        - when CIU clock divider value is set to 3, all possible 8 phase shift
+          values can be used.
+        - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
+          phase shift clocks should be 0.
+      If missing, values from samsung,dw-mshc-ddr-timing property are used.
+
+  samsung,dw-mshc-sdr-timing:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - description: CIU clock phase shift value for tx mode
+        minimum: 0
+        maximum: 7
+      - description: CIU clock phase shift value for rx mode
+        minimum: 0
+        maximum: 7
+    description:
+      The value of CIU clock phase shift value in transmit mode and CIU clock
+      phase shift value in receive mode for single data rate mode operation.
+      See also samsung,dw-mshc-hs400-timing property.
+
+  samsung,read-strobe-delay:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
+      line in Read path). If missing, default from hardware is used.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - samsung,dw-mshc-ddr-timing
+  - samsung,dw-mshc-sdr-timing
+
+allOf:
+  - $ref: "synopsys-dw-mshc-common.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - samsung,exynos5250-dw-mshc
+              - samsung,exynos5420-dw-mshc
+              - samsung,exynos7-dw-mshc
+              - samsung,exynos7-dw-mshc-smu
+              - axis,artpec8-dw-mshc
+    then:
+      required:
+        - samsung,dw-mshc-ciu-div
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos5420.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mmc@12220000 {
+        compatible = "samsung,exynos5420-dw-mshc";
+        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x12220000 0x1000>;
+        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+        clock-names = "biu", "ciu";
+        fifo-depth = <0x40>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        max-frequency = <200000000>;
+        vmmc-supply = <&ldo19_reg>;
+        vqmmc-supply = <&ldo13_reg>;
+        sd-uhs-sdr50;
+        sd-uhs-sdr104;
+        sd-uhs-ddr50;
+    };
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index e4236334e748..31a3ce208e1a 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -17,6 +17,9 @@ description:
 properties:
   compatible:
     oneOf:
+      - enum:
+          - qcom,sdhci-msm-v4
+        deprecated: true
       - items:
           - enum:
               - qcom,apq8084-sdhci
@@ -27,6 +30,9 @@ properties:
               - qcom,msm8992-sdhci
               - qcom,msm8994-sdhci
               - qcom,msm8996-sdhci
+          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
+      - items:
+          - enum:
               - qcom,qcs404-sdhci
               - qcom,sc7180-sdhci
               - qcom,sc7280-sdhci
@@ -38,12 +44,7 @@ properties:
               - qcom,sm6350-sdhci
               - qcom,sm8150-sdhci
               - qcom,sm8250-sdhci
-          - enum:
-              - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
-              - qcom,sdhci-msm-v5 # for sdcc version 5.0
-      - items:
-          - const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility)
-                                     # for sdcc versions less than 5.0
+          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
 
   reg:
     minItems: 1
@@ -53,6 +54,28 @@ properties:
       - description: CQE register map
       - description: Inline Crypto Engine register map
 
+  reg-names:
+    minItems: 1
+    maxItems: 4
+    oneOf:
+      - items:
+          - const: hc_mem
+      - items:
+          - const: hc_mem
+          - const: core_mem
+      - items:
+          - const: hc_mem
+          - const: cqe_mem
+      - items:
+          - const: hc_mem
+          - const: cqe_mem
+          - const: ice_mem
+      - items:
+          - const: hc_mem
+          - const: core_mem
+          - const: cqe_mem
+          - const: ice_mem
+
   clocks:
     minItems: 3
     items:
@@ -121,6 +144,16 @@ properties:
     description: A phandle to sdhci power domain node
     maxItems: 1
 
+  mmc-ddr-1_8v: true
+
+  mmc-hs200-1_8v: true
+
+  mmc-hs400-1_8v: true
+
+  bus-width: true
+
+  max-frequency: true
+
 patternProperties:
   '^opp-table(-[a-z0-9]+)?$':
     if:
@@ -140,7 +173,10 @@ required:
   - clock-names
   - interrupts
 
-additionalProperties: true
+allOf:
+  - $ref: mmc-controller.yaml#
+
+unevaluatedProperties: false
 
 examples:
   - |
@@ -149,7 +185,7 @@ examples:
     #include <dt-bindings/clock/qcom,rpmh.h>
     #include <dt-bindings/power/qcom-rpmpd.h>
 
-    sdhc_2: sdhci@8804000 {
+    sdhc_2: mmc@8804000 {
       compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
       reg = <0 0x08804000 0 0x1000>;
 
diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.yaml b/Documentation/devicetree/bindings/mtd/mxc-nand.yaml
index 73b86f2226c7..66da1b476ab7 100644
--- a/Documentation/devicetree/bindings/mtd/mxc-nand.yaml
+++ b/Documentation/devicetree/bindings/mtd/mxc-nand.yaml
@@ -37,6 +37,4 @@ examples:
         compatible = "fsl,imx27-nand";
         reg = <0xd8000000 0x1000>;
         interrupts = <29>;
-        nand-bus-width = <8>;
-        nand-ecc-mode = "hw";
     };
diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
index 84ad7ff30121..482a2c068740 100644
--- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
@@ -102,6 +102,31 @@ allOf:
             - const: rx
             - const: cmd
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq806x-nand
+
+    then:
+      properties:
+        qcom,boot-partitions:
+          $ref: /schemas/types.yaml#/definitions/uint32-matrix
+          items:
+            items:
+              - description: offset
+              - description: size
+          description:
+            Boot partition use a different layout where the 4 bytes of spare
+            data are not protected by ECC. Use this to declare these special
+            partitions by defining first the offset and then the size.
+
+            It's in the form of <offset1 size1 offset2 size2 offset3 ...>
+            and should be declared in ascending order.
+
+            Refer to the ipq8064 example on how to use this special binding.
+
 required:
   - compatible
   - reg
@@ -135,6 +160,8 @@ examples:
         nand-ecc-strength = <4>;
         nand-bus-width = <8>;
 
+        qcom,boot-partitions = <0x0 0x58a0000>;
+
         partitions {
           compatible = "fixed-partitions";
           #address-cells = <1>;
diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml b/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml
index 5aac094fd217..df59575840fe 100644
--- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml
+++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml
@@ -23,6 +23,7 @@ properties:
       - brcm,bcm4345c5
       - brcm,bcm43540-bt
       - brcm,bcm4335a0
+      - brcm,bcm4349-bt
 
   shutdown-gpios:
     maxItems: 1
@@ -92,6 +93,13 @@ properties:
        pcm-sync-mode: slave, master
        pcm-clock-mode: slave, master
 
+  brcm,requires-autobaud-mode:
+    type: boolean
+    description:
+      Set this property if autobaud mode is required. Autobaud mode is required
+      if the device's initial baud rate in normal mode is not supported by the
+      host or if the device requires autobaud mode startup before loading FW.
+
   interrupts:
     items:
       - description: Handle to the line HOST_WAKE used to wake
diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
new file mode 100644
index 000000000000..a3bf432960d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -0,0 +1,404 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT7530 Ethernet switch
+
+maintainers:
+  - Sean Wang <sean.wang@mediatek.com>
+  - Landen Chao <Landen.Chao@mediatek.com>
+  - DENG Qingfang <dqfext@gmail.com>
+
+description: |
+  Port 5 of mt7530 and mt7621 switch is muxed between:
+  1. GMAC5: GMAC5 can interface with another external MAC or PHY.
+  2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
+     of the SOC. Used in many setups where port 0/4 becomes the WAN port.
+     Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
+       GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
+       connected to external component!
+
+  Port 5 modes/configurations:
+  1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
+     GMAC of the SOC.
+     In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
+     GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
+  2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
+     It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
+     and RGMII delay.
+  3. Port 5 is muxed to GMAC5 and can interface to an external phy.
+     Port 5 becomes an extra switch port.
+     Only works on platform where external phy TX<->RX lines are swapped.
+     Like in the Ubiquiti ER-X-SFP.
+  4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
+     Currently a 2nd CPU port is not supported by DSA code.
+
+  Depending on how the external PHY is wired:
+  1. normal: The PHY can only connect to 2nd GMAC but not to the switch
+  2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
+     a ethernet port. But can't interface to the 2nd GMAC.
+
+    Based on the DT the port 5 mode is configured.
+
+  Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
+  When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
+  phy-mode must be set, see also example 2 below!
+  * mt7621: phy-mode = "rgmii-txid";
+  * mt7623: phy-mode = "rgmii";
+
+  CPU-Ports need a phy-mode property:
+    Allowed values on mt7530 and mt7621:
+      - "rgmii"
+      - "trgmii"
+    On mt7531:
+      - "1000base-x"
+      - "2500base-x"
+      - "rgmii"
+      - "sgmii"
+
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt7530
+      - mediatek,mt7531
+      - mediatek,mt7621
+
+  core-supply:
+    description:
+      Phandle to the regulator node necessary for the core power.
+
+  "#gpio-cells":
+    const: 2
+
+  gpio-controller:
+    type: boolean
+    description:
+      if defined, MT7530's LED controller will run on GPIO mode.
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  io-supply:
+    description:
+      Phandle to the regulator node necessary for the I/O power.
+      See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
+      for details for the regulator setup on these boards.
+
+  mediatek,mcm:
+    type: boolean
+    description:
+      if defined, indicates that either MT7530 is the part on multi-chip
+      module belong to MT7623A has or the remotely standalone chip as the
+      function MT7623N reference board provided for.
+
+  reset-gpios:
+    maxItems: 1
+
+  reset-names:
+    const: mcm
+
+  resets:
+    description:
+      Phandle pointing to the system reset controller with line index for
+      the ethsys.
+    maxItems: 1
+
+patternProperties:
+  "^(ethernet-)?ports$":
+    type: object
+
+    patternProperties:
+      "^(ethernet-)?port@[0-9]+$":
+        type: object
+        description: Ethernet switch ports
+
+        unevaluatedProperties: false
+
+        properties:
+          reg:
+            description:
+              Port address described must be 5 or 6 for CPU port and from 0
+              to 5 for user ports.
+
+        allOf:
+          - $ref: dsa-port.yaml#
+          - if:
+              properties:
+                label:
+                  items:
+                    - const: cpu
+            then:
+              required:
+                - reg
+                - phy-mode
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: "dsa.yaml#"
+  - if:
+      required:
+        - mediatek,mcm
+    then:
+      required:
+        - resets
+        - reset-names
+
+  - dependencies:
+      interrupt-controller: [ interrupts ]
+
+  - if:
+      properties:
+        compatible:
+          items:
+            - const: mediatek,mt7530
+    then:
+      required:
+        - core-supply
+        - io-supply
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        switch@0 {
+            compatible = "mediatek,mt7530";
+            reg = <0>;
+
+            core-supply = <&mt6323_vpa_reg>;
+            io-supply = <&mt6323_vemc3v3_reg>;
+            reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
+
+            ethernet-ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                    reg = <0>;
+                    label = "lan0";
+                };
+
+                port@1 {
+                    reg = <1>;
+                    label = "lan1";
+                };
+
+                port@2 {
+                    reg = <2>;
+                    label = "lan2";
+                };
+
+                port@3 {
+                    reg = <3>;
+                    label = "lan3";
+                };
+
+                port@4 {
+                    reg = <4>;
+                    label = "wan";
+                };
+
+                port@6 {
+                    reg = <6>;
+                    label = "cpu";
+                    ethernet = <&gmac0>;
+                    phy-mode = "trgmii";
+                    fixed-link {
+                        speed = <1000>;
+                        full-duplex;
+                    };
+                };
+            };
+        };
+    };
+
+  - |
+    //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
+
+    ethernet {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        gmac0: mac@0 {
+            compatible = "mediatek,eth-mac";
+            reg = <0>;
+            phy-mode = "rgmii";
+
+            fixed-link {
+                speed = <1000>;
+                full-duplex;
+                pause;
+            };
+        };
+
+        gmac1: mac@1 {
+            compatible = "mediatek,eth-mac";
+            reg = <1>;
+            phy-mode = "rgmii-txid";
+            phy-handle = <&phy4>;
+        };
+
+        mdio: mdio-bus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* Internal phy */
+            phy4: ethernet-phy@4 {
+                reg = <4>;
+            };
+
+            mt7530: switch@1f {
+                compatible = "mediatek,mt7621";
+                reg = <0x1f>;
+                mediatek,mcm;
+
+                resets = <&rstctrl 2>;
+                reset-names = "mcm";
+
+                ethernet-ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+                        label = "lan0";
+                    };
+
+                    port@1 {
+                        reg = <1>;
+                        label = "lan1";
+                    };
+
+                    port@2 {
+                        reg = <2>;
+                        label = "lan2";
+                    };
+
+                    port@3 {
+                        reg = <3>;
+                        label = "lan3";
+                    };
+
+                    /* Commented out. Port 4 is handled by 2nd GMAC.
+                    port@4 {
+                        reg = <4>;
+                        label = "lan4";
+                    };
+                    */
+
+                    port@6 {
+                        reg = <6>;
+                        label = "cpu";
+                        ethernet = <&gmac0>;
+                        phy-mode = "rgmii";
+
+                        fixed-link {
+                            speed = <1000>;
+                            full-duplex;
+                            pause;
+                        };
+                    };
+                };
+            };
+        };
+    };
+
+  - |
+    //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
+
+    ethernet {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        gmac_0: mac@0 {
+            compatible = "mediatek,eth-mac";
+            reg = <0>;
+            phy-mode = "rgmii";
+
+            fixed-link {
+                speed = <1000>;
+                full-duplex;
+                pause;
+            };
+        };
+
+        mdio0: mdio-bus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* External phy */
+            ephy5: ethernet-phy@7 {
+                reg = <7>;
+            };
+
+            switch@1f {
+                compatible = "mediatek,mt7621";
+                reg = <0x1f>;
+                mediatek,mcm;
+
+                resets = <&rstctrl 2>;
+                reset-names = "mcm";
+
+                ethernet-ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+                        label = "lan0";
+                    };
+
+                    port@1 {
+                        reg = <1>;
+                        label = "lan1";
+                    };
+
+                    port@2 {
+                        reg = <2>;
+                        label = "lan2";
+                    };
+
+                    port@3 {
+                        reg = <3>;
+                        label = "lan3";
+                    };
+
+                    port@4 {
+                        reg = <4>;
+                        label = "lan4";
+                    };
+
+                    port@5 {
+                        reg = <5>;
+                        label = "lan5";
+                        phy-mode = "rgmii";
+                        phy-handle = <&ephy5>;
+                    };
+
+                    cpu_port0: port@6 {
+                        reg = <6>;
+                        label = "cpu";
+                        ethernet = <&gmac_0>;
+                        phy-mode = "rgmii";
+
+                        fixed-link {
+                            speed = <1000>;
+                            full-duplex;
+                            pause;
+                        };
+                    };
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
deleted file mode 100644
index 18247ebfc487..000000000000
--- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
+++ /dev/null
@@ -1,327 +0,0 @@
-Mediatek MT7530 Ethernet switch
-================================
-
-Required properties:
-
-- compatible: may be compatible = "mediatek,mt7530"
-	or compatible = "mediatek,mt7621"
-	or compatible = "mediatek,mt7531"
-- #address-cells: Must be 1.
-- #size-cells: Must be 0.
-- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
-	on multi-chip module belong to MT7623A has or the remotely standalone
-	chip as the function MT7623N reference board provided for.
-
-If compatible mediatek,mt7530 is set then the following properties are required
-
-- core-supply: Phandle to the regulator node necessary for the core power.
-- io-supply: Phandle to the regulator node necessary for the I/O power.
-	See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
-	for details for the regulator setup on these boards.
-
-If the property mediatek,mcm isn't defined, following property is required
-
-- reset-gpios: Should be a gpio specifier for a reset line.
-
-Else, following properties are required
-
-- resets : Phandle pointing to the system reset controller with
-	line index for the ethsys.
-- reset-names : Should be set to "mcm".
-
-Required properties for the child nodes within ports container:
-
-- reg: Port address described must be 6 for CPU port and from 0 to 5 for
-	user ports.
-- phy-mode: String, the following values are acceptable for port labeled
-	"cpu":
-	If compatible mediatek,mt7530 or mediatek,mt7621 is set,
-	must be either "trgmii" or "rgmii"
-	If compatible mediatek,mt7531 is set,
-	must be either "sgmii", "1000base-x" or "2500base-x"
-
-Port 5 of mt7530 and mt7621 switch is muxed between:
-1. GMAC5: GMAC5 can interface with another external MAC or PHY.
-2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
-   of the SOC. Used in many setups where port 0/4 becomes the WAN port.
-   Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
-	 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
-	 connected to external component!
-
-Port 5 modes/configurations:
-1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
-   GMAC of the SOC.
-   In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
-   GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
-2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
-   It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
-   and RGMII delay.
-3. Port 5 is muxed to GMAC5 and can interface to an external phy.
-   Port 5 becomes an extra switch port.
-   Only works on platform where external phy TX<->RX lines are swapped.
-   Like in the Ubiquiti ER-X-SFP.
-4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
-   Currently a 2nd CPU port is not supported by DSA code.
-
-Depending on how the external PHY is wired:
-1. normal: The PHY can only connect to 2nd GMAC but not to the switch
-2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
-   a ethernet port. But can't interface to the 2nd GMAC.
-
-Based on the DT the port 5 mode is configured.
-
-Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
-When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
-phy-mode must be set, see also example 2 below!
- * mt7621: phy-mode = "rgmii-txid";
- * mt7623: phy-mode = "rgmii";
-
-Optional properties:
-
-- gpio-controller: Boolean; if defined, MT7530's LED controller will run on
-	GPIO mode.
-- #gpio-cells: Must be 2 if gpio-controller is defined.
-- interrupt-controller: Boolean; Enables the internal interrupt controller.
-
-If interrupt-controller is defined, the following properties are required.
-
-- #interrupt-cells: Must be 1.
-- interrupts: Parent interrupt for the interrupt controller.
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
-required, optional properties and how the integrated switch subnodes must
-be specified.
-
-Example:
-
-	&mdio0 {
-		switch@0 {
-			compatible = "mediatek,mt7530";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-
-			core-supply = <&mt6323_vpa_reg>;
-			io-supply = <&mt6323_vemc3v3_reg>;
-			reset-gpios = <&pio 33 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0>;
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@4 {
-					reg = <4>;
-					label = "wan";
-				};
-
-				port@6 {
-					reg = <6>;
-					label = "cpu";
-					ethernet = <&gmac0>;
-					phy-mode = "trgmii";
-					fixed-link {
-						speed = <1000>;
-						full-duplex;
-					};
-				};
-			};
-		};
-	};
-
-Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
-
-&eth {
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "rgmii";
-
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "rgmii-txid";
-		phy-handle = <&phy4>;
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* Internal phy */
-		phy4: ethernet-phy@4 {
-			reg = <4>;
-		};
-
-		mt7530: switch@1f {
-			compatible = "mediatek,mt7621";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1f>;
-			pinctrl-names = "default";
-			mediatek,mcm;
-
-			resets = <&rstctrl 2>;
-			reset-names = "mcm";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-/* Commented out. Port 4 is handled by 2nd GMAC.
-				port@4 {
-					reg = <4>;
-					label = "lan4";
-				};
-*/
-
-				cpu_port0: port@6 {
-					reg = <6>;
-					label = "cpu";
-					ethernet = <&gmac0>;
-					phy-mode = "rgmii";
-
-					fixed-link {
-						speed = <1000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
-
-Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
-
-&eth {
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "rgmii";
-
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* External phy */
-		ephy5: ethernet-phy@7 {
-			reg = <7>;
-		};
-
-		mt7530: switch@1f {
-			compatible = "mediatek,mt7621";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x1f>;
-			pinctrl-names = "default";
-			mediatek,mcm;
-
-			resets = <&rstctrl 2>;
-			reset-names = "mcm";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "lan0";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "lan2";
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "lan3";
-				};
-
-				port@4 {
-					reg = <4>;
-					label = "lan4";
-				};
-
-				port@5 {
-					reg = <5>;
-					label = "lan5";
-					phy-mode = "rgmii";
-					phy-handle = <&ephy5>;
-				};
-
-				cpu_port0: port@6 {
-					reg = <6>;
-					label = "cpu";
-					ethernet = <&gmac0>;
-					phy-mode = "rgmii";
-
-					fixed-link {
-						speed = <1000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.yaml b/Documentation/devicetree/bindings/net/ti,dp83867.yaml
index 047d757e8d82..76ff08a477ba 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83867.yaml
+++ b/Documentation/devicetree/bindings/net/ti,dp83867.yaml
@@ -31,6 +31,16 @@ properties:
   reg:
     maxItems: 1
 
+  nvmem-cells:
+    maxItems: 1
+    description:
+      Nvmem data cell containing the value to write to the
+      IO_IMPEDANCE_CTRL field of the IO_MUX_CFG register.
+
+  nvmem-cell-names:
+    items:
+      - const: io_impedance_ctrl
+
   ti,min-output-impedance:
     type: boolean
     description: |
@@ -42,9 +52,11 @@ properties:
     description: |
       MAC Interface Impedance control to set the programmable output impedance
       to a maximum value (70 ohms).
-      Note: ti,min-output-impedance and ti,max-output-impedance are mutually
-        exclusive. When both properties are present ti,max-output-impedance
-        takes precedence.
+      Note: Specifying an io_impedance_ctrl nvmem cell or one of the
+        ti,min-output-impedance, ti,max-output-impedance properties
+        are mutually exclusive. If more than one is present, an nvmem
+        cell takes precedence over ti,max-output-impedance, which in
+        turn takes precedence over ti,min-output-impedance.
 
   tx-fifo-depth:
     $ref: /schemas/types.yaml#/definitions/uint32
diff --git a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.yaml b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.yaml
index 8cd0adbf7021..7029cb1f38ff 100644
--- a/Documentation/devicetree/bindings/net/wireless/qca,ath9k.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qca,ath9k.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Atheros ath9k wireless devices Generic Binding
 
 maintainers:
-  - Kalle Valo <kvalo@codeaurora.org>
+  - Toke Høiland-Jørgensen <toke@toke.dk>
 
 description: |
   This node provides properties for configuring the ath9k wireless device.
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
index 8c01fdba134b..a677b056f112 100644
--- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
@@ -9,7 +9,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath11k wireless devices Generic Binding
 
 maintainers:
-  - Kalle Valo <kvalo@codeaurora.org>
+  - Kalle Valo <kvalo@kernel.org>
 
 description: |
   These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax
diff --git a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
new file mode 100644
index 000000000000..92d8ade988f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/xlnx,emaclite.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Emaclite Ethernet controller
+
+maintainers:
+  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
+  - Harini Katakam <harini.katakam@amd.com>
+
+allOf:
+  - $ref: ethernet-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - xlnx,opb-ethernetlite-1.01.a
+      - xlnx,opb-ethernetlite-1.01.b
+      - xlnx,xps-ethernetlite-1.00.a
+      - xlnx,xps-ethernetlite-2.00.a
+      - xlnx,xps-ethernetlite-2.01.a
+      - xlnx,xps-ethernetlite-3.00.a
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  phy-handle: true
+
+  local-mac-address: true
+
+  xlnx,tx-ping-pong:
+    type: boolean
+    description: hardware supports tx ping pong buffer.
+
+  xlnx,rx-ping-pong:
+    type: boolean
+    description: hardware supports rx ping pong buffer.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - phy-handle
+
+additionalProperties: false
+
+examples:
+  - |
+    axi_ethernetlite_1: ethernet@40e00000 {
+        compatible = "xlnx,xps-ethernetlite-3.00.a";
+        reg = <0x40e00000 0x10000>;
+        interrupt-parent = <&axi_intc_1>;
+        interrupts = <1>;
+        local-mac-address = [00 00 00 00 00 00];
+        phy-handle = <&phy0>;
+        xlnx,rx-ping-pong;
+        xlnx,tx-ping-pong;
+    };
diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
new file mode 100644
index 000000000000..7c7233e29ecf
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek efuse
+
+description: |
+  MediaTek's efuse is used for storing calibration data, it can be accessed
+  on ARM devices usiong I/O mapped memory.
+
+maintainers:
+  - Andrew-CT Chen <andrew-ct.chen@mediatek.com>
+  - Lala Lin <lala.lin@mediatek.com>
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  $nodename:
+    pattern: "^efuse@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - mediatek,mt7622-efuse
+              - mediatek,mt7623-efuse
+              - mediatek,mt8173-efuse
+              - mediatek,mt8183-efuse
+              - mediatek,mt8192-efuse
+              - mediatek,mt8195-efuse
+              - mediatek,mt8516-efuse
+          - const: mediatek,efuse
+      - const: mediatek,mt8173-efuse
+        deprecated: true
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    efuse@11c10000 {
+        compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
+        reg = <0x11c10000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        u3_tx_imp_p0: usb3-tx-imp@184,1 {
+            reg = <0x184 0x1>;
+            bits = <0 5>;
+        };
+        u3_rx_imp_p0: usb3-rx-imp@184,2 {
+            reg = <0x184 0x2>;
+            bits = <5 5>;
+        };
+        u3_intr_p0: usb3-intr@185 {
+            reg = <0x185 0x1>;
+            bits = <2 6>;
+        };
+        comb_tx_imp_p1: usb3-tx-imp@186,1 {
+            reg = <0x186 0x1>;
+            bits = <0 5>;
+        };
+        comb_rx_imp_p1: usb3-rx-imp@186,2 {
+            reg = <0x186 0x2>;
+            bits = <5 5>;
+        };
+        comb_intr_p1: usb3-intr@187 {
+            reg = <0x187 0x1>;
+            bits = <2 6>;
+        };
+        u2_intr_p0: usb2-intr-p0@188,1 {
+            reg = <0x188 0x1>;
+            bits = <0 5>;
+        };
+        u2_intr_p1: usb2-intr-p1@188,2 {
+            reg = <0x188 0x2>;
+            bits = <5 5>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
new file mode 100644
index 000000000000..c3c96fd0baac
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip SAMA7G5 OTP Controller (OTPC)
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+description: |
+  OTP controller drives a NVMEM memory where system specific data
+  (e.g. calibration data for analog cells, hardware configuration
+  settings, chip identifiers) or user specific data could be stored.
+
+allOf:
+  - $ref: "nvmem.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: microchip,sama7g5-otpc
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
+
+    otpc: efuse@e8c00000 {
+        compatible = "microchip,sama7g5-otpc", "syscon";
+        reg = <0xe8c00000 0xec>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        temperature_calib: calib@1 {
+            reg = <OTP_PKT(1) 76>;
+        };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt
deleted file mode 100644
index 39d529599444..000000000000
--- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-= Mediatek MTK-EFUSE device tree bindings =
-
-This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
-
-Required properties:
-- compatible: should be
-	      "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
-	      "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
-	      "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
-	      "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
-	      "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195
-	      "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
-- reg: Should contain registers location and length
-- bits: contain the bits range by offset and size
-
-= Data cells =
-Are child nodes of MTK-EFUSE, bindings of which as described in
-bindings/nvmem/nvmem.txt
-
-Example:
-
-	efuse: efuse@10206000 {
-		compatible = "mediatek,mt8173-efuse";
-		reg	   = <0 0x10206000 0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* Data cells */
-		thermal_calibration: calib@528 {
-			reg = <0x528 0xc>;
-		};
-	};
-
-= Data consumers =
-Are device nodes which consume nvmem data cells.
-
-For example:
-
-	thermal {
-		...
-		nvmem-cells = <&thermal_calibration>;
-		nvmem-cell-names = "calibration";
-	};
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index dede8892ee01..b4163086a5be 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -18,6 +18,7 @@ properties:
       - enum:
           - qcom,apq8064-qfprom
           - qcom,apq8084-qfprom
+          - qcom,ipq8064-qfprom
           - qcom,msm8974-qfprom
           - qcom,msm8916-qfprom
           - qcom,msm8996-qfprom
@@ -25,6 +26,7 @@ properties:
           - qcom,qcs404-qfprom
           - qcom,sc7180-qfprom
           - qcom,sc7280-qfprom
+          - qcom,sdm630-qfprom
           - qcom,sdm845-qfprom
       - const: qcom,qfprom
 
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 0b69b12b849e..c40ba753707c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -11,7 +11,7 @@ maintainers:
   - Stanimir Varbanov <svarbanov@mm-sol.com>
 
 description: |
-  Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
+  Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
   PCIe IP.
 
 properties:
diff --git a/Documentation/devicetree/bindings/perf/arm,ccn.yaml b/Documentation/devicetree/bindings/perf/arm,ccn.yaml
new file mode 100644
index 000000000000..0b0bb2091016
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm,ccn.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,ccn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM CCN (Cache Coherent Network) Performance Monitors
+
+maintainers:
+  - Robin Murphy <robin.murphy@arm.com>
+
+properties:
+  compatible:
+    enum:
+      - arm,ccn-502
+      - arm,ccn-504
+      - arm,ccn-508
+      - arm,ccn-512
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    ccn@20000000 {
+        compatible = "arm,ccn-504";
+        reg = <0x20000000 0x1000000>;
+        interrupts = <0 181 4>;
+    };
+...
diff --git a/Documentation/devicetree/bindings/perf/arm-ccn.txt b/Documentation/devicetree/bindings/perf/arm-ccn.txt
deleted file mode 100644
index 1c53b5aa3317..000000000000
--- a/Documentation/devicetree/bindings/perf/arm-ccn.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* ARM CCN (Cache Coherent Network)
-
-Required properties:
-
-- compatible: (standard compatible string) should be one of:
-	"arm,ccn-502"
-	"arm,ccn-504"
-	"arm,ccn-508"
-	"arm,ccn-512"
-
-- reg: (standard registers property) physical address and size
-	(16MB) of the configuration registers block
-
-- interrupts: (standard interrupt property) single interrupt
-	generated by the control block
-
-Example:
-
-	ccn@2000000000 {
-		compatible = "arm,ccn-504";
-		reg = <0x20 0x00000000 0 0x1000000>;
-		interrupts = <0 181 4>;
-	};
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
index 6e4d795f9b02..9c2a7345955d 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
@@ -24,6 +24,10 @@ properties:
           - enum:
               - mediatek,mt7623-mipi-tx
           - const: mediatek,mt2701-mipi-tx
+      - items:
+          - enum:
+              - mediatek,mt8365-mipi-tx
+          - const: mediatek,mt8183-mipi-tx
       - const: mediatek,mt2701-mipi-tx
       - const: mediatek,mt8173-mipi-tx
       - const: mediatek,mt8183-mipi-tx
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index 7b2e1bc119be..4b638c1d4221 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -82,6 +82,7 @@ properties:
               - mediatek,mt8183-tphy
               - mediatek,mt8186-tphy
               - mediatek,mt8192-tphy
+              - mediatek,mt8365-tphy
           - const: mediatek,generic-tphy-v2
       - items:
           - enum:
diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
index c9f5c0caf8a9..c9e392c64a7c 100644
--- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt
@@ -8,6 +8,7 @@ Required properties:
 	* "fsl,vf610-usbphy" for Vybrid vf610
 	* "fsl,imx6sx-usbphy" for imx6sx
 	* "fsl,imx7ulp-usbphy" for imx7ulp
+	* "fsl,imx8dxl-usbphy" for imx8dxl
   "fsl,imx23-usbphy" is still a fallback for other strings
 - reg: Should contain registers location and length
 - interrupts: Should contain phy interrupt
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
index a5850ff529f8..cf9e9b8011cb 100644
--- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
@@ -41,6 +41,9 @@ properties:
   "#phy-cells":
     const: 0
 
+  vdda-phy-supply: true
+  vdda-pll-supply: true
+
 required:
   - compatible
   - reg
@@ -65,5 +68,8 @@ examples:
 
       #clock-cells = <1>;
       #phy-cells = <0>;
+
+      vdda-phy-supply = <&vdd_a_edp_0_1p2>;
+      vdda-pll-supply = <&vdd_a_edp_0_0p9>;
     };
 ...
diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
new file mode 100644
index 000000000000..fdb277edebeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon HDMI phy
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-phy-8660
+      - qcom,hdmi-phy-8960
+      - qcom,hdmi-phy-8974
+      - qcom,hdmi-phy-8084
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: hdmi_phy
+      - const: hdmi_pll
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  power-domains:
+    maxItems: 1
+
+  core-vdda-supply:
+    description: phandle to VDDA supply regulator
+
+  vddio-supply:
+    description: phandle to VDD I/O supply regulator
+
+  '#phy-cells':
+    const: 0
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-phy-8660
+              - qcom,hdmi-phy-8960
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: slave_iface
+        vddio-supply: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,hdmi-phy-8084
+              - qcom,hdmi-phy-8974
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+        clock-names:
+          items:
+            - const: iface
+            - const: alt_iface
+
+required:
+  - compatible
+  - clocks
+  - reg
+  - reg-names
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    hdmi_phy: phy@4a00400 {
+      compatible = "qcom,hdmi-phy-8960";
+      reg-names = "hdmi_phy",
+                  "hdmi_pll";
+      reg = <0x4a00400 0x60>,
+            <0x4a00500 0x100>;
+      #phy-cells = <0>;
+      power-domains = <&mmcc 1>;
+      clock-names = "slave_iface";
+      clocks = <&clk 21>;
+      core-vdda-supply = <&pm8921_hdmi_mvs>;
+    };
diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
new file mode 100644
index 000000000000..eea2e02678ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Adreno/Snapdragon QMP HDMI phy
+
+maintainers:
+  - Rob Clark <robdclark@gmail.com>
+
+properties:
+  compatible:
+    enum:
+      - qcom,hdmi-phy-8996
+
+  reg:
+    maxItems: 6
+
+  reg-names:
+    items:
+      - const: hdmi_pll
+      - const: hdmi_tx_l0
+      - const: hdmi_tx_l1
+      - const: hdmi_tx_l2
+      - const: hdmi_tx_l3
+      - const: hdmi_phy
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: iface
+      - const: ref
+
+  power-domains:
+    maxItems: 1
+
+  vcca-supply:
+    description: phandle to VCCA supply regulator
+
+  vddio-supply:
+    description: phandle to VDD I/O supply regulator
+
+  '#phy-cells':
+    const: 0
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    hdmi-phy@9a0600 {
+      compatible = "qcom,hdmi-phy-8996";
+      reg = <0x009a0600 0x1c4>,
+            <0x009a0a00 0x124>,
+            <0x009a0c00 0x124>,
+            <0x009a0e00 0x124>,
+            <0x009a1000 0x124>,
+            <0x009a1200 0x0c8>;
+      reg-names = "hdmi_pll",
+                  "hdmi_tx_l0",
+                  "hdmi_tx_l1",
+                  "hdmi_tx_l2",
+                  "hdmi_tx_l3",
+                  "hdmi_phy";
+
+      clocks = <&mmcc 116>,
+               <&gcc 214>;
+      clock-names = "iface",
+                    "ref";
+      #phy-cells = <0>;
+
+      vddio-supply = <&vreg_l12a_1p8>;
+      vcca-supply = <&vreg_l28a_0p925>;
+    };
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
index b8483f9edbfc..fe57c5373d18 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
@@ -34,7 +34,7 @@ properties:
     # must not be 0.
     minItems: 2
     items:
-      - const: usb3-if # The funcional clock
+      - const: usb3-if # The functional clock
       - const: usb3s_clk # The usb3's external clock
       - const: usb_extal # The usb2's external clock
 
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index f6ed1a005e7a..8da99461e817 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - samsung,exynos7-ufs-phy
       - samsung,exynosautov9-ufs-phy
+      - tesla,fsd-ufs-phy
 
   reg:
     maxItems: 1
@@ -40,9 +41,17 @@ properties:
       - const: tx0_symbol_clk
 
   samsung,pmu-syscon:
-    $ref: '/schemas/types.yaml#/definitions/phandle'
-    description: phandle for PMU system controller interface, used to
-                 control pmu registers bits for ufs m-phy
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    maxItems: 1
+    items:
+      minItems: 1
+      items:
+        - description: phandle for PMU system controller interface, used to
+                       control pmu registers bits for ufs m-phy
+        - description: offset of the pmu control register
+    description:
+      It can be phandle/offset pair. The second cell which can represent an
+      offset is optional.
 
 required:
   - "#phy-cells"
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index bfce850c2035..fa0c2df04675 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -80,9 +80,6 @@ properties:
       - const: hosc
       - const: losc
 
-  resets:
-    maxItems: 1
-
   gpio-controller: true
   interrupt-controller: true
   gpio-line-names: true
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
deleted file mode 100644
index e0e886b73527..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Device tree binding for NVIDIA Tegra DPAUX pad controller
-========================================================
-
-The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
-which can be assigned to either the DPAUX channel or to an I2C
-controller.
-
-This document defines the device-specific binding for the DPAUX pad
-controller. Refer to pinctrl-bindings.txt in this directory for generic
-information about pin controller device tree bindings. Please refer to
-the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
-details on the DPAUX binding.
-
-Pin muxing:
------------
-
-Child nodes contain the pinmux configurations following the conventions
-from the pinctrl-bindings.txt document.
-
-Since only three configurations are possible, only three child nodes are
-needed to describe the pin mux'ing options for the DPAUX pads.
-Furthermore, given that the pad functions are only applicable to a
-single set of pads, the child nodes only need to describe the pad group
-the functions are being applied to rather than the individual pads.
-
-Required properties:
-- groups: Must be "dpaux-io"
-- function: Must be either "aux", "i2c" or "off".
-
-Example:
---------
-
-	dpaux@545c0000 {
-		...
-
-		state_dpaux_aux: pinmux-aux {
-			groups = "dpaux-io";
-			function = "aux";
-		};
-
-		state_dpaux_i2c: pinmux-i2c {
-			groups = "dpaux-io";
-			function = "i2c";
-		};
-
-		state_dpaux_off: pinmux-off {
-			groups = "dpaux-io";
-			function = "off";
-		};
-	};
-
-	...
-
-	i2c@7000d100 {
-		...
-		pinctrl-0 = <&state_dpaux_i2c>;
-		pinctrl-1 = <&state_dpaux_off>;
-		pinctrl-names = "default", "idle";
-	};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
index c90a132fbc79..e39f5893bf16 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml
@@ -80,46 +80,24 @@ patternProperties:
               dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
             enum: [2, 4, 6, 8, 10, 12, 14, 16]
 
-          mediatek,drive-strength-adv:
-            description: |
-              Describe the specific driving setup property.
-              For I2C pins, the existing generic driving setup can only support
-              2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
-              can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
-              driving setup, the existing generic setup will be disabled.
-              The specific driving setup is controlled by E1E0EN.
-              When E1=0/E0=0, the strength is 0.125mA.
-              When E1=0/E0=1, the strength is 0.25mA.
-              When E1=1/E0=0, the strength is 0.5mA.
-              When E1=1/E0=1, the strength is 1mA.
-              EN is used to enable or disable the specific driving setup.
-              Valid arguments are described as below:
-              0: (E1, E0, EN) = (0, 0, 0)
-              1: (E1, E0, EN) = (0, 0, 1)
-              2: (E1, E0, EN) = (0, 1, 0)
-              3: (E1, E0, EN) = (0, 1, 1)
-              4: (E1, E0, EN) = (1, 0, 0)
-              5: (E1, E0, EN) = (1, 0, 1)
-              6: (E1, E0, EN) = (1, 1, 0)
-              7: (E1, E0, EN) = (1, 1, 1)
-              So the valid arguments are from 0 to 7.
-            $ref: /schemas/types.yaml#/definitions/uint32
-            enum: [0, 1, 2, 3, 4, 5, 6, 7]
-
-          mediatek,pull-up-adv:
-            description: |
-              Pull up settings for 2 pull resistors, R0 and R1. User can
-              configure those special pins. Valid arguments are described as below:
-              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
-              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
-              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
-              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
-            $ref: /schemas/types.yaml#/definitions/uint32
-            enum: [0, 1, 2, 3]
-
-          bias-pull-down: true
-
-          bias-pull-up: true
+          drive-strength-microamp:
+            enum: [125, 250, 500, 1000]
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+                description: normal pull down.
+              - enum: [100, 101, 102, 103]
+                description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_
+                  defines in dt-bindings/pinctrl/mt65xx.h.
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+                description: normal pull up.
+              - enum: [100, 101, 102, 103]
+                description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_
+                  defines in dt-bindings/pinctrl/mt65xx.h.
 
           bias-disable: true
 
diff --git a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
index d8e75b3e64f1..15092fdd4b5b 100644
--- a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
@@ -288,11 +288,14 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - $ref: "pinctrl.yaml#"
+
 examples:
   - |
     #include <dt-bindings/pinctrl/sppctl-sp7021.h>
 
-    pinctl@9c000100 {
+    pinctrl@9c000100 {
         compatible = "sunplus,sp7021-pctl";
         reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
               <0x9c0032e4 0x1c>, <0x9c000080 0x20>;
diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml
index 0d7cbbdf808b..402d9d2ed2b9 100644
--- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml
+++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml
@@ -28,7 +28,7 @@ properties:
     maxItems: 1
 
   usb-otg-vbus:
-    type: object
+    $ref: /schemas/regulator/regulator.yaml#
     description: |
       Regulator that is used to control the VBUS voltage direction for
       either USB host mode or for charging on the OTG port
diff --git a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml
index caeff68c66d5..cbac55d3cb92 100644
--- a/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml
+++ b/Documentation/devicetree/bindings/power/supply/qcom,pm8941-charger.yaml
@@ -117,11 +117,18 @@ properties:
       be done externally to fully comply with the JEITA safety guidelines if this flag
       is set.
 
+  usb-charge-current-limit:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 100000
+    maximum: 2500000
+    description: |
+      Default USB charge current limit in uA.
+
   usb-otg-in-supply:
     description: Reference to the regulator supplying power to the USB_OTG_IN pin.
 
   otg-vbus:
-    type: object
+    $ref: /schemas/regulator/regulator.yaml#
     description: |
       This node defines a regulator used to control the direction of VBUS voltage.
       Specifically whether to supply voltage to VBUS for host mode operation of the OTG port,
diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
index 20862cdfc116..ce0bca4689f6 100644
--- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
+++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
@@ -82,7 +82,7 @@ properties:
       - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
 
   usb-vbus:
-    $ref: "../../regulator/regulator.yaml#"
+    $ref: /schemas/regulator/regulator.yaml#
     type: object
 
     properties:
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
index 033d1fc0f405..4969ac1d9766 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
@@ -9,6 +9,7 @@ Required properties:
    - "mediatek,mt7628-pwm": found on mt7628 SoC.
    - "mediatek,mt7629-pwm": found on mt7629 SoC.
    - "mediatek,mt8183-pwm": found on mt8183 SoC.
+   - "mediatek,mt8365-pwm": found on mt8365 SoC.
    - "mediatek,mt8516-pwm": found on mt8516 SoC.
  - reg: physical base address and length of the controller's registers.
  - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
@@ -18,6 +19,7 @@ Required properties:
                 has no clocks
    - "top": the top clock generator
    - "main": clock used by the PWM core
+   - "pwm1-3": the three per PWM clocks for mt8365
    - "pwm1-8": the eight per PWM clocks for mt2712
    - "pwm1-6": the six per PWM clocks for mt7622
    - "pwm1-5": the five per PWM clocks for mt7623
diff --git a/Documentation/devicetree/bindings/regulator/mps,mp5416.yaml b/Documentation/devicetree/bindings/regulator/mps,mp5416.yaml
index 90727fdc1283..7023c597c3ed 100644
--- a/Documentation/devicetree/bindings/regulator/mps,mp5416.yaml
+++ b/Documentation/devicetree/bindings/regulator/mps,mp5416.yaml
@@ -15,6 +15,7 @@ properties:
   compatible:
     enum:
       - mps,mp5416
+      - mps,mp5496
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
deleted file mode 100644
index 3d78d507e29f..000000000000
--- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-Bindings for the Generic PWM Regulator
-======================================
-
-Currently supports 2 modes of operation:
-
-Voltage Table:		When in this mode, a voltage table (See below) of
-			predefined voltage <=> duty-cycle values must be
-			provided via DT. Limitations are that the regulator can
-			only operate at the voltages supplied in the table.
-			Intermediary duty-cycle values which would normally
-			allow finer grained voltage selection are ignored and
-			rendered useless.  Although more control is given to
-			the user if the assumptions made in continuous-voltage
-			mode do not reign true.
-
-Continuous Voltage:	This mode uses the regulator's maximum and minimum
-			supplied voltages specified in the
-			regulator-{min,max}-microvolt properties to calculate
-			appropriate duty-cycle values.  This allows for a much
-			more fine grained solution when compared with
-			voltage-table mode above.  This solution does make an
-			assumption that a %50 duty-cycle value will cause the
-			regulator voltage to run at half way between the
-			supplied max_uV and min_uV values.
-
-Required properties:
---------------------
-- compatible:		Should be "pwm-regulator"
-
-- pwms:			PWM specification (See: ../pwm/pwm.txt)
-
-Only required for Voltage Table Mode:
-- voltage-table: 	Voltage and Duty-Cycle table consisting of 2 cells
-			    First cell is voltage in microvolts (uV)
-			    Second cell is duty-cycle in percent (%)
-
-Optional properties for Continuous mode:
-- pwm-dutycycle-unit:	Integer value encoding the duty cycle unit. If not
-			defined, <100> is assumed, meaning that
-			pwm-dutycycle-range contains values expressed in
-			percent.
-
-- pwm-dutycycle-range:	Should contain 2 entries. The first entry is encoding
-			the dutycycle for regulator-min-microvolt and the
-			second one the dutycycle for regulator-max-microvolt.
-			Duty cycle values are expressed in pwm-dutycycle-unit.
-			If not defined, <0 100> is assumed.
-
-NB: To be clear, if voltage-table is provided, then the device will be used
-in Voltage Table Mode.  If no voltage-table is provided, then the device will
-be used in Continuous Voltage Mode.
-
-Optional properties:
---------------------
-- enable-gpios:		GPIO to use to enable/disable the regulator
-
-Any property defined as part of the core regulator binding can also be used.
-(See: ../regulator/regulator.txt)
-
-Continuous Voltage With Enable GPIO Example:
-	pwm_regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm1 0 8448 0>;
-		enable-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
-		regulator-min-microvolt = <1016000>;
-		regulator-max-microvolt = <1114000>;
-		regulator-name = "vdd_logic";
-		/* unit == per-mille */
-		pwm-dutycycle-unit = <1000>;
-		/*
-		 * Inverted PWM logic, and the duty cycle range is limited
-		 * to 30%-70%.
-		 */
-		pwm-dutycycle-range = <700 300>; /* */
-	};
-
-Voltage Table Example:
-	pwm_regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm1 0 8448 0>;
-		regulator-min-microvolt = <1016000>;
-		regulator-max-microvolt = <1114000>;
-		regulator-name = "vdd_logic";
-
-			      /* Voltage Duty-Cycle */
-		voltage-table = <1114000 0>,
-				<1095000 10>,
-				<1076000 20>,
-				<1056000 30>,
-				<1036000 40>,
-				<1016000 50>;
-	};
diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.yaml b/Documentation/devicetree/bindings/regulator/pwm-regulator.yaml
new file mode 100644
index 000000000000..0332fec48a88
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for the Generic PWM Regulator
+
+maintainers:
+  - Brian Norris <briannorris@chromium.org>
+  - Lee Jones <lee.jones@linaro.org>
+  - Alexandre Courbot <acourbot@nvidia.com>
+
+description: |
+  Currently supports 2 modes of operation:
+
+  Voltage Table:
+    When in this mode, a voltage table (See below) of predefined voltage <=>
+    duty-cycle values must be provided via DT. Limitations are that the
+    regulator can only operate at the voltages supplied in the table.
+    Intermediary duty-cycle values which would normally allow finer grained
+    voltage selection are ignored and rendered useless.  Although more control
+    is given to the user if the assumptions made in continuous-voltage mode do
+    not reign true.
+
+  Continuous Voltage:
+    This mode uses the regulator's maximum and minimum supplied voltages
+    specified in the regulator-{min,max}-microvolt properties to calculate
+    appropriate duty-cycle values.  This allows for a much more fine grained
+    solution when compared with voltage-table mode above.  This solution does
+    make an assumption that a %50 duty-cycle value will cause the regulator
+    voltage to run at half way between the supplied max_uV and min_uV values.
+
+  If voltage-table is provided, then the device will be used in Voltage Table
+  Mode.  If no voltage-table is provided, then the device will be used in
+  Continuous Voltage Mode.
+
+allOf:
+  - $ref: regulator.yaml#
+
+properties:
+  compatible:
+    const: pwm-regulator
+
+  pwms:
+    maxItems: 1
+
+  voltage-table:
+    description: Voltage and Duty-Cycle table.
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      items:
+        - description: voltage in microvolts (uV)
+        - description: duty-cycle in percent (%)
+
+  enable-gpios:
+    description: Regulator enable GPIO
+    maxItems: 1
+
+   # Optional properties for Continuous mode:
+  pwm-dutycycle-unit:
+    description:
+      Integer value encoding the duty cycle unit. If not
+        defined, <100> is assumed, meaning that
+        pwm-dutycycle-range contains values expressed in
+        percent.
+    default: 100
+
+  pwm-dutycycle-range:
+    description:
+      Should contain 2 entries. The first entry is encoding
+        the dutycycle for regulator-min-microvolt and the
+        second one the dutycycle for regulator-max-microvolt.
+        Duty cycle values are expressed in pwm-dutycycle-unit.
+        If not defined, <0 100> is assumed.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - description: the dutycycle for regulator-min-microvolt
+      - description: the dutycycle for regulator-max-microvolt
+    default: [ 0 100 ]
+
+required:
+  - compatible
+  - pwms
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    // Continuous Voltage With Enable GPIO Example:
+    regulator {
+        compatible = "pwm-regulator";
+        pwms = <&pwm1 0 8448 0>;
+        enable-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+        regulator-min-microvolt = <1016000>;
+        regulator-max-microvolt = <1114000>;
+        regulator-name = "vdd_logic";
+        /* unit == per-mille */
+        pwm-dutycycle-unit = <1000>;
+        /*
+        * Inverted PWM logic, and the duty cycle range is limited
+        * to 30%-70%.
+        */
+        pwm-dutycycle-range = <700 300>; /* */
+    };
+
+  - |
+    // Voltage Table Example:
+    regulator {
+        compatible = "pwm-regulator";
+        pwms = <&pwm1 0 8448 0>;
+        regulator-min-microvolt = <1016000>;
+        regulator-max-microvolt = <1114000>;
+        regulator-name = "vdd_logic";
+
+                /* Voltage Duty-Cycle */
+        voltage-table = <1114000 0>,
+            <1095000 10>,
+            <1076000 20>,
+            <1056000 30>,
+            <1036000 40>,
+            <1016000 50>;
+    };
+...
diff --git a/Documentation/devicetree/bindings/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt
deleted file mode 100644
index 4f8d8fde0c1c..000000000000
--- a/Documentation/devicetree/bindings/serial/efm32-uart.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Energymicro efm32 UART
-
-Required properties:
-- compatible : Should be "energymicro,efm32-uart"
-- reg : Address and length of the register set
-- interrupts : Should contain uart interrupt
-
-Optional properties:
-- energymicro,location : Decides the location of the USART I/O pins.
-  Allowed range : [0 .. 5]
-  Default: 0
-
-Example:
-
-uart@4000c400 {
-	compatible = "energymicro,efm32-uart";
-	reg = <0x4000c400 0x400>;
-	interrupts = <15>;
-	energymicro,location = <0>;
-};
diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
new file mode 100644
index 000000000000..4ff27d6d4d5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+allOf:
+  - $ref: serial.yaml#
+
+description: |
+  The MediaTek UART is based on the basic 8250 UART and compatible
+  with 16550A, with enhancements for high speed baud rates and
+  support for DMA.
+
+properties:
+  compatible:
+    oneOf:
+      - const: mediatek,mt6577-uart
+      - items:
+          - enum:
+              - mediatek,mt2701-uart
+              - mediatek,mt2712-uart
+              - mediatek,mt6580-uart
+              - mediatek,mt6582-uart
+              - mediatek,mt6589-uart
+              - mediatek,mt6755-uart
+              - mediatek,mt6765-uart
+              - mediatek,mt6779-uart
+              - mediatek,mt6795-uart
+              - mediatek,mt6797-uart
+              - mediatek,mt7622-uart
+              - mediatek,mt7623-uart
+              - mediatek,mt7629-uart
+              - mediatek,mt7986-uart
+              - mediatek,mt8127-uart
+              - mediatek,mt8135-uart
+              - mediatek,mt8173-uart
+              - mediatek,mt8183-uart
+              - mediatek,mt8186-uart
+              - mediatek,mt8192-uart
+              - mediatek,mt8195-uart
+              - mediatek,mt8516-uart
+          - const: mediatek,mt6577-uart
+
+  reg:
+    description: The base address of the UART register bank
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    items:
+      - description: The clock the baudrate is derived from
+      - description: The bus clock for register accesses
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: baud
+      - const: bus
+
+  dmas:
+    items:
+      - description: phandle to TX DMA
+      - description: phandle to RX DMA
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  interrupts:
+    minItems: 1
+    maxItems: 2
+
+  interrupt-names:
+    description:
+      The UART interrupt and optionally the RX in-band wakeup interrupt.
+    minItems: 1
+    items:
+      - const: uart
+      - const: wakeup
+
+  pinctrl-0: true
+  pinctrl-1: true
+
+  pinctrl-names:
+    minItems: 1
+    items:
+      - const: default
+      - const: sleep
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    serial@11006000 {
+        compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
+        reg = <0x11006000 0x400>;
+        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+                     <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
+        interrupt-names = "uart", "wakeup";
+        clocks = <&uart_clk>, <&bus_clk>;
+        clock-names = "baud", "bus";
+        pinctrl-0 = <&uart_pin>;
+        pinctrl-1 = <&uart_pin_sleep>;
+        pinctrl-names = "default", "sleep";
+    };
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
deleted file mode 100644
index 113b5d6a2245..000000000000
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
-
-Required properties:
-- compatible should contain:
-  * "mediatek,mt2701-uart" for MT2701 compatible UARTS
-  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
-  * "mediatek,mt6580-uart" for MT6580 compatible UARTS
-  * "mediatek,mt6582-uart" for MT6582 compatible UARTS
-  * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-  * "mediatek,mt6755-uart" for MT6755 compatible UARTS
-  * "mediatek,mt6765-uart" for MT6765 compatible UARTS
-  * "mediatek,mt6779-uart" for MT6779 compatible UARTS
-  * "mediatek,mt6795-uart" for MT6795 compatible UARTS
-  * "mediatek,mt6797-uart" for MT6797 compatible UARTS
-  * "mediatek,mt7622-uart" for MT7622 compatible UARTS
-  * "mediatek,mt7623-uart" for MT7623 compatible UARTS
-  * "mediatek,mt7629-uart" for MT7629 compatible UARTS
-  * "mediatek,mt7986-uart", "mediatek,mt6577-uart" for MT7986 compatible UARTS
-  * "mediatek,mt8127-uart" for MT8127 compatible UARTS
-  * "mediatek,mt8135-uart" for MT8135 compatible UARTS
-  * "mediatek,mt8173-uart" for MT8173 compatible UARTS
-  * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
-  * "mediatek,mt8186-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
-  * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
-  * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS
-  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
-  * "mediatek,mt6577-uart" for MT6577 and all of the above
-
-- reg: The base address of the UART register bank.
-
-- interrupts:
-  index 0: an interrupt specifier for the UART controller itself
-  index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to
-           support Rx in-band wake up. If one would like to use this feature,
-           one must create an addtional pinctrl to reconfigure Rx pin to normal
-           GPIO before suspend.
-
-- clocks : Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names:
-  - "baud": The clock the baudrate is derived from
-  - "bus": The bus clock for register accesses (optional)
-
-For compatibility with older device trees an unnamed clock is used for the
-baud clock if the baudclk does not exist. Do not use this for new designs.
-
-Example:
-
-	uart0: serial@11006000 {
-		compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
-		reg = <0x11006000 0x400>;
-		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
-		clocks = <&uart_clk>, <&bus_clk>;
-		clock-names = "baud", "bus";
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&uart_pin>;
-		pinctrl-1 = <&uart_pin_sleep>;
-	};
diff --git a/Documentation/devicetree/bindings/serio/ps2-gpio.txt b/Documentation/devicetree/bindings/serio/ps2-gpio.txt
deleted file mode 100644
index 7b7bc9cdf986..000000000000
--- a/Documentation/devicetree/bindings/serio/ps2-gpio.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Device-Tree binding for ps/2 gpio device
-
-Required properties:
-	- compatible = "ps2-gpio"
-	- data-gpios: the data pin
-	- clk-gpios: the clock pin
-	- interrupts: Should trigger on the falling edge of the clock line.
-
-Optional properties:
-	- write-enable: Indicates whether write function is provided
-	to serio device. Possibly providing the write fn will not work, because
-	of the tough timing requirements.
-
-Example nodes:
-
-ps2@0 {
-	compatible = "ps2-gpio";
-	interrupt-parent = <&gpio>;
-	interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
-	data-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
-	clk-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
-	write-enable;
-};
diff --git a/Documentation/devicetree/bindings/serio/ps2-gpio.yaml b/Documentation/devicetree/bindings/serio/ps2-gpio.yaml
new file mode 100644
index 000000000000..a63d9172346f
--- /dev/null
+++ b/Documentation/devicetree/bindings/serio/ps2-gpio.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serio/ps2-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for GPIO based PS/2
+
+maintainers:
+  - Danilo Krummrich <danilokrummrich@dk-develop.de>
+
+properties:
+  compatible:
+    const: ps2-gpio
+
+  data-gpios:
+    description:
+      the gpio used for the data signal - this should be flagged as
+      active high using open drain with (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)
+      from <dt-bindings/gpio/gpio.h> since the signal is open drain by
+      definition
+    maxItems: 1
+
+  clk-gpios:
+    description:
+      the gpio used for the clock signal - this should be flagged as
+      active high using open drain with (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)
+      from <dt-bindings/gpio/gpio.h> since the signal is open drain by
+      definition
+    maxItems: 1
+
+  interrupts:
+    description:
+      The given interrupt should trigger on the falling edge of the clock line.
+    maxItems: 1
+
+  write-enable:
+    type: boolean
+    description:
+      Indicates whether write function is provided to serio device. Possibly
+      providing the write function will not work, because of the tough timing
+      requirements.
+
+required:
+  - compatible
+  - data-gpios
+  - clk-gpios
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    ps2 {
+        compatible = "ps2-gpio";
+        interrupt-parent = <&gpio>;
+        interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+        data-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        clk-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        write-enable;
+    };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
index 31e4d3c339bf..d0a4bc3b03e9 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
@@ -20,6 +20,7 @@ properties:
   compatible:
     enum:
       - mediatek,mt6779-devapc
+      - mediatek,mt8186-devapc
 
   reg:
     description: The base address of devapc register bank
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
new file mode 100644
index 000000000000..627dcc3e8b32
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek mutex
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
+  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
+  data path or MDP data path.
+  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
+  the shadow register.
+  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt2701-disp-mutex
+      - mediatek,mt2712-disp-mutex
+      - mediatek,mt8167-disp-mutex
+      - mediatek,mt8173-disp-mutex
+      - mediatek,mt8183-disp-mutex
+      - mediatek,mt8186-disp-mutex
+      - mediatek,mt8192-disp-mutex
+      - mediatek,mt8195-disp-mutex
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: MUTEX Clock
+
+  mediatek,gce-events:
+    description:
+      The event id which is mapping to the specific hardware event signal
+      to gce. The event id is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+  mediatek,gce-client-reg:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle of GCE
+        - description: GCE subsys id
+        - description: register offset
+        - description: register size
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property. Each GCE subsys id is mapping to
+      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt8173-clk.h>
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mutex: mutex@14020000 {
+            compatible = "mediatek,mt8173-disp-mutex";
+            reg = <0 0x14020000 0 0x1000>;
+            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+            clocks = <&mmsys CLK_MM_MUTEX_32K>;
+            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
new file mode 100644
index 000000000000..d911fa2d40ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Smart Voltage Scaling (SVS) Device Tree Bindings
+
+maintainers:
+  - Roger Lu <roger.lu@mediatek.com>
+  - Matthias Brugger <matthias.bgg@gmail.com>
+  - Kevin Hilman <khilman@kernel.org>
+
+description: |+
+  The SVS engine is a piece of hardware which has several
+  controllers(banks) for calculating suitable voltage to
+  different power domains(CPU/GPU/CCI) according to
+  chip process corner, temperatures and other factors. Then DVFS
+  driver could apply SVS bank voltage to PMIC/Buck.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8183-svs
+      - mediatek,mt8192-svs
+
+  reg:
+    maxItems: 1
+    description: Address range of the MTK SVS controller.
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: Main clock for MTK SVS controller to work.
+
+  clock-names:
+    const: main
+
+  nvmem-cells:
+    minItems: 1
+    description:
+      Phandle to the calibration data provided by a nvmem device.
+    items:
+      - description: SVS efuse for SVS controller
+      - description: Thermal efuse for SVS controller
+
+  nvmem-cell-names:
+    items:
+      - const: svs-calibration-data
+      - const: t-calibration-data
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: svs_rst
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - nvmem-cells
+  - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        svs@1100b000 {
+            compatible = "mediatek,mt8183-svs";
+            reg = <0 0x1100b000 0 0x1000>;
+            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+            clocks = <&infracfg CLK_INFRA_THERM>;
+            clock-names = "main";
+            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
+            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+        };
+    };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index e2e173dfada7..d01e98768153 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -33,6 +33,7 @@ properties:
           - qcom,sm8150-aoss-qmp
           - qcom,sm8250-aoss-qmp
           - qcom,sm8350-aoss-qmp
+          - qcom,sm8450-aoss-qmp
       - const: qcom,aoss-qmp
 
   reg:
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
index f5ecf4a8c377..4a50f1d27724 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
@@ -65,33 +65,22 @@ properties:
 
   qcom,tcs-config:
     $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    minItems: 4
+    maxItems: 4
     items:
-      - items:
-          - description: TCS type
-            enum: [ 0, 1, 2, 3 ]
-          - description: Number of TCS
-      - items:
-          - description: TCS type
-            enum: [ 0, 1, 2, 3 ]
-          - description: Number of TCS
-      - items:
-          - description: TCS type
-            enum: [ 0, 1, 2, 3]
-          - description: Numbe r of TCS
-      - items:
-          - description: TCS type
-            enum: [ 0, 1, 2, 3 ]
-          - description: Number of TCS
+      items:
+        - description: |
+            TCS type::
+             - ACTIVE_TCS
+             - SLEEP_TCS
+             - WAKE_TCS
+             - CONTROL_TCS
+          enum: [ 0, 1, 2, 3 ]
+        - description: Number of TCS
     description: |
       The tuple defining the configuration of TCS. Must have two cells which
       describe each TCS type.  The order of the TCS must match the hardware
       configuration.
-      Cell 1 (TCS Type):: TCS types to be specified::
-       - ACTIVE_TCS
-       - SLEEP_TCS
-       - WAKE_TCS
-       - CONTROL_TCS
-      Cell 2 (Number of TCS):: <u32>
 
   qcom,tcs-offset:
     $ref: /schemas/types.yaml#/definitions/uint32
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
index f0f1bf06aea6..cc1b35080162 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -51,6 +51,9 @@ properties:
     $ref: /schemas/clock/qcom,rpmcc.yaml#
     unevaluatedProperties: false
 
+  power-controller:
+    $ref: /schemas/power/qcom,rpmpd.yaml#
+
   qcom,smd-channels:
     $ref: /schemas/types.yaml#/definitions/string-array
     description: Channel name used for the RPM communication
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,prr.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,prr.yaml
new file mode 100644
index 000000000000..654c96638e75
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,prr.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,prr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Product Register
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+  - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+  Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
+  Register that allows to retrieve SoC product and revision information.
+  If present, a device node for this register should be added.
+
+properties:
+  compatible:
+    enum:
+      - renesas,prr
+      - renesas,bsid
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    prr: chipid@ff000044 {
+        compatible = "renesas,prr";
+        reg = <0xff000044 4>;
+    };
diff --git a/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt
index 0720857089a7..8facbce53db8 100644
--- a/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt
+++ b/Documentation/devicetree/bindings/sound/atmel-sam9x5-wm8731-audio.txt
@@ -16,7 +16,7 @@ Board connectors:
  * Line In Jack
 
 wm8731 pins:
-cf Documentation/devicetree/bindings/sound/wm8731.txt
+cf Documentation/devicetree/bindings/sound/wlf,wm8731.yaml
 
 Example:
 sound {
diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.txt b/Documentation/devicetree/bindings/sound/fsl,mqs.txt
index 40353fc30255..d66284b8bef2 100644
--- a/Documentation/devicetree/bindings/sound/fsl,mqs.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,mqs.txt
@@ -2,7 +2,7 @@ fsl,mqs audio CODEC
 
 Required properties:
   - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
-		"fsl,imx8qm-mqs", "fsl,imx8qxp-mqs".
+		"fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
   - clocks : A list of phandles + clock-specifiers, one for each entry in
 	     clock-names
   - clock-names : "mclk" - must required.
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
index 6df6f858038c..47b6e712e4fb 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
@@ -110,6 +110,10 @@ patternProperties:
     type: object
     $ref: nvidia,tegra186-asrc.yaml#
 
+  '^processing-engine@[0-9a-f]+$':
+    type: object
+    $ref: nvidia,tegra210-ope.yaml#
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml
new file mode 100644
index 000000000000..5b9198602fc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-mbdrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 MBDRC
+
+description:
+  The Multi Band Dynamic Range Compressor (MBDRC) is part of Output
+  Processing Engine (OPE) which interfaces with Audio Hub (AHUB) via
+  Audio Client Interface (ACIF). MBDRC can be used as a traditional
+  single full band or a dual band or a multi band dynamic processor.
+
+maintainers:
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Mohan Kumar <mkumard@nvidia.com>
+  - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - const: nvidia,tegra210-mbdrc
+      - items:
+          - enum:
+              - nvidia,tegra234-mbdrc
+              - nvidia,tegra194-mbdrc
+              - nvidia,tegra186-mbdrc
+          - const: nvidia,tegra210-mbdrc
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    dynamic-range-compressor@702d8200 {
+        compatible = "nvidia,tegra210-mbdrc";
+        reg = <0x702d8200 0x200>;
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml
new file mode 100644
index 000000000000..9dc9ba590fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 OPE
+
+description:
+  The Output Processing Engine (OPE) is one of the AHUB client. It has
+  PEQ (Parametric Equalizer) and MBDRC (Multi Band Dynamic Range Compressor)
+  sub blocks for data processing.
+
+maintainers:
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Mohan Kumar <mkumard@nvidia.com>
+  - Sameer Pujar <spujar@nvidia.com>
+
+allOf:
+  - $ref: name-prefix.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: nvidia,tegra210-ope
+      - items:
+          - enum:
+              - nvidia,tegra234-ope
+              - nvidia,tegra194-ope
+              - nvidia,tegra186-ope
+          - const: nvidia,tegra210-ope
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+  sound-name-prefix:
+    pattern: "^OPE[1-9]$"
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: audio-graph-port.yaml#
+        unevaluatedProperties: false
+        description:
+          OPE ACIF (Audio Client Interface) input port. This is connected
+          to corresponding ACIF output port on AHUB (Audio Hub).
+
+      port@1:
+        $ref: audio-graph-port.yaml#
+        unevaluatedProperties: false
+        description:
+          OPE ACIF output port. This is connected to corresponding ACIF
+          input port on AHUB.
+
+patternProperties:
+  '^equalizer@[0-9a-f]+$':
+    type: object
+    $ref: nvidia,tegra210-peq.yaml#
+
+  '^dynamic-range-compressor@[0-9a-f]+$':
+    type: object
+    $ref: nvidia,tegra210-mbdrc.yaml#
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    processing-engine@702d8000 {
+        compatible = "nvidia,tegra210-ope";
+        reg = <0x702d8000 0x100>;
+        sound-name-prefix = "OPE1";
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml
new file mode 100644
index 000000000000..1e373c49d639
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-peq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 PEQ
+
+description:
+  The Parametric Equalizer (PEQ) is a cascade of biquad filters with
+  each filter tuned based on certain parameters. It can be used to
+  equalize the irregularities in the speaker frequency response.
+  PEQ sits inside Output Processing Engine (OPE) which interfaces
+  with Audio Hub (AHUB) via Audio Client Interface (ACIF).
+
+maintainers:
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Mohan Kumar <mkumard@nvidia.com>
+  - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+  compatible:
+    oneOf:
+      - const: nvidia,tegra210-peq
+      - items:
+          - enum:
+              - nvidia,tegra234-peq
+              - nvidia,tegra194-peq
+              - nvidia,tegra186-peq
+          - const: nvidia,tegra210-peq
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    equalizer@702d8100 {
+        compatible = "nvidia,tegra210-peq";
+        reg = <0x702d8100 0x100>;
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml b/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
index b9b1dba40856..7f2e68ff6d34 100644
--- a/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
+++ b/Documentation/devicetree/bindings/sound/nxp,tfa989x.yaml
@@ -15,6 +15,7 @@ allOf:
 properties:
   compatible:
     enum:
+      - nxp,tfa9890
       - nxp,tfa9895
       - nxp,tfa9897
 
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
index 7e8d252f7bca..0d9840375132 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     items:
       - enum:
+          - renesas,r9a07g043-ssi  # RZ/G2UL
           - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
           - renesas,r9a07g054-ssi  # RZ/V2L
       - const: renesas,rz-ssi
@@ -50,7 +51,7 @@ properties:
     minItems: 1
     maxItems: 2
     description:
-      The first cell represents a phandle to dmac
+      The first cell represents a phandle to dmac.
       The second cell specifies the encoded MID/RID values of the SSI port
       connected to the DMA client and the slave channel configuration
       parameters.
diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml
index 5ea16b8ef93f..7e36e389e976 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.yaml
@@ -61,6 +61,13 @@ properties:
           - const: tx
           - const: rx
 
+  pinctrl-names:
+    oneOf:
+      - const: default
+      - items:
+          - const: bclk_on
+          - const: bclk_off
+
   power-domains:
     maxItems: 1
 
diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt
deleted file mode 100644
index e0fa61a1be0c..000000000000
--- a/Documentation/devicetree/bindings/spi/efm32-spi.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-* Energy Micro EFM32 SPI
-
-Required properties:
-- #address-cells: see spi-bus.txt
-- #size-cells: see spi-bus.txt
-- compatible: should be "energymicro,efm32-spi"
-- reg: Offset and length of the register set for the controller
-- interrupts: pair specifying rx and tx irq
-- clocks: phandle to the spi clock
-- cs-gpios: see spi-bus.txt
-
-Recommended properties :
-- energymicro,location: Value to write to the ROUTE register's LOCATION
-                        bitfield to configure the pinmux for the device, see
-                        datasheet for values.
-                        If this property is not provided, keeping what is
-                        already configured in the hardware, so its either the
-                        reset default 0 or whatever the bootloader did.
-
-Example:
-
-spi1: spi@4000c400 { /* USART1 */
-	#address-cells = <1>;
-	#size-cells = <0>;
-	compatible = "energymicro,efm32-spi";
-	reg = <0x4000c400 0x400>;
-	interrupts = <15 16>;
-	clocks = <&cmu 20>;
-	cs-gpios = <&gpio 51 1>; // D3
-	energymicro,location = <1>;
-
-	ks8851@0 {
-		compatible = "ks8851";
-		spi-max-frequency = <6000000>;
-		reg = <0>;
-		interrupt-parent = <&boardfpga>;
-		interrupts = <4>;
-	};
-};
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
index 94ef0552bd42..d3d34a3a0b7f 100644
--- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
@@ -18,6 +18,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt7629-spi
+              - mediatek,mt8365-spi
           - const: mediatek,mt7622-spi
       - items:
           - enum:
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index ece261b8e963..7326c0a28d16 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -47,6 +47,5 @@ examples:
         clocks = <&clkcfg CLK_SPI0>;
         interrupt-parent = <&plic>;
         interrupts = <54>;
-        spi-max-frequency = <25000000>;
     };
 ...
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml
new file mode 100644
index 000000000000..24e0c2181d25
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Peripheral properties for Tegra Quad SPI Controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jonathan Hunter <jonathanh@nvidia.com>
+
+properties:
+  nvidia,tx-clk-tap-delay:
+    description:
+      Delays the clock going out to device with this tap value.
+      Tap value varies based on platform design trace lengths from Tegra
+      QSPI to corresponding slave device.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 31
+
+  nvidia,rx-clk-tap-delay:
+    description:
+      Delays the clock coming in from the device with this tap value.
+      Tap value varies based on platform design trace lengths from Tegra
+      QSPI to corresponding slave device.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 255
+
+unevaluatedProperties: true
+
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 0296edd1de22..6b733e5c1163 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -20,6 +20,7 @@ properties:
       - nvidia,tegra186-qspi
       - nvidia,tegra194-qspi
       - nvidia,tegra234-qspi
+      - nvidia,tegra241-qspi
 
   reg:
     maxItems: 1
@@ -57,27 +58,6 @@ patternProperties:
       spi-tx-bus-width:
         enum: [1, 2, 4]
 
-      nvidia,tx-clk-tap-delay:
-        description:
-          Delays the clock going out to device with this tap value.
-          Tap value varies based on platform design trace lengths from Tegra
-          QSPI to corresponding slave device.
-        $ref: /schemas/types.yaml#/definitions/uint32
-        minimum: 0
-        maximum: 31
-
-      nvidia,rx-clk-tap-delay:
-        description:
-          Delays the clock coming in from the device with this tap value.
-          Tap value varies based on platform design trace lengths from Tegra
-          QSPI to corresponding slave device.
-        $ref: /schemas/types.yaml#/definitions/uint32
-        minimum: 0
-        maximum: 255
-
-    required:
-      - reg
-
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index e2c7b934c50d..2e20ca313ec1 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -45,12 +45,15 @@ properties:
       - const: rx
 
   interconnects:
-    maxItems: 2
+    minItems: 2
+    maxItems: 3
 
   interconnect-names:
+    minItems: 2
     items:
       - const: qup-core
       - const: qup-config
+      - const: qup-memory
 
   interrupts:
     maxItems: 1
@@ -110,7 +113,6 @@ examples:
         pinctrl-names = "default";
         pinctrl-0 = <&qup_spi1_default>;
         interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
-        spi-max-frequency = <50000000>;
         #address-cells = <1>;
         #size-cells = <0>;
     };
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index d7e08b03e204..e25d44c218f2 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -124,9 +124,16 @@ properties:
 
   rx-sample-delay-ns:
     default: 0
-    description: Default value of the rx-sample-delay-ns property.
+    description: |
+      Default value of the rx-sample-delay-ns property.
       This value will be used if the property is not explicitly defined
-      for a SPI slave device. See below.
+      for a SPI slave device.
+
+      SPI Rx sample delay offset, unit is nanoseconds.
+      The delay from the default sample time before the actual sample of the
+      rxd input signal occurs. The "rx_sample_delay" is an optional feature
+      of the designware controller, and the upper limit is also subject to
+      controller configuration.
 
 patternProperties:
   "^.*@[0-9a-f]+$":
@@ -142,13 +149,6 @@ patternProperties:
       spi-tx-bus-width:
         const: 1
 
-      rx-sample-delay-ns:
-        description: SPI Rx sample delay offset, unit is nanoseconds.
-          The delay from the default sample time before the actual
-          sample of the rxd input signal occurs. The "rx_sample_delay"
-          is an optional feature of the designware controller, and the
-          upper limit is also subject to controller configuration.
-
 unevaluatedProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 5e32928c4fc3..9d63a58b46a0 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -71,6 +71,11 @@ properties:
     description:
       Delay, in microseconds, after a read transfer.
 
+  rx-sample-delay-ns:
+    description: SPI Rx sample delay offset, unit is nanoseconds.
+      The delay from the default sample time before the actual
+      sample of the rxd input signal occurs.
+
   spi-tx-bus-width:
     description:
       Bus width to the SPI bus used for write transfers.
@@ -112,5 +117,6 @@ properties:
 allOf:
   - $ref: cdns,qspi-nor-peripheral-props.yaml#
   - $ref: samsung,spi-peripheral-props.yaml#
+  - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
 
 additionalProperties: true
diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
new file mode 100644
index 000000000000..e9199190198d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sram/qcom,imem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IMEM memory region
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+  Qualcomm IMEM is dedicated memory region for various debug features and DMA
+  transactions.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,apq8064-imem
+          - qcom,msm8974-imem
+          - qcom,qcs404-imem
+          - qcom,sc7180-imem
+          - qcom,sc7280-imem
+          - qcom,sdm630-imem
+          - qcom,sdm845-imem
+          - qcom,sdx55-imem
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  ranges: true
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  reboot-mode:
+    $ref: /schemas/power/reset/syscon-reboot-mode.yaml#
+
+patternProperties:
+  "^pil-reloc@[0-9a-f]+$":
+    $ref: /schemas/remoteproc/qcom,pil-info.yaml#
+    description: Peripheral image loader relocation region
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        sram@146bf000 {
+            compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
+            reg = <0 0x146bf000 0 0x1000>;
+            ranges = <0 0 0x146bf000 0x1000>;
+
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            pil-reloc@94c {
+                compatible = "qcom,pil-reloc-info";
+                reg = <0x94c 0xc8>;
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
index 930188bc5e6a..071f2d676196 100644
--- a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
+++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
@@ -72,10 +72,10 @@ patternProperties:
 
 examples:
   - |
-      #include <dt-bindings/clock/qcom,rpmcc.h>
-      #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
 
-      ocmem: ocmem@fdd00000 {
+    sram@fdd00000 {
         compatible = "qcom,msm8974-ocmem";
 
         reg = <0xfdd00000 0x2000>,
@@ -93,6 +93,6 @@ examples:
         ranges = <0 0xfec00000 0x100000>;
 
         gmu-sram@0 {
-                reg = <0x0 0x100000>;
+            reg = <0x0 0x100000>;
         };
-      };
+    };
diff --git a/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml b/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml
new file mode 100644
index 000000000000..5f08b6e59b8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom,spmi-temp-alarm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QPNP PMIC Temperature Alarm
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+  QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
+  that utilize the Qualcomm SPMI implementation. These peripherals provide an
+  interrupt signal and status register to identify high PMIC die temperature.
+
+allOf:
+  - $ref: thermal-sensor.yaml#
+
+properties:
+  compatible:
+    const: qcom,spmi-temp-alarm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  io-channels:
+    items:
+      - description: ADC channel, which reports chip die temperature
+
+  io-channel-names:
+    items:
+      - const: thermal
+
+  '#thermal-sensor-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - '#thermal-sensor-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pmic {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pm8350_temp_alarm: temperature-sensor@a00 {
+            compatible = "qcom,spmi-temp-alarm";
+            reg = <0xa00>;
+            interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+            #thermal-sensor-cells = <0>;
+        };
+    };
+
+    thermal-zones {
+        pm8350_thermal: pm8350c-thermal {
+            polling-delay-passive = <100>;
+            polling-delay = <0>;
+            thermal-sensors = <&pm8350_temp_alarm>;
+
+            trips {
+                pm8350_trip0: trip0 {
+                    temperature = <95000>;
+                    hysteresis = <0>;
+                    type = "passive";
+                };
+
+                pm8350_crit: pm8350c-crit {
+                    temperature = <115000>;
+                    hysteresis = <0>;
+                    type = "critical";
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt b/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
deleted file mode 100644
index 2d5b2ad03314..000000000000
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Qualcomm QPNP PMIC Temperature Alarm
-
-QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
-that utilize the Qualcomm SPMI implementation. These peripherals provide an
-interrupt signal and status register to identify high PMIC die temperature.
-
-Required properties:
-- compatible:      Should contain "qcom,spmi-temp-alarm".
-- reg:             Specifies the SPMI address.
-- interrupts:      PMIC temperature alarm interrupt.
-- #thermal-sensor-cells: Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
-
-Optional properties:
-- io-channels:     Should contain IIO channel specifier for the ADC channel,
-                   which report chip die temperature.
-- io-channel-names: Should contain "thermal".
-
-Example:
-
-	pm8941_temp: thermal-alarm@2400 {
-		compatible = "qcom,spmi-temp-alarm";
-		reg = <0x2400>;
-		interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
-		#thermal-sensor-cells = <0>;
-
-		io-channels = <&pm8941_vadc VADC_DIE_TEMP>;
-		io-channel-names = "thermal";
-	};
-
-	thermal-zones {
-		pm8941 {
-			polling-delay-passive = <250>;
-			polling-delay = <1000>;
-
-			thermal-sensors = <&pm8941_temp>;
-
-			trips {
-				stage1 {
-					temperature = <105000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				stage2 {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-		};
-	};
-
diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml
index 1368d90da0e8..0f05f5c886c5 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml
@@ -8,9 +8,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Renesas R-Car Gen3 Thermal Sensor
 
 description:
-  On R-Car Gen3 SoCs, the thermal sensor controllers (TSC) control the thermal
-  sensors (THS) which are the analog circuits for measuring temperature (Tj)
-  inside the LSI.
+  On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC)
+  control the thermal sensors (THS) which are the analog circuits for
+  measuring temperature (Tj) inside the LSI.
 
 maintainers:
   - Niklas Söderlund <niklas.soderlund@ragnatech.se>
@@ -27,6 +27,7 @@ properties:
       - renesas,r8a77965-thermal # R-Car M3-N
       - renesas,r8a77980-thermal # R-Car V3H
       - renesas,r8a779a0-thermal # R-Car V3U
+      - renesas,r8a779f0-thermal # R-Car S4-8
 
   reg: true
 
@@ -57,31 +58,38 @@ required:
   - "#thermal-sensor-cells"
 
 if:
-  not:
-    properties:
-      compatible:
-        contains:
-          enum:
-            - renesas,r8a779a0-thermal
+  properties:
+    compatible:
+      contains:
+        enum:
+          - renesas,r8a779a0-thermal
 then:
   properties:
     reg:
-      minItems: 2
       items:
+        - description: TSC0 registers
         - description: TSC1 registers
         - description: TSC2 registers
         - description: TSC3 registers
-  required:
-    - interrupts
+        - description: TSC4 registers
 else:
   properties:
     reg:
+      minItems: 2
       items:
-        - description: TSC0 registers
         - description: TSC1 registers
         - description: TSC2 registers
         - description: TSC3 registers
-        - description: TSC4 registers
+  if:
+    not:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r8a779f0-thermal
+  then:
+    required:
+      - interrupts
 
 additionalProperties: false
 
diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml
index 6aafa71806a3..7c62c2740330 100644
--- a/Documentation/devicetree/bindings/trivial-devices.yaml
+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
@@ -41,6 +41,8 @@ properties:
           - adi,adp5585-02
             # Analog Devices ADP5589 Keypad Decoder and I/O Expansion
           - adi,adp5589
+            # Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher
+          - adi,lt7182s
             # AMS iAQ-Core VOC Sensor
           - ams,iaq-core
             # i2c serial eeprom (24cxx)
@@ -93,8 +95,6 @@ properties:
           - dh,dhcom-board
             # DA9053: flexible system level PMIC with multicore support
           - dlg,da9053
-            # DA9063: system PMIC for quad-core application processors
-          - dlg,da9063
             # DMARD05: 3-axis I2C Accelerometer
           - domintech,dmard05
             # DMARD06: 3-axis I2C Accelerometer
diff --git a/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml
new file mode 100644
index 000000000000..f04f9f61fa9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/renesas,ufs.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car UFS Host Controller
+
+maintainers:
+  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+  - $ref: ufs-common.yaml
+
+properties:
+  compatible:
+    const: renesas,r8a779f0-ufs
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: fck
+      - const: ref_clk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/r8a779f0-sysc.h>
+
+    ufs: ufs@e686000 {
+            compatible = "renesas,r8a779f0-ufs";
+            reg = <0xe6860000 0x100>;
+            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+            clock-names = "fck", "ref_clk";
+            freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+            resets = <&cpg 1514>;
+    };
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c949eb617313..2c715eec48b8 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -21,6 +21,7 @@ properties:
       - samsung,exynos7-ufs
       - samsung,exynosautov9-ufs
       - samsung,exynosautov9-ufs-vh
+      - tesla,fsd-ufs
 
   reg:
     items:
diff --git a/Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml b/Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
new file mode 100644
index 000000000000..c3b6be3d8002
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 Facebook Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/aspeed,ast2600-udc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED USB 2.0 Device Controller
+
+maintainers:
+  - Neal Liu <neal_liu@aspeedtech.com>
+
+description: |+
+  The ASPEED USB 2.0 Device Controller implements 1 control endpoint and
+  4 generic endpoints for AST260x.
+
+  Supports independent DMA channel for each generic endpoint.
+  Supports 32/256 stages descriptor mode for all generic endpoints.
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2600-udc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/aspeed-clock.h>
+    udc: usb@1e6a2000 {
+        compatible = "aspeed,ast2600-udc";
+        reg = <0x1e6a2000 0x300>;
+        interrupts = <9>;
+        clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb2bd_default>;
+    };
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 8d22a9843ba5..1bfbc6ef16eb 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -11,6 +11,7 @@ maintainers:
 
 allOf:
   - $ref: usb-drd.yaml#
+  - $ref: usb-hcd.yaml#
 
 properties:
   compatible:
@@ -161,6 +162,8 @@ properties:
       property is used.
     $ref: /schemas/graph.yaml#/properties/port
 
+  tpl-support: true
+
 dependencies:
   port: [ usb-role-switch ]
   role-switch-default-mode: [ usb-role-switch ]
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 0b4524b6409e..1e84e1b7ab27 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -136,7 +136,8 @@ properties:
       Phandle of a companion.
 
   phys:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   phy-names:
     const: usb
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index e2ac84665316..bb6bbd5f129d 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -103,7 +103,8 @@ properties:
       Overrides the detected port count
 
   phys:
-    maxItems: 1
+    minItems: 1
+    maxItems: 3
 
   phy-names:
     const: usb
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index 084d7135b2d9..892718459d25 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -113,6 +113,9 @@ properties:
   vbus-supply:
     description: Regulator of USB VBUS5v
 
+  resets:
+    maxItems: 1
+
   usb3-lpm-capable: true
 
   usb2-lpm-disable: true
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
index 37b02a841dc4..e63b66545317 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
@@ -107,6 +107,9 @@ properties:
   maximum-speed:
     enum: [super-speed-plus, super-speed, high-speed, full-speed]
 
+  resets:
+    maxItems: 1
+
   "#address-cells":
     enum: [1, 2]
 
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index d41265ba8ce2..1779d08ba1c0 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -343,6 +343,11 @@ properties:
       This port is used with the 'usb-role-switch' property  to connect the
       dwc3 to type C connector.
 
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable USB remote wakeup.
+
 unevaluatedProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d..7303da874cf3 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -141,6 +141,8 @@ patternProperties:
     description: ASIX Electronics Corporation
   "^aspeed,.*":
     description: ASPEED Technology Inc.
+  "^asrock,.*":
+    description: ASRock Inc.
   "^asus,.*":
     description: AsusTek Computer Inc.
   "^atheros,.*":
@@ -198,12 +200,14 @@ patternProperties:
     description: Broadcom Corporation
   "^bsh,.*":
     description: BSH Hausgeraete GmbH
+  "^bticino,.*":
+    description: Bticino International
   "^buffalo,.*":
     description: Buffalo, Inc.
   "^bur,.*":
     description: B&R Industrial Automation GmbH
-  "^bticino,.*":
-    description: Bticino International
+  "^bytedance,.*":
+    description: ByteDance Ltd.
   "^calamp,.*":
     description: CalAmp Corp.
   "^calaosystems,.*":
@@ -547,6 +551,8 @@ patternProperties:
     description: Shenzhen Hugsun Technology Co. Ltd.
   "^hwacom,.*":
     description: HwaCom Systems Inc.
+  "^hxt,.*":
+    description: HXT Semiconductor
   "^hycon,.*":
     description: Hycon Technology Corp.
   "^hydis,.*":
@@ -581,6 +587,8 @@ patternProperties:
     description: Infineon Technologies
   "^inforce,.*":
     description: Inforce Computing
+  "^ingrasys,.*":
+    description: Ingrasys Technology Inc.
   "^ivo,.*":
     description: InfoVision Optoelectronics Kunshan Co. Ltd.
   "^ingenic,.*":
@@ -601,6 +609,8 @@ patternProperties:
     description: Inter Control Group
   "^invensense,.*":
     description: InvenSense Inc.
+  "^inventec,.*":
+    description: Inventec
   "^inversepath,.*":
     description: Inverse Path
   "^iom,.*":
@@ -1013,6 +1023,8 @@ patternProperties:
     description: Shenzhen QiShenglong Industrialist Co., Ltd.
   "^qnap,.*":
     description: QNAP Systems, Inc.
+  "^quanta,.*":
+    description: Quanta Computer Inc.
   "^radxa,.*":
     description: Radxa
   "^raidsonic,.*":
@@ -1101,6 +1113,8 @@ patternProperties:
     description: SGX Sensortech
   "^sharp,.*":
     description: Sharp Corporation
+  "^shift,.*":
+    description: SHIFT GmbH
   "^shimafuji,.*":
     description: Shimafuji Electric, Inc.
   "^shiratech,.*":
diff --git a/Documentation/doc-guide/kernel-doc.rst b/Documentation/doc-guide/kernel-doc.rst
index a7cb2afd7990..9b868d9eb20f 100644
--- a/Documentation/doc-guide/kernel-doc.rst
+++ b/Documentation/doc-guide/kernel-doc.rst
@@ -12,6 +12,9 @@ when it is embedded in source files.
    reasons. The kernel source contains tens of thousands of kernel-doc
    comments. Please stick to the style described here.
 
+.. note:: kernel-doc does not cover Rust code: please see
+   Documentation/rust/general-information.rst instead.
+
 The kernel-doc structure is extracted from the comments, and proper
 `Sphinx C Domain`_ function and type descriptions with anchors are
 generated from them. The descriptions are filtered for special kernel-doc
diff --git a/Documentation/driver-api/firmware/other_interfaces.rst b/Documentation/driver-api/firmware/other_interfaces.rst
index b81794e0cfbb..06ac89adaafb 100644
--- a/Documentation/driver-api/firmware/other_interfaces.rst
+++ b/Documentation/driver-api/firmware/other_interfaces.rst
@@ -13,6 +13,12 @@ EDD Interfaces
 .. kernel-doc:: drivers/firmware/edd.c
    :internal:
 
+Generic System Framebuffers Interface
+-------------------------------------
+
+.. kernel-doc:: drivers/firmware/sysfb.c
+   :export:
+
 Intel Stratix10 SoC Service Layer
 ---------------------------------
 Some features of the Intel Stratix10 SoC require a level of privilege
diff --git a/Documentation/driver-api/gpio/board.rst b/Documentation/driver-api/gpio/board.rst
index 4e3adf31c8d1..b33aa04f213f 100644
--- a/Documentation/driver-api/gpio/board.rst
+++ b/Documentation/driver-api/gpio/board.rst
@@ -6,7 +6,7 @@ This document explains how GPIOs can be assigned to given devices and functions.
 
 Note that it only applies to the new descriptor-based interface. For a
 description of the deprecated integer-based GPIO interface please refer to
-gpio-legacy.txt (actually, there is no real mapping possible with the old
+legacy.rst (actually, there is no real mapping possible with the old
 interface; you just fetch an integer from somewhere and request the
 corresponding GPIO).
 
diff --git a/Documentation/driver-api/gpio/consumer.rst b/Documentation/driver-api/gpio/consumer.rst
index 47869ca8ccf0..72bcf5f5e3a2 100644
--- a/Documentation/driver-api/gpio/consumer.rst
+++ b/Documentation/driver-api/gpio/consumer.rst
@@ -4,7 +4,7 @@ GPIO Descriptor Consumer Interface
 
 This document describes the consumer interface of the GPIO framework. Note that
 it describes the new descriptor-based interface. For a description of the
-deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
+deprecated integer-based GPIO interface please refer to legacy.rst.
 
 
 Guidelines for GPIOs consumers
@@ -78,7 +78,7 @@ whether the line is configured active high or active low (see
 
 The two last flags are used for use cases where open drain is mandatory, such
 as I2C: if the line is not already configured as open drain in the mappings
-(see board.txt), then open drain will be enforced anyway and a warning will be
+(see board.rst), then open drain will be enforced anyway and a warning will be
 printed that the board configuration needs to be updated to match the use case.
 
 Both functions return either a valid GPIO descriptor, or an error code checkable
@@ -270,7 +270,7 @@ driven.
 The same is applicable for open drain or open source output lines: those do not
 actively drive their output high (open drain) or low (open source), they just
 switch their output to a high impedance value. The consumer should not need to
-care. (For details read about open drain in driver.txt.)
+care. (For details read about open drain in driver.rst.)
 
 With this, all the gpiod_set_(array)_value_xxx() functions interpret the
 parameter "value" as "asserted" ("1") or "de-asserted" ("0"). The physical line
diff --git a/Documentation/driver-api/gpio/intro.rst b/Documentation/driver-api/gpio/intro.rst
index 2e924fb5b3d5..c9c19243b97f 100644
--- a/Documentation/driver-api/gpio/intro.rst
+++ b/Documentation/driver-api/gpio/intro.rst
@@ -14,12 +14,12 @@ Due to the history of GPIO interfaces in the kernel, there are two different
 ways to obtain and use GPIOs:
 
   - The descriptor-based interface is the preferred way to manipulate GPIOs,
-    and is described by all the files in this directory excepted gpio-legacy.txt.
+    and is described by all the files in this directory excepted legacy.rst.
   - The legacy integer-based interface which is considered deprecated (but still
-    usable for compatibility reasons) is documented in gpio-legacy.txt.
+    usable for compatibility reasons) is documented in legacy.rst.
 
 The remainder of this document applies to the new descriptor-based interface.
-gpio-legacy.txt contains the same information applied to the legacy
+legacy.rst contains the same information applied to the legacy
 integer-based interface.
 
 
diff --git a/Documentation/driver-api/serial/serial-rs485.rst b/Documentation/driver-api/serial/serial-rs485.rst
index 6bc824f948f9..00b5d333acba 100644
--- a/Documentation/driver-api/serial/serial-rs485.rst
+++ b/Documentation/driver-api/serial/serial-rs485.rst
@@ -38,10 +38,14 @@ RS485 Serial Communications
    the values given by the device tree.
 
    Any driver for devices capable of working both as RS232 and RS485 should
-   implement the rs485_config callback in the uart_port structure. The
-   serial_core calls rs485_config to do the device specific part in response
-   to TIOCSRS485 and TIOCGRS485 ioctls (see below). The rs485_config callback
-   receives a pointer to struct serial_rs485.
+   implement the rs485_config callback and provide rs485_supported in the
+   uart_port structure. The serial core calls rs485_config to do the device
+   specific part in response to TIOCSRS485 ioctl (see below). The rs485_config
+   callback receives a pointer to a sanitizated serial_rs485 structure. The
+   serial_rs485 userspace provides is sanitized before calling rs485_config
+   using rs485_supported that indicates what RS485 features the driver supports
+   for the uart_port. TIOCGRS485 ioctl can be used to read back the
+   serial_rs485 structure matching to the current configuration.
 
 4. Usage from user-level
 ========================
diff --git a/Documentation/driver-api/surface_aggregator/client.rst b/Documentation/driver-api/surface_aggregator/client.rst
index e519d374c378..27f95abdbe99 100644
--- a/Documentation/driver-api/surface_aggregator/client.rst
+++ b/Documentation/driver-api/surface_aggregator/client.rst
@@ -17,6 +17,8 @@
 .. |SSAM_DEVICE| replace:: :c:func:`SSAM_DEVICE`
 .. |ssam_notifier_register| replace:: :c:func:`ssam_notifier_register`
 .. |ssam_notifier_unregister| replace:: :c:func:`ssam_notifier_unregister`
+.. |ssam_device_notifier_register| replace:: :c:func:`ssam_device_notifier_register`
+.. |ssam_device_notifier_unregister| replace:: :c:func:`ssam_device_notifier_unregister`
 .. |ssam_request_sync| replace:: :c:func:`ssam_request_sync`
 .. |ssam_event_mask| replace:: :c:type:`enum ssam_event_mask <ssam_event_mask>`
 
@@ -312,7 +314,9 @@ Handling Events
 To receive events from the SAM EC, an event notifier must be registered for
 the desired event via |ssam_notifier_register|. The notifier must be
 unregistered via |ssam_notifier_unregister| once it is not required any
-more.
+more. For |ssam_device| type clients, the |ssam_device_notifier_register| and
+|ssam_device_notifier_unregister| wrappers should be preferred as they properly
+handle hot-removal of client devices.
 
 Event notifiers are registered by providing (at minimum) a callback to call
 in case an event has been received, the registry specifying how the event
diff --git a/Documentation/driver-api/vfio-mediated-device.rst b/Documentation/driver-api/vfio-mediated-device.rst
index eded8719180f..66bd00d7aecf 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -1,3 +1,4 @@
+.. SPDX-License-Identifier: GPL-2.0-only
 .. include:: <isonum.txt>
 
 =====================
@@ -8,9 +9,6 @@ VFIO Mediated devices
 :Author: Neo Jia <cjia@nvidia.com>
 :Author: Kirti Wankhede <kwankhede@nvidia.com>
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License version 2 as
-published by the Free Software Foundation.
 
 
 Virtual Function I/O (VFIO) Mediated devices[1]
diff --git a/Documentation/driver-api/vme.rst b/Documentation/driver-api/vme.rst
index def139c13410..c0b475369de0 100644
--- a/Documentation/driver-api/vme.rst
+++ b/Documentation/driver-api/vme.rst
@@ -290,8 +290,8 @@ The function :c:func:`vme_bus_num` returns the bus ID of the provided bridge.
 VME API
 -------
 
-.. kernel-doc:: include/linux/vme.h
+.. kernel-doc:: drivers/staging/vme_user/vme.h
    :internal:
 
-.. kernel-doc:: drivers/vme/vme.c
+.. kernel-doc:: drivers/staging/vme_user/vme.c
    :export:
diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt
index c9e0a16290e6..e59071a49090 100644
--- a/Documentation/features/time/context-tracking/arch-support.txt
+++ b/Documentation/features/time/context-tracking/arch-support.txt
@@ -1,7 +1,7 @@
 #
-# Feature name:          context-tracking
-#         Kconfig:       HAVE_CONTEXT_TRACKING
-#         description:   arch supports context tracking for NO_HZ_FULL
+# Feature name:          user-context-tracking
+#         Kconfig:       HAVE_CONTEXT_TRACKING_USER
+#         description:   arch supports user context tracking for NO_HZ_FULL
 #
     -----------------------
     |         arch |status|
diff --git a/Documentation/filesystems/btrfs.rst b/Documentation/filesystems/btrfs.rst
index d0904f602819..992eddb0e11b 100644
--- a/Documentation/filesystems/btrfs.rst
+++ b/Documentation/filesystems/btrfs.rst
@@ -19,13 +19,23 @@ The main Btrfs features include:
     * Subvolumes (separate internal filesystem roots)
     * Object level mirroring and striping
     * Checksums on data and metadata (multiple algorithms available)
-    * Compression
+    * Compression (multiple algorithms available)
+    * Reflink, deduplication
+    * Scrub (on-line checksum verification)
+    * Hierarchical quota groups (subvolume and snapshot support)
     * Integrated multiple device support, with several raid algorithms
     * Offline filesystem check
-    * Efficient incremental backup and FS mirroring
+    * Efficient incremental backup and FS mirroring (send/receive)
+    * Trim/discard
     * Online filesystem defragmentation
+    * Swapfile support
+    * Zoned mode
+    * Read/write metadata verification
+    * Online resize (shrink, grow)
 
-For more information please refer to the wiki
+For more information please refer to the documentation site or wiki
+
+  https://btrfs.readthedocs.io
 
   https://btrfs.wiki.kernel.org
 
diff --git a/Documentation/filesystems/ext2.rst b/Documentation/filesystems/ext2.rst
index 154101cf0e4f..92aae683e16a 100644
--- a/Documentation/filesystems/ext2.rst
+++ b/Documentation/filesystems/ext2.rst
@@ -59,8 +59,6 @@ acl				Enable POSIX Access Control Lists support
 				(requires CONFIG_EXT2_FS_POSIX_ACL).
 noacl				Don't support POSIX ACLs.
 
-nobh				Do not attach buffer_heads to file pagecache.
-
 quota, usrquota			Enable user disk quota support
 				(requires CONFIG_QUOTA).
 
diff --git a/Documentation/filesystems/fscrypt.rst b/Documentation/filesystems/fscrypt.rst
index 2e9aaa295125..5ba5817c17c2 100644
--- a/Documentation/filesystems/fscrypt.rst
+++ b/Documentation/filesystems/fscrypt.rst
@@ -337,6 +337,7 @@ Currently, the following pairs of encryption modes are supported:
 - AES-256-XTS for contents and AES-256-CTS-CBC for filenames
 - AES-128-CBC for contents and AES-128-CTS-CBC for filenames
 - Adiantum for both contents and filenames
+- AES-256-XTS for contents and AES-256-HCTR2 for filenames (v2 policies only)
 
 If unsure, you should use the (AES-256-XTS, AES-256-CTS-CBC) pair.
 
@@ -357,6 +358,17 @@ To use Adiantum, CONFIG_CRYPTO_ADIANTUM must be enabled.  Also, fast
 implementations of ChaCha and NHPoly1305 should be enabled, e.g.
 CONFIG_CRYPTO_CHACHA20_NEON and CONFIG_CRYPTO_NHPOLY1305_NEON for ARM.
 
+AES-256-HCTR2 is another true wide-block encryption mode that is intended for
+use on CPUs with dedicated crypto instructions.  AES-256-HCTR2 has the property
+that a bitflip in the plaintext changes the entire ciphertext.  This property
+makes it desirable for filename encryption since initialization vectors are
+reused within a directory.  For more details on AES-256-HCTR2, see the paper
+"Length-preserving encryption with HCTR2"
+(https://eprint.iacr.org/2021/1441.pdf).  To use AES-256-HCTR2,
+CONFIG_CRYPTO_HCTR2 must be enabled.  Also, fast implementations of XCTR and
+POLYVAL should be enabled, e.g. CRYPTO_POLYVAL_ARM64_CE and
+CRYPTO_AES_ARM64_CE_BLK for ARM64.
+
 New encryption modes can be added relatively easily, without changes
 to individual filesystems.  However, authenticated encryption (AE)
 modes are not currently supported because of the difficulty of dealing
@@ -404,11 +416,11 @@ alternatively has the file's nonce (for `DIRECT_KEY policies`_) or
 inode number (for `IV_INO_LBLK_64 policies`_) included in the IVs.
 Thus, IV reuse is limited to within a single directory.
 
-With CTS-CBC, the IV reuse means that when the plaintext filenames
-share a common prefix at least as long as the cipher block size (16
-bytes for AES), the corresponding encrypted filenames will also share
-a common prefix.  This is undesirable.  Adiantum does not have this
-weakness, as it is a wide-block encryption mode.
+With CTS-CBC, the IV reuse means that when the plaintext filenames share a
+common prefix at least as long as the cipher block size (16 bytes for AES), the
+corresponding encrypted filenames will also share a common prefix.  This is
+undesirable.  Adiantum and HCTR2 do not have this weakness, as they are
+wide-block encryption modes.
 
 All supported filenames encryption modes accept any plaintext length
 >= 16 bytes; cipher block alignment is not required.  However,
diff --git a/Documentation/filesystems/locking.rst b/Documentation/filesystems/locking.rst
index c0fe711f14d3..4bb2627026ec 100644
--- a/Documentation/filesystems/locking.rst
+++ b/Documentation/filesystems/locking.rst
@@ -252,9 +252,8 @@ prototypes::
 	bool (*release_folio)(struct folio *, gfp_t);
 	void (*free_folio)(struct folio *);
 	int (*direct_IO)(struct kiocb *, struct iov_iter *iter);
-	bool (*isolate_page) (struct page *, isolate_mode_t);
-	int (*migratepage)(struct address_space *, struct page *, struct page *);
-	void (*putback_page) (struct page *);
+	int (*migrate_folio)(struct address_space *, struct folio *dst,
+			struct folio *src, enum migrate_mode);
 	int (*launder_folio)(struct folio *);
 	bool (*is_partially_uptodate)(struct folio *, size_t from, size_t count);
 	int (*error_remove_page)(struct address_space *, struct page *);
@@ -280,9 +279,7 @@ invalidate_folio:	yes					exclusive
 release_folio:		yes
 free_folio:		yes
 direct_IO:
-isolate_page:		yes
-migratepage:		yes (both)
-putback_page:		yes
+migrate_folio:		yes (both)
 launder_folio:		yes
 is_partially_uptodate:	yes
 error_remove_page:	yes
diff --git a/Documentation/filesystems/proc.rst b/Documentation/filesystems/proc.rst
index 1bc91fb8c321..979b699e7d14 100644
--- a/Documentation/filesystems/proc.rst
+++ b/Documentation/filesystems/proc.rst
@@ -448,6 +448,7 @@ Memory Area, or VMA) there is a series of lines such as the following::
     MMUPageSize:           4 kB
     Rss:                 892 kB
     Pss:                 374 kB
+    Pss_Dirty:             0 kB
     Shared_Clean:        892 kB
     Shared_Dirty:          0 kB
     Private_Clean:         0 kB
@@ -479,7 +480,9 @@ dirty shared and private pages in the mapping.
 The "proportional set size" (PSS) of a process is the count of pages it has
 in memory, where each page is divided by the number of processes sharing it.
 So if a process has 1000 pages all to itself, and 1000 shared with one other
-process, its PSS will be 1500.
+process, its PSS will be 1500.  "Pss_Dirty" is the portion of PSS which
+consists of dirty pages.  ("Pss_Clean" is not included, but it can be
+calculated by subtracting "Pss_Dirty" from "Pss".)
 
 Note that even a page which is part of a MAP_SHARED mapping, but has only
 a single pte mapped, i.e.  is currently used by only one process, is accounted
@@ -514,8 +517,10 @@ replaced by copy-on-write) part of the underlying shmem object out on swap.
 "SwapPss" shows proportional swap share of this mapping. Unlike "Swap", this
 does not take into account swapped out page of underlying shmem objects.
 "Locked" indicates whether the mapping is locked in memory or not.
+
 "THPeligible" indicates whether the mapping is eligible for allocating THP
-pages - 1 if true, 0 otherwise. It just shows the current status.
+pages as well as the THP is PMD mappable or not - 1 if true, 0 otherwise.
+It just shows the current status.
 
 "VmFlags" field deserves a separate description. This member represents the
 kernel flags associated with the particular virtual memory area in two letter
diff --git a/Documentation/filesystems/vfs.rst b/Documentation/filesystems/vfs.rst
index 08069ecd49a6..6cd6953e175b 100644
--- a/Documentation/filesystems/vfs.rst
+++ b/Documentation/filesystems/vfs.rst
@@ -737,12 +737,8 @@ cache in your filesystem.  The following members are defined:
 		bool (*release_folio)(struct folio *, gfp_t);
 		void (*free_folio)(struct folio *);
 		ssize_t (*direct_IO)(struct kiocb *, struct iov_iter *iter);
-		/* isolate a page for migration */
-		bool (*isolate_page) (struct page *, isolate_mode_t);
-		/* migrate the contents of a page to the specified target */
-		int (*migratepage) (struct page *, struct page *);
-		/* put migration-failed page back to right list */
-		void (*putback_page) (struct page *);
+		int (*migrate_folio)(struct mapping *, struct folio *dst,
+				struct folio *src, enum migrate_mode);
 		int (*launder_folio) (struct folio *);
 
 		bool (*is_partially_uptodate) (struct folio *, size_t from,
@@ -774,13 +770,38 @@ cache in your filesystem.  The following members are defined:
 	See the file "Locking" for more details.
 
 ``read_folio``
-	called by the VM to read a folio from backing store.  The folio
-	will be locked when read_folio is called, and should be unlocked
-	and marked uptodate once the read completes.  If ->read_folio
-	discovers that it cannot perform the I/O at this time, it can
-        unlock the folio and return AOP_TRUNCATED_PAGE.  In this case,
-	the folio will be looked up again, relocked and if that all succeeds,
-	->read_folio will be called again.
+	Called by the page cache to read a folio from the backing store.
+	The 'file' argument supplies authentication information to network
+	filesystems, and is generally not used by block based filesystems.
+	It may be NULL if the caller does not have an open file (eg if
+	the kernel is performing a read for itself rather than on behalf
+	of a userspace process with an open file).
+
+	If the mapping does not support large folios, the folio will
+	contain a single page.	The folio will be locked when read_folio
+	is called.  If the read completes successfully, the folio should
+	be marked uptodate.  The filesystem should unlock the folio
+	once the read has completed, whether it was successful or not.
+	The filesystem does not need to modify the refcount on the folio;
+	the page cache holds a reference count and that will not be
+	released until the folio is unlocked.
+
+	Filesystems may implement ->read_folio() synchronously.
+	In normal operation, folios are read through the ->readahead()
+	method.  Only if this fails, or if the caller needs to wait for
+	the read to complete will the page cache call ->read_folio().
+	Filesystems should not attempt to perform their own readahead
+	in the ->read_folio() operation.
+
+	If the filesystem cannot perform the read at this time, it can
+	unlock the folio, do whatever action it needs to ensure that the
+	read will succeed in the future and return AOP_TRUNCATED_PAGE.
+	In this case, the caller should look up the folio, lock it,
+	and call ->read_folio again.
+
+	Callers may invoke the ->read_folio() method directly, but using
+	read_mapping_folio() will take care of locking, waiting for the
+	read to complete and handle cases such as AOP_TRUNCATED_PAGE.
 
 ``writepages``
 	called by the VM to write out pages associated with the
@@ -905,20 +926,12 @@ cache in your filesystem.  The following members are defined:
 	data directly between the storage and the application's address
 	space.
 
-``isolate_page``
-	Called by the VM when isolating a movable non-lru page.  If page
-	is successfully isolated, VM marks the page as PG_isolated via
-	__SetPageIsolated.
-
-``migrate_page``
+``migrate_folio``
 	This is used to compact the physical memory usage.  If the VM
-	wants to relocate a page (maybe off a memory card that is
-	signalling imminent failure) it will pass a new page and an old
-	page to this function.  migrate_page should transfer any private
-	data across and update any references that it has to the page.
-
-``putback_page``
-	Called by the VM when isolated page's migration fails.
+	wants to relocate a folio (maybe from a memory device that is
+	signalling imminent failure) it will pass a new folio and an old
+	folio to this function.  migrate_folio should transfer any private
+	data across and update any references that it has to the folio.
 
 ``launder_folio``
 	Called before freeing a folio - it writes back the dirty folio.
diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst
index 6c9f166a8d6f..92c5117368d7 100644
--- a/Documentation/gpu/drm-usage-stats.rst
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -105,6 +105,27 @@ object belong to this client, in the respective memory region.
 Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
 indicating kibi- or mebi-bytes.
 
+- drm-cycles-<str> <uint>
+
+Engine identifier string must be the same as the one specified in the
+drm-engine-<str> tag and shall contain the number of busy cycles for the given
+engine.
+
+Values are not required to be constantly monotonic if it makes the driver
+implementation easier, but are required to catch up with the previously reported
+larger value within a reasonable period. Upon observing a value lower than what
+was previously read, userspace is expected to stay with that larger previous
+value until a monotonic update is seen.
+
+- drm-maxfreq-<str> <uint> [Hz|MHz|KHz]
+
+Engine identifier string must be the same as the one specified in the
+drm-engine-<str> tag and shall contain the maximum frequency for the given
+engine.  Taken together with drm-cycles-<str>, this can be used to calculate
+percentage utilization of the engine, whereas drm-engine-<str> only reflects
+time active without considering what frequency the engine is operating as a
+percentage of it's maximum frequency.
+
 ===============================
 Driver specific implementations
 ===============================
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 10bfb50908d1..513b20ccef1e 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -617,6 +617,17 @@ Contact: Javier Martinez Canillas <javierm@redhat.com>
 
 Level: Intermediate
 
+Convert Kernel Selftests (kselftest) to KUnit tests when appropriate
+--------------------------------------------------------------------
+
+Many of the `Kselftest <https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html>`_
+tests in DRM could be converted to Kunit tests instead, since that framework
+is more suitable for unit testing.
+
+Contact: Javier Martinez Canillas <javierm@redhat.com>
+
+Level: Starter
+
 Enable trinity for DRM
 ----------------------
 
diff --git a/Documentation/gpu/vkms.rst b/Documentation/gpu/vkms.rst
index 9c873c3912cc..973e2d43108b 100644
--- a/Documentation/gpu/vkms.rst
+++ b/Documentation/gpu/vkms.rst
@@ -102,12 +102,6 @@ Debugging:
 
 - kms_plane: some test cases are failing due to timeout on capturing CRC;
 
-- kms_flip: when running test cases in sequence, some successful individual
-  test cases are failing randomly; when individually, some successful test
-  cases display in the log the following error::
-
-  [drm:vkms_prepare_fb [vkms]] ERROR vmap failed: -4
-
 Virtual hardware (vblank-less) mode:
 
 - VKMS already has support for vblanks simulated via hrtimers, which can be
diff --git a/Documentation/hwmon/asus_ec_sensors.rst b/Documentation/hwmon/asus_ec_sensors.rst
index 78ca69eda877..00d8c46ef9e0 100644
--- a/Documentation/hwmon/asus_ec_sensors.rst
+++ b/Documentation/hwmon/asus_ec_sensors.rst
@@ -19,6 +19,7 @@ Supported boards:
  * ROG STRIX X570-E GAMING WIFI II
  * ROG STRIX X570-F GAMING
  * ROG STRIX X570-I GAMING
+ * ROG STRIX Z690-A GAMING WIFI D4
 
 Authors:
     - Eugene Shalygin <eugene.shalygin@gmail.com>
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index a72c16872ec2..f7113b0f8b2a 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -109,6 +109,7 @@ Hardware Monitoring Kernel Drivers
    lm95234
    lm95245
    lochnagar
+   lt7182s
    ltc2992
    ltc2945
    ltc2947
diff --git a/Documentation/hwmon/lm90.rst b/Documentation/hwmon/lm90.rst
index 05391fb4042d..23af17a0ab44 100644
--- a/Documentation/hwmon/lm90.rst
+++ b/Documentation/hwmon/lm90.rst
@@ -3,6 +3,14 @@ Kernel driver lm90
 
 Supported chips:
 
+  * National Semiconductor LM84
+
+    Prefix: 'lm84'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the National Semiconductor website
+
   * National Semiconductor LM90
 
     Prefix: 'lm90'
@@ -43,6 +51,30 @@ Supported chips:
 
 	       http://www.national.com/mpf/LM/LM86.html
 
+  * Analog Devices ADM1020
+
+    Prefix: 'adm1020'
+
+    Addresses scanned: I2C 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Analog Devices website
+
+  * Analog Devices ADM1021
+
+    Prefix: 'adm1021'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Analog Devices website
+
+  * Analog Devices ADM1021A/ADM1023
+
+    Prefix: 'adm1023'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Analog Devices website
+
   * Analog Devices ADM1032
 
     Prefix: 'adm1032'
@@ -73,6 +105,36 @@ Supported chips:
 
 	       https://www.onsemi.com/PowerSolutions/product.do?id=ADT7461A
 
+  * Analog Devices ADT7481
+
+    Prefix: 'adt7481'
+
+    Addresses scanned: I2C 0x4b and 0x4c
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=ADT7481
+
+  * Analog Devices ADT7482
+
+    Prefix: 'adt7482'
+
+    Addresses scanned: I2C 0x4c
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=ADT7482
+
+  * Analog Devices ADT7483A
+
+    Prefix: 'adt7483a'
+
+    Addresses scanned: I2C 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, 0x4d, 0x4e
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=ADT7483A
+
   * ON Semiconductor NCT1008
 
     Prefix: 'nct1008'
@@ -83,6 +145,72 @@ Supported chips:
 
 	       https://www.onsemi.com/PowerSolutions/product.do?id=NCT1008
 
+  * ON Semiconductor NCT210
+
+    Prefix: 'adm1021'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=NCT210
+
+  * ON Semiconductor NCT214
+
+    Prefix: 'nct214'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=NCT214
+
+  * ON Semiconductor NCT218
+
+    Prefix: 'nct218'
+
+    Addresses scanned: I2C 0x4c - 0x4d
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=NCT218
+
+  * ON Semiconductor NCT72
+
+    Prefix: 'nct72'
+
+    Addresses scanned: I2C 0x4c - 0x4d
+
+    Datasheet: Publicly available at the ON Semiconductor website
+
+	       https://www.onsemi.com/PowerSolutions/product.do?id=NCT72
+
+  * Maxim MAX1617
+
+    Prefix: 'max1617'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Maxim website
+
+  * Maxim MAX1617A
+
+    Prefix: 'max1617a'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Maxim website
+
+  * Maxim MAX6642
+
+    Prefix: 'max6642'
+
+    Addresses scanned: I2C 0x48-0x4f
+
+    Datasheet: Publicly available at the Maxim website
+
+	       http://datasheets.maxim-ic.com/en/ds/MAX6642.pdf
+
   * Maxim MAX6646
 
     Prefix: 'max6646'
@@ -105,7 +233,7 @@ Supported chips:
 
   * Maxim MAX6648
 
-    Prefix: 'max6646'
+    Prefix: 'max6648'
 
     Addresses scanned: I2C 0x4c
 
@@ -191,7 +319,7 @@ Supported chips:
 
   * Maxim MAX6692
 
-    Prefix: 'max6646'
+    Prefix: 'max6648'
 
     Addresses scanned: I2C 0x4c
 
@@ -275,6 +403,46 @@ Supported chips:
 
 	       https://www.ti.com/lit/gpn/tmp461
 
+  * Philips NE1617, NE1617A
+
+    Prefix: 'max1617' (probably detected as a max1617)
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheets: Publicly available at the Philips website
+
+  * Philips NE1618
+
+    Prefix: 'ne1618'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheets: Publicly available at the Philips website
+
+  * Genesys Logic GL523SM
+
+    Prefix: 'gl523sm'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet:
+
+  * TI THMC10
+
+    Prefix: 'thmc10'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the TI website
+
+  * Onsemi MC1066
+
+    Prefix: 'mc1066'
+
+    Addresses scanned: I2C 0x18 - 0x1a, 0x29 - 0x2b, 0x4c - 0x4e
+
+    Datasheet: Publicly available at the Onsemi website
+
 Author: Jean Delvare <jdelvare@suse.de>
 
 
@@ -285,6 +453,12 @@ The LM90 is a digital temperature sensor. It senses its own temperature as
 well as the temperature of up to one external diode. It is compatible
 with many other devices, many of which are supported by this driver.
 
+The family of chips supported by this driver is derived from MAX1617.
+This chip as well as various compatible chips support a local and a remote
+temperature sensor with 8 bit accuracy. Later chips provide improved accuracy
+and other additional features such as hysteresis and temperature offset
+registers.
+
 Note that there is no easy way to differentiate between the MAX6657,
 MAX6658 and MAX6659 variants. The extra features of the MAX6659 are only
 supported by this driver if the chip is located at address 0x4d or 0x4e,
@@ -292,15 +466,31 @@ or if the chip type is explicitly selected as max6659.
 The MAX6680 and MAX6681 only differ in their pinout, therefore they obviously
 can't (and don't need to) be distinguished.
 
-The specificity of this family of chipsets over the ADM1021/LM84
-family is that it features critical limits with hysteresis, and an
-increased resolution of the remote temperature measurement.
-
 The different chipsets of the family are not strictly identical, although
 very similar. For reference, here comes a non-exhaustive list of specific
 features:
 
+LM84:
+  * 8 bit sensor resolution
+
+ADM1020, ADM1021, GL523SM, MAX1617, NE1617, NE1617A, THMC10:
+  * 8 bit sensor resolution
+  * Low temperature limits
+
+NCT210, NE1618:
+  * 11 bit sensor resolution for remote temperature sensor
+  * Low temperature limits
+
+ADM1021A, ADM1023:
+  * Temperature offset register for remote temperature sensor
+  * 11 bit resolution for remote temperature sensor
+  * Low temperature limits
+
 LM90:
+  * 11 bit resolution for remote temperature sensor
+  * Temperature offset register for remote temperature sensor
+  * Low and critical temperature limits
+  * Configurable conversion rate
   * Filter and alert configuration register at 0xBF.
   * ALERT is triggered by temperatures over critical limits.
 
@@ -322,8 +512,31 @@ ADM1032:
 ADT7461, ADT7461A, NCT1008:
   * Extended temperature range (breaks compatibility)
   * Lower resolution for remote temperature
+  * SMBus PEC support for Write Byte and Receive Byte transactions.
+  * 10 bit temperature resolution
+
+ADT7481, ADT7482, ADT7483:
+  * Temperature offset register
+  * SMBus PEC support
+  * 10 bit temperature resolution for external sensors
+  * Two remote sensors
+  * Selectable address (ADT7483)
+
+MAX6642:
+  * No critical limit register
+  * Conversion rate not configurable
+  * Better local resolution (10 bit)
+  * 10 bit external sensor resolution
+
+MAX6646, MAX6647, MAX6649:
+  * Better local resolution
+  * Extended range unsigned external temperature
+
+MAX6648, MAX6692:
+  * Better local resolution
+  * Unsigned temperature
 
-MAX6654:
+MAX6654, MAX6690:
   * Better local resolution
   * Selectable address
   * Remote sensor type selection
@@ -423,6 +636,6 @@ two transactions will typically mean twice as much delay waiting for
 transaction completion, effectively doubling the register cache refresh time.
 I guess reliability comes at a price, but it's quite expensive this time.
 
-So, as not everyone might enjoy the slowdown, PEC can be disabled through
-sysfs. Just write 0 to the "pec" file and PEC will be disabled. Write 1
-to that file to enable PEC again.
+So, as not everyone might enjoy the slowdown, PEC is disabled by default and
+can be enabled through sysfs. Just write 1 to the "pec" file and PEC will be
+enabled. Write 0 to that file to disable PEC again.
diff --git a/Documentation/hwmon/lt7182s.rst b/Documentation/hwmon/lt7182s.rst
new file mode 100644
index 000000000000..f7268311b191
--- /dev/null
+++ b/Documentation/hwmon/lt7182s.rst
@@ -0,0 +1,92 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver lt7182s
+=====================
+
+Supported chips:
+
+  * ADI LT7182S
+
+    Prefix: 'lt7182s'
+
+    Addresses scanned: -
+
+    Datasheet: https://www.analog.com/en/products/lt7182s.html
+
+Author: Guenter Roeck <linux@roeck-us.net>
+
+
+Description
+-----------
+
+LT7182S is a Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher with
+Digital Power System Management support.
+
+
+Usage Notes
+-----------
+
+This driver does not probe for PMBus devices. You will have to instantiate
+devices explicitly.
+
+Example: the following commands will load the driver for a LT7182S
+at address 0x4f on I2C bus #4::
+
+    # modprobe lt7182s
+    # echo lt7182s 0x4f > /sys/bus/i2c/devices/i2c-4/new_device
+
+It can also be instantiated by declaring an entry in device tree.
+
+
+Sysfs attributes
+----------------
+
+======================= ====================================
+curr[1-2]_label		"iin[12]"
+curr[1-2]_input		Measured input current
+curr[1-2]_max		Maximum input current
+curr[1-2]_max_alarm	Current high alarm
+
+curr[3-4]_label		"iout[1-2]"
+curr[3-4]_input		Measured output current
+curr[3-4]_highest	Highest measured output current
+curr[3-4]_max		Maximum output current
+curr[3-4]_max_alarm	Output current high alarm
+
+in[1-2]_label		"vin[12]"
+in[1-2]_input		Measured input voltage
+in[1-2]_highest		Highest measured input voltage
+in[1-2]_crit		Critical maximum input voltage
+in[1-2]_crit_alarm	Input voltage critical high alarm
+in[1-2]_min		Minimum input voltage
+in[1-2]_min_alarm	Input voltage low alarm
+in[1-2]_rated_min	Rated minimum input voltage
+in[1-2]_rated_max	Rated maximum input voltage
+in1_reset_history	Write to reset history for all attributes
+
+in[3-5]_label		"vmon[1-3]"
+in[3-5]_input		Measured voltage on ITH1/ITH2/EXTVCC pins
+			Only available if enabled with MFR_ADC_CONTROL_LT7182S
+			command.
+
+in[3-4|6-7]_label	"vout[1-2]"
+in[3-4|6-7]_input	Measured output voltage
+in[3-4|6-7]_highest	Highest measured output voltage
+in[3-4|6-7]_lcrit	Critical minimum output voltage
+in[3-4|6-7]_lcrit_alarm	Output voltage critical low alarm
+in[3-4|6-7]_min		Minimum output voltage
+in[3-4|6-7]_max_alarm	Output voltage low alarm
+in[3-4|6-7]_max		Maximum output voltage
+in[3-4|6-7]_max_alarm	Output voltage high alarm
+in[3-4|6-7]_crit	Critical maximum output voltage
+in[3-4|6-7]_crit_alarm	Output voltage critical high alarm
+
+power[1-2]_label	"pout[1-2]"
+power[1-2]_input	Measured output power
+
+temp1_input		Measured temperature
+temp1_crit		Critical high temperature
+temp1_crit_alarm	Chip temperature critical high alarm
+temp1_max		Maximum temperature
+temp1_max_alarm		Chip temperature high alarm
+======================= ====================================
diff --git a/Documentation/hwmon/pmbus-core.rst b/Documentation/hwmon/pmbus-core.rst
index e7e0c9ef10be..84c5a4e40c40 100644
--- a/Documentation/hwmon/pmbus-core.rst
+++ b/Documentation/hwmon/pmbus-core.rst
@@ -121,6 +121,15 @@ Specifically, it provides the following information.
   non-standard PMBus commands to standard commands, or to augment standard
   command return values with device specific information.
 
+PEC Support
+===========
+
+Many PMBus devices support SMBus PEC (Packet Error Checking). If supported
+by both the I2C adapter and by the PMBus chip, it is by default enabled.
+If PEC is supported, the PMBus core driver adds an attribute named 'pec' to
+the I2C device. This attribute can be used to control PEC support in the
+communication with the PMBus chip.
+
 API functions
 =============
 
diff --git a/Documentation/index.rst b/Documentation/index.rst
index 67036a05b771..35d90903242a 100644
--- a/Documentation/index.rst
+++ b/Documentation/index.rst
@@ -82,6 +82,7 @@ merged much easier.
    maintainer/index
    fault-injection/index
    livepatch/index
+   rust/index
 
 
 Kernel API documentation
diff --git a/Documentation/kbuild/kbuild.rst b/Documentation/kbuild/kbuild.rst
index ef19b9c13523..08f575e6236c 100644
--- a/Documentation/kbuild/kbuild.rst
+++ b/Documentation/kbuild/kbuild.rst
@@ -48,6 +48,10 @@ KCFLAGS
 -------
 Additional options to the C compiler (for built-in and modules).
 
+KRUSTFLAGS
+----------
+Additional options to the Rust compiler (for built-in and modules).
+
 CFLAGS_KERNEL
 -------------
 Additional options for $(CC) when used to compile
@@ -57,6 +61,15 @@ CFLAGS_MODULE
 -------------
 Additional module specific options to use for $(CC).
 
+RUSTFLAGS_KERNEL
+----------------
+Additional options for $(RUSTC) when used to compile
+code that is compiled as built-in.
+
+RUSTFLAGS_MODULE
+----------------
+Additional module specific options to use for $(RUSTC).
+
 LDFLAGS_MODULE
 --------------
 Additional options used for $(LD) when linking modules.
@@ -69,6 +82,10 @@ HOSTCXXFLAGS
 ------------
 Additional flags to be passed to $(HOSTCXX) when building host programs.
 
+HOSTRUSTFLAGS
+-------------
+Additional flags to be passed to $(HOSTRUSTC) when building host programs.
+
 HOSTLDFLAGS
 -----------
 Additional flags to be passed when linking host programs.
diff --git a/Documentation/kbuild/llvm.rst b/Documentation/kbuild/llvm.rst
index b854bb413164..6b2bac8e9ce0 100644
--- a/Documentation/kbuild/llvm.rst
+++ b/Documentation/kbuild/llvm.rst
@@ -129,18 +129,24 @@ yet. Bug reports are always welcome at the issue tracker below!
    * - arm64
      - Supported
      - ``LLVM=1``
+   * - hexagon
+     - Maintained
+     - ``LLVM=1``
    * - mips
      - Maintained
-     - ``CC=clang``
+     - ``LLVM=1``
    * - powerpc
      - Maintained
      - ``CC=clang``
    * - riscv
      - Maintained
-     - ``CC=clang``
+     - ``LLVM=1``
    * - s390
      - Maintained
      - ``CC=clang``
+   * - um (User Mode)
+     - Maintained
+     - ``LLVM=1``
    * - x86
      - Supported
      - ``LLVM=1``
diff --git a/Documentation/kbuild/makefiles.rst b/Documentation/kbuild/makefiles.rst
index 11a296e52d68..5ea1e72d89c8 100644
--- a/Documentation/kbuild/makefiles.rst
+++ b/Documentation/kbuild/makefiles.rst
@@ -29,8 +29,9 @@ This document describes the Linux kernel Makefiles.
 	   --- 4.1 Simple Host Program
 	   --- 4.2 Composite Host Programs
 	   --- 4.3 Using C++ for host programs
-	   --- 4.4 Controlling compiler options for host programs
-	   --- 4.5 When host programs are actually built
+	   --- 4.4 Using Rust for host programs
+	   --- 4.5 Controlling compiler options for host programs
+	   --- 4.6 When host programs are actually built
 
 	=== 5 Userspace Program support
 	   --- 5.1 Simple Userspace Program
@@ -835,7 +836,24 @@ Both possibilities are described in the following.
 		qconf-cxxobjs := qconf.o
 		qconf-objs    := check.o
 
-4.4 Controlling compiler options for host programs
+4.4 Using Rust for host programs
+--------------------------------
+
+	Kbuild offers support for host programs written in Rust. However,
+	since a Rust toolchain is not mandatory for kernel compilation,
+	it may only be used in scenarios where Rust is required to be
+	available (e.g. when  ``CONFIG_RUST`` is enabled).
+
+	Example::
+
+		hostprogs     := target
+		target-rust   := y
+
+	Kbuild will compile ``target`` using ``target.rs`` as the crate root,
+	located in the same directory as the ``Makefile``. The crate may
+	consist of several source files (see ``samples/rust/hostprogs``).
+
+4.5 Controlling compiler options for host programs
 --------------------------------------------------
 
 	When compiling host programs, it is possible to set specific flags.
@@ -867,7 +885,7 @@ Both possibilities are described in the following.
 	When linking qconf, it will be passed the extra option
 	"-L$(QTDIR)/lib".
 
-4.5 When host programs are actually built
+4.6 When host programs are actually built
 -----------------------------------------
 
 	Kbuild will only build host-programs when they are referenced
@@ -1181,6 +1199,17 @@ When kbuild executes, the following steps are followed (roughly):
 	The first example utilises the trick that a config option expands
 	to 'y' when selected.
 
+    KBUILD_RUSTFLAGS
+	$(RUSTC) compiler flags
+
+	Default value - see top level Makefile
+	Append or modify as required per architecture.
+
+	Often, the KBUILD_RUSTFLAGS variable depends on the configuration.
+
+	Note that target specification file generation (for ``--target``)
+	is handled in ``scripts/generate_rust_target.rs``.
+
     KBUILD_AFLAGS_KERNEL
 	Assembler options specific for built-in
 
@@ -1208,6 +1237,19 @@ When kbuild executes, the following steps are followed (roughly):
 	are used for $(CC).
 	From commandline CFLAGS_MODULE shall be used (see kbuild.rst).
 
+    KBUILD_RUSTFLAGS_KERNEL
+	$(RUSTC) options specific for built-in
+
+	$(KBUILD_RUSTFLAGS_KERNEL) contains extra Rust compiler flags used to
+	compile resident kernel code.
+
+    KBUILD_RUSTFLAGS_MODULE
+	Options for $(RUSTC) when building modules
+
+	$(KBUILD_RUSTFLAGS_MODULE) is used to add arch-specific options that
+	are used for $(RUSTC).
+	From commandline RUSTFLAGS_MODULE shall be used (see kbuild.rst).
+
     KBUILD_LDFLAGS_MODULE
 	Options for $(LD) when linking modules
 
diff --git a/Documentation/litmus-tests/locking/DCL-broken.litmus b/Documentation/litmus-tests/locking/DCL-broken.litmus
new file mode 100644
index 000000000000..cfaa25ff82b1
--- /dev/null
+++ b/Documentation/litmus-tests/locking/DCL-broken.litmus
@@ -0,0 +1,55 @@
+C DCL-broken
+
+(*
+ * Result: Sometimes
+ *
+ * This litmus test demonstrates more than just locking is required to
+ * correctly implement double-checked locking.
+ *)
+
+{
+	int flag;
+	int data;
+	int lck;
+}
+
+P0(int *flag, int *data, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	r0 = READ_ONCE(*flag);
+	if (r0 == 0) {
+		spin_lock(lck);
+		r1 = READ_ONCE(*flag);
+		if (r1 == 0) {
+			WRITE_ONCE(*data, 1);
+			WRITE_ONCE(*flag, 1);
+		}
+		spin_unlock(lck);
+	}
+	r2 = READ_ONCE(*data);
+}
+
+P1(int *flag, int *data, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	r0 = READ_ONCE(*flag);
+	if (r0 == 0) {
+		spin_lock(lck);
+		r1 = READ_ONCE(*flag);
+		if (r1 == 0) {
+			WRITE_ONCE(*data, 1);
+			WRITE_ONCE(*flag, 1);
+		}
+		spin_unlock(lck);
+	}
+	r2 = READ_ONCE(*data);
+}
+
+locations [flag;data;lck;0:r0;0:r1;1:r0;1:r1]
+exists (0:r2=0 \/ 1:r2=0)
diff --git a/Documentation/litmus-tests/locking/DCL-fixed.litmus b/Documentation/litmus-tests/locking/DCL-fixed.litmus
new file mode 100644
index 000000000000..579d6c246f16
--- /dev/null
+++ b/Documentation/litmus-tests/locking/DCL-fixed.litmus
@@ -0,0 +1,56 @@
+C DCL-fixed
+
+(*
+ * Result: Never
+ *
+ * This litmus test demonstrates that double-checked locking can be
+ * reliable given proper use of smp_load_acquire() and smp_store_release()
+ * in addition to the locking.
+ *)
+
+{
+	int flag;
+	int data;
+	int lck;
+}
+
+P0(int *flag, int *data, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	r0 = smp_load_acquire(flag);
+	if (r0 == 0) {
+		spin_lock(lck);
+		r1 = READ_ONCE(*flag);
+		if (r1 == 0) {
+			WRITE_ONCE(*data, 1);
+			smp_store_release(flag, 1);
+		}
+		spin_unlock(lck);
+	}
+	r2 = READ_ONCE(*data);
+}
+
+P1(int *flag, int *data, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	r0 = smp_load_acquire(flag);
+	if (r0 == 0) {
+		spin_lock(lck);
+		r1 = READ_ONCE(*flag);
+		if (r1 == 0) {
+			WRITE_ONCE(*data, 1);
+			smp_store_release(flag, 1);
+		}
+		spin_unlock(lck);
+	}
+	r2 = READ_ONCE(*data);
+}
+
+locations [flag;data;lck;0:r0;0:r1;1:r0;1:r1]
+exists (0:r2=0 \/ 1:r2=0)
diff --git a/Documentation/litmus-tests/locking/RM-broken.litmus b/Documentation/litmus-tests/locking/RM-broken.litmus
new file mode 100644
index 000000000000..c586ae4b547d
--- /dev/null
+++ b/Documentation/litmus-tests/locking/RM-broken.litmus
@@ -0,0 +1,42 @@
+C RM-broken
+
+(*
+ * Result: DEADLOCK
+ *
+ * This litmus test demonstrates that the old "roach motel" approach
+ * to locking, where code can be freely moved into critical sections,
+ * cannot be used in the Linux kernel.
+ *)
+
+{
+	int lck;
+	int x;
+	int y;
+}
+
+P0(int *x, int *y, int *lck)
+{
+	int r2;
+
+	spin_lock(lck);
+	r2 = atomic_inc_return(y);
+	WRITE_ONCE(*x, 1);
+	spin_unlock(lck);
+}
+
+P1(int *x, int *y, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	spin_lock(lck);
+	r0 = READ_ONCE(*x);
+	r1 = READ_ONCE(*x);
+	r2 = atomic_inc_return(y);
+	spin_unlock(lck);
+}
+
+locations [x;lck;0:r2;1:r0;1:r1;1:r2]
+filter (y=2 /\ 1:r0=0 /\ 1:r1=1)
+exists (1:r2=1)
diff --git a/Documentation/litmus-tests/locking/RM-fixed.litmus b/Documentation/litmus-tests/locking/RM-fixed.litmus
new file mode 100644
index 000000000000..672856736b42
--- /dev/null
+++ b/Documentation/litmus-tests/locking/RM-fixed.litmus
@@ -0,0 +1,42 @@
+C RM-fixed
+
+(*
+ * Result: Never
+ *
+ * This litmus test demonstrates that the old "roach motel" approach
+ * to locking, where code can be freely moved into critical sections,
+ * cannot be used in the Linux kernel.
+ *)
+
+{
+	int lck;
+	int x;
+	int y;
+}
+
+P0(int *x, int *y, int *lck)
+{
+	int r2;
+
+	spin_lock(lck);
+	r2 = atomic_inc_return(y);
+	WRITE_ONCE(*x, 1);
+	spin_unlock(lck);
+}
+
+P1(int *x, int *y, int *lck)
+{
+	int r0;
+	int r1;
+	int r2;
+
+	r0 = READ_ONCE(*x);
+	r1 = READ_ONCE(*x);
+	spin_lock(lck);
+	r2 = atomic_inc_return(y);
+	spin_unlock(lck);
+}
+
+locations [x;lck;0:r2;1:r0;1:r1;1:r2]
+filter (y=2 /\ 1:r0=0 /\ 1:r1=1)
+exists (1:r2=1)
diff --git a/Documentation/networking/tls.rst b/Documentation/networking/tls.rst
index 8cb2cd4e2a80..be8e10c14b05 100644
--- a/Documentation/networking/tls.rst
+++ b/Documentation/networking/tls.rst
@@ -214,6 +214,31 @@ of calling send directly after a handshake using gnutls.
 Since it doesn't implement a full record layer, control
 messages are not supported.
 
+Optional optimizations
+----------------------
+
+There are certain condition-specific optimizations the TLS ULP can make,
+if requested. Those optimizations are either not universally beneficial
+or may impact correctness, hence they require an opt-in.
+All options are set per-socket using setsockopt(), and their
+state can be checked using getsockopt() and via socket diag (``ss``).
+
+TLS_TX_ZEROCOPY_RO
+~~~~~~~~~~~~~~~~~~
+
+For device offload only. Allow sendfile() data to be transmitted directly
+to the NIC without making an in-kernel copy. This allows true zero-copy
+behavior when device offload is enabled.
+
+The application must make sure that the data is not modified between being
+submitted and transmission completing. In other words this is mostly
+applicable if the data sent on a socket via sendfile() is read-only.
+
+Modifying the data may result in different versions of the data being used
+for the original TCP transmission and TCP retransmissions. To the receiver
+this will look like TLS records had been tampered with and will result
+in record authentication failures.
+
 Statistics
 ==========
 
diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst
index 19c286c23786..e03747566cbd 100644
--- a/Documentation/process/changes.rst
+++ b/Documentation/process/changes.rst
@@ -31,6 +31,8 @@ you probably needn't concern yourself with pcmciautils.
 ====================== ===============  ========================================
 GNU C                  5.1              gcc --version
 Clang/LLVM (optional)  11.0.0           clang --version
+Rust (optional)        1.60.0           rustc --version
+bindgen (optional)     0.56.0           bindgen --version
 GNU make               3.81             make --version
 bash                   4.2              bash --version
 binutils               2.23             ld -v
@@ -80,6 +82,29 @@ kernels. Older releases aren't guaranteed to work, and we may drop workarounds
 from the kernel that were used to support older versions. Please see additional
 docs on :ref:`Building Linux with Clang/LLVM <kbuild_llvm>`.
 
+Rust (optional)
+---------------
+
+A particular version of the Rust toolchain is required. Newer versions may or
+may not work because the kernel depends on some unstable Rust features, for
+the moment.
+
+Each Rust toolchain comes with several "components", some of which are required
+(like ``rustc``) and some that are optional. The ``rust-src`` component (which
+is optional) needs to be installed to build the kernel. Other components are
+useful for developing.
+
+Please see Documentation/rust/quick-start.rst for instructions on how to
+satisfy the build requirements of Rust support. In particular, the ``Makefile``
+target ``rustavailable`` is useful to check why the Rust toolchain may not
+be detected.
+
+bindgen (optional)
+------------------
+
+``bindgen`` is used to generate the Rust bindings to the C side of the kernel.
+It depends on ``libclang``.
+
 Make
 ----
 
@@ -348,6 +373,12 @@ Sphinx
 Please see :ref:`sphinx_install` in :ref:`Documentation/doc-guide/sphinx.rst <sphinxdoc>`
 for details about Sphinx requirements.
 
+rustdoc
+-------
+
+``rustdoc`` is used to generate the documentation for Rust code. Please see
+Documentation/rust/general-information.rst for more information.
+
 Getting updated software
 ========================
 
@@ -364,6 +395,16 @@ Clang/LLVM
 
 - :ref:`Getting LLVM <getting_llvm>`.
 
+Rust
+----
+
+- Documentation/rust/quick-start.rst.
+
+bindgen
+-------
+
+- Documentation/rust/quick-start.rst.
+
 Make
 ----
 
diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst
new file mode 100644
index 000000000000..79ebad889720
--- /dev/null
+++ b/Documentation/rust/arch-support.rst
@@ -0,0 +1,25 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Arch Support
+============
+
+Currently, the Rust compiler (``rustc``) uses LLVM for code generation,
+which limits the supported architectures that can be targeted. In addition,
+support for building the kernel with LLVM/Clang varies (please see
+Documentation/kbuild/llvm.rst). This support is needed for ``bindgen``
+which uses ``libclang``.
+
+Below is a general summary of architectures that currently work. Level of
+support corresponds to ``S`` values in the ``MAINTAINERS`` file.
+
+============  ================  ==============================================
+Architecture  Level of support  Constraints
+============  ================  ==============================================
+``arm``       Maintained        ``armv6`` and compatible only,
+                                ``RUST_OPT_LEVEL >= 2``.
+``arm64``     Maintained        None.
+``powerpc``   Maintained        ``ppc64le`` only, ``RUST_OPT_LEVEL < 2``
+                                requires ``CONFIG_THREAD_SHIFT=15``.
+``riscv``     Maintained        ``riscv64`` only.
+``x86``       Maintained        ``x86_64`` only.
+============  ================  ==============================================
diff --git a/Documentation/rust/coding-guidelines.rst b/Documentation/rust/coding-guidelines.rst
new file mode 100644
index 000000000000..aa8ed082613e
--- /dev/null
+++ b/Documentation/rust/coding-guidelines.rst
@@ -0,0 +1,216 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Coding Guidelines
+=================
+
+This document describes how to write Rust code in the kernel.
+
+
+Style & formatting
+------------------
+
+The code should be formatted using ``rustfmt``. In this way, a person
+contributing from time to time to the kernel does not need to learn and
+remember one more style guide. More importantly, reviewers and maintainers
+do not need to spend time pointing out style issues anymore, and thus
+less patch roundtrips may be needed to land a change.
+
+.. note:: Conventions on comments and documentation are not checked by
+  ``rustfmt``. Thus those are still needed to be taken care of.
+
+The default settings of ``rustfmt`` are used. This means the idiomatic Rust
+style is followed. For instance, 4 spaces are used for indentation rather
+than tabs.
+
+It is convenient to instruct editors/IDEs to format while typing,
+when saving or at commit time. However, if for some reason reformatting
+the entire kernel Rust sources is needed at some point, the following can be
+run::
+
+	make LLVM=1 rustfmt
+
+It is also possible to check if everything is formatted (printing a diff
+otherwise), for instance for a CI, with::
+
+	make LLVM=1 rustfmtcheck
+
+Like ``clang-format`` for the rest of the kernel, ``rustfmt`` works on
+individual files, and does not require a kernel configuration. Sometimes it may
+even work with broken code.
+
+
+Comments
+--------
+
+"Normal" comments (i.e. ``//``, rather than code documentation which starts
+with ``///`` or ``//!``) are written in Markdown the same way as documentation
+comments are, even though they will not be rendered. This improves consistency,
+simplifies the rules and allows to move content between the two kinds of
+comments more easily. For instance:
+
+.. code-block:: rust
+
+	// `object` is ready to be handled now.
+	f(object);
+
+Furthermore, just like documentation, comments are capitalized at the beginning
+of a sentence and ended with a period (even if it is a single sentence). This
+includes ``// SAFETY:``, ``// TODO:`` and other "tagged" comments, e.g.:
+
+.. code-block:: rust
+
+	// FIXME: The error should be handled properly.
+
+Comments should not be used for documentation purposes: comments are intended
+for implementation details, not users. This distinction is useful even if the
+reader of the source file is both an implementor and a user of an API. In fact,
+sometimes it is useful to use both comments and documentation at the same time.
+For instance, for a ``TODO`` list or to comment on the documentation itself.
+For the latter case, comments can be inserted in the middle; that is, closer to
+the line of documentation to be commented. For any other case, comments are
+written after the documentation, e.g.:
+
+.. code-block:: rust
+
+	/// Returns a new [`Foo`].
+	///
+	/// # Examples
+	///
+	// TODO: Find a better example.
+	/// ```
+	/// let foo = f(42);
+	/// ```
+	// FIXME: Use fallible approach.
+	pub fn f(x: i32) -> Foo {
+	    // ...
+	}
+
+One special kind of comments are the ``// SAFETY:`` comments. These must appear
+before every ``unsafe`` block, and they explain why the code inside the block is
+correct/sound, i.e. why it cannot trigger undefined behavior in any case, e.g.:
+
+.. code-block:: rust
+
+	// SAFETY: `p` is valid by the safety requirements.
+	unsafe { *p = 0; }
+
+``// SAFETY:`` comments are not to be confused with the ``# Safety`` sections
+in code documentation. ``# Safety`` sections specify the contract that callers
+(for functions) or implementors (for traits) need to abide by. ``// SAFETY:``
+comments show why a call (for functions) or implementation (for traits) actually
+respects the preconditions stated in a ``# Safety`` section or the language
+reference.
+
+
+Code documentation
+------------------
+
+Rust kernel code is not documented like C kernel code (i.e. via kernel-doc).
+Instead, the usual system for documenting Rust code is used: the ``rustdoc``
+tool, which uses Markdown (a lightweight markup language).
+
+To learn Markdown, there are many guides available out there. For instance,
+the one at:
+
+	https://commonmark.org/help/
+
+This is how a well-documented Rust function may look like:
+
+.. code-block:: rust
+
+	/// Returns the contained [`Some`] value, consuming the `self` value,
+	/// without checking that the value is not [`None`].
+	///
+	/// # Safety
+	///
+	/// Calling this method on [`None`] is *[undefined behavior]*.
+	///
+	/// [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html
+	///
+	/// # Examples
+	///
+	/// ```
+	/// let x = Some("air");
+	/// assert_eq!(unsafe { x.unwrap_unchecked() }, "air");
+	/// ```
+	pub unsafe fn unwrap_unchecked(self) -> T {
+	    match self {
+	        Some(val) => val,
+
+	        // SAFETY: The safety contract must be upheld by the caller.
+	        None => unsafe { hint::unreachable_unchecked() },
+	    }
+	}
+
+This example showcases a few ``rustdoc`` features and some conventions followed
+in the kernel:
+
+  - The first paragraph must be a single sentence briefly describing what
+    the documented item does. Further explanations must go in extra paragraphs.
+
+  - Unsafe functions must document their safety preconditions under
+    a ``# Safety`` section.
+
+  - While not shown here, if a function may panic, the conditions under which
+    that happens must be described under a ``# Panics`` section.
+
+    Please note that panicking should be very rare and used only with a good
+    reason. In almost all cases, a fallible approach should be used, typically
+    returning a ``Result``.
+
+  - If providing examples of usage would help readers, they must be written in
+    a section called ``# Examples``.
+
+  - Rust items (functions, types, constants...) must be linked appropriately
+    (``rustdoc`` will create a link automatically).
+
+  - Any ``unsafe`` block must be preceded by a ``// SAFETY:`` comment
+    describing why the code inside is sound.
+
+    While sometimes the reason might look trivial and therefore unneeded,
+    writing these comments is not just a good way of documenting what has been
+    taken into account, but most importantly, it provides a way to know that
+    there are no *extra* implicit constraints.
+
+To learn more about how to write documentation for Rust and extra features,
+please take a look at the ``rustdoc`` book at:
+
+	https://doc.rust-lang.org/rustdoc/how-to-write-documentation.html
+
+
+Naming
+------
+
+Rust kernel code follows the usual Rust naming conventions:
+
+	https://rust-lang.github.io/api-guidelines/naming.html
+
+When existing C concepts (e.g. macros, functions, objects...) are wrapped into
+a Rust abstraction, a name as close as reasonably possible to the C side should
+be used in order to avoid confusion and to improve readability when switching
+back and forth between the C and Rust sides. For instance, macros such as
+``pr_info`` from C are named the same in the Rust side.
+
+Having said that, casing should be adjusted to follow the Rust naming
+conventions, and namespacing introduced by modules and types should not be
+repeated in the item names. For instance, when wrapping constants like:
+
+.. code-block:: c
+
+	#define GPIO_LINE_DIRECTION_IN	0
+	#define GPIO_LINE_DIRECTION_OUT	1
+
+The equivalent in Rust may look like (ignoring documentation):
+
+.. code-block:: rust
+
+	pub mod gpio {
+	    pub enum LineDirection {
+	        In = bindings::GPIO_LINE_DIRECTION_IN as _,
+	        Out = bindings::GPIO_LINE_DIRECTION_OUT as _,
+	    }
+	}
+
+That is, the equivalent of ``GPIO_LINE_DIRECTION_IN`` would be referred to as
+``gpio::LineDirection::In``. In particular, it should not be named
+``gpio::gpio_line_direction::GPIO_LINE_DIRECTION_IN``.
diff --git a/Documentation/rust/general-information.rst b/Documentation/rust/general-information.rst
new file mode 100644
index 000000000000..49029ee82e55
--- /dev/null
+++ b/Documentation/rust/general-information.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+General Information
+===================
+
+This document contains useful information to know when working with
+the Rust support in the kernel.
+
+
+Code documentation
+------------------
+
+Rust kernel code is documented using ``rustdoc``, its built-in documentation
+generator.
+
+The generated HTML docs include integrated search, linked items (e.g. types,
+functions, constants), source code, etc. They may be read at (TODO: link when
+in mainline and generated alongside the rest of the documentation):
+
+	http://kernel.org/
+
+The docs can also be easily generated and read locally. This is quite fast
+(same order as compiling the code itself) and no special tools or environment
+are needed. This has the added advantage that they will be tailored to
+the particular kernel configuration used. To generate them, use the ``rustdoc``
+target with the same invocation used for compilation, e.g.::
+
+	make LLVM=1 rustdoc
+
+To read the docs locally in your web browser, run e.g.::
+
+	xdg-open rust/doc/kernel/index.html
+
+To learn about how to write the documentation, please see coding-guidelines.rst.
+
+
+Extra lints
+-----------
+
+While ``rustc`` is a very helpful compiler, some extra lints and analyses are
+available via ``clippy``, a Rust linter. To enable it, pass ``CLIPPY=1`` to
+the same invocation used for compilation, e.g.::
+
+	make LLVM=1 CLIPPY=1
+
+Please note that Clippy may change code generation, thus it should not be
+enabled while building a production kernel.
+
+
+Abstractions vs. bindings
+-------------------------
+
+Abstractions are Rust code wrapping kernel functionality from the C side.
+
+In order to use functions and types from the C side, bindings are created.
+Bindings are the declarations for Rust of those functions and types from
+the C side.
+
+For instance, one may write a ``Mutex`` abstraction in Rust which wraps
+a ``struct mutex`` from the C side and calls its functions through the bindings.
+
+Abstractions are not available for all the kernel internal APIs and concepts,
+but it is intended that coverage is expanded as time goes on. "Leaf" modules
+(e.g. drivers) should not use the C bindings directly. Instead, subsystems
+should provide as-safe-as-possible abstractions as needed.
+
+
+Conditional compilation
+-----------------------
+
+Rust code has access to conditional compilation based on the kernel
+configuration:
+
+.. code-block:: rust
+
+	#[cfg(CONFIG_X)]       // Enabled               (`y` or `m`)
+	#[cfg(CONFIG_X="y")]   // Enabled as a built-in (`y`)
+	#[cfg(CONFIG_X="m")]   // Enabled as a module   (`m`)
+	#[cfg(not(CONFIG_X))]  // Disabled
diff --git a/Documentation/rust/index.rst b/Documentation/rust/index.rst
new file mode 100644
index 000000000000..4ae8c66b94fa
--- /dev/null
+++ b/Documentation/rust/index.rst
@@ -0,0 +1,22 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Rust
+====
+
+Documentation related to Rust within the kernel. To start using Rust
+in the kernel, please read the quick-start.rst guide.
+
+.. toctree::
+    :maxdepth: 1
+
+    quick-start
+    general-information
+    coding-guidelines
+    arch-support
+
+.. only::  subproject and html
+
+   Indices
+   =======
+
+   * :ref:`genindex`
diff --git a/Documentation/rust/quick-start.rst b/Documentation/rust/quick-start.rst
new file mode 100644
index 000000000000..13b7744b1e27
--- /dev/null
+++ b/Documentation/rust/quick-start.rst
@@ -0,0 +1,232 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Quick Start
+===========
+
+This document describes how to get started with kernel development in Rust.
+
+
+Requirements: Building
+----------------------
+
+This section explains how to fetch the tools needed for building.
+
+Some of these requirements might be available from Linux distributions
+under names like ``rustc``, ``rust-src``, ``rust-bindgen``, etc. However,
+at the time of writing, they are likely not to be recent enough unless
+the distribution tracks the latest releases.
+
+To easily check whether the requirements are met, the following target
+can be used::
+
+	make LLVM=1 rustavailable
+
+This triggers the same logic used by Kconfig to determine whether
+``RUST_IS_AVAILABLE`` should be enabled; but it also explains why not
+if that is the case.
+
+
+rustc
+*****
+
+A particular version of the Rust compiler is required. Newer versions may or
+may not work because, for the moment, the kernel depends on some unstable
+Rust features.
+
+If ``rustup`` is being used, enter the checked out source code directory
+and run::
+
+	rustup override set $(scripts/min-tool-version.sh rustc)
+
+Otherwise, fetch a standalone installer or install ``rustup`` from:
+
+	https://www.rust-lang.org
+
+
+Rust standard library source
+****************************
+
+The Rust standard library source is required because the build system will
+cross-compile ``core`` and ``alloc``.
+
+If ``rustup`` is being used, run::
+
+	rustup component add rust-src
+
+The components are installed per toolchain, thus upgrading the Rust compiler
+version later on requires re-adding the component.
+
+Otherwise, if a standalone installer is used, the Rust repository may be cloned
+into the installation folder of the toolchain::
+
+	git clone --recurse-submodules \
+		--branch $(scripts/min-tool-version.sh rustc) \
+		https://github.com/rust-lang/rust \
+		$(rustc --print sysroot)/lib/rustlib/src/rust
+
+In this case, upgrading the Rust compiler version later on requires manually
+updating this clone.
+
+
+libclang
+********
+
+``libclang`` (part of LLVM) is used by ``bindgen`` to understand the C code
+in the kernel, which means LLVM needs to be installed; like when the kernel
+is compiled with ``CC=clang`` or ``LLVM=1``.
+
+Linux distributions are likely to have a suitable one available, so it is
+best to check that first.
+
+There are also some binaries for several systems and architectures uploaded at:
+
+	https://releases.llvm.org/download.html
+
+Otherwise, building LLVM takes quite a while, but it is not a complex process:
+
+	https://llvm.org/docs/GettingStarted.html#getting-the-source-code-and-building-llvm
+
+Please see Documentation/kbuild/llvm.rst for more information and further ways
+to fetch pre-built releases and distribution packages.
+
+
+bindgen
+*******
+
+The bindings to the C side of the kernel are generated at build time using
+the ``bindgen`` tool. A particular version is required.
+
+Install it via (note that this will download and build the tool from source)::
+
+	cargo install --locked --version $(scripts/min-tool-version.sh bindgen) bindgen
+
+
+Requirements: Developing
+------------------------
+
+This section explains how to fetch the tools needed for developing. That is,
+they are not needed when just building the kernel.
+
+
+rustfmt
+*******
+
+The ``rustfmt`` tool is used to automatically format all the Rust kernel code,
+including the generated C bindings (for details, please see
+coding-guidelines.rst).
+
+If ``rustup`` is being used, its ``default`` profile already installs the tool,
+thus nothing needs to be done. If another profile is being used, the component
+can be installed manually::
+
+	rustup component add rustfmt
+
+The standalone installers also come with ``rustfmt``.
+
+
+clippy
+******
+
+``clippy`` is a Rust linter. Running it provides extra warnings for Rust code.
+It can be run by passing ``CLIPPY=1`` to ``make`` (for details, please see
+general-information.rst).
+
+If ``rustup`` is being used, its ``default`` profile already installs the tool,
+thus nothing needs to be done. If another profile is being used, the component
+can be installed manually::
+
+	rustup component add clippy
+
+The standalone installers also come with ``clippy``.
+
+
+cargo
+*****
+
+``cargo`` is the Rust native build system. It is currently required to run
+the tests since it is used to build a custom standard library that contains
+the facilities provided by the custom ``alloc`` in the kernel. The tests can
+be run using the ``rusttest`` Make target.
+
+If ``rustup`` is being used, all the profiles already install the tool,
+thus nothing needs to be done.
+
+The standalone installers also come with ``cargo``.
+
+
+rustdoc
+*******
+
+``rustdoc`` is the documentation tool for Rust. It generates pretty HTML
+documentation for Rust code (for details, please see
+general-information.rst).
+
+``rustdoc`` is also used to test the examples provided in documented Rust code
+(called doctests or documentation tests). The ``rusttest`` Make target uses
+this feature.
+
+If ``rustup`` is being used, all the profiles already install the tool,
+thus nothing needs to be done.
+
+The standalone installers also come with ``rustdoc``.
+
+
+rust-analyzer
+*************
+
+The `rust-analyzer <https://rust-analyzer.github.io/>`_ language server can
+be used with many editors to enable syntax highlighting, completion, go to
+definition, and other features.
+
+``rust-analyzer`` needs a configuration file, ``rust-project.json``, which
+can be generated by the ``rust-analyzer`` Make target.
+
+
+Configuration
+-------------
+
+``Rust support`` (``CONFIG_RUST``) needs to be enabled in the ``General setup``
+menu. The option is only shown if a suitable Rust toolchain is found (see
+above), as long as the other requirements are met. In turn, this will make
+visible the rest of options that depend on Rust.
+
+Afterwards, go to::
+
+	Kernel hacking
+	    -> Sample kernel code
+	        -> Rust samples
+
+And enable some sample modules either as built-in or as loadable.
+
+
+Building
+--------
+
+Building a kernel with a complete LLVM toolchain is the best supported setup
+at the moment. That is::
+
+	make LLVM=1
+
+For architectures that do not support a full LLVM toolchain, use::
+
+	make CC=clang
+
+Using GCC also works for some configurations, but it is very experimental at
+the moment.
+
+
+Hacking
+-------
+
+To dive deeper, take a look at the source code of the samples
+at ``samples/rust/``, the Rust support code under ``rust/`` and
+the ``Rust hacking`` menu under ``Kernel hacking``.
+
+If GDB/Binutils is used and Rust symbols are not getting demangled, the reason
+is the toolchain does not support Rust's new v0 mangling scheme yet.
+There are a few ways out:
+
+  - Install a newer release (GDB >= 10.2, Binutils >= 2.36).
+
+  - Some versions of GDB (e.g. vanilla GDB 10.1) are able to use
+    the pre-demangled names embedded in the debug info (``CONFIG_DEBUG_INFO``).
diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
index 8dff5906639b..a900ff66911a 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
@@ -109,6 +109,13 @@ All components are stored with the same number of bits per component.
       - Cb, Cr
       - No
       - 16x16 tiles
+    * - V4L2_PIX_FMT_P010
+      - 'P010'
+      - 10
+      - 4:2:0
+      - Cb, Cr
+      - Yes
+      - Linear
     * - V4L2_PIX_FMT_NV16
       - 'NV16'
       - 8
@@ -171,6 +178,7 @@ horizontally.
 .. _V4L2-PIX-FMT-NV21:
 .. _V4L2-PIX-FMT-NV12M:
 .. _V4L2-PIX-FMT-NV21M:
+.. _V4L2-PIX-FMT-P010:
 
 NV12, NV21, NV12M and NV21M
 ---------------------------
@@ -519,6 +527,52 @@ number of lines as the luma plane.
       - Cb\ :sub:`33`
       - Cr\ :sub:`33`
 
+.. _V4L2_PIX_FMT_P010:
+
+P010
+----
+
+Like NV12 with 10 bits per component, expanded to 16 bits.
+Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian order.
+
+.. flat-table:: Sample 4x4 P010 Image
+    :header-rows:  0
+    :stub-columns: 0
+
+    * - start + 0:
+      - Y'\ :sub:`00`
+      - Y'\ :sub:`01`
+      - Y'\ :sub:`02`
+      - Y'\ :sub:`03`
+    * - start + 8:
+      - Y'\ :sub:`10`
+      - Y'\ :sub:`11`
+      - Y'\ :sub:`12`
+      - Y'\ :sub:`13`
+    * - start + 16:
+      - Y'\ :sub:`20`
+      - Y'\ :sub:`21`
+      - Y'\ :sub:`22`
+      - Y'\ :sub:`23`
+    * - start + 24:
+      - Y'\ :sub:`30`
+      - Y'\ :sub:`31`
+      - Y'\ :sub:`32`
+      - Y'\ :sub:`33`
+    * - start + 32:
+      - Cb\ :sub:`00`
+      - Cr\ :sub:`00`
+      - Cb\ :sub:`01`
+      - Cr\ :sub:`01`
+    * - start + 40:
+      - Cb\ :sub:`10`
+      - Cr\ :sub:`10`
+      - Cb\ :sub:`11`
+      - Cr\ :sub:`11`
+
+.. raw:: latex
+
+    \endgroup
 
 Fully Planar YUV Formats
 ========================
diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst
index 0cbc045d5df6..d21d532eee15 100644
--- a/Documentation/userspace-api/media/v4l/subdev-formats.rst
+++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst
@@ -1492,6 +1492,80 @@ The following tables list existing packed RGB formats.
       - b\ :sub:`2`
       - b\ :sub:`1`
       - b\ :sub:`0`
+    * .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO:
+
+      - MEDIA_BUS_FMT_RGB666_1X30-CPADLO
+      - 0x101e
+      -
+      -
+      -
+      - r\ :sub:`5`
+      - r\ :sub:`4`
+      - r\ :sub:`3`
+      - r\ :sub:`2`
+      - r\ :sub:`1`
+      - r\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - g\ :sub:`5`
+      - g\ :sub:`4`
+      - g\ :sub:`3`
+      - g\ :sub:`2`
+      - g\ :sub:`1`
+      - g\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - b\ :sub:`5`
+      - b\ :sub:`4`
+      - b\ :sub:`3`
+      - b\ :sub:`2`
+      - b\ :sub:`1`
+      - b\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+    * .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO:
+
+      - MEDIA_BUS_FMT_RGB888_1X30-CPADLO
+      - 0x101f
+      -
+      -
+      -
+      - r\ :sub:`7`
+      - r\ :sub:`6`
+      - r\ :sub:`5`
+      - r\ :sub:`4`
+      - r\ :sub:`3`
+      - r\ :sub:`2`
+      - r\ :sub:`1`
+      - r\ :sub:`0`
+      - 0
+      - 0
+      - g\ :sub:`7`
+      - g\ :sub:`6`
+      - g\ :sub:`5`
+      - g\ :sub:`4`
+      - g\ :sub:`3`
+      - g\ :sub:`2`
+      - g\ :sub:`1`
+      - g\ :sub:`0`
+      - 0
+      - 0
+      - b\ :sub:`7`
+      - b\ :sub:`6`
+      - b\ :sub:`5`
+      - b\ :sub:`4`
+      - b\ :sub:`3`
+      - b\ :sub:`2`
+      - b\ :sub:`1`
+      - b\ :sub:`0`
+      - 0
+      - 0
     * .. _MEDIA-BUS-FMT-ARGB888-1X32:
 
       - MEDIA_BUS_FMT_ARGB888_1X32
@@ -1669,6 +1743,88 @@ The following table list existing packed 36bit wide RGB formats.
       - 2
       - 1
       - 0
+    * .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO:
+
+      - MEDIA_BUS_FMT_RGB666_1X36_CPADLO
+      - 0x1020
+      -
+      - r\ :sub:`5`
+      - r\ :sub:`4`
+      - r\ :sub:`3`
+      - r\ :sub:`2`
+      - r\ :sub:`1`
+      - r\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+      - g\ :sub:`5`
+      - g\ :sub:`4`
+      - g\ :sub:`3`
+      - g\ :sub:`2`
+      - g\ :sub:`1`
+      - g\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+      - b\ :sub:`5`
+      - b\ :sub:`4`
+      - b\ :sub:`3`
+      - b\ :sub:`2`
+      - b\ :sub:`1`
+      - b\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+      - 0
+    * .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO:
+
+      - MEDIA_BUS_FMT_RGB888_1X36_CPADLO
+      - 0x1021
+      -
+      - r\ :sub:`7`
+      - r\ :sub:`6`
+      - r\ :sub:`5`
+      - r\ :sub:`4`
+      - r\ :sub:`3`
+      - r\ :sub:`2`
+      - r\ :sub:`1`
+      - r\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - g\ :sub:`7`
+      - g\ :sub:`6`
+      - g\ :sub:`5`
+      - g\ :sub:`4`
+      - g\ :sub:`3`
+      - g\ :sub:`2`
+      - g\ :sub:`1`
+      - g\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
+      - b\ :sub:`7`
+      - b\ :sub:`6`
+      - b\ :sub:`5`
+      - b\ :sub:`4`
+      - b\ :sub:`3`
+      - b\ :sub:`2`
+      - b\ :sub:`1`
+      - b\ :sub:`0`
+      - 0
+      - 0
+      - 0
+      - 0
     * .. _MEDIA-BUS-FMT-RGB121212-1X36:
 
       - MEDIA_BUS_FMT_RGB121212_1X36
diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
index 11e00a46c610..84c486ce6279 100644
--- a/Documentation/virt/kvm/api.rst
+++ b/Documentation/virt/kvm/api.rst
@@ -1150,6 +1150,10 @@ The following bits are defined in the flags field:
   fields contain a valid state. This bit will be set whenever
   KVM_CAP_EXCEPTION_PAYLOAD is enabled.
 
+- KVM_VCPUEVENT_VALID_TRIPLE_FAULT may be set to signal that the
+  triple_fault_pending field contains a valid state. This bit will
+  be set whenever KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled.
+
 ARM64:
 ^^^^^^
 
@@ -1245,6 +1249,10 @@ can be set in the flags field to signal that the
 exception_has_payload, exception_payload, and exception.pending fields
 contain a valid state and shall be written into the VCPU.
 
+If KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled, KVM_VCPUEVENT_VALID_TRIPLE_FAULT
+can be set in flags field to signal that the triple_fault field contains
+a valid state and shall be written into the VCPU.
+
 ARM64:
 ^^^^^^
 
@@ -2998,7 +3006,9 @@ KVM_CREATE_PIT2. The state is returned in the following structure::
 Valid flags are::
 
   /* disable PIT in HPET legacy mode */
-  #define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
+  #define KVM_PIT_FLAGS_HPET_LEGACY     0x00000001
+  /* speaker port data bit enabled */
+  #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002
 
 This IOCTL replaces the obsolete KVM_GET_PIT.
 
@@ -5127,7 +5137,15 @@ into ESA mode. This reset is a superset of the initial reset.
 	__u32 reserved[3];
   };
 
-cmd values:
+**Ultravisor return codes**
+The Ultravisor return (reason) codes are provided by the kernel if a
+Ultravisor call has been executed to achieve the results expected by
+the command. Therefore they are independent of the IOCTL return
+code. If KVM changes `rc`, its value will always be greater than 0
+hence setting it to 0 before issuing a PV command is advised to be
+able to detect a change of `rc`.
+
+**cmd values:**
 
 KVM_PV_ENABLE
   Allocate memory and register the VM with the Ultravisor, thereby
@@ -5143,7 +5161,6 @@ KVM_PV_ENABLE
   =====      =============================
 
 KVM_PV_DISABLE
-
   Deregister the VM from the Ultravisor and reclaim the memory that
   had been donated to the Ultravisor, making it usable by the kernel
   again.  All registered VCPUs are converted back to non-protected
@@ -5160,6 +5177,117 @@ KVM_PV_VM_VERIFY
   Verify the integrity of the unpacked image. Only if this succeeds,
   KVM is allowed to start protected VCPUs.
 
+KVM_PV_INFO
+  :Capability: KVM_CAP_S390_PROTECTED_DUMP
+
+  Presents an API that provides Ultravisor related data to userspace
+  via subcommands. len_max is the size of the user space buffer,
+  len_written is KVM's indication of how much bytes of that buffer
+  were actually written to. len_written can be used to determine the
+  valid fields if more response fields are added in the future.
+
+  ::
+
+     enum pv_cmd_info_id {
+	KVM_PV_INFO_VM,
+	KVM_PV_INFO_DUMP,
+     };
+
+     struct kvm_s390_pv_info_header {
+	__u32 id;
+	__u32 len_max;
+	__u32 len_written;
+	__u32 reserved;
+     };
+
+     struct kvm_s390_pv_info {
+	struct kvm_s390_pv_info_header header;
+	struct kvm_s390_pv_info_dump dump;
+	struct kvm_s390_pv_info_vm vm;
+     };
+
+**subcommands:**
+
+  KVM_PV_INFO_VM
+    This subcommand provides basic Ultravisor information for PV
+    hosts. These values are likely also exported as files in the sysfs
+    firmware UV query interface but they are more easily available to
+    programs in this API.
+
+    The installed calls and feature_indication members provide the
+    installed UV calls and the UV's other feature indications.
+
+    The max_* members provide information about the maximum number of PV
+    vcpus, PV guests and PV guest memory size.
+
+    ::
+
+      struct kvm_s390_pv_info_vm {
+	__u64 inst_calls_list[4];
+	__u64 max_cpus;
+	__u64 max_guests;
+	__u64 max_guest_addr;
+	__u64 feature_indication;
+      };
+
+
+  KVM_PV_INFO_DUMP
+    This subcommand provides information related to dumping PV guests.
+
+    ::
+
+      struct kvm_s390_pv_info_dump {
+	__u64 dump_cpu_buffer_len;
+	__u64 dump_config_mem_buffer_per_1m;
+	__u64 dump_config_finalize_len;
+      };
+
+KVM_PV_DUMP
+  :Capability: KVM_CAP_S390_PROTECTED_DUMP
+
+  Presents an API that provides calls which facilitate dumping a
+  protected VM.
+
+  ::
+
+    struct kvm_s390_pv_dmp {
+      __u64 subcmd;
+      __u64 buff_addr;
+      __u64 buff_len;
+      __u64 gaddr;		/* For dump storage state */
+    };
+
+  **subcommands:**
+
+  KVM_PV_DUMP_INIT
+    Initializes the dump process of a protected VM. If this call does
+    not succeed all other subcommands will fail with -EINVAL. This
+    subcommand will return -EINVAL if a dump process has not yet been
+    completed.
+
+    Not all PV vms can be dumped, the owner needs to set `dump
+    allowed` PCF bit 34 in the SE header to allow dumping.
+
+  KVM_PV_DUMP_CONFIG_STOR_STATE
+     Stores `buff_len` bytes of tweak component values starting with
+     the 1MB block specified by the absolute guest address
+     (`gaddr`). `buff_len` needs to be `conf_dump_storage_state_len`
+     aligned and at least >= the `conf_dump_storage_state_len` value
+     provided by the dump uv_info data. buff_user might be written to
+     even if an error rc is returned. For instance if we encounter a
+     fault after writing the first page of data.
+
+  KVM_PV_DUMP_COMPLETE
+    If the subcommand succeeds it completes the dump process and lets
+    KVM_PV_DUMP_INIT be called again.
+
+    On success `conf_dump_finalize_len` bytes of completion data will be
+    stored to the `buff_addr`. The completion data contains a key
+    derivation seed, IV, tweak nonce and encryption keys as well as an
+    authentication tag all of which are needed to decrypt the dump at a
+    later time.
+
+
 4.126 KVM_X86_SET_MSR_FILTER
 ----------------------------
 
@@ -5802,6 +5930,32 @@ of CPUID leaf 0xD on the host.
 
 This ioctl injects an event channel interrupt directly to the guest vCPU.
 
+4.136 KVM_S390_PV_CPU_COMMAND
+-----------------------------
+
+:Capability: KVM_CAP_S390_PROTECTED_DUMP
+:Architectures: s390
+:Type: vcpu ioctl
+:Parameters: none
+:Returns: 0 on success, < 0 on error
+
+This ioctl closely mirrors `KVM_S390_PV_COMMAND` but handles requests
+for vcpus. It re-uses the kvm_s390_pv_dmp struct and hence also shares
+the command ids.
+
+**command:**
+
+KVM_PV_DUMP
+  Presents an API that provides calls which facilitate dumping a vcpu
+  of a protected VM.
+
+**subcommand:**
+
+KVM_PV_DUMP_CPU
+  Provides encrypted dump data like register values.
+  The length of the returned data is provided by uv_info.guest_cpu_stor_len.
+
+
 5. The kvm_run structure
 ========================
 
@@ -6405,6 +6559,26 @@ array field represents return values. The userspace should update the return
 values of SBI call before resuming the VCPU. For more details on RISC-V SBI
 spec refer, https://github.com/riscv/riscv-sbi-doc.
 
+::
+
+    /* KVM_EXIT_NOTIFY */
+    struct {
+  #define KVM_NOTIFY_CONTEXT_INVALID	(1 << 0)
+      __u32 flags;
+    } notify;
+
+Used on x86 systems. When the VM capability KVM_CAP_X86_NOTIFY_VMEXIT is
+enabled, a VM exit generated if no event window occurs in VM non-root mode
+for a specified amount of time. Once KVM_X86_NOTIFY_VMEXIT_USER is set when
+enabling the cap, it would exit to userspace with the exit reason
+KVM_EXIT_NOTIFY for further handling. The "flags" field contains more
+detailed info.
+
+The valid value for 'flags' is:
+
+  - KVM_NOTIFY_CONTEXT_INVALID -- the VM context is corrupted and not valid
+    in VMCS. It would run into unknown result if resume the target VM.
+
 ::
 
 		/* Fix the size of the union. */
@@ -7350,6 +7524,56 @@ The valid bits in cap.args[0] are:
                                     generate a #UD within the guest.
 =================================== ============================================
 
+7.32 KVM_CAP_MAX_VCPU_ID
+------------------------
+
+:Architectures: x86
+:Target: VM
+:Parameters: args[0] - maximum APIC ID value set for current VM
+:Returns: 0 on success, -EINVAL if args[0] is beyond KVM_MAX_VCPU_IDS
+          supported in KVM or if it has been set.
+
+This capability allows userspace to specify maximum possible APIC ID
+assigned for current VM session prior to the creation of vCPUs, saving
+memory for data structures indexed by the APIC ID.  Userspace is able
+to calculate the limit to APIC ID values from designated
+CPU topology.
+
+The value can be changed only until KVM_ENABLE_CAP is set to a nonzero
+value or until a vCPU is created.  Upon creation of the first vCPU,
+if the value was set to zero or KVM_ENABLE_CAP was not invoked, KVM
+uses the return value of KVM_CHECK_EXTENSION(KVM_CAP_MAX_VCPU_ID) as
+the maximum APIC ID.
+
+7.33 KVM_CAP_X86_NOTIFY_VMEXIT
+------------------------------
+
+:Architectures: x86
+:Target: VM
+:Parameters: args[0] is the value of notify window as well as some flags
+:Returns: 0 on success, -EINVAL if args[0] contains invalid flags or notify
+          VM exit is unsupported.
+
+Bits 63:32 of args[0] are used for notify window.
+Bits 31:0 of args[0] are for some flags. Valid bits are::
+
+  #define KVM_X86_NOTIFY_VMEXIT_ENABLED    (1 << 0)
+  #define KVM_X86_NOTIFY_VMEXIT_USER       (1 << 1)
+
+This capability allows userspace to configure the notify VM exit on/off
+in per-VM scope during VM creation. Notify VM exit is disabled by default.
+When userspace sets KVM_X86_NOTIFY_VMEXIT_ENABLED bit in args[0], VMM will
+enable this feature with the notify window provided, which will generate
+a VM exit if no event window occurs in VM non-root mode for a specified of
+time (notify window).
+
+If KVM_X86_NOTIFY_VMEXIT_USER is set in args[0], upon notify VM exits happen,
+KVM would exit to userspace for handling.
+
+This capability is aimed to mitigate the threat that malicious VMs can
+cause CPU stuck (due to event windows don't open up) and make the CPU
+unavailable to host or other VMs.
+
 8. Other capabilities.
 ======================
 
@@ -7956,6 +8180,20 @@ should adjust CPUID leaf 0xA to reflect that the PMU is disabled.
 When enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of
 type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request.
 
+8.37 KVM_CAP_S390_PROTECTED_DUMP
+--------------------------------
+
+:Capability: KVM_CAP_S390_PROTECTED_DUMP
+:Architectures: s390
+:Type: vm
+
+This capability indicates that KVM and the Ultravisor support dumping
+PV guests. The `KVM_PV_DUMP` command is available for the
+`KVM_S390_PV_COMMAND` ioctl and the `KVM_PV_INFO` command provides
+dump related UV data. Also the vcpu ioctl `KVM_S390_PV_CPU_COMMAND` is
+available and supports the `KVM_PV_DUMP_CPU` subcommand.
+
+
 9. Known KVM API problems
 =========================
 
diff --git a/Documentation/virt/kvm/s390/index.rst b/Documentation/virt/kvm/s390/index.rst
index 605f488f0cc5..44ec9ab14b59 100644
--- a/Documentation/virt/kvm/s390/index.rst
+++ b/Documentation/virt/kvm/s390/index.rst
@@ -10,3 +10,4 @@ KVM for s390 systems
    s390-diag
    s390-pv
    s390-pv-boot
+   s390-pv-dump
diff --git a/Documentation/virt/kvm/s390/s390-pv-dump.rst b/Documentation/virt/kvm/s390/s390-pv-dump.rst
new file mode 100644
index 000000000000..e542f06048f3
--- /dev/null
+++ b/Documentation/virt/kvm/s390/s390-pv-dump.rst
@@ -0,0 +1,64 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===========================================
+s390 (IBM Z) Protected Virtualization dumps
+===========================================
+
+Summary
+-------
+
+Dumping a VM is an essential tool for debugging problems inside
+it. This is especially true when a protected VM runs into trouble as
+there's no way to access its memory and registers from the outside
+while it's running.
+
+However when dumping a protected VM we need to maintain its
+confidentiality until the dump is in the hands of the VM owner who
+should be the only one capable of analysing it.
+
+The confidentiality of the VM dump is ensured by the Ultravisor who
+provides an interface to KVM over which encrypted CPU and memory data
+can be requested. The encryption is based on the Customer
+Communication Key which is the key that's used to encrypt VM data in a
+way that the customer is able to decrypt.
+
+
+Dump process
+------------
+
+A dump is done in 3 steps:
+
+**Initiation**
+
+This step initializes the dump process, generates cryptographic seeds
+and extracts dump keys with which the VM dump data will be encrypted.
+
+**Data gathering**
+
+Currently there are two types of data that can be gathered from a VM:
+the memory and the vcpu state.
+
+The vcpu state contains all the important registers, general, floating
+point, vector, control and tod/timers of a vcpu. The vcpu dump can
+contain incomplete data if a vcpu is dumped while an instruction is
+emulated with help of the hypervisor. This is indicated by a flag bit
+in the dump data. For the same reason it is very important to not only
+write out the encrypted vcpu state, but also the unencrypted state
+from the hypervisor.
+
+The memory state is further divided into the encrypted memory and its
+metadata comprised of the encryption tweaks and status flags. The
+encrypted memory can simply be read once it has been exported. The
+time of the export does not matter as no re-encryption is
+needed. Memory that has been swapped out and hence was exported can be
+read from the swap and written to the dump target without need for any
+special actions.
+
+The tweaks / status flags for the exported pages need to be requested
+from the Ultravisor.
+
+**Finalization**
+
+The finalization step will provide the data needed to be able to
+decrypt the vcpu and memory data and end the dump process. When this
+step completes successfully a new dump initiation can be started.
diff --git a/Documentation/vm/balance.rst b/Documentation/vm/balance.rst
index 6a1fadf3e173..e38e9d83c1c7 100644
--- a/Documentation/vm/balance.rst
+++ b/Documentation/vm/balance.rst
@@ -6,7 +6,7 @@ Memory Balancing
 
 Started Jan 2000 by Kanoj Sarcar <kanoj@sgi.com>
 
-Memory balancing is needed for !__GFP_ATOMIC and !__GFP_KSWAPD_RECLAIM as
+Memory balancing is needed for !__GFP_HIGH and !__GFP_KSWAPD_RECLAIM as
 well as for non __GFP_IO allocations.
 
 The first reason why a caller may avoid reclaim is that the caller can not
diff --git a/Documentation/vm/hwpoison.rst b/Documentation/vm/hwpoison.rst
index c742de1769d1..b9d5253c1305 100644
--- a/Documentation/vm/hwpoison.rst
+++ b/Documentation/vm/hwpoison.rst
@@ -120,7 +120,8 @@ Testing
   unpoison-pfn
 	Software-unpoison page at PFN echoed into this file. This way
 	a page can be reused again.  This only works for Linux
-	injected failures, not for real memory failures.
+	injected failures, not for real memory failures. Once any hardware
+	memory failure happens, this feature is disabled.
 
   Note these injection interfaces are not stable and might change between
   kernel versions
diff --git a/Documentation/vm/page_migration.rst b/Documentation/vm/page_migration.rst
index 8c5cb8147e55..11493bad7112 100644
--- a/Documentation/vm/page_migration.rst
+++ b/Documentation/vm/page_migration.rst
@@ -152,110 +152,15 @@ Steps:
 Non-LRU page migration
 ======================
 
-Although migration originally aimed for reducing the latency of memory accesses
-for NUMA, compaction also uses migration to create high-order pages.
+Although migration originally aimed for reducing the latency of memory
+accesses for NUMA, compaction also uses migration to create high-order
+pages.  For compaction purposes, it is also useful to be able to move
+non-LRU pages, such as zsmalloc and virtio-balloon pages.
 
-Current problem of the implementation is that it is designed to migrate only
-*LRU* pages. However, there are potential non-LRU pages which can be migrated
-in drivers, for example, zsmalloc, virtio-balloon pages.
-
-For virtio-balloon pages, some parts of migration code path have been hooked
-up and added virtio-balloon specific functions to intercept migration logics.
-It's too specific to a driver so other drivers who want to make their pages
-movable would have to add their own specific hooks in the migration path.
-
-To overcome the problem, VM supports non-LRU page migration which provides
-generic functions for non-LRU movable pages without driver specific hooks
-in the migration path.
-
-If a driver wants to make its pages movable, it should define three functions
-which are function pointers of struct address_space_operations.
-
-1. ``bool (*isolate_page) (struct page *page, isolate_mode_t mode);``
-
-   What VM expects from isolate_page() function of driver is to return *true*
-   if driver isolates the page successfully. On returning true, VM marks the page
-   as PG_isolated so concurrent isolation in several CPUs skip the page
-   for isolation. If a driver cannot isolate the page, it should return *false*.
-
-   Once page is successfully isolated, VM uses page.lru fields so driver
-   shouldn't expect to preserve values in those fields.
-
-2. ``int (*migratepage) (struct address_space *mapping,``
-|	``struct page *newpage, struct page *oldpage, enum migrate_mode);``
-
-   After isolation, VM calls migratepage() of driver with the isolated page.
-   The function of migratepage() is to move the contents of the old page to the
-   new page
-   and set up fields of struct page newpage. Keep in mind that you should
-   indicate to the VM the oldpage is no longer movable via __ClearPageMovable()
-   under page_lock if you migrated the oldpage successfully and returned
-   MIGRATEPAGE_SUCCESS. If driver cannot migrate the page at the moment, driver
-   can return -EAGAIN. On -EAGAIN, VM will retry page migration in a short time
-   because VM interprets -EAGAIN as "temporary migration failure". On returning
-   any error except -EAGAIN, VM will give up the page migration without
-   retrying.
-
-   Driver shouldn't touch the page.lru field while in the migratepage() function.
-
-3. ``void (*putback_page)(struct page *);``
-
-   If migration fails on the isolated page, VM should return the isolated page
-   to the driver so VM calls the driver's putback_page() with the isolated page.
-   In this function, the driver should put the isolated page back into its own data
-   structure.
-
-Non-LRU movable page flags
-
-   There are two page flags for supporting non-LRU movable page.
-
-   * PG_movable
-
-     Driver should use the function below to make page movable under page_lock::
-
-	void __SetPageMovable(struct page *page, struct address_space *mapping)
-
-     It needs argument of address_space for registering migration
-     family functions which will be called by VM. Exactly speaking,
-     PG_movable is not a real flag of struct page. Rather, VM
-     reuses the page->mapping's lower bits to represent it::
-
-	#define PAGE_MAPPING_MOVABLE 0x2
-	page->mapping = page->mapping | PAGE_MAPPING_MOVABLE;
-
-     so driver shouldn't access page->mapping directly. Instead, driver should
-     use page_mapping() which masks off the low two bits of page->mapping under
-     page lock so it can get the right struct address_space.
-
-     For testing of non-LRU movable pages, VM supports __PageMovable() function.
-     However, it doesn't guarantee to identify non-LRU movable pages because
-     the page->mapping field is unified with other variables in struct page.
-     If the driver releases the page after isolation by VM, page->mapping
-     doesn't have a stable value although it has PAGE_MAPPING_MOVABLE set
-     (look at __ClearPageMovable). But __PageMovable() is cheap to call whether
-     page is LRU or non-LRU movable once the page has been isolated because LRU
-     pages can never have PAGE_MAPPING_MOVABLE set in page->mapping. It is also
-     good for just peeking to test non-LRU movable pages before more expensive
-     checking with lock_page() in pfn scanning to select a victim.
-
-     For guaranteeing non-LRU movable page, VM provides PageMovable() function.
-     Unlike __PageMovable(), PageMovable() validates page->mapping and
-     mapping->a_ops->isolate_page under lock_page(). The lock_page() prevents
-     sudden destroying of page->mapping.
-
-     Drivers using __SetPageMovable() should clear the flag via
-     __ClearMovablePage() under page_lock() before the releasing the page.
-
-   * PG_isolated
-
-     To prevent concurrent isolation among several CPUs, VM marks isolated page
-     as PG_isolated under lock_page(). So if a CPU encounters PG_isolated
-     non-LRU movable page, it can skip it. Driver doesn't need to manipulate the
-     flag because VM will set/clear it automatically. Keep in mind that if the
-     driver sees a PG_isolated page, it means the page has been isolated by the
-     VM so it shouldn't touch the page.lru field.
-     The PG_isolated flag is aliased with the PG_reclaim flag so drivers
-     shouldn't use PG_isolated for its own purposes.
+If a driver wants to make its pages movable, it should define a struct
+movable_operations.  It then needs to call __SetPageMovable() on each
+page that it may be able to move.  This uses the ``page->mapping`` field,
+so this field is not available for the driver to use for other purposes.
 
 Monitoring Migration
 =====================
@@ -286,3 +191,5 @@ THP_MIGRATION_FAIL and PGMIGRATE_FAIL to increase.
 
 Christoph Lameter, May 8, 2006.
 Minchan Kim, Mar 28, 2016.
+
+.. kernel-doc:: include/linux/migrate.h
diff --git a/Documentation/x86/x86_64/boot-options.rst b/Documentation/x86/x86_64/boot-options.rst
index 03ec9cf01181..cbd14124a667 100644
--- a/Documentation/x86/x86_64/boot-options.rst
+++ b/Documentation/x86/x86_64/boot-options.rst
@@ -287,11 +287,13 @@ iommu options only relevant to the AMD GART hardware IOMMU:
 iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
 implementation:
 
-    swiotlb=<pages>[,force]
-      <pages>
-        Prereserve that many 128K pages for the software IO bounce buffering.
+    swiotlb=<slots>[,force,noforce]
+      <slots>
+        Prereserve that many 2K slots for the software IO bounce buffering.
       force
         Force all IO through the software TLB.
+      noforce
+        Do not initialize the software TLB.
 
 
 Miscellaneous
diff --git a/MAINTAINERS b/MAINTAINERS
index 3cf9842d9233..cd7a70782aaa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -171,7 +171,6 @@ F:	drivers/scsi/53c700*
 
 6LOWPAN GENERIC (BTLE/IEEE 802.15.4)
 M:	Alexander Aring <alex.aring@gmail.com>
-M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
 L:	linux-bluetooth@vger.kernel.org
 L:	linux-wpan@vger.kernel.org
 S:	Maintained
@@ -733,6 +732,14 @@ S:	Maintained
 F:	Documentation/i2c/busses/i2c-ali1563.rst
 F:	drivers/i2c/busses/i2c-ali1563.c
 
+ALIBABA ELASTIC RDMA DRIVER
+M:	Cheng Xu <chengyou@linux.alibaba.com>
+M:	Kai Shen <kaishen@linux.alibaba.com>
+L:	linux-rdma@vger.kernel.org
+S:	Supported
+F:	drivers/infiniband/hw/erdma
+F:	include/uapi/rdma/erdma-abi.h
+
 ALIENWARE WMI DRIVER
 L:	Dell.Client.Kernel@dell.com
 S:	Maintained
@@ -1370,10 +1377,13 @@ F:	include/uapi/linux/apm_bios.h
 
 APPARMOR SECURITY MODULE
 M:	John Johansen <john.johansen@canonical.com>
-L:	apparmor@lists.ubuntu.com (subscribers-only, general discussion)
+L:	apparmor@lists.ubuntu.com (moderated for non-subscribers)
 S:	Supported
-W:	wiki.apparmor.net
+W:	apparmor.net
+B:	https://gitlab.com/apparmor/apparmor-kernel
+C:	irc://irc.oftc.net/apparmor
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor
+T:	https://gitlab.com/apparmor/apparmor-kernel.git
 F:	Documentation/admin-guide/LSM/apparmor.rst
 F:	security/apparmor/
 
@@ -1520,7 +1530,7 @@ F:	Documentation/devicetree/bindings/arm/arm,versatile.yaml
 F:	Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
 F:	Documentation/devicetree/bindings/auxdisplay/arm,versatile-lcd.yaml
 F:	Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml
-F:	Documentation/devicetree/bindings/i2c/i2c-versatile.txt
+F:	Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
 F:	Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
 F:	arch/arm/boot/dts/arm-realview-*
@@ -1832,6 +1842,7 @@ T:	git https://github.com/AsahiLinux/linux.git
 F:	Documentation/devicetree/bindings/arm/apple.yaml
 F:	Documentation/devicetree/bindings/arm/apple/*
 F:	Documentation/devicetree/bindings/clock/apple,nco.yaml
+F:	Documentation/devicetree/bindings/dma/apple,admac.yaml
 F:	Documentation/devicetree/bindings/i2c/apple,i2c.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/apple,*
 F:	Documentation/devicetree/bindings/iommu/apple,dart.yaml
@@ -1845,6 +1856,7 @@ F:	Documentation/devicetree/bindings/power/apple*
 F:	Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
 F:	arch/arm64/boot/dts/apple/
 F:	drivers/clk/clk-apple-nco.c
+F:	drivers/dma/apple-admac.c
 F:	drivers/i2c/busses/i2c-pasemi-core.c
 F:	drivers/i2c/busses/i2c-pasemi-platform.c
 F:	drivers/iommu/apple-dart.c
@@ -1893,6 +1905,7 @@ L:	linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
 S:	Supported
 Q:	https://patchwork.ozlabs.org/project/linux-aspeed/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git
+F:	Documentation/devicetree/bindings/arm/aspeed/
 F:	arch/arm/boot/dts/aspeed-*
 F:	arch/arm/mach-aspeed/
 N:	aspeed
@@ -2416,7 +2429,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
 F:	Documentation/devicetree/bindings/arm/ste-*
 F:	Documentation/devicetree/bindings/arm/ux500.yaml
 F:	Documentation/devicetree/bindings/arm/ux500/
-F:	Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
+F:	Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml
 F:	arch/arm/boot/dts/ste-*
 F:	arch/arm/mach-nomadik/
 F:	arch/arm/mach-ux500/
@@ -2467,6 +2480,7 @@ ARM/NXP S32G ARCHITECTURE
 M:	Chester Lin <clin@suse.com>
 R:	Andreas Färber <afaerber@suse.de>
 R:	Matthias Brugger <mbrugger@suse.com>
+R:	NXP S32 Linux Team <s32@nxp.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm64/boot/dts/freescale/s32g*.dts*
@@ -2587,7 +2601,7 @@ L:	linux-unisoc@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/rda.yaml
 F:	Documentation/devicetree/bindings/gpio/gpio-rda.yaml
-F:	Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
+F:	Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml
 F:	Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml
 F:	Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml
 F:	arch/arm/boot/dts/rda8810pl-*
@@ -3136,6 +3150,13 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/media/aspeed-video.txt
 F:	drivers/media/platform/aspeed/
 
+ASPEED USB UDC DRIVER
+M:	Neal Liu <neal_liu@aspeedtech.com>
+L:	linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
+F:	drivers/usb/gadget/udc/aspeed_udc.c
+
 ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
 M:	Corentin Chary <corentin.chary@gmail.com>
 L:	acpi4asus-user@lists.sourceforge.net
@@ -3662,7 +3683,7 @@ BPF JIT for ARM
 M:	Shubham Bansal <illusionist.neo@gmail.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/arm/net/
 
 BPF JIT for ARM64
@@ -3686,14 +3707,15 @@ BPF JIT for NFP NICs
 M:	Jakub Kicinski <kuba@kernel.org>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Supported
+S:	Odd Fixes
 F:	drivers/net/ethernet/netronome/nfp/bpf/
 
 BPF JIT for POWERPC (32-BIT AND 64-BIT)
 M:	Naveen N. Rao <naveen.n.rao@linux.ibm.com>
+M:	Michael Ellerman <mpe@ellerman.id.au>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Supported
 F:	arch/powerpc/net/
 
 BPF JIT for RISC-V (32-bit)
@@ -3719,7 +3741,7 @@ M:	Heiko Carstens <hca@linux.ibm.com>
 M:	Vasily Gorbik <gor@linux.ibm.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Supported
 F:	arch/s390/net/
 X:	arch/s390/net/pnet.c
 
@@ -3727,14 +3749,14 @@ BPF JIT for SPARC (32-BIT AND 64-BIT)
 M:	David S. Miller <davem@davemloft.net>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/sparc/net/
 
 BPF JIT for X86 32-BIT
 M:	Wang YanQing <udknight@gmail.com>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
-S:	Maintained
+S:	Odd Fixes
 F:	arch/x86/net/bpf_jit_comp32.c
 
 BPF JIT for X86 64-BIT
@@ -3757,6 +3779,19 @@ F:	include/linux/bpf_lsm.h
 F:	kernel/bpf/bpf_lsm.c
 F:	security/bpf/
 
+BPF L7 FRAMEWORK
+M:	John Fastabend <john.fastabend@gmail.com>
+M:	Jakub Sitnicki <jakub@cloudflare.com>
+L:	netdev@vger.kernel.org
+L:	bpf@vger.kernel.org
+S:	Maintained
+F:	include/linux/skmsg.h
+F:	net/core/skmsg.c
+F:	net/core/sock_map.c
+F:	net/ipv4/tcp_bpf.c
+F:	net/ipv4/udp_bpf.c
+F:	net/unix/unix_bpf.c
+
 BPFTOOL
 M:	Quentin Monnet <quentin@isovalent.com>
 L:	bpf@vger.kernel.org
@@ -3790,18 +3825,28 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 T:	git git://github.com/broadcom/stblinux.git
 F:	Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml
-F:	arch/arm/boot/dts/bcm47622.dtsi
-F:	arch/arm/boot/dts/bcm947622.dts
+F:	arch/arm64/boot/dts/broadcom/bcmbca/*
 N:	bcmbca
 N:	bcm[9]?47622
+N:	bcm[9]?4912
+N:	bcm[9]?63146
+N:	bcm[9]?63148
+N:	bcm[9]?63158
+N:	bcm[9]?63178
+N:	bcm[9]?6756
+N:	bcm[9]?6846
+N:	bcm[9]?6855
+N:	bcm[9]?6856
+N:	bcm[9]?6858
+N:	bcm[9]?6878
 
 BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
-M:	Nicolas Saenz Julienne <nsaenz@kernel.org>
+M:	Florian Fainelli <f.fainelli@gmail.com>
 R:	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
 L:	linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
+T:	git git://github.com/broadcom/stblinux.git
 F:	Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
 F:	drivers/pci/controller/pcie-brcmstb.c
 F:	drivers/staging/vc04_services
@@ -4959,6 +5004,7 @@ Q:	http://patchwork.kernel.org/project/linux-clk/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
 F:	Documentation/devicetree/bindings/clock/
 F:	drivers/clk/
+F:	include/dt-bindings/clock/
 F:	include/linux/clk-pr*
 F:	include/linux/clk/
 F:	include/linux/of_clk.h
@@ -5039,6 +5085,7 @@ F:	include/linux/console*
 
 CONTEXT TRACKING
 M:	Frederic Weisbecker <frederic@kernel.org>
+M:	"Paul E. McKenney" <paulmck@kernel.org>
 S:	Maintained
 F:	kernel/context_tracking.c
 F:	include/linux/context_tracking*
@@ -5361,7 +5408,7 @@ W:	http://www.chelsio.com
 F:	drivers/net/ethernet/chelsio/cxgb3/
 
 CXGB3 ISCSI DRIVER (CXGB3I)
-M:	Karen Xie <kxie@chelsio.com>
+M:	Varun Prakash <varun@chelsio.com>
 L:	linux-scsi@vger.kernel.org
 S:	Supported
 W:	http://www.chelsio.com
@@ -5393,7 +5440,7 @@ W:	http://www.chelsio.com
 F:	drivers/net/ethernet/chelsio/cxgb4/
 
 CXGB4 ISCSI DRIVER (CXGB4I)
-M:	Karen Xie <kxie@chelsio.com>
+M:	Varun Prakash <varun@chelsio.com>
 L:	linux-scsi@vger.kernel.org
 S:	Supported
 W:	http://www.chelsio.com
@@ -5764,6 +5811,7 @@ L:	linux-pm@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
 F:	Documentation/devicetree/bindings/devfreq/
+F:	Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
 F:	drivers/devfreq/
 F:	include/linux/devfreq.h
 F:	include/trace/events/devfreq.h
@@ -5838,6 +5886,7 @@ W:	http://www.dialog-semiconductor.com/products
 F:	Documentation/devicetree/bindings/input/da90??-onkey.txt
 F:	Documentation/devicetree/bindings/input/dlg,da72??.txt
 F:	Documentation/devicetree/bindings/mfd/da90*.txt
+F:	Documentation/devicetree/bindings/mfd/da90*.yaml
 F:	Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
 F:	Documentation/devicetree/bindings/regulator/da92*.txt
 F:	Documentation/devicetree/bindings/regulator/slg51000.txt
@@ -5953,6 +6002,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git
 F:	Documentation/devicetree/bindings/dma/
 F:	Documentation/driver-api/dmaengine/
 F:	drivers/dma/
+F:	include/dt-bindings/dma/
 F:	include/linux/dma/
 F:	include/linux/dmaengine.h
 F:	include/linux/of_dma.h
@@ -6284,6 +6334,12 @@ S:	Orphan / Obsolete
 F:	drivers/gpu/drm/i810/
 F:	include/uapi/drm/i810_drm.h
 
+DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER
+M:	Paul Kocialkowski <paul.kocialkowski@bootlin.com>
+S:	Supported
+T:	git git://anongit.freedesktop.org/drm/drm-misc
+F:	drivers/gpu/drm/logicvc/
+
 DRM DRIVER FOR LVDS PANELS
 M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 L:	dri-devel@lists.freedesktop.org
@@ -6462,6 +6518,7 @@ F:	include/uapi/drm/savage_drm.h
 
 DRM DRIVER FOR SIMPLE FRAMEBUFFERS
 M:	Thomas Zimmermann <tzimmermann@suse.de>
+M:	Javier Martinez Canillas <javierm@redhat.com>
 L:	dri-devel@lists.freedesktop.org
 S:	Maintained
 T:	git git://anongit.freedesktop.org/drm/drm-misc
@@ -6503,6 +6560,12 @@ DRM DRIVER FOR TDFX VIDEO CARDS
 S:	Orphan / Obsolete
 F:	drivers/gpu/drm/tdfx/
 
+DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
+F:	drivers/gpu/drm/bridge/ti-dlpc3433.c
+
 DRM DRIVER FOR TI SN65DSI86 BRIDGE CHIP
 R:	Douglas Anderson <dianders@chromium.org>
 F:	Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
@@ -6661,6 +6724,16 @@ F:	Documentation/devicetree/bindings/display/imx/
 F:	drivers/gpu/drm/imx/
 F:	drivers/gpu/ipu-v3/
 
+DRM DRIVERS FOR FREESCALE IMX BRIDGE
+M:	Liu Ying <victor.liu@nxp.com>
+L:	dri-devel@lists.freedesktop.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+F:	Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+F:	drivers/gpu/drm/bridge/imx/
+
 DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
 M:	Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
 L:	dri-devel@lists.freedesktop.org
@@ -6791,6 +6864,7 @@ F:	drivers/gpu/drm/omapdrm/
 
 DRM DRIVERS FOR V3D
 M:	Emma Anholt <emma@anholt.net>
+M:	Melissa Wen <mwen@igalia.com>
 S:	Supported
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 F:	Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
@@ -7394,6 +7468,8 @@ F:	include/video/s1d13xxxfb.h
 EROFS FILE SYSTEM
 M:	Gao Xiang <xiang@kernel.org>
 M:	Chao Yu <chao@kernel.org>
+R:	Yue Hu <huyue2@coolpad.com>
+R:	Jeffle Xu <jefflexu@linux.alibaba.com>
 L:	linux-erofs@lists.ozlabs.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
@@ -7682,9 +7758,6 @@ F:	include/linux/fs.h
 F:	include/linux/fs_types.h
 F:	include/uapi/linux/fs.h
 F:	include/uapi/linux/openat2.h
-X:	fs/io-wq.c
-X:	fs/io-wq.h
-X:	fs/io_uring.c
 
 FINTEK F75375S HARDWARE MONITOR AND FAN CONTROLLER DRIVER
 M:	Riku Voipio <riku.voipio@iki.fi>
@@ -7815,6 +7888,13 @@ F:	Documentation/fpga/
 F:	drivers/fpga/
 F:	include/linux/fpga/
 
+INTEL MAX10 BMC SECURE UPDATES
+M:	Russ Weight <russell.h.weight@intel.com>
+L:	linux-fpga@vger.kernel.org
+S:	Maintained
+F:	Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
+F:	drivers/fpga/intel-m10-bmc-sec-update.c
+
 FPU EMULATOR
 M:	Bill Metzenthen <billm@melbpc.org.au>
 S:	Maintained
@@ -8316,6 +8396,7 @@ Q:	https://patchwork.kernel.org/project/linux-phy/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
 F:	Documentation/devicetree/bindings/phy/
 F:	drivers/phy/
+F:	include/dt-bindings/phy/
 F:	include/linux/phy/
 
 GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
@@ -8479,6 +8560,7 @@ F:	Documentation/devicetree/bindings/gpio/
 F:	Documentation/driver-api/gpio/
 F:	drivers/gpio/
 F:	include/asm-generic/gpio.h
+F:	include/dt-bindings/gpio/
 F:	include/linux/gpio.h
 F:	include/linux/gpio/
 F:	include/linux/of_gpio.h
@@ -8944,16 +9026,25 @@ F:	Documentation/admin-guide/perf/hisi-pcie-pmu.rst
 F:	Documentation/admin-guide/perf/hisi-pmu.rst
 F:	drivers/perf/hisilicon
 
-HISILICON QM AND ZIP Controller DRIVER
+HISILICON QM DRIVER
+M:	Weili Qian <qianweili@huawei.com>
 M:	Zhou Wang <wangzhou1@hisilicon.com>
 L:	linux-crypto@vger.kernel.org
 S:	Maintained
-F:	Documentation/ABI/testing/debugfs-hisi-zip
+F:	drivers/crypto/hisilicon/Kconfig
+F:	drivers/crypto/hisilicon/Makefile
 F:	drivers/crypto/hisilicon/qm.c
 F:	drivers/crypto/hisilicon/sgl.c
-F:	drivers/crypto/hisilicon/zip/
 F:	include/linux/hisi_acc_qm.h
 
+HISILICON ZIP Controller DRIVER
+M:	Yang Shen <shenyang39@huawei.com>
+M:	Zhou Wang <wangzhou1@hisilicon.com>
+L:	linux-crypto@vger.kernel.org
+S:	Maintained
+F:	Documentation/ABI/testing/debugfs-hisi-zip
+F:	drivers/crypto/hisilicon/zip/
+
 HISILICON ROCE DRIVER
 M:	Wenpeng Liang <liangwenpeng@huawei.com>
 M:	Weihang Li <liweihang@huawei.com>
@@ -9132,6 +9223,7 @@ F:	drivers/media/platform/st/sti/hva
 
 HWPOISON MEMORY FAILURE HANDLING
 M:	Naoya Horiguchi <naoya.horiguchi@nec.com>
+R:	Miaohe Lin <linmiaohe@huawei.com>
 L:	linux-mm@kvack.org
 S:	Maintained
 F:	mm/hwpoison-inject.c
@@ -9617,6 +9709,7 @@ F:	Documentation/ABI/testing/sysfs-bus-iio*
 F:	Documentation/devicetree/bindings/iio/
 F:	drivers/iio/
 F:	drivers/staging/iio/
+F:	include/dt-bindings/iio/
 F:	include/linux/iio/
 F:	tools/iio/
 
@@ -9813,7 +9906,10 @@ INTEL ASoC DRIVERS
 M:	Cezary Rojewski <cezary.rojewski@intel.com>
 M:	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 M:	Liam Girdwood <liam.r.girdwood@linux.intel.com>
-M:	Jie Yang <yang.jie@linux.intel.com>
+M:	Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+M:	Bard Liao <yung-chuan.liao@linux.intel.com>
+M:	Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+M:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Supported
 F:	sound/soc/intel/
@@ -9942,7 +10038,8 @@ S:	Supported
 Q:	https://patchwork.kernel.org/project/linux-dmaengine/list/
 F:	drivers/dma/ioat*
 
-INTEL IADX DRIVER
+INTEL IDXD DRIVER
+M:	Fenghua Yu <fenghua.yu@intel.com>
 M:	Dave Jiang <dave.jiang@intel.com>
 L:	dmaengine@vger.kernel.org
 S:	Supported
@@ -10136,7 +10233,7 @@ F:	drivers/gpio/gpio-*cove.c
 
 INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
 M:	Andy Shevchenko <andy@kernel.org>
-S:	Maintained
+S:	Supported
 F:	drivers/mfd/intel_soc_pmic*
 F:	include/linux/mfd/intel_soc_pmic*
 
@@ -10380,9 +10477,7 @@ L:	io-uring@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.dk/linux-block
 T:	git git://git.kernel.dk/liburing
-F:	fs/io-wq.c
-F:	fs/io-wq.h
-F:	fs/io_uring.c
+F:	io_uring/
 F:	include/linux/io_uring.h
 F:	include/uapi/linux/io_uring.h
 F:	tools/io_uring/
@@ -11098,20 +11193,6 @@ S:	Maintained
 F:	include/net/l3mdev.h
 F:	net/l3mdev
 
-L7 BPF FRAMEWORK
-M:	John Fastabend <john.fastabend@gmail.com>
-M:	Daniel Borkmann <daniel@iogearbox.net>
-M:	Jakub Sitnicki <jakub@cloudflare.com>
-L:	netdev@vger.kernel.org
-L:	bpf@vger.kernel.org
-S:	Maintained
-F:	include/linux/skmsg.h
-F:	net/core/skmsg.c
-F:	net/core/sock_map.c
-F:	net/ipv4/tcp_bpf.c
-F:	net/ipv4/udp_bpf.c
-F:	net/unix/unix_bpf.c
-
 LANDLOCK SECURITY MODULE
 M:	Mickaël Salaün <mic@digikod.net>
 L:	linux-security-module@vger.kernel.org
@@ -11591,6 +11672,7 @@ F:	drivers/gpu/drm/bridge/lontium-lt8912b.c
 LOONGARCH
 M:	Huacai Chen <chenhuacai@kernel.org>
 R:	WANG Xuerui <kernel@xen0n.name>
+L:	loongarch@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
 F:	arch/loongarch/
@@ -11791,6 +11873,18 @@ L:	linux-man@vger.kernel.org
 S:	Maintained
 W:	http://www.kernel.org/doc/man-pages
 
+MAPLE TREE
+M:	Liam R. Howlett <Liam.Howlett@oracle.com>
+L:	linux-mm@kvack.org
+S:	Supported
+F:	Documentation/core-api/maple_tree.rst
+F:	include/linux/maple_tree.h
+F:	include/trace/events/maple_tree.h
+F:	lib/maple_tree.c
+F:	lib/test_maple_tree.c
+F:	tools/testing/radix-tree/linux/maple_tree.h
+F:	tools/testing/radix-tree/maple.c
+
 MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
 M:	Rahul Bedarkar <rahulbedarkar89@gmail.com>
 L:	linux-mips@vger.kernel.org
@@ -12129,7 +12223,6 @@ F:	Documentation/devicetree/bindings/*/maxim,max77686.yaml
 F:	Documentation/devicetree/bindings/*/maxim,max77693.yaml
 F:	Documentation/devicetree/bindings/*/maxim,max77843.yaml
 F:	Documentation/devicetree/bindings/clock/maxim,max77686.txt
-F:	Documentation/devicetree/bindings/mfd/max77693.txt
 F:	drivers/*/*max77843.c
 F:	drivers/*/max14577*.c
 F:	drivers/*/max77686*.c
@@ -12846,9 +12939,8 @@ M:	Andrew Morton <akpm@linux-foundation.org>
 L:	linux-mm@kvack.org
 S:	Maintained
 W:	http://www.linux-mm.org
-T:	quilt https://ozlabs.org/~akpm/mmotm/
-T:	quilt https://ozlabs.org/~akpm/mmots/
-T:	git git://github.com/hnaz/linux-mm.git
+T:	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
+T:	quilt git://git.kernel.org/pub/scm/linux/kernel/git/akpm/25-new
 F:	include/linux/gfp.h
 F:	include/linux/memory_hotplug.h
 F:	include/linux/mm.h
@@ -12858,6 +12950,18 @@ F:	include/linux/vmalloc.h
 F:	mm/
 F:	tools/testing/selftests/vm/
 
+MEMORY HOT(UN)PLUG
+M:	David Hildenbrand <david@redhat.com>
+M:	Oscar Salvador <osalvador@suse.de>
+L:	linux-mm@kvack.org
+S:	Maintained
+F:	Documentation/admin-guide/mm/memory-hotplug.rst
+F:	Documentation/core-api/memory-hotplug.rst
+F:	drivers/base/memory.c
+F:	include/linux/memory_hotplug.h
+F:	mm/memory_hotplug.c
+F:	tools/testing/selftests/memory-hotplug/
+
 MEMORY TECHNOLOGY DEVICES (MTD)
 M:	Miquel Raynal <miquel.raynal@bootlin.com>
 M:	Richard Weinberger <richard@nod.at>
@@ -13110,6 +13214,14 @@ S:	Supported
 F:	Documentation/devicetree/bindings/mtd/atmel-nand.txt
 F:	drivers/mtd/nand/raw/atmel/*
 
+MICROCHIP OTPC DRIVER
+M:	Claudiu Beznea <claudiu.beznea@microchip.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Supported
+F:	Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+F:	drivers/nvmem/microchip-otpc.c
+F:	include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
+
 MICROCHIP PWM DRIVER
 M:	Claudiu Beznea <claudiu.beznea@microchip.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -13954,7 +14066,6 @@ F:	net/ipv6/tcp*.c
 NETWORKING [TLS]
 M:	Boris Pismenny <borisp@nvidia.com>
 M:	John Fastabend <john.fastabend@gmail.com>
-M:	Daniel Borkmann <daniel@iogearbox.net>
 M:	Jakub Kicinski <kuba@kernel.org>
 L:	netdev@vger.kernel.org
 S:	Maintained
@@ -14263,7 +14374,7 @@ F:	drivers/iio/gyro/fxas21002c_i2c.c
 F:	drivers/iio/gyro/fxas21002c_spi.c
 
 NXP i.MX CLOCK DRIVERS
-M:	Abel Vesa <abel.vesa@nxp.com>
+M:	Abel Vesa <abelvesa@kernel.org>
 L:	linux-clk@vger.kernel.org
 L:	linux-imx@nxp.com
 S:	Maintained
@@ -14880,7 +14991,7 @@ M:	Peter Korsgaard <peter@korsgaard.com>
 M:	Andrew Lunn <andrew@lunn.ch>
 L:	linux-i2c@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+F:	Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml
 F:	Documentation/i2c/busses/i2c-ocores.rst
 F:	drivers/i2c/busses/i2c-ocores.c
 F:	include/linux/platform_data/i2c-ocores.h
@@ -15741,7 +15852,7 @@ F:	drivers/pinctrl/freescale/
 PIN CONTROLLER - INTEL
 M:	Mika Westerberg <mika.westerberg@linux.intel.com>
 M:	Andy Shevchenko <andy@kernel.org>
-S:	Maintained
+S:	Supported
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
 F:	drivers/pinctrl/intel/
 
@@ -16263,7 +16374,7 @@ F:	drivers/crypto/qat/
 
 QCOM AUDIO (ASoC) DRIVERS
 M:	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-M:	Banajit Goswami <bgoswami@codeaurora.org>
+M:	Banajit Goswami <bgoswami@quicinc.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Supported
 F:	sound/soc/codecs/lpass-va-macro.c
@@ -17162,6 +17273,8 @@ S:	Supported
 F:	arch/riscv/boot/dts/microchip/
 F:	drivers/mailbox/mailbox-mpfs.c
 F:	drivers/soc/microchip/
+F:	drivers/spi/spi-microchip-core.c
+F:	drivers/usb/musb/mpfs.c
 F:	include/soc/microchip/mpfs.h
 
 RNBD BLOCK DRIVERS
@@ -17356,6 +17469,21 @@ L:	linux-rdma@vger.kernel.org
 S:	Maintained
 F:	drivers/infiniband/ulp/rtrs/
 
+RUST
+M:	Miguel Ojeda <ojeda@kernel.org>
+M:	Alex Gaynor <alex.gaynor@gmail.com>
+M:	Wedson Almeida Filho <wedsonaf@google.com>
+L:	rust-for-linux@vger.kernel.org
+S:	Supported
+W:	https://github.com/Rust-for-Linux/linux
+B:	https://github.com/Rust-for-Linux/linux/issues
+T:	git https://github.com/Rust-for-Linux/linux.git rust-next
+F:	Documentation/rust/
+F:	rust/
+F:	samples/rust/
+F:	scripts/*rust*
+K:	\b(?i:rust)\b
+
 RXRPC SOCKETS (AF_RXRPC)
 M:	David Howells <dhowells@redhat.com>
 M:	Marc Dionne <marc.dionne@auristor.com>
@@ -18689,8 +18817,10 @@ F:	sound/soc/
 SOUND - SOUND OPEN FIRMWARE (SOF) DRIVERS
 M:	Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 M:	Liam Girdwood <lgirdwood@gmail.com>
+M:	Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+M:	Bard Liao <yung-chuan.liao@linux.intel.com>
 M:	Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
-M:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
+R:	Kai Vehmanen <kai.vehmanen@linux.intel.com>
 M:	Daniel Baluta <daniel.baluta@nxp.com>
 L:	sound-open-firmware@alsa-project.org (moderated for non-subscribers)
 S:	Supported
@@ -18939,6 +19069,7 @@ F:	drivers/staging/olpc_dcon/
 STAGING - REALTEK RTL8188EU DRIVERS
 M:	Larry Finger <Larry.Finger@lwfinger.net>
 M:	Phillip Potter <phil@philpotter.co.uk>
+R:	Pavel Skripkin <paskripkin@gmail.com>
 S:	Supported
 F:	drivers/staging/r8188eu/
 
@@ -19772,6 +19903,7 @@ F:	Documentation/ABI/testing/sysfs-class-thermal
 F:	Documentation/devicetree/bindings/thermal/
 F:	Documentation/driver-api/thermal/
 F:	drivers/thermal/
+F:	include/dt-bindings/thermal/
 F:	include/linux/cpu_cooling.h
 F:	include/linux/thermal.h
 F:	include/uapi/linux/thermal.h
@@ -20454,6 +20586,13 @@ L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	drivers/ufs/host/ufs-mediatek*
 
+UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS
+M:	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+L:	linux-renesas-soc@vger.kernel.org
+L:	linux-scsi@vger.kernel.org
+S:	Maintained
+F:	drivers/ufs/host/ufs-renesas.c
+
 UNSORTED BLOCK IMAGES (UBI)
 M:	Richard Weinberger <richard@nod.at>
 L:	linux-mtd@lists.infradead.org
@@ -20714,6 +20853,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
 F:	Documentation/devicetree/bindings/usb/
 F:	Documentation/usb/
 F:	drivers/usb/
+F:	include/dt-bindings/usb/
 F:	include/linux/usb.h
 F:	include/linux/usb/
 
@@ -20893,6 +21033,7 @@ M:	OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
 S:	Maintained
 F:	Documentation/filesystems/vfat.rst
 F:	fs/fat/
+F:	tools/testing/selftests/filesystems/fat/
 
 VFIO DRIVER
 M:	Alex Williamson <alex.williamson@redhat.com>
@@ -21248,12 +21389,10 @@ M:	Martyn Welch <martyn@welchs.me.uk>
 M:	Manohar Vanga <manohar.vanga@gmail.com>
 M:	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 L:	linux-kernel@vger.kernel.org
-S:	Maintained
+S:	Odd fixes
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
 F:	Documentation/driver-api/vme.rst
 F:	drivers/staging/vme_user/
-F:	drivers/vme/
-F:	include/linux/vme*
 
 VM SOCKETS (AF_VSOCK)
 M:	Stefano Garzarella <sgarzare@redhat.com>
diff --git a/Makefile b/Makefile
index 513c1fbf7888..e911262bbb71 100644
--- a/Makefile
+++ b/Makefile
@@ -120,6 +120,15 @@ endif
 
 export KBUILD_CHECKSRC
 
+# Enable "clippy" (a linter) as part of the Rust compilation.
+#
+# Use 'make CLIPPY=1' to enable it.
+ifeq ("$(origin CLIPPY)", "command line")
+  KBUILD_CLIPPY := $(CLIPPY)
+endif
+
+export KBUILD_CLIPPY
+
 # Use make M=dir or set the environment variable KBUILD_EXTMOD to specify the
 # directory of external module to build. Setting M= takes precedence.
 ifeq ("$(origin M)", "command line")
@@ -267,7 +276,7 @@ no-dot-config-targets := $(clean-targets) \
 			 cscope gtags TAGS tags help% %docs check% coccicheck \
 			 $(version_h) headers headers_% archheaders archscripts \
 			 %asm-generic kernelversion %src-pkg dt_binding_check \
-			 outputmakefile
+			 outputmakefile rustavailable rustfmt rustfmtcheck
 # Installation targets should not require compiler. Unfortunately, vdso_install
 # is an exception where build artifacts may be updated. This must be fixed.
 no-compiler-targets := $(no-dot-config-targets) install dtbs_install \
@@ -437,6 +446,7 @@ HOSTCC	= gcc
 HOSTCXX	= g++
 endif
 HOSTPKG_CONFIG	= pkg-config
+HOSTRUSTC = rustc
 
 KBUILD_USERHOSTCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \
 			 -O2 -fomit-frame-pointer -std=gnu11 \
@@ -444,8 +454,26 @@ KBUILD_USERHOSTCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \
 KBUILD_USERCFLAGS  := $(KBUILD_USERHOSTCFLAGS) $(USERCFLAGS)
 KBUILD_USERLDFLAGS := $(USERLDFLAGS)
 
+# These flags apply to all Rust code in the tree, including the kernel and
+# host programs.
+export rust_common_flags := --edition=2021 \
+			    -Zbinary_dep_depinfo=y \
+			    -Dunsafe_op_in_unsafe_fn -Drust_2018_idioms \
+			    -Dunreachable_pub -Dnon_ascii_idents \
+			    -Wmissing_docs \
+			    -Drustdoc::missing_crate_level_docs \
+			    -Dclippy::correctness -Dclippy::style \
+			    -Dclippy::suspicious -Dclippy::complexity \
+			    -Dclippy::perf \
+			    -Dclippy::let_unit_value -Dclippy::mut_mut \
+			    -Dclippy::needless_bitwise_bool \
+			    -Dclippy::needless_continue \
+			    -Wclippy::dbg_macro
+
 KBUILD_HOSTCFLAGS   := $(KBUILD_USERHOSTCFLAGS) $(HOST_LFS_CFLAGS) $(HOSTCFLAGS)
 KBUILD_HOSTCXXFLAGS := -Wall -O2 $(HOST_LFS_CFLAGS) $(HOSTCXXFLAGS)
+KBUILD_HOSTRUSTFLAGS := $(rust_common_flags) -O -Cstrip=debuginfo \
+			-Zallow-features= $(HOSTRUSTFLAGS)
 KBUILD_HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS) $(HOSTLDFLAGS)
 KBUILD_HOSTLDLIBS   := $(HOST_LFS_LIBS) $(HOSTLDLIBS)
 
@@ -470,6 +498,12 @@ OBJDUMP		= $(CROSS_COMPILE)objdump
 READELF		= $(CROSS_COMPILE)readelf
 STRIP		= $(CROSS_COMPILE)strip
 endif
+RUSTC		= rustc
+RUSTDOC		= rustdoc
+RUSTFMT		= rustfmt
+CLIPPY_DRIVER	= clippy-driver
+BINDGEN		= bindgen
+CARGO		= cargo
 PAHOLE		= pahole
 RESOLVE_BTFIDS	= $(objtree)/tools/bpf/resolve_btfids/resolve_btfids
 LEX		= flex
@@ -495,9 +529,11 @@ CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
 		  -Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
 NOSTDINC_FLAGS :=
 CFLAGS_MODULE   =
+RUSTFLAGS_MODULE =
 AFLAGS_MODULE   =
 LDFLAGS_MODULE  =
 CFLAGS_KERNEL	=
+RUSTFLAGS_KERNEL =
 AFLAGS_KERNEL	=
 LDFLAGS_vmlinux =
 
@@ -526,15 +562,42 @@ KBUILD_CFLAGS   := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs \
 		   -Werror=return-type -Wno-format-security \
 		   -std=gnu11
 KBUILD_CPPFLAGS := -D__KERNEL__
+KBUILD_RUSTFLAGS := $(rust_common_flags) \
+		    --target=$(objtree)/rust/target.json \
+		    -Cpanic=abort -Cembed-bitcode=n -Clto=n \
+		    -Cforce-unwind-tables=n -Ccodegen-units=1 \
+		    -Csymbol-mangling-version=v0 \
+		    -Crelocation-model=static \
+		    -Zfunction-sections=n \
+		    -Dclippy::float_arithmetic
+
 KBUILD_AFLAGS_KERNEL :=
 KBUILD_CFLAGS_KERNEL :=
+KBUILD_RUSTFLAGS_KERNEL :=
 KBUILD_AFLAGS_MODULE  := -DMODULE
 KBUILD_CFLAGS_MODULE  := -DMODULE
+KBUILD_RUSTFLAGS_MODULE := --cfg MODULE
 KBUILD_LDFLAGS_MODULE :=
 KBUILD_LDFLAGS :=
 CLANG_FLAGS :=
 
+ifeq ($(KBUILD_CLIPPY),1)
+	RUSTC_OR_CLIPPY_QUIET := CLIPPY
+	RUSTC_OR_CLIPPY = $(CLIPPY_DRIVER)
+else
+	RUSTC_OR_CLIPPY_QUIET := RUSTC
+	RUSTC_OR_CLIPPY = $(RUSTC)
+endif
+
+ifdef RUST_LIB_SRC
+	export RUST_LIB_SRC
+endif
+
+export RUSTC_BOOTSTRAP := 1
+
 export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC HOSTPKG_CONFIG
+export RUSTC RUSTDOC RUSTFMT RUSTC_OR_CLIPPY_QUIET RUSTC_OR_CLIPPY BINDGEN CARGO
+export HOSTRUSTC KBUILD_HOSTRUSTFLAGS
 export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL
 export PERL PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX
 export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD
@@ -543,9 +606,10 @@ export KBUILD_USERCFLAGS KBUILD_USERLDFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS
 export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE
+export KBUILD_RUSTFLAGS RUSTFLAGS_KERNEL RUSTFLAGS_MODULE
 export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE
-export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE
-export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL
+export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_RUSTFLAGS_MODULE KBUILD_LDFLAGS_MODULE
+export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL KBUILD_RUSTFLAGS_KERNEL
 export PAHOLE_FLAGS
 
 # Files to ignore in find ... statements
@@ -726,7 +790,7 @@ $(KCONFIG_CONFIG):
 #
 # Do not use $(call cmd,...) here. That would suppress prompts from syncconfig,
 # so you cannot notice that Kconfig is waiting for the user input.
-%/config/auto.conf %/config/auto.conf.cmd %/generated/autoconf.h: $(KCONFIG_CONFIG)
+%/config/auto.conf %/config/auto.conf.cmd %/generated/autoconf.h %/generated/rustc_cfg: $(KCONFIG_CONFIG)
 	$(Q)$(kecho) "  SYNC    $@"
 	$(Q)$(MAKE) -f $(srctree)/Makefile syncconfig
 else # !may-sync-config
@@ -755,11 +819,27 @@ KBUILD_CFLAGS	+= $(call cc-disable-warning, address-of-packed-member)
 
 ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE
 KBUILD_CFLAGS += -O2
+KBUILD_RUSTFLAGS_OPT_LEVEL_MAP := 2
 else ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3
 KBUILD_CFLAGS += -O3
+KBUILD_RUSTFLAGS_OPT_LEVEL_MAP := 3
 else ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 KBUILD_CFLAGS += -Os
-endif
+KBUILD_RUSTFLAGS_OPT_LEVEL_MAP := s
+endif
+
+# Always set `debug-assertions` and `overflow-checks` because their default
+# depends on `opt-level` and `debug-assertions`, respectively.
+KBUILD_RUSTFLAGS += -Cdebug-assertions=$(if $(CONFIG_RUST_DEBUG_ASSERTIONS),y,n)
+KBUILD_RUSTFLAGS += -Coverflow-checks=$(if $(CONFIG_RUST_OVERFLOW_CHECKS),y,n)
+KBUILD_RUSTFLAGS += -Copt-level=$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_SIMILAR_AS_CHOSEN_FOR_C),$(KBUILD_RUSTFLAGS_OPT_LEVEL_MAP))$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_0),0)$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_1),1)$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_2),2)$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_3),3)$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_S),s)$\
+	$(if $(CONFIG_RUST_OPT_LEVEL_Z),z)
 
 # Tell gcc to never replace conditional load with a non-conditional one
 ifdef CONFIG_CC_IS_GCC
@@ -791,6 +871,9 @@ KBUILD_CFLAGS-$(CONFIG_WERROR) += -Werror
 KBUILD_CFLAGS-$(CONFIG_CC_NO_ARRAY_BOUNDS) += -Wno-array-bounds
 KBUILD_CFLAGS += $(KBUILD_CFLAGS-y) $(CONFIG_CC_IMPLICIT_FALLTHROUGH)
 
+KBUILD_RUSTFLAGS-$(CONFIG_WERROR) += -Dwarnings
+KBUILD_RUSTFLAGS += $(KBUILD_RUSTFLAGS-y)
+
 ifdef CONFIG_CC_IS_CLANG
 KBUILD_CPPFLAGS += -Qunused-arguments
 # The kernel builds with '-std=gnu11' so use of GNU extensions is acceptable.
@@ -811,12 +894,15 @@ KBUILD_CFLAGS += $(call cc-disable-warning, dangling-pointer)
 
 ifdef CONFIG_FRAME_POINTER
 KBUILD_CFLAGS	+= -fno-omit-frame-pointer -fno-optimize-sibling-calls
+KBUILD_RUSTFLAGS += -Cforce-frame-pointers=y
 else
 # Some targets (ARM with Thumb2, for example), can't be built with frame
 # pointers.  For those, we don't have FUNCTION_TRACER automatically
 # select FRAME_POINTER.  However, FUNCTION_TRACER adds -pg, and this is
 # incompatible with -fomit-frame-pointer with current GCC, so we don't use
 # -fomit-frame-pointer with FUNCTION_TRACER.
+# In the Rust target specification, "frame-pointer" is set explicitly
+# to "may-omit".
 ifndef CONFIG_FUNCTION_TRACER
 KBUILD_CFLAGS	+= -fomit-frame-pointer
 endif
@@ -881,8 +967,10 @@ ifdef CONFIG_DEBUG_SECTION_MISMATCH
 KBUILD_CFLAGS += -fno-inline-functions-called-once
 endif
 
+# `rustc`'s `-Zfunction-sections` applies to data too (as of 1.59.0).
 ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION
 KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections
+KBUILD_RUSTFLAGS_KERNEL += -Zfunction-sections=y
 LDFLAGS_vmlinux += --gc-sections
 endif
 
@@ -1025,10 +1113,11 @@ include $(addprefix $(srctree)/, $(include-y))
 # Do not add $(call cc-option,...) below this line. When you build the kernel
 # from the clean source tree, the GCC plugins do not exist at this point.
 
-# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
+# Add user supplied CPPFLAGS, AFLAGS, CFLAGS and RUSTFLAGS as the last assignments
 KBUILD_CPPFLAGS += $(KCPPFLAGS)
 KBUILD_AFLAGS   += $(KAFLAGS)
 KBUILD_CFLAGS   += $(KCFLAGS)
+KBUILD_RUSTFLAGS += $(KRUSTFLAGS)
 
 KBUILD_LDFLAGS_MODULE += --build-id=sha1
 LDFLAGS_vmlinux += --build-id=sha1
@@ -1097,6 +1186,8 @@ export MODULES_NSDEPS := $(extmod_prefix)modules.nsdeps
 ifeq ($(KBUILD_EXTMOD),)
 core-y			+= kernel/ certs/ mm/ fs/ ipc/ security/ crypto/
 core-$(CONFIG_BLOCK)	+= block/
+core-$(CONFIG_IO_URING)	+= io_uring/
+core-$(CONFIG_RUST)	+= rust/
 
 vmlinux-dirs	:= $(patsubst %/,%,$(filter %/, \
 		     $(core-y) $(core-m) $(drivers-y) $(drivers-m) \
@@ -1201,6 +1292,10 @@ prepare0: archprepare
 
 # All the preparing..
 prepare: prepare0
+ifdef CONFIG_RUST
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust-is-available.sh -v
+	$(Q)$(MAKE) $(build)=rust
+endif
 
 PHONY += remove-stale-files
 remove-stale-files:
@@ -1490,7 +1585,7 @@ endif # CONFIG_MODULES
 # Directories & files removed with 'make clean'
 CLEAN_FILES += include/ksym vmlinux.symvers modules-only.symvers \
 	       modules.builtin modules.builtin.modinfo modules.nsdeps \
-	       compile_commands.json .thinlto-cache
+	       compile_commands.json .thinlto-cache rust/test rust/doc
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_FILES += include/config include/generated          \
@@ -1501,7 +1596,8 @@ MRPROPER_FILES += include/config include/generated          \
 		  certs/signing_key.pem \
 		  certs/x509.genkey \
 		  vmlinux-gdb.py \
-		  *.spec
+		  *.spec \
+		  rust/target.json rust/libmacros.so
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1526,6 +1622,9 @@ $(mrproper-dirs):
 
 mrproper: clean $(mrproper-dirs)
 	$(call cmd,rmfiles)
+	@find . $(RCS_FIND_IGNORE) \
+		\( -name '*.rmeta' \) \
+		-type f -print | xargs rm -f
 
 # distclean
 #
@@ -1613,6 +1712,23 @@ help:
 	@echo  '  kselftest-merge   - Merge all the config dependencies of'
 	@echo  '		      kselftest to existing .config.'
 	@echo  ''
+	@echo  'Rust targets:'
+	@echo  '  rustavailable   - Checks whether the Rust toolchain is'
+	@echo  '		    available and, if not, explains why.'
+	@echo  '  rustfmt	  - Reformat all the Rust code in the kernel'
+	@echo  '  rustfmtcheck	  - Checks if all the Rust code in the kernel'
+	@echo  '		    is formatted, printing a diff otherwise.'
+	@echo  '  rustdoc	  - Generate Rust documentation'
+	@echo  '		    (requires kernel .config)'
+	@echo  '  rusttest        - Runs the Rust tests'
+	@echo  '                    (requires kernel .config; downloads external repos)'
+	@echo  '  rust-analyzer	  - Generate rust-project.json rust-analyzer support file'
+	@echo  '		    (requires kernel .config)'
+	@echo  '  dir/file.[os]   - Build specified target only'
+	@echo  '  dir/file.i      - Build macro expanded source, similar to C preprocessing'
+	@echo  '                    (run with RUSTFMT=n to skip reformatting if needed)'
+	@echo  '  dir/file.ll     - Build the LLVM assembly file'
+	@echo  ''
 	@$(if $(dtstree), \
 		echo 'Devicetree:'; \
 		echo '* dtbs             - Build device tree blobs for enabled boards'; \
@@ -1685,6 +1801,52 @@ PHONY += $(DOC_TARGETS)
 $(DOC_TARGETS):
 	$(Q)$(MAKE) $(build)=Documentation $@
 
+
+# Rust targets
+# ---------------------------------------------------------------------------
+
+# "Is Rust available?" target
+PHONY += rustavailable
+rustavailable:
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust-is-available.sh -v && echo >&2 "Rust is available!"
+
+# Documentation target
+#
+# Using the singular to avoid running afoul of `no-dot-config-targets`.
+PHONY += rustdoc
+rustdoc: prepare
+	$(Q)$(MAKE) $(build)=rust $@
+
+# Testing target
+PHONY += rusttest
+rusttest: prepare
+	$(Q)$(MAKE) $(build)=rust $@
+
+# Formatting targets
+PHONY += rustfmt rustfmtcheck
+
+# We skip `rust/alloc` since we want to minimize the diff w.r.t. upstream.
+#
+# We match using absolute paths since `find` does not resolve them
+# when matching, which is a problem when e.g. `srctree` is `..`.
+# We `grep` afterwards in order to remove the directory entry itself.
+rustfmt:
+	$(Q)find $(abs_srctree) -type f -name '*.rs' \
+		-o -path $(abs_srctree)/rust/alloc -prune \
+		-o -path $(abs_objtree)/rust/test -prune \
+		| grep -Fv $(abs_srctree)/rust/alloc \
+		| grep -Fv $(abs_objtree)/rust/test \
+		| grep -Fv generated \
+		| xargs $(RUSTFMT) $(rustfmt_flags)
+
+rustfmtcheck: rustfmt_flags = --check
+rustfmtcheck: rustfmt
+
+# IDE support targets
+PHONY += rust-analyzer
+rust-analyzer:
+	$(Q)$(MAKE) $(build)=rust $@
+
 # Misc
 # ---------------------------------------------------------------------------
 
diff --git a/Next/SHA1s b/Next/SHA1s
new file mode 100644
index 000000000000..a96e14bbb2ef
--- /dev/null
+++ b/Next/SHA1s
@@ -0,0 +1,358 @@
+Name		SHA1
+----		----
+origin		de5c208d533a46a074eb46ea17f672cc005a7269
+fixes		d06c942efea40e1701ade200477a7449008d9f24
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+extcon		775486c096982ff8e768f467bc3c3e91635f1e97
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+kspp-gustavo	f2906aa863381afb0015a9eb7fefad885d4e5a56
+mm-stable	6edda04ccc7cfb281d139e352dbd5dd933bd2751
+mm-nonmm-stable	00c9d5632277b21ba8802e26c27254cd9d0dfa13
+mm		8b3452cdabacfcfe3b627b2d735ed4411ce40ca2
+amdgpu		fdf249c70a36e2daa7ddf1252cf3b71faed87abc
diff --git a/Next/Trees b/Next/Trees
new file mode 100644
index 000000000000..3e0f1e03dadf
--- /dev/null
+++ b/Next/Trees
@@ -0,0 +1,361 @@
+Trees included into this release:
+
+Name		Type	URL
+----		----	---
+origin		git	git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#master
+fixes		git	git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes.git#fixes
+mm-hotfixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-hotfixes-unstable
+kbuild-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git#fixes
+arc-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git#for-curr
+arm-current	git	git://git.armlinux.org.uk/~rmk/linux-arm.git#fixes
+arm64-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux#for-next/fixes
+arm-soc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git#arm/fixes
+drivers-memory-fixes	git	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git#fixes
+tee-fixes	git	https://git.linaro.org/people/jens.wiklander/linux-tee.git#fixes
+m68k-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git#for-linus
+powerpc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git#fixes
+s390-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git#fixes
+sparc		git	git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc.git#master
+fscrypt-current	git	git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git#for-stable
+net		git	git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git#master
+bpf		git	git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git#master
+ipsec		git	git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git#master
+netfilter	git	git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf.git#master
+ipvs		git	git://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs.git#master
+wireless	git	git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless.git#for-next
+rdma-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#for-rc
+sound-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git#for-linus
+sound-asoc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-linus
+regmap-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-linus
+regulator-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-linus
+spi-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-linus
+pci-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git#for-linus
+driver-core.current	git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git#driver-core-linus
+tty.current	git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git#tty-linus
+usb.current	git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#usb-linus
+usb-gadget-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git#fixes
+usb-serial-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git#usb-linus
+phy		git	git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git#fixes
+staging.current	git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git#staging-linus
+iio-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git#fixes-togreg
+counter-fixes	git	https://gitlab.com/vilhelmgray/counter.git#fixes-togreg
+char-misc.current	git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git#char-misc-linus
+soundwire-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git#fixes
+thunderbolt-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git#fixes
+input-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git#for-linus
+crypto-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git#master
+vfio-fixes	git	git://github.com/awilliam/linux-vfio.git#for-linus
+kselftest-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#fixes
+modules-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git#modules-linus
+dmaengine-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git#fixes
+backlight-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git#for-backlight-fixes
+mtd-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#mtd/fixes
+mfd-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-fixes
+v4l-dvb-fixes	git	git://linuxtv.org/mchehab/media-next.git#fixes
+reset-fixes	git	https://git.pengutronix.de/git/pza/linux#reset/fixes
+mips-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git#mips-fixes
+at91-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git#at91-fixes
+omap-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git#fixes
+kvm-fixes	git	git://git.kernel.org/pub/scm/virt/kvm/kvm.git#master
+kvms390-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git#master
+hwmon-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git#hwmon
+nvdimm-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git#libnvdimm-fixes
+cxl-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git#fixes
+btrfs-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git#next-fixes
+vfs-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git#fixes
+dma-mapping-fixes	git	git://git.infradead.org/users/hch/dma-mapping.git#for-linus
+i3c-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git#i3c/fixes
+drivers-x86-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git#fixes
+samsung-krzk-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git#fixes
+pinctrl-samsung-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git#fixes
+devicetree-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#dt/linus
+dt-krzk-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git#fixes
+scsi-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git#fixes
+drm-fixes	git	git://git.freedesktop.org/git/drm/drm.git#drm-fixes
+amdgpu-fixes	git	git://people.freedesktop.org/~agd5f/linux#drm-fixes
+drm-intel-fixes	git	git://anongit.freedesktop.org/drm-intel#for-linux-next-fixes
+mmc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#fixes
+rtc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git#rtc-fixes
+gnss-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git#gnss-linus
+hyperv-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git#hyperv-fixes
+soc-fsl-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux.git#fix
+risc-v-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git#fixes
+risc-v-mc-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#dt-fixes
+pidfd-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git#fixes
+fpga-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git#fixes
+spdx		git	git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx.git#spdx-linus
+gpio-brgl-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#gpio/for-current
+gpio-intel-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git#fixes
+pinctrl-intel-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git#fixes
+erofs-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git#fixes
+integrity-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity#fixes
+kunit-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#kunit-fixes
+ubifs-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git#fixes
+memblock-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git#fixes
+cel-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux#for-rc
+irqchip-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git#irq/irqchip-fixes
+renesas-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git#fixes
+broadcom-fixes	git	https://github.com/Broadcom/stblinux.git#fixes
+perf-current	git	git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git#perf/urgent
+efi-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git#urgent
+zstd-fixes	git	https://github.com/terrelln/linux.git#zstd-linus
+battery-fixes	git	git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#fixes
+drm-misc-fixes	git	git://anongit.freedesktop.org/drm/drm-misc#for-linux-next-fixes
+kbuild		git	git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git#for-next
+clang-format	git	https://github.com/ojeda/linux.git#clang-format
+perf		git	git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git#perf/core
+compiler-attributes	git	https://github.com/ojeda/linux.git#compiler-attributes
+dma-mapping	git	git://git.infradead.org/users/hch/dma-mapping.git#for-next
+asm-generic	git	git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git#master
+arc		git	git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git#for-next
+arm		git	git://git.armlinux.org.uk/~rmk/linux-arm.git#for-next
+arm64		git	git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux#for-next/core
+arm-perf	git	git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git#for-next/perf
+arm-soc		git	git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git#for-next
+actions		git	git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions.git#for-next
+amlogic		git	git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git#for-next
+aspeed		git	git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git#for-next
+at91		git	git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git#at91-next
+broadcom	git	https://github.com/Broadcom/stblinux.git#next
+drivers-memory	git	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git#for-next
+imx-mxs		git	git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git#for-next
+keystone	git	git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git#next
+mediatek	git	git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git#for-next
+mvebu		git	git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git#for-next
+omap		git	git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git#for-next
+qcom		git	git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git#for-next
+raspberrypi	git	git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git#for-next
+renesas		git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git#next
+reset		git	https://git.pengutronix.de/git/pza/linux#reset/next
+rockchip	git	git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git#for-next
+samsung-krzk	git	git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git#for-next
+scmi		git	git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git#for-linux-next
+stm32		git	git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git#stm32-next
+sunxi		git	git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git#sunxi/for-next
+tee		git	https://git.linaro.org/people/jens.wiklander/linux-tee.git#next
+tegra		git	git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git#for-next
+ti		git	git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git#ti-next
+xilinx		git	git://github.com/Xilinx/linux-xlnx.git#for-next
+clk		git	git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-next
+clk-imx		git	git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git#for-next
+clk-renesas	git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#renesas-clk
+clk-samsung	git	git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git#for-next
+csky		git	git://github.com/c-sky/csky-linux.git#linux-next
+loongarch	git	git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git#loongarch-next
+m68k		git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git#for-next
+m68knommu	git	git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git#for-next
+microblaze	git	git://git.monstr.eu/linux-2.6-microblaze.git#next
+mips		git	git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git#mips-next
+nios2		git	git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git#for-next
+openrisc	git	git://github.com/openrisc/linux.git#for-next
+parisc-hd	git	git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git#for-next
+powerpc		git	git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git#next
+soc-fsl		git	git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux.git#next
+risc-v		git	git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git#for-next
+risc-v-mc	git	git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#dt-for-next
+s390		git	git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git#for-next
+sh		git	git://git.libc.org/linux-sh#for-next
+sparc-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next.git#master
+uml		git	git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml.git#linux-next
+xtensa		git	git://github.com/jcmvbkbc/linux-xtensa.git#xtensa-for-next
+pidfd		git	git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git#for-next
+fscrypt		git	git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git#master
+fscache		git	git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#fscache-next
+afs		git	git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#afs-next
+btrfs		git	git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git#for-next
+ceph		git	git://github.com/ceph/ceph-client.git#master
+cifs		git	git://git.samba.org/sfrench/cifs-2.6.git#for-next
+configfs	git	git://git.infradead.org/users/hch/configfs.git#for-next
+ecryptfs	git	git://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs.git#next
+erofs		git	git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git#dev
+exfat		git	git://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/exfat.git#dev
+ext3		git	git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs.git#for_next
+ext4		git	git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git#dev
+f2fs		git	git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git#dev
+fsverity	git	git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git#fsverity
+fuse		git	git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git#for-next
+gfs2		git	git://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux-gfs2.git#for-next
+jfs		git	git://github.com/kleikamp/linux-shaggy.git#jfs-next
+ksmbd		git	https://github.com/smfrench/smb3-kernel.git#ksmbd-for-next
+nfs		git	git://git.linux-nfs.org/projects/trondmy/nfs-2.6.git#linux-next
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+nfsd		git	git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux#for-next
+ntfs3		git	https://github.com/Paragon-Software-Group/linux-ntfs3.git#master
+orangefs	git	git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux#for-next
+overlayfs	git	git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git#overlayfs-next
+ubifs		git	git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git#next
+v9fs		git	git://github.com/martinetd/linux#9p-next
+xfs		git	git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git#for-next
+zonefs		git	git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git#for-next
+iomap		git	git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git#iomap-for-next
+djw-vfs		git	git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git#vfs-for-next
+file-locks	git	git://git.kernel.org/pub/scm/linux/kernel/git/jlayton/linux.git#locks-next
+vfs		git	git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git#for-next
+printk		git	git://git.kernel.org/pub/scm/linux/kernel/git/printk/linux.git#for-next
+pci		git	git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git#next
+pstore		git	git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/pstore
+hid		git	git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git#for-next
+i2c		git	git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git#i2c/for-next
+i3c		git	git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git#i3c/next
+dmi		git	git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging.git#dmi-for-next
+hwmon-staging	git	git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git#hwmon-next
+jc_docs		git	git://git.lwn.net/linux.git#docs-next
+v4l-dvb		git	git://linuxtv.org/media_tree.git#master
+v4l-dvb-next	git	git://linuxtv.org/mchehab/media-next.git#master
+pm		git	git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git#linux-next
+cpufreq-arm	git	git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git#cpufreq/arm/linux-next
+cpupower	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git#cpupower
+devfreq		git	git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git#devfreq-next
+opp		git	git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git#opp/linux-next
+thermal		git	git://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git#thermal/linux-next
+ieee1394	git	git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git#for-next
+dlm		git	git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm.git#next
+rdma		git	git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#for-next
+net-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git#master
+bpf-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git#for-next
+ipsec-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git#master
+mlx5-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git#mlx5-next
+netfilter-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next.git#master
+ipvs-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs-next.git#master
+bluetooth	git	git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git#master
+wireless-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git#for-next
+mtd		git	git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#mtd/next
+nand		git	git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#nand/next
+spi-nor		git	git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#spi-nor/next
+crypto		git	git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git#master
+drm		git	git://git.freedesktop.org/git/drm/drm.git#drm-next
+drm-misc	git	git://anongit.freedesktop.org/drm/drm-misc#for-linux-next
+drm-intel	git	git://anongit.freedesktop.org/drm-intel#for-linux-next
+drm-tegra	git	git://anongit.freedesktop.org/tegra/linux.git#drm/tegra/for-next
+drm-msm		git	https://gitlab.freedesktop.org/drm/msm.git#msm-next
+drm-msm-lumag	git	https://gitlab.freedesktop.org/lumag/msm.git#msm-next-lumag
+imx-drm		git	https://git.pengutronix.de/git/pza/linux#imx-drm/next
+etnaviv		git	https://git.pengutronix.de/git/lst/linux#etnaviv/next
+fbdev		git	git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git#for-next
+regmap		git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-next
+sound		git	git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git#for-next
+sound-asoc	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-next
+modules		git	git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git#modules-next
+input		git	git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git#next
+block		git	git://git.kernel.dk/linux-block.git#for-next
+device-mapper	git	git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git#for-next
+libata		git	git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata.git#for-next
+pcmcia		git	git://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git#pcmcia-next
+mmc		git	git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#next
+mfd		git	git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-next
+backlight	git	git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git#for-backlight-next
+battery		git	git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#for-next
+regulator	git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-next
+security	git	git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git#next-testing
+apparmor	git	git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor#apparmor-next
+integrity	git	git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity#next-integrity
+keys		git	git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#keys-next
+safesetid	git	https://github.com/micah-morton/linux.git#safesetid-next
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+smack		git	git://github.com/cschaufler/smack-next#next
+tomoyo		git	https://scm.osdn.net/gitroot/tomoyo/tomoyo-test1.git#master
+tpmdd		git	git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git#next
+watchdog	git	git://www.linux-watchdog.org/linux-watchdog-next.git#master
+iommu		git	git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git#next
+audit		git	git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit.git#next
+devicetree	git	git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
+dt-krzk		git	git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git#for-next
+mailbox		git	git://git.linaro.org/landing-teams/working/fujitsu/integration.git#mailbox-for-next
+spi		git	git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-next
+tip		git	git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#master
+clockevents	git	git://git.linaro.org/people/daniel.lezcano/linux.git#timers/drivers/next
+edac		git	git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git#edac-for-next
+irqchip		git	git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git#irq/irqchip-next
+ftrace		git	git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git#for-next
+rcu		git	git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git#rcu/next
+kvm		git	git://git.kernel.org/pub/scm/virt/kvm/kvm.git#next
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+chrome-platform	git	git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git#for-next
+hsi		git	git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git#for-next
+leds		git	git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git#for-next
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+pinctrl-renesas	git	git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#renesas-pinctrl
+pinctrl-samsung	git	git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git#for-next
+pwm		git	git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git#for-next
+userns		git	git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git#for-next
+ktest		git	git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-ktest.git#for-next
+kselftest	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#next
+livepatching	git	git://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching#for-next
+rtc		git	git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git#rtc-next
+nvdimm		git	git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git#libnvdimm-for-next
+at24		git	git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#at24/for-next
+ntb		git	https://github.com/jonmason/ntb.git#ntb-next
+seccomp		git	git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/seccomp
+cisco		git	https://github.com/daniel-walker/cisco-linux.git#for-next
+fsi		git	git://git.kernel.org/pub/scm/linux/kernel/git/joel/fsi.git#next
+slimbus		git	git://git.kernel.org/pub/scm/linux/kernel/git/srini/slimbus.git#for-next
+nvmem		git	git://git.kernel.org/pub/scm/linux/kernel/git/srini/nvmem.git#for-next
+xarray		git	git://git.infradead.org/users/willy/xarray.git#main
+hyperv		git	git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git#hyperv-next
+auxdisplay	git	https://github.com/ojeda/linux.git#auxdisplay
+kgdb		git	git://git.kernel.org/pub/scm/linux/kernel/git/danielt/linux.git#kgdb/for-next
+hmm		git	git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#hmm
+kunit		git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#test
+cfi		git	git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#cfi/next
+kunit-next	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#kunit
+trivial		git	git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial.git#for-next
+mhi		git	git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi.git#mhi-next
+memblock	git	git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git#for-next
+init		git	git://git.infradead.org/users/hch/misc.git#init-user-pointers
+counters	git	git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git#counters
+cxl		git	git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git#next
+folio-iomap	git	git://git.infradead.org/users/willy/linux.git#folio-iomap
+zstd		git	https://github.com/terrelln/linux.git#zstd-next
+efi		git	git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git#next
+unicode		git	git://git.kernel.org/pub/scm/linux/kernel/git/krisman/unicode.git#for-next
+slab		git	git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git#for-next
+random		git	git://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git#master
+landlock	git	git://git.kernel.org/pub/scm/linux/kernel/git/mic/linux.git#next
+rust		git	https://github.com/Rust-for-Linux/linux.git#rust-next
+sysctl		git	git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git#sysctl-next
+folio		git	git://git.infradead.org/users/willy/pagecache.git#for-next
+execve		git	git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/execve
+bitmap		git	https://github.com/norov/linux.git#bitmap-for-next
+hte		git	git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git#hte/for-next
+kspp		git	git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/kspp
+kspp-gustavo	git	git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git#for-next/kspp
+mm-stable	git	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-stable
+mm-nonmm-stable	git	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-nonmm-stable
+mm		git	git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-everything
+amdgpu		git	https://gitlab.freedesktop.org/agd5f/linux#drm-next
+akpm		mmotm	https://www.ozlabs.org/~akpm/mmotm/
diff --git a/Next/merge.log b/Next/merge.log
new file mode 100644
index 000000000000..8a047d19c4f8
--- /dev/null
+++ b/Next/merge.log
@@ -0,0 +1,8327 @@
+$ date -R
+Thu, 23 Jun 2022 08:59:15 +1000
+$ git checkout master
+Already on 'master'
+$ git reset --hard stable
+HEAD is now at ca1fdab7fd27 Merge tag 'efi-urgent-for-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi
+Merging origin/master (de5c208d533a Merge tag 'linux-kselftest-fixes-5.19-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git origin/master
+Updating ca1fdab7fd27..de5c208d533a
+Fast-forward (no commit created; -m option ignored)
+ fs/9p/fid.c                                     | 22 +++++++++-------------
+ fs/9p/vfs_addr.c                                | 13 +++++++++++++
+ fs/9p/vfs_inode.c                               |  8 ++++----
+ fs/9p/vfs_inode_dotl.c                          |  3 +++
+ tools/testing/selftests/dma/Makefile            |  1 +
+ tools/testing/selftests/dma/dma_map_benchmark.c |  2 +-
+ tools/testing/selftests/lib.mk                  | 25 +++++++++++++++++++++++--
+ tools/testing/selftests/vm/gup_test.c           |  4 ++--
+ tools/testing/selftests/vm/ksm_tests.c          |  2 ++
+ 9 files changed, 58 insertions(+), 22 deletions(-)
+Merging fixes/fixes (d06c942efea4 Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/sfr/next-fixes.git fixes/fixes
+Already up to date.
+Merging mm-hotfixes/mm-hotfixes-unstable (d18fe3d3a891 Documentation: highmem: use literal block for code example in highmem.h comment)
+$ git merge -m Merge branch 'mm-hotfixes-unstable' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-hotfixes/mm-hotfixes-unstable
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .mailmap                      |  4 +++
+ Documentation/vm/hwpoison.rst |  3 +-
+ MAINTAINERS                   | 21 ++++++++++---
+ arch/sh/include/asm/io.h      |  8 +++--
+ drivers/base/memory.c         |  2 +-
+ fs/hugetlbfs/inode.c          | 68 +++++++++++++++++++++++++++++++++----------
+ include/linux/highmem.h       | 18 ++++++------
+ include/linux/mm.h            |  3 +-
+ kernel/kthread.c              | 14 ++++-----
+ mm/damon/reclaim.c            |  8 +++++
+ mm/damon/vaddr.c              |  3 +-
+ mm/hwpoison-inject.c          |  2 +-
+ mm/kfence/core.c              |  7 +++--
+ mm/madvise.c                  |  2 +-
+ mm/memcontrol.c               |  2 +-
+ mm/memory-failure.c           | 12 ++++++++
+ mm/page_isolation.c           |  2 ++
+ mm/sparse-vmemmap.c           |  8 +++++
+ mm/swap.c                     |  2 +-
+ mm/userfaultfd.c              |  5 +++-
+ 20 files changed, 145 insertions(+), 49 deletions(-)
+Merging kbuild-current/fixes (291810be4227 Documentation/llvm: Update Supported Arch table)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kbuild-current/fixes
+Merge made by the 'ort' strategy.
+ Documentation/kbuild/llvm.rst | 10 ++++++++--
+ scripts/mod/modpost.c         |  2 +-
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+Merging arc-current/for-curr (f978e8023f33 ARC: bitops: Change __fls to return unsigned long)
+$ git merge -m Merge branch 'for-curr' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git arc-current/for-curr
+Merge made by the 'ort' strategy.
+ arch/arc/include/asm/bitops.h | 4 ++--
+ arch/arc/kernel/smp.c         | 2 +-
+ arch/arc/mm/cache.c           | 4 ++--
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+Merging arm-current/fixes (3cfb30199796 ARM: 9197/1: spectre-bhb: fix loop8 sequence for Thumb2)
+$ git merge -m Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm.git arm-current/fixes
+Already up to date.
+Merging arm64-fixes/for-next/fixes (c50f11c6196f arm64: mm: Don't invalidate FROM_DEVICE buffers at start of DMA transfer)
+$ git merge -m Merge branch 'for-next/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux arm64-fixes/for-next/fixes
+Already up to date.
+Merging arm-soc-fixes/arm/fixes (5e93207e962a bus: bt1-axi: Don't print error on -EPROBE_DEFER)
+$ git merge -m Merge branch 'arm/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git arm-soc-fixes/arm/fixes
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS                                |  5 ++-
+ arch/arm/boot/dts/imx6qdl-colibri.dtsi     |  2 +-
+ arch/arm/boot/dts/imx6qdl.dtsi             |  2 +-
+ arch/arm/boot/dts/imx7s.dtsi               |  2 +-
+ arch/arm/boot/dts/stm32mp15-scmi.dtsi      | 47 +++++++++++++++++++++
+ arch/arm/boot/dts/stm32mp151.dtsi          | 41 ------------------
+ arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 13 +-----
+ arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 13 +-----
+ arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 13 +-----
+ arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 13 +-----
+ arch/arm/mach-axxia/platsmp.c              |  1 +
+ arch/arm64/boot/dts/freescale/s32g2.dtsi   |  2 +-
+ drivers/bus/bt1-apb.c                      | 14 +++---
+ drivers/bus/bt1-axi.c                      | 14 +++---
+ drivers/firmware/arm_scmi/base.c           | 24 +++++++----
+ drivers/firmware/arm_scmi/clock.c          |  7 ++-
+ drivers/firmware/arm_scmi/perf.c           |  6 +--
+ drivers/firmware/arm_scmi/power.c          |  2 +-
+ drivers/firmware/arm_scmi/protocols.h      |  2 -
+ drivers/firmware/arm_scmi/reset.c          |  2 +-
+ drivers/firmware/arm_scmi/sensors.c        | 68 +++++++++++++++++++++++-------
+ drivers/firmware/arm_scmi/voltage.c        | 15 +++----
+ drivers/soc/bcm/brcmstb/pm/pm-arm.c        |  1 +
+ drivers/soc/imx/imx8m-blk-ctrl.c           |  2 +-
+ include/linux/scmi_protocol.h              |  9 ++--
+ 25 files changed, 158 insertions(+), 162 deletions(-)
+ create mode 100644 arch/arm/boot/dts/stm32mp15-scmi.dtsi
+Merging drivers-memory-fixes/fixes (1332661e0930 memory: samsung: exynos5422-dmc: Fix refcount leak in of_get_dram_timings)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git drivers-memory-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/memory/Kconfig                  |  1 +
+ drivers/memory/mtk-smi.c                |  5 ++++-
+ drivers/memory/samsung/exynos5422-dmc.c | 29 ++++++++++++++++++-----------
+ 3 files changed, 23 insertions(+), 12 deletions(-)
+Merging tee-fixes/fixes (98268f2a2a9f Merge branch 'optee_ffa_probe_fix_for_v5.18' into fixes)
+$ git merge -m Merge branch 'fixes' of https://git.linaro.org/people/jens.wiklander/linux-tee.git tee-fixes/fixes
+Merge made by the 'ort' strategy.
+Merging m68k-current/for-linus (30b5e6ef4a32 m68k: atari: Make Atari ROM port I/O write macros return void)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git m68k-current/for-linus
+Already up to date.
+Merging powerpc-fixes/fixes (f3eac426657d powerpc/powernv: wire up rng during setup_arch)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git powerpc-fixes/fixes
+Merge made by the 'ort' strategy.
+ arch/powerpc/kernel/process.c                |  2 +-
+ arch/powerpc/kernel/prom_init.c              |  2 +-
+ arch/powerpc/kernel/rtas.c                   | 11 +++++-
+ arch/powerpc/kernel/setup-common.c           | 13 +++----
+ arch/powerpc/platforms/microwatt/microwatt.h |  7 ++++
+ arch/powerpc/platforms/microwatt/rng.c       | 10 ++----
+ arch/powerpc/platforms/microwatt/setup.c     |  8 +++++
+ arch/powerpc/platforms/powernv/powernv.h     |  2 ++
+ arch/powerpc/platforms/powernv/rng.c         | 52 +++++++++++++++++++---------
+ arch/powerpc/platforms/powernv/setup.c       |  2 ++
+ arch/powerpc/platforms/pseries/pseries.h     |  2 ++
+ arch/powerpc/platforms/pseries/rng.c         | 11 ++----
+ arch/powerpc/platforms/pseries/setup.c       |  1 +
+ 13 files changed, 83 insertions(+), 40 deletions(-)
+ create mode 100644 arch/powerpc/platforms/microwatt/microwatt.h
+Merging s390-fixes/fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git s390-fixes/fixes
+Already up to date.
+Merging sparc/master (05a59d79793d Merge git://git.kernel.org:/pub/scm/linux/kernel/git/netdev/net)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc.git sparc/master
+Already up to date.
+Merging fscrypt-current/for-stable (80f6e3080bfc fs-verity: fix signed integer overflow with i_size near S64_MAX)
+$ git merge -m Merge branch 'for-stable' of git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git fscrypt-current/for-stable
+Already up to date.
+Merging net/master (1e70212e0315 hinic: Replace memcpy() with direct assignment)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git net/master
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS                                        | 41 ++++++------
+ arch/x86/net/bpf_jit_comp.c                        |  3 +-
+ drivers/net/bonding/bond_main.c                    |  4 +-
+ drivers/net/ethernet/huawei/hinic/hinic_devlink.c  |  4 +-
+ drivers/net/ethernet/intel/igb/igb_main.c          |  7 +-
+ drivers/net/hamradio/6pack.c                       |  9 ++-
+ drivers/net/phy/aquantia_main.c                    | 15 ++++-
+ drivers/net/phy/at803x.c                           |  6 ++
+ drivers/net/phy/smsc.c                             |  6 +-
+ drivers/net/veth.c                                 |  4 ++
+ kernel/bpf/btf.c                                   |  5 ++
+ kernel/trace/bpf_trace.c                           | 60 ++++++++++++-----
+ kernel/trace/ftrace.c                              | 13 +++-
+ kernel/trace/rethook.c                             |  9 +++
+ net/core/dev.c                                     | 25 ++++---
+ net/core/filter.c                                  | 34 ++++++++--
+ net/core/net-sysfs.c                               |  1 +
+ net/ethtool/eeprom.c                               |  2 +-
+ net/ipv4/ip_gre.c                                  | 15 +++--
+ net/ipv4/ping.c                                    | 10 ++-
+ net/ipv6/ip6_gre.c                                 | 15 +++--
+ net/netfilter/nf_dup_netdev.c                      | 25 +++++--
+ net/netfilter/nfnetlink_cttimeout.c                |  2 +-
+ net/netfilter/nft_meta.c                           | 13 +---
+ net/netfilter/nft_numgen.c                         | 12 +---
+ net/sched/sch_netem.c                              |  4 +-
+ net/tipc/core.c                                    |  3 +-
+ net/tls/tls_main.c                                 |  3 +
+ net/xdp/xsk.c                                      | 16 +++--
+ samples/fprobe/fprobe_example.c                    | 29 ++++++--
+ .../testing/selftests/bpf/prog_tests/bpf_cookie.c  | 78 +++++++++++-----------
+ .../selftests/bpf/prog_tests/kprobe_multi_test.c   |  3 +
+ tools/testing/selftests/bpf/prog_tests/tailcalls.c | 55 +++++++++++++++
+ tools/testing/selftests/bpf/progs/kprobe_multi.c   | 24 +++----
+ .../selftests/bpf/progs/tailcall_bpf2bpf6.c        | 42 ++++++++++++
+ tools/testing/selftests/net/fcnal-test.sh          | 61 +++++++++++++++--
+ .../selftests/netfilter/nft_concat_range.sh        |  2 +-
+ 37 files changed, 484 insertions(+), 176 deletions(-)
+ create mode 100644 tools/testing/selftests/bpf/progs/tailcall_bpf2bpf6.c
+Merging bpf/master (a2b1a5d40bd1 net/sched: sch_netem: Fix arithmetic in netem_dump() for 32-bit platforms)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git bpf/master
+Already up to date.
+Merging ipsec/master (f85daf0e7253 xfrm: xfrm_policy: fix a possible double xfrm_pols_put() in xfrm_bundle_lookup())
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git ipsec/master
+Merge made by the 'ort' strategy.
+ net/xfrm/xfrm_policy.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+Merging netfilter/master (7fb0269720d7 Merge tag 'for-net-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf.git netfilter/master
+Already up to date.
+Merging ipvs/master (7fb0269720d7 Merge tag 'for-net-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs.git ipvs/master
+Already up to date.
+Merging wireless/for-next (c2b3a0759c76 dt-bindings: net: wireless: ath11k: change Kalle's email)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless.git wireless/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/net/wireless/qca,ath9k.yaml        |  2 +-
+ .../devicetree/bindings/net/wireless/qcom,ath11k.yaml      |  2 +-
+ drivers/net/wireless/realtek/rtw88/main.h                  |  6 +++---
+ drivers/net/wireless/realtek/rtw88/rtw8821c.c              | 14 ++++++++------
+ 4 files changed, 13 insertions(+), 11 deletions(-)
+Merging rdma-fixes/for-rc (118f767413ad RDMA/qedr: Fix reporting QP timeout attribute)
+$ git merge -m Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git rdma-fixes/for-rc
+Merge made by the 'ort' strategy.
+ drivers/infiniband/hw/qedr/qedr.h  | 1 +
+ drivers/infiniband/hw/qedr/verbs.c | 4 +++-
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+Merging sound-current/for-linus (627ce0d68eb4 ALSA: hda/realtek: Add quirk for Clevo NS50PU)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git sound-current/for-linus
+Merge made by the 'ort' strategy.
+ drivers/firewire/core-cdev.c    |  2 +-
+ drivers/firewire/core-device.c  |  6 ++----
+ sound/core/memalloc.c           | 23 +----------------------
+ sound/hda/hdac_i915.c           | 15 ++++++---------
+ sound/hda/intel-dsp-config.c    | 12 ++++++++++++
+ sound/hda/intel-nhlt.c          | 17 ++++++++---------
+ sound/pci/hda/hda_auto_parser.c |  7 ++++---
+ sound/pci/hda/hda_local.h       |  1 +
+ sound/pci/hda/patch_conexant.c  |  4 ++--
+ sound/pci/hda/patch_realtek.c   | 36 +++++++++++++++++++++++++++++++++++-
+ sound/pci/hda/patch_via.c       |  4 ++--
+ sound/usb/mixer_us16x08.c       |  6 +++---
+ sound/x86/intel_hdmi_audio.c    | 15 +++++++++++++--
+ 13 files changed, 90 insertions(+), 58 deletions(-)
+Merging sound-asoc-fixes/for-linus (8966a2d8ebef Merge remote-tracking branch 'asoc/for-5.18' into asoc-linus)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git sound-asoc-fixes/for-linus
+Auto-merging MAINTAINERS
+Auto-merging sound/soc/codecs/wm_adsp.c
+Merge made by the 'ort' strategy.
+ MAINTAINERS                            |  11 ++-
+ drivers/base/regmap/regmap.c           |  15 ++--
+ include/sound/soc.h                    |   2 -
+ sound/soc/codecs/ak4613.c              |   6 +-
+ sound/soc/codecs/cs35l41.c             |  12 +--
+ sound/soc/codecs/max98373-sdw.c        |  12 ++-
+ sound/soc/codecs/rt1308-sdw.c          |  11 +++
+ sound/soc/codecs/rt1316-sdw.c          |  11 +++
+ sound/soc/codecs/rt5682-sdw.c          |   5 +-
+ sound/soc/codecs/rt700-sdw.c           |   6 +-
+ sound/soc/codecs/rt700.c               |  30 ++++---
+ sound/soc/codecs/rt711-sdca-sdw.c      |   9 +-
+ sound/soc/codecs/rt711-sdca.c          |  44 +++++----
+ sound/soc/codecs/rt711-sdw.c           |   9 +-
+ sound/soc/codecs/rt711.c               |  40 ++++-----
+ sound/soc/codecs/rt715-sdca-sdw.c      |  12 +++
+ sound/soc/codecs/rt715-sdw.c           |  12 +++
+ sound/soc/codecs/tlv320adc3xxx.c       |   3 +
+ sound/soc/codecs/wcd9335.c             |   8 +-
+ sound/soc/codecs/wcd938x.c             |  12 +++
+ sound/soc/codecs/wm5110.c              |   8 +-
+ sound/soc/codecs/wm_adsp.c             |   2 +-
+ sound/soc/fsl/fsl_micfil.c             |  19 ++++
+ sound/soc/intel/avs/topology.c         |   4 +-
+ sound/soc/intel/boards/bytcr_wm5102.c  |  13 ++-
+ sound/soc/intel/boards/sof_sdw.c       |  51 ++++++-----
+ sound/soc/qcom/qdsp6/q6apm-dai.c       |   6 ++
+ sound/soc/rockchip/rockchip_i2s.c      | 160 ++++++++++++++++++++++++++-------
+ sound/soc/soc-ops.c                    |  12 ++-
+ sound/soc/sof/intel/hda-dsp.c          |  10 ++-
+ sound/soc/sof/intel/hda-loader.c       |  13 +--
+ sound/soc/sof/intel/hda-pcm.c          |  74 +--------------
+ sound/soc/sof/intel/hda-stream.c       |  94 ++++++++++++++++++-
+ sound/soc/sof/intel/hda.h              |   4 +
+ sound/soc/sof/ipc3-topology.c          |  23 +++--
+ sound/soc/sof/mediatek/mt8186/mt8186.c |   2 +-
+ sound/soc/sof/pm.c                     |  21 ++++-
+ sound/soc/sof/sof-priv.h               |   2 +
+ 38 files changed, 547 insertions(+), 241 deletions(-)
+Merging regmap-fixes/for-linus (3f05010f243b regmap-irq: Fix offset/index mismatch in read_sub_irq_data())
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git regmap-fixes/for-linus
+Merge made by the 'ort' strategy.
+ drivers/base/regmap/regmap-irq.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+Merging regulator-fixes/for-linus (122e951eb804 regulator: qcom_smd: correct MP5496 ranges)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git regulator-fixes/for-linus
+Merge made by the 'ort' strategy.
+ drivers/regulator/qcom_smd-regulator.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+Merging spi-fixes/for-linus (419bc8f681a0 spi: rockchip: Unmask IRQ at the final to avoid preemption)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git spi-fixes/for-linus
+Merge made by the 'ort' strategy.
+ .../bindings/spi/microchip,mpfs-spi.yaml           |  1 -
+ .../bindings/spi/qcom,spi-geni-qcom.yaml           |  1 -
+ drivers/spi/spi-cadence.c                          | 37 ++++++++++++++++++----
+ drivers/spi/spi-mem.c                              |  2 +-
+ drivers/spi/spi-rockchip.c                         | 11 ++++---
+ 5 files changed, 39 insertions(+), 13 deletions(-)
+Merging pci-current/for-linus (a2b36ffbf5b6 x86/PCI: Revert "x86/PCI: Clip only host bridge windows for E820 regions")
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci-current/for-linus
+Already up to date.
+Merging driver-core.current/driver-core-linus (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'driver-core-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git driver-core.current/driver-core-linus
+Already up to date.
+Merging tty.current/tty-linus (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'tty-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty.current/tty-linus
+Already up to date.
+Merging usb.current/usb-linus (9ef165406308 usb: typec: wcove: Drop wrong dependency to INTEL_SOC_PMIC)
+$ git merge -m Merge branch 'usb-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb.current/usb-linus
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/usb/generic-ehci.yaml      |  3 +-
+ .../devicetree/bindings/usb/generic-ohci.yaml      |  3 +-
+ MAINTAINERS                                        |  1 +
+ drivers/usb/gadget/function/uvc_video.c            |  3 ++
+ drivers/usb/gadget/legacy/raw_gadget.c             | 62 ++++++++++++++++------
+ drivers/usb/typec/tcpm/Kconfig                     |  1 -
+ 6 files changed, 54 insertions(+), 19 deletions(-)
+Merging usb-gadget-fixes/fixes (e49d033bddf5 Linux 5.12-rc6)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git usb-gadget-fixes/fixes
+Already up to date.
+Merging usb-serial-fixes/usb-linus (33b29dbb39bc USB: serial: option: add Quectel EM05-G modem)
+$ git merge -m Merge branch 'usb-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git usb-serial-fixes/usb-linus
+Merge made by the 'ort' strategy.
+ drivers/usb/serial/option.c |  4 ++++
+ drivers/usb/serial/pl2303.c | 29 +++++++++++++++++------------
+ 2 files changed, 21 insertions(+), 12 deletions(-)
+Merging phy/fixes (9293ee00cc1c phy: ti: tusb1210: Don't check for write errors when powering on)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git phy/fixes
+Merge made by the 'ort' strategy.
+ drivers/phy/ti/phy-tusb1210.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+Merging staging.current/staging-linus (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'staging-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git staging.current/staging-linus
+Already up to date.
+Merging iio-fixes/fixes-togreg (315f7e15c261 Merge tag 'iio-fixes-for-5.19a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next)
+$ git merge -m Merge branch 'fixes-togreg' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git iio-fixes/fixes-togreg
+Merge made by the 'ort' strategy.
+ Documentation/ABI/testing/sysfs-bus-iio-vf610    |  2 +-
+ drivers/iio/accel/bma180.c                       |  3 +-
+ drivers/iio/accel/kxcjk-1013.c                   |  4 +--
+ drivers/iio/accel/mma8452.c                      | 22 +++++++++-----
+ drivers/iio/accel/mxc4005.c                      |  4 +--
+ drivers/iio/adc/adi-axi-adc.c                    |  3 ++
+ drivers/iio/adc/aspeed_adc.c                     |  1 +
+ drivers/iio/adc/axp288_adc.c                     |  8 +++++
+ drivers/iio/adc/rzg2l_adc.c                      |  8 +++--
+ drivers/iio/adc/stm32-adc-core.c                 |  9 ++++--
+ drivers/iio/adc/stm32-adc.c                      | 37 +++++++++++-------------
+ drivers/iio/adc/ti-ads131e08.c                   | 10 +++++--
+ drivers/iio/adc/xilinx-ams.c                     |  2 +-
+ drivers/iio/afe/iio-rescale.c                    |  2 +-
+ drivers/iio/chemical/ccs811.c                    |  4 +--
+ drivers/iio/frequency/admv1014.c                 |  6 ++--
+ drivers/iio/gyro/mpu3050-core.c                  |  1 +
+ drivers/iio/humidity/hts221_buffer.c             |  5 +++-
+ drivers/iio/imu/inv_icm42600/inv_icm42600.h      |  1 +
+ drivers/iio/imu/inv_icm42600/inv_icm42600_core.c |  2 +-
+ drivers/iio/magnetometer/yamaha-yas530.c         |  2 +-
+ drivers/iio/proximity/sx9324.c                   |  3 ++
+ drivers/iio/test/Kconfig                         |  2 +-
+ drivers/iio/test/Makefile                        |  2 +-
+ drivers/iio/trigger/iio-trig-sysfs.c             |  1 +
+ 25 files changed, 92 insertions(+), 52 deletions(-)
+Merging counter-fixes/fixes-togreg (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes-togreg' of https://gitlab.com/vilhelmgray/counter.git counter-fixes/fixes-togreg
+Already up to date.
+Merging char-misc.current/char-misc-linus (315f7e15c261 Merge tag 'iio-fixes-for-5.19a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next)
+$ git merge -m Merge branch 'char-misc-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git char-misc.current/char-misc-linus
+Already up to date.
+Merging soundwire-fixes/fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git soundwire-fixes/fixes
+Already up to date.
+Merging thunderbolt-fixes/fixes (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git thunderbolt-fixes/fixes
+Already up to date.
+Merging input-current/for-linus (6ab2e51898cd Input: soc_button_array - also add Lenovo Yoga Tablet2 1051F to dmi_use_low_level_irq)
+$ git merge -m Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git input-current/for-linus
+Already up to date.
+Merging crypto-current/master (abfed87e2a12 crypto: memneq - move into lib/)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git crypto-current/master
+Already up to date.
+Merging vfio-fixes/for-linus (1ef3342a934e vfio/pci: Fix vf_token mechanism when device-specific VF drivers are used)
+$ git merge -m Merge branch 'for-linus' of git://github.com/awilliam/linux-vfio.git vfio-fixes/for-linus
+Already up to date.
+Merging kselftest-fixes/fixes (9b4d5c01eb23 selftests: make use of GUP_TEST_FILE macro)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kselftest-fixes/fixes
+Already up to date.
+Merging modules-fixes/modules-linus (7390b94a3c2d module: merge check_exported_symbol() into find_exported_symbol_in_section())
+$ git merge -m Merge branch 'modules-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git modules-fixes/modules-linus
+Already up to date.
+Merging dmaengine-fixes/fixes (a7cd3cf0b2e5 dmaengine: imx-sdma: Allow imx8m for imx7 FW revs)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git dmaengine-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/dma/dmatest.c         | 13 +++----------
+ drivers/dma/imx-sdma.c        |  2 +-
+ drivers/dma/ti/dma-crossbar.c |  5 +++++
+ 3 files changed, 9 insertions(+), 11 deletions(-)
+Merging backlight-fixes/for-backlight-fixes (a38fd8748464 Linux 5.12-rc2)
+$ git merge -m Merge branch 'for-backlight-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git backlight-fixes/for-backlight-fixes
+Already up to date.
+Merging mtd-fixes/mtd/fixes (06781a502635 mtd: rawnand: gpmi: Fix setting busy timeout setting)
+$ git merge -m Merge branch 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd-fixes/mtd/fixes
+Merge made by the 'ort' strategy.
+ drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 2 +-
+ drivers/mtd/nand/raw/nand_ids.c            | 3 ---
+ 2 files changed, 1 insertion(+), 4 deletions(-)
+Merging mfd-fixes/for-mfd-fixes (a61f4661fba4 mfd: intel_quark_i2c_gpio: Revert "Constify static struct resources")
+$ git merge -m Merge branch 'for-mfd-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git mfd-fixes/for-mfd-fixes
+Already up to date.
+Merging v4l-dvb-fixes/fixes (d3daf73380ce media: dvb_vb2: fix possible out of bound access)
+$ git merge -m Merge branch 'fixes' of git://linuxtv.org/mchehab/media-next.git v4l-dvb-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/media/dvb-core/dvb_vb2.c              | 11 +++++++++++
+ drivers/media/i2c/Kconfig                     |  1 +
+ drivers/media/v4l2-core/v4l2-compat-ioctl32.c |  2 ++
+ drivers/media/v4l2-core/v4l2-ioctl.c          | 26 ++++++++++++--------------
+ 4 files changed, 26 insertions(+), 14 deletions(-)
+Merging reset-fixes/reset/fixes (03cb66463b55 dt-bindings: reset: Add parent "resets" property as optional)
+$ git merge -m Merge branch 'reset/fixes' of https://git.pengutronix.de/git/pza/linux reset-fixes/reset/fixes
+Already up to date.
+Merging mips-fixes/mips-fixes (3748d2185ac4 mips: lantiq: Add missing of_node_put() in irq.c)
+$ git merge -m Merge branch 'mips-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git mips-fixes/mips-fixes
+Merge made by the 'ort' strategy.
+ arch/mips/boot/dts/ingenic/x1000.dtsi | 5 +++--
+ arch/mips/boot/dts/ingenic/x1830.dtsi | 5 +++--
+ arch/mips/generic/board-ranchu.c      | 1 +
+ arch/mips/lantiq/falcon/sysctrl.c     | 6 ++++++
+ arch/mips/lantiq/irq.c                | 1 +
+ arch/mips/lantiq/xway/sysctrl.c       | 4 ++++
+ arch/mips/mti-malta/malta-time.c      | 2 ++
+ arch/mips/pic32/pic32mzda/init.c      | 7 ++++++-
+ arch/mips/pic32/pic32mzda/time.c      | 3 +++
+ arch/mips/ralink/of.c                 | 2 ++
+ arch/mips/vr41xx/common/icu.c         | 2 --
+ drivers/gpio/gpio-vr41xx.c            | 2 --
+ 12 files changed, 31 insertions(+), 9 deletions(-)
+Merging at91-fixes/at91-fixes (0c640d9544d0 ARM: dts: at91: fix pinctrl phandles)
+$ git merge -m Merge branch 'at91-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git at91-fixes/at91-fixes
+Already up to date.
+Merging omap-fixes/fixes (46ff3df87215 ARM: dts: logicpd-som-lv: Fix wrong pinmuxing on OMAP35)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git omap-fixes/fixes
+Already up to date.
+Merging kvm-fixes/master (e0f3f46e4206 KVM: selftests: Restrict test region to 48-bit physical addresses when using nested)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git kvm-fixes/master
+Already up to date.
+Merging kvms390-fixes/master (242c04f01377 KVM: s390: selftests: Use TAP interface in the reset test)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git kvms390-fixes/master
+Auto-merging arch/x86/kvm/vmx/vmx.c
+Auto-merging arch/x86/kvm/x86.c
+Auto-merging virt/kvm/kvm_main.c
+Merge made by the 'ort' strategy.
+ arch/x86/kvm/vmx/vmx.c                             |   8 +-
+ arch/x86/kvm/x86.c                                 |   7 +-
+ include/linux/kvm_types.h                          |   2 +
+ tools/testing/selftests/kvm/s390x/memop.c          |  95 +++++++--
+ tools/testing/selftests/kvm/s390x/resets.c         |  38 +++-
+ tools/testing/selftests/kvm/s390x/sync_regs_test.c |  87 ++++++--
+ tools/testing/selftests/kvm/s390x/tprot.c          |  29 ++-
+ virt/kvm/kvm_main.c                                |   9 +
+ virt/kvm/pfncache.c                                | 231 +++++++++++++--------
+ 9 files changed, 368 insertions(+), 138 deletions(-)
+Merging hwmon-fixes/hwmon (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'hwmon' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-fixes/hwmon
+Already up to date.
+Merging nvdimm-fixes/libnvdimm-fixes (d28820419ca3 cxl/pci: Drop shadowed variable)
+$ git merge -m Merge branch 'libnvdimm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git nvdimm-fixes/libnvdimm-fixes
+Already up to date.
+Merging cxl-fixes/fixes (fae8817ae804 cxl/mem: Fix memory device capacity probing)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl-fixes/fixes
+Already up to date.
+Merging btrfs-fixes/next-fixes (5f414c4e30de Merge branch 'misc-5.19' into next-fixes)
+$ git merge -m Merge branch 'next-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git btrfs-fixes/next-fixes
+Merge made by the 'ort' strategy.
+Merging vfs-fixes/fixes (1c7c0f168f97 fix short copy handling in copy_mc_pipe_to_iter())
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git vfs-fixes/fixes
+Merge made by the 'ort' strategy.
+ include/linux/pipe_fs_i.h |  9 +++++++++
+ lib/iov_iter.c            | 15 +++++++++++----
+ 2 files changed, 20 insertions(+), 4 deletions(-)
+Merging dma-mapping-fixes/for-linus (18a3c5f7abfd Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost)
+$ git merge -m Merge branch 'for-linus' of git://git.infradead.org/users/hch/dma-mapping.git dma-mapping-fixes/for-linus
+Already up to date.
+Merging i3c-fixes/i3c/fixes (fe07bfda2fb9 Linux 5.12-rc1)
+$ git merge -m Merge branch 'i3c/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git i3c-fixes/i3c/fixes
+Already up to date.
+Merging drivers-x86-fixes/fixes (4ef3824db96f platform/x86: thinkpad_acpi: Fix a memory leak of EFCH MMIO resource)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git drivers-x86-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/platform/mellanox/nvsw-sn2201.c | 4 +++-
+ drivers/platform/x86/intel/pmc/core.c   | 1 +
+ drivers/platform/x86/thinkpad_acpi.c    | 1 +
+ 3 files changed, 5 insertions(+), 1 deletion(-)
+Merging samsung-krzk-fixes/fixes (c4c79525042a ARM: exynos: Fix refcount leak in exynos_map_pmu)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git samsung-krzk-fixes/fixes
+Merge made by the 'ort' strategy.
+ arch/arm/mach-exynos/exynos.c              |  1 +
+ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
+ 2 files changed, 7 insertions(+), 6 deletions(-)
+Merging pinctrl-samsung-fixes/fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git pinctrl-samsung-fixes/fixes
+Already up to date.
+Merging devicetree-fixes/dt/linus (0b9431c8221c dt-bindings: display: arm,malidp: remove bogus RQOS property)
+$ git merge -m Merge branch 'dt/linus' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git devicetree-fixes/dt/linus
+Already up to date.
+Merging dt-krzk-fixes/fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git dt-krzk-fixes/fixes
+Already up to date.
+Merging scsi-fixes/fixes (aeaadcde1a60 scsi: ibmvfc: Store vhost pointer during subcrq allocation)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git scsi-fixes/fixes
+Already up to date.
+Merging drm-fixes/drm-fixes (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'drm-fixes' of git://git.freedesktop.org/git/drm/drm.git drm-fixes/drm-fixes
+Already up to date.
+Merging amdgpu-fixes/drm-fixes (2c409ba81be2 drm/radeon: fix si_enable_smc_cac() failed issue)
+$ git merge -m Merge branch 'drm-fixes' of git://people.freedesktop.org/~agd5f/linux amdgpu-fixes/drm-fixes
+Already up to date.
+Merging drm-intel-fixes/for-linux-next-fixes (c7b28f52f406 drm/i915/display: Re-add check for low voltage sku for max dp source rate)
+$ git merge -m Merge branch 'for-linux-next-fixes' of git://anongit.freedesktop.org/drm-intel drm-intel-fixes/for-linux-next-fixes
+Merge made by the 'ort' strategy.
+ drivers/gpu/drm/i915/display/intel_dp.c       | 32 ++++++++++++++++++++++++---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  4 ++--
+ drivers/gpu/drm/i915/i915_drm_client.c        |  5 +++--
+ 3 files changed, 34 insertions(+), 7 deletions(-)
+Merging mmc-fixes/fixes (89bcd9a64b84 mmc: mediatek: wait dma stop bit reset to 0)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git mmc-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/mmc/host/mtk-sd.c            | 20 ++++++++++++--------
+ drivers/mmc/host/sdhci-pci-o2micro.c |  2 ++
+ 2 files changed, 14 insertions(+), 8 deletions(-)
+Merging rtc-fixes/rtc-fixes (bd33335aa93d rtc: cmos: Disable irq around direct invocation of cmos_interrupt())
+$ git merge -m Merge branch 'rtc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-fixes/rtc-fixes
+Auto-merging drivers/rtc/rtc-cmos.c
+Merge made by the 'ort' strategy.
+Merging gnss-fixes/gnss-linus (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'gnss-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git gnss-fixes/gnss-linus
+Already up to date.
+Merging hyperv-fixes/hyperv-fixes (49d6a3c062a1 x86/Hyper-V: Add SEV negotiate protocol support in Isolation VM)
+$ git merge -m Merge branch 'hyperv-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git hyperv-fixes/hyperv-fixes
+Already up to date.
+Merging soc-fsl-fixes/fix (4b0986a3613c Linux 5.18)
+$ git merge -m Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux.git soc-fsl-fixes/fix
+Already up to date.
+Merging risc-v-fixes/fixes (e83031564137 riscv: Fix ALT_THEAD_PMA's asm parameters)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git risc-v-fixes/fixes
+Merge made by the 'ort' strategy.
+ arch/riscv/include/asm/errata_list.h | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+Merging risc-v-mc-fixes/dt-fixes (5e757deddd91 riscv: dts: microchip: re-add pdma to mpfs device tree)
+$ git merge -m Merge branch 'dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git risc-v-mc-fixes/dt-fixes
+Already up to date.
+Merging pidfd-fixes/fixes (03ba0fe4d09f file: simplify logic in __close_range())
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git pidfd-fixes/fixes
+Already up to date.
+Merging fpga-fixes/fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git fpga-fixes/fixes
+Already up to date.
+Merging spdx/spdx-linus (de0130355306 x86/crypto: Remove stray comment terminator)
+$ git merge -m Merge branch 'spdx-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx.git spdx/spdx-linus
+Merge made by the 'ort' strategy.
+ Documentation/arm/samsung-s3c24xx/cpufreq.rst      |  2 +-
+ Documentation/driver-api/vfio-mediated-device.rst  |  4 +---
+ arch/arm/boot/bootp/bootp.lds                      |  5 +----
+ arch/arm/boot/dts/am33xx.dtsi                      |  5 +----
+ arch/arm/boot/dts/am3517.dtsi                      |  5 +----
+ arch/arm/boot/dts/am4372.dtsi                      |  5 +----
+ arch/arm/boot/dts/artpec6-devboard.dts             |  9 ++------
+ arch/arm/boot/dts/bcm11351.dtsi                    | 14 ++-----------
+ arch/arm/boot/dts/bcm21664-garnet.dts              | 14 ++-----------
+ arch/arm/boot/dts/bcm21664.dtsi                    | 14 ++-----------
+ arch/arm/boot/dts/bcm28155-ap.dts                  | 14 ++-----------
+ arch/arm/boot/dts/dm814x.dtsi                      |  6 +-----
+ arch/arm/boot/dts/dm816x.dtsi                      |  6 +-----
+ arch/arm/boot/dts/dra62x.dtsi                      |  6 +-----
+ arch/arm/boot/dts/dra7-dspeve-thermal.dtsi         |  5 +----
+ arch/arm/boot/dts/dra7-iva-thermal.dtsi            |  5 +----
+ arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi          | 10 +--------
+ arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi          | 10 +--------
+ arch/arm/boot/dts/imx23-pinfunc.h                  |  8 +-------
+ arch/arm/boot/dts/imx28-pinfunc.h                  |  8 +-------
+ arch/arm/boot/dts/imx6q-gk802.dts                  |  9 ++------
+ arch/arm/boot/dts/mxs-pinfunc.h                    |  8 +-------
+ arch/arm/boot/dts/omap2.dtsi                       |  5 +----
+ arch/arm/boot/dts/omap2420.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap2430.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap3-cpu-thermal.dtsi           |  5 +----
+ arch/arm/boot/dts/omap3.dtsi                       |  5 +----
+ arch/arm/boot/dts/omap34xx.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap36xx.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap4-cpu-thermal.dtsi           |  5 +----
+ arch/arm/boot/dts/omap443x.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap4460.dtsi                    |  5 +----
+ arch/arm/boot/dts/omap5-core-thermal.dtsi          |  5 +----
+ arch/arm/boot/dts/omap5-gpu-thermal.dtsi           |  5 +----
+ arch/arm/boot/dts/orion5x-lacie-d2-network.dts     |  5 +----
+ .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |  9 ++------
+ .../boot/dts/orion5x-maxtor-shared-storage-2.dts   |  5 +----
+ arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  9 ++------
+ arch/arm/boot/dts/orion5x-mv88f5182.dtsi           |  9 ++------
+ arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      |  9 ++------
+ arch/arm/boot/dts/orion5x-rd88f5182-nas.dts        |  9 ++------
+ arch/arm/boot/dts/orion5x.dtsi                     |  9 ++------
+ arch/arm/include/asm/hardware/cache-aurora-l2.h    |  5 +----
+ arch/arm/include/asm/hardware/cache-feroceon-l2.h  |  6 +-----
+ arch/arm/include/asm/hardware/cache-tauros2.h      |  5 +----
+ arch/arm/include/debug/brcmstb.S                   | 14 ++-----------
+ arch/arm/mach-bcm/Makefile                         |  9 +-------
+ arch/arm/mach-bcm/bcm63xx.c                        | 14 ++-----------
+ arch/arm/mach-bcm/bcm_cygnus.c                     | 14 ++-----------
+ arch/arm/mach-bcm/bcm_hr2.c                        | 14 ++-----------
+ arch/arm/mach-bcm/bcm_kona_smc.c                   | 14 ++-----------
+ arch/arm/mach-bcm/bcm_kona_smc.h                   | 14 ++-----------
+ arch/arm/mach-bcm/bcm_nsp.c                        | 14 ++-----------
+ arch/arm/mach-bcm/board_bcm21664.c                 | 14 ++-----------
+ arch/arm/mach-bcm/board_bcm23550.c                 | 14 ++-----------
+ arch/arm/mach-bcm/board_bcm281xx.c                 | 14 ++-----------
+ arch/arm/mach-bcm/brcmstb.c                        | 14 ++-----------
+ arch/arm/mach-bcm/kona_l2_cache.c                  | 14 ++-----------
+ arch/arm/mach-bcm/kona_l2_cache.h                  | 14 ++-----------
+ arch/arm/mach-bcm/platsmp-brcmstb.c                | 10 +--------
+ arch/arm/mach-davinci/board-da830-evm.c            |  6 ++----
+ arch/arm/mach-davinci/board-da850-evm.c            |  6 ++----
+ arch/arm/mach-davinci/board-dm355-evm.c            |  6 ++----
+ arch/arm/mach-davinci/board-dm355-leopard.c        |  5 +----
+ arch/arm/mach-davinci/board-dm365-evm.c            | 11 +---------
+ arch/arm/mach-davinci/board-dm644x-evm.c           |  6 ++----
+ arch/arm/mach-davinci/board-dm646x-evm.c           |  7 +------
+ arch/arm/mach-davinci/board-mityomapl138.c         |  5 +----
+ arch/arm/mach-davinci/board-neuros-osd2.c          |  5 +----
+ arch/arm/mach-davinci/board-omapl138-hawk.c        |  5 +----
+ arch/arm/mach-davinci/common.c                     |  6 ++----
+ arch/arm/mach-davinci/common.h                     |  6 ++----
+ arch/arm/mach-davinci/cpuidle.h                    |  5 +----
+ arch/arm/mach-davinci/cputype.h                    |  6 ++----
+ arch/arm/mach-davinci/da830.c                      |  6 ++----
+ arch/arm/mach-davinci/da850.c                      |  6 ++----
+ arch/arm/mach-davinci/da8xx.h                      |  6 ++----
+ arch/arm/mach-davinci/davinci.h                    | 10 +--------
+ arch/arm/mach-davinci/dm355.c                      |  6 ++----
+ arch/arm/mach-davinci/dm365.c                      | 10 +--------
+ arch/arm/mach-davinci/dm644x.c                     |  6 ++----
+ arch/arm/mach-davinci/dm646x.c                     |  6 ++----
+ arch/arm/mach-davinci/hardware.h                   |  6 ++----
+ arch/arm/mach-davinci/mux.c                        |  6 ++----
+ arch/arm/mach-davinci/mux.h                        |  6 ++----
+ arch/arm/mach-davinci/pm.h                         | 10 +--------
+ arch/arm/mach-davinci/pm_domain.c                  |  5 +----
+ arch/arm/mach-davinci/serial.h                     |  6 ++----
+ arch/arm/mach-dove/bridge-regs.h                   |  9 ++------
+ arch/arm/mach-dove/cm-a510.c                       |  5 +----
+ arch/arm/mach-dove/common.c                        |  5 +----
+ arch/arm/mach-dove/common.h                        |  5 +----
+ arch/arm/mach-dove/dove-db-setup.c                 |  5 +----
+ arch/arm/mach-dove/dove.h                          |  9 ++------
+ arch/arm/mach-dove/irq.c                           |  5 +----
+ arch/arm/mach-dove/irqs.h                          |  9 ++------
+ arch/arm/mach-dove/mpp.c                           |  5 +----
+ arch/arm/mach-dove/pcie.c                          |  5 +----
+ arch/arm/mach-dove/pm.h                            |  6 +-----
+ arch/arm/mach-lpc18xx/board-dt.c                   |  5 +----
+ arch/arm/mach-lpc32xx/pm.c                         |  6 ++----
+ arch/arm/mach-lpc32xx/suspend.S                    |  6 ++----
+ arch/arm/mach-mv78xx0/bridge-regs.h                |  6 +-----
+ arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |  5 +----
+ arch/arm/mach-mv78xx0/common.c                     |  5 +----
+ arch/arm/mach-mv78xx0/common.h                     |  5 +----
+ arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |  5 +----
+ arch/arm/mach-mv78xx0/irq.c                        |  5 +----
+ arch/arm/mach-mv78xx0/irqs.h                       |  9 ++------
+ arch/arm/mach-mv78xx0/mpp.c                        |  5 +----
+ arch/arm/mach-mv78xx0/mpp.h                        |  6 +-----
+ arch/arm/mach-mv78xx0/mv78xx0.h                    |  5 +----
+ arch/arm/mach-mv78xx0/pcie.c                       |  5 +----
+ arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |  5 +----
+ arch/arm/mach-mvebu/armada-370-xp.h                |  5 +----
+ arch/arm/mach-mvebu/board-v7.c                     |  5 +----
+ arch/arm/mach-mvebu/coherency.c                    |  5 +----
+ arch/arm/mach-mvebu/coherency.h                    |  6 +-----
+ arch/arm/mach-mvebu/coherency_ll.S                 |  5 +----
+ arch/arm/mach-mvebu/common.h                       |  5 +----
+ arch/arm/mach-mvebu/cpu-reset.c                    |  5 +----
+ arch/arm/mach-mvebu/dove.c                         |  5 +----
+ arch/arm/mach-mvebu/headsmp-a9.S                   |  5 +----
+ arch/arm/mach-mvebu/headsmp.S                      |  5 +----
+ arch/arm/mach-mvebu/kirkwood.c                     |  5 +----
+ arch/arm/mach-mvebu/kirkwood.h                     |  5 +----
+ arch/arm/mach-mvebu/mvebu-soc-id.c                 |  5 +----
+ arch/arm/mach-mvebu/mvebu-soc-id.h                 |  5 +----
+ arch/arm/mach-mvebu/platsmp-a9.c                   |  5 +----
+ arch/arm/mach-mvebu/platsmp.c                      |  5 +----
+ arch/arm/mach-mvebu/pm-board.c                     |  5 +----
+ arch/arm/mach-mvebu/pm.c                           |  5 +----
+ arch/arm/mach-mvebu/pmsu.c                         |  5 +----
+ arch/arm/mach-mvebu/pmsu.h                         |  5 +----
+ arch/arm/mach-mvebu/pmsu_ll.S                      |  5 +----
+ arch/arm/mach-mvebu/system-controller.c            |  5 +----
+ arch/arm/mach-omap1/board-sx1.h                    |  9 +-------
+ arch/arm/mach-omap1/gpio15xx.c                     | 10 +--------
+ arch/arm/mach-omap1/gpio16xx.c                     | 10 +--------
+ arch/arm/mach-omap1/gpio7xx.c                      | 10 +--------
+ arch/arm/mach-omap1/mtd-xip.h                      |  6 ++----
+ arch/arm/mach-omap1/pm_bus.c                       |  6 +-----
+ arch/arm/mach-omap1/timer.c                        | 10 +--------
+ arch/arm/mach-omap2/am33xx.h                       | 10 +--------
+ arch/arm/mach-omap2/clockdomains33xx_data.c        | 10 +--------
+ arch/arm/mach-omap2/clockdomains81xx_data.c        | 10 +--------
+ arch/arm/mach-omap2/cm-regbits-33xx.h              | 10 +--------
+ arch/arm/mach-omap2/cm33xx.c                       | 10 +--------
+ arch/arm/mach-omap2/cm33xx.h                       | 10 +--------
+ arch/arm/mach-omap2/cm81xx.h                       | 10 +--------
+ arch/arm/mach-omap2/display.c                      | 10 +--------
+ arch/arm/mach-omap2/omap_hwmod_81xx_data.c         | 11 +---------
+ arch/arm/mach-omap2/omap_opp_data.h                | 10 +--------
+ arch/arm/mach-omap2/opp3xxx_data.c                 | 10 +--------
+ arch/arm/mach-omap2/opp4xxx_data.c                 | 10 +--------
+ arch/arm/mach-omap2/powerdomains33xx_data.c        | 10 +--------
+ arch/arm/mach-omap2/prcm43xx.h                     |  5 +----
+ arch/arm/mach-omap2/prm-regbits-33xx.h             | 10 +--------
+ arch/arm/mach-omap2/prm33xx.c                      | 10 +--------
+ arch/arm/mach-omap2/prm33xx.h                      | 10 +--------
+ arch/arm/mach-omap2/ti81xx.h                       | 10 +--------
+ arch/arm/mach-omap2/vc.c                           |  6 +-----
+ arch/arm/mach-orion5x/board-d2net.c                |  5 +----
+ arch/arm/mach-orion5x/board-dt.c                   |  5 +----
+ arch/arm/mach-orion5x/board-rd88f5182.c            |  5 +----
+ arch/arm/mach-orion5x/bridge-regs.h                |  9 ++------
+ arch/arm/mach-orion5x/common.c                     |  5 +----
+ arch/arm/mach-orion5x/db88f5281-setup.c            |  5 +----
+ arch/arm/mach-orion5x/irq.c                        |  5 +----
+ arch/arm/mach-orion5x/irqs.h                       |  5 +----
+ arch/arm/mach-orion5x/kurobox_pro-setup.c          |  5 +----
+ arch/arm/mach-orion5x/ls_hgl-setup.c               |  5 +----
+ arch/arm/mach-orion5x/mpp.c                        |  5 +----
+ arch/arm/mach-orion5x/net2big-setup.c              |  6 +-----
+ arch/arm/mach-orion5x/orion5x.h                    |  5 +----
+ arch/arm/mach-orion5x/pci.c                        |  5 +----
+ arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |  5 +----
+ arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |  5 +----
+ arch/arm/mach-orion5x/rd88f5182-setup.c            |  5 +----
+ arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |  5 +----
+ arch/arm/mach-orion5x/ts78xx-setup.c               |  5 +----
+ arch/arm/mach-orion5x/wnr854t-setup.c              |  9 ++------
+ arch/arm/mach-orion5x/wrt350n-v2-setup.c           |  9 ++------
+ arch/arm/mach-pxa/eseries.c                        |  7 +------
+ arch/arm/mach-pxa/standby.S                        |  6 ++----
+ arch/arm/mach-spear/generic.h                      |  5 +----
+ arch/arm/mach-spear/misc_regs.h                    |  5 +----
+ arch/arm/mach-spear/pl080.c                        |  5 +----
+ arch/arm/mach-spear/pl080.h                        |  5 +----
+ arch/arm/mach-spear/restart.c                      |  5 +----
+ arch/arm/mach-spear/spear.h                        |  5 +----
+ arch/arm/mach-spear/spear1310.c                    |  5 +----
+ arch/arm/mach-spear/spear1340.c                    |  5 +----
+ arch/arm/mach-spear/spear13xx.c                    |  5 +----
+ arch/arm/mach-spear/spear300.c                     |  5 +----
+ arch/arm/mach-spear/spear310.c                     |  5 +----
+ arch/arm/mach-spear/spear320.c                     |  5 +----
+ arch/arm/mach-spear/spear3xx.c                     |  5 +----
+ arch/arm/mach-spear/spear6xx.c                     |  5 +----
+ arch/arm/mach-spear/time.c                         |  5 +----
+ arch/arm/mach-versatile/spc.c                      | 10 +--------
+ arch/arm/mm/cache-feroceon-l2.c                    |  5 +----
+ arch/arm/mm/cache-tauros2.c                        |  5 +----
+ arch/arm64/boot/dts/mediatek/mt6755.dtsi           |  9 +-------
+ arch/arm64/boot/dts/mediatek/mt6795.dtsi           |  9 +-------
+ arch/arm64/boot/dts/mediatek/mt8173.dtsi           |  9 +-------
+ arch/powerpc/kernel/kgdb.c                         |  5 +----
+ arch/sparc/vdso/vdso2c.c                           |  2 +-
+ arch/x86/crypto/crc32-pclmul_asm.S                 | 24 +---------------------
+ arch/x86/entry/vdso/vdso2c.c                       |  2 +-
+ drivers/bluetooth/btmrvl_debugfs.c                 | 15 +-------------
+ drivers/bluetooth/btmrvl_drv.h                     | 16 +--------------
+ drivers/bluetooth/btmrvl_main.c                    | 15 +-------------
+ drivers/bluetooth/btmrvl_sdio.c                    | 15 +-------------
+ drivers/bluetooth/btmrvl_sdio.h                    | 16 +--------------
+ drivers/bus/mvebu-mbus.c                           |  5 +----
+ drivers/bus/omap_l3_noc.c                          | 10 +--------
+ drivers/bus/omap_l3_noc.h                          | 10 +--------
+ drivers/bus/sunxi-rsb.c                            |  6 +-----
+ drivers/bus/tegra-gmi.c                            |  5 +----
+ drivers/bus/ts-nbus.c                              |  5 +----
+ drivers/char/hw_random/iproc-rng200.c              |  9 +-------
+ drivers/clk/axs10x/i2s_pll_clock.c                 |  5 +----
+ drivers/clk/axs10x/pll_clock.c                     |  5 +----
+ drivers/clk/bcm/clk-bcm21664.c                     | 10 +--------
+ drivers/clk/bcm/clk-bcm281xx.c                     | 10 +--------
+ drivers/clk/bcm/clk-bcm63xx.c                      | 14 ++-----------
+ drivers/clk/bcm/clk-cygnus.c                       | 14 ++-----------
+ drivers/clk/bcm/clk-hr2.c                          | 14 ++-----------
+ drivers/clk/bcm/clk-iproc-armpll.c                 | 14 ++-----------
+ drivers/clk/bcm/clk-iproc-asiu.c                   | 14 ++-----------
+ drivers/clk/bcm/clk-iproc-pll.c                    | 14 ++-----------
+ drivers/clk/bcm/clk-iproc.h                        | 14 ++-----------
+ drivers/clk/bcm/clk-kona-setup.c                   | 10 +--------
+ drivers/clk/bcm/clk-kona.c                         | 10 +--------
+ drivers/clk/bcm/clk-kona.h                         | 10 +--------
+ drivers/clk/bcm/clk-ns2.c                          | 14 ++-----------
+ drivers/clk/bcm/clk-nsp.c                          | 14 ++-----------
+ drivers/clk/clk-hsdk-pll.c                         |  5 +----
+ drivers/clk/clk-moxart.c                           |  5 +----
+ drivers/clk/keystone/sci-clk.c                     | 10 +--------
+ drivers/clk/mmp/clk-apbc.c                         |  5 +----
+ drivers/clk/mmp/clk-apmu.c                         |  5 +----
+ drivers/clk/mmp/clk-frac.c                         |  5 +----
+ drivers/clk/mmp/clk-gate.c                         |  5 +----
+ drivers/clk/mmp/clk-mix.c                          |  5 +----
+ drivers/clk/mmp/clk-mmp2.c                         |  5 +----
+ drivers/clk/mmp/clk-of-mmp2.c                      |  5 +----
+ drivers/clk/mmp/clk-of-pxa168.c                    |  5 +----
+ drivers/clk/mmp/clk-of-pxa1928.c                   |  5 +----
+ drivers/clk/mmp/clk-of-pxa910.c                    |  5 +----
+ drivers/clk/mmp/clk-pxa168.c                       |  5 +----
+ drivers/clk/mmp/clk-pxa910.c                       |  5 +----
+ drivers/clk/nxp/clk-lpc18xx-ccu.c                  |  5 +----
+ drivers/clk/nxp/clk-lpc18xx-cgu.c                  |  5 +----
+ drivers/clk/nxp/clk-lpc18xx-creg.c                 |  5 +----
+ drivers/clk/spear/clk-aux-synth.c                  |  5 +----
+ drivers/clk/spear/clk-frac-synth.c                 |  5 +----
+ drivers/clk/spear/clk-gpt-synth.c                  |  5 +----
+ drivers/clk/spear/clk-vco-pll.c                    |  5 +----
+ drivers/clk/spear/clk.c                            |  5 +----
+ drivers/clk/spear/clk.h                            |  5 +----
+ drivers/clk/spear/spear1310_clock.c                |  5 +----
+ drivers/clk/spear/spear1340_clock.c                |  5 +----
+ drivers/clk/spear/spear3xx_clock.c                 |  5 +----
+ drivers/clk/spear/spear6xx_clock.c                 |  5 +----
+ drivers/clk/ti/adpll.c                             | 11 +---------
+ drivers/clk/ti/apll.c                              | 10 +--------
+ drivers/clk/ti/autoidle.c                          | 10 +--------
+ drivers/clk/ti/clk-2xxx.c                          | 10 +--------
+ drivers/clk/ti/clk-33xx.c                          | 10 +--------
+ drivers/clk/ti/clk-3xxx.c                          | 10 +--------
+ drivers/clk/ti/clk-43xx.c                          | 10 +--------
+ drivers/clk/ti/clk-816x.c                          | 11 +---------
+ drivers/clk/ti/clk-dra7-atl.c                      | 10 +--------
+ drivers/clk/ti/clk.c                               | 10 +--------
+ drivers/clk/ti/clkctrl.c                           | 10 +--------
+ drivers/clk/ti/clkt_dflt.c                         | 10 +--------
+ drivers/clk/ti/clock.h                             | 10 +--------
+ drivers/clk/ti/clockdomain.c                       | 10 +--------
+ drivers/clk/ti/composite.c                         | 10 +--------
+ drivers/clk/ti/divider.c                           | 10 +--------
+ drivers/clk/ti/dpll.c                              | 10 +--------
+ drivers/clk/ti/fapll.c                             | 11 +---------
+ drivers/clk/ti/fixed-factor.c                      | 10 +--------
+ drivers/clk/ti/gate.c                              | 10 +--------
+ drivers/clk/ti/interface.c                         | 10 +--------
+ drivers/clk/ti/mux.c                               | 10 +--------
+ drivers/cpufreq/mvebu-cpufreq.c                    |  5 +----
+ drivers/cpufreq/scpi-cpufreq.c                     | 10 +--------
+ drivers/cpuidle/cpuidle-at91.c                     |  5 +----
+ drivers/cpuidle/cpuidle-kirkwood.c                 |  5 +----
+ drivers/dma/bcm-sba-raid.c                         | 14 ++-----------
+ drivers/dma/bestcomm/ata.c                         |  7 +------
+ drivers/dma/bestcomm/bestcomm.c                    |  7 +------
+ drivers/dma/bestcomm/fec.c                         |  7 +------
+ drivers/dma/bestcomm/sram.c                        |  7 +------
+ drivers/dma/moxart-dma.c                           |  5 +----
+ drivers/dma/ppc4xx/adma.h                          |  5 +----
+ drivers/dma/ppc4xx/dma.h                           |  5 +----
+ drivers/dma/ppc4xx/xor.h                           |  5 +----
+ drivers/dma/ti/edma.c                              | 10 +--------
+ drivers/edac/edac_pci.c                            |  7 ++-----
+ drivers/edac/fsl_ddr_edac.c                        |  6 ++----
+ drivers/edac/fsl_ddr_edac.h                        |  7 ++-----
+ drivers/edac/mpc85xx_edac.h                        |  7 ++-----
+ drivers/gpio/gpio-bcm-kona.c                       | 10 +--------
+ drivers/gpio/gpio-brcmstb.c                        | 14 ++-----------
+ drivers/gpio/gpio-lp873x.c                         | 10 +--------
+ drivers/gpio/gpio-lp87565.c                        | 10 +--------
+ drivers/gpio/gpio-mpc8xxx.c                        |  5 +----
+ drivers/gpio/gpio-mvebu.c                          |  5 +----
+ drivers/gpio/gpio-pisosr.c                         | 10 +--------
+ drivers/gpio/gpio-spear-spics.c                    |  5 +----
+ drivers/gpio/gpio-tpic2810.c                       | 10 +--------
+ drivers/gpio/gpio-ts4800.c                         |  5 +----
+ drivers/i2c/busses/i2c-bcm-iproc.c                 | 14 ++-----------
+ drivers/i2c/busses/i2c-bcm-kona.c                  | 14 ++-----------
+ drivers/i2c/busses/i2c-brcmstb.c                   | 14 ++-----------
+ drivers/input/keyboard/bcm-keypad.c                | 14 ++-----------
+ drivers/input/misc/gpio_decoder.c                  | 10 +--------
+ drivers/input/misc/palmas-pwrbutton.c              | 10 +--------
+ drivers/input/misc/tps65218-pwrbutton.c            | 10 +--------
+ drivers/input/touchscreen/bcm_iproc_tsc.c          |  9 +-------
+ drivers/irqchip/irq-keystone.c                     | 10 +--------
+ drivers/mailbox/bcm-flexrm-mailbox.c               | 14 ++-----------
+ drivers/media/i2c/adv7343_regs.h                   | 10 +--------
+ drivers/media/i2c/adv7393_regs.h                   | 10 +--------
+ drivers/media/platform/ti/davinci/vpif.h           | 11 +---------
+ drivers/media/platform/ti/davinci/vpif_display.h   | 10 +--------
+ drivers/memory/ti-emif-sram-pm.S                   | 10 +--------
+ drivers/mfd/lp873x.c                               | 10 +--------
+ drivers/mfd/tps65086.c                             | 10 +--------
+ drivers/mfd/tps65217.c                             | 10 +--------
+ drivers/mfd/tps65218.c                             | 10 +--------
+ drivers/mfd/tps65912-core.c                        | 10 +--------
+ drivers/mfd/tps65912-i2c.c                         | 10 +--------
+ drivers/mfd/tps65912-spi.c                         | 10 +--------
+ drivers/misc/sram-exec.c                           | 10 +--------
+ drivers/mmc/host/sdhci-bcm-kona.c                  | 14 ++-----------
+ drivers/mmc/host/sdhci-iproc.c                     | 14 ++-----------
+ drivers/net/can/ti_hecc.c                          | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/common.h         | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/cphy.h           | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/cpl5_cmd.h       | 12 +----------
+ drivers/net/ethernet/chelsio/cxgb/elmer0.h         | 12 +----------
+ drivers/net/ethernet/chelsio/cxgb/espi.c           | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/espi.h           | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/gmac.h           | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/mv88x201x.c      | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/pm3393.c         | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/regs.h           | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/sge.c            | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/sge.h            | 11 +---------
+ drivers/net/ethernet/chelsio/cxgb/subr.c           | 11 +---------
+ .../net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h  | 12 +----------
+ drivers/net/ethernet/cisco/enic/cq_desc.h          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/cq_enet_desc.h     | 15 +-------------
+ drivers/net/ethernet/cisco/enic/enic.h             | 15 +-------------
+ drivers/net/ethernet/cisco/enic/enic_api.c         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_api.h         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_dev.c         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_dev.h         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_ethtool.c     | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_pp.c          | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_pp.h          | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/enic_res.c         | 15 +-------------
+ drivers/net/ethernet/cisco/enic/enic_res.h         | 15 +-------------
+ drivers/net/ethernet/cisco/enic/rq_enet_desc.h     | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_cq.c          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_cq.h          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_dev.c         | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_dev.h         | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_devcmd.h      | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_enet.h        | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_intr.c        | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_intr.h        | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_nic.h         | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_resource.h    | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_rq.c          | 16 +--------------
+ drivers/net/ethernet/cisco/enic/vnic_rq.h          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_rss.h         | 14 +------------
+ drivers/net/ethernet/cisco/enic/vnic_stats.h       | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_vic.c         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/vnic_vic.h         | 19 ++---------------
+ drivers/net/ethernet/cisco/enic/vnic_wq.c          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/vnic_wq.h          | 15 +-------------
+ drivers/net/ethernet/cisco/enic/wq_enet_desc.h     | 15 +-------------
+ drivers/net/wireless/marvell/mwifiex/11ac.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11ac.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11h.c         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11n.c         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11n.h         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11n_aggr.c    | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/11n_aggr.h    | 14 +------------
+ .../net/wireless/marvell/mwifiex/11n_rxreorder.c   | 14 +------------
+ .../net/wireless/marvell/mwifiex/11n_rxreorder.h   | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/Makefile      | 13 +-----------
+ drivers/net/wireless/marvell/mwifiex/cfg80211.c    | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/cfg80211.h    | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/cfp.c         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/cmdevt.c      | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/debugfs.c     | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/decl.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/ethtool.c     | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/fw.h          | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/ie.c          | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/init.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/ioctl.h       | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/join.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/main.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/main.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/pcie.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/pcie.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/pcie_quirks.c | 18 ++--------------
+ drivers/net/wireless/marvell/mwifiex/pcie_quirks.h | 18 ++--------------
+ drivers/net/wireless/marvell/mwifiex/scan.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sdio.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sdio.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_cmd.c     | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_event.c   | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_ioctl.c   | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_rx.c      | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/sta_tx.c      | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/txrx.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/uap_cmd.c     | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/uap_event.c   | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/uap_txrx.c    | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/usb.c         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/usb.h         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/util.c        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/util.h        | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/wmm.c         | 14 +------------
+ drivers/net/wireless/marvell/mwifiex/wmm.h         | 14 +------------
+ drivers/nvmem/bcm-ocotp.c                          | 14 ++-----------
+ drivers/phy/broadcom/phy-bcm-cygnus-pcie.c         | 14 ++-----------
+ drivers/phy/broadcom/phy-bcm-ns2-pcie.c            | 14 ++-----------
+ drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c          | 14 ++-----------
+ drivers/phy/motorola/phy-cpcap-usb.c               | 10 +--------
+ drivers/phy/ti/phy-dm816x-usb.c                    | 11 +---------
+ drivers/pinctrl/bcm/pinctrl-bcm281xx.c             | 14 ++-----------
+ drivers/pinctrl/bcm/pinctrl-cygnus-mux.c           | 14 ++-----------
+ drivers/pinctrl/bcm/pinctrl-ns2-mux.c              | 10 +--------
+ drivers/pinctrl/bcm/pinctrl-nsp-gpio.c             | 14 ++-----------
+ drivers/pinctrl/bcm/pinctrl-nsp-mux.c              | 10 +--------
+ drivers/pinctrl/pinctrl-as3722.c                   | 15 +-------------
+ drivers/pinctrl/pinctrl-palmas.c                   | 15 +-------------
+ drivers/pinctrl/pinctrl-utils.c                    | 15 +-------------
+ drivers/pinctrl/pinctrl-utils.h                    | 15 +-------------
+ drivers/power/reset/brcm-kona-reset.c              | 14 ++-----------
+ drivers/power/reset/brcmstb-reboot.c               | 14 ++-----------
+ drivers/power/supply/cpcap-battery.c               | 10 +--------
+ drivers/ptp/ptp_dte.c                              | 14 ++-----------
+ drivers/pwm/pwm-bcm-iproc.c                        | 14 ++-----------
+ drivers/pwm/pwm-bcm-kona.c                         | 14 ++-----------
+ drivers/regulator/cpcap-regulator.c                | 10 +--------
+ drivers/regulator/isl6271a-regulator.c             | 10 +--------
+ drivers/regulator/lp873x-regulator.c               | 10 +--------
+ drivers/regulator/max8973-regulator.c              | 15 +-------------
+ drivers/regulator/ti-abb-regulator.c               | 10 +--------
+ drivers/regulator/tps51632-regulator.c             | 15 +-------------
+ drivers/regulator/tps62360-regulator.c             | 15 +-------------
+ drivers/regulator/tps65023-regulator.c             | 10 +--------
+ drivers/regulator/tps6507x-regulator.c             | 10 +--------
+ drivers/regulator/tps65086-regulator.c             | 10 +--------
+ drivers/regulator/tps65217-regulator.c             | 10 +--------
+ drivers/regulator/tps65218-regulator.c             | 10 +--------
+ drivers/regulator/tps65912-regulator.c             | 10 +--------
+ drivers/reset/reset-ti-sci.c                       | 10 +--------
+ drivers/reset/reset-ti-syscon.c                    | 10 +--------
+ drivers/scsi/fnic/cq_desc.h                        | 14 +------------
+ drivers/scsi/fnic/cq_enet_desc.h                   | 14 +------------
+ drivers/scsi/fnic/cq_exch_desc.h                   | 14 +------------
+ drivers/scsi/fnic/fcpio.h                          | 14 +------------
+ drivers/scsi/fnic/fnic.h                           | 14 +------------
+ drivers/scsi/fnic/fnic_attrs.c                     | 14 +------------
+ drivers/scsi/fnic/fnic_debugfs.c                   | 18 ++--------------
+ drivers/scsi/fnic/fnic_fcs.c                       | 14 +------------
+ drivers/scsi/fnic/fnic_fip.h                       | 14 +------------
+ drivers/scsi/fnic/fnic_io.h                        | 14 +------------
+ drivers/scsi/fnic/fnic_isr.c                       | 15 +-------------
+ drivers/scsi/fnic/fnic_main.c                      | 15 +-------------
+ drivers/scsi/fnic/fnic_res.c                       | 14 +------------
+ drivers/scsi/fnic/fnic_res.h                       | 14 +------------
+ drivers/scsi/fnic/fnic_scsi.c                      | 14 +------------
+ drivers/scsi/fnic/fnic_stats.h                     | 18 ++--------------
+ drivers/scsi/fnic/fnic_trace.c                     | 18 ++--------------
+ drivers/scsi/fnic/fnic_trace.h                     | 18 ++--------------
+ drivers/scsi/fnic/rq_enet_desc.h                   | 14 +------------
+ drivers/scsi/fnic/vnic_cq.c                        | 14 +------------
+ drivers/scsi/fnic/vnic_cq.h                        | 14 +------------
+ drivers/scsi/fnic/vnic_cq_copy.h                   | 14 +------------
+ drivers/scsi/fnic/vnic_dev.c                       | 14 +------------
+ drivers/scsi/fnic/vnic_dev.h                       | 14 +------------
+ drivers/scsi/fnic/vnic_devcmd.h                    | 14 +------------
+ drivers/scsi/fnic/vnic_intr.c                      | 14 +------------
+ drivers/scsi/fnic/vnic_intr.h                      | 14 +------------
+ drivers/scsi/fnic/vnic_nic.h                       | 14 +------------
+ drivers/scsi/fnic/vnic_resource.h                  | 14 +------------
+ drivers/scsi/fnic/vnic_rq.c                        | 15 +-------------
+ drivers/scsi/fnic/vnic_rq.h                        | 14 +------------
+ drivers/scsi/fnic/vnic_scsi.h                      | 14 +------------
+ drivers/scsi/fnic/vnic_stats.h                     | 14 +------------
+ drivers/scsi/fnic/vnic_wq.c                        | 14 +------------
+ drivers/scsi/fnic/vnic_wq.h                        | 14 +------------
+ drivers/scsi/fnic/vnic_wq_copy.c                   | 15 +-------------
+ drivers/scsi/fnic/vnic_wq_copy.h                   | 14 +------------
+ drivers/scsi/fnic/wq_enet_desc.h                   | 14 +------------
+ drivers/scsi/snic/cq_desc.h                        | 18 ++--------------
+ drivers/scsi/snic/cq_enet_desc.h                   | 18 ++--------------
+ drivers/scsi/snic/snic.h                           | 18 ++--------------
+ drivers/scsi/snic/snic_attrs.c                     | 18 ++--------------
+ drivers/scsi/snic/snic_ctl.c                       | 18 ++--------------
+ drivers/scsi/snic/snic_debugfs.c                   | 18 ++--------------
+ drivers/scsi/snic/snic_disc.c                      | 18 ++--------------
+ drivers/scsi/snic/snic_disc.h                      | 18 ++--------------
+ drivers/scsi/snic/snic_fwint.h                     | 18 ++--------------
+ drivers/scsi/snic/snic_io.c                        | 18 ++--------------
+ drivers/scsi/snic/snic_io.h                        | 18 ++--------------
+ drivers/scsi/snic/snic_isr.c                       | 18 ++--------------
+ drivers/scsi/snic/snic_main.c                      | 18 ++--------------
+ drivers/scsi/snic/snic_res.c                       | 18 ++--------------
+ drivers/scsi/snic/snic_res.h                       | 18 ++--------------
+ drivers/scsi/snic/snic_scsi.c                      | 18 ++--------------
+ drivers/scsi/snic/snic_stats.h                     | 18 ++--------------
+ drivers/scsi/snic/snic_trc.c                       | 18 ++--------------
+ drivers/scsi/snic/snic_trc.h                       | 18 ++--------------
+ drivers/scsi/snic/vnic_cq.c                        | 18 ++--------------
+ drivers/scsi/snic/vnic_cq.h                        | 18 ++--------------
+ drivers/scsi/snic/vnic_cq_fw.h                     | 18 ++--------------
+ drivers/scsi/snic/vnic_dev.c                       | 18 ++--------------
+ drivers/scsi/snic/vnic_dev.h                       | 18 ++--------------
+ drivers/scsi/snic/vnic_devcmd.h                    | 18 ++--------------
+ drivers/scsi/snic/vnic_intr.c                      | 18 ++--------------
+ drivers/scsi/snic/vnic_intr.h                      | 18 ++--------------
+ drivers/scsi/snic/vnic_resource.h                  | 18 ++--------------
+ drivers/scsi/snic/vnic_snic.h                      | 18 ++--------------
+ drivers/scsi/snic/vnic_stats.h                     | 18 ++--------------
+ drivers/scsi/snic/vnic_wq.c                        | 18 ++--------------
+ drivers/scsi/snic/vnic_wq.h                        | 18 ++--------------
+ drivers/scsi/snic/wq_enet_desc.h                   | 18 ++--------------
+ drivers/soc/ti/knav_dma.c                          | 10 +--------
+ drivers/thermal/hisi_thermal.c                     | 10 +--------
+ drivers/uio/uio_pruss.c                            | 10 +--------
+ drivers/video/backlight/tps65217_bl.c              | 10 +--------
+ include/dt-bindings/clock/bcm21664.h               | 10 +--------
+ include/dt-bindings/clock/bcm281xx.h               | 10 +--------
+ include/dt-bindings/clock/ti-dra7-atl.h            | 10 +--------
+ include/dt-bindings/pinctrl/hisi.h                 | 10 +--------
+ include/dt-bindings/pinctrl/keystone.h             | 10 +--------
+ include/dt-bindings/power/mt6797-power.h           |  9 +-------
+ include/linux/clk/ti.h                             | 10 +--------
+ include/linux/input/elan-i2c-ids.h                 |  5 +----
+ include/linux/mfd/lp873x.h                         | 10 +--------
+ include/linux/mfd/tps65086.h                       | 10 +--------
+ include/linux/mfd/tps65217.h                       | 10 +--------
+ include/linux/mfd/tps65218.h                       | 10 +--------
+ include/linux/mfd/tps65912.h                       | 10 +--------
+ include/linux/platform_data/davinci_asp.h          | 10 +--------
+ include/linux/platform_data/gpio-davinci.h         | 10 +--------
+ include/linux/platform_data/uio_dmem_genirq.h      | 10 +--------
+ include/linux/platform_data/uio_pruss.h            | 10 +--------
+ include/linux/platform_data/usb-omap.h             | 16 +--------------
+ include/linux/pm_wakeirq.h                         | 14 ++-----------
+ include/linux/reset/bcm63xx_pmb.h                  | 10 +--------
+ include/linux/soc/ti/knav_dma.h                    | 10 +--------
+ include/linux/soc/ti/knav_qmss.h                   | 10 +--------
+ include/linux/soc/ti/ti-msgmgr.h                   | 10 +--------
+ include/linux/sram.h                               | 14 ++-----------
+ include/linux/sunrpc/bc_xprt.h                     | 17 +--------------
+ include/linux/ti-emif-sram.h                       | 10 +--------
+ include/linux/usb/audio-v2.h                       |  3 ---
+ include/linux/usb/audio.h                          |  3 ---
+ include/linux/usb/c67x00.h                         | 15 --------------
+ include/linux/usb/cdc-wdm.h                        |  4 ----
+ include/linux/usb/cdc.h                            |  4 ----
+ include/linux/usb/composite.h                      | 14 -------------
+ include/linux/usb/ehci_def.h                       | 14 -------------
+ include/linux/usb/ehci_pdriver.h                   | 14 -------------
+ include/linux/usb/g_hid.h                          | 14 -------------
+ include/linux/usb/gadget.h                         |  2 --
+ include/linux/usb/hcd.h                            | 14 -------------
+ include/linux/usb/input.h                          |  4 ----
+ include/linux/usb/isp1301.h                        | 10 ---------
+ include/linux/usb/m66592.h                         | 14 -------------
+ include/linux/usb/musb-ux500.h                     | 10 ---------
+ include/linux/usb/net2280.h                        | 14 -------------
+ include/linux/usb/of.h                             |  2 --
+ include/linux/usb/ohci_pdriver.h                   | 14 -------------
+ include/linux/usb/otg-fsm.h                        | 17 ++-------------
+ include/linux/usb/phy_companion.h                  | 10 ---------
+ include/linux/usb/r8a66597.h                       | 14 -------------
+ include/linux/usb/rndis_host.h                     | 14 -------------
+ include/linux/usb/serial.h                         |  5 -----
+ include/linux/usb/storage.h                        |  2 --
+ include/linux/usb/tegra_usb_phy.h                  | 10 ---------
+ include/linux/usb/ulpi.h                           |  4 ----
+ include/linux/usb/usb338x.h                        | 11 ----------
+ include/linux/usb/usbnet.h                         | 14 -------------
+ include/linux/usb/xhci-dbgp.h                      |  4 ----
+ include/linux/wkup_m3_ipc.h                        | 10 +--------
+ include/media/i2c/adv7343.h                        | 10 +--------
+ include/media/i2c/adv7393.h                        | 10 +--------
+ include/media/i2c/ov2659.h                         | 14 +------------
+ include/uapi/linux/netfilter/xt_IDLETIMER.h        | 17 +--------------
+ net/hsr/hsr_debugfs.c                              | 10 +--------
+ net/sunrpc/backchannel_rqst.c                      | 16 +--------------
+ net/sunrpc/sunrpc.h                                | 16 +--------------
+ samples/v4l/v4l2-pci-skeleton.c                    | 14 +------------
+ scripts/gcc-plugins/latent_entropy_plugin.c        |  2 +-
+ scripts/gcc-plugins/stackleak_plugin.c             |  2 +-
+ scripts/gcc-plugins/structleak_plugin.c            |  2 +-
+ sound/soc/bcm/cygnus-pcm.c                         | 14 ++-----------
+ sound/soc/bcm/cygnus-ssp.c                         | 14 ++-----------
+ sound/soc/bcm/cygnus-ssp.h                         | 14 ++-----------
+ tools/power/cpupower/debug/i386/dump_psb.c         |  6 ++----
+ 617 files changed, 731 insertions(+), 5619 deletions(-)
+Merging gpio-brgl-fixes/gpio/for-current (a01a40e33499 gpio: realtek-otto: Make the irqchip immutable)
+$ git merge -m Merge branch 'gpio/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio-brgl-fixes/gpio/for-current
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ Documentation/driver-api/gpio/board.rst    |  2 +-
+ Documentation/driver-api/gpio/consumer.rst |  6 +++---
+ Documentation/driver-api/gpio/intro.rst    |  6 +++---
+ MAINTAINERS                                |  1 +
+ drivers/gpio/gpio-realtek-otto.c           | 10 ++++++++--
+ 5 files changed, 16 insertions(+), 9 deletions(-)
+Merging gpio-intel-fixes/fixes (b93a8b2c5161 gpio: dln2: make irq_chip immutable)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git gpio-intel-fixes/fixes
+Already up to date.
+Merging pinctrl-intel-fixes/fixes (ba79c5e45eec MAINTAINERS: Update Intel pin control to Supported)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git pinctrl-intel-fixes/fixes
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging erofs-fixes/fixes (8b1ac84dcf2c Documentation/ABI: sysfs-fs-erofs: Fix Sphinx errors)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git erofs-fixes/fixes
+Already up to date.
+Merging integrity-fixes/fixes (843385694721 evm: Fix a small race in init_desc())
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity integrity-fixes/fixes
+Already up to date.
+Merging kunit-fixes/kunit-fixes (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'kunit-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit-fixes/kunit-fixes
+Already up to date.
+Merging ubifs-fixes/fixes (c3c07fc25f37 ubi: fastmap: Return error code if memory allocation fails in add_aeb())
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git ubifs-fixes/fixes
+Already up to date.
+Merging memblock-fixes/fixes (c94afc46cae7 memblock: use kfree() to release kmalloced memblock regions)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git memblock-fixes/fixes
+Already up to date.
+Merging cel-fixes/for-rc (da9e94fe000e SUNRPC: Remove pointer type casts from xdr_get_next_encode_buffer())
+$ git merge -m Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux cel-fixes/for-rc
+Already up to date.
+Merging irqchip-fixes/irq/irqchip-fixes (4deb96e35c5c irqchip/gicv3: Handle resource request failure consistently)
+$ git merge -m Merge branch 'irq/irqchip-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irqchip-fixes/irq/irqchip-fixes
+Merge made by the 'ort' strategy.
+ drivers/irqchip/irq-gic-v3.c | 41 +++++++++++++++++++++++++++++++----------
+ 1 file changed, 31 insertions(+), 10 deletions(-)
+Merging renesas-fixes/fixes (432b52eea3dc ARM: shmobile: defconfig: Restore graphical consoles)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git renesas-fixes/fixes
+Already up to date.
+Merging broadcom-fixes/fixes (0070ff32d9fc Merge branch 'maintainers/fixes' into fixes)
+$ git merge -m Merge branch 'fixes' of https://github.com/Broadcom/stblinux.git broadcom-fixes/fixes
+Merge made by the 'ort' strategy.
+Merging perf-current/perf/urgent (140cd9ec8fdd tools headers UAPI: Sync linux/prctl.h with the kernel sources)
+$ git merge -m Merge branch 'perf/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf-current/perf/urgent
+Already up to date.
+Merging efi-fixes/urgent (aa6d1ed107eb efi/x86: libstub: Fix typo in __efi64_argmap* name)
+$ git merge -m Merge branch 'urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git efi-fixes/urgent
+Already up to date.
+Merging zstd-fixes/zstd-linus (88a309465b3f lib: zstd: clean up double word in comment.)
+$ git merge -m Merge branch 'zstd-linus' of https://github.com/terrelln/linux.git zstd-fixes/zstd-linus
+Merge made by the 'ort' strategy.
+ include/linux/zstd_lib.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+Merging battery-fixes/fixes (093d27bb6f2d power: supply: core: Fix boundary conditions in interpolation)
+$ git merge -m Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git battery-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/power/reset/arm-versatile-reboot.c |  1 +
+ drivers/power/supply/ab8500_fg.c           |  9 ++++++++-
+ drivers/power/supply/power_supply_core.c   | 24 ++++++++++++------------
+ 3 files changed, 21 insertions(+), 13 deletions(-)
+Merging drm-misc-fixes/for-linux-next-fixes (85016f66af85 drm/sun4i: Return if frontend is not present)
+$ git merge -m Merge branch 'for-linux-next-fixes' of git://anongit.freedesktop.org/drm/drm-misc drm-misc-fixes/for-linux-next-fixes
+Merge made by the 'ort' strategy.
+ drivers/gpu/drm/drm_panel_orientation_quirks.c |   6 +
+ drivers/gpu/drm/sun4i/sun4i_drv.c              |  12 +-
+ drivers/gpu/drm/sun4i/sun4i_layer.c            |   2 +-
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c          |  54 +------
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h          |   2 -
+ drivers/gpu/drm/vc4/vc4_bo.c                   |  62 +++++++-
+ drivers/gpu/drm/vc4/vc4_crtc.c                 | 196 ++++++++++++++++++-------
+ drivers/gpu/drm/vc4/vc4_drv.c                  |  97 ++++++++++--
+ drivers/gpu/drm/vc4/vc4_drv.h                  |  19 ++-
+ drivers/gpu/drm/vc4/vc4_gem.c                  |  40 +++++
+ drivers/gpu/drm/vc4/vc4_hdmi.c                 |   2 +-
+ drivers/gpu/drm/vc4/vc4_hvs.c                  |  18 +--
+ drivers/gpu/drm/vc4/vc4_irq.c                  |  16 ++
+ drivers/gpu/drm/vc4/vc4_kms.c                  |  24 ++-
+ drivers/gpu/drm/vc4/vc4_perfmon.c              |  47 +++++-
+ drivers/gpu/drm/vc4/vc4_plane.c                |  29 +++-
+ drivers/gpu/drm/vc4/vc4_render_cl.c            |   4 +
+ drivers/gpu/drm/vc4/vc4_v3d.c                  |  15 ++
+ drivers/gpu/drm/vc4/vc4_validate.c             |  16 ++
+ drivers/gpu/drm/vc4/vc4_validate_shaders.c     |   4 +
+ 20 files changed, 503 insertions(+), 162 deletions(-)
+Merging kbuild/for-next (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kbuild/for-next
+Already up to date.
+Merging clang-format/clang-format (781121a7f6d1 clang-format: Fix space after for_each macros)
+$ git merge -m Merge branch 'clang-format' of https://github.com/ojeda/linux.git clang-format/clang-format
+Already up to date.
+Merging perf/perf/core (9886142c7a22 Merge tag 'input-for-v5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input)
+$ git merge -m Merge branch 'perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git perf/perf/core
+Already up to date.
+Merging compiler-attributes/compiler-attributes (7c00621dcaee compiler_types: mark __compiletime_assert failure as __noreturn)
+$ git merge -m Merge branch 'compiler-attributes' of https://github.com/ojeda/linux.git compiler-attributes/compiler-attributes
+Already up to date.
+Merging dma-mapping/for-next (0bf28fc40d89 swiotlb: panic if nslabs is too small)
+$ git merge -m Merge branch 'for-next' of git://git.infradead.org/users/hch/dma-mapping.git dma-mapping/for-next
+Merge made by the 'ort' strategy.
+ Documentation/x86/x86_64/boot-options.rst | 8 +++++---
+ include/linux/swiotlb.h                   | 1 -
+ kernel/dma/swiotlb.c                      | 8 ++++++--
+ 3 files changed, 11 insertions(+), 6 deletions(-)
+Merging asm-generic/master (6f1de1da8156 soc: qcom: geni: Disable MMIO tracing for GENI SE)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git asm-generic/master
+Auto-merging drivers/tty/serial/qcom_geni_serial.c
+Auto-merging lib/Kconfig
+Auto-merging lib/Makefile
+Merge made by the 'ort' strategy.
+ arch/Kconfig                                       |  3 +
+ arch/arm/kernel/irq.c                              |  3 +-
+ arch/arm64/Kconfig                                 |  1 +
+ arch/arm64/include/asm/io.h                        | 41 ++-------
+ arch/arm64/kvm/hyp/nvhe/Makefile                   |  7 +-
+ arch/parisc/kernel/irq.c                           |  2 +
+ arch/powerpc/kernel/irq.c                          |  4 +
+ arch/s390/include/asm/softirq_stack.h              |  3 +-
+ arch/sh/kernel/irq.c                               |  2 +
+ arch/sparc/kernel/irq_64.c                         |  2 +
+ drivers/gpu/drm/meson/meson_viu.c                  | 22 ++---
+ drivers/hwtracing/coresight/coresight-etm4x-core.c |  8 +-
+ drivers/hwtracing/coresight/coresight-etm4x.h      |  8 +-
+ drivers/irqchip/irq-tegra.c                        | 10 +--
+ drivers/soc/qcom/qcom-geni-se.c                    |  3 +
+ drivers/tty/serial/qcom_geni_serial.c              |  3 +
+ include/asm-generic/io.h                           | 91 +++++++++++++++++++-
+ include/asm-generic/softirq_stack.h                |  2 +-
+ include/trace/events/rwmmio.h                      | 97 ++++++++++++++++++++++
+ lib/Kconfig                                        |  7 ++
+ lib/Makefile                                       |  2 +
+ lib/trace_readwrite.c                              | 47 +++++++++++
+ 22 files changed, 303 insertions(+), 65 deletions(-)
+ create mode 100644 include/trace/events/rwmmio.h
+ create mode 100644 lib/trace_readwrite.c
+Merging arc/for-next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git arc/for-next
+Already up to date.
+Merging arm/for-next (bafa10435c4f ARM: 9209/1: Spectre-BHB: avoid pr_info() every time a CPU comes out of idle)
+$ git merge -m Merge branch 'for-next' of git://git.armlinux.org.uk/~rmk/linux-arm.git arm/for-next
+Auto-merging drivers/amba/bus.c
+Merge made by the 'ort' strategy.
+ arch/arm/kernel/entry-common.S | 1 +
+ arch/arm/mm/proc-v7-bugs.c     | 6 +++---
+ drivers/amba/bus.c             | 8 ++------
+ 3 files changed, 6 insertions(+), 9 deletions(-)
+Merging arm64/for-next/core (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'for-next/core' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux arm64/for-next/core
+Already up to date.
+Merging arm-perf/for-next/perf (c5781212985a perf/arm-cmn: Decode CAL devices properly in debugfs)
+$ git merge -m Merge branch 'for-next/perf' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git arm-perf/for-next/perf
+Already up to date.
+Merging arm-soc/for-next (3949559bf346 arm: document merges)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git arm-soc/for-next
+Merge made by the 'ort' strategy.
+ arch/arm/arm-soc-for-next-contents.txt | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 arch/arm/arm-soc-for-next-contents.txt
+Merging actions/for-next (444d018d8d38 ARM: dts: owl-s500-roseapplepi: Add ATC2603C PMIC)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions.git actions/for-next
+Auto-merging arch/arm/boot/dts/owl-s500-roseapplepi.dts
+Merge made by the 'ort' strategy.
+Merging amlogic/for-next (147c83586707 Merge branch 'v5.20/drivers' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git amlogic/for-next
+Merge made by the 'ort' strategy.
+ arch/arm/boot/dts/meson.dtsi                       |  4 ++--
+ arch/arm/boot/dts/meson8.dtsi                      |  2 +-
+ arch/arm/boot/dts/meson8b.dtsi                     |  2 +-
+ arch/arm/mach-meson/platsmp.c                      |  2 ++
+ arch/arm64/boot/dts/amlogic/meson-axg.dtsi         |  2 +-
+ .../arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts | 27 ++++++++++++++++++++--
+ .../boot/dts/amlogic/meson-g12b-gtking-pro.dts     |  2 --
+ arch/arm64/boot/dts/amlogic/meson-gx.dtsi          |  2 +-
+ arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts |  2 --
+ .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts    |  4 +---
+ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts    |  4 +---
+ .../dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts |  4 +---
+ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts      |  4 +---
+ .../dts/amlogic/meson-gxl-s905d-vero4k-plus.dts    |  4 +---
+ .../amlogic/meson-gxl-s905w-jethome-jethub-j80.dts |  2 +-
+ .../boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts |  4 +---
+ .../boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts   |  4 +---
+ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts     |  4 +---
+ .../boot/dts/amlogic/meson-gxm-wetek-core2.dts     |  2 --
+ arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |  6 +++++
+ arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts   | 10 ++++----
+ drivers/soc/amlogic/meson-mx-socinfo.c             |  1 +
+ drivers/soc/amlogic/meson-secure-pwrc.c            |  4 +++-
+ 23 files changed, 57 insertions(+), 45 deletions(-)
+Merging aspeed/for-next (bfcbea2c93e5 ARM: dts: aspeed: nuvia: rename vendor nuvia to qcom)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc.git aspeed/for-next
+Auto-merging arch/arm/boot/dts/Makefile
+Merge made by the 'ort' strategy.
+ arch/arm/boot/dts/Makefile                                            | 2 +-
+ .../{aspeed-bmc-nuvia-dc-scm.dts => aspeed-bmc-qcom-dc-scm-v1.dts}    | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+ rename arch/arm/boot/dts/{aspeed-bmc-nuvia-dc-scm.dts => aspeed-bmc-qcom-dc-scm-v1.dts} (97%)
+Merging at91/at91-next (3519476d99a4 Merge branch 'at91-dt' into at91-next)
+$ git merge -m Merge branch 'at91-next' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git at91/at91-next
+Merge made by the 'ort' strategy.
+Merging broadcom/next (d5a4ebb64049 Merge branch 'devicetree/next' into next)
+$ git merge -m Merge branch 'next' of https://github.com/Broadcom/stblinux.git broadcom/next
+Auto-merging MAINTAINERS
+Auto-merging arch/arm/boot/dts/Makefile
+Auto-merging arch/arm/boot/dts/bcm28155-ap.dts
+Auto-merging arch/arm/mach-bcm/bcm_kona_smc.c
+Auto-merging drivers/soc/bcm/brcmstb/pm/pm-arm.c
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/arm/bcm/brcm,bcm4708.yaml  |   7 +
+ .../devicetree/bindings/arm/bcm/brcm,bcmbca.yaml   |  84 +++++++++++
+ MAINTAINERS                                        |  14 +-
+ arch/arm/boot/dts/Makefile                         |   9 +-
+ arch/arm/boot/dts/bcm2711-rpi.dtsi                 |   4 +
+ arch/arm/boot/dts/bcm2711.dtsi                     |  11 ++
+ arch/arm/boot/dts/bcm28155-ap.dts                  |   8 +-
+ arch/arm/boot/dts/bcm283x.dtsi                     |   8 +-
+ arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts        |   6 +-
+ arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts        |   8 +-
+ .../dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi    |  10 +-
+ arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts  |  10 +-
+ arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts    |   4 +-
+ arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts    |   4 +-
+ arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts       |   2 +-
+ arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts       |   2 +-
+ arch/arm/boot/dts/bcm4708-netgear-r6250.dts        |   6 +-
+ arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts     |   6 +-
+ arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts      |   6 +-
+ arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts        |   4 +-
+ arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts |   8 +-
+ arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts  |   2 +-
+ arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts      |   2 +-
+ arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts      |   2 +-
+ arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts |   4 +-
+ arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts        |   6 +-
+ arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts  |  14 +-
+ arch/arm/boot/dts/bcm4709-linksys-ea9200.dts       |   6 +-
+ arch/arm/boot/dts/bcm4709-netgear-r7000.dts        |   8 +-
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts        |  10 +-
+ arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts  |   6 +-
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts       |   8 +-
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts      |   6 +-
+ arch/arm/boot/dts/bcm47094-linksys-panamera.dts    |   6 +-
+ arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts      |   2 +-
+ arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts      |   2 +-
+ arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts      |   2 +-
+ arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts      |   4 +-
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts      |   2 +-
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts   |   2 +-
+ arch/arm/boot/dts/bcm47094-netgear-r8500.dts       |   8 +-
+ arch/arm/boot/dts/bcm47094-phicomm-k3.dts          |   2 +-
+ arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts      |   2 +-
+ arch/arm/boot/dts/bcm47189-luxul-xap-810.dts       |   2 +-
+ arch/arm/boot/dts/bcm47189-tenda-ac9.dts           |   6 +-
+ arch/arm/boot/dts/bcm47622.dtsi                    |  14 +-
+ arch/arm/boot/dts/bcm53015-meraki-mr26.dts         | 166 +++++++++++++++++++++
+ arch/arm/boot/dts/bcm53016-meraki-mr32.dts         |   4 +-
+ arch/arm/boot/dts/bcm5301x.dtsi                    |   6 +-
+ arch/arm/boot/dts/bcm63148.dtsi                    | 103 +++++++++++++
+ arch/arm/boot/dts/bcm63178.dtsi                    | 118 +++++++++++++++
+ arch/arm/boot/dts/bcm6756.dtsi                     | 130 ++++++++++++++++
+ arch/arm/boot/dts/bcm6846.dtsi                     | 103 +++++++++++++
+ arch/arm/boot/dts/bcm6855.dtsi                     | 120 +++++++++++++++
+ arch/arm/boot/dts/bcm6878.dtsi                     | 110 ++++++++++++++
+ arch/arm/boot/dts/bcm911360_entphn.dts             |   4 +-
+ arch/arm/boot/dts/bcm947189acdbmr.dts              |   4 +-
+ arch/arm/boot/dts/bcm953012er.dts                  |   4 +-
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi      |   2 +-
+ arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi    |   2 +-
+ arch/arm/boot/dts/bcm963148.dts                    |  30 ++++
+ arch/arm/boot/dts/bcm963178.dts                    |  30 ++++
+ arch/arm/boot/dts/bcm96756.dts                     |  30 ++++
+ arch/arm/boot/dts/bcm96846.dts                     |  30 ++++
+ arch/arm/boot/dts/bcm96855.dts                     |  30 ++++
+ arch/arm/boot/dts/bcm96878.dts                     |  30 ++++
+ arch/arm/configs/bcm2835_defconfig                 |   1 +
+ arch/arm/configs/multi_v7_defconfig                |   1 +
+ arch/arm/mach-bcm/bcm_kona_smc.c                   |   1 +
+ arch/arm64/Kconfig.platforms                       |   9 ++
+ arch/arm64/boot/dts/broadcom/Makefile              |   1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile       |   6 +
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi   | 128 ++++++++++++++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi  | 110 ++++++++++++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi  | 128 ++++++++++++++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi   | 103 +++++++++++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi   | 121 +++++++++++++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts   |  30 ++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts  |  30 ++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts  |  30 ++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts   |  30 ++++
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts   |  30 ++++
+ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi |   2 +-
+ arch/arm64/configs/defconfig                       |   2 +
+ drivers/soc/bcm/brcmstb/pm/pm-arm.c                |   2 +-
+ 85 files changed, 2035 insertions(+), 135 deletions(-)
+ create mode 100644 arch/arm/boot/dts/bcm53015-meraki-mr26.dts
+ create mode 100644 arch/arm/boot/dts/bcm63148.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm63178.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm6756.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm6846.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm6855.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm6878.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm963148.dts
+ create mode 100644 arch/arm/boot/dts/bcm963178.dts
+ create mode 100644 arch/arm/boot/dts/bcm96756.dts
+ create mode 100644 arch/arm/boot/dts/bcm96846.dts
+ create mode 100644 arch/arm/boot/dts/bcm96855.dts
+ create mode 100644 arch/arm/boot/dts/bcm96878.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+Merging drivers-memory/for-next (44a5f0330d32 Merge branch 'mem-ctrl-next' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git drivers-memory/for-next
+Merge made by the 'ort' strategy.
+ .../memory-controllers/mediatek,smi-common.yaml         |  1 +
+ .../bindings/memory-controllers/mediatek,smi-larb.yaml  |  1 +
+ drivers/memory/mtk-smi.c                                | 17 +++++++++++++++++
+ 3 files changed, 19 insertions(+)
+Merging imx-mxs/for-next (8ba5923278b5 Merge branch 'imx/defconfig' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git imx-mxs/for-next
+Auto-merging arch/arm/boot/dts/Makefile
+Auto-merging arch/arm64/configs/defconfig
+Merge made by the 'ort' strategy.
+ Documentation/devicetree/bindings/arm/fsl.yaml     |   43 +-
+ arch/arm/boot/dts/Makefile                         |    7 +
+ arch/arm/boot/dts/e60k02.dtsi                      |    4 +-
+ arch/arm/boot/dts/e70k02.dtsi                      |    8 +-
+ arch/arm/boot/dts/imx25.dtsi                       |    2 +-
+ arch/arm/boot/dts/imx27.dtsi                       |    6 +-
+ arch/arm/boot/dts/imx31.dtsi                       |    4 +-
+ arch/arm/boot/dts/imx50.dtsi                       |    6 +-
+ arch/arm/boot/dts/imx51-ts4800.dts                 |    2 +-
+ arch/arm/boot/dts/imx51.dtsi                       |    6 +-
+ arch/arm/boot/dts/imx53.dtsi                       |    6 +-
+ arch/arm/boot/dts/imx6dl-plym2m.dts                |    2 +-
+ arch/arm/boot/dts/imx6dl-prtvt7.dts                |    2 +-
+ arch/arm/boot/dts/imx6dl-victgo.dts                |    2 +-
+ arch/arm/boot/dts/imx6dl.dtsi                      |    2 +-
+ arch/arm/boot/dts/imx6q-apalis-eval.dts            |  127 +--
+ arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts      |  263 +----
+ arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts      |  276 ++++++
+ arch/arm/boot/dts/imx6q-apalis-ixora.dts           |  113 +--
+ arch/arm/boot/dts/imx6q-bosch-acc.dts              |    2 +-
+ .../boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts    |    6 +
+ arch/arm/boot/dts/imx6q.dtsi                       |    4 +-
+ arch/arm/boot/dts/imx6qdl-apalis.dtsi              |  638 +++++++++---
+ arch/arm/boot/dts/imx6qdl-colibri.dtsi             |   19 +-
+ arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi       |    4 +-
+ arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi            |   10 +
+ arch/arm/boot/dts/imx6qdl.dtsi                     |    6 +-
+ arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts       |   10 +-
+ arch/arm/boot/dts/imx6sx.dtsi                      |    2 +-
+ arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi      |    1 -
+ arch/arm/boot/dts/imx6ul-phytec-segin.dtsi         |    5 -
+ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi            |    2 +-
+ arch/arm/boot/dts/imx6ul.dtsi                      |   36 +-
+ arch/arm/boot/dts/imx6ull-colibri.dtsi             |    1 -
+ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi           |    2 +-
+ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi          |    2 +-
+ arch/arm/boot/dts/imx6ull.dtsi                     |    2 +-
+ arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts           |    4 +
+ arch/arm/boot/dts/imx7-colibri-aster.dtsi          |  142 +--
+ arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi        |  156 +--
+ arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi        |  112 +++
+ arch/arm/boot/dts/imx7-colibri-iris.dtsi           |  108 ++
+ arch/arm/boot/dts/imx7-colibri.dtsi                |  830 ++++++++++------
+ arch/arm/boot/dts/imx7d-colibri-aster.dts          |   30 +-
+ arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts     |   10 +-
+ arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts   |   10 +-
+ arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts   |   21 +
+ arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts      |   21 +
+ arch/arm/boot/dts/imx7d-colibri-emmc.dtsi          |   17 +-
+ arch/arm/boot/dts/imx7d-colibri-eval-v3.dts        |   45 +-
+ arch/arm/boot/dts/imx7d-colibri-iris-v2.dts        |   83 ++
+ arch/arm/boot/dts/imx7d-colibri-iris.dts           |   56 ++
+ arch/arm/boot/dts/imx7d-colibri.dtsi               |   13 +-
+ arch/arm/boot/dts/imx7d-sdb.dts                    |    2 +-
+ arch/arm/boot/dts/imx7d-smegw01.dts                |    4 +-
+ arch/arm/boot/dts/imx7d.dtsi                       |    2 +-
+ arch/arm/boot/dts/imx7s-colibri-aster.dts          |   27 +-
+ arch/arm/boot/dts/imx7s-colibri-eval-v3.dts        |   43 +-
+ arch/arm/boot/dts/imx7s-colibri-iris-v2.dts        |   78 ++
+ arch/arm/boot/dts/imx7s-colibri-iris.dts           |   51 +
+ arch/arm/boot/dts/imx7s-colibri.dtsi               |    5 +-
+ arch/arm/boot/dts/imx7s.dtsi                       |    2 +-
+ arch/arm/boot/dts/imxrt1050.dtsi                   |    4 +-
+ arch/arm/boot/dts/ls1021a-iot.dts                  |    2 +-
+ arch/arm/mach-imx/Kconfig                          |    6 +-
+ arch/arm/mach-imx/cpu-imx25.c                      |    2 +
+ arch/arm64/boot/dts/freescale/Makefile             |    2 +
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  |    2 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     |   10 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts  |    2 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi     |   16 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi     |   12 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi     |   12 +-
+ .../arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts |   10 +-
+ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi     |    8 +-
+ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     |   10 +-
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts  |    4 +-
+ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi     |    8 +-
+ arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts  |    4 +-
+ arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi    |   10 +-
+ .../dts/freescale/imx8mm-beacon-baseboard.dtsi     |    4 +-
+ .../boot/dts/freescale/imx8mm-icore-mx8mm.dtsi     |   12 +-
+ arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts  |    4 +-
+ .../boot/dts/freescale/imx8mm-var-som-symphony.dts |    6 +-
+ .../boot/dts/freescale/imx8mm-venice-gw700x.dtsi   |   24 +-
+ .../boot/dts/freescale/imx8mm-venice-gw7901.dts    |    8 +-
+ .../boot/dts/freescale/imx8mm-venice-gw7902.dts    |   10 +-
+ .../boot/dts/freescale/imx8mm-venice-gw7903.dts    |    6 +-
+ arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi   |    2 +-
+ arch/arm64/boot/dts/freescale/imx8mm.dtsi          |   16 +-
+ .../dts/freescale/imx8mn-beacon-baseboard.dtsi     |    4 +-
+ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi      |    2 +-
+ .../boot/dts/freescale/imx8mn-var-som-symphony.dts |    6 +-
+ .../boot/dts/freescale/imx8mn-venice-gw7902.dts    |    8 +-
+ arch/arm64/boot/dts/freescale/imx8mn.dtsi          |   13 +-
+ .../arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts |  163 ++++
+ .../arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 1030 ++++++++++++++++++++
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts       |   38 +-
+ arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi   |    2 +-
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi          |   11 +-
+ .../boot/dts/freescale/imx8mq-librem5-devkit.dts   |    6 +-
+ arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi  |    4 +-
+ arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts  |    6 +-
+ .../arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi |    2 +-
+ arch/arm64/boot/dts/freescale/imx8mq.dtsi          |   15 +-
+ .../dts/freescale/imx8qxp-colibri-eval-v3.dtsi     |    8 +-
+ arch/arm64/boot/dts/freescale/imx8qxp.dtsi         |    2 +-
+ arch/arm64/boot/dts/freescale/imx8ulp.dtsi         |   14 +-
+ arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts  |  114 +++
+ arch/arm64/boot/dts/freescale/imx93-pinfunc.h      |  623 ++++++++++++
+ arch/arm64/boot/dts/freescale/imx93.dtsi           |  334 +++++++
+ arch/arm64/boot/dts/freescale/mba8mx.dtsi          |    8 +-
+ arch/arm64/configs/defconfig                       |    2 +
+ drivers/soc/imx/gpcv2.c                            |    8 +-
+ 114 files changed, 4717 insertions(+), 1427 deletions(-)
+ create mode 100644 arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
+ create mode 100644 arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7-colibri-iris.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
+ create mode 100644 arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
+ create mode 100644 arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
+ create mode 100644 arch/arm/boot/dts/imx7d-colibri-iris.dts
+ create mode 100644 arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
+ create mode 100644 arch/arm/boot/dts/imx7s-colibri-iris.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+ create mode 100755 arch/arm64/boot/dts/freescale/imx93-pinfunc.h
+ create mode 100644 arch/arm64/boot/dts/freescale/imx93.dtsi
+Merging keystone/next (cb293d3b430e Merge branch 'for_5.15/drivers-soc' into next)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git keystone/next
+Merge made by the 'ort' strategy.
+Merging mediatek/for-next (71eaf1887203 Merge branch 'v5.19-next/soc' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git mediatek/for-next
+Auto-merging arch/arm64/boot/dts/mediatek/mt6795.dtsi
+Auto-merging arch/arm64/boot/dts/mediatek/mt8173.dtsi
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/soc/mediatek/devapc.yaml   |    1 +
+ .../{display => soc}/mediatek/mediatek,mutex.yaml  |   14 +-
+ .../devicetree/bindings/soc/mediatek/mtk-svs.yaml  |   91 +
+ arch/arm/boot/dts/en7523-evb.dts                   |    8 +
+ arch/arm/boot/dts/en7523.dtsi                      |   66 +
+ arch/arm/boot/dts/mt2701.dtsi                      |    8 +-
+ arch/arm/boot/dts/mt7623.dtsi                      |    6 +-
+ arch/arm/boot/dts/mt7623a-rfb-emmc.dts             |    4 +-
+ arch/arm/boot/dts/mt7623a-rfb-nand.dts             |    4 +-
+ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts      |    4 +-
+ arch/arm/boot/dts/mt7623n-rfb-emmc.dts             |    4 +-
+ arch/arm/boot/dts/mt7629-rfb.dts                   |    4 +-
+ arch/arm64/boot/dts/mediatek/mt2712-evb.dts        |    2 +-
+ arch/arm64/boot/dts/mediatek/mt2712e.dtsi          |    2 +
+ arch/arm64/boot/dts/mediatek/mt6795.dtsi           |  260 ++-
+ .../boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts  |   19 +-
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts       |   13 +-
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi           |   10 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi          |    4 +-
+ .../boot/dts/mediatek/mt8173-elm-hana-rev7.dts     |    6 +-
+ arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi       |   24 +-
+ arch/arm64/boot/dts/mediatek/mt8173-evb.dts        |   12 +-
+ arch/arm64/boot/dts/mediatek/mt8173.dtsi           |    9 +-
+ arch/arm64/boot/dts/mediatek/mt8183-evb.dts        |   38 +-
+ .../boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi    |    4 +-
+ .../boot/dts/mediatek/mt8183-kukui-kakadu.dtsi     |    2 +-
+ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi     |    8 +-
+ arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts    |    2 +-
+ arch/arm64/boot/dts/mediatek/mt8183.dtsi           |  313 ++-
+ arch/arm64/boot/dts/mediatek/mt8192.dtsi           |   29 +-
+ arch/arm64/boot/dts/mediatek/mt8195-evb.dts        |    8 +-
+ arch/arm64/boot/dts/mediatek/mt8195.dtsi           |   76 +-
+ arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi   |    4 +-
+ drivers/soc/mediatek/Kconfig                       |   10 +
+ drivers/soc/mediatek/Makefile                      |    1 +
+ drivers/soc/mediatek/mt8195-pm-domains.h           |    2 +-
+ drivers/soc/mediatek/mt8365-mmsys.h                |   22 +
+ drivers/soc/mediatek/mtk-devapc.c                  |   45 +-
+ drivers/soc/mediatek/mtk-mutex.c                   |  159 +-
+ drivers/soc/mediatek/mtk-pm-domains.c              |    3 +
+ drivers/soc/mediatek/mtk-pm-domains.h              |    2 +
+ drivers/soc/mediatek/mtk-pmic-wrap.c               |  225 +-
+ drivers/soc/mediatek/mtk-svs.c                     | 2399 ++++++++++++++++++++
+ include/linux/soc/mediatek/mtk-mutex.h             |   27 +
+ 44 files changed, 3644 insertions(+), 310 deletions(-)
+ rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,mutex.yaml (81%)
+ create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
+ create mode 100644 drivers/soc/mediatek/mtk-svs.c
+Merging mvebu/for-next (58ec0844bd13 Merge branch 'mvebu/dt64' into mvebu/for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git mvebu/for-next
+Merge made by the 'ort' strategy.
+Merging omap/for-next (b5418fc0478c Merge branch 'omap-for-v5.19/dt' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git omap/for-next
+Auto-merging MAINTAINERS
+Auto-merging arch/arm/boot/dts/logicpd-som-lv.dtsi
+Auto-merging drivers/bus/ti-sysc.c
+Merge made by the 'ort' strategy.
+Merging qcom/for-next (5faa5cd718a4 Merge branches 'arm64-for-5.19', 'arm64-defconfig-for-5.19', 'clk-for-5.19', 'defconfig-for-5.19', 'drivers-for-5.19', 'dts-for-5.19' and 'arm64-fixes-for-5.18' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git qcom/for-next
+Auto-merging Documentation/devicetree/bindings/arm/qcom.yaml
+Auto-merging Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+Auto-merging arch/arm64/boot/dts/qcom/sm8250.dtsi
+Merge made by the 'ort' strategy.
+Merging raspberrypi/for-next (c5915b53d4c2 dt-bindings: soc: bcm: Convert brcm,bcm2835-vchiq to json-schema)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git raspberrypi/for-next
+Merge made by the 'ort' strategy.
+ arch/arm/boot/dts/bcm2711-rpi-400.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+Merging renesas/next (64d15244c480 Merge branch 'renesas-dt-bindings-for-v5.20' into renesas-next)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git renesas/next
+Auto-merging arch/arm64/configs/defconfig
+Merge made by the 'ort' strategy.
+ .../bindings/{arm => soc/renesas}/renesas,prr.yaml |   4 +-
+ arch/arm/boot/dts/r7s9210-rza2mevb.dts             |   4 +-
+ arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts        |   4 +
+ arch/arm/configs/shmobile_defconfig                |   4 +-
+ .../boot/dts/renesas/beacon-renesom-baseboard.dtsi |   6 +-
+ .../arm64/boot/dts/renesas/beacon-renesom-som.dtsi |   4 +-
+ arch/arm64/boot/dts/renesas/draak.dtsi             |   2 +-
+ arch/arm64/boot/dts/renesas/ebisu.dtsi             |   8 +-
+ arch/arm64/boot/dts/renesas/hihope-common.dtsi     |   4 +-
+ arch/arm64/boot/dts/renesas/r8a774c0.dtsi          |   6 +-
+ arch/arm64/boot/dts/renesas/r8a77990.dtsi          |   6 +-
+ arch/arm64/boot/dts/renesas/r8a779a0.dtsi          |  31 +-
+ .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi      |  13 +
+ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts    |   1 +
+ arch/arm64/boot/dts/renesas/r8a779f0.dtsi          | 434 ++++++++++++++++++++-
+ arch/arm64/boot/dts/renesas/r9a07g043.dtsi         |  21 +-
+ arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts |   6 -
+ arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts  |  14 +
+ arch/arm64/boot/dts/renesas/r9a09g011.dtsi         |  51 +++
+ arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi   |   4 +-
+ arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi  |   4 +-
+ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi      |   2 +-
+ arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi  |  23 +-
+ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi      |   6 +
+ arch/arm64/boot/dts/renesas/salvator-common.dtsi   |   8 +-
+ arch/arm64/boot/dts/renesas/ulcb-kf.dtsi           |  14 +-
+ arch/arm64/boot/dts/renesas/ulcb.dtsi              |   6 +-
+ arch/arm64/configs/defconfig                       |   1 +
+ drivers/soc/renesas/r8a779a0-sysc.c                |  10 +-
+ drivers/soc/renesas/rcar-gen4-sysc.h               |   4 +-
+ drivers/soc/renesas/rcar-sysc.h                    |   4 +-
+ 31 files changed, 634 insertions(+), 75 deletions(-)
+ rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas,prr.yaml (85%)
+Merging reset/reset/next (2ca065dc9468 dt-bindings: reset: st,sti-powerdown: Convert to yaml)
+$ git merge -m Merge branch 'reset/next' of https://git.pengutronix.de/git/pza/linux reset/reset/next
+Already up to date.
+Merging rockchip/for-next (4a8d51f2a26d Merge branch 'v5.20-armsoc/dts64' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git rockchip/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/arm/rockchip.yaml          |   5 +
+ arch/arm/boot/dts/rk3066a-bqcurie2.dts             |   4 +-
+ arch/arm/boot/dts/rk3066a-mk808.dts                |  18 ++
+ arch/arm/boot/dts/rk3066a-rayeager.dts             |   2 +-
+ arch/arm/boot/dts/rk3188-bqedison2qc.dts           |   4 +-
+ arch/arm/boot/dts/rk3188-px3-evb.dts               |   2 +-
+ arch/arm/boot/dts/rk3188-radxarock.dts             |   2 +-
+ arch/arm/boot/dts/rk3229-evb.dts                   |   2 +-
+ arch/arm/boot/dts/rk3288-evb.dtsi                  |   2 +-
+ arch/arm/boot/dts/rk3288-firefly-reload.dts        |   2 +-
+ arch/arm/boot/dts/rk3288-firefly.dtsi              |   2 +-
+ arch/arm/boot/dts/rk3288-phycore-rdk.dts           |   4 +-
+ arch/arm/boot/dts/rk3288-popmetal.dts              |   2 +-
+ arch/arm/boot/dts/rk3288-r89.dts                   |   2 +-
+ arch/arm/boot/dts/rk3288-rock2-square.dts          |   2 +-
+ arch/arm/boot/dts/rk3288-tinker.dtsi               |   4 +-
+ .../boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi |  10 +-
+ arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi    |   2 +-
+ arch/arm/boot/dts/rk3288-veyron-minnie.dts         |   4 +-
+ arch/arm/boot/dts/rk3288-veyron-pinky.dts          |   2 +-
+ arch/arm/boot/dts/rk3288-veyron.dtsi               |   2 +-
+ arch/arm/boot/dts/rv1108-elgin-r1.dts              |  14 +-
+ arch/arm/boot/dts/rv1108-evb.dts                   |  14 +-
+ arch/arm/boot/dts/rv1108.dtsi                      |   2 +-
+ arch/arm/mach-rockchip/pm.c                        |   7 +-
+ arch/arm64/boot/dts/rockchip/Makefile              |   1 +
+ arch/arm64/boot/dts/rockchip/px30.dtsi             |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3308-evb.dts        |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts  | 253 +++++++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts |  32 +--
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi       |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts    |   2 +-
+ .../boot/dts/rockchip/rk3368-orion-r68-meta.dts    |   4 +-
+ arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts    |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-r88.dts        |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3368.dtsi           |   6 +-
+ arch/arm64/boot/dts/rockchip/rk3399-evb.dts        |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-firefly.dts    |   2 +-
+ .../boot/dts/rockchip/rk3399-gru-chromebook.dtsi   |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts  |   2 +-
+ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi      |   6 +-
+ .../boot/dts/rockchip/rk3399-khadas-edge.dtsi      |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts |   4 +-
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi   |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts   |   2 +-
+ .../boot/dts/rockchip/rk3399-pinebook-pro.dts      |   4 +-
+ .../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi    |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi |  72 +++++-
+ .../dts/rockchip/rk3399-sapphire-excavator.dts     |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi  |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi           |   6 +-
+ .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi     |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi  |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 115 ++++++++++
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts |   2 +-
+ arch/arm64/boot/dts/rockchip/rk3566.dtsi           |   4 +
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts |  89 ++++++++
+ arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts   |  47 ++++
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts    |  47 ++++
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi           |   4 +
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi           | 166 ++++++++++++++
+ 63 files changed, 917 insertions(+), 101 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+Merging samsung-krzk/for-next (1c48f35a8247 Merge branch 'next/dt' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git samsung-krzk/for-next
+Merge made by the 'ort' strategy.
+ .../bindings/clock/samsung,exynos7885-clock.yaml   |  27 ++
+ arch/arm/boot/dts/alpine.dtsi                      |   2 +-
+ arch/arm/boot/dts/animeo_ip.dts                    |  10 +-
+ arch/arm/boot/dts/aspeed-ast2500-evb.dts           |   2 +-
+ arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts        |   1 +
+ arch/arm/boot/dts/aspeed-ast2600-evb.dts           |   2 +-
+ .../boot/dts/aspeed-bmc-arm-centriq2400-rep.dts    |   2 +-
+ arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts  |   6 +-
+ arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts        |   6 +-
+ arch/arm/boot/dts/at91-kizbox3-hs.dts              |   2 +-
+ arch/arm/boot/dts/at91-sam9x60ek.dts               |   2 +-
+ arch/arm/boot/dts/at91-sama5d27_som1.dtsi          |   2 +-
+ arch/arm/boot/dts/at91-sama5d27_som1_ek.dts        |   4 +-
+ arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts      |   2 +-
+ arch/arm/boot/dts/at91-sama5d2_icp.dts             |   4 +-
+ arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts          |   6 +-
+ arch/arm/boot/dts/at91-sama5d2_xplained.dts        |   6 +-
+ arch/arm/boot/dts/axm5516-cpus.dtsi                |  32 +-
+ arch/arm/boot/dts/ecx-common.dtsi                  |  10 +-
+ arch/arm/boot/dts/exynos-pinctrl.h                 |  55 +++
+ arch/arm/boot/dts/exynos3250-artik5.dtsi           |   2 +-
+ arch/arm/boot/dts/exynos3250-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos3250.dtsi                  |   6 +-
+ arch/arm/boot/dts/exynos4210-i9100.dts             |   8 +-
+ arch/arm/boot/dts/exynos4210-origen.dts            |  12 +-
+ arch/arm/boot/dts/exynos4210-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos4210-trats.dts             |   2 +-
+ arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi        |   8 +-
+ arch/arm/boot/dts/exynos4412-itop-elite.dts        |  15 +-
+ arch/arm/boot/dts/exynos4412-midas.dtsi            |   3 +-
+ arch/arm/boot/dts/exynos4412-odroidu3.dts          |   4 +-
+ arch/arm/boot/dts/exynos4412-odroidx.dts           |   5 +-
+ arch/arm/boot/dts/exynos4412-p4note.dtsi           |  86 +++-
+ arch/arm/boot/dts/exynos4412-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos4412-tiny4412.dts          |   3 +
+ arch/arm/boot/dts/exynos5.dtsi                     |   2 +-
+ arch/arm/boot/dts/exynos5250-arndale.dts           |  12 +-
+ arch/arm/boot/dts/exynos5250-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos5250-snow-common.dtsi      |   2 +-
+ arch/arm/boot/dts/exynos5250-spring.dts            |   2 +-
+ arch/arm/boot/dts/exynos5260-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos5410-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos5420-arndale-octa.dts      |   2 +-
+ arch/arm/boot/dts/exynos5420-peach-pit.dts         |   2 +-
+ arch/arm/boot/dts/exynos5420-pinctrl.dtsi          |   2 +-
+ arch/arm/boot/dts/exynos5422-odroidhc1.dts         |   4 +-
+ arch/arm/boot/dts/exynos5422-odroidxu4.dts         |   4 +-
+ arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi    |   8 +-
+ arch/arm/boot/dts/exynos5800-peach-pi.dts          |   2 +-
+ arch/arm/boot/dts/lpc18xx.dtsi                     |   2 +-
+ arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi      |   2 +-
+ arch/arm/boot/dts/nuvoton-npcm750.dtsi             |   2 +-
+ arch/arm/boot/dts/pxa300-raumfeld-common.dtsi      |  10 +-
+ arch/arm/boot/dts/qcom-apq8064.dtsi                |  12 +-
+ arch/arm/boot/dts/qcom-apq8084.dtsi                |   4 +-
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi      |   2 +-
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts    |   2 +-
+ arch/arm/boot/dts/qcom-ipq8064.dtsi                |   2 +-
+ arch/arm/boot/dts/qcom-msm8974.dtsi                |   4 +-
+ arch/arm/boot/dts/s3c2410-pinctrl.h                |  19 +
+ arch/arm/boot/dts/s3c2416-pinctrl.dtsi             |  38 +-
+ arch/arm/boot/dts/s3c64xx-pinctrl.dtsi             | 178 ++++----
+ arch/arm/boot/dts/s3c64xx-pinctrl.h                |  27 ++
+ arch/arm/boot/dts/s5pv210-aquila.dts               |   4 +-
+ arch/arm/boot/dts/s5pv210-aries.dtsi               | 134 +++---
+ arch/arm/boot/dts/s5pv210-fascinate4g.dts          |  28 +-
+ arch/arm/boot/dts/s5pv210-galaxys.dts              |  42 +-
+ arch/arm/boot/dts/s5pv210-pinctrl.dtsi             | 480 ++++++++++-----------
+ arch/arm/boot/dts/s5pv210-pinctrl.h                |  39 ++
+ arch/arm/boot/dts/sam9x60.dtsi                     |   2 +-
+ arch/arm/boot/dts/sd5203.dts                       |   2 +-
+ arch/arm/boot/dts/spear1310-evb.dts                |   2 +-
+ arch/arm/boot/dts/spear1340-evb.dts                |   2 +-
+ arch/arm/boot/dts/spear1340.dtsi                   |   2 +-
+ arch/arm/boot/dts/spear300-evb.dts                 |   2 +-
+ arch/arm/boot/dts/spear310-evb.dts                 |   2 +-
+ arch/arm/boot/dts/spear320-evb.dts                 |   2 +-
+ arch/arm/boot/dts/spear320-hmi.dts                 |   2 +-
+ arch/arm/boot/dts/spear320.dtsi                    |   2 +-
+ arch/arm/boot/dts/ste-ab8500.dtsi                  |   6 +-
+ arch/arm/boot/dts/ste-hrefv60plus.dtsi             |   4 +-
+ arch/arm/boot/dts/stih407-family.dtsi              | 174 ++++----
+ arch/arm/boot/dts/stih407.dtsi                     |   4 +-
+ arch/arm/boot/dts/stih410.dtsi                     |   4 +-
+ arch/arm/boot/dts/stihxxx-b2120.dtsi               |   8 +-
+ arch/arm/mach-s3c/Kconfig                          |  14 +-
+ arch/arm/mach-s3c/Kconfig.s3c24xx                  |  26 +-
+ arch/arm/mach-s3c/Kconfig.s3c64xx                  |  16 +-
+ arch/arm/mach-s3c/mach-mini2440.c                  |   2 +-
+ arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts   |   4 +-
+ arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts   |   4 +-
+ arch/arm64/boot/dts/apm/apm-merlin.dts             |   2 +-
+ arch/arm64/boot/dts/apm/apm-mustang.dts            |   2 +-
+ arch/arm64/boot/dts/apm/apm-shadowcat.dtsi         |   2 +-
+ arch/arm64/boot/dts/apm/apm-storm.dtsi             |   4 +-
+ .../bcm4908/bcm4906-tplink-archer-c2300-v1.dts     |   8 +-
+ .../broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts    |   8 +-
+ arch/arm64/boot/dts/exynos/exynos-pinctrl.h        |  79 ++++
+ arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi |   2 +-
+ arch/arm64/boot/dts/exynos/exynos5433.dtsi         |   6 +-
+ arch/arm64/boot/dts/exynos/exynos7-espresso.dts    |   6 +-
+ arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi    |  72 ++--
+ .../boot/dts/exynos/exynos7885-jackpotlte.dts      |  20 +
+ arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi |   2 +-
+ arch/arm64/boot/dts/exynos/exynos7885.dtsi         |  32 ++
+ arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi  |   2 +-
+ .../boot/dts/exynos/exynosautov9-pinctrl.dtsi      |   2 +-
+ arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts   |  18 +
+ arch/arm64/boot/dts/exynos/exynosautov9.dtsi       |  83 +++-
+ arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts  |  14 +-
+ arch/arm64/boot/dts/hisilicon/hi3660.dtsi          |   8 +-
+ arch/arm64/boot/dts/hisilicon/hi3670.dtsi          |   2 +-
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts     |  12 +-
+ arch/arm64/boot/dts/hisilicon/hip05-d02.dts        |   6 +-
+ arch/arm64/boot/dts/hisilicon/hip06.dtsi           |   6 +-
+ arch/arm64/boot/dts/hisilicon/hip07.dtsi           |   6 +-
+ arch/arm64/boot/dts/lg/lg1312.dtsi                 |  38 +-
+ arch/arm64/boot/dts/lg/lg1313.dtsi                 |  38 +-
+ .../boot/dts/marvell/armada-7040-mochabin.dts      |   4 +-
+ arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi |   2 +-
+ .../boot/dts/marvell/armada-8040-puzzle-m801.dts   |   4 +-
+ arch/arm64/boot/dts/marvell/cn9130-db.dtsi         |   2 +-
+ .../boot/dts/microchip/sparx5_pcb134_board.dtsi    | 200 ++++-----
+ .../boot/dts/microchip/sparx5_pcb135_board.dtsi    |  48 +--
+ arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts       |   2 +-
+ arch/arm64/boot/dts/qcom/msm8916.dtsi              |   2 +-
+ arch/arm64/boot/dts/qcom/msm8996.dtsi              |   2 +-
+ arch/arm64/boot/dts/qcom/msm8998-mtp.dts           |   2 +-
+ arch/arm64/boot/dts/qcom/msm8998.dtsi              |   2 +-
+ arch/arm64/boot/dts/qcom/pm660l.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/pmi8994.dtsi              |   2 +-
+ arch/arm64/boot/dts/qcom/pmi8998.dtsi              |   2 +-
+ arch/arm64/boot/dts/qcom/qcs404.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/sc7180.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/sc7280.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/sdm630.dtsi               |  10 +-
+ arch/arm64/boot/dts/qcom/sm8150.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/sm8250.dtsi               |   2 +-
+ arch/arm64/boot/dts/qcom/sm8350.dtsi               |   2 +-
+ arch/arm64/boot/dts/sprd/sc9836.dtsi               |  10 +-
+ arch/arm64/boot/dts/sprd/sc9863a.dtsi              |   4 +-
+ arch/arm64/boot/dts/sprd/whale2.dtsi               |   2 +-
+ arch/arm64/boot/dts/tesla/fsd-evb.dts              |   4 +
+ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi         | 106 +++--
+ arch/arm64/boot/dts/tesla/fsd-pinctrl.h            |  33 ++
+ arch/arm64/boot/dts/tesla/fsd.dtsi                 | 120 ++++++
+ include/dt-bindings/clock/exynos7885.h             |  54 ++-
+ include/dt-bindings/soc/samsung,boot-mode.h        |  18 +
+ 148 files changed, 1763 insertions(+), 1074 deletions(-)
+ create mode 100644 arch/arm/boot/dts/exynos-pinctrl.h
+ create mode 100644 arch/arm/boot/dts/s3c2410-pinctrl.h
+ create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.h
+ create mode 100644 arch/arm/boot/dts/s5pv210-pinctrl.h
+ create mode 100644 arch/arm64/boot/dts/exynos/exynos-pinctrl.h
+ create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.h
+ create mode 100644 include/dt-bindings/soc/samsung,boot-mode.h
+Merging scmi/for-linux-next (04dbc874a2f5 Merge branch 'for-next/scmi' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into for-linux-next)
+$ git merge -m Merge branch 'for-linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git scmi/for-linux-next
+Merge made by the 'ort' strategy.
+ arch/arm64/boot/dts/arm/fvp-base-revc.dts |  2 +-
+ arch/arm64/boot/dts/arm/juno-base.dtsi    | 44 +++++++++++++++----------------
+ arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 16 +++++------
+ arch/arm64/boot/dts/arm/juno-scmi.dtsi    |  1 -
+ drivers/firmware/arm_scmi/clock.c         | 26 +++++++++++++++++-
+ drivers/firmware/arm_scmi/driver.c        |  1 +
+ drivers/firmware/arm_scmi/protocols.h     |  3 +++
+ 7 files changed, 60 insertions(+), 33 deletions(-)
+Merging stm32/stm32-next (3fc30e640f52 ARM: dts: stm32: add fake interrupt propoerty for ASync notif - TEMP/TO REMOVE)
+$ git merge -m Merge branch 'stm32-next' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32/stm32-next
+Auto-merging arch/arm/boot/dts/stm32mp151.dtsi
+Auto-merging drivers/firmware/arm_scmi/base.c
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/clock/st,stm32mp1-rcc.yaml |   1 +
+ arch/arm/boot/dts/stm32429i-eval.dts               |   8 +-
+ arch/arm/boot/dts/stm32h743.dtsi                   |   4 +-
+ arch/arm/boot/dts/stm32h743i-disco.dts             |   8 +-
+ arch/arm/boot/dts/stm32h743i-eval.dts              |   8 +-
+ arch/arm/boot/dts/stm32h750i-art-pi.dts            |   8 +-
+ arch/arm/boot/dts/stm32mp131.dtsi                  | 142 +++++++++++----------
+ arch/arm/boot/dts/stm32mp133.dtsi                  |   4 +-
+ arch/arm/boot/dts/stm32mp135f-dk.dts               |  11 ++
+ arch/arm/boot/dts/stm32mp13xc.dtsi                 |   3 +-
+ arch/arm/boot/dts/stm32mp13xf.dtsi                 |   3 +-
+ arch/arm/boot/dts/stm32mp151.dtsi                  |   7 +-
+ arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi     |   5 +
+ arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi       |   4 +-
+ arch/arm/boot/dts/stm32mp15xx-osd32.dtsi           |   9 +-
+ 15 files changed, 122 insertions(+), 103 deletions(-)
+Merging sunxi/sunxi/for-next (ba585a9e1791 Merge branch 'sunxi/dt-for-5.20' into sunxi/for-next)
+$ git merge -m Merge branch 'sunxi/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/sunxi/for-next
+Merge made by the 'ort' strategy.
+ .../clock/allwinner,sun8i-a83t-de2-clk.yaml        |   3 +
+ arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts       |  40 ++++----
+ arch/arm/boot/dts/sun4i-a10-pcduino.dts            |   6 +-
+ arch/arm/boot/dts/sun5i-a13-licheepi-one.dts       |   6 +-
+ arch/arm/boot/dts/sun6i-a31.dtsi                   |  12 ++-
+ arch/arm/boot/dts/sun7i-a20-pcduino3.dts           |   6 +-
+ arch/arm/boot/dts/sun8i-a23-a33.dtsi               |   8 +-
+ .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts    |   8 +-
+ arch/arm/boot/dts/sun8i-h3-beelink-x2.dts          |   6 +-
+ arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts    |   6 +-
+ arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts         |   8 +-
+ arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts      |   2 +-
+ arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts           |   4 +-
+ arch/arm/boot/dts/sun8i-h3-nanopi.dtsi             |   4 +-
+ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts          |   6 +-
+ arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts       |   4 +-
+ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts        |   4 +-
+ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts         |   4 +-
+ arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts       |   4 +-
+ arch/arm/boot/dts/sun8i-r40.dtsi                   |   8 +-
+ arch/arm/boot/dts/sun8i-v3s.dtsi                   |   6 +-
+ arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi      |   8 +-
+ arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi    |   4 +-
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi                 |  13 ++-
+ arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi   |   4 +-
+ .../dts/allwinner/sun50i-a64-amarula-relic.dts     |   2 +-
+ .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts |   4 +-
+ .../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts   |   2 +-
+ .../boot/dts/allwinner/sun50i-a64-orangepi-win.dts |   4 +-
+ .../boot/dts/allwinner/sun50i-a64-pinebook.dts     |   4 +-
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  10 +-
+ .../boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts |   4 +-
+ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  |   4 +-
+ .../dts/allwinner/sun50i-h5-orangepi-prime.dts     |   4 +-
+ .../boot/dts/allwinner/sun50i-h6-orangepi-3.dts    |   4 +-
+ .../dts/allwinner/sun50i-h6-orangepi-lite2.dts     |   4 +-
+ arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi |   2 +-
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi       |  12 ++-
+ drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c             |  16 +--
+ drivers/clk/sunxi-ng/ccu-sun8i-de2.c               |  77 ++++----------
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c                | 113 +--------------------
+ drivers/clk/sunxi-ng/ccu-sun8i-r.c                 |  40 ++------
+ drivers/clk/sunxi-ng/ccu-sun8i-v3s.c               |  80 +--------------
+ 43 files changed, 168 insertions(+), 402 deletions(-)
+Merging tee/next (db30e53bf897 Merge branch 'tee_cleanup_for_v5.19' into next)
+$ git merge -m Merge branch 'next' of https://git.linaro.org/people/jens.wiklander/linux-tee.git tee/next
+Auto-merging drivers/tee/tee_shm.c
+Merge made by the 'ort' strategy.
+Merging tegra/for-next (22cd13a29127 Merge branch for-5.20/arm64/defconfig into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tegra/for-next
+Auto-merging arch/arm64/configs/defconfig
+Merge made by the 'ort' strategy.
+ arch/arm/boot/dts/tegra20-acer-a500-picasso.dts    |  2 +-
+ arch/arm/boot/dts/tegra20-asus-tf101.dts           |  2 +-
+ .../dts/tegra30-asus-nexus7-grouper-common.dtsi    |  6 +-
+ arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi |  2 +-
+ arch/arm/boot/dts/tegra30-colibri.dtsi             |  6 +-
+ arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 43 +++++++++++
+ arch/arm64/boot/dts/nvidia/tegra186.dtsi           | 23 ++++++
+ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 43 +++++++++++
+ .../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 43 +++++++++++
+ arch/arm64/boot/dts/nvidia/tegra194.dtsi           | 23 ++++++
+ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 84 ++++++++++++++++++++++
+ arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 84 ++++++++++++++++++++++
+ arch/arm64/boot/dts/nvidia/tegra210.dtsi           | 42 ++++++++++-
+ .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts  | 43 +++++++++++
+ arch/arm64/boot/dts/nvidia/tegra234.dtsi           | 65 +++++++++++++++++
+ arch/arm64/configs/defconfig                       |  1 +
+ include/dt-bindings/memory/tegra234-mc.h           |  1 +
+ include/dt-bindings/reset/tegra234-reset.h         |  1 +
+ 18 files changed, 504 insertions(+), 10 deletions(-)
+Merging ti/ti-next (9b123c7c630c Merge branches 'ti-keystone-dts-next', 'ti-drivers-soc-next' and 'ti-k3-dts-next' into ti-next)
+$ git merge -m Merge branch 'ti-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git ti/ti-next
+Merge made by the 'ort' strategy.
+ arch/arm/boot/dts/keystone-k2e-netcp.dtsi          | 26 +++++++++++-----------
+ arch/arm/boot/dts/keystone-k2e.dtsi                |  6 ++---
+ arch/arm/boot/dts/keystone-k2g-netcp.dtsi          |  2 +-
+ arch/arm/boot/dts/keystone-k2g.dtsi                | 18 +++++++--------
+ arch/arm/boot/dts/keystone-k2hk-netcp.dtsi         | 12 +++++-----
+ arch/arm/boot/dts/keystone-k2hk.dtsi               |  4 ++--
+ arch/arm/boot/dts/keystone-k2l-netcp.dtsi          | 18 +++++++--------
+ arch/arm/boot/dts/keystone-k2l.dtsi                |  8 +++----
+ arch/arm/boot/dts/keystone.dtsi                    | 18 +++++++--------
+ arch/arm64/boot/dts/ti/k3-am62-main.dtsi           |  4 ++--
+ arch/arm64/boot/dts/ti/k3-am625-sk.dts             |  2 +-
+ arch/arm64/boot/dts/ti/k3-am64-main.dtsi           |  6 ++---
+ arch/arm64/boot/dts/ti/k3-am642-evm.dts            |  2 +-
+ arch/arm64/boot/dts/ti/k3-am642-sk.dts             |  2 +-
+ arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi |  4 ++--
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi           | 14 ++++++------
+ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi         |  4 ++--
+ arch/arm64/boot/dts/ti/k3-am654-base-board.dts     |  8 +++----
+ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi    |  4 ++--
+ .../boot/dts/ti/k3-j721e-common-proc-board.dts     |  4 ++--
+ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi    |  4 ++--
+ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi         |  6 ++---
+ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi   |  4 ++--
+ drivers/soc/ti/wkup_m3_ipc.c                       |  2 +-
+ 24 files changed, 90 insertions(+), 92 deletions(-)
+Merging xilinx/for-next (63623390c0d6 arm64: dts: zynqmp: add AMS driver to device tree)
+$ git merge -m Merge branch 'for-next' of git://github.com/Xilinx/linux-xlnx.git xilinx/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/gpio/gpio-zynq.yaml        | 59 +++++++++++++++++++++-
+ arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi     |  4 ++
+ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts  |  2 +-
+ arch/arm64/boot/dts/xilinx/zynqmp.dtsi             | 26 ++++++++++
+ 4 files changed, 89 insertions(+), 2 deletions(-)
+Merging clk/clk-next (292dcfc1f60e Merge branch 'clk-devm-enable' into clk-next)
+$ git merge -m Merge branch 'clk-next' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk/clk-next
+Auto-merging MAINTAINERS
+Auto-merging drivers/clk/ti/clkctrl.c
+Merge made by the 'ort' strategy.
+ .../arm/mediatek/mediatek,mt8186-sys-clock.yaml    |   3 +
+ .../arm/mediatek/mediatek,mt8192-clock.yaml        |   8 -
+ .../arm/mediatek/mediatek,mt8192-sys-clock.yaml    |   3 +
+ .../arm/mediatek/mediatek,mt8195-sys-clock.yaml    |   3 +
+ .../bindings/clock/fixed-factor-clock.yaml         |   1 -
+ MAINTAINERS                                        |   1 +
+ drivers/clk/clk-devres.c                           |  91 +++++++--
+ drivers/clk/clk-fixed-factor.c                     |  11 +-
+ drivers/clk/clk.c                                  |  48 -----
+ drivers/clk/mediatek/clk-mt2701-eth.c              |  10 +-
+ drivers/clk/mediatek/clk-mt2701-g3d.c              |  10 +-
+ drivers/clk/mediatek/clk-mt2701-hif.c              |  10 +-
+ drivers/clk/mediatek/clk-mt2701.c                  |  22 ++-
+ drivers/clk/mediatek/clk-mt2712.c                  |  22 ++-
+ drivers/clk/mediatek/clk-mt7622-eth.c              |  10 +-
+ drivers/clk/mediatek/clk-mt7622-hif.c              |  12 +-
+ drivers/clk/mediatek/clk-mt7622.c                  |  22 ++-
+ drivers/clk/mediatek/clk-mt7629-eth.c              |  10 +-
+ drivers/clk/mediatek/clk-mt7629-hif.c              |  12 +-
+ drivers/clk/mediatek/clk-mt8135.c                  |  22 ++-
+ drivers/clk/mediatek/clk-mt8173.c                  |  22 ++-
+ drivers/clk/mediatek/clk-mt8183.c                  |  18 +-
+ drivers/clk/mediatek/clk-mt8186-infra_ao.c         |  23 +++
+ drivers/clk/mediatek/clk-mt8192-msdc.c             |  21 ---
+ drivers/clk/mediatek/clk-mt8192.c                  |  29 +++
+ drivers/clk/mediatek/clk-mt8195-infra_ao.c         |  24 +++
+ drivers/clk/mediatek/clk-mtk.c                     |   7 +
+ drivers/clk/mediatek/clk-mtk.h                     |   9 +-
+ drivers/clk/mediatek/reset.c                       | 198 +++++++++++++------
+ drivers/clk/mediatek/reset.h                       |  82 ++++++++
+ drivers/clk/meson/axg-audio.c                      |  36 +---
+ drivers/clk/stm32/reset-stm32.c                    |   1 +
+ drivers/clk/ti/clk-44xx.c                          | 210 ++++++++++-----------
+ drivers/clk/ti/clk-54xx.c                          | 160 ++++++++--------
+ drivers/clk/ti/clkctrl.c                           |   4 -
+ include/dt-bindings/reset/mt8186-resets.h          |   5 +
+ include/dt-bindings/reset/mt8192-resets.h          |   8 +
+ include/dt-bindings/reset/mt8195-resets.h          |   6 +
+ include/linux/clk-provider.h                       |   2 -
+ include/linux/clk.h                                | 134 ++++++++++++-
+ 40 files changed, 915 insertions(+), 415 deletions(-)
+ create mode 100644 drivers/clk/mediatek/reset.h
+Merging clk-imx/for-next (c196175acdd3 clk: imx: clk-fracn-gppll: Add more freq config for video pll)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk-imx/for-next
+Merge made by the 'ort' strategy.
+ drivers/clk/imx/clk-fracn-gppll.c | 36 +++++++++++++++++++++---------------
+ drivers/clk/imx/clk-imx93.c       |  6 +++---
+ 2 files changed, 24 insertions(+), 18 deletions(-)
+Merging clk-renesas/renesas-clk (080bcd8d5997 clk: renesas: r8a779f0: Add HSCIF clocks)
+$ git merge -m Merge branch 'renesas-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas/renesas-clk
+Merge made by the 'ort' strategy.
+ .../bindings/clock/renesas,rzg2l-cpg.yaml          |  7 ++---
+ drivers/clk/renesas/clk-r8a73a4.c                  | 22 +++++++--------
+ drivers/clk/renesas/clk-r8a7740.c                  | 20 ++++++-------
+ drivers/clk/renesas/clk-r8a7778.c                  | 31 ++++++--------------
+ drivers/clk/renesas/clk-r8a7779.c                  | 27 ++++++------------
+ drivers/clk/renesas/clk-rz.c                       | 33 ++++++++++------------
+ drivers/clk/renesas/clk-sh73a0.c                   | 26 ++++++++---------
+ drivers/clk/renesas/r8a779f0-cpg-mssr.c            | 10 +++++++
+ drivers/clk/renesas/r9a06g032-clocks.c             | 32 ++++++++++-----------
+ drivers/clk/renesas/r9a07g044-cpg.c                | 17 ++++++++++-
+ drivers/clk/renesas/r9a09g011-cpg.c                |  5 ++++
+ drivers/clk/renesas/rzg2l-cpg.c                    |  2 +-
+ 12 files changed, 117 insertions(+), 115 deletions(-)
+Merging clk-samsung/for-next (b35f27fe73d8 clk: samsung: exynosautov9: add cmu_peric1 clock support)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git clk-samsung/for-next
+Already up to date.
+Merging csky/linux-next (64d83f067746 csky: Move $(core-y) into arch/csky/Kbuild)
+$ git merge -m Merge branch 'linux-next' of git://github.com/c-sky/csky-linux.git csky/linux-next
+Already up to date.
+Merging loongarch/loongarch-next (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'loongarch-next' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git loongarch/loongarch-next
+Already up to date.
+Merging m68k/for-next (bcc94f9a2581 m68k: sun3: Use __func__ to get function's name in an output message)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git m68k/for-next
+Merge made by the 'ort' strategy.
+ arch/m68k/Kconfig.machine |  3 ++-
+ arch/m68k/mac/iop.c       |  4 ++--
+ arch/m68k/sun3/mmu_emu.c  | 11 +++++------
+ 3 files changed, 9 insertions(+), 9 deletions(-)
+Merging m68knommu/for-next (8c6c2af9a4ed m68k: Fix syntax errors in comments)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git m68knommu/for-next
+Merge made by the 'ort' strategy.
+ arch/m68k/coldfire/device.c | 6 +++---
+ arch/m68k/coldfire/intc-2.c | 2 +-
+ arch/m68k/coldfire/m523x.c  | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+Merging microblaze/next (78b5f52ab6f6 microblaze: fix typos in comments)
+$ git merge -m Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze.git microblaze/next
+Already up to date.
+Merging mips/mips-next (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'mips-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git mips/mips-next
+Already up to date.
+Merging nios2/for-next (7f7bc20bc41a nios2: Don't use _end for calculating min_low_pfn)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git nios2/for-next
+Already up to date.
+Merging openrisc/for-next (83da38d82b2f openrisc: Allow power off handler overriding)
+$ git merge -m Merge branch 'for-next' of git://github.com/openrisc/linux.git openrisc/for-next
+Already up to date.
+Merging parisc-hd/for-next (1d0811b03eb3 parisc/stifb: Fix fb_is_primary_device() only available with CONFIG_FB_STI)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git parisc-hd/for-next
+Merge made by the 'ort' strategy.
+ arch/parisc/include/asm/fb.h    | 2 +-
+ drivers/video/console/sticore.c | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+Merging powerpc/next (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git powerpc/next
+Already up to date.
+Merging soc-fsl/next (4b0986a3613c Linux 5.18)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux.git soc-fsl/next
+Already up to date.
+Merging risc-v/for-next (bb356ddb78b2 RISC-V: PCI: Avoid handing out address 0 to devices)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git risc-v/for-next
+Merge made by the 'ort' strategy.
+ arch/riscv/errata/thead/errata.c   | 38 ++++++++++---------------------
+ arch/riscv/include/asm/hwcap.h     | 25 +++++++++++++++++++++
+ arch/riscv/include/asm/pci.h       |  4 ++--
+ arch/riscv/include/asm/switch_to.h |  4 ++--
+ arch/riscv/kernel/alternative.c    | 18 +++++++--------
+ arch/riscv/kernel/cpufeature.c     | 46 ++++++++++++++------------------------
+ 6 files changed, 67 insertions(+), 68 deletions(-)
+Merging risc-v-mc/dt-for-next (3f8ccf5f1a8c riscv: dts: microchip: remove spi-max-frequency property)
+$ git merge -m Merge branch 'dt-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git risc-v-mc/dt-for-next
+Auto-merging arch/riscv/boot/dts/microchip/mpfs.dtsi
+Merge made by the 'ort' strategy.
+ arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 ---
+ 1 file changed, 3 deletions(-)
+Merging s390/for-next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git s390/for-next
+Already up to date.
+Merging sh/for-next (8518e694203d sh: pgtable-3level: Fix cast to pointer from integer of different size)
+$ git merge -m Merge branch 'for-next' of git://git.libc.org/linux-sh sh/for-next
+Already up to date.
+Merging sparc-next/master (dd0d718152e4 Merge tag 'spi-fix-v5.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next.git sparc-next/master
+Already up to date.
+Merging uml/linux-next (2a4a62a14be1 um: Fix out-of-bounds read in LDT setup)
+$ git merge -m Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml.git uml/linux-next
+Already up to date.
+Merging xtensa/xtensa-for-next (a2d9b75b19dc xtensa: change '.bss' to '.section .bss')
+$ git merge -m Merge branch 'xtensa-for-next' of git://github.com/jcmvbkbc/linux-xtensa.git xtensa/xtensa-for-next
+Merge made by the 'ort' strategy.
+ arch/xtensa/kernel/entry.S           | 2 +-
+ arch/xtensa/kernel/time.c            | 1 +
+ arch/xtensa/platforms/xtfpga/setup.c | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+Merging pidfd/for-next (168f91289340 fs: account for group membership)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git pidfd/for-next
+Already up to date.
+Merging fscrypt/master (218d921b581e fscrypt: add new helper functions for test_dummy_encryption)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git fscrypt/master
+Already up to date.
+Merging fscache/fscache-next (0885eacdc81f Merge tag 'nfsd-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux)
+$ git merge -m Merge branch 'fscache-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git fscache/fscache-next
+Already up to date.
+Merging afs/afs-next (26291c54e111 Linux 5.17-rc2)
+$ git merge -m Merge branch 'afs-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git afs/afs-next
+Already up to date.
+Merging btrfs/for-next (df302b62096a Merge branch 'for-next-next-v5.19-20220622' into for-next-20220622)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git btrfs/for-next
+Auto-merging fs/btrfs/disk-io.c
+Merge made by the 'ort' strategy.
+ Documentation/filesystems/btrfs.rst  |  16 +-
+ arch/parisc/include/asm/cacheflush.h |   6 +-
+ arch/parisc/kernel/cache.c           |   2 +-
+ fs/btrfs/async-thread.h              |   1 -
+ fs/btrfs/backref.c                   |  88 ++--
+ fs/btrfs/backref.h                   |   3 +-
+ fs/btrfs/block-group.c               |   1 +
+ fs/btrfs/block-group.h               |   1 +
+ fs/btrfs/compression.c               |  59 +--
+ fs/btrfs/compression.h               |   7 +-
+ fs/btrfs/ctree.h                     |  69 ++-
+ fs/btrfs/delayed-inode.c             | 364 +++++++++++-----
+ fs/btrfs/delayed-inode.h             |  11 +
+ fs/btrfs/disk-io.c                   | 240 ++++-------
+ fs/btrfs/disk-io.h                   |  17 +-
+ fs/btrfs/extent-tree.c               |  98 ++---
+ fs/btrfs/extent_io.c                 | 683 ++++++++++++++----------------
+ fs/btrfs/extent_io.h                 |   6 -
+ fs/btrfs/file.c                      |  94 ++++-
+ fs/btrfs/inode.c                     | 585 +++++++++++++-------------
+ fs/btrfs/ioctl.c                     | 139 +++---
+ fs/btrfs/locking.c                   |   3 -
+ fs/btrfs/lzo.c                       |  28 +-
+ fs/btrfs/ordered-data.c              |  40 +-
+ fs/btrfs/ordered-data.h              |   5 +-
+ fs/btrfs/raid56.c                    | 792 ++++++++++++++++-------------------
+ fs/btrfs/raid56.h                    | 168 +++++++-
+ fs/btrfs/reflink.c                   |  29 +-
+ fs/btrfs/scrub.c                     |  71 ++--
+ fs/btrfs/send.c                      | 460 ++++++++++++++++----
+ fs/btrfs/send.h                      | 169 +++++---
+ fs/btrfs/space-info.c                |  34 +-
+ fs/btrfs/space-info.h                |   4 +
+ fs/btrfs/struct-funcs.c              |  11 +-
+ fs/btrfs/subpage.c                   |   4 +-
+ fs/btrfs/super.c                     |  28 +-
+ fs/btrfs/sysfs.c                     | 182 +++++++-
+ fs/btrfs/transaction.c               |  22 +
+ fs/btrfs/tree-log.c                  |  20 +-
+ fs/btrfs/tree-log.h                  |   3 +
+ fs/btrfs/volumes.c                   | 358 ++++++++--------
+ fs/btrfs/volumes.h                   |  47 ++-
+ fs/btrfs/zoned.c                     |  33 +-
+ fs/btrfs/zoned.h                     |   5 +
+ fs/btrfs/zstd.c                      |  42 +-
+ include/linux/highmem-internal.h     |  10 +-
+ include/trace/events/btrfs.h         | 158 +++++++
+ include/uapi/linux/btrfs.h           |  10 +-
+ mm/highmem.c                         |   2 +-
+ 49 files changed, 3081 insertions(+), 2147 deletions(-)
+Merging ceph/master (45d719fe7562 fscrypt: add fscrypt_context_for_new_inode)
+$ git merge -m Merge branch 'master' of git://github.com/ceph/ceph-client.git ceph/master
+Merge made by the 'ort' strategy.
+ fs/crypto/fname.c           | 36 ++++++++++++++++++++++++++++++------
+ fs/crypto/fscrypt_private.h |  9 +++------
+ fs/crypto/hooks.c           |  6 +++---
+ fs/crypto/policy.c          | 35 +++++++++++++++++++++++++++++------
+ fs/inode.c                  | 10 +++++++---
+ include/linux/fscrypt.h     |  5 +++++
+ 6 files changed, 77 insertions(+), 24 deletions(-)
+Merging cifs/for-next (b5a802831a48 cifs: periodically query network interfaces from server)
+$ git merge -m Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6.git cifs/for-next
+Merge made by the 'ort' strategy.
+ fs/cifs/cifs_debug.c |  12 ++--
+ fs/cifs/cifsglob.h   |  58 ++++++++++++++++-
+ fs/cifs/cifsproto.h  |   7 +++
+ fs/cifs/connect.c    |  38 ++++++++++-
+ fs/cifs/misc.c       |   9 ++-
+ fs/cifs/sess.c       | 157 +++++++++++++++++++++++++++++++++++-----------
+ fs/cifs/smb2ops.c    | 173 +++++++++++++++++++++++++++------------------------
+ fs/cifs/smb2pdu.c    |  21 +++++--
+ 8 files changed, 339 insertions(+), 136 deletions(-)
+Merging configfs/for-next (84ec758fb2da configfs: fix a race in configfs_{,un}register_subsystem())
+$ git merge -m Merge branch 'for-next' of git://git.infradead.org/users/hch/configfs.git configfs/for-next
+Already up to date.
+Merging ecryptfs/next (682a8e2b41ef Merge tag 'ecryptfs-5.13-rc1-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs.git ecryptfs/next
+Already up to date.
+Merging erofs/dev (94f870f13595 MAINTAINERS: erofs: add myself as reviewer)
+$ git merge -m Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git erofs/dev
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS | 2 ++
+ 1 file changed, 2 insertions(+)
+Merging exfat/dev (204e6ceaa103 exfat: use updated exfat_chain directly during renaming)
+$ git merge -m Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/exfat.git exfat/dev
+Merge made by the 'ort' strategy.
+ fs/exfat/namei.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+Merging ext3/for_next (4bca7e80b645 init: Initialize noop_backing_dev_info early)
+$ git merge -m Merge branch 'for_next' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs.git ext3/for_next
+Already up to date.
+Merging ext4/dev (729e657ab8d4 ext4: fix a doubled word "need" in a comment)
+$ git merge -m Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git ext4/dev
+Merge made by the 'ort' strategy.
+Merging f2fs/dev (82c7863ed95d f2fs: do not count ENOENT for error case)
+$ git merge -m Merge branch 'dev' of git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git f2fs/dev
+Merge made by the 'ort' strategy.
+ fs/f2fs/iostat.c | 31 ++++++++++++++++++-------------
+ fs/f2fs/namei.c  | 17 +++++++++++------
+ fs/f2fs/node.c   |  4 +++-
+ 3 files changed, 32 insertions(+), 20 deletions(-)
+Merging fsverity/fsverity (e6af1bb07704 fs-verity: Use struct_size() helper in enable_verity())
+$ git merge -m Merge branch 'fsverity' of git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git fsverity/fsverity
+Already up to date.
+Merging fuse/for-next (6b49bc9d8a5f fuse: avoid unnecessary spinlock bump)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git fuse/for-next
+Auto-merging fs/fuse/dax.c
+Auto-merging fs/fuse/dir.c
+Auto-merging fs/fuse/file.c
+Merge made by the 'ort' strategy.
+ fs/fuse/dax.c  |  2 +-
+ fs/fuse/dir.c  |  7 ++++++-
+ fs/fuse/file.c | 39 ++++++++++++++++++++++++++-------------
+ 3 files changed, 33 insertions(+), 15 deletions(-)
+Merging gfs2/for-next (565f82b57abe gfs2: Rewrap overlong comment in do_promote)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux-gfs2.git gfs2/for-next
+Merge made by the 'ort' strategy.
+ fs/gfs2/file.c  | 3 +--
+ fs/gfs2/glock.c | 7 ++++---
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+Merging jfs/jfs-next (e471e5942c00 fs/jfs: Remove dead code)
+$ git merge -m Merge branch 'jfs-next' of git://github.com/kleikamp/linux-shaggy.git jfs/jfs-next
+Already up to date.
+Merging ksmbd/ksmbd-for-next (06ee1c0aebd5 ksmbd: smbd: Remove useless license text when SPDX-License-Identifier is already used)
+$ git merge -m Merge branch 'ksmbd-for-next' of https://github.com/smfrench/smb3-kernel.git ksmbd/ksmbd-for-next
+Merge made by the 'ort' strategy.
+ fs/ksmbd/transport_rdma.c | 10 ----------
+ fs/ksmbd/transport_tcp.c  |  2 +-
+ 2 files changed, 1 insertion(+), 11 deletions(-)
+Merging nfs/linux-next (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'linux-next' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6.git nfs/linux-next
+Already up to date.
+Merging nfs-anna/linux-next (5ee3d10f84d0 NFSv4: Add FMODE_CAN_ODIRECT after successful open of a NFS4.x file)
+$ git merge -m Merge branch 'linux-next' of git://git.linux-nfs.org/projects/anna/linux-nfs.git nfs-anna/linux-next
+Already up to date.
+Merging nfsd/for-next (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux nfsd/for-next
+Already up to date.
+Merging ntfs3/master (f759942b72a9 fs/ntfs3: Add missing error check)
+$ git merge -m Merge branch 'master' of https://github.com/Paragon-Software-Group/linux-ntfs3.git ntfs3/master
+Auto-merging fs/ntfs3/file.c
+Auto-merging fs/ntfs3/inode.c
+Auto-merging fs/ntfs3/super.c
+Merge made by the 'ort' strategy.
+ fs/ntfs3/attrib.c  |  2 +-
+ fs/ntfs3/bitmap.c  |  4 +---
+ fs/ntfs3/file.c    |  1 -
+ fs/ntfs3/frecord.c | 49 +++++++++++++++++++++++++++++++++++++------------
+ fs/ntfs3/fslog.c   |  4 +++-
+ fs/ntfs3/index.c   | 27 ++++++++++-----------------
+ fs/ntfs3/inode.c   |  1 +
+ fs/ntfs3/record.c  |  5 ++---
+ fs/ntfs3/super.c   |  8 ++++----
+ fs/ntfs3/xattr.c   |  6 +++---
+ 10 files changed, 62 insertions(+), 45 deletions(-)
+Merging orangefs/for-next (40a74870b2d1 orangefs: Fix the size of a memory allocation in orangefs_bufmap_alloc())
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux orangefs/for-next
+Already up to date.
+Merging overlayfs/overlayfs-next (bc70682a497c ovl: support idmapped layers)
+$ git merge -m Merge branch 'overlayfs-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git overlayfs/overlayfs-next
+Already up to date.
+Merging ubifs/next (8c03a1c21d72 ubi: ubi_create_volume: Fix use-after-free when volume creation failed)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git ubifs/next
+Already up to date.
+Merging v9fs/9p-next (b0017602fdf6 9p: fix EBADF errors in cached mode)
+$ git merge -m Merge branch '9p-next' of git://github.com/martinetd/linux v9fs/9p-next
+Already up to date.
+Merging xfs/for-next (e89ab76d7e25 xfs: preserve DIFLAG2_NREXT64 when setting other inode attributes)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git xfs/for-next
+Already up to date.
+Merging zonefs/for-next (31a644b3c2ae documentation: zonefs: Document sysfs attributes)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git zonefs/for-next
+Already up to date.
+Merging iomap/iomap-for-next (e9c3a8e820ed iomap: don't invalidate folios after writeback errors)
+$ git merge -m Merge branch 'iomap-for-next' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git iomap/iomap-for-next
+Already up to date.
+Merging djw-vfs/vfs-for-next (49df34221804 fs: fix an infinite loop in iomap_fiemap)
+$ git merge -m Merge branch 'vfs-for-next' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git djw-vfs/vfs-for-next
+Already up to date.
+Merging file-locks/locks-next (80d8e4d3f313 fs/locks: fix fcntl_getlk64/fcntl_setlk64 stub prototypes)
+$ git merge -m Merge branch 'locks-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jlayton/linux.git file-locks/locks-next
+Auto-merging include/linux/fs.h
+Merge made by the 'ort' strategy.
+Merging vfs/for-next (e9921ffd594f Merge branches 'work.namei', 'work.mount' and 'work.fd' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git vfs/for-next
+Auto-merging fs/internal.h
+Auto-merging include/linux/fs.h
+Merge made by the 'ort' strategy.
+Merging printk/for-next (e1d9d8011258 Merge branch 'rework/kthreads' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/printk/linux.git printk/for-next
+Merge made by the 'ort' strategy.
+ kernel/printk/printk.c | 39 ++++++++++++++++++++++++++-------------
+ 1 file changed, 26 insertions(+), 13 deletions(-)
+Merging pci/next (20ba3070acb6 Merge branch 'pci/ctrl/vmd')
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/pci/qcom,pcie.yaml         |   2 +-
+ drivers/pci/controller/dwc/pcie-designware-host.c  |  14 +--
+ drivers/pci/controller/dwc/pcie-designware.h       |   2 +-
+ drivers/pci/controller/dwc/pcie-tegra194.c         |   1 +
+ drivers/pci/controller/pci-aardvark.c              | 112 +++++++++++++++++++--
+ drivers/pci/controller/pcie-brcmstb.c              |   2 +
+ drivers/pci/controller/pcie-mediatek-gen3.c        |   7 +-
+ drivers/pci/controller/pcie-microchip-host.c       |   2 +
+ drivers/pci/controller/vmd.c                       |   5 +-
+ drivers/pci/pcie/err.c                             |  12 ++-
+ drivers/pci/quirks.c                               |   3 +
+ drivers/pci/switch/switchtec.c                     |   7 +-
+ 12 files changed, 139 insertions(+), 30 deletions(-)
+Merging pstore/for-next/pstore (8126b1c73108 pstore: Don't use semaphores in always-atomic-context code)
+$ git merge -m Merge branch 'for-next/pstore' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git pstore/for-next/pstore
+Already up to date.
+Merging hid/for-next (6c55e6cce170 Merge branch 'for-5.20/nintendo' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git hid/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/input/elan,ekth6915.yaml   |  65 ++++++
+ drivers/hid/.kunitconfig                           |   5 +
+ drivers/hid/Kconfig                                |  16 ++
+ drivers/hid/Makefile                               |   3 +
+ drivers/hid/amd-sfh-hid/amd_sfh_pcie.c             |   3 +-
+ drivers/hid/hid-apple.c                            |  34 +++-
+ drivers/hid/hid-cp2112.c                           |   5 +
+ drivers/hid/hid-ids.h                              |   2 +
+ drivers/hid/hid-input.c                            |   2 +
+ drivers/hid/hid-logitech-hidpp.c                   |   2 +-
+ drivers/hid/hid-multitouch.c                       |  13 +-
+ drivers/hid/hid-nintendo.c                         |   5 +-
+ drivers/hid/hid-uclogic-core.c                     |   2 +
+ drivers/hid/hid-uclogic-params.c                   | 225 +++++++++++++++++++--
+ drivers/hid/hid-uclogic-rdesc-test.c               | 219 ++++++++++++++++++++
+ drivers/hid/hid-uclogic-rdesc.c                    | 124 +++++++++++-
+ drivers/hid/hid-uclogic-rdesc.h                    |  24 ++-
+ drivers/hid/i2c-hid/Kconfig                        |  15 ++
+ drivers/hid/i2c-hid/Makefile                       |   1 +
+ drivers/hid/i2c-hid/i2c-hid-of-elan.c              | 130 ++++++++++++
+ drivers/hid/intel-ish-hid/ipc/ipc.c                |   2 +-
+ drivers/hid/wacom_sys.c                            |   2 +-
+ drivers/hid/wacom_wac.c                            |  72 ++++---
+ 23 files changed, 909 insertions(+), 62 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/input/elan,ekth6915.yaml
+ create mode 100644 drivers/hid/.kunitconfig
+ create mode 100644 drivers/hid/hid-uclogic-rdesc-test.c
+ create mode 100644 drivers/hid/i2c-hid/i2c-hid-of-elan.c
+Merging i2c/i2c/for-next (bc1801ec0931 Merge branch 'i2c/for-mergewindow' into i2c/for-next)
+$ git merge -m Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/i2c/for-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/i2c/arm,i2c-versatile.yaml |  29 ++++
+ .../devicetree/bindings/i2c/i2c-nomadik.txt        |  23 ---
+ .../devicetree/bindings/i2c/i2c-ocores.txt         |  78 ---------
+ .../devicetree/bindings/i2c/i2c-qcom-cci.txt       |   7 +-
+ .../devicetree/bindings/i2c/i2c-versatile.txt      |  10 --
+ .../bindings/i2c/nuvoton,npcm7xx-i2c.yaml          |  25 ++-
+ .../bindings/i2c/opencores,i2c-ocores.yaml         | 113 +++++++++++++
+ .../devicetree/bindings/i2c/st,nomadik-i2c.yaml    | 113 +++++++++++++
+ MAINTAINERS                                        |   6 +-
+ drivers/i2c/busses/Kconfig                         |   8 +-
+ drivers/i2c/busses/Makefile                        |   2 +-
+ drivers/i2c/busses/i2c-hisi.c                      |   3 +-
+ drivers/i2c/busses/i2c-mv64xxx.c                   |  61 +++++--
+ drivers/i2c/busses/i2c-mxs.c                       |   2 +-
+ drivers/i2c/busses/i2c-npcm7xx.c                   | 176 ++++++++++++---------
+ drivers/i2c/busses/i2c-qcom-cci.c                  |  62 ++++++--
+ drivers/i2c/busses/i2c-xiic.c                      |   4 +-
+ drivers/i2c/i2c-core-base.c                        |   9 +-
+ 18 files changed, 487 insertions(+), 244 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml
+ delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
+ delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+ delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-versatile.txt
+ create mode 100644 Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml
+ create mode 100644 Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml
+Merging i3c/i3c/next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'i3c/next' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git i3c/i3c/next
+Already up to date.
+Merging dmi/dmi-for-next (f97a2103f1a7 firmware: dmi: Move product_sku info to the end of the modalias)
+$ git merge -m Merge branch 'dmi-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging.git dmi/dmi-for-next
+Already up to date.
+Merging hwmon-staging/hwmon-next (c59ed392a4a3 hwmon: (dell-smm) Improve assembly code)
+$ git merge -m Merge branch 'hwmon-next' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-staging/hwmon-next
+Merge made by the 'ort' strategy.
+ Documentation/ABI/testing/sysfs-class-hwmon        |    9 +
+ .../devicetree/bindings/hwmon/national,lm90.yaml   |  131 +
+ .../devicetree/bindings/trivial-devices.yaml       |    2 +
+ Documentation/hwmon/asus_ec_sensors.rst            |    1 +
+ Documentation/hwmon/index.rst                      |    1 +
+ Documentation/hwmon/lm90.rst                       |  233 +-
+ Documentation/hwmon/lt7182s.rst                    |   92 +
+ Documentation/hwmon/pmbus-core.rst                 |    9 +
+ drivers/hwmon/Kconfig                              |   21 +-
+ drivers/hwmon/asus-ec-sensors.c                    |   18 +
+ drivers/hwmon/dell-smm-hwmon.c                     |   93 +-
+ drivers/hwmon/f71882fg.c                           |    2 +
+ drivers/hwmon/gsc-hwmon.c                          |    3 +
+ drivers/hwmon/lm75.h                               |    3 +-
+ drivers/hwmon/lm90.c                               | 2558 +++++++++++++-------
+ drivers/hwmon/nct6775-platform.c                   |   12 +-
+ drivers/hwmon/occ/p9_sbe.c                         |    6 +-
+ drivers/hwmon/pmbus/Kconfig                        |    9 +
+ drivers/hwmon/pmbus/Makefile                       |    1 +
+ drivers/hwmon/pmbus/lt7182s.c                      |  195 ++
+ drivers/hwmon/pmbus/ltc2978.c                      |   44 +-
+ drivers/hwmon/pmbus/pmbus.h                        |   10 +-
+ drivers/hwmon/pmbus/pmbus_core.c                   |  446 +++-
+ drivers/hwmon/sch56xx-common.c                     |   44 +-
+ 24 files changed, 2963 insertions(+), 980 deletions(-)
+ create mode 100644 Documentation/hwmon/lt7182s.rst
+ create mode 100644 drivers/hwmon/pmbus/lt7182s.c
+Merging jc_docs/docs-next (387c67afccbb docs: arm: tcm: Fix typo in description of TCM and MMU usage)
+$ git merge -m Merge branch 'docs-next' of git://git.lwn.net/linux.git jc_docs/docs-next
+Already up to date.
+Merging v4l-dvb/master (945a9a8e448b media: pvrusb2: fix memory leak in pvr_probe)
+$ git merge -m Merge branch 'master' of git://linuxtv.org/media_tree.git v4l-dvb/master
+Auto-merging drivers/media/v4l2-core/v4l2-ioctl.c
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/media/vivid.rst          |  14 +
+ .../media/mediatek,vcodec-subdev-decoder.yaml      |  52 ++--
+ .../bindings/media/mediatek-jpeg-encoder.yaml      |   6 +
+ .../bindings/media/qcom,sdm660-camss.yaml          |   7 +
+ .../userspace-api/media/v4l/pixfmt-yuv-planar.rst  |  54 ++++
+ drivers/media/cec/core/cec-adap.c                  |   5 +-
+ drivers/media/cec/platform/cros-ec/cros-ec-cec.c   |   2 +
+ drivers/media/common/v4l2-tpg/v4l2-tpg-core.c      |  38 +++
+ drivers/media/i2c/adv7180.c                        |   5 +-
+ drivers/media/i2c/adv7604.c                        |   5 +-
+ drivers/media/i2c/tda1997x.c                       |   1 +
+ drivers/media/pci/cx88/cx88-core.c                 |  22 +-
+ drivers/media/pci/tw5864/tw5864-core.c             |  30 +-
+ drivers/media/pci/tw686x/tw686x-core.c             |  18 +-
+ drivers/media/platform/amphion/vdec.c              |   3 +-
+ drivers/media/platform/amphion/venc.c              |   3 +-
+ drivers/media/platform/amphion/vpu_cmds.c          |   3 +-
+ drivers/media/platform/amphion/vpu_core.c          |  11 +-
+ drivers/media/platform/amphion/vpu_dbg.c           |   2 +-
+ drivers/media/platform/amphion/vpu_malone.c        |  18 ++
+ drivers/media/platform/amphion/vpu_malone.h        |   1 +
+ drivers/media/platform/amphion/vpu_rpc.c           |   2 +-
+ drivers/media/platform/amphion/vpu_v4l2.c          |   6 +-
+ drivers/media/platform/atmel/atmel-isc-base.c      |  16 +-
+ drivers/media/platform/atmel/atmel-sama7g5-isc.c   |   2 +
+ .../media/platform/mediatek/jpeg/mtk_jpeg_core.c   |   3 +
+ .../platform/mediatek/vcodec/mtk_vcodec_dec.c      |  43 +++
+ .../platform/mediatek/vcodec/mtk_vcodec_dec_drv.c  |   8 +
+ .../platform/mediatek/vcodec/mtk_vcodec_dec_hw.c   |  12 +-
+ .../platform/mediatek/vcodec/mtk_vcodec_dec_hw.h   |   2 +
+ .../platform/mediatek/vcodec/mtk_vcodec_dec_pm.c   |  50 ++++
+ .../platform/mediatek/vcodec/mtk_vcodec_drv.h      |  14 +-
+ .../mediatek/vcodec/vdec/vdec_h264_req_multi_if.c  |  25 +-
+ .../mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c     | 200 ++++++++++++-
+ .../media/platform/mediatek/vcodec/vdec_drv_if.c   |   2 +-
+ .../media/platform/mediatek/vcodec/vdec_vpu_if.c   |   5 +
+ drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c  |  11 +-
+ drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.h  |   9 +-
+ drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c     | 316 ++++++++++++---------
+ drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h     |   4 +-
+ drivers/media/platform/qcom/camss/camss-csid.c     |   2 +-
+ drivers/media/platform/qcom/camss/camss-ispif.c    |  39 ++-
+ drivers/media/platform/qcom/camss/camss-vfe.c      |  34 ---
+ drivers/media/platform/qcom/camss/camss-vfe.h      |   3 -
+ drivers/media/platform/qcom/camss/camss.c          |  71 ++---
+ drivers/media/platform/qcom/camss/camss.h          |   7 +-
+ .../media/platform/renesas/rcar-vin/rcar-core.c    |   2 +-
+ .../media/platform/samsung/exynos-gsc/gsc-core.c   |   3 +-
+ .../media/platform/samsung/exynos-gsc/gsc-core.h   |   2 +-
+ .../platform/samsung/exynos4-is/fimc-is-errno.h    |   2 +-
+ .../media/platform/samsung/exynos4-is/mipi-csis.c  |   2 +-
+ .../media/platform/samsung/s5p-jpeg/jpeg-core.c    |   2 +-
+ .../media/platform/samsung/s5p-mfc/s5p_mfc_pm.c    |   3 +-
+ drivers/media/platform/st/sti/delta/delta-v4l2.c   |  24 +-
+ drivers/media/platform/ti/davinci/vpif.c           |   1 +
+ drivers/media/platform/ti/omap/omap_voutlib.c      |   4 +-
+ drivers/media/rc/igorplugusb.c                     |  19 +-
+ drivers/media/rc/iguanair.c                        |   5 +-
+ drivers/media/rc/imon_raw.c                        |  16 +-
+ drivers/media/rc/lirc_dev.c                        |   6 +-
+ drivers/media/rc/rc-main.c                         |   6 +-
+ drivers/media/rc/redrat3.c                         |   4 +-
+ drivers/media/rc/streamzap.c                       |   2 +-
+ drivers/media/rc/ttusbir.c                         |   4 +-
+ drivers/media/rc/xbox_remote.c                     |  10 +-
+ drivers/media/test-drivers/vivid/vivid-ctrls.c     |  14 +
+ drivers/media/usb/Kconfig                          |   1 -
+ drivers/media/usb/Makefile                         |   1 -
+ drivers/media/usb/airspy/airspy.c                  |  17 +-
+ drivers/media/usb/pvrusb2/pvrusb2-hdw.c            |   1 +
+ drivers/media/usb/usbtv/usbtv-video.c              |   5 +-
+ drivers/media/usb/usbtv/usbtv.h                    |   3 +-
+ drivers/media/v4l2-core/v4l2-common.c              |   1 +
+ drivers/media/v4l2-core/v4l2-ioctl.c               |   1 +
+ drivers/staging/media/Kconfig                      |  12 +-
+ drivers/staging/media/Makefile                     |   1 +
+ drivers/staging/media/atomisp/i2c/ov5693/ov5693.h  |   2 +-
+ drivers/staging/media/hantro/hantro_drv.c          |  12 +-
+ drivers/staging/media/hantro/hantro_g2_regs.h      |   2 +-
+ drivers/staging/media/hantro/hantro_hevc.c         |  30 ++
+ drivers/staging/media/hantro/hantro_hw.h           |  14 +
+ drivers/staging/media/hantro/hantro_v4l2.c         |   2 +-
+ drivers/staging/media/hantro/imx8m_vpu_hw.c        |  80 ++++--
+ drivers/staging/media/hantro/rockchip_vpu_hw.c     | 104 ++++---
+ drivers/staging/media/hantro/sama5d4_vdec_hw.c     |  40 ++-
+ drivers/staging/media/hantro/sunxi_vpu_hw.c        |  24 +-
+ .../{media/usb => staging/media}/stkwebcam/Kconfig |   8 +-
+ .../usb => staging/media}/stkwebcam/Makefile       |   2 +-
+ drivers/staging/media/stkwebcam/TODO               |  12 +
+ .../usb => staging/media}/stkwebcam/stk-sensor.c   |   0
+ .../usb => staging/media}/stkwebcam/stk-webcam.c   |   0
+ .../usb => staging/media}/stkwebcam/stk-webcam.h   |   0
+ drivers/staging/media/zoran/videocodec.c           |  93 +++---
+ drivers/staging/media/zoran/videocodec.h           |  15 +
+ drivers/staging/media/zoran/zoran.h                |  14 +
+ drivers/staging/media/zoran/zr36016.c              |  91 +++---
+ drivers/staging/media/zoran/zr36050.c              | 144 +++++-----
+ drivers/staging/media/zoran/zr36060.c              |  97 ++++---
+ include/media/tpg/v4l2-tpg.h                       |  16 ++
+ include/uapi/linux/videodev2.h                     |   1 +
+ 100 files changed, 1475 insertions(+), 688 deletions(-)
+ rename drivers/{media/usb => staging/media}/stkwebcam/Kconfig (68%)
+ rename drivers/{media/usb => staging/media}/stkwebcam/Makefile (63%)
+ create mode 100644 drivers/staging/media/stkwebcam/TODO
+ rename drivers/{media/usb => staging/media}/stkwebcam/stk-sensor.c (100%)
+ rename drivers/{media/usb => staging/media}/stkwebcam/stk-webcam.c (100%)
+ rename drivers/{media/usb => staging/media}/stkwebcam/stk-webcam.h (100%)
+Merging v4l-dvb-next/master (945a9a8e448b media: pvrusb2: fix memory leak in pvr_probe)
+$ git merge -m Merge branch 'master' of git://linuxtv.org/mchehab/media-next.git v4l-dvb-next/master
+Already up to date.
+Merging pm/linux-next (22f7e9edec50 Merge branch 'pm-sleep' into linux-next)
+$ git merge -m Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git pm/linux-next
+Auto-merging drivers/platform/x86/thinkpad_acpi.c
+Merge made by the 'ort' strategy.
+ drivers/acpi/acpi_video.c            |  41 +++++------
+ drivers/acpi/apei/apei-base.c        |   2 +-
+ drivers/acpi/bus.c                   |  13 ++++
+ drivers/acpi/container.c             |  17 ++---
+ drivers/acpi/device_pm.c             |  22 ++++++
+ drivers/acpi/glue.c                  | 133 ++++++++++++++++++++++++-----------
+ drivers/acpi/processor_idle.c        |   6 +-
+ drivers/acpi/property.c              |  45 ++++++------
+ drivers/acpi/scan.c                  |  59 ++++++++--------
+ drivers/cpufreq/cpufreq.c            |  27 +++----
+ drivers/cpuidle/governors/haltpoll.c |   3 +
+ drivers/mmc/host/sdhci-acpi.c        |   7 +-
+ drivers/mmc/host/sdhci-pci-core.c    |  11 +--
+ drivers/platform/x86/thinkpad_acpi.c |  53 +++++++-------
+ drivers/soundwire/slave.c            | 117 +++++++++++++++++-------------
+ drivers/thermal/thermal_core.c       |  18 ++---
+ drivers/thunderbolt/acpi.c           |  29 ++------
+ drivers/usb/core/usb-acpi.c          |  18 +----
+ include/acpi/acpi_bus.h              |   6 ++
+ include/trace/events/power.h         |  29 ++++++++
+ kernel/power/hibernate.c             |   2 +-
+ 21 files changed, 374 insertions(+), 284 deletions(-)
+Merging cpufreq-arm/cpufreq/arm/linux-next (c40bffd189af cpufreq: Add MT8186 to cpufreq-dt-platdev blocklist)
+$ git merge -m Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git cpufreq-arm/cpufreq/arm/linux-next
+Merge made by the 'ort' strategy.
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ drivers/cpufreq/pmac32-cpufreq.c     | 4 ++++
+ drivers/cpufreq/qcom-cpufreq-hw.c    | 6 ++++++
+ drivers/cpufreq/qoriq-cpufreq.c      | 1 +
+ 4 files changed, 12 insertions(+)
+Merging cpupower/cpupower (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'cpupower' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git cpupower/cpupower
+Already up to date.
+Merging devfreq/devfreq-next (9f3ec0f65421 PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver)
+$ git merge -m Merge branch 'devfreq-next' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git devfreq/devfreq-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../bindings/interconnect/mediatek,cci.yaml        | 141 +++++++
+ MAINTAINERS                                        |   1 +
+ drivers/devfreq/Kconfig                            |  10 +
+ drivers/devfreq/Makefile                           |   1 +
+ drivers/devfreq/mtk-cci-devfreq.c                  | 440 +++++++++++++++++++++
+ 5 files changed, 593 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
+ create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
+Merging opp/opp/linux-next (914c6294f3e0 OPP: Provide a simple implementation to configure multiple clocks)
+$ git merge -m Merge branch 'opp/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git opp/opp/linux-next
+Auto-merging drivers/tty/serial/qcom_geni_serial.c
+Merge made by the 'ort' strategy.
+ drivers/cpufreq/cpufreq-dt.c                   |   14 +-
+ drivers/cpufreq/imx-cpufreq-dt.c               |   12 +-
+ drivers/cpufreq/qcom-cpufreq-nvmem.c           |  107 +-
+ drivers/cpufreq/sti-cpufreq.c                  |   22 +-
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c         |   11 +-
+ drivers/cpufreq/tegra20-cpufreq.c              |   10 +-
+ drivers/cpufreq/ti-cpufreq.c                   |   38 +-
+ drivers/devfreq/exynos-bus.c                   |   23 +-
+ drivers/devfreq/sun8i-a33-mbus.c               |    8 +-
+ drivers/devfreq/tegra30-devfreq.c              |    8 +-
+ drivers/gpu/drm/lima/lima_devfreq.c            |   12 +-
+ drivers/gpu/drm/msm/adreno/a5xx_gpu.c          |    8 +-
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.c          |   10 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c        |    6 +-
+ drivers/gpu/drm/msm/dp/dp_ctrl.c               |    6 +-
+ drivers/gpu/drm/msm/dsi/dsi_host.c             |    6 +-
+ drivers/gpu/drm/panfrost/panfrost_devfreq.c    |    9 +-
+ drivers/gpu/drm/tegra/gr3d.c                   |    6 +-
+ drivers/media/platform/qcom/venus/pm_helpers.c |   18 +-
+ drivers/memory/tegra/tegra124-emc.c            |   14 +-
+ drivers/mmc/host/sdhci-msm.c                   |    6 +-
+ drivers/opp/core.c                             | 1432 +++++++++++-------------
+ drivers/opp/cpu.c                              |   12 +-
+ drivers/opp/debugfs.c                          |   27 +-
+ drivers/opp/of.c                               |   91 +-
+ drivers/opp/opp.h                              |   29 +-
+ drivers/opp/ti-opp-supply.c                    |   78 +-
+ drivers/soc/tegra/common.c                     |   14 +-
+ drivers/soc/tegra/pmc.c                        |    8 +-
+ drivers/spi/spi-geni-qcom.c                    |    6 +-
+ drivers/spi/spi-qcom-qspi.c                    |    6 +-
+ drivers/tty/serial/qcom_geni_serial.c          |    6 +-
+ include/linux/pm_opp.h                         |  166 +--
+ 33 files changed, 1066 insertions(+), 1163 deletions(-)
+Merging thermal/thermal/linux-next (4768f717d85c dt-bindings: thermal: rcar-gen3-thermal: Add r8a779f0 support)
+$ git merge -m Merge branch 'thermal/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git thermal/thermal/linux-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../bindings/thermal/qcom,spmi-temp-alarm.yaml     | 85 ++++++++++++++++++++++
+ .../bindings/thermal/qcom-spmi-temp-alarm.txt      | 51 -------------
+ .../bindings/thermal/rcar-gen3-thermal.yaml        | 36 +++++----
+ MAINTAINERS                                        |  1 +
+ drivers/thermal/cpufreq_cooling.c                  | 77 +++++++-------------
+ drivers/thermal/devfreq_cooling.c                  | 27 +++----
+ drivers/thermal/rcar_gen3_thermal.c                |  4 +-
+ include/trace/events/thermal.h                     | 28 ++-----
+ 8 files changed, 152 insertions(+), 157 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/thermal/qcom,spmi-temp-alarm.yaml
+ delete mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-temp-alarm.txt
+Merging ieee1394/for-next (54b3bd99f094 firewire: nosy: switch from 'pci_' to 'dma_' API)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git ieee1394/for-next
+Already up to date.
+Merging dlm/next (8e51ec6146fd dlm: use kref_put_lock in __put_lkb)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm.git dlm/next
+Already up to date.
+Merging rdma/for-next (686141bc02f2 Merge branch 'mlx5-next' into wip/leon-for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git rdma/for-next
+Auto-merging drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+Merge made by the 'ort' strategy.
+ drivers/infiniband/core/cma.c                     | 230 ++++++++++++++++++++--
+ drivers/infiniband/core/cma_priv.h                |   1 +
+ drivers/infiniband/hw/hfi1/pio_copy.c             |   2 +-
+ drivers/infiniband/hw/mlx5/cq.c                   |   4 +
+ drivers/infiniband/hw/mlx5/dm.c                   |  53 +++--
+ drivers/infiniband/hw/mlx5/mlx5_ib.h              |  12 +-
+ drivers/infiniband/hw/mlx5/mr.c                   |   1 +
+ drivers/infiniband/hw/mlx5/umr.c                  |  78 +++++++-
+ drivers/infiniband/hw/usnic/usnic_uiom.c          |   2 +-
+ drivers/infiniband/sw/rxe/rxe_pool.c              |   4 +-
+ drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c  |  33 ++++
+ drivers/net/ethernet/mellanox/mlx5/core/fs_core.c |  18 +-
+ drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c  |  42 ++++
+ drivers/net/ethernet/mellanox/mlx5/core/main.c    |   7 -
+ include/linux/mlx5/device.h                       |  36 ++--
+ include/linux/mlx5/driver.h                       |   1 +
+ include/linux/mlx5/fs.h                           |  14 ++
+ include/linux/mlx5/mlx5_ifc.h                     | 151 ++++++++++++--
+ include/rdma/rdma_cm.h                            |   1 +
+ include/uapi/rdma/mlx5_user_ioctl_verbs.h         |   1 +
+ 20 files changed, 599 insertions(+), 92 deletions(-)
+Merging net-next/master (6dd4142fb5a9 Merge branch 'af_unix-per-netns-socket-hash')
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git net-next/master
+Auto-merging MAINTAINERS
+Auto-merging arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+CONFLICT (content): Merge conflict in arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+Auto-merging drivers/net/bonding/bond_main.c
+Auto-merging drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+Auto-merging drivers/net/phy/smsc.c
+Auto-merging drivers/net/wireless/realtek/rtw88/rtw8821c.c
+Auto-merging kernel/bpf/btf.c
+Auto-merging kernel/trace/bpf_trace.c
+Auto-merging net/core/dev.c
+Auto-merging net/core/filter.c
+Auto-merging net/core/net-sysfs.c
+Auto-merging net/ipv4/ping.c
+Auto-merging net/ipv6/ip6_gre.c
+Resolved 'arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master d11b98215b9b] Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
+$ git diff -M --stat --summary HEAD^..
+ Documentation/bpf/btf.rst                          |  43 +-
+ Documentation/bpf/instruction-set.rst              |   2 +-
+ .../bindings/net/dsa/mediatek,mt7530.yaml          | 404 +++++++++
+ .../devicetree/bindings/net/dsa/mt7530.txt         | 327 -------
+ .../devicetree/bindings/net/ti,dp83867.yaml        |  18 +-
+ .../devicetree/bindings/net/xlnx,emaclite.yaml     |  63 ++
+ Documentation/networking/tls.rst                   |  25 +
+ MAINTAINERS                                        |   1 -
+ arch/arm/net/bpf_jit_32.c                          |  16 -
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts |  48 +
+ arch/riscv/net/bpf_jit.h                           |   1 +
+ arch/riscv/net/bpf_jit_core.c                      |   8 +-
+ drivers/atm/iphase.c                               |   2 +-
+ drivers/net/bonding/bond_main.c                    |  24 +-
+ drivers/net/bonding/bond_netlink.c                 | 101 ++-
+ drivers/net/bonding/bond_options.c                 |  32 +-
+ drivers/net/dsa/microchip/ksz8.h                   |   3 +-
+ drivers/net/dsa/microchip/ksz8795.c                | 233 ++---
+ drivers/net/dsa/microchip/ksz8795_reg.h            |  16 -
+ drivers/net/dsa/microchip/ksz9477.c                | 181 ++--
+ drivers/net/dsa/microchip/ksz9477_reg.h            |   1 -
+ drivers/net/dsa/microchip/ksz_common.c             | 342 +++++--
+ drivers/net/dsa/microchip/ksz_common.h             |  80 +-
+ drivers/net/dsa/mt7530.c                           |  82 +-
+ drivers/net/dsa/mt7530.h                           |   1 -
+ drivers/net/dsa/ocelot/felix_vsc9959.c             |  83 +-
+ drivers/net/dsa/qca/ar9331.c                       |  17 +-
+ drivers/net/dsa/realtek/rtl8365mb.c                | 299 ++++---
+ drivers/net/dsa/sja1105/sja1105_main.c             |   2 +-
+ drivers/net/eql.c                                  |   4 +-
+ drivers/net/ethernet/altera/altera_utils.h         |   5 +-
+ drivers/net/ethernet/atheros/ag71xx.c              |   2 +-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c       |   4 +-
+ drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c    |   2 +-
+ drivers/net/ethernet/cadence/macb_main.c           |   4 +-
+ drivers/net/ethernet/cadence/macb_ptp.c            |   7 +-
+ drivers/net/ethernet/huawei/hinic/hinic_sriov.c    |   6 -
+ drivers/net/ethernet/intel/e1000/e1000_hw.c        |   4 +-
+ drivers/net/ethernet/intel/fm10k/fm10k_mbx.c       |   2 +-
+ drivers/net/ethernet/intel/i40e/i40e.h             |   1 +
+ drivers/net/ethernet/intel/i40e/i40e_ethtool.c     |   9 +
+ drivers/net/ethernet/intel/i40e/i40e_main.c        | 135 ++-
+ drivers/net/ethernet/intel/i40e/i40e_txrx.c        |  87 +-
+ drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c |   8 +-
+ drivers/net/ethernet/intel/iavf/iavf.h             |   7 +-
+ drivers/net/ethernet/intel/iavf/iavf_main.c        | 127 ++-
+ drivers/net/ethernet/intel/iavf/iavf_virtchnl.c    |  61 +-
+ drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c  |   4 +-
+ drivers/net/ethernet/intel/ice/ice_gnss.c          |  11 +-
+ drivers/net/ethernet/intel/ice/ice_lib.c           |   5 +-
+ drivers/net/ethernet/intel/ice/ice_sriov.c         |  10 -
+ drivers/net/ethernet/intel/ice/ice_virtchnl.c      | 121 ++-
+ drivers/net/ethernet/intel/igb/e1000_defines.h     |   3 -
+ drivers/net/ethernet/intel/igb/e1000_regs.h        |   1 -
+ drivers/net/ethernet/intel/ixgb/ixgb_hw.c          |   4 +-
+ drivers/net/ethernet/intel/ixgbe/ixgbe.h           |  34 +
+ drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c     |   2 +-
+ drivers/net/ethernet/intel/ixgbe/ixgbe_common.c    |   2 +-
+ drivers/net/ethernet/intel/ixgbe/ixgbe_main.c      |  86 ++
+ drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c     |   2 +-
+ drivers/net/ethernet/intel/ixgbe/ixgbe_type.h      |   7 +
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c        |  11 +-
+ .../ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c |   4 +-
+ drivers/net/ethernet/mellanox/mlxsw/Makefile       |   1 -
+ drivers/net/ethernet/mellanox/mlxsw/cmd.h          |  53 +-
+ drivers/net/ethernet/mellanox/mlxsw/core.c         |  12 -
+ drivers/net/ethernet/mellanox/mlxsw/core.h         |  12 +-
+ drivers/net/ethernet/mellanox/mlxsw/minimal.c      |   3 +-
+ drivers/net/ethernet/mellanox/mlxsw/pci.c          |  42 +-
+ drivers/net/ethernet/mellanox/mlxsw/port.h         |   2 -
+ drivers/net/ethernet/mellanox/mlxsw/reg.h          | 987 +++++++--------------
+ drivers/net/ethernet/mellanox/mlxsw/spectrum.c     |  38 +-
+ drivers/net/ethernet/mellanox/mlxsw/spectrum.h     |   2 +-
+ drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c | 124 ++-
+ .../net/ethernet/mellanox/mlxsw/spectrum_router.c  | 875 ++++++------------
+ .../net/ethernet/mellanox/mlxsw/spectrum_router.h  |  76 +-
+ .../ethernet/mellanox/mlxsw/spectrum_router_xm.c   | 812 -----------------
+ .../ethernet/mellanox/mlxsw/spectrum_switchdev.c   | 162 +++-
+ .../net/ethernet/mellanox/mlxsw/spectrum_trap.c    |   8 +-
+ drivers/net/ethernet/mellanox/mlxsw/trap.h         |   4 +-
+ drivers/net/ethernet/microchip/lan743x_ethtool.c   |  63 +-
+ drivers/net/ethernet/microchip/lan743x_ethtool.h   |  26 +
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+ drivers/net/ethernet/microsoft/mana/mana.h         |  70 ++
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+ drivers/net/ipa/gsi.c                              | 229 ++---
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+ .../testing/selftests/bpf/progs/core_reloc_types.h |  78 ++
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+ tools/testing/selftests/bpf/test_btf.h             |   1 +
+ tools/testing/selftests/bpf/test_xdping.sh         |   4 +
+ tools/testing/selftests/bpf/xdp_synproxy.c         | 466 ++++++++++
+ .../drivers/net/mlxsw/rif_counter_scale.sh         | 107 +++
+ .../drivers/net/mlxsw/spectrum-2/resource_scale.sh |  31 +-
+ .../net/mlxsw/spectrum-2/rif_counter_scale.sh      |   1 +
+ .../net/mlxsw/spectrum-2/tc_flower_scale.sh        |  15 +-
+ .../drivers/net/mlxsw/spectrum/resource_scale.sh   |  29 +-
+ .../net/mlxsw/spectrum/rif_counter_scale.sh        |  34 +
+ .../selftests/drivers/net/mlxsw/tc_flower_scale.sh |  17 +
+ .../net/forwarding/mirror_gre_bridge_1q_lag.sh     |   7 +-
+ 446 files changed, 11988 insertions(+), 6972 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+ delete mode 100644 Documentation/devicetree/bindings/net/dsa/mt7530.txt
+ create mode 100644 Documentation/devicetree/bindings/net/xlnx,emaclite.yaml
+ delete mode 100644 drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c
+ delete mode 100644 drivers/net/wireless/realtek/rtw88/rtw8723de.h
+ delete mode 100644 drivers/net/wireless/realtek/rtw88/rtw8821ce.h
+ delete mode 100644 drivers/net/wireless/realtek/rtw88/rtw8822be.h
+ delete mode 100644 drivers/net/wireless/realtek/rtw88/rtw8822ce.h
+ create mode 100644 include/net/dropreason.h
+ create mode 100644 net/core/.gitignore
+ create mode 100644 tools/testing/selftests/bpf/benchs/bench_bpf_hashmap_full_update.c
+ create mode 100755 tools/testing/selftests/bpf/benchs/run_bench_bpf_hashmap_full_update.sh
+ create mode 100644 tools/testing/selftests/bpf/prog_tests/libbpf_str.c
+ create mode 100644 tools/testing/selftests/bpf/prog_tests/xdp_synproxy.c
+ create mode 100644 tools/testing/selftests/bpf/progs/bpf_hashmap_full_update_bench.c
+ create mode 100644 tools/testing/selftests/bpf/progs/btf__core_reloc_enum64val.c
+ create mode 100644 tools/testing/selftests/bpf/progs/btf__core_reloc_enum64val___diff.c
+ create mode 100644 tools/testing/selftests/bpf/progs/btf__core_reloc_enum64val___err_missing.c
+ create mode 100644 tools/testing/selftests/bpf/progs/btf__core_reloc_enum64val___val3_missing.c
+ create mode 100644 tools/testing/selftests/bpf/progs/test_core_reloc_enum64val.c
+ create mode 100644 tools/testing/selftests/bpf/progs/xdp_synproxy_kern.c
+ create mode 100644 tools/testing/selftests/bpf/xdp_synproxy.c
+ create mode 100644 tools/testing/selftests/drivers/net/mlxsw/rif_counter_scale.sh
+ create mode 120000 tools/testing/selftests/drivers/net/mlxsw/spectrum-2/rif_counter_scale.sh
+ create mode 100644 tools/testing/selftests/drivers/net/mlxsw/spectrum/rif_counter_scale.sh
+Merging bpf-next/for-next (772251742262 samples/bpf: fixup some tools to be able to support xdp multibuffer)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git bpf-next/for-next
+Auto-merging arch/x86/net/bpf_jit_comp.c
+Auto-merging net/unix/af_unix.c
+Merge made by the 'ort' strategy.
+ arch/arm64/net/bpf_jit_comp.c                      |   9 +-
+ arch/x86/net/bpf_jit_comp.c                        |   6 +
+ include/linux/bpf.h                                |   3 +
+ include/linux/bpf_verifier.h                       |  12 +
+ include/linux/filter.h                             |   1 +
+ include/linux/net.h                                |   4 +
+ include/net/tcp.h                                  |   1 +
+ include/net/udp.h                                  |   3 +-
+ kernel/bpf/bpf_iter.c                              |   9 +-
+ kernel/bpf/core.c                                  |   6 +
+ kernel/bpf/verifier.c                              | 183 +++++++++++-
+ kernel/trace/trace_uprobe.c                        |   2 +
+ net/core/skmsg.c                                   |  48 ++-
+ net/ipv4/af_inet.c                                 |   3 +-
+ net/ipv4/tcp.c                                     |  44 +++
+ net/ipv4/udp.c                                     |  11 +-
+ net/ipv6/af_inet6.c                                |   3 +-
+ net/unix/af_unix.c                                 |  23 +-
+ samples/bpf/xdp1_kern.c                            |  11 +-
+ samples/bpf/xdp2_kern.c                            |  11 +-
+ samples/bpf/xdp_tx_iptunnel_kern.c                 |   2 +-
+ tools/testing/selftests/bpf/config                 |   6 +
+ tools/testing/selftests/bpf/prog_tests/bpf_loop.c  |  62 ++++
+ tools/testing/selftests/bpf/prog_tests/btf.c       |   1 -
+ tools/testing/selftests/bpf/progs/bpf_loop.c       | 114 +++++++
+ tools/testing/selftests/bpf/test_btf.h             |   2 +
+ tools/testing/selftests/bpf/test_verifier.c        | 328 +++++++++++++++++++--
+ .../selftests/bpf/verifier/bpf_loop_inline.c       | 252 ++++++++++++++++
+ 28 files changed, 1070 insertions(+), 90 deletions(-)
+ create mode 100644 tools/testing/selftests/bpf/verifier/bpf_loop_inline.c
+Merging ipsec-next/master (0f9008e5c510 Merge  branch 'Be explicit with XFRM offload direction')
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git ipsec-next/master
+Already up to date.
+Merging mlx5-next/mlx5-next (cdcdce948d64 net/mlx5: Add bits and fields to support enhanced CQE compression)
+$ git merge -m Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git mlx5-next/mlx5-next
+Already up to date.
+Merging netfilter-next/master (677fb7525331 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next.git netfilter-next/master
+Already up to date.
+Merging ipvs-next/master (677fb7525331 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs-next.git ipvs-next/master
+Already up to date.
+Merging bluetooth/master (d9cc9d78ca85 Bluetooth: mgmt: Fix refresh cached connection info)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git bluetooth/master
+Auto-merging include/net/bluetooth/hci_core.h
+Auto-merging net/bluetooth/hci_core.c
+Auto-merging net/bluetooth/hci_sync.c
+Auto-merging net/bluetooth/mgmt.c
+Merge made by the 'ort' strategy.
+ .../bindings/net/broadcom-bluetooth.yaml           |  8 ++
+ drivers/bluetooth/btbcm.c                          | 33 +++++++--
+ drivers/bluetooth/btbcm.h                          |  8 +-
+ drivers/bluetooth/btusb.c                          |  3 +
+ drivers/bluetooth/hci_bcm.c                        | 17 ++++-
+ drivers/bluetooth/hci_intel.c                      |  6 +-
+ drivers/bluetooth/hci_qca.c                        |  2 +-
+ include/net/bluetooth/hci.h                        |  1 +
+ include/net/bluetooth/hci_core.h                   | 13 ++++
+ net/bluetooth/eir.c                                | 41 +++++++----
+ net/bluetooth/hci_conn.c                           |  3 +
+ net/bluetooth/hci_core.c                           | 86 ++++++++++++++--------
+ net/bluetooth/hci_event.c                          |  9 ++-
+ net/bluetooth/hci_sock.c                           | 11 ++-
+ net/bluetooth/hci_sync.c                           | 66 +++++++++++------
+ net/bluetooth/l2cap_core.c                         |  1 +
+ net/bluetooth/mgmt.c                               | 14 ++--
+ 17 files changed, 226 insertions(+), 96 deletions(-)
+Merging wireless-next/for-next (683a4647a7a3 wifi: rtw89: 8852a: rfk: fix div 0 exception)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git wireless-next/for-next
+Auto-merging drivers/net/wireless/marvell/mwifiex/11h.c
+Auto-merging drivers/net/wireless/marvell/mwifiex/cfg80211.c
+Merge made by the 'ort' strategy.
+ drivers/net/wireless/admtek/adm8211.c              |    2 +-
+ drivers/net/wireless/ath/ar5523/ar5523.c           |   12 +-
+ drivers/net/wireless/ath/ath10k/core.c             |   11 +-
+ drivers/net/wireless/ath/ath10k/core.h             |    1 +
+ drivers/net/wireless/ath/ath10k/htt_rx.c           |    8 +-
+ drivers/net/wireless/ath/ath10k/htt_tx.c           |   61 +-
+ drivers/net/wireless/ath/ath10k/mac.c              |  113 +-
+ drivers/net/wireless/ath/ath10k/qmi.c              |    4 +-
+ drivers/net/wireless/ath/ath10k/snoc.c             |    5 +-
+ drivers/net/wireless/ath/ath10k/txrx.c             |   15 +-
+ drivers/net/wireless/ath/ath10k/wmi-tlv.c          |    2 +-
+ drivers/net/wireless/ath/ath10k/wmi.c              |    4 +-
+ drivers/net/wireless/ath/ath11k/ahb.c              |    4 +-
+ drivers/net/wireless/ath/ath11k/core.c             |   16 +-
+ drivers/net/wireless/ath/ath11k/core.h             |    6 +-
+ drivers/net/wireless/ath/ath11k/debug.h            |    4 +-
+ .../net/wireless/ath/ath11k/debugfs_htt_stats.c    |   88 +-
+ .../net/wireless/ath/ath11k/debugfs_htt_stats.h    |   39 +
+ drivers/net/wireless/ath/ath11k/dp_rx.c            |    8 +-
+ drivers/net/wireless/ath/ath11k/hal_rx.c           |    2 +-
+ drivers/net/wireless/ath/ath11k/htc.c              |    4 +-
+ drivers/net/wireless/ath/ath11k/mac.c              |   64 +-
+ drivers/net/wireless/ath/ath11k/pci.c              |    2 +
+ drivers/net/wireless/ath/ath11k/qmi.c              |    6 +-
+ drivers/net/wireless/ath/ath11k/wmi.c              |    6 +-
+ drivers/net/wireless/ath/ath5k/base.c              |    2 +-
+ drivers/net/wireless/ath/ath5k/mac80211-ops.c      |   14 +-
+ drivers/net/wireless/ath/ath5k/phy.c               |    2 +-
+ drivers/net/wireless/ath/ath6kl/cfg80211.c         |    8 +-
+ drivers/net/wireless/ath/ath6kl/wmi.h              |    2 +-
+ drivers/net/wireless/ath/ath9k/beacon.c            |   15 +-
+ drivers/net/wireless/ath/ath9k/dfs.c               |    2 +-
+ drivers/net/wireless/ath/ath9k/htc_drv_beacon.c    |    4 +-
+ drivers/net/wireless/ath/ath9k/htc_drv_main.c      |   18 +-
+ drivers/net/wireless/ath/ath9k/main.c              |   12 +-
+ drivers/net/wireless/ath/carl9170/main.c           |    4 +-
+ drivers/net/wireless/ath/carl9170/tx.c             |    2 +-
+ drivers/net/wireless/ath/wcn36xx/main.c            |   22 +-
+ drivers/net/wireless/ath/wcn36xx/smd.c             |    2 +-
+ drivers/net/wireless/ath/wil6210/cfg80211.c        |    9 +-
+ drivers/net/wireless/ath/wil6210/wmi.c             |    4 +-
+ drivers/net/wireless/atmel/at76c50x-usb.c          |    2 +-
+ drivers/net/wireless/broadcom/b43/main.c           |    6 +-
+ drivers/net/wireless/broadcom/b43legacy/main.c     |    4 +-
+ .../broadcom/brcm80211/brcmfmac/cfg80211.c         |   10 +-
+ .../broadcom/brcm80211/brcmsmac/mac80211_if.c      |   18 +-
+ drivers/net/wireless/intel/iwlegacy/3945-mac.c     |    6 +-
+ drivers/net/wireless/intel/iwlegacy/4965-rs.c      |    5 +-
+ drivers/net/wireless/intel/iwlegacy/4965.c         |    6 +-
+ drivers/net/wireless/intel/iwlegacy/common.c       |   18 +-
+ drivers/net/wireless/intel/iwlegacy/common.h       |    2 +-
+ drivers/net/wireless/intel/iwlwifi/dvm/agn.h       |    2 +-
+ drivers/net/wireless/intel/iwlwifi/dvm/lib.c       |    4 +-
+ drivers/net/wireless/intel/iwlwifi/dvm/main.c      |    4 +-
+ drivers/net/wireless/intel/iwlwifi/dvm/rxon.c      |   26 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/coex.c      |   10 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/d3.c        |    4 +-
+ .../net/wireless/intel/iwlwifi/mvm/debugfs-vif.c   |    4 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c   |    2 +-
+ .../net/wireless/intel/iwlwifi/mvm/ftm-initiator.c |   12 +-
+ .../net/wireless/intel/iwlwifi/mvm/ftm-responder.c |    4 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/mac-ctxt.c  |   24 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c  |   88 +-
+ .../net/wireless/intel/iwlwifi/mvm/offloading.c    |    6 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/ops.c       |    2 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/power.c     |    4 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/quota.c     |    4 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/rs.c        |    2 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/scan.c      |    4 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/sf.c        |    6 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/sta.c       |    2 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/tdls.c      |    4 +-
+ .../net/wireless/intel/iwlwifi/mvm/time-event.c    |   12 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/tx.c        |    2 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/utils.c     |    6 +-
+ drivers/net/wireless/intersil/p54/main.c           |    8 +-
+ drivers/net/wireless/mac80211_hwsim.c              |  245 +++--
+ drivers/net/wireless/mac80211_hwsim.h              |    5 +-
+ drivers/net/wireless/marvell/libertas/mesh.c       |   10 +-
+ drivers/net/wireless/marvell/libertas_tf/main.c    |    6 +-
+ drivers/net/wireless/marvell/mwifiex/11h.c         |    2 +-
+ drivers/net/wireless/marvell/mwifiex/cfg80211.c    |   18 +-
+ drivers/net/wireless/marvell/mwl8k.c               |   14 +-
+ drivers/net/wireless/mediatek/mt76/mac80211.c      |    4 +-
+ drivers/net/wireless/mediatek/mt76/mt7603/beacon.c |    2 +-
+ drivers/net/wireless/mediatek/mt76/mt7603/main.c   |    4 +-
+ drivers/net/wireless/mediatek/mt76/mt7615/main.c   |    4 +-
+ drivers/net/wireless/mediatek/mt76/mt7615/mcu.c    |    8 +-
+ .../net/wireless/mediatek/mt76/mt76_connac_mcu.c   |   10 +-
+ drivers/net/wireless/mediatek/mt76/mt76x02.h       |    2 +-
+ .../net/wireless/mediatek/mt76/mt76x02_beacon.c    |    2 +-
+ drivers/net/wireless/mediatek/mt76/mt76x02_util.c  |    2 +-
+ drivers/net/wireless/mediatek/mt76/mt7915/main.c   |    4 +-
+ drivers/net/wireless/mediatek/mt76/mt7915/mcu.c    |   12 +-
+ drivers/net/wireless/mediatek/mt76/mt7921/main.c   |    4 +-
+ drivers/net/wireless/mediatek/mt76/mt7921/mcu.c    |    4 +-
+ drivers/net/wireless/mediatek/mt7601u/main.c       |    2 +-
+ drivers/net/wireless/mediatek/mt7601u/phy.c        |    9 +-
+ drivers/net/wireless/microchip/wilc1000/cfg80211.c |    3 +-
+ drivers/net/wireless/purelifi/plfxlc/mac.c         |    8 +-
+ drivers/net/wireless/quantenna/qtnfmac/cfg80211.c  |   14 +-
+ drivers/net/wireless/quantenna/qtnfmac/commands.c  |    2 +-
+ drivers/net/wireless/quantenna/qtnfmac/event.c     |   15 +-
+ drivers/net/wireless/ralink/rt2x00/rt2x00.h        |    2 +-
+ drivers/net/wireless/ralink/rt2x00/rt2x00config.c  |    4 +-
+ drivers/net/wireless/ralink/rt2x00/rt2x00mac.c     |    4 +-
+ drivers/net/wireless/ralink/rt2x00/rt2x00queue.c   |    2 +-
+ drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c |    4 +-
+ drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c |    4 +-
+ .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c  |   12 +-
+ drivers/net/wireless/realtek/rtlwifi/core.c        |    8 +-
+ drivers/net/wireless/realtek/rtlwifi/pci.c         |    2 +-
+ drivers/net/wireless/realtek/rtw88/bf.c            |    2 +-
+ drivers/net/wireless/realtek/rtw88/fw.c            |    2 +-
+ drivers/net/wireless/realtek/rtw88/mac80211.c      |    9 +-
+ drivers/net/wireless/realtek/rtw88/main.c          |   17 +-
+ drivers/net/wireless/realtek/rtw89/cam.c           |   31 +-
+ drivers/net/wireless/realtek/rtw89/cam.h           |    9 +-
+ drivers/net/wireless/realtek/rtw89/core.c          |  150 ++-
+ drivers/net/wireless/realtek/rtw89/core.h          |   35 +-
+ drivers/net/wireless/realtek/rtw89/debug.c         |    3 +-
+ drivers/net/wireless/realtek/rtw89/debug.h         |    2 +
+ drivers/net/wireless/realtek/rtw89/fw.c            |    5 +-
+ drivers/net/wireless/realtek/rtw89/mac80211.c      |   12 +-
+ drivers/net/wireless/realtek/rtw89/pci.c           |   16 +-
+ drivers/net/wireless/realtek/rtw89/phy.c           |   22 +-
+ drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c  |    4 +-
+ drivers/net/wireless/realtek/rtw89/ser.c           |   15 +-
+ drivers/net/wireless/rndis_wlan.c                  |    5 +-
+ drivers/net/wireless/rsi/rsi_91x_core.c            |    3 +-
+ drivers/net/wireless/rsi/rsi_91x_hal.c             |    9 +-
+ drivers/net/wireless/rsi/rsi_91x_mac80211.c        |   33 +-
+ drivers/net/wireless/rsi/rsi_91x_mgmt.c            |    3 +-
+ drivers/net/wireless/silabs/wfx/hif_tx.c           |   12 +-
+ drivers/net/wireless/silabs/wfx/sta.c              |   40 +-
+ drivers/net/wireless/silabs/wfx/sta.h              |   10 +-
+ drivers/net/wireless/st/cw1200/sta.c               |   44 +-
+ drivers/net/wireless/st/cw1200/sta.h               |    2 +-
+ drivers/net/wireless/st/cw1200/txrx.c              |    4 +-
+ drivers/net/wireless/ti/wl1251/main.c              |   12 +-
+ drivers/net/wireless/ti/wlcore/cmd.c               |    4 +-
+ drivers/net/wireless/ti/wlcore/main.c              |   47 +-
+ drivers/net/wireless/zydas/zd1211rw/zd_mac.c       |   13 +-
+ drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c  |    8 +-
+ drivers/staging/vt6655/device_main.c               |    8 +-
+ drivers/staging/vt6655/rxtx.c                      |    2 +-
+ drivers/staging/vt6656/main_usb.c                  |    6 +-
+ drivers/staging/vt6656/rxtx.c                      |    2 +-
+ drivers/staging/wlan-ng/cfg80211.c                 |    2 +-
+ include/linux/ieee80211.h                          |  225 ++++
+ include/net/cfg80211.h                             |  214 +++-
+ include/net/mac80211.h                             |  210 ++--
+ include/uapi/linux/nl80211.h                       |   37 +
+ net/mac80211/agg-rx.c                              |    4 +-
+ net/mac80211/agg-tx.c                              |    2 +-
+ net/mac80211/airtime.c                             |    4 +-
+ net/mac80211/cfg.c                                 |  490 +++++----
+ net/mac80211/chan.c                                |  660 ++++++-----
+ net/mac80211/debug.h                               |   14 +
+ net/mac80211/debugfs_key.c                         |   10 +-
+ net/mac80211/debugfs_netdev.c                      |   20 +-
+ net/mac80211/driver-ops.h                          |  102 +-
+ net/mac80211/eht.c                                 |    9 +-
+ net/mac80211/ethtool.c                             |   26 +-
+ net/mac80211/he.c                                  |   17 +-
+ net/mac80211/ht.c                                  |   41 +-
+ net/mac80211/ibss.c                                |   65 +-
+ net/mac80211/ieee80211_i.h                         |  294 ++---
+ net/mac80211/iface.c                               |  249 ++++-
+ net/mac80211/key.c                                 |   56 +-
+ net/mac80211/main.c                                |  143 ++-
+ net/mac80211/mesh.c                                |   20 +-
+ net/mac80211/mesh_plink.c                          |   14 +-
+ net/mac80211/mlme.c                                |  434 ++++----
+ net/mac80211/ocb.c                                 |   15 +-
+ net/mac80211/offchannel.c                          |   22 +-
+ net/mac80211/rate.c                                |   19 +-
+ net/mac80211/rate.h                                |    8 +-
+ net/mac80211/rx.c                                  |   43 +-
+ net/mac80211/scan.c                                |    2 +-
+ net/mac80211/sta_info.c                            |  313 ++++--
+ net/mac80211/sta_info.h                            |   28 +-
+ net/mac80211/status.c                              |   24 +-
+ net/mac80211/tdls.c                                |   31 +-
+ net/mac80211/trace.h                               | 1160 +++++++++++---------
+ net/mac80211/tx.c                                  |  304 ++---
+ net/mac80211/util.c                                |   80 +-
+ net/mac80211/vht.c                                 |  177 +--
+ net/mac80211/wme.c                                 |    3 +-
+ net/wireless/ap.c                                  |   46 +-
+ net/wireless/chan.c                                |  196 +++-
+ net/wireless/core.c                                |   28 +-
+ net/wireless/core.h                                |   24 +-
+ net/wireless/ibss.c                                |   57 +-
+ net/wireless/mesh.c                                |   31 +-
+ net/wireless/mlme.c                                |  160 +--
+ net/wireless/nl80211.c                             |  957 ++++++++++++----
+ net/wireless/ocb.c                                 |    5 +-
+ net/wireless/rdev-ops.h                            |   58 +-
+ net/wireless/reg.c                                 |  139 ++-
+ net/wireless/scan.c                                |    8 +-
+ net/wireless/sme.c                                 |  512 ++++++---
+ net/wireless/trace.h                               |  378 ++++---
+ net/wireless/util.c                                |   44 +-
+ net/wireless/wext-compat.c                         |   48 +-
+ net/wireless/wext-sme.c                            |   29 +-
+ 206 files changed, 6747 insertions(+), 3554 deletions(-)
+Merging mtd/mtd/next (278811d5a7b2 mtd: parsers: scpart: add missing of_node_put() in scpart_parse())
+$ git merge -m Merge branch 'mtd/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/mtd/next
+Merge made by the 'ort' strategy.
+ drivers/mtd/devices/powernv_flash.c          |   4 +-
+ drivers/mtd/devices/spear_smi.c              |  10 +-
+ drivers/mtd/devices/st_spi_fsm.c             |  23 +--
+ drivers/mtd/hyperbus/hbmc-am654.c            |   6 +-
+ drivers/mtd/hyperbus/hyperbus-core.c         |   8 +-
+ drivers/mtd/hyperbus/rpc-if.c                |   5 +-
+ drivers/mtd/lpddr/lpddr2_nvm.c               |   4 +-
+ drivers/mtd/maps/physmap-core.c              |  13 +-
+ drivers/mtd/maps/physmap-versatile.c         |   2 +
+ drivers/mtd/mtdchar.c                        |  13 +-
+ drivers/mtd/nand/raw/atmel/nand-controller.c |   4 +-
+ drivers/mtd/nand/raw/meson_nand.c            |  16 +-
+ drivers/mtd/nand/raw/omap2.c                 |   6 +-
+ drivers/mtd/nand/raw/tegra_nand.c            |   5 +-
+ drivers/mtd/parsers/Kconfig                  |   9 +
+ drivers/mtd/parsers/Makefile                 |   1 +
+ drivers/mtd/parsers/ofpart_bcm4908.c         |   3 +
+ drivers/mtd/parsers/redboot.c                |   1 +
+ drivers/mtd/parsers/scpart.c                 | 249 +++++++++++++++++++++++++++
+ drivers/mtd/sm_ftl.c                         |   2 +-
+ include/linux/mtd/hyperbus.h                 |   4 +-
+ include/uapi/mtd/mtd-abi.h                   |   4 +-
+ 22 files changed, 317 insertions(+), 75 deletions(-)
+ create mode 100644 drivers/mtd/parsers/scpart.c
+Merging nand/nand/next (5278cc93a97f dt-bindings: mtd: qcom_nandc: document qcom,boot-partitions binding)
+$ git merge -m Merge branch 'nand/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/nand/next
+Auto-merging drivers/mtd/nand/raw/meson_nand.c
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/mtd/mxc-nand.yaml          |   2 -
+ .../devicetree/bindings/mtd/qcom,nandc.yaml        |  27 ++
+ drivers/mtd/nand/raw/cafe_nand.c                   |   9 +-
+ drivers/mtd/nand/raw/meson_nand.c                  |   1 -
+ drivers/mtd/nand/raw/qcom_nandc.c                  | 306 +++++++++++++++++----
+ drivers/mtd/nand/spi/Makefile                      |   2 +-
+ drivers/mtd/nand/spi/ato.c                         |  86 ++++++
+ drivers/mtd/nand/spi/core.c                        |   1 +
+ include/linux/mtd/spinand.h                        |   1 +
+ 9 files changed, 379 insertions(+), 56 deletions(-)
+ create mode 100644 drivers/mtd/nand/spi/ato.c
+Merging spi-nor/spi-nor/next (c47452194641 mtd: spi-nor: debugfs: fix format specifier)
+$ git merge -m Merge branch 'spi-nor/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/spi-nor/next
+Already up to date.
+Merging crypto/master (bffa1fc06589 crypto: hisilicon/sec - only HW V2 needs to change the BD err detection)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git crypto/master
+Auto-merging MAINTAINERS
+Auto-merging crypto/Kconfig
+Auto-merging crypto/Makefile
+Auto-merging fs/crypto/fscrypt_private.h
+Auto-merging fs/crypto/policy.c
+Auto-merging lib/Kconfig
+Auto-merging lib/Makefile
+Merge made by the 'ort' strategy.
+ Documentation/filesystems/fscrypt.rst              |   22 +-
+ MAINTAINERS                                        |   15 +-
+ arch/arm/crypto/Kconfig                            |    2 +-
+ arch/arm/crypto/Makefile                           |    4 +-
+ arch/arm/crypto/blake2s-shash.c                    |   75 -
+ arch/arm64/crypto/Kconfig                          |    9 +-
+ arch/arm64/crypto/Makefile                         |    3 +
+ arch/arm64/crypto/aes-glue.c                       |   80 +-
+ arch/arm64/crypto/aes-modes.S                      |  349 ++--
+ arch/arm64/crypto/polyval-ce-core.S                |  361 ++++
+ arch/arm64/crypto/polyval-ce-glue.c                |  191 +++
+ arch/x86/crypto/Makefile                           |    7 +-
+ arch/x86/crypto/aes_ctrby8_avx-x86_64.S            |  232 ++-
+ arch/x86/crypto/aesni-intel_glue.c                 |  114 +-
+ arch/x86/crypto/blake2s-glue.c                     |    3 +-
+ arch/x86/crypto/blake2s-shash.c                    |   77 -
+ arch/x86/crypto/polyval-clmulni_asm.S              |  321 ++++
+ arch/x86/crypto/polyval-clmulni_glue.c             |  203 +++
+ crypto/Kconfig                                     |   59 +-
+ crypto/Makefile                                    |    4 +-
+ crypto/blake2s_generic.c                           |   75 -
+ crypto/hctr2.c                                     |  581 +++++++
+ crypto/polyval-generic.c                           |  245 +++
+ crypto/tcrypt.c                                    |   22 +-
+ crypto/testmgr.c                                   |   44 +-
+ crypto/testmgr.h                                   | 1745 +++++++++++++++++---
+ crypto/xctr.c                                      |  191 +++
+ .../crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c    |    1 +
+ drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c  |   16 +-
+ drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c  |   10 +-
+ drivers/crypto/atmel-ecc.c                         |   12 +-
+ drivers/crypto/ccp/ccp-dev.h                       |    2 +-
+ drivers/crypto/ccp/sev-dev.c                       |   10 +-
+ drivers/crypto/hisilicon/qm.c                      |  203 ++-
+ drivers/crypto/hisilicon/sec2/sec.h                |    4 +-
+ drivers/crypto/hisilicon/sec2/sec_main.c           |   39 +-
+ drivers/crypto/hisilicon/trng/trng.c               |    2 +-
+ drivers/crypto/hisilicon/zip/zip_main.c            |   17 +-
+ .../crypto/marvell/octeontx2/otx2_cpt_devlink.c    |   40 +-
+ .../crypto/marvell/octeontx2/otx2_cptpf_ucode.c    |   17 +-
+ .../crypto/marvell/octeontx2/otx2_cptpf_ucode.h    |    3 +
+ fs/crypto/fscrypt_private.h                        |    2 +-
+ fs/crypto/keysetup.c                               |    7 +
+ fs/crypto/policy.c                                 |   14 +-
+ include/crypto/internal/blake2s.h                  |  108 --
+ include/crypto/polyval.h                           |   22 +
+ include/linux/hisi_acc_qm.h                        |    8 +-
+ include/uapi/linux/fscrypt.h                       |    3 +-
+ lib/crypto/blake2s-selftest.c                      |   41 +
+ lib/crypto/blake2s.c                               |   37 +-
+ 50 files changed, 4688 insertions(+), 964 deletions(-)
+ delete mode 100644 arch/arm/crypto/blake2s-shash.c
+ create mode 100644 arch/arm64/crypto/polyval-ce-core.S
+ create mode 100644 arch/arm64/crypto/polyval-ce-glue.c
+ delete mode 100644 arch/x86/crypto/blake2s-shash.c
+ create mode 100644 arch/x86/crypto/polyval-clmulni_asm.S
+ create mode 100644 arch/x86/crypto/polyval-clmulni_glue.c
+ delete mode 100644 crypto/blake2s_generic.c
+ create mode 100644 crypto/hctr2.c
+ create mode 100644 crypto/polyval-generic.c
+ create mode 100644 crypto/xctr.c
+ create mode 100644 include/crypto/polyval.h
+Merging drm/drm-next (0a2af0bd6e48 Merge tag 'drm-misc-next-2022-06-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next)
+$ git merge -m Merge branch 'drm-next' of git://git.freedesktop.org/git/drm/drm.git drm/drm-next
+Auto-merging MAINTAINERS
+Auto-merging drivers/dma-buf/udmabuf.c
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+Auto-merging drivers/gpu/drm/msm/dsi/dsi_host.c
+Auto-merging drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+Auto-merging drivers/gpu/drm/ttm/ttm_bo.c
+Merge made by the 'ort' strategy.
+ .../bindings/display/bridge/fsl,ldb.yaml           |   16 +-
+ .../display/bridge/ingenic,jz4780-hdmi.yaml        |    1 -
+ .../bindings/display/bridge/ti,dlpc3433.yaml       |  117 ++
+ .../display/panel/feiyang,fy07024di26a30d.yaml     |    1 -
+ .../bindings/display/panel/novatek,nt36672a.yaml   |    2 +
+ .../devicetree/bindings/gpu/arm,mali-bifrost.yaml  |   25 +-
+ .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml      |    1 +
+ .../driver-api/firmware/other_interfaces.rst       |    6 +
+ Documentation/gpu/todo.rst                         |   11 +
+ Documentation/gpu/vkms.rst                         |    6 -
+ MAINTAINERS                                        |   14 +
+ drivers/dma-buf/Makefile                           |    2 +-
+ drivers/dma-buf/dma-buf.c                          |  110 +-
+ drivers/dma-buf/dma-fence-chain.c                  |    4 +-
+ drivers/dma-buf/dma-fence-unwrap.c                 |  162 ++
+ drivers/dma-buf/st-dma-fence-unwrap.c              |  157 +-
+ drivers/dma-buf/sync_file.c                        |  119 +-
+ drivers/dma-buf/udmabuf.c                          |   18 +-
+ drivers/firmware/sysfb.c                           |   58 +-
+ drivers/firmware/sysfb_simplefb.c                  |   16 +-
+ drivers/gpu/drm/Kconfig                            |    2 +
+ drivers/gpu/drm/Makefile                           |    1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c       |   51 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h       |   27 -
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   27 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c  |   38 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h  |    2 -
+ drivers/gpu/drm/bridge/Kconfig                     |   19 +
+ drivers/gpu/drm/bridge/Makefile                    |    1 +
+ drivers/gpu/drm/bridge/adv7511/adv7511.h           |   12 -
+ drivers/gpu/drm/bridge/adv7511/adv7511_cec.c       |   12 +
+ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c       |    7 +-
+ drivers/gpu/drm/bridge/analogix/anx7625.c          |   13 +-
+ drivers/gpu/drm/bridge/cdns-dsi.c                  |   26 +
+ drivers/gpu/drm/bridge/chipone-icn6211.c           |   53 +-
+ drivers/gpu/drm/bridge/lontium-lt8912b.c           |    9 +-
+ drivers/gpu/drm/bridge/lontium-lt9211.c            |    6 +-
+ drivers/gpu/drm/bridge/lontium-lt9611.c            |   24 +-
+ drivers/gpu/drm/bridge/lontium-lt9611uxc.c         |    2 +-
+ drivers/gpu/drm/bridge/nwl-dsi.c                   |    6 +
+ drivers/gpu/drm/bridge/parade-ps8640.c             |   73 +-
+ drivers/gpu/drm/bridge/tc358767.c                  |  175 ++-
+ drivers/gpu/drm/bridge/tc358775.c                  |   21 +-
+ drivers/gpu/drm/bridge/ti-dlpc3433.c               |  417 +++++
+ drivers/gpu/drm/bridge/ti-sn65dsi83.c              |   64 +-
+ drivers/gpu/drm/bridge/ti-sn65dsi86.c              |    4 +-
+ drivers/gpu/drm/display/drm_dp_aux_bus.c           |  211 ++-
+ drivers/gpu/drm/display/drm_dp_mst_topology.c      |    7 +-
+ drivers/gpu/drm/drm_bridge.c                       |   23 +
+ drivers/gpu/drm/drm_client_modeset.c               |   28 +-
+ drivers/gpu/drm/drm_debugfs.c                      |   21 +
+ drivers/gpu/drm/drm_displayid.c                    |   16 +-
+ drivers/gpu/drm/drm_edid.c                         | 1596 +++++++++++++-------
+ drivers/gpu/drm/drm_encoder.c                      |    2 +-
+ drivers/gpu/drm/drm_gem_atomic_helper.c            |    6 +-
+ drivers/gpu/drm/drm_gem_cma_helper.c               |   39 +-
+ drivers/gpu/drm/drm_gem_framebuffer_helper.c       |  104 +-
+ drivers/gpu/drm/drm_gem_vram_helper.c              |   54 +-
+ drivers/gpu/drm/drm_mipi_dbi.c                     |    7 +
+ drivers/gpu/drm/drm_modes.c                        |    4 +
+ drivers/gpu/drm/drm_of.c                           |   61 +
+ drivers/gpu/drm/drm_probe_helper.c                 |  207 ++-
+ drivers/gpu/drm/drm_syncobj.c                      |   59 +-
+ drivers/gpu/drm/gma500/cdv_intel_crt.c             |   47 +-
+ drivers/gpu/drm/gma500/cdv_intel_hdmi.c            |   98 +-
+ drivers/gpu/drm/gma500/cdv_intel_lvds.c            |   80 +-
+ drivers/gpu/drm/gma500/intel_i2c.c                 |   36 +-
+ drivers/gpu/drm/gma500/oaktrail_lvds.c             |   50 +-
+ drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c         |   36 +-
+ drivers/gpu/drm/gma500/psb_drv.h                   |    2 +-
+ drivers/gpu/drm/gma500/psb_intel_drv.h             |   24 +-
+ drivers/gpu/drm/gma500/psb_intel_lvds.c            |   86 +-
+ drivers/gpu/drm/hyperv/hyperv_drm_drv.c            |   74 +-
+ .../gpu/drm/i915/display/intel_display_debugfs.c   |   28 +
+ drivers/gpu/drm/logicvc/Kconfig                    |    9 +
+ drivers/gpu/drm/logicvc/Makefile                   |    9 +
+ drivers/gpu/drm/logicvc/logicvc_crtc.c             |  280 ++++
+ drivers/gpu/drm/logicvc/logicvc_crtc.h             |   21 +
+ drivers/gpu/drm/logicvc/logicvc_drm.c              |  497 ++++++
+ drivers/gpu/drm/logicvc/logicvc_drm.h              |   67 +
+ drivers/gpu/drm/logicvc/logicvc_interface.c        |  214 +++
+ drivers/gpu/drm/logicvc/logicvc_interface.h        |   28 +
+ drivers/gpu/drm/logicvc/logicvc_layer.c            |  628 ++++++++
+ drivers/gpu/drm/logicvc/logicvc_layer.h            |   64 +
+ drivers/gpu/drm/logicvc/logicvc_mode.c             |   80 +
+ drivers/gpu/drm/logicvc/logicvc_mode.h             |   15 +
+ drivers/gpu/drm/logicvc/logicvc_of.c               |  185 +++
+ drivers/gpu/drm/logicvc/logicvc_of.h               |   46 +
+ drivers/gpu/drm/logicvc/logicvc_regs.h             |   80 +
+ drivers/gpu/drm/meson/meson_encoder_cvbs.c         |    1 +
+ drivers/gpu/drm/meson/meson_encoder_hdmi.c         |   27 +-
+ drivers/gpu/drm/mgag200/Makefile                   |   14 +-
+ drivers/gpu/drm/mgag200/mgag200_drv.c              |  387 ++---
+ drivers/gpu/drm/mgag200/mgag200_drv.h              |  148 +-
+ drivers/gpu/drm/mgag200/mgag200_g200.c             |  201 +++
+ drivers/gpu/drm/mgag200/mgag200_g200eh.c           |   50 +
+ drivers/gpu/drm/mgag200/mgag200_g200eh3.c          |   51 +
+ drivers/gpu/drm/mgag200/mgag200_g200er.c           |   46 +
+ drivers/gpu/drm/mgag200/mgag200_g200ev.c           |   50 +
+ drivers/gpu/drm/mgag200/mgag200_g200ew3.c          |   60 +
+ drivers/gpu/drm/mgag200/mgag200_g200se.c           |  130 ++
+ drivers/gpu/drm/mgag200/mgag200_g200wb.c           |   50 +
+ drivers/gpu/drm/mgag200/mgag200_i2c.c              |   59 +-
+ drivers/gpu/drm/mgag200/mgag200_mm.c               |  116 --
+ drivers/gpu/drm/mgag200/mgag200_mode.c             |  453 +++---
+ drivers/gpu/drm/mgag200/mgag200_pll.c              |   12 +-
+ drivers/gpu/drm/mgag200/mgag200_reg.h              |    2 +
+ drivers/gpu/drm/msm/dp/dp_parser.c                 |   10 +-
+ drivers/gpu/drm/msm/dsi/dsi_host.c                 |    9 +-
+ drivers/gpu/drm/nouveau/include/nvhw/drf.h         |    4 +-
+ drivers/gpu/drm/nouveau/nouveau_fbcon.c            |    2 +
+ drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c |   14 +-
+ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c   |    2 +-
+ drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c     |    4 +-
+ drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c    |    2 +-
+ drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h    |    2 +-
+ drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c  |    2 +-
+ .../gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c   |   14 +-
+ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c      |    2 +-
+ drivers/gpu/drm/panel/Kconfig                      |    2 +
+ .../gpu/drm/panel/panel-feiyang-fy07024di26a30d.c  |    2 +-
+ drivers/gpu/drm/panel/panel-novatek-nt36672a.c     |    4 +
+ drivers/gpu/drm/panfrost/panfrost_device.c         |    9 +-
+ drivers/gpu/drm/panfrost/panfrost_drv.c            |    1 +
+ drivers/gpu/drm/panfrost/panfrost_features.h       |   13 +
+ drivers/gpu/drm/panfrost/panfrost_gpu.c            |   18 +-
+ drivers/gpu/drm/panfrost/panfrost_issues.h         |   19 +-
+ drivers/gpu/drm/panfrost/panfrost_regs.h           |    1 +
+ drivers/gpu/drm/qxl/qxl_kms.c                      |    2 -
+ drivers/gpu/drm/r128/r128_drv.h                    |    4 +-
+ drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c            |   15 +-
+ drivers/gpu/drm/rockchip/Kconfig                   |    4 +-
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c       |    5 +-
+ drivers/gpu/drm/scheduler/sched_entity.c           |    6 +-
+ drivers/gpu/drm/solomon/ssd130x-spi.c              |    2 +
+ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h              |    9 +-
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c             |  242 ++-
+ drivers/gpu/drm/tiny/bochs.c                       |    1 +
+ drivers/gpu/drm/tiny/st7735r.c                     |    1 +
+ drivers/gpu/drm/ttm/ttm_bo.c                       |    9 +-
+ drivers/gpu/drm/udl/udl_connector.c                |    2 +-
+ drivers/gpu/drm/v3d/Kconfig                        |    5 +-
+ drivers/gpu/drm/v3d/v3d_debugfs.c                  |   18 +-
+ drivers/gpu/drm/v3d/v3d_drv.c                      |   12 +-
+ drivers/gpu/drm/v3d/v3d_gem.c                      |   12 +-
+ drivers/gpu/drm/virtio/virtgpu_ioctl.c             |    6 +-
+ drivers/gpu/drm/virtio/virtgpu_object.c            |    4 +-
+ drivers/gpu/drm/virtio/virtgpu_prime.c             |    6 +-
+ drivers/gpu/drm/vkms/vkms_composer.c               |   10 +-
+ drivers/gpu/drm/vmwgfx/vmwgfx_bo.c                 |   10 +-
+ drivers/video/fbdev/core/fbcon.c                   |    1 -
+ drivers/video/fbdev/core/fbmem.c                   |   34 +-
+ drivers/video/fbdev/efifb.c                        |   11 -
+ drivers/video/fbdev/simplefb.c                     |   11 -
+ include/drm/display/drm_dp_aux_bus.h               |   34 +-
+ include/drm/display/drm_dp_helper.h                |   18 +-
+ include/drm/drm_bridge.h                           |    1 +
+ include/drm/drm_displayid.h                        |    6 +-
+ include/drm/drm_edid.h                             |   36 +-
+ include/drm/drm_gem_framebuffer_helper.h           |   10 +-
+ include/drm/drm_of.h                               |   22 +
+ include/drm/drm_probe_helper.h                     |    2 +
+ include/drm/gpu_scheduler.h                        |    4 +-
+ include/linux/dma-fence-unwrap.h                   |   82 +-
+ include/linux/fb.h                                 |    1 -
+ include/linux/iosys-map.h                          |    2 +-
+ include/linux/sysfb.h                              |   22 +-
+ include/uapi/linux/dma-buf.h                       |   84 ++
+ 168 files changed, 7198 insertions(+), 2728 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml
+ create mode 100644 drivers/dma-buf/dma-fence-unwrap.c
+ create mode 100644 drivers/gpu/drm/bridge/ti-dlpc3433.c
+ create mode 100644 drivers/gpu/drm/logicvc/Kconfig
+ create mode 100644 drivers/gpu/drm/logicvc/Makefile
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_crtc.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_crtc.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_drm.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_drm.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_interface.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_interface.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_layer.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_layer.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_mode.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_mode.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_of.c
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_of.h
+ create mode 100644 drivers/gpu/drm/logicvc/logicvc_regs.h
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh3.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200er.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ev.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ew3.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200se.c
+ create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200wb.c
+ delete mode 100644 drivers/gpu/drm/mgag200/mgag200_mm.c
+Merging drm-misc/for-linux-next (009a3a52791f drm/hyperv-drm: Include framebuffer and EDID headers)
+$ git merge -m Merge branch 'for-linux-next' of git://anongit.freedesktop.org/drm/drm-misc drm-misc/for-linux-next
+Auto-merging MAINTAINERS
+Auto-merging MAINTAINERS
+Auto-merging drivers/dma-buf/dma-buf.c
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+Auto-merging drivers/gpu/drm/bridge/Kconfig
+Auto-merging drivers/gpu/drm/display/drm_dp_mst_topology.c
+Auto-merging drivers/gpu/drm/drm_panel_orientation_quirks.c
+Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
+Auto-merging drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+Auto-merging drivers/gpu/drm/msm/dp/dp_parser.c
+Auto-merging drivers/gpu/drm/msm/dsi/dsi_host.c
+Auto-merging drivers/gpu/drm/sun4i/sun4i_layer.c
+Auto-merging drivers/gpu/drm/vc4/vc4_bo.c
+Auto-merging drivers/gpu/drm/vc4/vc4_crtc.c
+Auto-merging drivers/gpu/drm/vc4/vc4_kms.c
+Auto-merging drivers/gpu/drm/vc4/vc4_plane.c
+Auto-merging drivers/video/fbdev/core/fbmem.c
+Auto-merging drivers/video/fbdev/efifb.c
+Auto-merging drivers/video/fbdev/simplefb.c
+Auto-merging include/drm/drm_edid.h
+Auto-merging include/uapi/linux/dma-buf.h
+CONFLICT (content): Merge conflict in include/uapi/linux/dma-buf.h
+Merge made by the 'ort' strategy.
+ .../bindings/display/bridge/analogix,anx7625.yaml  |  19 +-
+ .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml   | 173 +++++
+ .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 ++++
+ .../display/bridge/fsl,imx8qxp-pixel-link.yaml     | 144 ++++
+ .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml        | 108 +++
+ .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml   | 192 ++++++
+ .../userspace-api/media/v4l/subdev-formats.rst     | 156 +++++
+ MAINTAINERS                                        |  10 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |   1 +
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   3 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h    |   1 +
+ drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c   |   1 +
+ drivers/gpu/drm/arm/display/komeda/komeda_kms.h    |   1 +
+ drivers/gpu/drm/arm/display/komeda/komeda_plane.c  |   1 +
+ .../drm/arm/display/komeda/komeda_wb_connector.c   |   1 +
+ drivers/gpu/drm/arm/hdlcd_crtc.c                   |   1 +
+ drivers/gpu/drm/arm/malidp_crtc.c                  |   1 +
+ drivers/gpu/drm/arm/malidp_mw.c                    |   2 +
+ drivers/gpu/drm/arm/malidp_planes.c                |   2 +
+ drivers/gpu/drm/armada/armada_fb.h                 |   2 +
+ drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c           |   1 +
+ drivers/gpu/drm/aspeed/aspeed_gfx_out.c            |   1 +
+ drivers/gpu/drm/ast/ast_mode.c                     |   1 +
+ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c    |   2 +
+ drivers/gpu/drm/bridge/Kconfig                     |   2 +
+ drivers/gpu/drm/bridge/Makefile                    |   1 +
+ drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |   1 +
+ drivers/gpu/drm/bridge/analogix/anx7625.c          |   8 +-
+ .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.c    |   1 +
+ drivers/gpu/drm/bridge/imx/Kconfig                 |  43 ++
+ drivers/gpu/drm/bridge/imx/Makefile                |   9 +
+ drivers/gpu/drm/bridge/imx/imx-ldb-helper.c        | 220 +++++++
+ drivers/gpu/drm/bridge/imx/imx-ldb-helper.h        |  96 +++
+ drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c        | 587 +++++++++++++++++
+ drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c       | 722 +++++++++++++++++++++
+ .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c    | 448 +++++++++++++
+ drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c    | 429 ++++++++++++
+ drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c       | 487 ++++++++++++++
+ drivers/gpu/drm/bridge/lontium-lt8912b.c           |   1 +
+ drivers/gpu/drm/bridge/panel.c                     |  34 +
+ drivers/gpu/drm/bridge/parade-ps8640.c             |  40 +-
+ drivers/gpu/drm/bridge/simple-bridge.c             |   1 +
+ drivers/gpu/drm/bridge/tc358775.c                  |   3 +-
+ drivers/gpu/drm/bridge/ti-sn65dsi83.c              |   8 +-
+ drivers/gpu/drm/bridge/ti-tfp410.c                 |   1 +
+ drivers/gpu/drm/display/drm_dp_helper.c            |   3 +-
+ drivers/gpu/drm/display/drm_dp_mst_topology.c      |  26 +-
+ drivers/gpu/drm/drm_aperture.c                     |  26 +-
+ drivers/gpu/drm/drm_atomic.c                       |   2 +
+ drivers/gpu/drm/drm_atomic_helper.c                |   2 +
+ drivers/gpu/drm/drm_atomic_state_helper.c          |   2 +
+ drivers/gpu/drm/drm_atomic_uapi.c                  |   1 +
+ drivers/gpu/drm/drm_bridge_connector.c             |   8 +-
+ drivers/gpu/drm/drm_client_modeset.c               |   1 +
+ drivers/gpu/drm/drm_connector.c                    |  31 +
+ drivers/gpu/drm/drm_crtc.c                         |   2 +
+ drivers/gpu/drm/drm_crtc_helper.c                  |   1 +
+ drivers/gpu/drm/drm_damage_helper.c                |   1 +
+ drivers/gpu/drm/drm_fb_helper.c                    |   1 +
+ drivers/gpu/drm/drm_gem_atomic_helper.c            |   1 +
+ drivers/gpu/drm/drm_ioctl.c                        |   2 +-
+ drivers/gpu/drm/drm_kms_helper_common.c            |   1 +
+ drivers/gpu/drm/drm_mipi_dbi.c                     |   1 +
+ drivers/gpu/drm/drm_mode_config.c                  |   1 +
+ drivers/gpu/drm/drm_modes.c                        |   1 +
+ drivers/gpu/drm/drm_modeset_helper.c               |   1 +
+ drivers/gpu/drm/drm_panel_orientation_quirks.c     |   2 +-
+ drivers/gpu/drm/drm_prime.c                        |   2 +-
+ drivers/gpu/drm/drm_writeback.c                    |   1 +
+ drivers/gpu/drm/exynos/exynos5433_drm_decon.c      |   2 +
+ drivers/gpu/drm/exynos/exynos7_drm_decon.c         |   1 +
+ drivers/gpu/drm/exynos/exynos_drm_fb.c             |   1 +
+ drivers/gpu/drm/exynos/exynos_drm_fbdev.c          |   1 +
+ drivers/gpu/drm/exynos/exynos_drm_fimd.c           |   2 +
+ drivers/gpu/drm/exynos/exynos_drm_ipp.c            |   1 +
+ drivers/gpu/drm/exynos/exynos_drm_plane.c          |   2 +
+ drivers/gpu/drm/exynos/exynos_drm_scaler.c         |   1 +
+ drivers/gpu/drm/exynos/exynos_drm_vidi.c           |   1 +
+ drivers/gpu/drm/exynos/exynos_mixer.c              |   3 +
+ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c        |   1 +
+ drivers/gpu/drm/gma500/cdv_intel_dp.c              |   1 +
+ drivers/gpu/drm/gma500/framebuffer.c               |   1 +
+ drivers/gpu/drm/gma500/gma_display.c               |   1 +
+ drivers/gpu/drm/gma500/oaktrail_crtc.c             |   1 +
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c             |   1 +
+ drivers/gpu/drm/gma500/oaktrail_lvds.c             |   1 +
+ drivers/gpu/drm/gma500/psb_intel_modes.c           |   2 +
+ drivers/gpu/drm/gud/gud_connector.c                |   1 +
+ drivers/gpu/drm/gud/gud_drv.c                      |   1 +
+ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c    |   1 +
+ drivers/gpu/drm/hyperv/hyperv_drm_modeset.c        |   2 +
+ drivers/gpu/drm/i915/display/i9xx_plane.c          |   1 +
+ drivers/gpu/drm/i915/display/intel_bios.c          |   1 +
+ drivers/gpu/drm/i915/display/intel_cursor.c        |   1 +
+ drivers/gpu/drm/i915/display/intel_display_types.h |   1 +
+ drivers/gpu/drm/i915/display/intel_dp.c            |   1 +
+ drivers/gpu/drm/i915/display/intel_fb.c            |   1 +
+ drivers/gpu/drm/i915/display/intel_fbc.c           |   1 +
+ drivers/gpu/drm/i915/display/intel_lspcon.c        |   1 +
+ drivers/gpu/drm/i915/display/intel_opregion.c      |   2 +
+ drivers/gpu/drm/i915/display/intel_sprite.c        |   1 +
+ drivers/gpu/drm/i915/display/skl_universal_plane.c |   1 +
+ drivers/gpu/drm/i915/intel_pm.c                    |   1 +
+ drivers/gpu/drm/imx/dcss/dcss-plane.c              |   2 +
+ drivers/gpu/drm/imx/imx-ldb.c                      |   1 +
+ drivers/gpu/drm/imx/imx-tve.c                      |   1 +
+ drivers/gpu/drm/imx/ipuv3-plane.c                  |   2 +
+ drivers/gpu/drm/imx/parallel-display.c             |   1 +
+ drivers/gpu/drm/ingenic/ingenic-drm-drv.c          |   1 +
+ drivers/gpu/drm/ingenic/ingenic-ipu.c              |   1 +
+ drivers/gpu/drm/kmb/kmb_plane.c                    |   2 +
+ drivers/gpu/drm/logicvc/logicvc_layer.c            |   2 +
+ drivers/gpu/drm/mcde/mcde_display.c                |   1 +
+ drivers/gpu/drm/mediatek/mtk_disp_ovl.c            |   2 +
+ drivers/gpu/drm/mediatek/mtk_disp_rdma.c           |   2 +
+ drivers/gpu/drm/mediatek/mtk_drm_plane.c           |   2 +
+ drivers/gpu/drm/meson/meson_overlay.c              |   2 +
+ drivers/gpu/drm/meson/meson_plane.c                |   2 +
+ drivers/gpu/drm/mgag200/mgag200_mode.c             |   1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |   2 +
+ .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c    |   2 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c        |   1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          |   2 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c      |   2 +
+ drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c         |   1 +
+ drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c          |   1 +
+ drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c         |   2 +
+ drivers/gpu/drm/msm/disp/mdp_format.c              |   2 +
+ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c             |   1 +
+ drivers/gpu/drm/msm/msm_debugfs.c                  |   1 +
+ drivers/gpu/drm/msm/msm_fb.c                       |   1 +
+ drivers/gpu/drm/msm/msm_fbdev.c                    |   1 +
+ drivers/gpu/drm/mxsfb/mxsfb_kms.c                  |   1 +
+ drivers/gpu/drm/nouveau/dispnv50/wndw.c            |   1 +
+ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c      |   2 +-
+ drivers/gpu/drm/omapdrm/dss/hdmi4.c                |   1 +
+ drivers/gpu/drm/omapdrm/dss/hdmi5.c                |   1 +
+ drivers/gpu/drm/omapdrm/omap_debugfs.c             |   1 +
+ drivers/gpu/drm/omapdrm/omap_fb.c                  |   2 +
+ drivers/gpu/drm/omapdrm/omap_fbdev.c               |   1 +
+ drivers/gpu/drm/omapdrm/omap_plane.c               |   2 +
+ drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c     |  12 +
+ drivers/gpu/drm/panel/panel-edp.c                  |  47 +-
+ drivers/gpu/drm/panel/panel-elida-kd35t133.c       |  12 +
+ drivers/gpu/drm/panel/panel-ilitek-ili9881c.c      |  12 +
+ drivers/gpu/drm/panel/panel-lvds.c                 |  13 +
+ drivers/gpu/drm/panel/panel-samsung-atna33xc20.c   |  51 +-
+ drivers/gpu/drm/panel/panel-simple.c               |  14 +-
+ drivers/gpu/drm/pl111/pl111_display.c              |   1 +
+ drivers/gpu/drm/pl111/pl111_drv.c                  |   1 +
+ drivers/gpu/drm/pl111/pl111_versatile.c            |   2 +
+ drivers/gpu/drm/qxl/qxl_display.c                  |   2 +
+ drivers/gpu/drm/qxl/qxl_draw.c                     |   1 +
+ drivers/gpu/drm/radeon/atombios_crtc.c             |   1 +
+ drivers/gpu/drm/radeon/evergreen.c                 |   1 +
+ drivers/gpu/drm/radeon/r100.c                      |   1 +
+ drivers/gpu/drm/radeon/radeon_device.c             |   1 +
+ drivers/gpu/drm/radeon/radeon_display.c            |   1 +
+ drivers/gpu/drm/radeon/radeon_fb.c                 |   1 +
+ drivers/gpu/drm/radeon/radeon_legacy_crtc.c        |   1 +
+ drivers/gpu/drm/radeon/rs600.c                     |   1 +
+ drivers/gpu/drm/radeon/rv770.c                     |   1 +
+ drivers/gpu/drm/rcar-du/rcar_du_kms.c              |   1 +
+ drivers/gpu/drm/rcar-du/rcar_du_plane.c            |   2 +
+ drivers/gpu/drm/rcar-du/rcar_du_vsp.c              |   2 +
+ drivers/gpu/drm/rcar-du/rcar_du_writeback.c        |   2 +
+ drivers/gpu/drm/rockchip/rk3066_hdmi.c             |   1 +
+ drivers/gpu/drm/rockchip/rockchip_drm_fb.c         |   1 +
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   2 +
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c       |   2 +
+ drivers/gpu/drm/selftests/test-drm_damage_helper.c |   1 +
+ drivers/gpu/drm/selftests/test-drm_plane_helper.c  |   1 +
+ drivers/gpu/drm/shmobile/shmob_drm_crtc.c          |   1 +
+ drivers/gpu/drm/shmobile/shmob_drm_kms.c           |   1 +
+ drivers/gpu/drm/shmobile/shmob_drm_plane.c         |   1 +
+ drivers/gpu/drm/solomon/ssd130x.c                  |   2 +
+ drivers/gpu/drm/sprd/sprd_dpu.c                    |   2 +
+ drivers/gpu/drm/sti/sti_cursor.c                   |   1 +
+ drivers/gpu/drm/sti/sti_gdp.c                      |   1 +
+ drivers/gpu/drm/sti/sti_hqvdp.c                    |   1 +
+ drivers/gpu/drm/sti/sti_plane.c                    |   2 +
+ drivers/gpu/drm/stm/ltdc.c                         |   3 +
+ drivers/gpu/drm/sun4i/sun4i_backend.c              |   2 +
+ drivers/gpu/drm/sun4i/sun4i_framebuffer.c          |   1 +
+ drivers/gpu/drm/sun4i/sun4i_layer.c                |   1 +
+ drivers/gpu/drm/sun4i/sun8i_mixer.c                |   1 +
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c             |   2 +
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c             |   2 +
+ drivers/gpu/drm/tegra/dc.c                         |   2 +
+ drivers/gpu/drm/tegra/drm.c                        |   1 +
+ drivers/gpu/drm/tegra/fb.c                         |   1 +
+ drivers/gpu/drm/tegra/hub.c                        |   2 +
+ drivers/gpu/drm/tegra/plane.c                      |   1 +
+ drivers/gpu/drm/tidss/tidss_dispc.c                |   2 +
+ drivers/gpu/drm/tidss/tidss_plane.c                |   2 +
+ drivers/gpu/drm/tilcdc/tilcdc_crtc.c               |   1 +
+ drivers/gpu/drm/tilcdc/tilcdc_plane.c              |   1 +
+ drivers/gpu/drm/tiny/arcpgu.c                      |   2 +
+ drivers/gpu/drm/tiny/bochs.c                       |   2 +
+ drivers/gpu/drm/tiny/cirrus.c                      |   2 +
+ drivers/gpu/drm/tiny/gm12u320.c                    |   2 +
+ drivers/gpu/drm/tiny/ili9225.c                     |   1 +
+ drivers/gpu/drm/tiny/repaper.c                     |   1 +
+ drivers/gpu/drm/tiny/st7586.c                      |   1 +
+ drivers/gpu/drm/tve200/tve200_display.c            |   1 +
+ drivers/gpu/drm/udl/udl_connector.c                |   1 +
+ drivers/gpu/drm/vboxvideo/vbox_mode.c              |   2 +
+ drivers/gpu/drm/vc4/vc4_bo.c                       |   2 +
+ drivers/gpu/drm/vc4/vc4_crtc.c                     |   1 +
+ drivers/gpu/drm/vc4/vc4_kms.c                      |   1 +
+ drivers/gpu/drm/vc4/vc4_plane.c                    |   2 +
+ drivers/gpu/drm/vc4/vc4_regs.h                     |   2 +-
+ drivers/gpu/drm/vc4/vc4_txp.c                      |   1 +
+ drivers/gpu/drm/virtio/virtgpu_display.c           |   1 +
+ drivers/gpu/drm/virtio/virtgpu_drv.h               |   1 +
+ drivers/gpu/drm/virtio/virtgpu_vq.c                |   2 +
+ drivers/gpu/drm/vkms/vkms_drv.h                    |   1 +
+ drivers/gpu/drm/vkms/vkms_output.c                 |   1 +
+ drivers/gpu/drm/vkms/vkms_writeback.c              |   1 +
+ drivers/gpu/drm/vmwgfx/vmwgfx_kms.h                |   1 +
+ drivers/gpu/drm/xen/xen_drm_front_conn.c           |   1 +
+ drivers/gpu/drm/xen/xen_drm_front_kms.c            |   1 +
+ drivers/gpu/drm/xlnx/zynqmp_disp.c                 |   1 +
+ drivers/video/fbdev/core/fbcon.c                   |  12 +-
+ include/drm/display/drm_dp_helper.h                |  30 +
+ include/drm/drm_bridge.h                           |  14 +
+ include/drm/drm_connector.h                        |   4 +
+ include/drm/drm_crtc.h                             |   6 +-
+ include/drm/drm_panel.h                            |   9 +
+ include/uapi/linux/media-bus-format.h              |   6 +-
+ 231 files changed, 4576 insertions(+), 98 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+ create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
+ create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
+ create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
+Merging drm-intel/for-linux-next (6434cf630086 drm/i915/bios: calculate panel type as per child device index in VBT)
+$ git merge -m Merge branch 'for-linux-next' of git://anongit.freedesktop.org/drm-intel drm-intel/for-linux-next
+Auto-merging drivers/gpu/drm/i915/Makefile
+Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
+Auto-merging drivers/gpu/drm/i915/display/intel_audio.c
+Auto-merging drivers/gpu/drm/i915/display/intel_bios.c
+Auto-merging drivers/gpu/drm/i915/display/intel_ddi.c
+Auto-merging drivers/gpu/drm/i915/display/intel_display.c
+Auto-merging drivers/gpu/drm/i915/display/intel_display_power.c
+Auto-merging drivers/gpu/drm/i915/display/intel_display_types.h
+Auto-merging drivers/gpu/drm/i915/display/intel_dmc.c
+Auto-merging drivers/gpu/drm/i915/display/intel_dmc_regs.h
+CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_dmc_regs.h
+Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
+CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_dp.c
+Auto-merging drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+Auto-merging drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+Auto-merging drivers/gpu/drm/i915/display/intel_fbc.c
+Auto-merging drivers/gpu/drm/i915/display/intel_hdcp.c
+Auto-merging drivers/gpu/drm/i915/display/intel_opregion.c
+Auto-merging drivers/gpu/drm/i915/display/intel_sdvo.c
+Auto-merging drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+Auto-merging drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+Auto-merging drivers/gpu/drm/i915/gt/intel_rc6.c
+Auto-merging drivers/gpu/drm/i915/gt/intel_rps.c
+CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_rps.c
+Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+Auto-merging drivers/gpu/drm/i915/i915_driver.c
+Auto-merging drivers/gpu/drm/i915/i915_drv.h
+Auto-merging drivers/gpu/drm/i915/i915_pci.c
+Auto-merging drivers/gpu/drm/i915/i915_reg.h
+Auto-merging drivers/gpu/drm/i915/intel_device_info.h
+Auto-merging drivers/gpu/drm/i915/intel_pm.c
+Resolved 'drivers/gpu/drm/i915/display/intel_dmc_regs.h' using previous resolution.
+Resolved 'drivers/gpu/drm/i915/display/intel_dp.c' using previous resolution.
+Resolved 'drivers/gpu/drm/i915/gt/intel_rps.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master 7abd801158ce] Merge branch 'for-linux-next' of git://anongit.freedesktop.org/drm-intel
+$ git diff -M --stat --summary HEAD^..
+ drivers/gpu/drm/i915/Makefile                      |    3 +
+ drivers/gpu/drm/i915/TODO.txt                      |    2 +-
+ drivers/gpu/drm/i915/display/g4x_dp.c              |   22 +-
+ drivers/gpu/drm/i915/display/hsw_ips.c             |    4 +-
+ drivers/gpu/drm/i915/display/icl_dsi.c             |   11 +-
+ drivers/gpu/drm/i915/display/intel_audio.c         |    1 +
+ drivers/gpu/drm/i915/display/intel_audio_regs.h    |  160 ++
+ drivers/gpu/drm/i915/display/intel_backlight.c     |   23 +-
+ drivers/gpu/drm/i915/display/intel_bios.c          |  652 ++++---
+ drivers/gpu/drm/i915/display/intel_bios.h          |    7 +
+ drivers/gpu/drm/i915/display/intel_bw.c            |    6 +-
+ drivers/gpu/drm/i915/display/intel_cdclk.c         |   16 +-
+ drivers/gpu/drm/i915/display/intel_color.c         |    2 +-
+ .../gpu/drm/i915/display/intel_crtc_state_dump.c   |  314 ++++
+ .../gpu/drm/i915/display/intel_crtc_state_dump.h   |   16 +
+ drivers/gpu/drm/i915/display/intel_ddi.c           |   52 +-
+ drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |   37 +-
+ drivers/gpu/drm/i915/display/intel_display.c       | 1826 ++------------------
+ drivers/gpu/drm/i915/display/intel_display.h       |   19 +
+ drivers/gpu/drm/i915/display/intel_display_power.c |    6 +-
+ .../drm/i915/display/intel_display_power_well.c    |    4 +-
+ drivers/gpu/drm/i915/display/intel_display_types.h |   89 +-
+ drivers/gpu/drm/i915/display/intel_dmc.c           |  103 +-
+ drivers/gpu/drm/i915/display/intel_dmc_regs.h      |   41 +
+ drivers/gpu/drm/i915/display/intel_dp.c            |   94 +-
+ drivers/gpu/drm/i915/display/intel_dp.h            |    2 +
+ .../gpu/drm/i915/display/intel_dp_aux_backlight.c  |    6 +-
+ drivers/gpu/drm/i915/display/intel_dpll.c          |   89 +-
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c      |  409 +++--
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.h      |    8 +
+ drivers/gpu/drm/i915/display/intel_drrs.c          |    3 -
+ drivers/gpu/drm/i915/display/intel_dsi.c           |    2 +-
+ .../gpu/drm/i915/display/intel_dsi_dcs_backlight.c |    9 +-
+ drivers/gpu/drm/i915/display/intel_dsi_vbt.c       |   56 +-
+ drivers/gpu/drm/i915/display/intel_fbc.c           |    4 +-
+ drivers/gpu/drm/i915/display/intel_hdcp.c          |    2 +-
+ drivers/gpu/drm/i915/display/intel_hotplug.c       |    3 +-
+ drivers/gpu/drm/i915/display/intel_lvds.c          |    8 +-
+ drivers/gpu/drm/i915/display/intel_modeset_setup.c |  734 ++++++++
+ drivers/gpu/drm/i915/display/intel_modeset_setup.h |   15 +
+ .../gpu/drm/i915/display/intel_modeset_verify.c    |  246 +++
+ .../gpu/drm/i915/display/intel_modeset_verify.h    |   21 +
+ drivers/gpu/drm/i915/display/intel_opregion.c      |   14 +
+ drivers/gpu/drm/i915/display/intel_opregion.h      |    7 +
+ drivers/gpu/drm/i915/display/intel_overlay.c       |    2 -
+ drivers/gpu/drm/i915/display/intel_panel.c         |   66 +-
+ drivers/gpu/drm/i915/display/intel_panel.h         |    3 +-
+ drivers/gpu/drm/i915/display/intel_pch_refclk.c    |   91 +-
+ drivers/gpu/drm/i915/display/intel_pps.c           |  129 +-
+ drivers/gpu/drm/i915/display/intel_pps.h           |    1 +
+ drivers/gpu/drm/i915/display/intel_psr.c           |   72 +-
+ drivers/gpu/drm/i915/display/intel_sdvo.c          |    5 +-
+ drivers/gpu/drm/i915/display/intel_snps_phy.c      |   77 +-
+ drivers/gpu/drm/i915/display/intel_snps_phy.h      |    5 +-
+ drivers/gpu/drm/i915/display/intel_tc.c            |    3 +-
+ drivers/gpu/drm/i915/display/intel_vbt_defs.h      |   67 +-
+ drivers/gpu/drm/i915/display/intel_vrr.c           |   30 +-
+ drivers/gpu/drm/i915/display/intel_vrr.h           |    4 +-
+ drivers/gpu/drm/i915/display/vlv_dsi.c             |   14 +-
+ .../gpu/drm/i915/gt/intel_execlists_submission.c   |    2 +-
+ drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c      |    4 +-
+ drivers/gpu/drm/i915/gt/intel_llc.c                |    3 +-
+ drivers/gpu/drm/i915/gt/intel_rc6.c                |    4 +-
+ drivers/gpu/drm/i915/gt/intel_ring.c               |    3 +-
+ drivers/gpu/drm/i915/gt/intel_rps.c                |    5 +-
+ drivers/gpu/drm/i915/gt/selftest_llc.c             |    2 +-
+ drivers/gpu/drm/i915/gt/selftest_rps.c             |    2 +-
+ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c         |    2 +-
+ drivers/gpu/drm/i915/i915_driver.c                 |   12 +-
+ drivers/gpu/drm/i915/i915_drv.h                    |   70 +-
+ drivers/gpu/drm/i915/i915_gem.h                    |   39 -
+ drivers/gpu/drm/i915/i915_pci.c                    |    2 +
+ drivers/gpu/drm/i915/i915_reg.h                    |  154 +-
+ drivers/gpu/drm/i915/i915_scheduler.h              |    1 +
+ drivers/gpu/drm/i915/i915_tasklet.h                |   43 +
+ drivers/gpu/drm/i915/i915_utils.h                  |   40 -
+ drivers/gpu/drm/i915/intel_device_info.h           |    1 +
+ drivers/gpu/drm/i915/intel_dram.c                  |    2 +-
+ drivers/gpu/drm/i915/intel_gvt_mmio_table.c        |    2 +
+ drivers/gpu/drm/i915/intel_pcode.c                 |   93 +-
+ drivers/gpu/drm/i915/intel_pcode.h                 |   20 +-
+ drivers/gpu/drm/i915/intel_pm.c                    |  148 +-
+ drivers/gpu/drm/i915/intel_pm.h                    |   14 +-
+ drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c       |    5 +-
+ 84 files changed, 3633 insertions(+), 2757 deletions(-)
+ create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h
+ create mode 100644 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+ create mode 100644 drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+ create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.c
+ create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.h
+ create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
+ create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h
+ create mode 100644 drivers/gpu/drm/i915/i915_tasklet.h
+Merging drm-tegra/drm/tegra/for-next (fd27de58b0ad dt-bindings: display: tegra: Convert to json-schema)
+$ git merge -m Merge branch 'drm/tegra/for-next' of git://anongit.freedesktop.org/tegra/linux.git drm-tegra/drm/tegra/for-next
+Merge made by the 'ort' strategy.
+ .../display/tegra/nvidia,tegra114-mipi.txt         |  41 --
+ .../display/tegra/nvidia,tegra114-mipi.yaml        |  74 +++
+ .../display/tegra/nvidia,tegra124-dpaux.yaml       | 149 +++++
+ .../display/tegra/nvidia,tegra124-sor.yaml         | 206 +++++++
+ .../display/tegra/nvidia,tegra124-vic.yaml         |  71 +++
+ .../bindings/display/tegra/nvidia,tegra186-dc.yaml |  85 +++
+ .../display/tegra/nvidia,tegra186-display.yaml     | 310 ++++++++++
+ .../display/tegra/nvidia,tegra186-dsi-padctl.yaml  |  45 ++
+ .../bindings/display/tegra/nvidia,tegra20-dc.yaml  | 181 ++++++
+ .../bindings/display/tegra/nvidia,tegra20-dsi.yaml | 159 +++++
+ .../bindings/display/tegra/nvidia,tegra20-epp.yaml |  70 +++
+ .../display/tegra/nvidia,tegra20-gr2d.yaml         |  73 +++
+ .../display/tegra/nvidia,tegra20-gr3d.yaml         | 214 +++++++
+ .../display/tegra/nvidia,tegra20-hdmi.yaml         | 126 ++++
+ .../display/tegra/nvidia,tegra20-host1x.txt        | 675 ---------------------
+ .../display/tegra/nvidia,tegra20-host1x.yaml       | 347 +++++++++++
+ .../bindings/display/tegra/nvidia,tegra20-isp.yaml |  67 ++
+ .../bindings/display/tegra/nvidia,tegra20-mpe.yaml |  73 +++
+ .../bindings/display/tegra/nvidia,tegra20-tvo.yaml |  58 ++
+ .../bindings/display/tegra/nvidia,tegra20-vi.yaml  | 163 +++++
+ .../display/tegra/nvidia,tegra210-csi.yaml         |  52 ++
+ .../pinctrl/nvidia,tegra124-dpaux-padctl.txt       |  59 --
+ 22 files changed, 2523 insertions(+), 775 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+ delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
+ delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
+Merging drm-msm/msm-next (24df12013853 MAINTAINERS: Add Dmitry as MSM DRM driver co-maintainer)
+$ git merge -m Merge branch 'msm-next' of https://gitlab.freedesktop.org/drm/msm.git drm-msm/msm-next
+Already up to date.
+Merging drm-msm-lumag/msm-next-lumag (2f49e2e6b886 Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi', 'msm-next-lumag-mdp5' and 'msm-next-lumag-mdp4' into msm-next-lumag)
+$ git merge -m Merge branch 'msm-next-lumag' of https://gitlab.freedesktop.org/lumag/msm.git drm-msm-lumag/msm-next-lumag
+Auto-merging drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+Auto-merging drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+Auto-merging drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+Auto-merging drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+Auto-merging drivers/gpu/drm/msm/dp/dp_ctrl.c
+Auto-merging drivers/gpu/drm/msm/dp/dp_parser.c
+Auto-merging drivers/gpu/drm/msm/dsi/dsi_host.c
+Auto-merging drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+Merge made by the 'ort' strategy.
+ .../bindings/display/msm/dp-controller.yaml        |   8 +-
+ .../devicetree/bindings/display/msm/hdmi.txt       |  99 ----
+ .../devicetree/bindings/display/msm/hdmi.yaml      | 232 ++++++++++
+ .../bindings/phy/qcom,hdmi-phy-other.yaml          | 104 +++++
+ .../devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml |  85 ++++
+ Documentation/gpu/drm-usage-stats.rst              |  21 +
+ arch/arm/boot/dts/qcom-apq8064-ifc6410.dts         |   1 -
+ drivers/gpu/drm/msm/Makefile                       |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c      |  24 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h      |   4 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 111 ++++-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |   5 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 150 ++++--
+ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  26 +-
+ .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c    |  18 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     | 510 +++++++++------------
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |  20 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c         |   5 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h         |   2 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c        |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c  |   5 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h  |   2 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c        |  20 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h        |   8 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |  49 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c     |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c    |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c        |   5 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h        |   4 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c         |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |  49 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |  18 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c        |   5 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c          |   1 -
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |  11 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |   2 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          |  20 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |   2 +-
+ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |   2 +-
+ drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c           |  29 +-
+ drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h           |   6 -
+ drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c           |   5 +
+ drivers/gpu/drm/msm/dp/dp_clk_util.c               | 120 -----
+ drivers/gpu/drm/msm/dp/dp_clk_util.h               |  38 --
+ drivers/gpu/drm/msm/dp/dp_ctrl.c                   |  13 +-
+ drivers/gpu/drm/msm/dp/dp_display.c                |   4 +-
+ drivers/gpu/drm/msm/dp/dp_parser.c                 |  43 +-
+ drivers/gpu/drm/msm/dp/dp_parser.h                 |   6 +-
+ drivers/gpu/drm/msm/dp/dp_power.c                  | 104 +----
+ drivers/gpu/drm/msm/dsi/dsi_host.c                 |  48 +-
+ drivers/gpu/drm/msm/hdmi/hdmi.c                    | 126 ++---
+ drivers/gpu/drm/msm/hdmi/hdmi.h                    |  15 +-
+ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c             |  10 -
+ drivers/gpu/drm/msm/hdmi/hdmi_hpd.c                |  62 +--
+ drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c           |  12 +
+ drivers/gpu/drm/msm/msm_drv.c                      |  19 +-
+ drivers/gpu/drm/msm/msm_drv.h                      |  10 -
+ drivers/gpu/drm/msm/msm_fence.c                    |  13 +-
+ drivers/gpu/drm/msm/msm_gem.c                      |   2 +-
+ drivers/gpu/drm/msm/msm_gem.h                      |   1 -
+ drivers/gpu/drm/msm/msm_gpu.c                      |  21 +-
+ drivers/gpu/drm/msm/msm_gpu.h                      |  19 +
+ drivers/gpu/drm/msm/msm_gpu_devfreq.c              |   2 +-
+ include/drm/drm_gem.h                              |  26 +-
+ 65 files changed, 1276 insertions(+), 1112 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.txt
+ create mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.yaml
+ create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml
+ create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml
+ delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.c
+ delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.h
+Merging imx-drm/imx-drm/next (927d8fd465ad drm/imx: ipuv3-plane: Remove redundant color encoding and range initialisation)
+$ git merge -m Merge branch 'imx-drm/next' of https://git.pengutronix.de/git/pza/linux imx-drm/imx-drm/next
+Already up to date.
+Merging etnaviv/etnaviv/next (2829a9fcb738 drm/etnaviv: reap idle softpin mappings when necessary)
+$ git merge -m Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux etnaviv/etnaviv/next
+Already up to date.
+Merging fbdev/for-next (cb5177336ecb video: fbdev: omap: Remove duplicate 'the' in comment)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git fbdev/for-next
+Auto-merging drivers/video/fbdev/simplefb.c
+Merge made by the 'ort' strategy.
+ drivers/video/fbdev/au1100fb.c                  |  6 ++----
+ drivers/video/fbdev/cirrusfb.c                  |  6 ------
+ drivers/video/fbdev/intelfb/intelfbdrv.c        |  4 ++--
+ drivers/video/fbdev/intelfb/intelfbhw.c         | 12 +++++-------
+ drivers/video/fbdev/omap/sossi.c                |  2 +-
+ drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c |  2 +-
+ drivers/video/fbdev/pxa3xx-gcu.c                |  2 +-
+ drivers/video/fbdev/simplefb.c                  |  3 +--
+ drivers/video/fbdev/skeletonfb.c                | 15 ++++++++-------
+ 9 files changed, 21 insertions(+), 31 deletions(-)
+Merging regmap/for-next (301fd0553383 Merge remote-tracking branch 'regmap/for-5.20' into regmap-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git regmap/for-next
+Merge made by the 'ort' strategy.
+ drivers/base/regmap/regcache.c |  2 +-
+ drivers/base/regmap/regmap.c   | 22 ++++++++++++++++++++++
+ include/linux/regmap.h         | 37 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 60 insertions(+), 1 deletion(-)
+Merging sound/for-next (3809db6430bf ALSA: rawmidi: Take buffer refcount while draining output)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git sound/for-next
+Merge made by the 'ort' strategy.
+ include/sound/control.h  |   2 +-
+ include/sound/core.h     |   6 ++
+ include/sound/rawmidi.h  |   6 +-
+ sound/core/Kconfig       |  37 +++++--
+ sound/core/control.c     | 267 +++++++++++++++++++++++++++++++++------------
+ sound/core/init.c        |   4 +
+ sound/core/rawmidi.c     | 274 +++++++++++++++++++++++++++++------------------
+ sound/soc/soc-topology.c |   2 +-
+ 8 files changed, 411 insertions(+), 187 deletions(-)
+Merging sound-asoc/for-next (332787fa90a4 Merge remote-tracking branch 'asoc/for-5.20' into asoc-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git sound-asoc/for-next
+Auto-merging drivers/base/regmap/regmap.c
+Auto-merging sound/soc/bcm/cygnus-ssp.c
+Merge made by the 'ort' strategy.
+ .../bindings/dsp/mediatek,mt8186-dsp.yaml          |   91 +
+ .../bindings/dsp/mediatek,mt8195-dsp.yaml          |   10 +-
+ .../bindings/sound/atmel-sam9x5-wm8731-audio.txt   |    2 +-
+ .../devicetree/bindings/sound/fsl,mqs.txt          |    2 +-
+ .../bindings/sound/nvidia,tegra210-ahub.yaml       |    4 +
+ .../bindings/sound/nvidia,tegra210-mbdrc.yaml      |   47 +
+ .../bindings/sound/nvidia,tegra210-ope.yaml        |   87 +
+ .../bindings/sound/nvidia,tegra210-peq.yaml        |   48 +
+ .../devicetree/bindings/sound/nxp,tfa989x.yaml     |    1 +
+ .../devicetree/bindings/sound/rockchip-i2s.yaml    |    7 +
+ drivers/firmware/mtk-adsp-ipc.c                    |   36 +-
+ drivers/gpu/drm/bridge/sii902x.c                   |    5 +-
+ .../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c    |    2 +-
+ drivers/gpu/drm/exynos/exynos_hdmi.c               |    8 +-
+ drivers/gpu/drm/i2c/tda998x_drv.c                  |    6 +-
+ drivers/gpu/drm/sti/sti_hdmi.c                     |    8 +-
+ drivers/soundwire/qcom.c                           |   10 +
+ include/linux/soundwire/sdw_intel.h                |    2 +
+ include/sound/cs35l41.h                            |    3 +
+ include/sound/hdmi-codec.h                         |    4 +-
+ include/sound/pcm.h                                |   19 +-
+ include/sound/simple_card_utils.h                  |    2 +-
+ include/sound/soc-acpi-intel-match.h               |    2 +
+ include/sound/soc-card.h                           |    1 +
+ include/sound/soc-component.h                      |    5 -
+ include/sound/soc-dai.h                            |    6 +
+ include/sound/soc.h                                |   15 +-
+ include/sound/sof.h                                |    1 +
+ include/sound/sof/dai-amd.h                        |    7 +
+ include/sound/sof/dai.h                            |    2 +-
+ include/sound/sof/ipc4/header.h                    |    8 +
+ include/uapi/sound/sof/abi.h                       |    2 +
+ include/uapi/sound/sof/header.h                    |   30 +
+ include/uapi/sound/sof/tokens.h                    |   44 +
+ sound/soc/amd/acp-config.c                         |   30 +
+ sound/soc/amd/acp/Kconfig                          |    1 +
+ sound/soc/amd/acp/acp-mach-common.c                |  233 +-
+ sound/soc/amd/acp/acp-mach.h                       |    3 +
+ sound/soc/amd/acp/acp-pdm.c                        |    2 +-
+ sound/soc/amd/acp/acp-renoir.c                     |   10 +-
+ sound/soc/amd/acp/acp-sof-mach.c                   |   30 +
+ sound/soc/amd/mach-config.h                        |    1 +
+ sound/soc/amd/vangogh/acp5x-i2s.c                  |    4 +-
+ sound/soc/atmel/atmel-i2s.c                        |    4 +-
+ sound/soc/atmel/atmel_ssc_dai.c                    |   18 +-
+ sound/soc/atmel/mchp-i2s-mcc.c                     |    8 +-
+ sound/soc/atmel/mchp-pdmc.c                        |    4 +-
+ sound/soc/atmel/mikroe-proto.c                     |    4 +-
+ sound/soc/au1x/i2sc.c                              |    2 +-
+ sound/soc/au1x/psc-i2s.c                           |    4 +-
+ sound/soc/bcm/bcm2835-i2s.c                        |   20 +-
+ sound/soc/bcm/cygnus-ssp.c                         |    4 +-
+ sound/soc/cirrus/ep93xx-i2s.c                      |    4 +-
+ sound/soc/codecs/Kconfig                           |   10 +
+ sound/soc/codecs/Makefile                          |    2 +
+ sound/soc/codecs/ab8500-codec.c                    |    2 -
+ sound/soc/codecs/ab8500-codec.h                    |    2 -
+ sound/soc/codecs/ak4613.c                          |    6 -
+ sound/soc/codecs/cros_ec_codec.c                   |    1 +
+ sound/soc/codecs/cs35l41-lib.c                     |   82 +-
+ sound/soc/codecs/cs35l41.c                         |   71 +-
+ sound/soc/codecs/cs35l45-i2c.c                     |    4 +-
+ sound/soc/codecs/cs35l45.c                         |    6 +-
+ sound/soc/codecs/cs35l45.h                         |    4 +-
+ sound/soc/codecs/cs4270.c                          |    1 -
+ sound/soc/codecs/cs42l42.c                         |    3 +-
+ sound/soc/codecs/cx2072x.c                         |   17 +-
+ sound/soc/codecs/da7210.c                          |    2 +
+ sound/soc/codecs/da7219.c                          |    6 -
+ sound/soc/codecs/da732x.c                          |    6 -
+ sound/soc/codecs/hda-dai.c                         |  102 +
+ sound/soc/codecs/hda.c                             |  395 +++
+ sound/soc/codecs/hda.h                             |   19 +
+ sound/soc/codecs/hdmi-codec.c                      |   18 +-
+ sound/soc/codecs/lm49453.c                         |    6 -
+ sound/soc/codecs/max98090.c                        |   12 +-
+ sound/soc/codecs/max98373.c                        |   14 +-
+ sound/soc/codecs/max98390.c                        |    2 +-
+ sound/soc/codecs/max9860.c                         |    6 +-
+ sound/soc/codecs/msm8916-wcd-digital.c             |   46 +-
+ sound/soc/codecs/mt6358.c                          |    1 +
+ sound/soc/codecs/nau8822.c                         |   14 +
+ sound/soc/codecs/nau8822.h                         |    2 +
+ sound/soc/codecs/rk3328_codec.c                    |    6 +-
+ sound/soc/codecs/rt1308-sdw.c                      |   12 +
+ sound/soc/codecs/rt1316-sdw.c                      |   12 +
+ sound/soc/codecs/rt274.c                           |    9 +-
+ sound/soc/codecs/rt286.c                           |   17 +-
+ sound/soc/codecs/rt286.h                           |    2 -
+ sound/soc/codecs/rt298.c                           |   17 +-
+ sound/soc/codecs/rt298.h                           |    2 -
+ sound/soc/codecs/rt700.c                           |    5 +
+ sound/soc/codecs/rt711-sdca.c                      |    5 +
+ sound/soc/codecs/rt711.c                           |    5 +
+ sound/soc/codecs/rt715-sdca.c                      |   12 +
+ sound/soc/codecs/rt715.c                           |   12 +
+ sound/soc/codecs/ssm2518.c                         |    4 +-
+ sound/soc/codecs/ssm2602.c                         |    6 +-
+ sound/soc/codecs/ssm4567.c                         |    4 +-
+ sound/soc/codecs/sta32x.c                          |    4 +-
+ sound/soc/codecs/sta350.c                          |    4 +-
+ sound/soc/codecs/sti-sas.c                         |    6 +-
+ sound/soc/codecs/tas2552.c                         |   10 +-
+ sound/soc/codecs/tas2770.c                         |    6 +-
+ sound/soc/codecs/tas5086.c                         |    2 +-
+ sound/soc/codecs/tas5720.c                         |    4 +-
+ sound/soc/codecs/tas6424.c                         |    6 +-
+ sound/soc/codecs/tfa9879.c                         |    4 +-
+ sound/soc/codecs/tfa989x.c                         |   30 +
+ sound/soc/codecs/tlv320adc3xxx.c                   |    3 +-
+ sound/soc/codecs/tlv320adcx140.c                   |   10 +-
+ sound/soc/codecs/tlv320aic23.c                     |    7 +-
+ sound/soc/codecs/tlv320aic26.c                     |   15 +-
+ sound/soc/codecs/tlv320aic31xx.c                   |   19 +-
+ sound/soc/codecs/tlv320aic32x4.c                   |    9 +-
+ sound/soc/codecs/tlv320aic3x.c                     |   11 +-
+ sound/soc/codecs/tlv320dac33.c                     |   12 +-
+ sound/soc/codecs/twl4030.c                         |  101 +-
+ sound/soc/codecs/uda1334.c                         |    2 +-
+ sound/soc/codecs/wcd-mbhc-v2.c                     |    2 +-
+ sound/soc/codecs/wcd9335.c                         |   85 +-
+ sound/soc/dwc/dwc-i2s.c                            |    8 +-
+ sound/soc/fsl/fsl_asrc_dma.c                       |   18 +-
+ sound/soc/fsl/fsl_audmix.c                         |    6 +-
+ sound/soc/fsl/fsl_esai.c                           |    8 +-
+ sound/soc/fsl/fsl_mqs.c                            |  135 +-
+ sound/soc/fsl/fsl_sai.c                            |   72 +-
+ sound/soc/fsl/fsl_ssi.c                            |   22 +-
+ sound/soc/fsl/fsl_xcvr.c                           |    9 +
+ sound/soc/fsl/imx-audmix.c                         |    4 +-
+ sound/soc/fsl/imx-audmux.c                         |   24 +-
+ sound/soc/fsl/imx-card.c                           |    2 +-
+ sound/soc/fsl/pcm030-audio-fabric.c                |    5 +-
+ sound/soc/generic/simple-card-utils.c              |   18 +-
+ sound/soc/generic/test-component.c                 |   18 +-
+ sound/soc/hisilicon/hi6210-i2s.c                   |   18 +-
+ sound/soc/img/img-i2s-in.c                         |    4 +-
+ sound/soc/img/img-i2s-out.c                        |    6 +-
+ sound/soc/intel/Kconfig                            |    3 +
+ sound/soc/intel/atom/sst-atom-controls.c           |    8 +-
+ sound/soc/intel/atom/sst/sst.c                     |    2 +-
+ sound/soc/intel/atom/sst/sst_ipc.c                 |    8 +-
+ sound/soc/intel/avs/Makefile                       |    3 +
+ sound/soc/intel/avs/boards/Kconfig                 |  121 +
+ sound/soc/intel/avs/boards/Makefile                |   27 +
+ sound/soc/intel/avs/boards/da7219.c                |  282 ++
+ sound/soc/intel/avs/boards/dmic.c                  |   93 +
+ sound/soc/intel/avs/boards/hdaudio.c               |  294 ++
+ sound/soc/intel/avs/boards/i2s_test.c              |  180 ++
+ sound/soc/intel/avs/boards/max98357a.c             |  154 ++
+ sound/soc/intel/avs/boards/max98373.c              |  239 ++
+ sound/soc/intel/avs/boards/nau8825.c               |  353 +++
+ sound/soc/intel/avs/boards/rt274.c                 |  310 +++
+ sound/soc/intel/avs/boards/rt286.c                 |  281 ++
+ sound/soc/intel/avs/boards/rt298.c                 |  281 ++
+ sound/soc/intel/avs/boards/rt5682.c                |  340 +++
+ sound/soc/intel/avs/boards/ssm4567.c               |  271 ++
+ sound/soc/intel/boards/Kconfig                     |    1 -
+ sound/soc/intel/boards/broadwell.c                 |   18 +-
+ sound/soc/intel/boards/bxt_da7219_max98357a.c      |   21 +-
+ sound/soc/intel/boards/bxt_rt298.c                 |    2 +-
+ sound/soc/intel/boards/bytcht_cx2072x.c            |    2 +-
+ sound/soc/intel/boards/bytcht_da7213.c             |    2 +-
+ sound/soc/intel/boards/bytcht_es8316.c             |    2 +-
+ sound/soc/intel/boards/bytcht_nocodec.c            |    2 +-
+ sound/soc/intel/boards/bytcr_rt5640.c              |    4 +-
+ sound/soc/intel/boards/bytcr_rt5651.c              |    4 +-
+ sound/soc/intel/boards/bytcr_wm5102.c              |    2 +-
+ sound/soc/intel/boards/cht_bsw_max98090_ti.c       |    3 +-
+ sound/soc/intel/boards/cht_bsw_rt5645.c            |    8 +-
+ sound/soc/intel/boards/cht_bsw_rt5672.c            |    2 +-
+ sound/soc/intel/boards/cml_rt1011_rt5682.c         |   23 +-
+ sound/soc/intel/boards/glk_rt5682_max98357a.c      |   21 +-
+ sound/soc/intel/boards/hda_dsp_common.c            |    4 +-
+ sound/soc/intel/boards/kbl_da7219_max98357a.c      |   21 +-
+ sound/soc/intel/boards/kbl_da7219_max98927.c       |   21 +-
+ sound/soc/intel/boards/kbl_rt5663_max98927.c       |   21 +-
+ .../soc/intel/boards/kbl_rt5663_rt5514_max98927.c  |   21 +-
+ sound/soc/intel/boards/skl_hda_dsp_generic.c       |    4 +-
+ sound/soc/intel/boards/skl_nau88l25_max98357a.c    |   19 +-
+ sound/soc/intel/boards/skl_nau88l25_ssm4567.c      |   19 +-
+ sound/soc/intel/boards/skl_rt286.c                 |    2 +-
+ sound/soc/intel/boards/sof_cs42l42.c               |   23 +-
+ sound/soc/intel/boards/sof_da7219_max98373.c       |   23 +-
+ sound/soc/intel/boards/sof_nau8825.c               |   23 +-
+ sound/soc/intel/boards/sof_pcm512x.c               |    2 +-
+ sound/soc/intel/boards/sof_realtek_common.c        |   24 +-
+ sound/soc/intel/boards/sof_realtek_common.h        |    6 +-
+ sound/soc/intel/boards/sof_rt5682.c                |   25 +-
+ sound/soc/intel/boards/sof_sdw.c                   |   34 +-
+ sound/soc/intel/common/Makefile                    |    1 +
+ sound/soc/intel/common/soc-acpi-intel-mtl-match.c  |   72 +
+ sound/soc/intel/keembay/kmb_platform.c             |    4 +-
+ sound/soc/intel/skylake/skl-topology.c             |    6 -
+ sound/soc/jz4740/jz4740-i2s.c                      |   10 +-
+ sound/soc/mediatek/mt6797/mt6797-mt6351.c          |    6 +-
+ sound/soc/mediatek/mt8173/mt8173-afe-pcm.c         |    6 +-
+ sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c   |   10 +-
+ sound/soc/mediatek/mt8173/mt8173-rt5650.c          |    9 +-
+ sound/soc/mediatek/mt8186/mt8186-afe-clk.c         |  651 +++++
+ sound/soc/mediatek/mt8186/mt8186-afe-clk.h         |  106 +
+ sound/soc/mediatek/mt8186/mt8186-afe-gpio.c        |  243 ++
+ sound/soc/mediatek/mt8186/mt8186-afe-gpio.h        |   19 +
+ sound/soc/mediatek/mt8186/mt8186-audsys-clk.c      |  150 +
+ sound/soc/mediatek/mt8186/mt8186-audsys-clk.h      |   15 +
+ sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h    |   45 +
+ sound/soc/mediatek/mt8186/mt8186-dai-adda.c        |  873 ++++++
+ sound/soc/mediatek/mt8186/mt8186-dai-hostless.c    |  298 ++
+ sound/soc/mediatek/mt8186/mt8186-dai-hw-gain.c     |  236 ++
+ sound/soc/mediatek/mt8186/mt8186-dai-i2s.c         | 1286 +++++++++
+ sound/soc/mediatek/mt8186/mt8186-dai-pcm.c         |  423 +++
+ sound/soc/mediatek/mt8186/mt8186-dai-src.c         |  695 +++++
+ sound/soc/mediatek/mt8186/mt8186-dai-tdm.c         |  698 +++++
+ sound/soc/mediatek/mt8186/mt8186-interconnection.h |   69 +
+ sound/soc/mediatek/mt8186/mt8186-misc-control.c    |  252 ++
+ sound/soc/mediatek/mt8186/mt8186-reg.h             | 2913 ++++++++++++++++++++
+ sound/soc/mediatek/mt8195/mt8195-afe-clk.c         |    8 +-
+ sound/soc/mediatek/mt8195/mt8195-dai-etdm.c        |    6 +-
+ sound/soc/mediatek/mt8195/mt8195-dai-pcm.c         |    6 +-
+ sound/soc/meson/aiu-encoder-i2s.c                  |    2 +-
+ sound/soc/meson/axg-tdm-interface.c                |   14 +-
+ sound/soc/meson/meson-codec-glue.c                 |    2 +-
+ sound/soc/mxs/mxs-saif.c                           |    4 +-
+ sound/soc/pxa/magician.c                           |    8 +-
+ sound/soc/pxa/mmp-sspa.c                           |    6 +-
+ sound/soc/pxa/pxa-ssp.c                            |   22 +-
+ sound/soc/pxa/pxa2xx-i2s.c                         |    6 +-
+ sound/soc/qcom/apq8016_sbc.c                       |    2 +-
+ sound/soc/qcom/qdsp6/audioreach.c                  |    4 +-
+ sound/soc/qcom/qdsp6/q6adm.c                       |    6 +-
+ sound/soc/qcom/qdsp6/q6afe.c                       |    6 +-
+ sound/soc/qcom/sc7180.c                            |    2 +-
+ sound/soc/qcom/sdm845.c                            |    6 +-
+ sound/soc/qcom/sm8250.c                            |    4 +-
+ sound/soc/rockchip/rk3288_hdmi_analog.c            |    4 +-
+ sound/soc/rockchip/rockchip_i2s.c                  |   85 +-
+ sound/soc/rockchip/rockchip_i2s_tdm.c              |    6 +-
+ sound/soc/samsung/aries_wm8994.c                   |    6 +-
+ sound/soc/samsung/i2s.c                            |    6 +-
+ sound/soc/samsung/pcm.c                            |    4 +-
+ sound/soc/samsung/s3c-i2s-v2.c                     |    6 +-
+ sound/soc/samsung/s3c24xx-i2s.c                    |    6 +-
+ sound/soc/samsung/snow.c                           |    2 +-
+ sound/soc/sh/fsi.c                                 |    6 +-
+ sound/soc/sh/rcar/core.c                           |    4 +-
+ sound/soc/sh/rz-ssi.c                              |    2 +-
+ sound/soc/sh/ssi.c                                 |   10 +-
+ sound/soc/soc-card.c                               |    6 +
+ sound/soc/soc-core.c                               |   19 +-
+ sound/soc/soc-dai.c                                |    3 +-
+ sound/soc/soc-ops.c                                |   51 +-
+ sound/soc/soc-topology-test.c                      |    4 +-
+ sound/soc/sof/Kconfig                              |    7 +
+ sound/soc/sof/Makefile                             |   16 +-
+ sound/soc/sof/amd/Kconfig                          |    1 +
+ sound/soc/sof/amd/acp-dsp-offset.h                 |    2 +
+ sound/soc/sof/amd/acp.c                            |   36 +
+ sound/soc/sof/amd/acp.h                            |    4 +
+ sound/soc/sof/amd/pci-rn.c                         |    4 +
+ sound/soc/sof/amd/renoir.c                         |    4 +
+ sound/soc/sof/core.c                               |    7 +-
+ sound/soc/sof/debug.c                              |    5 +-
+ sound/soc/sof/imx/Kconfig                          |    1 +
+ sound/soc/sof/intel/Kconfig                        |   27 +
+ sound/soc/sof/intel/Makefile                       |    4 +-
+ sound/soc/sof/intel/apl.c                          |    1 +
+ sound/soc/sof/intel/cnl.c                          |    2 +
+ sound/soc/sof/intel/hda-dai.c                      |  208 +-
+ sound/soc/sof/intel/hda-dsp.c                      |   19 +-
+ sound/soc/sof/intel/hda-loader.c                   |   18 +-
+ sound/soc/sof/intel/hda-stream.c                   |    6 +-
+ sound/soc/sof/intel/hda.h                          |    5 +
+ sound/soc/sof/intel/icl.c                          |    1 +
+ sound/soc/sof/intel/mtl.c                          |  799 ++++++
+ sound/soc/sof/intel/mtl.h                          |   76 +
+ sound/soc/sof/intel/pci-apl.c                      |    1 +
+ sound/soc/sof/intel/pci-cnl.c                      |    1 +
+ sound/soc/sof/intel/pci-icl.c                      |    1 +
+ sound/soc/sof/intel/pci-mtl.c                      |   71 +
+ sound/soc/sof/intel/pci-tgl.c                      |    1 +
+ sound/soc/sof/intel/shim.h                         |    2 +
+ sound/soc/sof/intel/tgl.c                          |   34 +-
+ sound/soc/sof/ipc.c                                |   24 +-
+ sound/soc/sof/ipc3-dtrace.c                        |   55 +-
+ sound/soc/sof/ipc3-loader.c                        |   11 +-
+ sound/soc/sof/ipc3-pcm.c                           |    8 +-
+ sound/soc/sof/ipc3-topology.c                      |   77 +-
+ sound/soc/sof/ipc3.c                               |   25 +-
+ sound/soc/sof/ipc4-control.c                       |  216 ++
+ sound/soc/sof/ipc4-pcm.c                           |  230 ++
+ sound/soc/sof/ipc4-priv.h                          |    7 +
+ sound/soc/sof/ipc4-topology.c                      | 1760 ++++++++++++
+ sound/soc/sof/ipc4-topology.h                      |  245 ++
+ sound/soc/sof/ipc4.c                               |   45 +-
+ sound/soc/sof/mediatek/Kconfig                     |    1 +
+ sound/soc/sof/mediatek/adsp_helper.h               |    1 +
+ sound/soc/sof/mediatek/mt8186/mt8186-clk.c         |    4 +-
+ sound/soc/sof/mediatek/mt8195/mt8195-clk.c         |    7 +
+ sound/soc/sof/mediatek/mt8195/mt8195.c             |   50 +-
+ sound/soc/sof/mediatek/mt8195/mt8195.h             |    5 +
+ sound/soc/sof/ops.h                                |    6 +
+ sound/soc/sof/pcm.c                                |   11 +
+ sound/soc/sof/sof-audio.h                          |   12 +
+ sound/soc/sof/sof-client.c                         |    4 +-
+ sound/soc/sof/sof-priv.h                           |   14 +-
+ sound/soc/sof/topology.c                           |  118 +-
+ sound/soc/stm/stm32_adfsdm.c                       |    2 +-
+ sound/soc/stm/stm32_i2s.c                          |    8 +-
+ sound/soc/stm/stm32_sai_sub.c                      |   10 +-
+ sound/soc/sunxi/sun4i-codec.c                      |   78 +-
+ sound/soc/sunxi/sun4i-i2s.c                        |   20 +-
+ sound/soc/sunxi/sun8i-codec.c                      |    6 +-
+ sound/soc/tegra/Kconfig                            |    9 +
+ sound/soc/tegra/Makefile                           |    2 +
+ sound/soc/tegra/tegra20_i2s.c                      |    6 +-
+ sound/soc/tegra/tegra210_ahub.c                    |   39 +-
+ sound/soc/tegra/tegra210_i2s.c                     |    6 +-
+ sound/soc/tegra/tegra210_mbdrc.c                   | 1014 +++++++
+ sound/soc/tegra/tegra210_mbdrc.h                   |  215 ++
+ sound/soc/tegra/tegra210_ope.c                     |  419 +++
+ sound/soc/tegra/tegra210_ope.h                     |   90 +
+ sound/soc/tegra/tegra210_peq.c                     |  434 +++
+ sound/soc/tegra/tegra210_peq.h                     |   56 +
+ sound/soc/tegra/tegra30_i2s.c                      |    6 +-
+ sound/soc/ti/davinci-i2s.c                         |   32 +-
+ sound/soc/ti/davinci-mcasp.c                       |   10 +-
+ sound/soc/ti/omap-mcbsp.c                          |   12 +-
+ sound/soc/ux500/mop500.c                           |    2 -
+ sound/soc/ux500/mop500_ab8500.c                    |    2 -
+ sound/soc/ux500/mop500_ab8500.h                    |    2 -
+ sound/soc/ux500/ux500_msp_dai.c                    |   38 +-
+ sound/soc/ux500/ux500_msp_dai.h                    |    2 -
+ sound/soc/ux500/ux500_msp_i2s.c                    |    2 -
+ sound/soc/ux500/ux500_msp_i2s.h                    |    2 -
+ sound/soc/ux500/ux500_pcm.c                        |    2 -
+ sound/soc/ux500/ux500_pcm.h                        |    2 -
+ sound/soc/xtensa/xtfpga-i2s.c                      |    4 +-
+ 337 files changed, 21278 insertions(+), 1287 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml
+ create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml
+ create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml
+ create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml
+ create mode 100644 sound/soc/codecs/hda-dai.c
+ create mode 100644 sound/soc/codecs/hda.c
+ create mode 100644 sound/soc/codecs/hda.h
+ create mode 100644 sound/soc/intel/avs/boards/Kconfig
+ create mode 100644 sound/soc/intel/avs/boards/Makefile
+ create mode 100644 sound/soc/intel/avs/boards/da7219.c
+ create mode 100644 sound/soc/intel/avs/boards/dmic.c
+ create mode 100644 sound/soc/intel/avs/boards/hdaudio.c
+ create mode 100644 sound/soc/intel/avs/boards/i2s_test.c
+ create mode 100644 sound/soc/intel/avs/boards/max98357a.c
+ create mode 100644 sound/soc/intel/avs/boards/max98373.c
+ create mode 100644 sound/soc/intel/avs/boards/nau8825.c
+ create mode 100644 sound/soc/intel/avs/boards/rt274.c
+ create mode 100644 sound/soc/intel/avs/boards/rt286.c
+ create mode 100644 sound/soc/intel/avs/boards/rt298.c
+ create mode 100644 sound/soc/intel/avs/boards/rt5682.c
+ create mode 100644 sound/soc/intel/avs/boards/ssm4567.c
+ create mode 100644 sound/soc/intel/common/soc-acpi-intel-mtl-match.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-clk.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-clk.h
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.h
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.h
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-adda.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-hostless.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-hw-gain.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-i2s.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-pcm.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-src.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-tdm.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-interconnection.h
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-misc-control.c
+ create mode 100644 sound/soc/mediatek/mt8186/mt8186-reg.h
+ create mode 100644 sound/soc/sof/intel/mtl.c
+ create mode 100644 sound/soc/sof/intel/mtl.h
+ create mode 100644 sound/soc/sof/intel/pci-mtl.c
+ create mode 100644 sound/soc/sof/ipc4-control.c
+ create mode 100644 sound/soc/sof/ipc4-pcm.c
+ create mode 100644 sound/soc/sof/ipc4-topology.c
+ create mode 100644 sound/soc/sof/ipc4-topology.h
+ create mode 100644 sound/soc/tegra/tegra210_mbdrc.c
+ create mode 100644 sound/soc/tegra/tegra210_mbdrc.h
+ create mode 100644 sound/soc/tegra/tegra210_ope.c
+ create mode 100644 sound/soc/tegra/tegra210_ope.h
+ create mode 100644 sound/soc/tegra/tegra210_peq.c
+ create mode 100644 sound/soc/tegra/tegra210_peq.h
+Merging modules/modules-next (7390b94a3c2d module: merge check_exported_symbol() into find_exported_symbol_in_section())
+$ git merge -m Merge branch 'modules-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git modules/modules-next
+Already up to date.
+Merging input/next (69cf890d8b28 Input: mtk-pmic-keys - move long press debounce mask to mtk_pmic_regs)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git input/next
+Auto-merging MAINTAINERS
+Auto-merging drivers/input/input.c
+Merge made by the 'ort' strategy.
+ .../bindings/input/fsl,mpr121-touchkey.yaml        |   4 +-
+ .../devicetree/bindings/input/gpio-keys.yaml       |   4 +-
+ .../devicetree/bindings/input/iqs269a.yaml         |   2 +-
+ .../devicetree/bindings/input/iqs626a.yaml         |   2 +-
+ .../bindings/input/microchip,cap11xx.yaml          |   2 +-
+ drivers/input/keyboard/Kconfig                     |   2 +-
+ drivers/input/keyboard/adp5588-keys.c              | 206 +++++++++------------
+ drivers/input/keyboard/cros_ec_keyb.c              |  89 ++++++---
+ drivers/input/keyboard/mtk-pmic-keys.c             |  98 +++++-----
+ drivers/input/keyboard/omap4-keypad.c              |  26 ++-
+ drivers/input/touchscreen/zinitix.c                | 112 +++++------
+ 11 files changed, 275 insertions(+), 272 deletions(-)
+Merging block/for-next (2df6d0856e60 Merge branch 'for-5.20/io_uring' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.dk/linux-block.git block/for-next
+Auto-merging MAINTAINERS
+Auto-merging fs/inode.c
+Auto-merging lib/iov_iter.c
+Merge made by the 'ort' strategy.
+ Documentation/ABI/stable/sysfs-block |     9 +
+ MAINTAINERS                          |     7 +-
+ Makefile                             |     1 +
+ block/bfq-cgroup.c                   |     8 +-
+ block/bfq-wf2q.c                     |     5 +-
+ block/bio.c                          |   114 +-
+ block/blk-core.c                     |     4 +-
+ block/blk-iocost.c                   |     2 +-
+ block/blk-merge.c                    |    69 +-
+ block/blk-mq.c                       |     8 +-
+ block/blk-mq.h                       |    12 +-
+ block/blk-sysfs.c                    |     9 +-
+ block/blk.h                          |    13 +
+ block/bounce.c                       |    13 +-
+ block/fops.c                         |    16 +-
+ drivers/block/drbd/drbd_bitmap.c     |    49 +-
+ drivers/md/dm.c                      |    17 +-
+ fs/Makefile                          |     2 -
+ fs/inode.c                           |   168 +-
+ fs/io_uring.c                        | 13253 ---------------------------------
+ fs/iomap/buffered-io.c               |    71 +-
+ fs/iomap/direct-io.c                 |     4 +-
+ fs/read_write.c                      |     4 +-
+ fs/xfs/xfs_file.c                    |    11 +-
+ fs/xfs/xfs_iomap.c                   |    11 +-
+ include/linux/blkdev.h               |    56 +-
+ include/linux/fs.h                   |     4 +
+ include/linux/io_uring_types.h       |   537 ++
+ include/linux/uio.h                  |     2 +
+ include/linux/writeback.h            |     7 +
+ include/trace/events/io_uring.h      |   215 +-
+ include/uapi/linux/io_uring.h        |    42 +-
+ io_uring/Makefile                    |    11 +
+ io_uring/advise.c                    |    99 +
+ io_uring/advise.h                    |     7 +
+ io_uring/cancel.c                    |   315 +
+ io_uring/cancel.h                    |    23 +
+ io_uring/epoll.c                     |    65 +
+ io_uring/epoll.h                     |     6 +
+ io_uring/fdinfo.c                    |   194 +
+ io_uring/fdinfo.h                    |     3 +
+ io_uring/filetable.c                 |   177 +
+ io_uring/filetable.h                 |    74 +
+ io_uring/fs.c                        |   293 +
+ io_uring/fs.h                        |    20 +
+ {fs => io_uring}/io-wq.c             |    18 +-
+ io_uring/io-wq.h                     |    83 +
+ io_uring/io_uring.c                  |  3983 ++++++++++
+ io_uring/io_uring.h                  |   246 +
+ io_uring/kbuf.c                      |   579 ++
+ io_uring/kbuf.h                      |   102 +
+ io_uring/msg_ring.c                  |   171 +
+ io_uring/msg_ring.h                  |     4 +
+ io_uring/net.c                       |   769 ++
+ io_uring/net.h                       |    43 +
+ io_uring/nop.c                       |    25 +
+ io_uring/nop.h                       |     4 +
+ io_uring/opdef.c                     |   490 ++
+ io_uring/opdef.h                     |    42 +
+ io_uring/openclose.c                 |   256 +
+ io_uring/openclose.h                 |    14 +
+ io_uring/poll.c                      |   871 +++
+ io_uring/poll.h                      |    32 +
+ io_uring/refs.h                      |    48 +
+ io_uring/rsrc.c                      |  1369 ++++
+ io_uring/rsrc.h                      |   166 +
+ io_uring/rw.c                        |  1046 +++
+ io_uring/rw.h                        |    23 +
+ fs/io-wq.h => io_uring/slist.h       |   100 +-
+ io_uring/splice.c                    |   122 +
+ io_uring/splice.h                    |     7 +
+ io_uring/sqpoll.c                    |   425 ++
+ io_uring/sqpoll.h                    |    29 +
+ io_uring/statx.c                     |    73 +
+ io_uring/statx.h                     |     5 +
+ io_uring/sync.c                      |   110 +
+ io_uring/sync.h                      |    10 +
+ io_uring/tctx.c                      |   340 +
+ io_uring/tctx.h                      |    57 +
+ io_uring/timeout.c                   |   632 ++
+ io_uring/timeout.h                   |    36 +
+ io_uring/uring_cmd.c                 |   114 +
+ io_uring/uring_cmd.h                 |    13 +
+ io_uring/xattr.c                     |   258 +
+ io_uring/xattr.h                     |    15 +
+ kernel/sched/core.c                  |     2 +-
+ lib/iov_iter.c                       |    92 +
+ mm/page-writeback.c                  |    89 +-
+ 88 files changed, 15212 insertions(+), 13731 deletions(-)
+ delete mode 100644 fs/io_uring.c
+ create mode 100644 include/linux/io_uring_types.h
+ create mode 100644 io_uring/Makefile
+ create mode 100644 io_uring/advise.c
+ create mode 100644 io_uring/advise.h
+ create mode 100644 io_uring/cancel.c
+ create mode 100644 io_uring/cancel.h
+ create mode 100644 io_uring/epoll.c
+ create mode 100644 io_uring/epoll.h
+ create mode 100644 io_uring/fdinfo.c
+ create mode 100644 io_uring/fdinfo.h
+ create mode 100644 io_uring/filetable.c
+ create mode 100644 io_uring/filetable.h
+ create mode 100644 io_uring/fs.c
+ create mode 100644 io_uring/fs.h
+ rename {fs => io_uring}/io-wq.c (99%)
+ create mode 100644 io_uring/io-wq.h
+ create mode 100644 io_uring/io_uring.c
+ create mode 100644 io_uring/io_uring.h
+ create mode 100644 io_uring/kbuf.c
+ create mode 100644 io_uring/kbuf.h
+ create mode 100644 io_uring/msg_ring.c
+ create mode 100644 io_uring/msg_ring.h
+ create mode 100644 io_uring/net.c
+ create mode 100644 io_uring/net.h
+ create mode 100644 io_uring/nop.c
+ create mode 100644 io_uring/nop.h
+ create mode 100644 io_uring/opdef.c
+ create mode 100644 io_uring/opdef.h
+ create mode 100644 io_uring/openclose.c
+ create mode 100644 io_uring/openclose.h
+ create mode 100644 io_uring/poll.c
+ create mode 100644 io_uring/poll.h
+ create mode 100644 io_uring/refs.h
+ create mode 100644 io_uring/rsrc.c
+ create mode 100644 io_uring/rsrc.h
+ create mode 100644 io_uring/rw.c
+ create mode 100644 io_uring/rw.h
+ rename fs/io-wq.h => io_uring/slist.h (56%)
+ create mode 100644 io_uring/splice.c
+ create mode 100644 io_uring/splice.h
+ create mode 100644 io_uring/sqpoll.c
+ create mode 100644 io_uring/sqpoll.h
+ create mode 100644 io_uring/statx.c
+ create mode 100644 io_uring/statx.h
+ create mode 100644 io_uring/sync.c
+ create mode 100644 io_uring/sync.h
+ create mode 100644 io_uring/tctx.c
+ create mode 100644 io_uring/tctx.h
+ create mode 100644 io_uring/timeout.c
+ create mode 100644 io_uring/timeout.h
+ create mode 100644 io_uring/uring_cmd.c
+ create mode 100644 io_uring/uring_cmd.h
+ create mode 100644 io_uring/xattr.c
+ create mode 100644 io_uring/xattr.h
+Merging device-mapper/for-next (85e123c27d5c dm mirror log: round up region bitmap size to BITS_PER_LONG)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git device-mapper/for-next
+Already up to date.
+Merging libata/for-next (2b5960a0e33b ata: pata_macio: Fix compilation warning)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata.git libata/for-next
+Merge made by the 'ort' strategy.
+ drivers/ata/libata-acpi.c      |   8 +--
+ drivers/ata/libata-core.c      |  68 +++++++++++------------
+ drivers/ata/libata-eh.c        |  30 +++++------
+ drivers/ata/libata-transport.c |   2 +-
+ drivers/ata/libata.h           |   8 +--
+ drivers/ata/pata_acpi.c        |   2 +-
+ drivers/ata/pata_ali.c         |   2 +-
+ drivers/ata/pata_amd.c         |  14 ++---
+ drivers/ata/pata_hpt366.c      |   2 +-
+ drivers/ata/pata_hpt37x.c      | 119 +++++++++++++++++++++--------------------
+ drivers/ata/pata_hpt3x2n.c     |  21 ++++----
+ drivers/ata/pata_macio.c       |   2 +-
+ drivers/ata/pata_pdc2027x.c    |   4 +-
+ drivers/ata/pata_serverworks.c |   4 +-
+ drivers/ata/pata_sis.c         |   2 +-
+ drivers/ata/pata_via.c         |   2 +-
+ include/linux/libata.h         |  51 +++++++++---------
+ 17 files changed, 172 insertions(+), 169 deletions(-)
+Merging pcmcia/pcmcia-next (2ef4bb24ff39 pcmcia: Use platform_get_irq() to get the interrupt)
+$ git merge -m Merge branch 'pcmcia-next' of git://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git pcmcia/pcmcia-next
+Already up to date.
+Merging mmc/next (bdc997a769ee mmc: core: Do not evaluate HS400 capabilities if bus has no MMC capability)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git mmc/next
+Merge made by the 'ort' strategy.
+ .../bindings/mmc/brcm,sdhci-brcmstb.yaml           |  32 +++-
+ .../devicetree/bindings/mmc/exynos-dw-mshc.txt     |  94 ----------
+ .../devicetree/bindings/mmc/mmc-spi-slot.txt       |  29 ----
+ .../devicetree/bindings/mmc/mmc-spi-slot.yaml      |  77 ++++++++
+ .../devicetree/bindings/mmc/renesas,sdhi.yaml      |   7 +-
+ .../bindings/mmc/samsung,exynos-dw-mshc.yaml       | 160 +++++++++++++++++
+ .../devicetree/bindings/mmc/sdhci-msm.yaml         |  52 +++++-
+ drivers/mmc/core/core.c                            |  10 +-
+ drivers/mmc/core/debugfs.c                         |  80 +++++++++
+ drivers/mmc/core/host.c                            |   2 +-
+ drivers/mmc/host/cqhci-core.c                      |   9 +-
+ drivers/mmc/host/dw_mmc-exynos.c                   |   4 +-
+ drivers/mmc/host/dw_mmc-hi3798cv200.c              |   4 +-
+ drivers/mmc/host/dw_mmc-rockchip.c                 |   4 +-
+ drivers/mmc/host/mmci.c                            |   2 +-
+ drivers/mmc/host/mtk-sd.c                          |   2 +-
+ drivers/mmc/host/mxcmmc.c                          |   2 +-
+ drivers/mmc/host/renesas_sdhi_internal_dmac.c      |   1 +
+ drivers/mmc/host/sdhci-brcmstb.c                   |  69 +++++++-
+ drivers/mmc/host/sdhci-of-arasan.c                 |   5 +-
+ drivers/mmc/host/sdhci-of-dwcmshc.c                | 193 ++++++++++++++++-----
+ drivers/mmc/host/sdhci-of-esdhc.c                  |   1 +
+ drivers/mmc/host/sdhci-pci-gli.c                   |  34 ++++
+ drivers/mmc/host/sdhci-st.c                        |   5 +-
+ drivers/mmc/host/sdhci.c                           |  59 +++++--
+ drivers/mmc/host/sdhci.h                           |   3 +
+ include/linux/mmc/host.h                           |  26 +++
+ include/linux/mmc/mmc.h                            |   6 +
+ 28 files changed, 761 insertions(+), 211 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+ delete mode 100644 Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
+ create mode 100644 Documentation/devicetree/bindings/mmc/mmc-spi-slot.yaml
+ create mode 100644 Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
+Merging mfd/for-mfd-next (198057c06f54 mfd: twl: Remove platform data support)
+$ git merge -m Merge branch 'for-mfd-next' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git mfd/for-mfd-next
+Auto-merging Documentation/devicetree/bindings/trivial-devices.yaml
+Auto-merging MAINTAINERS
+Auto-merging arch/arm/mach-pxa/eseries.c
+Merge made by the 'ort' strategy.
+ Documentation/devicetree/bindings/mfd/da9063.txt   |  114 --
+ .../devicetree/bindings/mfd/dlg,da9063.yaml        |  132 ++
+ .../devicetree/bindings/mfd/mps,mp2629.yaml        |    1 +
+ Documentation/devicetree/bindings/mfd/mt6397.txt   |    1 +
+ .../devicetree/bindings/mfd/qcom,tcsr.txt          |   24 -
+ .../devicetree/bindings/mfd/qcom,tcsr.yaml         |   50 +
+ .../devicetree/bindings/mfd/st,stm32-timers.yaml   |   15 +
+ .../bindings/mfd/ti,j721e-system-controller.yaml   |   12 +
+ .../devicetree/bindings/trivial-devices.yaml       |    2 -
+ MAINTAINERS                                        |    4 +-
+ arch/arm/mach-pxa/eseries.c                        |    1 -
+ drivers/mfd/asic3.c                                |    9 +-
+ drivers/mfd/cros_ec_dev.c                          |    5 +
+ drivers/mfd/max77620.c                             |    2 +
+ drivers/mfd/max77714.c                             |    4 +-
+ drivers/mfd/mfd-core.c                             |   31 +-
+ drivers/mfd/mt6358-irq.c                           |   24 +
+ drivers/mfd/mt6397-core.c                          |   44 +
+ drivers/mfd/syscon.c                               |    3 +-
+ drivers/mfd/t7l66xb.c                              |    6 +-
+ drivers/mfd/twl-core.c                             |  323 +---
+ include/linux/mfd/max77714.h                       |    2 +-
+ include/linux/mfd/mt6357/core.h                    |  119 ++
+ include/linux/mfd/mt6357/registers.h               | 1574 ++++++++++++++++++++
+ include/linux/mfd/mt6397/core.h                    |    1 +
+ include/linux/mfd/t7l66xb.h                        |    1 -
+ include/linux/mfd/tc6387xb.h                       |    1 -
+ include/linux/mfd/twl.h                            |   55 -
+ include/linux/platform_data/cros_ec_commands.h     |    2 +
+ include/linux/platform_data/cros_ec_proto.h        |    1 +
+ 30 files changed, 2022 insertions(+), 541 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/mfd/da9063.txt
+ create mode 100644 Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
+ delete mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
+ create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+ create mode 100644 include/linux/mfd/mt6357/core.h
+ create mode 100644 include/linux/mfd/mt6357/registers.h
+Merging backlight/for-backlight-next (023a8830a628 backlight: backlight: Slighly simplify devm_of_find_backlight())
+$ git merge -m Merge branch 'for-backlight-next' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git backlight/for-backlight-next
+Already up to date.
+Merging battery/for-next (f94ba7039fb4 Merge tag 'at91-reset-sama7g5-signed' into psy-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git battery/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/arm/atmel-sysregs.txt      |  15 --
+ .../devicetree/bindings/power/supply/bq24190.yaml  |   2 +-
+ .../bindings/power/supply/qcom,pm8941-charger.yaml |   9 +-
+ .../power/supply/summit,smb347-charger.yaml        |   2 +-
+ .../bindings/reset/atmel,at91sam9260-reset.yaml    |  68 ++++++++
+ drivers/power/reset/Kconfig                        |   6 +
+ drivers/power/reset/Makefile                       |   1 +
+ drivers/power/reset/at91-reset.c                   | 184 +++++++++++++++++++--
+ drivers/power/reset/pwr-mlxbf.c                    |  97 +++++++++++
+ drivers/power/supply/ab8500_chargalg.c             |  46 +++++-
+ drivers/power/supply/bq24257_charger.c             |   2 +-
+ drivers/power/supply/cros_peripheral_charger.c     |   2 +-
+ drivers/power/supply/goldfish_battery.c            |   4 +-
+ drivers/power/supply/lp8788-charger.c              |   2 +-
+ drivers/power/supply/max77976_charger.c            |   4 +-
+ include/dt-bindings/reset/sama7g5-reset.h          |  10 ++
+ 16 files changed, 412 insertions(+), 42 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
+ create mode 100644 drivers/power/reset/pwr-mlxbf.c
+ create mode 100644 include/dt-bindings/reset/sama7g5-reset.h
+$ git reset --hard HEAD^
+HEAD is now at 8e64d81f65f2 Merge branch 'for-mfd-next' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
+Merging next-20220617 version of battery
+$ git merge -m next-20220617/battery e08f8a118514c94c8cf78aa1dcf5f26f7b6918ba
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/power/supply/bq24190.yaml  |  2 +-
+ .../bindings/power/supply/qcom,pm8941-charger.yaml |  9 ++++-
+ .../power/supply/summit,smb347-charger.yaml        |  2 +-
+ drivers/power/supply/ab8500_chargalg.c             | 46 +++++++++++++++++++++-
+ drivers/power/supply/bq24257_charger.c             |  2 +-
+ drivers/power/supply/cros_peripheral_charger.c     |  2 +-
+ drivers/power/supply/goldfish_battery.c            |  4 +-
+ drivers/power/supply/lp8788-charger.c              |  2 +-
+ drivers/power/supply/max77976_charger.c            |  4 +-
+ 9 files changed, 61 insertions(+), 12 deletions(-)
+Merging regulator/for-next (901a2827fdf9 Merge remote-tracking branch 'regulator/for-5.20' into regulator-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git regulator/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/regulator/mps,mp5416.yaml  |   1 +
+ .../bindings/regulator/pwm-regulator.txt           |  92 ---------------
+ .../bindings/regulator/pwm-regulator.yaml          | 126 +++++++++++++++++++++
+ drivers/regulator/mp5416.c                         |  30 ++++-
+ drivers/regulator/qcom_smd-regulator.c             |   1 +
+ drivers/regulator/rpi-panel-attiny-regulator.c     |   6 +-
+ drivers/regulator/rt5190a-regulator.c              |   3 +
+ 7 files changed, 156 insertions(+), 103 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/regulator/pwm-regulator.txt
+ create mode 100644 Documentation/devicetree/bindings/regulator/pwm-regulator.yaml
+Merging security/next-testing (88c9c5679a06 Merge tag 'v5.18' into next-testing)
+$ git merge -m Merge branch 'next-testing' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git security/next-testing
+Merge made by the 'ort' strategy.
+Merging apparmor/apparmor-next (c2489617b3b9 apparmor: Fix undefined reference to `zlib_deflate_workspacesize')
+$ git merge -m Merge branch 'apparmor-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor apparmor/apparmor-next
+Auto-merging MAINTAINERS
+Auto-merging security/apparmor/lsm.c
+Auto-merging security/apparmor/policy_unpack_test.c
+CONFLICT (content): Merge conflict in security/apparmor/policy_unpack_test.c
+Resolved 'security/apparmor/policy_unpack_test.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master e768547fbe99] Merge branch 'apparmor-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor
+$ git diff -M --stat --summary HEAD^..
+ MAINTAINERS                            |  7 ++-
+ security/apparmor/Kconfig              | 86 ++++++++++++++++++++---------
+ security/apparmor/apparmorfs.c         | 99 +++++++++++++++++++---------------
+ security/apparmor/audit.c              |  2 +-
+ security/apparmor/include/apparmor.h   |  1 +
+ security/apparmor/include/apparmorfs.h | 14 +++++
+ security/apparmor/include/lib.h        |  5 ++
+ security/apparmor/label.c              | 17 +++---
+ security/apparmor/lib.c                |  2 +-
+ security/apparmor/lsm.c                | 23 ++++----
+ security/apparmor/mount.c              | 11 ++--
+ security/apparmor/policy.c             | 35 ++++++------
+ security/apparmor/policy_unpack.c      | 37 ++++++++-----
+ security/apparmor/policy_unpack_test.c | 28 +++++-----
+ security/apparmor/procattr.c           |  2 +-
+ 15 files changed, 231 insertions(+), 138 deletions(-)
+Merging integrity/next-integrity (51dd64bb99e4 Revert "evm: Fix memleak in init_desc")
+$ git merge -m Merge branch 'next-integrity' of git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity integrity/next-integrity
+Merge made by the 'ort' strategy.
+ security/integrity/evm/evm_crypto.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+Merging keys/keys-next (2d743660786e Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs)
+$ git merge -m Merge branch 'keys-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git keys/keys-next
+Already up to date.
+Merging safesetid/safesetid-next (1b8b71922919 LSM: SafeSetID: Mark safesetid_initialized as __initdata)
+$ git merge -m Merge branch 'safesetid-next' of https://github.com/micah-morton/linux.git safesetid/safesetid-next
+Already up to date.
+Merging selinux/next (ef54ccb61616 selinux: selinux_add_opt() callers free memory)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinux.git selinux/next
+Auto-merging Documentation/admin-guide/kernel-parameters.txt
+Auto-merging security/selinux/hooks.c
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/kernel-parameters.txt |  4 ++--
+ mm/secretmem.c                                  |  9 +++++++++
+ security/selinux/hooks.c                        | 17 +++++++----------
+ security/selinux/include/audit.h                |  2 +-
+ security/selinux/include/avc.h                  |  2 +-
+ security/selinux/ss/policydb.h                  |  2 ++
+ security/selinux/ss/services.c                  |  9 ++++++++-
+ 7 files changed, 30 insertions(+), 15 deletions(-)
+Merging smack/next (b50503990d88 smack: Remove the redundant lsm_inode_alloc)
+$ git merge -m Merge branch 'next' of git://github.com/cschaufler/smack-next smack/next
+Merge made by the 'ort' strategy.
+ security/smack/smack_access.c | 7 ++-----
+ security/smack/smack_lsm.c    | 7 -------
+ 2 files changed, 2 insertions(+), 12 deletions(-)
+Merging tomoyo/master (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'master' of https://scm.osdn.net/gitroot/tomoyo/tomoyo-test1.git tomoyo/master
+Already up to date.
+Merging tpmdd/next (27b5b22d252c certs: fix and refactor CONFIG_SYSTEM_BLACKLIST_HASH_LIST build)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git tpmdd/next
+Already up to date.
+Merging watchdog/master (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'master' of git://www.linux-watchdog.org/linux-watchdog-next.git watchdog/master
+Already up to date.
+Merging iommu/next (b0dacee202ef Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git iommu/next
+Already up to date.
+Merging audit/next (546093206ba1 audit: make is_audit_feature_set() static)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit.git audit/next
+Merge made by the 'ort' strategy.
+ include/linux/audit.h | 2 --
+ kernel/audit.c        | 4 ++--
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+Merging devicetree/for-next (cfda05c1ddb8 dt-bindings: vexpress-sysreg: Allow for no child nodes)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git devicetree/for-next
+Auto-merging Documentation/devicetree/bindings/vendor-prefixes.yaml
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/arm/vexpress-sysreg.yaml   |  10 +-
+ .../devicetree/bindings/clock/efm32-clock.txt      |  11 --
+ .../devicetree/bindings/display/arm,pl11x.yaml     |  15 +--
+ .../devicetree/bindings/display/bridge/sii902x.txt |  78 ------------
+ .../bindings/display/bridge/sil,sii9022.yaml       | 131 +++++++++++++++++++++
+ .../bindings/display/panel/arm,rtsm-display.yaml   |  27 +++++
+ .../bindings/{i2c => hwmon}/ibm,p8-occ-hwmon.txt   |   0
+ .../devicetree/bindings/i2c/i2c-efm32.txt          |  33 ------
+ .../interrupt-controller/rda,8810pl-intc.txt       |  61 ----------
+ .../interrupt-controller/rda,8810pl-intc.yaml      |  43 +++++++
+ .../devicetree/bindings/perf/arm,ccn.yaml          |  40 +++++++
+ Documentation/devicetree/bindings/perf/arm-ccn.txt |  23 ----
+ .../devicetree/bindings/serial/efm32-uart.txt      |  20 ----
+ .../devicetree/bindings/serio/ps2-gpio.txt         |  23 ----
+ .../devicetree/bindings/serio/ps2-gpio.yaml        |  64 ++++++++++
+ .../devicetree/bindings/spi/efm32-spi.txt          |  39 ------
+ .../devicetree/bindings/sram/qcom,imem.yaml        |  75 ++++++++++++
+ .../devicetree/bindings/sram/qcom,ocmem.yaml       |  10 +-
+ .../devicetree/bindings/vendor-prefixes.yaml       |  16 ++-
+ MAINTAINERS                                        |   2 +-
+ drivers/of/kexec.c                                 |  17 +++
+ include/dt-bindings/clock/efm32-cmu.h              |  43 -------
+ include/linux/of.h                                 |   5 +-
+ 23 files changed, 429 insertions(+), 357 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/clock/efm32-clock.txt
+ delete mode 100644 Documentation/devicetree/bindings/display/bridge/sii902x.txt
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
+ create mode 100644 Documentation/devicetree/bindings/display/panel/arm,rtsm-display.yaml
+ rename Documentation/devicetree/bindings/{i2c => hwmon}/ibm,p8-occ-hwmon.txt (100%)
+ delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-efm32.txt
+ delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml
+ create mode 100644 Documentation/devicetree/bindings/perf/arm,ccn.yaml
+ delete mode 100644 Documentation/devicetree/bindings/perf/arm-ccn.txt
+ delete mode 100644 Documentation/devicetree/bindings/serial/efm32-uart.txt
+ delete mode 100644 Documentation/devicetree/bindings/serio/ps2-gpio.txt
+ create mode 100644 Documentation/devicetree/bindings/serio/ps2-gpio.yaml
+ delete mode 100644 Documentation/devicetree/bindings/spi/efm32-spi.txt
+ create mode 100644 Documentation/devicetree/bindings/sram/qcom,imem.yaml
+ delete mode 100644 include/dt-bindings/clock/efm32-cmu.h
+Merging dt-krzk/for-next (8ebbcd3cef3a Merge branch 'for-v5.20/dt-bindings-aspeed' into next/dt-bindings)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git dt-krzk/for-next
+Auto-merging Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+Auto-merging Documentation/devicetree/bindings/vendor-prefixes.yaml
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/arm/aspeed/aspeed.yaml     |  87 +++++++++++++++++
+ Documentation/devicetree/bindings/arm/qcom.yaml    | 108 +++++++++++++++++++--
+ .../bindings/leds/backlight/qcom-wled.yaml         |   9 +-
+ .../devicetree/bindings/nvmem/qcom,qfprom.yaml     |   2 +
+ .../bindings/soc/qcom/qcom,aoss-qmp.yaml           |   1 +
+ .../bindings/soc/qcom/qcom,rpmh-rsc.yaml           |  33 +++----
+ .../devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml |   3 +
+ .../bindings/spi/qcom,spi-geni-qcom.yaml           |   5 +-
+ .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
+ MAINTAINERS                                        |   1 +
+ 10 files changed, 221 insertions(+), 30 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+Merging mailbox/mailbox-for-next (79f9fbe30352 mailbox: qcom-ipcc: Fix -Wunused-function with CONFIG_PM_SLEEP=n)
+$ git merge -m Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration.git mailbox/mailbox-for-next
+Already up to date.
+Merging spi/for-next (0cb24a68abbe Merge remote-tracking branch 'spi/for-5.20' into spi-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git spi/for-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/sound/renesas,rz-ssi.yaml  |   3 +-
+ .../bindings/spi/mediatek,spi-mt65xx.yaml          |   1 +
+ .../spi/nvidia,tegra210-quad-peripheral-props.yaml |  33 ++
+ .../bindings/spi/nvidia,tegra210-quad.yaml         |  22 +-
+ .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml   |  18 +-
+ .../bindings/spi/spi-peripheral-props.yaml         |   6 +
+ MAINTAINERS                                        |   1 +
+ drivers/spi/Kconfig                                |   9 +
+ drivers/spi/Makefile                               |   1 +
+ drivers/spi/atmel-quadspi.c                        | 104 +++-
+ drivers/spi/spi-altera-dfl.c                       |  14 +-
+ drivers/spi/spi-cadence-quadspi.c                  |  19 +-
+ drivers/spi/spi-intel.c                            |   4 +-
+ drivers/spi/spi-microchip-core.c                   | 633 +++++++++++++++++++++
+ drivers/spi/spi-s3c64xx.c                          |  56 +-
+ drivers/spi/spi-sifive.c                           |  39 ++
+ drivers/spi/spi-stm32-qspi.c                       |  18 +-
+ drivers/spi/spi-tegra210-quad.c                    |  33 +-
+ drivers/spi/spi-ti-qspi.c                          |  75 +--
+ drivers/spi/spi-topcliff-pch.c                     |  30 +-
+ drivers/spi/spi-zynqmp-gqspi.c                     |  25 +-
+ drivers/spi/spi.c                                  | 147 +++--
+ include/linux/spi/spi.h                            |  67 ++-
+ tools/spi/spidev_test.c                            |  11 +
+ 24 files changed, 1128 insertions(+), 241 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml
+ create mode 100644 drivers/spi/spi-microchip-core.c
+Merging tip/master (84bf7291902a Merge branch into tip/master: 'x86/mm')
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tip/master
+Auto-merging kernel/sched/core.c
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/pm/cpuidle.rst   |  15 ++-
+ Documentation/core-api/protection-keys.rst |  44 +++----
+ arch/x86/events/amd/uncore.c               | 146 ++++++++++++++++----
+ arch/x86/events/perf_event.h               |   3 +-
+ arch/x86/include/asm/cpufeatures.h         |   2 +-
+ arch/x86/include/asm/fpu/api.h             |   2 +
+ arch/x86/include/asm/mwait.h               |   1 +
+ arch/x86/include/asm/perf_event.h          |  16 +++
+ arch/x86/include/asm/special_insns.h       |   9 ++
+ arch/x86/kernel/fpu/core.c                 |  14 ++
+ arch/x86/kernel/process.c                  |  44 +++++--
+ arch/x86/mm/pkeys.c                        |  15 ++-
+ arch/x86/mm/tlb.c                          |  18 ++-
+ drivers/idle/intel_idle.c                  |  25 +++-
+ kernel/irq/pm.c                            |   2 -
+ kernel/sched/core.c                        |  30 +++--
+ kernel/sched/deadline.c                    |   6 +-
+ kernel/sched/fair.c                        | 205 ++++++++++++++---------------
+ kernel/sched/sched.h                       |   1 -
+ kernel/sched/topology.c                    |  23 ++--
+ 20 files changed, 414 insertions(+), 207 deletions(-)
+Merging clockevents/timers/drivers/next (ff714ee7191b clocksource/drivers/timer-ti-dm: Add compatible for am6 SoCs)
+$ git merge -m Merge branch 'timers/drivers/next' of git://git.linaro.org/people/daniel.lezcano/linux.git clockevents/timers/drivers/next
+Auto-merging arch/arm/mach-omap2/Kconfig
+Auto-merging drivers/clocksource/Kconfig
+Auto-merging drivers/clocksource/Makefile
+Auto-merging drivers/clocksource/timer-ti-dm.c
+Merge made by the 'ort' strategy.
+ arch/arm/mach-omap2/Kconfig       |   2 +
+ drivers/clocksource/Kconfig       |   8 ++-
+ drivers/clocksource/Makefile      |   2 +-
+ drivers/clocksource/timer-ti-dm.c | 123 ++++++++++++++++++++++++++++++++
+ include/clocksource/timer-ti-dm.h | 144 --------------------------------------
+ 5 files changed, 133 insertions(+), 146 deletions(-)
+Merging edac/edac-for-next (92705c9f9956 Merge edac-misc into for-next)
+$ git merge -m Merge branch 'edac-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac/edac-for-next
+Auto-merging drivers/edac/synopsys_edac.c
+Merge made by the 'ort' strategy.
+ drivers/edac/synopsys_edac.c | 44 +++++++++++++++++++++++++-------------------
+ 1 file changed, 25 insertions(+), 19 deletions(-)
+Merging irqchip/irq/irqchip-next (492449ae4f0a Merge branch irq/gic-v3-nmi-fixes-5.19 into irq/irqchip-next)
+$ git merge -m Merge branch 'irq/irqchip-next' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irqchip/irq/irqchip-next
+Already up to date.
+Merging ftrace/for-next (01dca6d03bb3 Merge branch 'trace/for-next-rtla' into trace/for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git ftrace/for-next
+Merge made by the 'ort' strategy.
+Merging rcu/rcu/next (19743f8bb51c rcu/nocb: Choose the right rcuog/rcuop kthreads to output)
+$ git merge -m Merge branch 'rcu/next' of git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git rcu/rcu/next
+Auto-merging Documentation/admin-guide/kernel-parameters.txt
+Auto-merging MAINTAINERS
+Auto-merging arch/Kconfig
+Auto-merging arch/arm/kernel/entry-common.S
+Auto-merging arch/arm64/Kconfig
+Auto-merging drivers/acpi/processor_idle.c
+Auto-merging kernel/sched/core.c
+Auto-merging kernel/sched/sched.h
+Merge made by the 'ort' strategy.
+ .../RCU/Design/Requirements/Requirements.rst       |  10 +-
+ Documentation/RCU/stallwarn.rst                    |   6 +-
+ Documentation/admin-guide/kernel-parameters.txt    |  34 ++
+ .../time/context-tracking/arch-support.txt         |   6 +-
+ .../litmus-tests/locking/DCL-broken.litmus         |  55 ++
+ .../litmus-tests/locking/DCL-fixed.litmus          |  56 ++
+ .../litmus-tests/locking/RM-broken.litmus          |  42 ++
+ Documentation/litmus-tests/locking/RM-fixed.litmus |  42 ++
+ MAINTAINERS                                        |   1 +
+ arch/Kconfig                                       |   8 +-
+ arch/arm/Kconfig                                   |   2 +-
+ arch/arm/kernel/entry-common.S                     |   4 +-
+ arch/arm/kernel/entry-header.S                     |  12 +-
+ arch/arm/mach-imx/cpuidle-imx6q.c                  |   5 +-
+ arch/arm64/Kconfig                                 |   2 +-
+ arch/arm64/kernel/entry-common.c                   |  14 +-
+ arch/csky/Kconfig                                  |   2 +-
+ arch/csky/kernel/entry.S                           |   8 +-
+ arch/mips/Kconfig                                  |   2 +-
+ arch/powerpc/Kconfig                               |   2 +-
+ arch/powerpc/include/asm/context_tracking.h        |   2 +-
+ arch/riscv/Kconfig                                 |   2 +-
+ arch/riscv/kernel/entry.S                          |  12 +-
+ arch/sparc/Kconfig                                 |   2 +-
+ arch/sparc/kernel/rtrap_64.S                       |   2 +-
+ arch/x86/Kconfig                                   |   4 +-
+ arch/x86/mm/fault.c                                |   2 +-
+ drivers/acpi/processor_idle.c                      |   5 +-
+ drivers/cpuidle/cpuidle-psci.c                     |   8 +-
+ drivers/cpuidle/cpuidle-riscv-sbi.c                |   8 +-
+ drivers/cpuidle/cpuidle.c                          |   9 +-
+ include/linux/context_tracking.h                   |  95 +--
+ include/linux/context_tracking_irq.h               |  21 +
+ include/linux/context_tracking_state.h             | 109 +++-
+ include/linux/entry-common.h                       |  10 +-
+ include/linux/hardirq.h                            |  12 +-
+ include/linux/rcupdate.h                           |  45 +-
+ include/linux/rcupdate_trace.h                     |   2 +-
+ include/linux/rcutiny.h                            |  27 +-
+ include/linux/rcutree.h                            |  11 +-
+ include/linux/sched.h                              |   4 +-
+ include/linux/tracepoint.h                         |   4 +-
+ init/Kconfig                                       |   4 +-
+ init/init_task.c                                   |   1 +
+ kernel/cfi.c                                       |   4 +-
+ kernel/context_tracking.c                          | 617 +++++++++++++++++--
+ kernel/cpu_pm.c                                    |   8 +-
+ kernel/entry/common.c                              |  16 +-
+ kernel/extable.c                                   |   4 +-
+ kernel/fork.c                                      |   1 +
+ kernel/locking/lockdep.c                           |   2 +-
+ kernel/rcu/Kconfig                                 |  31 +
+ kernel/rcu/Kconfig.debug                           |   2 +-
+ kernel/rcu/rcu.h                                   |  19 +-
+ kernel/rcu/rcuscale.c                              |   1 +
+ kernel/rcu/rcutorture.c                            | 247 +++++---
+ kernel/rcu/refscale.c                              |  18 +-
+ kernel/rcu/srcutree.c                              |  20 +-
+ kernel/rcu/tasks.h                                 | 541 ++++++++++-------
+ kernel/rcu/tiny.c                                  |  25 +-
+ kernel/rcu/tree.c                                  | 650 ++++++---------------
+ kernel/rcu/tree.h                                  |  21 +-
+ kernel/rcu/tree_exp.h                              | 115 +++-
+ kernel/rcu/tree_nocb.h                             | 272 ++++++---
+ kernel/rcu/tree_plugin.h                           |  81 +--
+ kernel/rcu/tree_stall.h                            |  55 +-
+ kernel/rcu/update.c                                |  15 +-
+ kernel/sched/core.c                                |  34 +-
+ kernel/sched/idle.c                                |  10 +-
+ kernel/sched/sched.h                               |   1 +
+ kernel/smp.c                                       |   4 +-
+ kernel/softirq.c                                   |   4 +-
+ kernel/time/Kconfig                                |  37 +-
+ kernel/time/tick-sched.c                           |   2 +-
+ kernel/trace/trace.c                               |   8 +-
+ tools/Makefile                                     |   3 +
+ tools/include/nolibc/Makefile                      |  37 +-
+ tools/include/nolibc/stdio.h                       |   4 +-
+ tools/include/nolibc/stdlib.h                      |   7 +-
+ tools/memory-model/Documentation/locking.txt       | 320 ++++++++++
+ tools/memory-model/linux-kernel.bell               |  16 +-
+ tools/memory-model/litmus-tests/.gitignore         |   2 +-
+ tools/memory-model/scripts/README                  |  16 +-
+ tools/memory-model/scripts/checkalllitmus.sh       |  29 +-
+ tools/memory-model/scripts/checkghlitmus.sh        |  11 +-
+ tools/memory-model/scripts/checklitmus.sh          |  25 +-
+ tools/memory-model/scripts/checklitmushist.sh      |   2 +-
+ tools/memory-model/scripts/checktheselitmus.sh     |  43 ++
+ tools/memory-model/scripts/cmplitmushist.sh        |  49 +-
+ tools/memory-model/scripts/hwfnseg.sh              |  20 +
+ tools/memory-model/scripts/initlitmushist.sh       |   2 +-
+ tools/memory-model/scripts/judgelitmus.sh          | 120 +++-
+ tools/memory-model/scripts/newlitmushist.sh        |   4 +-
+ tools/memory-model/scripts/parseargs.sh            |  21 +-
+ tools/memory-model/scripts/runlitmus.sh            |  80 +++
+ tools/memory-model/scripts/runlitmushist.sh        |  29 +-
+ tools/memory-model/scripts/simpletest.sh           |  35 ++
+ .../selftests/rcutorture/bin/kvm-check-branches.sh |  11 +-
+ .../testing/selftests/rcutorture/bin/kvm-remote.sh |   1 +
+ tools/testing/selftests/rcutorture/bin/kvm.sh      |   6 +-
+ 100 files changed, 3085 insertions(+), 1387 deletions(-)
+ create mode 100644 Documentation/litmus-tests/locking/DCL-broken.litmus
+ create mode 100644 Documentation/litmus-tests/locking/DCL-fixed.litmus
+ create mode 100644 Documentation/litmus-tests/locking/RM-broken.litmus
+ create mode 100644 Documentation/litmus-tests/locking/RM-fixed.litmus
+ create mode 100644 include/linux/context_tracking_irq.h
+ create mode 100644 tools/memory-model/Documentation/locking.txt
+ create mode 100755 tools/memory-model/scripts/checktheselitmus.sh
+ create mode 100755 tools/memory-model/scripts/hwfnseg.sh
+ create mode 100755 tools/memory-model/scripts/runlitmus.sh
+ create mode 100755 tools/memory-model/scripts/simpletest.sh
+Merging kvm/next (e20918f6d112 x86: kvm: remove NULL check before kfree)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git kvm/next
+Auto-merging arch/x86/events/perf_event.h
+Auto-merging arch/x86/include/asm/msr-index.h
+Auto-merging arch/x86/include/asm/perf_event.h
+Auto-merging arch/x86/kvm/vmx/vmx.c
+Auto-merging arch/x86/kvm/vmx/vmx.c
+Auto-merging arch/x86/kvm/vmx/vmx.h
+Auto-merging arch/x86/kvm/x86.c
+Auto-merging arch/x86/kvm/x86.c
+Auto-merging tools/testing/selftests/kvm/s390x/memop.c
+CONFLICT (content): Merge conflict in tools/testing/selftests/kvm/s390x/memop.c
+Auto-merging tools/testing/selftests/kvm/s390x/resets.c
+CONFLICT (content): Merge conflict in tools/testing/selftests/kvm/s390x/resets.c
+Auto-merging tools/testing/selftests/kvm/s390x/sync_regs_test.c
+CONFLICT (content): Merge conflict in tools/testing/selftests/kvm/s390x/sync_regs_test.c
+Auto-merging tools/testing/selftests/kvm/s390x/tprot.c
+CONFLICT (content): Merge conflict in tools/testing/selftests/kvm/s390x/tprot.c
+Auto-merging virt/kvm/kvm_main.c
+Resolved 'tools/testing/selftests/kvm/s390x/memop.c' using previous resolution.
+Resolved 'tools/testing/selftests/kvm/s390x/resets.c' using previous resolution.
+Resolved 'tools/testing/selftests/kvm/s390x/sync_regs_test.c' using previous resolution.
+Resolved 'tools/testing/selftests/kvm/s390x/tprot.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master c836e3aaf9cf] Merge branch 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git
+$ git diff -M --stat --summary HEAD^..
+ Documentation/virt/kvm/api.rst                     |  244 ++++-
+ Documentation/virt/kvm/s390/index.rst              |    1 +
+ Documentation/virt/kvm/s390/s390-pv-dump.rst       |   64 ++
+ arch/s390/boot/uv.c                                |    4 +
+ arch/s390/include/asm/kvm_host.h                   |    1 +
+ arch/s390/include/asm/uv.h                         |   45 +-
+ arch/s390/kernel/uv.c                              |   53 +
+ arch/s390/kvm/kvm-s390.c                           |  271 ++++-
+ arch/s390/kvm/kvm-s390.h                           |    5 +
+ arch/s390/kvm/pv.c                                 |  198 ++++
+ arch/x86/events/core.c                             |   28 +-
+ arch/x86/events/intel/core.c                       |  160 ++-
+ arch/x86/events/perf_event.h                       |    6 +-
+ arch/x86/include/asm/kvm-x86-ops.h                 |    1 +
+ arch/x86/include/asm/kvm-x86-pmu-ops.h             |    2 +-
+ arch/x86/include/asm/kvm_host.h                    |   52 +-
+ arch/x86/include/asm/msr-index.h                   |    7 +
+ arch/x86/include/asm/perf_event.h                  |   11 +-
+ arch/x86/include/asm/vmx.h                         |   18 +
+ arch/x86/include/asm/vmxfeatures.h                 |    6 +-
+ arch/x86/include/uapi/asm/kvm.h                    |    9 +-
+ arch/x86/include/uapi/asm/vmx.h                    |    4 +-
+ arch/x86/kernel/cpu/feat_ctl.c                     |    9 +-
+ arch/x86/kernel/kvm.c                              |    3 +-
+ arch/x86/kvm/cpuid.c                               |   35 +-
+ arch/x86/kvm/cpuid.h                               |    5 +
+ arch/x86/kvm/debugfs.c                             |    4 +-
+ arch/x86/kvm/emulate.c                             |   26 +-
+ arch/x86/kvm/i8254.c                               |   10 +-
+ arch/x86/kvm/i8254.h                               |    1 -
+ arch/x86/kvm/kvm_emulate.h                         |   28 +-
+ arch/x86/kvm/lapic.c                               |   64 +-
+ arch/x86/kvm/lapic.h                               |    3 +-
+ arch/x86/kvm/mmu.h                                 |   10 -
+ arch/x86/kvm/mmu/mmu.c                             |  112 +-
+ arch/x86/kvm/mmu/mmu_internal.h                    |   14 +
+ arch/x86/kvm/mmu/paging.h                          |   14 -
+ arch/x86/kvm/mmu/paging_tmpl.h                     |   75 +-
+ arch/x86/kvm/mmu/spte.c                            |    4 +-
+ arch/x86/kvm/mmu/spte.h                            |   28 +-
+ arch/x86/kvm/mmu/tdp_iter.c                        |    6 +-
+ arch/x86/kvm/mmu/tdp_mmu.c                         |   22 +-
+ arch/x86/kvm/pmu.c                                 |  224 ++--
+ arch/x86/kvm/pmu.h                                 |   49 +-
+ arch/x86/kvm/svm/nested.c                          |   63 +-
+ arch/x86/kvm/svm/pmu.c                             |   75 +-
+ arch/x86/kvm/svm/sev.c                             |   17 +-
+ arch/x86/kvm/svm/svm.c                             |  180 +++-
+ arch/x86/kvm/svm/svm.h                             |   12 +-
+ arch/x86/kvm/trace.h                               |   31 +-
+ arch/x86/kvm/vmx/capabilities.h                    |   57 +-
+ arch/x86/kvm/vmx/evmcs.c                           |    2 +
+ arch/x86/kvm/vmx/evmcs.h                           |    1 +
+ arch/x86/kvm/vmx/nested.c                          |   67 +-
+ arch/x86/kvm/vmx/pmu_intel.c                       |  210 ++--
+ arch/x86/kvm/vmx/posted_intr.c                     |   17 +-
+ arch/x86/kvm/vmx/posted_intr.h                     |    2 +
+ arch/x86/kvm/vmx/vmcs.h                            |    1 +
+ arch/x86/kvm/vmx/vmx.c                             |  321 +++++-
+ arch/x86/kvm/vmx/vmx.h                             |   83 +-
+ arch/x86/kvm/x86.c                                 |  248 +++--
+ arch/x86/kvm/x86.h                                 |   33 +-
+ include/linux/kvm_host.h                           |   12 +-
+ include/uapi/linux/kvm.h                           |   67 ++
+ tools/testing/selftests/kvm/.gitignore             |    5 +-
+ tools/testing/selftests/kvm/Makefile               |    3 +
+ tools/testing/selftests/kvm/aarch64/arch_timer.c   |   79 +-
+ .../selftests/kvm/aarch64/debug-exceptions.c       |   22 +-
+ tools/testing/selftests/kvm/aarch64/get-reg-list.c |   30 +-
+ tools/testing/selftests/kvm/aarch64/hypercalls.c   |   90 +-
+ tools/testing/selftests/kvm/aarch64/psci_test.c    |   69 +-
+ .../selftests/kvm/aarch64/vcpu_width_config.c      |   71 +-
+ tools/testing/selftests/kvm/aarch64/vgic_init.c    |  443 ++++----
+ tools/testing/selftests/kvm/aarch64/vgic_irq.c     |   40 +-
+ .../selftests/kvm/access_tracking_perf_test.c      |   92 +-
+ tools/testing/selftests/kvm/demand_paging_test.c   |   49 +-
+ tools/testing/selftests/kvm/dirty_log_perf_test.c  |   51 +-
+ tools/testing/selftests/kvm/dirty_log_test.c       |   95 +-
+ .../testing/selftests/kvm/hardware_disable_test.c  |   29 +-
+ .../selftests/kvm/include/aarch64/processor.h      |   28 +-
+ tools/testing/selftests/kvm/include/aarch64/vgic.h |    6 +-
+ .../testing/selftests/kvm/include/kvm_util_base.h  |  750 +++++++++----
+ .../testing/selftests/kvm/include/perf_test_util.h |    7 +-
+ .../selftests/kvm/include/riscv/processor.h        |   20 -
+ tools/testing/selftests/kvm/include/test_util.h    |    7 +
+ tools/testing/selftests/kvm/include/ucall_common.h |    2 +-
+ tools/testing/selftests/kvm/include/x86_64/evmcs.h |    2 +-
+ .../selftests/kvm/include/x86_64/processor.h       |  126 ++-
+ .../selftests/kvm/include/x86_64/svm_util.h        |   12 +
+ .../testing/selftests/kvm/kvm_binary_stats_test.c  |   31 +-
+ tools/testing/selftests/kvm/kvm_create_max_vcpus.c |   10 +-
+ tools/testing/selftests/kvm/kvm_page_table_test.c  |   66 +-
+ .../testing/selftests/kvm/lib/aarch64/processor.c  |   81 +-
+ tools/testing/selftests/kvm/lib/aarch64/ucall.c    |   13 +-
+ tools/testing/selftests/kvm/lib/aarch64/vgic.c     |   54 +-
+ tools/testing/selftests/kvm/lib/elf.c              |    1 -
+ tools/testing/selftests/kvm/lib/guest_modes.c      |    6 +-
+ tools/testing/selftests/kvm/lib/kvm_util.c         | 1104 ++++----------------
+ .../testing/selftests/kvm/lib/kvm_util_internal.h  |  128 ---
+ tools/testing/selftests/kvm/lib/perf_test_util.c   |   92 +-
+ tools/testing/selftests/kvm/lib/riscv/processor.c  |  111 +-
+ tools/testing/selftests/kvm/lib/riscv/ucall.c      |   16 +-
+ .../selftests/kvm/lib/s390x/diag318_test_handler.c |   11 +-
+ tools/testing/selftests/kvm/lib/s390x/processor.c  |   44 +-
+ tools/testing/selftests/kvm/lib/s390x/ucall.c      |   10 +-
+ .../selftests/kvm/lib/x86_64/perf_test_util.c      |    9 +-
+ tools/testing/selftests/kvm/lib/x86_64/processor.c |  533 ++++------
+ tools/testing/selftests/kvm/lib/x86_64/svm.c       |    6 +-
+ tools/testing/selftests/kvm/lib/x86_64/ucall.c     |   12 +-
+ tools/testing/selftests/kvm/lib/x86_64/vmx.c       |   16 +-
+ .../testing/selftests/kvm/max_guest_memory_test.c  |   53 +-
+ .../kvm/memslot_modification_stress_test.c         |   13 +-
+ tools/testing/selftests/kvm/memslot_perf_test.c    |   28 +-
+ tools/testing/selftests/kvm/rseq_test.c            |   22 +-
+ tools/testing/selftests/kvm/s390x/memop.c          |   95 +-
+ tools/testing/selftests/kvm/s390x/resets.c         |  140 +--
+ tools/testing/selftests/kvm/s390x/sync_regs_test.c |   64 +-
+ tools/testing/selftests/kvm/s390x/tprot.c          |   31 +-
+ .../testing/selftests/kvm/set_memory_region_test.c |   43 +-
+ tools/testing/selftests/kvm/steal_time.c           |  120 ++-
+ .../selftests/kvm/system_counter_offset_test.c     |   35 +-
+ tools/testing/selftests/kvm/x86_64/amx_test.c      |   56 +-
+ tools/testing/selftests/kvm/x86_64/cpuid_test.c    |   29 +-
+ .../selftests/kvm/x86_64/cr4_cpuid_sync_test.c     |   22 +-
+ tools/testing/selftests/kvm/x86_64/debug_regs.c    |   77 +-
+ .../selftests/kvm/x86_64/emulator_error_test.c     |   74 +-
+ tools/testing/selftests/kvm/x86_64/evmcs_test.c    |   62 +-
+ .../selftests/kvm/x86_64/fix_hypercall_test.c      |   45 +-
+ .../selftests/kvm/x86_64/get_msr_index_features.c  |  117 +--
+ tools/testing/selftests/kvm/x86_64/hyperv_clock.c  |   25 +-
+ tools/testing/selftests/kvm/x86_64/hyperv_cpuid.c  |   34 +-
+ .../testing/selftests/kvm/x86_64/hyperv_features.c |   61 +-
+ .../testing/selftests/kvm/x86_64/hyperv_svm_test.c |   25 +-
+ .../testing/selftests/kvm/x86_64/kvm_clock_test.c  |   29 +-
+ tools/testing/selftests/kvm/x86_64/kvm_pv_test.c   |   33 +-
+ .../selftests/kvm/x86_64/max_vcpuid_cap_test.c     |   44 +
+ .../selftests/kvm/x86_64/mmio_warning_test.c       |   16 +-
+ tools/testing/selftests/kvm/x86_64/mmu_role_test.c |   30 +-
+ .../selftests/kvm/x86_64/monitor_mwait_test        |  Bin 0 -> 1485656 bytes
+ .../selftests/kvm/x86_64/platform_info_test.c      |   51 +-
+ .../selftests/kvm/x86_64/pmu_event_filter_test.c   |  103 +-
+ .../testing/selftests/kvm/x86_64/set_boot_cpu_id.c |   91 +-
+ .../testing/selftests/kvm/x86_64/set_sregs_test.c  |   47 +-
+ .../selftests/kvm/x86_64/sev_migrate_tests.c       |  126 +--
+ tools/testing/selftests/kvm/x86_64/smm_test.c      |   39 +-
+ tools/testing/selftests/kvm/x86_64/state_test.c    |   31 +-
+ .../selftests/kvm/x86_64/svm_int_ctl_test.c        |   21 +-
+ .../kvm/x86_64/svm_nested_soft_inject_test.c       |  216 ++++
+ .../testing/selftests/kvm/x86_64/svm_vmcall_test.c |   16 +-
+ .../testing/selftests/kvm/x86_64/sync_regs_test.c  |   62 +-
+ .../selftests/kvm/x86_64/triple_fault_event_test.c |   90 ++
+ tools/testing/selftests/kvm/x86_64/tsc_msrs_test.c |   35 +-
+ .../selftests/kvm/x86_64/tsc_scaling_sync.c        |   25 +-
+ .../selftests/kvm/x86_64/userspace_io_test.c       |   18 +-
+ .../selftests/kvm/x86_64/userspace_msr_exit_test.c |  187 ++--
+ .../selftests/kvm/x86_64/vmx_apic_access_test.c    |   27 +-
+ .../kvm/x86_64/vmx_close_while_nested_test.c       |   17 +-
+ .../selftests/kvm/x86_64/vmx_dirty_log_test.c      |   13 +-
+ .../vmx_exception_with_invalid_guest_state.c       |   68 +-
+ .../kvm/x86_64/vmx_invalid_nested_guest_state.c    |   18 +-
+ .../kvm/x86_64/vmx_nested_tsc_scaling_test.c       |   29 +-
+ .../selftests/kvm/x86_64/vmx_pmu_caps_test.c       |   48 +-
+ .../kvm/x86_64/vmx_preemption_timer_test.c         |   35 +-
+ .../kvm/x86_64/vmx_set_nested_state_test.c         |   91 +-
+ .../selftests/kvm/x86_64/vmx_tsc_adjust_test.c     |   13 +-
+ .../testing/selftests/kvm/x86_64/xapic_ipi_test.c  |   48 +-
+ .../selftests/kvm/x86_64/xapic_state_test.c        |   60 +-
+ .../testing/selftests/kvm/x86_64/xen_shinfo_test.c |   73 +-
+ .../testing/selftests/kvm/x86_64/xen_vmcall_test.c |   25 +-
+ tools/testing/selftests/kvm/x86_64/xss_msr_test.c  |   56 +-
+ virt/kvm/kvm_main.c                                |  160 ++-
+ 171 files changed, 6196 insertions(+), 5083 deletions(-)
+ create mode 100644 Documentation/virt/kvm/s390/s390-pv-dump.rst
+ delete mode 100644 arch/x86/kvm/mmu/paging.h
+ delete mode 100644 tools/testing/selftests/kvm/lib/kvm_util_internal.h
+ create mode 100644 tools/testing/selftests/kvm/x86_64/max_vcpuid_cap_test.c
+ create mode 100755 tools/testing/selftests/kvm/x86_64/monitor_mwait_test
+ create mode 100644 tools/testing/selftests/kvm/x86_64/svm_nested_soft_inject_test.c
+ create mode 100644 tools/testing/selftests/kvm/x86_64/triple_fault_event_test.c
+Merging kvm-arm/next (5c0ad551e9aa Merge branch kvm-arm64/its-save-restore-fixes-5.19 into kvmarm-master/next)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git kvm-arm/next
+Already up to date.
+Merging kvms390/next (b1edf7f159a6 KVM: s390: selftests: Use TAP interface in the reset test)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git kvms390/next
+Already up to date.
+Merging xen-tip/linux-next (ca6969013d13 drm/xen: Add missing VM_DONTEXPAND flag in mmap callback)
+$ git merge -m Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git xen-tip/linux-next
+Merge made by the 'ort' strategy.
+ drivers/block/xen-blkfront.c            | 19 ++++++++++++-------
+ drivers/gpu/drm/xen/xen_drm_front_gem.c |  2 +-
+ drivers/xen/features.c                  |  2 +-
+ 3 files changed, 14 insertions(+), 9 deletions(-)
+Merging percpu/for-next (4e1f82dce05b Merge branch 'for-5.16-fixes' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu.git percpu/for-next
+Merge made by the 'ort' strategy.
+Merging workqueues/for-next (8bee9dd953b6 workqueue: Switch to new kerneldoc syntax for named variable macro argument)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq.git workqueues/for-next
+Already up to date.
+Merging drivers-x86/for-next (7518eefeb7ad platform/surface: aggregator_registry: Add support for keyboard cover on Surface Pro 8)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git drivers-x86/for-next
+Merge made by the 'ort' strategy.
+ .../driver-api/surface_aggregator/client.rst       |   6 +-
+ drivers/clk/x86/Makefile                           |   4 +-
+ drivers/hid/surface-hid/surface_hid_core.c         |  38 +-
+ drivers/platform/surface/aggregator/controller.c   |  53 ++-
+ .../platform/surface/surface_aggregator_registry.c | 403 +++++++++++++++------
+ drivers/platform/x86/Kconfig                       |   5 -
+ drivers/platform/x86/Makefile                      |   2 +-
+ drivers/platform/x86/system76_acpi.c               |   4 +-
+ drivers/power/supply/surface_battery.c             |   4 +-
+ drivers/power/supply/surface_charger.c             |   4 +-
+ include/linux/surface_aggregator/controller.h      |  24 +-
+ include/linux/surface_aggregator/device.h          | 125 ++++++-
+ include/linux/surface_aggregator/serial_hub.h      |   2 +-
+ 13 files changed, 517 insertions(+), 157 deletions(-)
+Merging chrome-platform/for-next (74bb746407bf platform/chrome: cros_ec: Always expose last resume result)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git chrome-platform/for-next
+Auto-merging drivers/mfd/cros_ec_dev.c
+Auto-merging include/linux/platform_data/cros_ec_commands.h
+Auto-merging include/linux/platform_data/cros_ec_proto.h
+Merge made by the 'ort' strategy.
+ .../chrome/google,cros-kbd-led-backlight.yaml      |   35 +
+ .../devicetree/bindings/mfd/google,cros-ec.yaml    |    3 +
+ drivers/mfd/cros_ec_dev.c                          |    4 +-
+ drivers/platform/chrome/Kconfig                    |   17 +-
+ drivers/platform/chrome/Makefile                   |    4 +
+ drivers/platform/chrome/cros_ec.c                  |   11 +-
+ drivers/platform/chrome/cros_ec_proto.c            |  371 ++---
+ drivers/platform/chrome/cros_ec_proto_test.c       | 1616 ++++++++++++++++++++
+ drivers/platform/chrome/cros_ec_trace.h            |    8 +-
+ drivers/platform/chrome/cros_ec_typec.c            |   39 +-
+ drivers/platform/chrome/cros_kbd_led_backlight.c   |  196 ++-
+ drivers/platform/chrome/cros_kunit_util.c          |   98 ++
+ drivers/platform/chrome/cros_kunit_util.h          |   36 +
+ drivers/platform/chrome/cros_usbpd_notify.c        |    4 +-
+ drivers/regulator/cros-ec-regulator.c              |   36 +-
+ include/linux/platform_data/cros_ec_commands.h     |    6 +-
+ include/linux/platform_data/cros_ec_proto.h        |    7 +-
+ 17 files changed, 2216 insertions(+), 275 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml
+ create mode 100644 drivers/platform/chrome/cros_ec_proto_test.c
+ create mode 100644 drivers/platform/chrome/cros_kunit_util.c
+ create mode 100644 drivers/platform/chrome/cros_kunit_util.h
+Merging hsi/for-next (43c14f8d18a7 HSI: omap_ssi: Fix refcount leak in ssi_probe)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git hsi/for-next
+Merge made by the 'ort' strategy.
+ drivers/hsi/clients/ssi_protocol.c      | 1 -
+ drivers/hsi/controllers/omap_ssi_core.c | 1 +
+ 2 files changed, 1 insertion(+), 1 deletion(-)
+Merging leds/for-next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds.git leds/for-next
+Already up to date.
+Merging ipmi/for-next (a508e33956b5 ipmi:ipmb: Fix refcount leak in ipmi_ipmb_probe)
+$ git merge -m Merge branch 'for-next' of git://github.com/cminyard/linux-ipmi.git ipmi/for-next
+Already up to date.
+Merging driver-core/driver-core-next (a52ed4866d2b mwifiex: fix sleep in atomic context bugs caused by dev_coredumpv)
+$ git merge -m Merge branch 'driver-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git driver-core/driver-core-next
+Auto-merging drivers/bluetooth/btmrvl_sdio.c
+Auto-merging drivers/bluetooth/hci_qca.c
+Auto-merging drivers/gpu/drm/msm/msm_gpu.c
+Auto-merging drivers/net/wireless/marvell/mwifiex/init.c
+Auto-merging drivers/net/wireless/marvell/mwifiex/main.c
+Auto-merging drivers/net/wireless/marvell/mwifiex/main.h
+Auto-merging drivers/net/wireless/marvell/mwifiex/sta_event.c
+Auto-merging drivers/net/wireless/realtek/rtw88/main.c
+Auto-merging drivers/net/wireless/realtek/rtw89/ser.c
+Auto-merging drivers/spi/spi.c
+Merge made by the 'ort' strategy.
+ drivers/base/base.h                                |   1 +
+ drivers/base/core.c                                | 122 +++++++++++++++++++--
+ drivers/base/dd.c                                  |  54 ++++-----
+ drivers/base/devcoredump.c                         |  16 +--
+ drivers/base/power/domain.c                        |   2 +-
+ drivers/bluetooth/btmrvl_sdio.c                    |   2 +-
+ drivers/bluetooth/hci_qca.c                        |   2 +-
+ drivers/gpu/drm/etnaviv/etnaviv_dump.c             |   2 +-
+ drivers/gpu/drm/msm/disp/msm_disp_snapshot.c       |   4 +-
+ drivers/gpu/drm/msm/msm_gpu.c                      |   4 +-
+ drivers/iommu/of_iommu.c                           |   2 +-
+ drivers/media/platform/qcom/venus/core.c           |   2 +-
+ drivers/net/can/spi/mcp251xfd/mcp251xfd-dump.c     |   2 +-
+ drivers/net/mdio/fwnode_mdio.c                     |   4 +-
+ drivers/net/wireless/ath/ath10k/coredump.c         |   2 +-
+ drivers/net/wireless/ath/wil6210/wil_crash_dump.c  |   2 +-
+ .../wireless/broadcom/brcm80211/brcmfmac/debug.c   |   2 +-
+ drivers/net/wireless/intel/iwlwifi/fw/dbg.c        |   6 +-
+ drivers/net/wireless/marvell/mwifiex/init.c        |   9 +-
+ drivers/net/wireless/marvell/mwifiex/main.c        |   3 +-
+ drivers/net/wireless/marvell/mwifiex/main.h        |   3 +-
+ drivers/net/wireless/marvell/mwifiex/sta_event.c   |   6 +-
+ drivers/net/wireless/mediatek/mt76/mt7615/mac.c    |   3 +-
+ drivers/net/wireless/mediatek/mt76/mt7921/mac.c    |   3 +-
+ drivers/net/wireless/realtek/rtw88/main.c          |   2 +-
+ drivers/net/wireless/realtek/rtw89/ser.c           |   2 +-
+ drivers/pinctrl/devicetree.c                       |   2 +-
+ drivers/remoteproc/qcom_q6v5_mss.c                 |   2 +-
+ drivers/remoteproc/remoteproc_coredump.c           |   8 +-
+ drivers/spi/spi.c                                  |   9 +-
+ include/drm/drm_print.h                            |   2 +-
+ include/linux/devcoredump.h                        |  13 +--
+ include/linux/device.h                             |   2 +
+ include/linux/device/driver.h                      |   2 +-
+ net/ipv4/ipconfig.c                                |   6 +
+ sound/soc/intel/avs/apl.c                          |   2 +-
+ sound/soc/intel/avs/skl.c                          |   2 +-
+ sound/soc/intel/catpt/dsp.c                        |   2 +-
+ 38 files changed, 200 insertions(+), 114 deletions(-)
+Merging usb/usb-next (105f3fd2f789 Merge branch 'staging-octeon' of gitolite.kernel.org:/pub/scm/linux/kernel/git/gregkh/staging into usb-next)
+$ git merge -m Merge branch 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb/usb-next
+Auto-merging MAINTAINERS
+CONFLICT (content): Merge conflict in MAINTAINERS
+Auto-merging drivers/usb/gadget/function/uvc_video.c
+Recorded preimage for 'MAINTAINERS'
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+Recorded resolution for 'MAINTAINERS'.
+[master 37ffe5d1e370] Merge branch 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
+$ git diff -M --stat --summary HEAD^..
+ Documentation/ABI/testing/sysfs-bus-usb            |   11 +
+ Documentation/ABI/testing/sysfs-class-typec        |    8 +
+ .../ABI/testing/sysfs-class-usb_power_delivery     |  240 +++
+ .../bindings/usb/aspeed,ast2600-udc.yaml           |   52 +
+ Documentation/devicetree/bindings/usb/dwc2.yaml    |    3 +
+ .../devicetree/bindings/usb/mediatek,mtk-xhci.yaml |    3 +
+ .../devicetree/bindings/usb/mediatek,mtu3.yaml     |    3 +
+ .../devicetree/bindings/usb/snps,dwc3.yaml         |    5 +
+ MAINTAINERS                                        |    8 +
+ arch/mips/configs/cavium_octeon_defconfig          |    2 +-
+ drivers/staging/Kconfig                            |    2 -
+ drivers/staging/Makefile                           |    1 -
+ drivers/staging/octeon-usb/Kconfig                 |   11 -
+ drivers/staging/octeon-usb/Makefile                |    2 -
+ drivers/staging/octeon-usb/TODO                    |    8 -
+ drivers/usb/cdns3/cdns3-gadget.c                   |    4 +-
+ drivers/usb/chipidea/ci.h                          |    1 +
+ drivers/usb/chipidea/ci_hdrc_imx.c                 |   23 +-
+ drivers/usb/chipidea/ci_hdrc_imx.h                 |    2 +-
+ drivers/usb/chipidea/core.c                        |    2 +
+ drivers/usb/chipidea/udc.c                         |   14 +
+ drivers/usb/common/usb-conn-gpio.c                 |   17 +
+ drivers/usb/core/hub.c                             |   99 +-
+ drivers/usb/core/hub.h                             |    3 +
+ drivers/usb/core/port.c                            |   83 +
+ drivers/usb/dwc2/hcd.c                             |    3 +
+ drivers/usb/dwc3/Kconfig                           |    4 +-
+ drivers/usb/dwc3/core.c                            |   50 +-
+ drivers/usb/dwc3/core.h                            |    1 +
+ drivers/usb/dwc3/dwc3-qcom.c                       |  140 +-
+ drivers/usb/dwc3/ep0.c                             |    2 +-
+ drivers/usb/gadget/function/f_uvc.c                |   30 +-
+ drivers/usb/gadget/function/uvc_queue.c            |   23 +-
+ drivers/usb/gadget/function/uvc_video.c            |   14 +-
+ drivers/usb/gadget/udc/Kconfig                     |   13 +
+ drivers/usb/gadget/udc/Makefile                    |    1 +
+ drivers/usb/gadget/udc/aspeed_udc.c                | 1594 ++++++++++++++++++++
+ drivers/usb/gadget/udc/bdc/bdc_cmd.c               |    2 +-
+ drivers/usb/gadget/udc/tegra-xudc.c                |    8 +-
+ drivers/usb/host/Kconfig                           |   10 +
+ drivers/usb/host/Makefile                          |    1 +
+ drivers/usb/host/ehci-platform.c                   |    2 +
+ drivers/usb/host/ehci-ppc-of.c                     |    1 +
+ drivers/usb/host/ehci-q.c                          |    2 +-
+ .../{staging/octeon-usb => usb/host}/octeon-hcd.c  |    0
+ .../{staging/octeon-usb => usb/host}/octeon-hcd.h  |    0
+ drivers/usb/host/ohci-at91.c                       |   69 +-
+ drivers/usb/host/ohci-nxp.c                        |    1 +
+ drivers/usb/host/ohci-platform.c                   |    3 +
+ drivers/usb/host/ohci-ppc-of.c                     |    1 +
+ drivers/usb/host/ohci-sm501.c                      |    2 +-
+ drivers/usb/host/xhci-mtk.c                        |    7 +
+ drivers/usb/host/xhci-tegra.c                      |    8 +-
+ drivers/usb/mtu3/mtu3.h                            |    1 +
+ drivers/usb/mtu3/mtu3_core.c                       |    3 +-
+ drivers/usb/mtu3/mtu3_gadget.c                     |   20 +-
+ drivers/usb/mtu3/mtu3_gadget_ep0.c                 |    2 +-
+ drivers/usb/mtu3/mtu3_plat.c                       |    7 +
+ drivers/usb/musb/Kconfig                           |   13 +-
+ drivers/usb/musb/Makefile                          |    1 +
+ drivers/usb/musb/mpfs.c                            |  265 ++++
+ drivers/usb/musb/musb_core.c                       |   16 +-
+ drivers/usb/musb/musb_gadget.c                     |    2 -
+ drivers/usb/renesas_usbhs/rza.c                    |    4 +
+ drivers/usb/storage/transport.c                    |    2 +-
+ drivers/usb/typec/Makefile                         |    2 +-
+ drivers/usb/typec/class.c                          |  149 ++
+ drivers/usb/typec/class.h                          |    4 +
+ drivers/usb/typec/mux.c                            |    8 +-
+ drivers/usb/typec/pd.c                             |  708 +++++++++
+ drivers/usb/typec/pd.h                             |   30 +
+ drivers/usb/typec/tcpm/tcpm.c                      |  144 +-
+ drivers/usb/typec/ucsi/ucsi_ccg.c                  |   28 +-
+ drivers/usb/usbip/vudc_rx.c                        |    6 +-
+ drivers/usb/usbip/vudc_sysfs.c                     |   14 +-
+ include/linux/usb.h                                |    2 +
+ include/linux/usb/pd.h                             |   38 +
+ include/linux/usb/typec.h                          |   23 +
+ include/linux/usb/typec_mux.h                      |   44 +-
+ 79 files changed, 3872 insertions(+), 263 deletions(-)
+ create mode 100644 Documentation/ABI/testing/sysfs-class-usb_power_delivery
+ create mode 100644 Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml
+ delete mode 100644 drivers/staging/octeon-usb/Kconfig
+ delete mode 100644 drivers/staging/octeon-usb/Makefile
+ delete mode 100644 drivers/staging/octeon-usb/TODO
+ create mode 100644 drivers/usb/gadget/udc/aspeed_udc.c
+ rename drivers/{staging/octeon-usb => usb/host}/octeon-hcd.c (100%)
+ rename drivers/{staging/octeon-usb => usb/host}/octeon-hcd.h (100%)
+ create mode 100644 drivers/usb/musb/mpfs.c
+ create mode 100644 drivers/usb/typec/pd.c
+ create mode 100644 drivers/usb/typec/pd.h
+Merging thunderbolt/next (34b9715b7cae thunderbolt: Fix typo in comment)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git thunderbolt/next
+Merge made by the 'ort' strategy.
+ drivers/thunderbolt/ctl.c     |   6 +-
+ drivers/thunderbolt/ctl.h     |   2 +-
+ drivers/thunderbolt/icm.c     |   2 +
+ drivers/thunderbolt/nhi.c     |   4 +
+ drivers/thunderbolt/nhi.h     |   2 +
+ drivers/thunderbolt/switch.c  |  91 +++++++++--------
+ drivers/thunderbolt/tb.c      |  68 ++++++++++---
+ drivers/thunderbolt/tb.h      |  48 ++++-----
+ drivers/thunderbolt/tb_regs.h |   6 ++
+ drivers/thunderbolt/tmu.c     | 221 +++++++++++++++++++++++++++++++++++-------
+ 10 files changed, 335 insertions(+), 115 deletions(-)
+Merging usb-gadget/next (e49d033bddf5 Linux 5.12-rc6)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git usb-gadget/next
+Already up to date.
+Merging usb-serial/usb-next (7828466cff6b USB: serial: use kmemdup instead of kmalloc + memcpy)
+$ git merge -m Merge branch 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git usb-serial/usb-next
+Merge made by the 'ort' strategy.
+ drivers/usb/serial/garmin_gps.c | 4 +---
+ drivers/usb/serial/opticon.c    | 4 +---
+ drivers/usb/serial/sierra.c     | 4 +---
+ 3 files changed, 3 insertions(+), 9 deletions(-)
+Merging tty/tty-next (df36f3e3fbb7 Merge tag 'v5.19-rc3' into tty-next)
+$ git merge -m Merge branch 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty/tty-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/serial/mediatek,uart.yaml  | 120 ++++
+ .../devicetree/bindings/serial/mtk-uart.txt        |  59 --
+ Documentation/driver-api/serial/serial-rs485.rst   |  12 +-
+ drivers/accessibility/braille/braille_console.c    |   2 +-
+ drivers/accessibility/speakup/main.c               |   2 +-
+ drivers/tty/mips_ejtag_fdc.c                       |   2 +-
+ drivers/tty/n_tty.c                                |  92 ++-
+ drivers/tty/serial/8250/8250.h                     |  21 +
+ drivers/tty/serial/8250/8250_bcm2835aux.c          |   1 +
+ drivers/tty/serial/8250/8250_core.c                |   4 +-
+ drivers/tty/serial/8250/8250_dw.c                  |   7 +-
+ drivers/tty/serial/8250/8250_dwlib.c               |  17 +-
+ drivers/tty/serial/8250/8250_exar.c                |  14 +-
+ drivers/tty/serial/8250/8250_fintek.c              |  29 +-
+ drivers/tty/serial/8250/8250_lpc18xx.c             |  20 +-
+ drivers/tty/serial/8250/8250_of.c                  |   1 +
+ drivers/tty/serial/8250/8250_pci.c                 |  24 +-
+ drivers/tty/serial/8250/8250_port.c                |  82 ++-
+ drivers/tty/serial/Kconfig                         |   1 +
+ drivers/tty/serial/amba-pl011.c                    |  13 +-
+ drivers/tty/serial/ar933x_uart.c                   |   7 +
+ drivers/tty/serial/atmel_serial.c                  |   7 +
+ drivers/tty/serial/fsl_lpuart.c                    |  25 +-
+ drivers/tty/serial/imx.c                           |  19 +-
+ drivers/tty/serial/max310x.c                       | 270 ++++++---
+ drivers/tty/serial/mcf.c                           |   7 +-
+ drivers/tty/serial/omap-serial.c                   |   8 +
+ drivers/tty/serial/pic32_uart.c                    |   4 +-
+ drivers/tty/serial/pmac_zilog.c                    |   1 -
+ drivers/tty/serial/sc16is7xx.c                     |   8 +-
+ drivers/tty/serial/serial-tegra.c                  |   4 +-
+ drivers/tty/serial/serial_core.c                   | 120 +++-
+ drivers/tty/serial/stm32-usart.c                   |   8 +
+ drivers/tty/tty_buffer.c                           |  59 +-
+ drivers/tty/tty_io.c                               |   2 +-
+ drivers/tty/tty_port.c                             |  21 +
+ drivers/tty/vt/Makefile                            |   2 +-
+ drivers/tty/vt/consolemap.c                        | 634 +++++++++++----------
+ drivers/tty/vt/defkeymap.c_shipped                 |   6 +-
+ drivers/tty/vt/selection.c                         |   3 +-
+ drivers/tty/vt/vt.c                                |   6 +-
+ drivers/video/console/vgacon.c                     |   4 +-
+ include/linux/console_struct.h                     |   6 +-
+ include/linux/consolemap.h                         |  60 +-
+ include/linux/serial_core.h                        |   2 +
+ include/linux/tty_buffer.h                         |   1 +
+ include/linux/tty_ldisc.h                          |  14 +
+ include/linux/tty_port.h                           |   2 +
+ 48 files changed, 1187 insertions(+), 646 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+ delete mode 100644 Documentation/devicetree/bindings/serial/mtk-uart.txt
+Merging char-misc/char-misc-next (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'char-misc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git char-misc/char-misc-next
+Already up to date.
+Merging coresight/next (a111daf0c53a Linux 5.19-rc3)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git coresight/next
+Already up to date.
+Merging fpga/for-next (2df84a757d87 fpga: altera-pr-ip: fix unsigned comparison with less than zero)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git fpga/for-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../testing/sysfs-driver-intel-m10-bmc-sec-update  |  61 ++
+ MAINTAINERS                                        |   7 +
+ drivers/fpga/Kconfig                               |  12 +
+ drivers/fpga/Makefile                              |   3 +
+ drivers/fpga/altera-pr-ip-core.c                   |   2 +-
+ drivers/fpga/dfl.c                                 |   4 +-
+ drivers/fpga/fpga-bridge.c                         |   6 +-
+ drivers/fpga/fpga-mgr.c                            |   6 +-
+ drivers/fpga/fpga-region.c                         |   6 +-
+ drivers/fpga/intel-m10-bmc-sec-update.c            | 625 +++++++++++++++++++++
+ drivers/mfd/intel-m10-bmc.c                        |   2 +-
+ 11 files changed, 721 insertions(+), 13 deletions(-)
+ create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
+ create mode 100644 drivers/fpga/intel-m10-bmc-sec-update.c
+Merging icc/icc-next (b3d5304b64e7 Merge branch 'icc-sm6350' into icc-next)
+$ git merge -m Merge branch 'icc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git icc/icc-next
+Merge made by the 'ort' strategy.
+ .../bindings/interconnect/qcom,rpmh-common.yaml    |  43 ++
+ .../bindings/interconnect/qcom,rpmh.yaml           |  22 +-
+ .../bindings/interconnect/qcom,sm6350-rpmh.yaml    |  82 ++++
+ drivers/interconnect/qcom/Kconfig                  |   9 +
+ drivers/interconnect/qcom/Makefile                 |   2 +
+ drivers/interconnect/qcom/icc-rpmh.c               |   4 +
+ drivers/interconnect/qcom/sm6350.c                 | 493 +++++++++++++++++++++
+ drivers/interconnect/qcom/sm6350.h                 | 139 ++++++
+ include/dt-bindings/interconnect/qcom,sm6350.h     | 148 +++++++
+ 9 files changed, 925 insertions(+), 17 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml
+ create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml
+ create mode 100644 drivers/interconnect/qcom/sm6350.c
+ create mode 100644 drivers/interconnect/qcom/sm6350.h
+ create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h
+Merging iio/togreg (88cb99daa2b5 iio: adc: stm32-adc: Use generic_handle_domain_irq())
+$ git merge -m Merge branch 'togreg' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git iio/togreg
+Auto-merging MAINTAINERS
+Auto-merging drivers/iio/adc/adi-axi-adc.c
+Auto-merging drivers/iio/adc/rzg2l_adc.c
+Auto-merging drivers/iio/adc/stm32-adc-core.c
+Auto-merging drivers/iio/adc/ti-ads131e08.c
+Auto-merging drivers/iio/chemical/ccs811.c
+Auto-merging drivers/iio/frequency/admv1014.c
+Auto-merging drivers/iio/gyro/mpu3050-core.c
+Auto-merging drivers/iio/humidity/hts221_buffer.c
+Auto-merging drivers/iio/imu/inv_icm42600/inv_icm42600.h
+Auto-merging drivers/iio/proximity/sx9324.c
+Merge made by the 'ort' strategy.
+ Documentation/ABI/testing/sysfs-bus-iio            |    5 +
+ .../bindings/iio/accel/adi,adis16240.yaml          |    2 +-
+ .../devicetree/bindings/iio/accel/adi,adxl345.yaml |    2 +-
+ .../bindings/iio/accel/bosch,bmi088.yaml           |    2 +
+ .../bindings/iio/accel/murata,sca3300.yaml         |    1 +
+ .../devicetree/bindings/iio/adc/adi,ad9467.yaml    |    1 -
+ .../devicetree/bindings/iio/adc/adi,axi-adc.yaml   |    1 -
+ .../bindings/iio/adc/qcom,spmi-rradc.yaml          |   51 +
+ .../bindings/iio/adc/renesas,rzg2l-adc.yaml        |   28 +-
+ .../devicetree/bindings/iio/dac/adi,ad5770r.yaml   |    2 +-
+ .../devicetree/bindings/iio/dac/ti,dac5571.yaml    |    1 +
+ .../devicetree/bindings/iio/imu/adi,adis16480.yaml |    2 +-
+ .../bindings/iio/proximity/semtech,sx9324.yaml     |   39 +
+ .../bindings/iio/proximity/semtech,sx9360.yaml     |    9 +
+ .../bindings/iio/proximity/st,vl53l0x.yaml         |    5 +
+ MAINTAINERS                                        |    1 +
+ drivers/iio/accel/Kconfig                          |    2 +
+ drivers/iio/accel/adxl313_core.c                   |    2 +-
+ drivers/iio/accel/adxl355_core.c                   |    2 +-
+ drivers/iio/accel/adxl367.c                        |   48 +-
+ drivers/iio/accel/adxl367_spi.c                    |    8 +-
+ drivers/iio/accel/bma220_spi.c                     |    2 +-
+ drivers/iio/accel/bma400.h                         |   50 +-
+ drivers/iio/accel/bma400_core.c                    |  710 +++++++++++++-
+ drivers/iio/accel/bma400_i2c.c                     |   10 +-
+ drivers/iio/accel/bma400_spi.c                     |    8 +-
+ drivers/iio/accel/bmi088-accel-core.c              |   99 +-
+ drivers/iio/accel/bmi088-accel-spi.c               |   17 +-
+ drivers/iio/accel/bmi088-accel.h                   |    9 +-
+ drivers/iio/accel/cros_ec_accel_legacy.c           |    2 +-
+ drivers/iio/accel/kxsd9-i2c.c                      |    2 +-
+ drivers/iio/accel/kxsd9-spi.c                      |    2 +-
+ drivers/iio/accel/kxsd9.c                          |   11 +-
+ drivers/iio/accel/mc3230.c                         |    4 +-
+ drivers/iio/accel/mma7660.c                        |    6 +-
+ drivers/iio/accel/sca3000.c                        |    6 +-
+ drivers/iio/accel/sca3300.c                        |  325 +++++--
+ drivers/iio/accel/stk8312.c                        |    4 +-
+ drivers/iio/accel/stk8ba50.c                       |    4 +-
+ drivers/iio/adc/Kconfig                            |   17 +-
+ drivers/iio/adc/Makefile                           |    1 +
+ drivers/iio/adc/ad7266.c                           |    4 +-
+ drivers/iio/adc/ad7280a.c                          |    2 +-
+ drivers/iio/adc/ad7292.c                           |    2 +-
+ drivers/iio/adc/ad7298.c                           |    2 +-
+ drivers/iio/adc/ad7476.c                           |    5 +-
+ drivers/iio/adc/ad7606.c                           |    1 +
+ drivers/iio/adc/ad7606.h                           |    4 +-
+ drivers/iio/adc/ad7606_par.c                       |    1 +
+ drivers/iio/adc/ad7766.c                           |    5 +-
+ drivers/iio/adc/ad7768-1.c                         |    4 +-
+ drivers/iio/adc/ad7887.c                           |    5 +-
+ drivers/iio/adc/ad7923.c                           |    4 +-
+ drivers/iio/adc/ad7949.c                           |    2 +-
+ drivers/iio/adc/ad9467.c                           |    1 +
+ drivers/iio/adc/adi-axi-adc.c                      |   11 +-
+ drivers/iio/adc/at91-sama5d2_adc.c                 |    2 +-
+ drivers/iio/adc/berlin2-adc.c                      |    2 +
+ drivers/iio/adc/hi8435.c                           |    2 +-
+ drivers/iio/adc/imx7d_adc.c                        |    1 +
+ drivers/iio/adc/imx8qxp-adc.c                      |    1 +
+ drivers/iio/adc/ina2xx-adc.c                       |   10 +-
+ drivers/iio/adc/ingenic-adc.c                      |    2 +
+ drivers/iio/adc/intel_mrfld_adc.c                  |    1 +
+ drivers/iio/adc/lpc18xx_adc.c                      |    3 +-
+ drivers/iio/adc/ltc2496.c                          |    4 +-
+ drivers/iio/adc/ltc2497.c                          |    4 +-
+ drivers/iio/adc/max1027.c                          |    2 +-
+ drivers/iio/adc/max11100.c                         |    4 +-
+ drivers/iio/adc/max1118.c                          |    2 +-
+ drivers/iio/adc/max1241.c                          |    2 +-
+ drivers/iio/adc/mcp320x.c                          |    2 +-
+ drivers/iio/adc/meson_saradc.c                     |  177 ++--
+ drivers/iio/adc/mp2629_adc.c                       |    1 +
+ drivers/iio/adc/mt6360-adc.c                       |    1 +
+ drivers/iio/adc/nau7802.c                          |   16 +-
+ drivers/iio/adc/npcm_adc.c                         |    1 +
+ drivers/iio/adc/qcom-spmi-rradc.c                  | 1022 ++++++++++++++++++++
+ drivers/iio/adc/rzg2l_adc.c                        |    4 +-
+ drivers/iio/adc/sc27xx_adc.c                       |   15 +-
+ drivers/iio/adc/stm32-adc-core.c                   |    2 +-
+ drivers/iio/adc/stx104.c                           |   56 +-
+ drivers/iio/adc/ti-adc0832.c                       |    2 +-
+ drivers/iio/adc/ti-adc084s021.c                    |    4 +-
+ drivers/iio/adc/ti-adc108s102.c                    |    4 +-
+ drivers/iio/adc/ti-adc12138.c                      |    2 +-
+ drivers/iio/adc/ti-adc128s052.c                    |    2 +-
+ drivers/iio/adc/ti-adc161s626.c                    |    2 +-
+ drivers/iio/adc/ti-ads1015.c                       |    8 +-
+ drivers/iio/adc/ti-ads124s08.c                     |    2 +-
+ drivers/iio/adc/ti-ads131e08.c                     |    2 +-
+ drivers/iio/adc/ti-ads7950.c                       |    4 +-
+ drivers/iio/adc/ti-ads8344.c                       |    2 +-
+ drivers/iio/adc/ti-ads8688.c                       |    2 +-
+ drivers/iio/adc/ti-tlc4541.c                       |    4 +-
+ drivers/iio/adc/vf610_adc.c                        |   15 +-
+ drivers/iio/addac/ad74413r.c                       |   12 +-
+ drivers/iio/amplifiers/ad8366.c                    |    4 +-
+ drivers/iio/chemical/atlas-sensor.c                |    8 +-
+ drivers/iio/chemical/bme680_core.c                 |    2 +-
+ drivers/iio/chemical/ccs811.c                      |   10 +-
+ .../iio/common/cros_ec_sensors/cros_ec_lid_angle.c |    1 +
+ .../iio/common/cros_ec_sensors/cros_ec_sensors.c   |    1 +
+ .../common/cros_ec_sensors/cros_ec_sensors_core.c  |   30 +-
+ drivers/iio/common/ssp_sensors/ssp.h               |    3 +-
+ drivers/iio/dac/Kconfig                            |    2 +-
+ drivers/iio/dac/ad5064.c                           |    4 +-
+ drivers/iio/dac/ad5360.c                           |    4 +-
+ drivers/iio/dac/ad5421.c                           |    4 +-
+ drivers/iio/dac/ad5449.c                           |    4 +-
+ drivers/iio/dac/ad5504.c                           |    2 +-
+ drivers/iio/dac/ad5592r-base.c                     |    2 +-
+ drivers/iio/dac/ad5592r-base.h                     |    4 +-
+ drivers/iio/dac/ad5686.h                           |    6 +-
+ drivers/iio/dac/ad5755.c                           |    4 +-
+ drivers/iio/dac/ad5761.c                           |    4 +-
+ drivers/iio/dac/ad5764.c                           |    4 +-
+ drivers/iio/dac/ad5766.c                           |    2 +-
+ drivers/iio/dac/ad5770r.c                          |    2 +-
+ drivers/iio/dac/ad5791.c                           |    2 +-
+ drivers/iio/dac/ad7293.c                           |    2 +-
+ drivers/iio/dac/ad7303.c                           |    4 +-
+ drivers/iio/dac/ad8801.c                           |    2 +-
+ drivers/iio/dac/cio-dac.c                          |   14 +-
+ drivers/iio/dac/ltc2688.c                          |    4 +-
+ drivers/iio/dac/mcp4922.c                          |    2 +-
+ drivers/iio/dac/stm32-dac.c                        |    6 +-
+ drivers/iio/dac/ti-dac082s085.c                    |    2 +-
+ drivers/iio/dac/ti-dac5571.c                       |    5 +-
+ drivers/iio/dac/ti-dac7311.c                       |    2 +-
+ drivers/iio/dac/ti-dac7612.c                       |    4 +-
+ drivers/iio/dac/vf610_dac.c                        |    1 +
+ drivers/iio/frequency/ad9523.c                     |    6 +-
+ drivers/iio/frequency/adf4350.c                    |    6 +-
+ drivers/iio/frequency/adf4371.c                    |    2 +-
+ drivers/iio/frequency/admv1013.c                   |    2 +-
+ drivers/iio/frequency/admv1014.c                   |    2 +-
+ drivers/iio/frequency/admv4420.c                   |    2 +-
+ drivers/iio/frequency/adrf6780.c                   |    2 +-
+ drivers/iio/gyro/adis16080.c                       |    2 +-
+ drivers/iio/gyro/adis16130.c                       |    2 +-
+ drivers/iio/gyro/adxrs450.c                        |    2 +-
+ drivers/iio/gyro/bmg160_core.c                     |    2 +-
+ drivers/iio/gyro/fxas21002c_core.c                 |    6 +-
+ drivers/iio/gyro/mpu3050-core.c                    |   14 +-
+ drivers/iio/gyro/mpu3050-i2c.c                     |    2 +-
+ drivers/iio/health/afe4404.c                       |    4 +-
+ drivers/iio/humidity/hts221_buffer.c               |    1 +
+ drivers/iio/humidity/hts221_core.c                 |   12 +-
+ drivers/iio/humidity/hts221_i2c.c                  |    3 +-
+ drivers/iio/humidity/hts221_spi.c                  |    3 +-
+ drivers/iio/imu/fxos8700_core.c                    |    2 +-
+ drivers/iio/imu/inv_icm42600/inv_icm42600.h        |    2 +-
+ drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h |    2 +-
+ drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h          |    2 +-
+ drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c       |   16 +-
+ drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c        |    3 +-
+ drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i3c.c        |    5 +-
+ drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c        |    3 +-
+ drivers/iio/industrialio-buffer.c                  |   56 +-
+ drivers/iio/industrialio-core.c                    |   66 +-
+ drivers/iio/industrialio-trigger.c                 |   37 +-
+ drivers/iio/light/bh1780.c                         |    7 +-
+ drivers/iio/light/cros_ec_light_prox.c             |    3 +-
+ drivers/iio/light/isl29028.c                       |    4 +-
+ drivers/iio/light/jsa1212.c                        |    4 +-
+ drivers/iio/light/opt3001.c                        |    3 +-
+ drivers/iio/light/pa12203001.c                     |    8 +-
+ drivers/iio/light/stk3310.c                        |    4 +-
+ drivers/iio/light/tsl2563.c                        |    7 +-
+ drivers/iio/light/tsl2583.c                        |    4 +-
+ drivers/iio/light/us5182d.c                        |    8 +-
+ drivers/iio/light/vcnl4000.c                       |    8 +-
+ drivers/iio/light/vcnl4035.c                       |   10 +-
+ drivers/iio/magnetometer/bmc150_magn.c             |    3 +-
+ drivers/iio/magnetometer/bmc150_magn.h             |    2 +-
+ drivers/iio/magnetometer/bmc150_magn_i2c.c         |    4 +-
+ drivers/iio/potentiometer/ad5110.c                 |    4 +-
+ drivers/iio/potentiometer/ad5272.c                 |    2 +-
+ drivers/iio/potentiometer/max5481.c                |    2 +-
+ drivers/iio/potentiometer/mcp41010.c               |    2 +-
+ drivers/iio/potentiometer/mcp4131.c                |    2 +-
+ drivers/iio/pressure/cros_ec_baro.c                |    3 +-
+ drivers/iio/pressure/dlhl60d.c                     |    2 +-
+ drivers/iio/proximity/as3935.c                     |    2 +-
+ drivers/iio/proximity/ping.c                       |    2 +-
+ drivers/iio/proximity/srf04.c                      |   11 +-
+ drivers/iio/proximity/srf08.c                      |    2 +-
+ drivers/iio/proximity/sx9324.c                     |   76 +-
+ drivers/iio/proximity/sx9360.c                     |   15 +-
+ drivers/iio/proximity/vcnl3020.c                   |    4 +-
+ drivers/iio/proximity/vl53l0x-i2c.c                |   55 +-
+ drivers/iio/resolver/ad2s1200.c                    |    2 +-
+ drivers/iio/resolver/ad2s90.c                      |    2 +-
+ drivers/iio/temperature/ltc2983.c                  |    4 +-
+ drivers/iio/temperature/max31865.c                 |    2 +-
+ drivers/iio/temperature/maxim_thermocouple.c       |    2 +-
+ drivers/iio/trigger/stm32-lptimer-trigger.c        |    4 +-
+ drivers/mfd/qcom-spmi-pmic.c                       |  272 ++++--
+ drivers/spmi/spmi.c                                |   17 +
+ include/linux/iio/common/cros_ec_sensors_core.h    |    2 -
+ include/linux/iio/iio.h                            |   14 +-
+ include/linux/iio/trigger.h                        |    5 +
+ include/linux/spmi.h                               |    3 +
+ include/soc/qcom/qcom-spmi-pmic.h                  |   61 ++
+ 205 files changed, 3194 insertions(+), 847 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml
+ create mode 100644 drivers/iio/adc/qcom-spmi-rradc.c
+ create mode 100644 include/soc/qcom/qcom-spmi-pmic.h
+Merging phy-next/next (18b3eb79b1cf MAINTAINERS: add include/dt-bindings/phy to GENERIC PHY FRAMEWORK)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git phy-next/next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/phy/mediatek,dsi-phy.yaml  |    4 +
+ .../devicetree/bindings/phy/mediatek,tphy.yaml     |    1 +
+ .../devicetree/bindings/phy/mxs-usb-phy.txt        |    1 +
+ .../devicetree/bindings/phy/qcom,edp-phy.yaml      |    6 +
+ .../devicetree/bindings/phy/renesas,usb3-phy.yaml  |    2 +-
+ .../devicetree/bindings/phy/samsung,ufs-phy.yaml   |   15 +-
+ MAINTAINERS                                        |    1 +
+ drivers/phy/qualcomm/Makefile                      |    8 +-
+ drivers/phy/qualcomm/phy-qcom-qmp-combo.c          | 2579 ++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c   | 1081 ++++
+ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c           | 2404 ++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c            | 1390 +++++
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c            | 2751 +++++++++
+ drivers/phy/qualcomm/phy-qcom-qmp.c                | 6350 --------------------
+ drivers/phy/samsung/Makefile                       |    1 +
+ drivers/phy/samsung/phy-exynos7-ufs.c              |    5 +-
+ drivers/phy/samsung/phy-exynosautov9-ufs.c         |   22 +-
+ drivers/phy/samsung/phy-fsd-ufs.c                  |   58 +
+ drivers/phy/samsung/phy-samsung-ufs.c              |   23 +-
+ drivers/phy/samsung/phy-samsung-ufs.h              |   26 +-
+ drivers/phy/ti/phy-j721e-wiz.c                     |   75 +-
+ 21 files changed, 10395 insertions(+), 6408 deletions(-)
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+ create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+ delete mode 100644 drivers/phy/qualcomm/phy-qcom-qmp.c
+ create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c
+Merging soundwire/next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git soundwire/next
+Already up to date.
+Merging extcon/extcon-next (775486c09698 extcon: rt8973a: Drop useless mask_invert flag on irqchip)
+$ git merge -m Merge branch 'extcon-next' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon.git extcon/extcon-next
+Merge made by the 'ort' strategy.
+ drivers/extcon/extcon-fsa9480.c  | 6 ------
+ drivers/extcon/extcon-max77843.c | 3 +--
+ drivers/extcon/extcon-palmas.c   | 2 +-
+ drivers/extcon/extcon-rt8973a.c  | 1 -
+ drivers/extcon/extcon-sm5502.c   | 2 --
+ drivers/extcon/extcon.c          | 2 +-
+ 6 files changed, 3 insertions(+), 13 deletions(-)
+Merging gnss/gnss-next (c0c725d7350e gnss: replace ida_simple API)
+$ git merge -m Merge branch 'gnss-next' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git gnss/gnss-next
+Merge made by the 'ort' strategy.
+ drivers/gnss/core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+Merging vfio/next (421cfe6596f6 vfio: remove VFIO_GROUP_NOTIFY_SET_KVM)
+$ git merge -m Merge branch 'next' of git://github.com/awilliam/linux-vfio.git vfio/next
+Already up to date.
+Merging staging/staging-next (6ad9232a99e0 Merge branch 'staging-octeon' of gitolite.kernel.org:/pub/scm/linux/kernel/git/gregkh/staging into staging-next)
+$ git merge -m Merge branch 'staging-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git staging/staging-next
+Auto-merging MAINTAINERS
+Auto-merging drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
+Auto-merging drivers/staging/vt6655/device_main.c
+Auto-merging drivers/staging/vt6655/rxtx.c
+Merge made by the 'ort' strategy.
+ Documentation/driver-api/vme.rst                   |    4 +-
+ MAINTAINERS                                        |    5 +-
+ drivers/Kconfig                                    |    2 -
+ drivers/Makefile                                   |    1 -
+ drivers/staging/fbtft/fb_ssd1351.c                 |    3 +-
+ drivers/staging/fbtft/fbtft-core.c                 |    3 +-
+ drivers/staging/greybus/audio_helper.c             |   14 +-
+ drivers/staging/greybus/fw-management.c            |    6 +-
+ drivers/staging/greybus/loopback.c                 |    2 +-
+ drivers/staging/olpc_dcon/olpc_dcon.c              |    7 +-
+ drivers/staging/qlge/qlge_main.c                   |   26 +-
+ drivers/staging/r8188eu/core/rtw_cmd.c             |   15 +-
+ drivers/staging/r8188eu/core/rtw_efuse.c           |   33 +-
+ drivers/staging/r8188eu/core/rtw_fw.c              |   78 +-
+ drivers/staging/r8188eu/core/rtw_ieee80211.c       |    1 +
+ drivers/staging/r8188eu/core/rtw_ioctl_set.c       |    1 -
+ drivers/staging/r8188eu/core/rtw_iol.c             |    8 +-
+ drivers/staging/r8188eu/core/rtw_led.c             |   16 +-
+ drivers/staging/r8188eu/core/rtw_mlme.c            |    2 -
+ drivers/staging/r8188eu/core/rtw_mlme_ext.c        |  199 +-
+ drivers/staging/r8188eu/core/rtw_pwrctrl.c         |    9 +-
+ drivers/staging/r8188eu/core/rtw_recv.c            |    5 +-
+ drivers/staging/r8188eu/core/rtw_wlan_util.c       |   46 +-
+ drivers/staging/r8188eu/core/rtw_xmit.c            |   34 +-
+ drivers/staging/r8188eu/hal/Hal8188ERateAdaptive.c |   33 +-
+ drivers/staging/r8188eu/hal/HalPhyRf_8188e.c       |   21 +-
+ drivers/staging/r8188eu/hal/HalPwrSeqCmd.c         |    9 +-
+ drivers/staging/r8188eu/hal/hal_com.c              |   27 +-
+ drivers/staging/r8188eu/hal/rtl8188e_cmd.c         |   37 +-
+ drivers/staging/r8188eu/hal/rtl8188e_dm.c          |    6 +-
+ drivers/staging/r8188eu/hal/rtl8188e_hal_init.c    |  136 +-
+ drivers/staging/r8188eu/hal/rtl8188e_phycfg.c      |   30 +-
+ drivers/staging/r8188eu/hal/rtl8188eu_recv.c       |    2 +-
+ drivers/staging/r8188eu/hal/usb_halinit.c          |  271 ++-
+ drivers/staging/r8188eu/hal/usb_ops_linux.c        |   33 +-
+ .../staging/r8188eu/include/Hal8188ERateAdaptive.h |   13 -
+ drivers/staging/r8188eu/include/basic_types.h      |   52 -
+ drivers/staging/r8188eu/include/hal_intf.h         |    1 -
+ drivers/staging/r8188eu/include/ieee80211.h        |    7 -
+ drivers/staging/r8188eu/include/osdep_service.h    |    1 -
+ drivers/staging/r8188eu/include/rtw_io.h           |    8 +-
+ drivers/staging/r8188eu/include/rtw_iol.h          |   24 +-
+ drivers/staging/r8188eu/include/rtw_mlme_ext.h     |    3 +-
+ drivers/staging/r8188eu/os_dep/ioctl_linux.c       |   49 +-
+ drivers/staging/r8188eu/os_dep/os_intfs.c          |   19 +-
+ drivers/staging/r8188eu/os_dep/usb_intf.c          |    2 +-
+ drivers/staging/r8188eu/os_dep/xmit_linux.c        |    2 +-
+ drivers/staging/rtl8192u/r8192U_dm.c               |    2 +-
+ drivers/staging/rtl8723bs/core/rtw_mlme_ext.c      |    2 +-
+ drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c  |  225 +--
+ drivers/staging/rts5208/spi.c                      |    6 +-
+ drivers/staging/sm750fb/ddk750_dvi.c               |    2 +-
+ drivers/staging/sm750fb/ddk750_power.h             |    2 +-
+ drivers/staging/sm750fb/ddk750_sii164.c            |    6 +-
+ drivers/staging/sm750fb/ddk750_sii164.h            |    2 +-
+ .../vc04_services/bcm2835-audio/bcm2835-vchiq.c    |   40 +-
+ .../include/linux/raspberrypi/vchiq.h              |   48 +-
+ drivers/staging/vc04_services/interface/TESTING    |   82 +
+ .../vc04_services/interface/vchiq_arm/vchiq_arm.c  |   92 +-
+ .../vc04_services/interface/vchiq_arm/vchiq_arm.h  |    8 +-
+ .../vc04_services/interface/vchiq_arm/vchiq_core.c |   97 +-
+ .../vc04_services/interface/vchiq_arm/vchiq_core.h |   38 +-
+ .../vc04_services/interface/vchiq_arm/vchiq_dev.c  |   40 +-
+ .../staging/vc04_services/vchiq-mmal/mmal-vchiq.c  |   63 +-
+ drivers/staging/vme_user/Kconfig                   |   27 +
+ drivers/staging/vme_user/Makefile                  |    3 +
+ drivers/{vme => staging/vme_user}/vme.c            |    2 +-
+ {include/linux => drivers/staging/vme_user}/vme.h  |    0
+ drivers/{vme => staging/vme_user}/vme_bridge.h     |    2 +-
+ .../{vme/bridges => staging/vme_user}/vme_fake.c   |    4 +-
+ .../{vme/bridges => staging/vme_user}/vme_tsi148.c |    4 +-
+ .../{vme/bridges => staging/vme_user}/vme_tsi148.h |    0
+ drivers/staging/vme_user/vme_user.c                |    2 +-
+ drivers/staging/vt6655/baseband.c                  |    2 +-
+ drivers/staging/vt6655/card.c                      |   71 +-
+ drivers/staging/vt6655/device_main.c               |   28 +-
+ drivers/staging/vt6655/mac.c                       |    2 +-
+ drivers/staging/vt6655/mac.h                       |   57 +-
+ drivers/staging/vt6655/power.c                     |    4 +-
+ drivers/staging/vt6655/rf.c                        |    4 +-
+ drivers/staging/vt6655/rxtx.c                      |    4 +-
+ drivers/staging/vt6655/srom.c                      |    2 +-
+ drivers/staging/vt6655/upc.h                       |   35 -
+ drivers/vme/Kconfig                                |   18 -
+ drivers/vme/Makefile                               |    8 -
+ drivers/vme/boards/Kconfig                         |   10 -
+ drivers/vme/boards/Makefile                        |    6 -
+ drivers/vme/boards/vme_vmivme7805.c                |  106 --
+ drivers/vme/boards/vme_vmivme7805.h                |   33 -
+ drivers/vme/bridges/Kconfig                        |   24 -
+ drivers/vme/bridges/Makefile                       |    4 -
+ drivers/vme/bridges/vme_ca91cx42.c                 | 1928 --------------------
+ drivers/vme/bridges/vme_ca91cx42.h                 |  579 ------
+ 93 files changed, 1329 insertions(+), 3701 deletions(-)
+ delete mode 100644 drivers/staging/r8188eu/include/basic_types.h
+ create mode 100644 drivers/staging/vc04_services/interface/TESTING
+ rename drivers/{vme => staging/vme_user}/vme.c (99%)
+ rename {include/linux => drivers/staging/vme_user}/vme.h (100%)
+ rename drivers/{vme => staging/vme_user}/vme_bridge.h (99%)
+ rename drivers/{vme/bridges => staging/vme_user}/vme_fake.c (99%)
+ rename drivers/{vme/bridges => staging/vme_user}/vme_tsi148.c (99%)
+ rename drivers/{vme/bridges => staging/vme_user}/vme_tsi148.h (100%)
+ delete mode 100644 drivers/staging/vt6655/upc.h
+ delete mode 100644 drivers/vme/Kconfig
+ delete mode 100644 drivers/vme/Makefile
+ delete mode 100644 drivers/vme/boards/Kconfig
+ delete mode 100644 drivers/vme/boards/Makefile
+ delete mode 100644 drivers/vme/boards/vme_vmivme7805.c
+ delete mode 100644 drivers/vme/boards/vme_vmivme7805.h
+ delete mode 100644 drivers/vme/bridges/Kconfig
+ delete mode 100644 drivers/vme/bridges/Makefile
+ delete mode 100644 drivers/vme/bridges/vme_ca91cx42.c
+ delete mode 100644 drivers/vme/bridges/vme_ca91cx42.h
+Merging mux/for-next (0fcfb00b28c0 Linux 5.16-rc4)
+$ git merge -m Merge branch 'for-next' of https://gitlab.com/peda-linux/mux.git mux/for-next
+Already up to date.
+Merging dmaengine/next (f7a03501b090 dmaengine: stm32-mdma: Remove dead code in stm32_mdma_irq_handler())
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git dmaengine/next
+Auto-merging MAINTAINERS
+Auto-merging drivers/dma/dmatest.c
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/dma/apple,admac.yaml       |  80 ++
+ .../devicetree/bindings/dma/mediatek,uart-dma.yaml |   1 +
+ .../devicetree/bindings/dma/ste-dma40.txt          | 138 ----
+ .../devicetree/bindings/dma/stericsson,dma40.yaml  | 159 ++++
+ MAINTAINERS                                        |   6 +-
+ drivers/dma/Kconfig                                |   8 +
+ drivers/dma/Makefile                               |   1 +
+ drivers/dma/apple-admac.c                          | 818 +++++++++++++++++++++
+ drivers/dma/dmatest.c                              |  33 +-
+ drivers/dma/dw-edma/dw-edma-v0-core.c              |   8 -
+ drivers/dma/dw/rzn1-dmamux.c                       |   3 +
+ drivers/dma/stm32-mdma.c                           |   5 -
+ 12 files changed, 1091 insertions(+), 169 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/dma/apple,admac.yaml
+ delete mode 100644 Documentation/devicetree/bindings/dma/ste-dma40.txt
+ create mode 100644 Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
+ create mode 100644 drivers/dma/apple-admac.c
+Merging cgroup/for-next (507c8695c65a Merge branch 'for-5.19-fixes' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git cgroup/for-next
+Merge made by the 'ort' strategy.
+ include/linux/cgroup-defs.h |   5 ++-
+ include/linux/cgroup.h      |   2 +-
+ kernel/cgroup/cgroup.c      | 103 +++++++++++++++++++++++---------------------
+ kernel/sched/psi.c          |  19 +++++---
+ 4 files changed, 71 insertions(+), 58 deletions(-)
+Merging scsi/for-next (32ec3929dcd0 Merge branch 'misc' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git scsi/for-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/ufs/renesas,ufs.yaml       |  61 +++
+ .../bindings/ufs/samsung,exynos-ufs.yaml           |   1 +
+ MAINTAINERS                                        |   7 +
+ drivers/scsi/aic94xx/aic94xx_dev.c                 |   2 +-
+ drivers/scsi/hosts.c                               |   4 +-
+ drivers/scsi/libiscsi.c                            |  44 +-
+ drivers/scsi/libsas/sas_expander.c                 |  67 +--
+ drivers/scsi/libsas/sas_internal.h                 |   2 +-
+ drivers/scsi/lpfc/lpfc_nvmet.c                     |   6 +-
+ drivers/scsi/pm8001/pm8001_hwi.c                   |   5 +
+ drivers/scsi/pm8001/pm8001_init.c                  |  73 ++-
+ drivers/scsi/pm8001/pm8001_sas.c                   |  10 +-
+ drivers/scsi/pm8001/pm8001_sas.h                   |   3 +
+ drivers/scsi/pm8001/pm80xx_hwi.c                   |  46 +-
+ drivers/scsi/qla2xxx/qla_attr.c                    |  29 +-
+ drivers/scsi/qla2xxx/qla_bsg.c                     |  96 +++-
+ drivers/scsi/qla2xxx/qla_bsg.h                     |  15 +
+ drivers/scsi/qla2xxx/qla_dbg.h                     |   2 +-
+ drivers/scsi/qla2xxx/qla_def.h                     |  33 +-
+ drivers/scsi/qla2xxx/qla_edif.c                    | 585 ++++++++++++++-------
+ drivers/scsi/qla2xxx/qla_edif.h                    |   7 +-
+ drivers/scsi/qla2xxx/qla_edif_bsg.h                | 106 ++--
+ drivers/scsi/qla2xxx/qla_fw.h                      |   2 +-
+ drivers/scsi/qla2xxx/qla_gbl.h                     |   8 +-
+ drivers/scsi/qla2xxx/qla_gs.c                      | 120 +++--
+ drivers/scsi/qla2xxx/qla_init.c                    |  56 +-
+ drivers/scsi/qla2xxx/qla_iocb.c                    |   5 +-
+ drivers/scsi/qla2xxx/qla_isr.c                     |  58 +-
+ drivers/scsi/qla2xxx/qla_mbx.c                     |  60 ++-
+ drivers/scsi/qla2xxx/qla_mid.c                     |   6 +-
+ drivers/scsi/qla2xxx/qla_os.c                      |  93 +++-
+ drivers/scsi/qla2xxx/qla_target.c                  |  35 +-
+ drivers/scsi/qla2xxx/qla_version.h                 |   4 +-
+ drivers/scsi/scsi_transport_iscsi.c                |  10 +-
+ drivers/target/iscsi/iscsi_target_configfs.c       | 113 ++--
+ drivers/target/iscsi/iscsi_target_nego.c           | 147 ++++--
+ drivers/target/iscsi/iscsi_target_nodeattrib.c     |   1 +
+ drivers/target/iscsi/iscsi_target_tpg.c            |   3 +-
+ drivers/ufs/core/ufshcd.c                          |  19 +-
+ drivers/ufs/host/Kconfig                           |  12 +
+ drivers/ufs/host/Makefile                          |   1 +
+ drivers/ufs/host/ufs-exynos.c                      | 165 +++++-
+ drivers/ufs/host/ufs-exynos.h                      |   1 +
+ drivers/ufs/host/ufs-mediatek.c                    | 255 +++++++--
+ drivers/ufs/host/ufs-mediatek.h                    |  58 ++
+ drivers/ufs/host/ufs-renesas.c                     | 412 +++++++++++++++
+ drivers/ufs/host/ufshcd-pltfrm.c                   |   5 +-
+ drivers/ufs/host/ufshcd-pltfrm.h                   |   2 +
+ include/scsi/libsas.h                              |   2 +-
+ include/scsi/sas.h                                 |  42 +-
+ include/scsi/scsi_transport_iscsi.h                |   2 +-
+ include/target/iscsi/iscsi_target_core.h           |  14 +
+ include/ufs/ufshcd.h                               |  15 +
+ include/ufs/unipro.h                               | 104 ++--
+ 54 files changed, 2335 insertions(+), 699 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/ufs/renesas,ufs.yaml
+ create mode 100644 drivers/ufs/host/ufs-renesas.c
+Merging scsi-mkp/for-next (e34cc16a8042 scsi: MAINTAINERS: Update cxgb3i and cxgb4i maintainer)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git scsi-mkp/for-next
+Auto-merging MAINTAINERS
+Auto-merging drivers/scsi/mpt3sas/mpt3sas_base.c
+Auto-merging drivers/scsi/scsi_transport_iscsi.c
+Auto-merging drivers/scsi/snic/snic_fwint.h
+Auto-merging drivers/ufs/core/ufshcd.c
+Merge made by the 'ort' strategy.
+ MAINTAINERS                              |   4 +-
+ block/bsg.c                              |   4 +-
+ drivers/infiniband/ulp/iser/iscsi_iser.c |   4 +-
+ drivers/message/fusion/mptspi.c          |   2 +-
+ drivers/scsi/aacraid/aachba.c            |   2 +-
+ drivers/scsi/be2iscsi/be_main.c          |  21 ++-
+ drivers/scsi/bnx2i/bnx2i_iscsi.c         |   2 +-
+ drivers/scsi/cxgbi/libcxgbi.c            |   4 +-
+ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c   |   4 +-
+ drivers/scsi/iscsi_tcp.c                 |  74 ++++++---
+ drivers/scsi/iscsi_tcp.h                 |   2 +
+ drivers/scsi/libiscsi.c                  | 269 +++++++++++++++++++++----------
+ drivers/scsi/libiscsi_tcp.c              |   6 +-
+ drivers/scsi/mpt3sas/mpt3sas_base.c      |   8 +-
+ drivers/scsi/mpt3sas/mpt3sas_scsih.c     |   3 +-
+ drivers/scsi/qedi/qedi_main.c            |  11 +-
+ drivers/scsi/scsi_transport_iscsi.c      |  88 +++++++---
+ drivers/scsi/snic/snic_fwint.h           |   2 +-
+ drivers/scsi/sym53c8xx_2/sym_hipd.c      |   2 +-
+ drivers/target/target_core_alua.c        |   2 +-
+ drivers/ufs/core/ufshcd.c                |   4 +-
+ drivers/ufs/host/ufs-mediatek.c          |   4 +-
+ include/scsi/libiscsi.h                  |  13 +-
+ include/scsi/scsi_transport_iscsi.h      |   1 +
+ include/trace/events/scsi.h              |  35 ++--
+ 25 files changed, 400 insertions(+), 171 deletions(-)
+Merging vhost/linux-next (eacea844594f um: virt-pci: set device ready in probe())
+$ git merge -m Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git vhost/linux-next
+Already up to date.
+Merging rpmsg/for-next (5e579c0f98f6 Merge branches 'rproc-next' and 'rpmsg-next' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git rpmsg/for-next
+Merge made by the 'ort' strategy.
+ drivers/remoteproc/imx_rproc.c           | 7 ++++---
+ drivers/remoteproc/omap_remoteproc.c     | 6 +++---
+ drivers/remoteproc/ti_k3_r5_remoteproc.c | 2 ++
+ drivers/rpmsg/mtk_rpmsg.c                | 2 ++
+ drivers/rpmsg/rpmsg_char.c               | 7 ++++++-
+ 5 files changed, 17 insertions(+), 7 deletions(-)
+Merging gpio/for-next (7ac554888233 MAINTAINERS: Remove reference to non-existing file)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git gpio/for-next
+Already up to date.
+Merging gpio-brgl/gpio/for-next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'gpio/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio-brgl/gpio/for-next
+Already up to date.
+Merging gpio-intel/for-next (b65bb2c14891 gpio: pch: Change PCI device macros)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git gpio-intel/for-next
+Merge made by the 'ort' strategy.
+ drivers/gpio/gpio-pch.c | 43 ++++++++++++++++++-------------------------
+ 1 file changed, 18 insertions(+), 25 deletions(-)
+Merging gpio-sim/gpio/gpio-sim (0fcfb00b28c0 Linux 5.16-rc4)
+$ git merge -m Merge branch 'gpio/gpio-sim' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio-sim/gpio/gpio-sim
+Already up to date.
+Merging pinctrl/for-next (f5143c44df51 Merge branch 'devel' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git pinctrl/for-next
+Auto-merging arch/arm/boot/dts/sun6i-a31.dtsi
+Auto-merging arch/arm/boot/dts/sun8i-a23-a33.dtsi
+Merge made by the 'ort' strategy.
+ .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml       |    3 -
+ .../bindings/pinctrl/pinctrl-mt8192.yaml           |   58 +-
+ .../bindings/pinctrl/sunplus,sp7021-pinctrl.yaml   |    5 +-
+ arch/arm/boot/dts/sun6i-a31.dtsi                   |    1 -
+ arch/arm/boot/dts/sun8i-a23-a33.dtsi               |    1 -
+ arch/arm/boot/dts/sun9i-a80.dtsi                   |    1 -
+ drivers/pinctrl/aspeed/pinctrl-aspeed.c            |    4 +-
+ drivers/pinctrl/nomadik/pinctrl-nomadik.c          |    4 +-
+ drivers/pinctrl/pinctrl-amd.c                      |  103 ++
+ drivers/pinctrl/pinctrl-amd.h                      | 1376 +++++++++++++++++++-
+ drivers/pinctrl/sunxi/Kconfig                      |    3 -
+ drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c       |    1 -
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c        |    1 -
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c      |    1 -
+ drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c        |   22 +-
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c        |   25 +-
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       |    1 -
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c         |   10 +-
+ drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c        |    1 -
+ include/linux/pinctrl/pinctrl.h                    |   20 +
+ 20 files changed, 1489 insertions(+), 152 deletions(-)
+Merging pinctrl-intel/for-next (487b87717b85 pinctrl: intel: Drop no more used members of struct intel_pingroup)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git pinctrl-intel/for-next
+Merge made by the 'ort' strategy.
+ drivers/pinctrl/intel/pinctrl-baytrail.c   | 18 +++++++++---------
+ drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++--------
+ drivers/pinctrl/intel/pinctrl-intel.c      | 14 +++++++-------
+ drivers/pinctrl/intel/pinctrl-intel.h      | 25 ++++++++-----------------
+ drivers/pinctrl/intel/pinctrl-lynxpoint.c  | 10 +++++-----
+ drivers/pinctrl/intel/pinctrl-merrifield.c | 14 +++++++-------
+ 6 files changed, 44 insertions(+), 53 deletions(-)
+Merging pinctrl-renesas/renesas-pinctrl (5223c511eb4f pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabled)
+$ git merge -m Merge branch 'renesas-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git pinctrl-renesas/renesas-pinctrl
+Merge made by the 'ort' strategy.
+ drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 ++
+ 1 file changed, 2 insertions(+)
+Merging pinctrl-samsung/for-next (c98ebe065e07 pinctrl: samsung: do not use bindings header with constants)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git pinctrl-samsung/for-next
+Merge made by the 'ort' strategy.
+ drivers/pinctrl/samsung/pinctrl-exynos.c  | 6 ++----
+ drivers/pinctrl/samsung/pinctrl-exynos.h  | 3 +++
+ drivers/pinctrl/samsung/pinctrl-samsung.c | 4 +---
+ drivers/pinctrl/samsung/pinctrl-samsung.h | 8 ++++++++
+ 4 files changed, 14 insertions(+), 7 deletions(-)
+Merging pwm/for-next (394b517585da pwm: mediatek: Add MT8365 support)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git pwm/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/pwm/pwm-mediatek.txt       |  2 +
+ drivers/pwm/core.c                                 | 82 +---------------------
+ drivers/pwm/pwm-atmel-tcb.c                        |  2 +-
+ drivers/pwm/pwm-mediatek.c                         |  7 ++
+ include/linux/pwm.h                                | 35 +++------
+ 5 files changed, 21 insertions(+), 107 deletions(-)
+Merging userns/for-next (a58ea318d8b9 Merge of per-namespace-ipc-sysctls-for-v5.19, kthread-cleanups-for-v5.19, ptrace_stop-cleanup-for-v5.19, and ucount-rlimits-cleanups-for-v5.19 for testing in linux-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git userns/for-next
+Auto-merging arch/um/kernel/process.c
+Auto-merging fs/exec.c
+Auto-merging ipc/mqueue.c
+Auto-merging kernel/fork.c
+Auto-merging kernel/sys.c
+Merge made by the 'ort' strategy.
+ fs/exec.c                      |  2 +-
+ fs/proc/array.c                |  2 +-
+ include/linux/user_namespace.h | 35 ++++++++++++++++++++++-------------
+ kernel/fork.c                  | 12 ++++++------
+ kernel/sys.c                   |  2 +-
+ kernel/ucount.c                | 34 +++++++++++++++-------------------
+ kernel/user_namespace.c        | 10 +++++-----
+ 7 files changed, 51 insertions(+), 46 deletions(-)
+Merging ktest/for-next (170f4869e662 ktest.pl: Fix the logic for truncating the size of the log file for email)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-ktest.git ktest/for-next
+Already up to date.
+Merging kselftest/next (cb6849a14c90 userfaultfd/selftests: Fix typo in comment)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kselftest/next
+Merge made by the 'ort' strategy.
+ tools/testing/selftests/vm/userfaultfd.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging livepatching/for-next (df44b1ee72f4 Merge branch 'for-5.20/selftests-fixes' into for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching livepatching/for-next
+Merge made by the 'ort' strategy.
+ lib/livepatch/test_klp_callbacks_busy.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+Merging rtc/rtc-next (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'rtc-next' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc/rtc-next
+Already up to date.
+Merging nvdimm/libnvdimm-for-next (f42e8e5088b9 pmem: implement pmem_recovery_write())
+$ git merge -m Merge branch 'libnvdimm-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git nvdimm/libnvdimm-for-next
+Already up to date.
+Merging at24/at24/for-next (312310928417 Linux 5.18-rc1)
+$ git merge -m Merge branch 'at24/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git at24/at24/for-next
+Already up to date.
+Merging ntb/ntb-next (0c4b285d9636 Documentation: PCI: Add specification for the PCI vNTB function device)
+$ git merge -m Merge branch 'ntb-next' of https://github.com/jonmason/ntb.git ntb/ntb-next
+Merge made by the 'ort' strategy.
+ Documentation/PCI/endpoint/index.rst             |    2 +
+ Documentation/PCI/endpoint/pci-vntb-function.rst |  126 ++
+ Documentation/PCI/endpoint/pci-vntb-howto.rst    |  161 +++
+ drivers/ntb/hw/epf/ntb_hw_epf.c                  |   48 +-
+ drivers/ntb/test/ntb_perf.c                      |  826 ++++++++++++-
+ drivers/pci/controller/dwc/pcie-designware-ep.c  |   10 +-
+ drivers/pci/endpoint/functions/Kconfig           |   11 +
+ drivers/pci/endpoint/functions/Makefile          |    1 +
+ drivers/pci/endpoint/functions/pci-epf-vntb.c    | 1425 ++++++++++++++++++++++
+ 9 files changed, 2580 insertions(+), 30 deletions(-)
+ create mode 100644 Documentation/PCI/endpoint/pci-vntb-function.rst
+ create mode 100644 Documentation/PCI/endpoint/pci-vntb-howto.rst
+ create mode 100644 drivers/pci/endpoint/functions/pci-epf-vntb.c
+Merging seccomp/for-next/seccomp (73a8dbafd31a selftests/seccomp: Fix compile warning when CC=clang)
+$ git merge -m Merge branch 'for-next/seccomp' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git seccomp/for-next/seccomp
+Merge made by the 'ort' strategy.
+ tools/testing/selftests/seccomp/seccomp_bpf.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging cisco/for-next (9e98c678c2d6 Linux 5.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://github.com/daniel-walker/cisco-linux.git cisco/for-next
+Already up to date.
+Merging fsi/next (f2af60bb7ce2 fsi: Add trace events in initialization path)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/fsi.git fsi/next
+Already up to date.
+Merging slimbus/for-next (4ad3deabeea2 slimbus: messaging: fix typos in comments)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/srini/slimbus.git slimbus/for-next
+Merge made by the 'ort' strategy.
+ drivers/slimbus/core.c      | 6 +++---
+ drivers/slimbus/messaging.c | 4 ++--
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+Merging nvmem/for-next (ccba200e4801 dt-bindings: nvmem: mediatek: efuse: add support mt8183)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/srini/nvmem.git nvmem/for-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/nvmem/mediatek,efuse.yaml  |  88 +++++++
+ .../bindings/nvmem/microchip,sama7g5-otpc.yaml     |  50 ++++
+ .../devicetree/bindings/nvmem/mtk-efuse.txt        |  43 ---
+ MAINTAINERS                                        |   8 +
+ drivers/nvmem/Kconfig                              |   7 +
+ drivers/nvmem/Makefile                             |   2 +
+ drivers/nvmem/microchip-otpc.c                     | 288 +++++++++++++++++++++
+ include/dt-bindings/nvmem/microchip,sama7g5-otpc.h |  12 +
+ 8 files changed, 455 insertions(+), 43 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+ create mode 100644 Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+ delete mode 100644 Documentation/devicetree/bindings/nvmem/mtk-efuse.txt
+ create mode 100644 drivers/nvmem/microchip-otpc.c
+ create mode 100644 include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
+Merging xarray/main (63b1898fffcd XArray: Disallow sibling entries of nodes)
+$ git merge -m Merge branch 'main' of git://git.infradead.org/users/willy/xarray.git xarray/main
+Already up to date.
+Merging hyperv/hyperv-next (d27423bf048d hv_balloon: Fix balloon_probe() and balloon_remove() error handling)
+$ git merge -m Merge branch 'hyperv-next' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git hyperv/hyperv-next
+Already up to date.
+Merging auxdisplay/auxdisplay (13de23494f38 auxdisplay: lcd2s: Use array size explicitly in lcd2s_gotoxy())
+$ git merge -m Merge branch 'auxdisplay' of https://github.com/ojeda/linux.git auxdisplay/auxdisplay
+Already up to date.
+Merging kgdb/kgdb/for-next (c1cb81429df4 kdb: Fix the putarea helper function)
+$ git merge -m Merge branch 'kgdb/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/danielt/linux.git kgdb/kgdb/for-next
+Already up to date.
+Merging hmm/hmm (457c42326fb9 RDMA/erdma: Add driver to kernel build environment)
+$ git merge -m Merge branch 'hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git hmm/hmm
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS                               |    8 +
+ drivers/infiniband/Kconfig                |   15 +-
+ drivers/infiniband/hw/Makefile            |    1 +
+ drivers/infiniband/hw/erdma/Kconfig       |   12 +
+ drivers/infiniband/hw/erdma/Makefile      |    4 +
+ drivers/infiniband/hw/erdma/erdma.h       |  287 ++++++
+ drivers/infiniband/hw/erdma/erdma_cm.c    | 1430 ++++++++++++++++++++++++++++
+ drivers/infiniband/hw/erdma/erdma_cm.h    |  167 ++++
+ drivers/infiniband/hw/erdma/erdma_cmdq.c  |  497 ++++++++++
+ drivers/infiniband/hw/erdma/erdma_cq.c    |  205 ++++
+ drivers/infiniband/hw/erdma/erdma_eq.c    |  329 +++++++
+ drivers/infiniband/hw/erdma/erdma_hw.h    |  508 ++++++++++
+ drivers/infiniband/hw/erdma/erdma_main.c  |  628 ++++++++++++
+ drivers/infiniband/hw/erdma/erdma_qp.c    |  566 +++++++++++
+ drivers/infiniband/hw/erdma/erdma_verbs.c | 1466 +++++++++++++++++++++++++++++
+ drivers/infiniband/hw/erdma/erdma_verbs.h |  342 +++++++
+ include/uapi/rdma/erdma-abi.h             |   49 +
+ include/uapi/rdma/ib_user_ioctl_verbs.h   |    1 +
+ 18 files changed, 6508 insertions(+), 7 deletions(-)
+ create mode 100644 drivers/infiniband/hw/erdma/Kconfig
+ create mode 100644 drivers/infiniband/hw/erdma/Makefile
+ create mode 100644 drivers/infiniband/hw/erdma/erdma.h
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_cm.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_cm.h
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_cmdq.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_cq.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_eq.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_hw.h
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_main.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_qp.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_verbs.c
+ create mode 100644 drivers/infiniband/hw/erdma/erdma_verbs.h
+ create mode 100644 include/uapi/rdma/erdma-abi.h
+Merging kunit/test (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'test' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit/test
+Already up to date.
+Merging cfi/cfi/next (312310928417 Linux 5.18-rc1)
+$ git merge -m Merge branch 'cfi/next' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git cfi/cfi/next
+Already up to date.
+Merging kunit-next/kunit (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'kunit' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit-next/kunit
+Already up to date.
+Merging trivial/for-next (081c8919b02b Documentation: remove trivial tree)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial.git trivial/for-next
+Already up to date.
+Merging mhi/mhi-next (b7ce71625431 bus: mhi: host: pci_generic: Add Cinterion MV31-W with new baseline)
+$ git merge -m Merge branch 'mhi-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi.git mhi/mhi-next
+Merge made by the 'ort' strategy.
+ drivers/bus/mhi/host/pci_generic.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+Merging memblock/for-next (000605cd1b14 memblock tests: remove completed TODO item)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git memblock/for-next
+Already up to date.
+Merging init/init-user-pointers (38b082236e77 initramfs: use vfs_utimes in do_copy)
+$ git merge -m Merge branch 'init-user-pointers' of git://git.infradead.org/users/hch/misc.git init/init-user-pointers
+Already up to date.
+Merging counters/counters (e71ba9452f0b Linux 5.11-rc2)
+$ git merge -m Merge branch 'counters' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git counters/counters
+Already up to date.
+Merging cxl/next (34e37b4c432c cxl/port: Enable HDM Capability after validating DVSEC Ranges)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl/next
+Already up to date.
+Merging folio-iomap/folio-iomap (4d7bd0eb72e5 iomap: Inline __iomap_zero_iter into its caller)
+$ git merge -m Merge branch 'folio-iomap' of git://git.infradead.org/users/willy/linux.git folio-iomap/folio-iomap
+Already up to date.
+Merging zstd/zstd-next (88a309465b3f lib: zstd: clean up double word in comment.)
+$ git merge -m Merge branch 'zstd-next' of https://github.com/terrelln/linux.git zstd/zstd-next
+Already up to date.
+Merging efi/next (98e152c19b66 brcmfmac: Switch to appropriate helper to load EFI variable contents)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git efi/next
+Auto-merging arch/x86/include/asm/efi.h
+Auto-merging mm/sparse-vmemmap.c
+Merge made by the 'ort' strategy.
+ arch/arm64/mm/init.c                               |   2 +-
+ arch/x86/include/asm/efi.h                         |   4 -
+ arch/x86/platform/efi/efi.c                        |  23 ----
+ drivers/firmware/efi/Kconfig                       |   1 +
+ drivers/firmware/efi/efi-init.c                    |   1 +
+ drivers/firmware/efi/efi.c                         | 126 +++++++++++----------
+ drivers/firmware/efi/efibc.c                       |  76 +++++--------
+ drivers/firmware/efi/memmap.c                      |   3 +-
+ .../broadcom/brcm80211/brcmfmac/firmware.c         |  25 ++--
+ drivers/net/wireless/intel/iwlwifi/fw/uefi.c       |  96 ++++++----------
+ .../media/atomisp/pci/atomisp_gmin_platform.c      |  27 +----
+ include/linux/efi.h                                |   3 +
+ mm/internal.h                                      |   2 +
+ mm/memblock.c                                      |   7 +-
+ mm/page_alloc.c                                    |   2 +-
+ mm/sparse-vmemmap.c                                |   2 +-
+ 16 files changed, 155 insertions(+), 245 deletions(-)
+Merging unicode/for-next (b500d6d7243d unicode: Handle memory allocation failures in mkutf8data)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/krisman/unicode.git unicode/for-next
+Merge made by the 'ort' strategy.
+ fs/unicode/mkutf8data.c | 38 ++++++++++++++++++++++++--------------
+ 1 file changed, 24 insertions(+), 14 deletions(-)
+Merging slab/for-next (c01651bc1ae4 Merge branches 'slab/for-5.20/trivial', 'slab/for-5.20/cleanup', 'slab/for-5.20/tracing' and 'slab/for-5.20/optimizations' into slab/for-next)
+$ git merge -m Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git slab/for-next
+Merge made by the 'ort' strategy.
+ include/trace/events/kmem.h | 40 ++++++++++++-------
+ mm/slab.c                   | 28 +++++---------
+ mm/slab.h                   | 30 ++++-----------
+ mm/slab_common.c            |  9 ++---
+ mm/slob.c                   |  8 ++--
+ mm/slub.c                   | 94 +++++++++++++++++----------------------------
+ 6 files changed, 86 insertions(+), 123 deletions(-)
+Merging random/master (63b8ea5e4f1a random: update comment from copy_to_user() -> copy_to_iter())
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git random/master
+Merge made by the 'ort' strategy.
+ drivers/char/random.c           |  6 +++---
+ include/linux/ratelimit_types.h | 12 ++++++++----
+ 2 files changed, 11 insertions(+), 7 deletions(-)
+Merging landlock/next (b13baccc3850 Linux 5.19-rc2)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/mic/linux.git landlock/next
+Already up to date.
+Merging rust/rust-next (9a5fe747d99e init/Kconfig: Specify the interpreter for rust-is-available.sh)
+$ git merge -m Merge branch 'rust-next' of https://github.com/Rust-for-Linux/linux.git rust/rust-next
+Auto-merging .gitignore
+Auto-merging Documentation/doc-guide/kernel-doc.rst
+Auto-merging Documentation/index.rst
+Auto-merging Documentation/process/changes.rst
+Auto-merging MAINTAINERS
+Auto-merging Makefile
+CONFLICT (content): Merge conflict in Makefile
+Auto-merging arch/Kconfig
+Auto-merging arch/arm/Kconfig
+Auto-merging arch/arm64/Kconfig
+Auto-merging arch/powerpc/Kconfig
+Auto-merging arch/riscv/Kconfig
+Auto-merging arch/riscv/Makefile
+Auto-merging arch/um/Kconfig
+Auto-merging arch/x86/Kconfig
+Auto-merging arch/x86/Makefile
+Auto-merging drivers/gpio/Kconfig
+Auto-merging include/kunit/test.h
+Auto-merging include/linux/kallsyms.h
+Auto-merging include/uapi/linux/android/binder.h
+CONFLICT (content): Merge conflict in include/uapi/linux/android/binder.h
+Auto-merging init/Kconfig
+Auto-merging kernel/kallsyms.c
+Auto-merging lib/Kconfig.debug
+Auto-merging lib/kunit/test.c
+Auto-merging lib/vsprintf.c
+Auto-merging scripts/Makefile
+Auto-merging scripts/Makefile.build
+Auto-merging scripts/Makefile.lib
+Auto-merging scripts/Makefile.modfinal
+Auto-merging scripts/checkpatch.pl
+Auto-merging scripts/decode_stacktrace.sh
+Auto-merging scripts/kallsyms.c
+Auto-merging scripts/min-tool-version.sh
+Resolved 'Makefile' using previous resolution.
+Resolved 'include/uapi/linux/android/binder.h' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master a7ad421b47e6] Merge branch 'rust-next' of https://github.com/Rust-for-Linux/linux.git
+$ git diff -M --stat --summary HEAD^..
+ .gitignore                                   |    5 +
+ .rustfmt.toml                                |   12 +
+ Documentation/core-api/printk-formats.rst    |   10 +
+ Documentation/doc-guide/kernel-doc.rst       |    3 +
+ Documentation/index.rst                      |    1 +
+ Documentation/kbuild/kbuild.rst              |   17 +
+ Documentation/kbuild/makefiles.rst           |   50 +-
+ Documentation/process/changes.rst            |   41 +
+ Documentation/rust/arch-support.rst          |   25 +
+ Documentation/rust/coding-guidelines.rst     |  216 ++
+ Documentation/rust/general-information.rst   |   79 +
+ Documentation/rust/index.rst                 |   22 +
+ Documentation/rust/quick-start.rst           |  232 ++
+ MAINTAINERS                                  |   15 +
+ Makefile                                     |  177 +-
+ arch/Kconfig                                 |    6 +
+ arch/arm/Kconfig                             |    1 +
+ arch/arm64/Kconfig                           |    1 +
+ arch/powerpc/Kconfig                         |    1 +
+ arch/riscv/Kconfig                           |    1 +
+ arch/riscv/Makefile                          |    5 +
+ arch/um/Kconfig                              |    1 +
+ arch/x86/Kconfig                             |    1 +
+ arch/x86/Makefile                            |   14 +
+ drivers/android/Kconfig                      |    6 +
+ drivers/android/Makefile                     |    2 +
+ drivers/android/allocation.rs                |  266 ++
+ drivers/android/context.rs                   |   80 +
+ drivers/android/defs.rs                      |   99 +
+ drivers/android/node.rs                      |  476 ++++
+ drivers/android/process.rs                   |  960 ++++++++
+ drivers/android/range_alloc.rs               |  189 ++
+ drivers/android/rust_binder.rs               |  111 +
+ drivers/android/thread.rs                    |  870 +++++++
+ drivers/android/transaction.rs               |  326 +++
+ drivers/gpio/Kconfig                         |    8 +
+ drivers/gpio/Makefile                        |    1 +
+ drivers/gpio/gpio_pl061_rust.rs              |  370 +++
+ include/linux/kallsyms.h                     |    2 +-
+ include/linux/spinlock.h                     |   25 +-
+ include/uapi/linux/android/binder.h          |   30 +-
+ init/Kconfig                                 |   51 +-
+ kernel/kallsyms.c                            |   26 +-
+ kernel/livepatch/core.c                      |    4 +-
+ lib/Kconfig.debug                            |  155 ++
+ lib/vsprintf.c                               |   13 +
+ rust/.gitignore                              |   10 +
+ rust/Makefile                                |  398 +++
+ rust/alloc/README.md                         |   33 +
+ rust/alloc/alloc.rs                          |  438 ++++
+ rust/alloc/borrow.rs                         |  498 ++++
+ rust/alloc/boxed.rs                          | 2007 +++++++++++++++
+ rust/alloc/collections/mod.rs                |  156 ++
+ rust/alloc/fmt.rs                            |  601 +++++
+ rust/alloc/lib.rs                            |  226 ++
+ rust/alloc/macros.rs                         |  127 +
+ rust/alloc/raw_vec.rs                        |  567 +++++
+ rust/alloc/slice.rs                          | 1282 ++++++++++
+ rust/alloc/str.rs                            |  632 +++++
+ rust/alloc/string.rs                         | 2869 ++++++++++++++++++++++
+ rust/alloc/vec/drain.rs                      |  186 ++
+ rust/alloc/vec/drain_filter.rs               |  145 ++
+ rust/alloc/vec/into_iter.rs                  |  356 +++
+ rust/alloc/vec/is_zero.rs                    |  106 +
+ rust/alloc/vec/mod.rs                        | 3362 ++++++++++++++++++++++++++
+ rust/alloc/vec/partial_eq.rs                 |   49 +
+ rust/alloc/vec/set_len_on_drop.rs            |   30 +
+ rust/alloc/vec/spec_extend.rs                |  174 ++
+ rust/bindgen_parameters                      |   17 +
+ rust/build_error.rs                          |   29 +
+ rust/compiler_builtins.rs                    |   57 +
+ rust/exports.c                               |   20 +
+ rust/helpers.c                               |  644 +++++
+ rust/kernel/allocator.rs                     |   65 +
+ rust/kernel/amba.rs                          |  257 ++
+ rust/kernel/bindings.rs                      |   47 +
+ rust/kernel/bindings_helper.h                |   46 +
+ rust/kernel/build_assert.rs                  |   82 +
+ rust/kernel/c_types.rs                       |  119 +
+ rust/kernel/chrdev.rs                        |  207 ++
+ rust/kernel/clk.rs                           |   79 +
+ rust/kernel/cred.rs                          |   46 +
+ rust/kernel/device.rs                        |  546 +++++
+ rust/kernel/driver.rs                        |  442 ++++
+ rust/kernel/error.rs                         |  565 +++++
+ rust/kernel/file.rs                          |  860 +++++++
+ rust/kernel/gpio.rs                          |  478 ++++
+ rust/kernel/hwrng.rs                         |  242 ++
+ rust/kernel/io_buffer.rs                     |  153 ++
+ rust/kernel/io_mem.rs                        |  275 +++
+ rust/kernel/iov_iter.rs                      |   81 +
+ rust/kernel/irq.rs                           |  411 ++++
+ rust/kernel/kasync.rs                        |    6 +
+ rust/kernel/kasync/net.rs                    |  322 +++
+ rust/kernel/kunit.rs                         |   91 +
+ rust/kernel/lib.rs                           |  261 ++
+ rust/kernel/linked_list.rs                   |  247 ++
+ rust/kernel/miscdev.rs                       |  291 +++
+ rust/kernel/mm.rs                            |  149 ++
+ rust/kernel/module_param.rs                  |  498 ++++
+ rust/kernel/net.rs                           |  392 +++
+ rust/kernel/net/filter.rs                    |  447 ++++
+ rust/kernel/of.rs                            |   63 +
+ rust/kernel/pages.rs                         |  144 ++
+ rust/kernel/platform.rs                      |  223 ++
+ rust/kernel/power.rs                         |  118 +
+ rust/kernel/prelude.rs                       |   36 +
+ rust/kernel/print.rs                         |  405 ++++
+ rust/kernel/random.rs                        |   42 +
+ rust/kernel/raw_list.rs                      |  361 +++
+ rust/kernel/rbtree.rs                        |  563 +++++
+ rust/kernel/revocable.rs                     |  161 ++
+ rust/kernel/security.rs                      |   38 +
+ rust/kernel/static_assert.rs                 |   38 +
+ rust/kernel/std_vendor.rs                    |  160 ++
+ rust/kernel/str.rs                           |  597 +++++
+ rust/kernel/sync.rs                          |  161 ++
+ rust/kernel/sync/arc.rs                      |  503 ++++
+ rust/kernel/sync/condvar.rs                  |  138 ++
+ rust/kernel/sync/guard.rs                    |  169 ++
+ rust/kernel/sync/locked_by.rs                |  111 +
+ rust/kernel/sync/mutex.rs                    |  153 ++
+ rust/kernel/sync/nowait.rs                   |  188 ++
+ rust/kernel/sync/revocable.rs                |  250 ++
+ rust/kernel/sync/rwsem.rs                    |  197 ++
+ rust/kernel/sync/seqlock.rs                  |  202 ++
+ rust/kernel/sync/smutex.rs                   |  295 +++
+ rust/kernel/sync/spinlock.rs                 |  360 +++
+ rust/kernel/sysctl.rs                        |  199 ++
+ rust/kernel/task.rs                          |  175 ++
+ rust/kernel/types.rs                         |  679 ++++++
+ rust/kernel/user_ptr.rs                      |  175 ++
+ rust/macros/helpers.rs                       |   79 +
+ rust/macros/lib.rs                           |   94 +
+ rust/macros/module.rs                        |  631 +++++
+ samples/Kconfig                              |    2 +
+ samples/Makefile                             |    1 +
+ samples/rust/Kconfig                         |  140 ++
+ samples/rust/Makefile                        |   16 +
+ samples/rust/hostprogs/.gitignore            |    3 +
+ samples/rust/hostprogs/Makefile              |    5 +
+ samples/rust/hostprogs/a.rs                  |    7 +
+ samples/rust/hostprogs/b.rs                  |    5 +
+ samples/rust/hostprogs/single.rs             |   12 +
+ samples/rust/rust_chrdev.rs                  |   50 +
+ samples/rust/rust_minimal.rs                 |   35 +
+ samples/rust/rust_miscdev.rs                 |  143 ++
+ samples/rust/rust_module_parameters.rs       |   69 +
+ samples/rust/rust_netfilter.rs               |   54 +
+ samples/rust/rust_platform.rs                |   22 +
+ samples/rust/rust_print.rs                   |   54 +
+ samples/rust/rust_random.rs                  |   60 +
+ samples/rust/rust_semaphore.rs               |  171 ++
+ samples/rust/rust_semaphore_c.c              |  212 ++
+ samples/rust/rust_stack_probing.rs           |   36 +
+ samples/rust/rust_sync.rs                    |   93 +
+ scripts/.gitignore                           |    1 +
+ scripts/Kconfig.include                      |    6 +-
+ scripts/Makefile                             |    3 +
+ scripts/Makefile.build                       |   60 +
+ scripts/Makefile.debug                       |   10 +
+ scripts/Makefile.host                        |   34 +-
+ scripts/Makefile.lib                         |   12 +
+ scripts/Makefile.modfinal                    |    8 +-
+ scripts/cc-version.sh                        |   12 +-
+ scripts/checkpatch.pl                        |    8 +-
+ scripts/decode_stacktrace.sh                 |   14 +
+ scripts/generate_rust_analyzer.py            |  134 +
+ scripts/generate_rust_target.rs              |  227 ++
+ scripts/is_rust_module.sh                    |   13 +
+ scripts/kallsyms.c                           |   47 +-
+ scripts/kconfig/confdata.c                   |   75 +
+ scripts/min-tool-version.sh                  |    6 +
+ scripts/rust-is-available-bindgen-libclang.h |    2 +
+ scripts/rust-is-available.sh                 |  158 ++
+ scripts/rustdoc_test_builder.py              |   59 +
+ scripts/rustdoc_test_gen.py                  |  164 ++
+ tools/include/linux/kallsyms.h               |    2 +-
+ tools/lib/perf/include/perf/event.h          |    2 +-
+ tools/lib/symbol/kallsyms.h                  |    2 +-
+ 180 files changed, 37619 insertions(+), 68 deletions(-)
+ create mode 100644 .rustfmt.toml
+ create mode 100644 Documentation/rust/arch-support.rst
+ create mode 100644 Documentation/rust/coding-guidelines.rst
+ create mode 100644 Documentation/rust/general-information.rst
+ create mode 100644 Documentation/rust/index.rst
+ create mode 100644 Documentation/rust/quick-start.rst
+ create mode 100644 drivers/android/allocation.rs
+ create mode 100644 drivers/android/context.rs
+ create mode 100644 drivers/android/defs.rs
+ create mode 100644 drivers/android/node.rs
+ create mode 100644 drivers/android/process.rs
+ create mode 100644 drivers/android/range_alloc.rs
+ create mode 100644 drivers/android/rust_binder.rs
+ create mode 100644 drivers/android/thread.rs
+ create mode 100644 drivers/android/transaction.rs
+ create mode 100644 drivers/gpio/gpio_pl061_rust.rs
+ create mode 100644 rust/.gitignore
+ create mode 100644 rust/Makefile
+ create mode 100644 rust/alloc/README.md
+ create mode 100644 rust/alloc/alloc.rs
+ create mode 100644 rust/alloc/borrow.rs
+ create mode 100644 rust/alloc/boxed.rs
+ create mode 100644 rust/alloc/collections/mod.rs
+ create mode 100644 rust/alloc/fmt.rs
+ create mode 100644 rust/alloc/lib.rs
+ create mode 100644 rust/alloc/macros.rs
+ create mode 100644 rust/alloc/raw_vec.rs
+ create mode 100644 rust/alloc/slice.rs
+ create mode 100644 rust/alloc/str.rs
+ create mode 100644 rust/alloc/string.rs
+ create mode 100644 rust/alloc/vec/drain.rs
+ create mode 100644 rust/alloc/vec/drain_filter.rs
+ create mode 100644 rust/alloc/vec/into_iter.rs
+ create mode 100644 rust/alloc/vec/is_zero.rs
+ create mode 100644 rust/alloc/vec/mod.rs
+ create mode 100644 rust/alloc/vec/partial_eq.rs
+ create mode 100644 rust/alloc/vec/set_len_on_drop.rs
+ create mode 100644 rust/alloc/vec/spec_extend.rs
+ create mode 100644 rust/bindgen_parameters
+ create mode 100644 rust/build_error.rs
+ create mode 100644 rust/compiler_builtins.rs
+ create mode 100644 rust/exports.c
+ create mode 100644 rust/helpers.c
+ create mode 100644 rust/kernel/allocator.rs
+ create mode 100644 rust/kernel/amba.rs
+ create mode 100644 rust/kernel/bindings.rs
+ create mode 100644 rust/kernel/bindings_helper.h
+ create mode 100644 rust/kernel/build_assert.rs
+ create mode 100644 rust/kernel/c_types.rs
+ create mode 100644 rust/kernel/chrdev.rs
+ create mode 100644 rust/kernel/clk.rs
+ create mode 100644 rust/kernel/cred.rs
+ create mode 100644 rust/kernel/device.rs
+ create mode 100644 rust/kernel/driver.rs
+ create mode 100644 rust/kernel/error.rs
+ create mode 100644 rust/kernel/file.rs
+ create mode 100644 rust/kernel/gpio.rs
+ create mode 100644 rust/kernel/hwrng.rs
+ create mode 100644 rust/kernel/io_buffer.rs
+ create mode 100644 rust/kernel/io_mem.rs
+ create mode 100644 rust/kernel/iov_iter.rs
+ create mode 100644 rust/kernel/irq.rs
+ create mode 100644 rust/kernel/kasync.rs
+ create mode 100644 rust/kernel/kasync/net.rs
+ create mode 100644 rust/kernel/kunit.rs
+ create mode 100644 rust/kernel/lib.rs
+ create mode 100644 rust/kernel/linked_list.rs
+ create mode 100644 rust/kernel/miscdev.rs
+ create mode 100644 rust/kernel/mm.rs
+ create mode 100644 rust/kernel/module_param.rs
+ create mode 100644 rust/kernel/net.rs
+ create mode 100644 rust/kernel/net/filter.rs
+ create mode 100644 rust/kernel/of.rs
+ create mode 100644 rust/kernel/pages.rs
+ create mode 100644 rust/kernel/platform.rs
+ create mode 100644 rust/kernel/power.rs
+ create mode 100644 rust/kernel/prelude.rs
+ create mode 100644 rust/kernel/print.rs
+ create mode 100644 rust/kernel/random.rs
+ create mode 100644 rust/kernel/raw_list.rs
+ create mode 100644 rust/kernel/rbtree.rs
+ create mode 100644 rust/kernel/revocable.rs
+ create mode 100644 rust/kernel/security.rs
+ create mode 100644 rust/kernel/static_assert.rs
+ create mode 100644 rust/kernel/std_vendor.rs
+ create mode 100644 rust/kernel/str.rs
+ create mode 100644 rust/kernel/sync.rs
+ create mode 100644 rust/kernel/sync/arc.rs
+ create mode 100644 rust/kernel/sync/condvar.rs
+ create mode 100644 rust/kernel/sync/guard.rs
+ create mode 100644 rust/kernel/sync/locked_by.rs
+ create mode 100644 rust/kernel/sync/mutex.rs
+ create mode 100644 rust/kernel/sync/nowait.rs
+ create mode 100644 rust/kernel/sync/revocable.rs
+ create mode 100644 rust/kernel/sync/rwsem.rs
+ create mode 100644 rust/kernel/sync/seqlock.rs
+ create mode 100644 rust/kernel/sync/smutex.rs
+ create mode 100644 rust/kernel/sync/spinlock.rs
+ create mode 100644 rust/kernel/sysctl.rs
+ create mode 100644 rust/kernel/task.rs
+ create mode 100644 rust/kernel/types.rs
+ create mode 100644 rust/kernel/user_ptr.rs
+ create mode 100644 rust/macros/helpers.rs
+ create mode 100644 rust/macros/lib.rs
+ create mode 100644 rust/macros/module.rs
+ create mode 100644 samples/rust/Kconfig
+ create mode 100644 samples/rust/Makefile
+ create mode 100644 samples/rust/hostprogs/.gitignore
+ create mode 100644 samples/rust/hostprogs/Makefile
+ create mode 100644 samples/rust/hostprogs/a.rs
+ create mode 100644 samples/rust/hostprogs/b.rs
+ create mode 100644 samples/rust/hostprogs/single.rs
+ create mode 100644 samples/rust/rust_chrdev.rs
+ create mode 100644 samples/rust/rust_minimal.rs
+ create mode 100644 samples/rust/rust_miscdev.rs
+ create mode 100644 samples/rust/rust_module_parameters.rs
+ create mode 100644 samples/rust/rust_netfilter.rs
+ create mode 100644 samples/rust/rust_platform.rs
+ create mode 100644 samples/rust/rust_print.rs
+ create mode 100644 samples/rust/rust_random.rs
+ create mode 100644 samples/rust/rust_semaphore.rs
+ create mode 100644 samples/rust/rust_semaphore_c.c
+ create mode 100644 samples/rust/rust_stack_probing.rs
+ create mode 100644 samples/rust/rust_sync.rs
+ create mode 100755 scripts/generate_rust_analyzer.py
+ create mode 100644 scripts/generate_rust_target.rs
+ create mode 100755 scripts/is_rust_module.sh
+ create mode 100644 scripts/rust-is-available-bindgen-libclang.h
+ create mode 100755 scripts/rust-is-available.sh
+ create mode 100755 scripts/rustdoc_test_builder.py
+ create mode 100755 scripts/rustdoc_test_gen.py
+Merging sysctl/sysctl-next (acdc07ace871 kernel/sysctl.c: Clean up indentation, replace spaces with tab.)
+$ git merge -m Merge branch 'sysctl-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git sysctl/sysctl-next
+Merge made by the 'ort' strategy.
+ kernel/sysctl.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+Merging folio/for-next (e0183897944e fs: remove the NULL get_block case in mpage_writepages)
+$ git merge -m Merge branch 'for-next' of git://git.infradead.org/users/willy/pagecache.git folio/for-next
+Auto-merging block/fops.c
+Auto-merging fs/btrfs/disk-io.c
+Auto-merging fs/btrfs/inode.c
+Auto-merging fs/f2fs/node.c
+Auto-merging fs/hugetlbfs/inode.c
+Auto-merging fs/iomap/buffered-io.c
+Auto-merging fs/ntfs3/inode.c
+Auto-merging include/linux/fs.h
+Auto-merging mm/secretmem.c
+Auto-merging mm/swap.c
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/cgroup-v1/memcg_test.rst |   2 +-
+ Documentation/filesystems/ext2.rst                 |   2 -
+ Documentation/filesystems/locking.rst              |   9 +-
+ Documentation/filesystems/vfs.rst                  |  65 ++--
+ Documentation/vm/page_migration.rst                | 113 +------
+ arch/powerpc/platforms/pseries/cmm.c               |  60 +---
+ block/fops.c                                       |   2 +-
+ block/partitions/check.h                           |   4 +-
+ block/partitions/core.c                            |  20 +-
+ drivers/gpu/drm/i915/gem/i915_gem_userptr.c        |   4 +-
+ drivers/misc/vmw_balloon.c                         |  61 +---
+ drivers/virtio/virtio_balloon.c                    |  47 +--
+ fs/afs/mntpt.c                                     |   6 -
+ fs/aio.c                                           |  36 +-
+ fs/befs/linuxvfs.c                                 |  16 +-
+ fs/btrfs/disk-io.c                                 |  41 +--
+ fs/btrfs/inode.c                                   |  26 +-
+ fs/buffer.c                                        | 363 ++-------------------
+ fs/coda/symlink.c                                  |  11 +-
+ fs/cramfs/inode.c                                  |  17 +-
+ fs/ext2/dir.c                                      |  20 +-
+ fs/ext2/ext2.h                                     |   1 -
+ fs/ext2/inode.c                                    |  53 +--
+ fs/ext2/namei.c                                    |  10 +-
+ fs/ext2/super.c                                    |   6 +-
+ fs/ext4/inode.c                                    |  44 +--
+ fs/f2fs/checkpoint.c                               |   4 +-
+ fs/f2fs/compress.c                                 |  35 +-
+ fs/f2fs/data.c                                     |  40 +--
+ fs/f2fs/f2fs.h                                     |   4 -
+ fs/f2fs/node.c                                     |   4 +-
+ fs/freevxfs/vxfs_immed.c                           |  43 ++-
+ fs/freevxfs/vxfs_subr.c                            |   6 -
+ fs/gfs2/aops.c                                     |   2 +-
+ fs/gfs2/lops.c                                     |  28 +-
+ fs/hfs/bnode.c                                     |   4 -
+ fs/hfsplus/bnode.c                                 |   4 -
+ fs/hostfs/hostfs_kern.c                            |   6 +-
+ fs/hugetlbfs/inode.c                               |  69 ++--
+ fs/iomap/buffered-io.c                             |  28 --
+ fs/jfs/inode.c                                     |  18 +-
+ fs/jfs/jfs_metapage.c                              |   2 +-
+ fs/mpage.c                                         | 124 +++----
+ fs/nfs/file.c                                      |   4 +-
+ fs/nfs/internal.h                                  |   6 +-
+ fs/nfs/read.c                                      |   4 -
+ fs/nfs/write.c                                     |  16 +-
+ fs/nilfs2/dir.c                                    |   2 +-
+ fs/nilfs2/page.c                                   |  60 ++--
+ fs/ntfs/aops.c                                     |   6 +-
+ fs/ntfs/aops.h                                     |   7 +-
+ fs/ntfs/file.c                                     |   5 -
+ fs/ntfs3/inode.c                                   |   8 +-
+ fs/ntfs3/ntfs_fs.h                                 |   7 +-
+ fs/ocfs2/aops.c                                    |  28 +-
+ fs/ocfs2/refcounttree.c                            |  42 +--
+ fs/orangefs/inode.c                                |   4 +-
+ fs/reiserfs/xattr.c                                |   9 +-
+ fs/remap_range.c                                   |  11 +-
+ fs/squashfs/file.c                                 |  15 +-
+ fs/ubifs/file.c                                    |  29 +-
+ fs/ufs/dir.c                                       |   2 +-
+ fs/ufs/util.c                                      |  11 -
+ fs/xfs/xfs_aops.c                                  |   2 +-
+ fs/zonefs/super.c                                  |   2 +-
+ include/linux/balloon_compaction.h                 |   6 +-
+ include/linux/buffer_head.h                        |  18 +-
+ include/linux/fs.h                                 |  20 +-
+ include/linux/iomap.h                              |   6 -
+ include/linux/migrate.h                            |  78 +++--
+ include/linux/mpage.h                              |   2 -
+ include/linux/netfs.h                              |  23 +-
+ include/linux/page-flags.h                         |   2 +-
+ include/linux/pagemap.h                            |  29 +-
+ include/linux/pagevec.h                            |  10 -
+ include/linux/swap.h                               |   3 +-
+ include/uapi/linux/magic.h                         |   4 -
+ mm/balloon_compaction.c                            |  10 +-
+ mm/compaction.c                                    |  34 +-
+ mm/filemap.c                                       | 154 ++++-----
+ mm/folio-compat.c                                  |  22 --
+ mm/huge_memory.c                                   |   1 +
+ mm/hugetlb.c                                       |  14 +-
+ mm/ksm.c                                           |   2 +-
+ mm/migrate.c                                       | 239 ++++++++------
+ mm/migrate_device.c                                |   3 +-
+ mm/readahead.c                                     |   2 +
+ mm/secretmem.c                                     |  13 +-
+ mm/shmem.c                                         |  17 +-
+ mm/swap.c                                          |  29 --
+ mm/swap_state.c                                    |   4 +-
+ mm/util.c                                          |   4 +-
+ mm/vmscan.c                                        |  56 ++--
+ mm/z3fold.c                                        |  84 +----
+ mm/zsmalloc.c                                      | 102 ++----
+ 95 files changed, 841 insertions(+), 1890 deletions(-)
+Merging execve/for-next/execve (6342140db660 selftests/timens: add a test for vfork+exit)
+$ git merge -m Merge branch 'for-next/execve' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git execve/for-next/execve
+Auto-merging fs/exec.c
+Auto-merging kernel/fork.c
+Merge made by the 'ort' strategy.
+ fs/exec.c                                   |  7 +++
+ kernel/fork.c                               |  5 +-
+ kernel/nsproxy.c                            |  3 +-
+ tools/testing/selftests/timens/Makefile     |  2 +-
+ tools/testing/selftests/timens/vfork_exec.c | 90 +++++++++++++++++++++++++++++
+ 5 files changed, 104 insertions(+), 3 deletions(-)
+ create mode 100644 tools/testing/selftests/timens/vfork_exec.c
+Merging bitmap/bitmap-for-next (0dfe54071d7c nodemask: Fix return values to be unsigned)
+$ git merge -m Merge branch 'bitmap-for-next' of https://github.com/norov/linux.git bitmap/bitmap-for-next
+Already up to date.
+Merging hte/hte/for-next (85ff37e302ef gpiolib: cdev: Fix kernel doc for struct line)
+$ git merge -m Merge branch 'hte/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git hte/hte/for-next
+Auto-merging drivers/gpio/gpiolib-cdev.c
+Merge made by the 'ort' strategy.
+ drivers/gpio/gpiolib-cdev.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+Merging kspp/for-next/kspp (e1d337335207 cfi: Fix __cfi_slowpath_diag RCU usage with cpuidle)
+$ git merge -m Merge branch 'for-next/kspp' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git kspp/for-next/kspp
+Auto-merging kernel/cfi.c
+CONFLICT (content): Merge conflict in kernel/cfi.c
+Resolved 'kernel/cfi.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master 74628e56fe5d] Merge branch 'for-next/kspp' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git
+$ git diff -M --stat --summary HEAD^..
+Merging kspp-gustavo/for-next/kspp (f2906aa86338 Linux 5.19-rc1)
+$ git merge -m Merge branch 'for-next/kspp' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux.git kspp-gustavo/for-next/kspp
+Already up to date.
+Merging mm-stable/mm-stable (6edda04ccc7c mm/kmemleak: prevent soft lockup in first object iteration loop of kmemleak_scan())
+$ git merge -m Merge branch 'mm-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-stable/mm-stable
+Auto-merging arch/x86/mm/fault.c
+Auto-merging include/linux/highmem.h
+Auto-merging mm/memblock.c
+Auto-merging mm/memcontrol.c
+Auto-merging mm/page_alloc.c
+Auto-merging mm/shmem.c
+Auto-merging mm/slab.c
+Auto-merging mm/sparse-vmemmap.c
+Auto-merging mm/vmalloc.c
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/cgroup-v2.rst |  24 ++-
+ Documentation/dev-tools/kmemleak.rst    |   1 -
+ arch/alpha/mm/fault.c                   |   4 +
+ arch/arc/mm/fault.c                     |   4 +
+ arch/arm/mm/fault.c                     |   4 +
+ arch/arm64/mm/fault.c                   |   4 +
+ arch/csky/mm/fault.c                    |   4 +
+ arch/hexagon/mm/vm_fault.c              |   4 +
+ arch/ia64/mm/fault.c                    |   4 +
+ arch/m68k/mm/fault.c                    |   4 +
+ arch/microblaze/mm/fault.c              |   4 +
+ arch/mips/mm/fault.c                    |   4 +
+ arch/nios2/mm/fault.c                   |   4 +
+ arch/openrisc/mm/fault.c                |   4 +
+ arch/parisc/mm/fault.c                  |   4 +
+ arch/powerpc/mm/copro_fault.c           |   5 +
+ arch/powerpc/mm/fault.c                 |   5 +
+ arch/riscv/mm/fault.c                   |   4 +
+ arch/s390/mm/fault.c                    |  12 ++
+ arch/sh/mm/fault.c                      |   4 +
+ arch/sparc/mm/fault_32.c                |   4 +
+ arch/sparc/mm/fault_64.c                |   5 +
+ arch/um/kernel/trap.c                   |   4 +
+ arch/x86/mm/fault.c                     |   4 +
+ arch/x86/mm/hugetlbpage.c               |  39 -----
+ arch/xtensa/mm/fault.c                  |   4 +
+ drivers/of/fdt.c                        |   2 +-
+ include/linux/damon.h                   |  17 +--
+ include/linux/highmem.h                 |  13 --
+ include/linux/kmemleak.h                |   8 +-
+ include/linux/memcontrol.h              |  53 ++++++-
+ include/linux/mm_types.h                |   2 +
+ lib/test_hmm.c                          |  10 +-
+ mm/gup.c                                |  34 ++++-
+ mm/kmemleak.c                           | 260 ++++++++++++++++++++++----------
+ mm/list_lru.c                           |   2 +-
+ mm/memblock.c                           |  14 +-
+ mm/memcontrol.c                         | 126 ++++++++++------
+ mm/memory.c                             |   2 +-
+ mm/memory_hotplug.c                     |  20 ++-
+ mm/mempool.c                            |   2 +-
+ mm/memremap.c                           |   6 +-
+ mm/page_alloc.c                         |   5 +-
+ mm/shmem.c                              |  10 +-
+ mm/sparse-vmemmap.c                     |   6 +-
+ mm/vmalloc.c                            |  46 +++---
+ net/core/net_namespace.c                |   7 +
+ tools/testing/memblock/linux/kmemleak.h |   2 +-
+ tools/vm/slabinfo.c                     |  32 ++--
+ 49 files changed, 565 insertions(+), 281 deletions(-)
+Merging mm-nonmm-stable/mm-nonmm-stable (00c9d5632277 lib/error-inject: convert to DEFINE_SEQ_ATTRIBUTE)
+$ git merge -m Merge branch 'mm-nonmm-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-nonmm-stable/mm-nonmm-stable
+Auto-merging MAINTAINERS
+Auto-merging scripts/checkpatch.pl
+Merge made by the 'ort' strategy.
+ MAINTAINERS                                        |   1 +
+ arch/ia64/include/uapi/asm/cmpxchg.h               |  28 +--
+ fs/fat/namei_vfat.c                                | 231 +++++++++++++++++----
+ fs/kernel_read_file.c                              |  38 ++--
+ fs/ocfs2/dlmfs/dlmfs.c                             |  14 +-
+ fs/squashfs/block.c                                |  10 +-
+ fs/squashfs/decompressor.h                         |   1 +
+ fs/squashfs/file_direct.c                          |  90 ++------
+ fs/squashfs/lz4_wrapper.c                          |   7 +-
+ fs/squashfs/lzo_wrapper.c                          |   7 +-
+ fs/squashfs/page_actor.c                           |  55 ++++-
+ fs/squashfs/page_actor.h                           |  21 +-
+ fs/squashfs/xz_wrapper.c                           |  11 +-
+ fs/squashfs/zlib_wrapper.c                         |  12 +-
+ fs/squashfs/zstd_wrapper.c                         |  12 +-
+ include/linux/kernel_read_file.h                   |  32 +--
+ include/linux/limits.h                             |   1 +
+ include/linux/rbtree.h                             |   2 +-
+ include/uapi/linux/swab.h                          |   6 +-
+ kernel/kexec_file.c                                |  10 +-
+ kernel/profile.c                                   |   7 +
+ lib/btree.c                                        |  30 ++-
+ lib/error-inject.c                                 |  16 +-
+ lib/flex_proportions.c                             |  10 +-
+ lib/list_debug.c                                   |  12 +-
+ scripts/checkpatch.pl                              |   5 +-
+ tools/accounting/getdelays.c                       |   4 -
+ tools/testing/selftests/Makefile                   |   1 +
+ tools/testing/selftests/filesystems/fat/.gitignore |   2 +
+ tools/testing/selftests/filesystems/fat/Makefile   |   7 +
+ tools/testing/selftests/filesystems/fat/config     |   2 +
+ .../selftests/filesystems/fat/rename_exchange.c    |  37 ++++
+ .../selftests/filesystems/fat/run_fat_tests.sh     |  82 ++++++++
+ 33 files changed, 569 insertions(+), 235 deletions(-)
+ create mode 100644 tools/testing/selftests/filesystems/fat/.gitignore
+ create mode 100644 tools/testing/selftests/filesystems/fat/Makefile
+ create mode 100644 tools/testing/selftests/filesystems/fat/config
+ create mode 100644 tools/testing/selftests/filesystems/fat/rename_exchange.c
+ create mode 100644 tools/testing/selftests/filesystems/fat/run_fat_tests.sh
+Merging mm/mm-everything (8b3452cdabac Merge branch 'mm-nonmm-unstable' into mm-everything)
+$ git merge -m Merge branch 'mm-everything' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm/mm-everything
+Auto-merging Documentation/admin-guide/kernel-parameters.txt
+Auto-merging MAINTAINERS
+Auto-merging MAINTAINERS
+Auto-merging arch/parisc/kernel/cache.c
+Auto-merging arch/x86/kvm/mmu/mmu.c
+Auto-merging drivers/firmware/efi/efi.c
+Auto-merging drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+Auto-merging drivers/md/dm.c
+Auto-merging drivers/misc/vmw_balloon.c
+Auto-merging drivers/virtio/virtio_balloon.c
+Auto-merging fs/btrfs/super.c
+Auto-merging fs/buffer.c
+Auto-merging fs/exec.c
+Auto-merging fs/ext2/super.c
+Auto-merging fs/ext4/super.c
+Auto-merging fs/gfs2/glock.c
+Auto-merging fs/ocfs2/refcounttree.c
+Auto-merging fs/proc/array.c
+Auto-merging fs/remap_range.c
+Auto-merging fs/squashfs/file.c
+Auto-merging fs/xfs/xfs_file.c
+Auto-merging fs/xfs/xfs_iomap.c
+Auto-merging include/linux/fs.h
+Auto-merging include/linux/highmem.h
+Auto-merging include/linux/migrate.h
+Auto-merging include/linux/net.h
+Auto-merging include/linux/page-flags.h
+Auto-merging include/linux/pagemap.h
+Auto-merging include/linux/pagevec.h
+CONFLICT (content): Merge conflict in include/linux/pagevec.h
+Auto-merging include/linux/sched.h
+Auto-merging kernel/events/core.c
+Auto-merging kernel/fork.c
+Auto-merging kernel/kallsyms.c
+Auto-merging kernel/rcu/tree.c
+Auto-merging kernel/sched/fair.c
+Auto-merging lib/Kconfig
+Auto-merging lib/Kconfig.debug
+Auto-merging lib/Makefile
+Auto-merging mm/compaction.c
+Auto-merging mm/huge_memory.c
+Auto-merging mm/hugetlb.c
+Auto-merging mm/internal.h
+Auto-merging mm/ksm.c
+Auto-merging mm/memcontrol.c
+Auto-merging mm/migrate.c
+Auto-merging mm/migrate_device.c
+Auto-merging mm/page_alloc.c
+Auto-merging mm/shmem.c
+Auto-merging mm/sparse-vmemmap.c
+Auto-merging mm/swap.c
+Auto-merging mm/swap_state.c
+Auto-merging mm/util.c
+Auto-merging mm/vmalloc.c
+Auto-merging mm/vmscan.c
+CONFLICT (content): Merge conflict in mm/vmscan.c
+Auto-merging mm/zsmalloc.c
+Resolved 'include/linux/pagevec.h' using previous resolution.
+Resolved 'mm/vmscan.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master 552265813e37] Merge branch 'mm-everything' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
+$ git diff -M --stat --summary HEAD^..
+ Documentation/ABI/testing/procfs-smaps_rollup      |     1 +
+ Documentation/admin-guide/kernel-parameters.txt    |    35 +-
+ Documentation/admin-guide/mm/damon/index.rst       |     1 +
+ Documentation/admin-guide/mm/damon/lru_sort.rst    |   294 +
+ Documentation/admin-guide/mm/damon/reclaim.rst     |     6 -
+ Documentation/admin-guide/mm/damon/usage.rst       |     2 +
+ Documentation/admin-guide/mm/index.rst             |     1 +
+ Documentation/admin-guide/mm/shrinker_debugfs.rst  |   135 +
+ Documentation/admin-guide/mm/userfaultfd.rst       |    40 +-
+ Documentation/admin-guide/sysctl/vm.rst            |     8 +-
+ Documentation/core-api/index.rst                   |     1 +
+ Documentation/core-api/maple_tree.rst              |   217 +
+ Documentation/filesystems/proc.rst                 |     9 +-
+ Documentation/vm/balance.rst                       |     2 +-
+ MAINTAINERS                                        |    12 +
+ arch/arm64/kernel/elfcore.c                        |    16 +-
+ arch/arm64/kernel/vdso.c                           |     3 +-
+ arch/arm64/mm/hugetlbpage.c                        |    20 +
+ arch/mips/kernel/mips-mt.c                         |     4 +-
+ arch/parisc/kernel/cache.c                         |     9 +-
+ arch/powerpc/kernel/vdso.c                         |     6 +-
+ arch/powerpc/mm/book3s32/tlb.c                     |    11 +-
+ arch/powerpc/mm/book3s64/subpage_prot.c            |    13 +-
+ arch/riscv/kernel/vdso.c                           |     3 +-
+ arch/s390/kernel/vdso.c                            |     3 +-
+ arch/s390/mm/gmap.c                                |     6 +-
+ arch/um/kernel/tlb.c                               |    14 +-
+ arch/x86/entry/vdso/vma.c                          |     9 +-
+ arch/x86/kernel/tboot.c                            |     2 +-
+ arch/x86/kvm/mmu/mmu.c                             |     2 +-
+ arch/xtensa/kernel/syscall.c                       |    18 +-
+ drivers/android/binder_alloc.c                     |    32 +-
+ drivers/android/binder_alloc.h                     |     2 +-
+ drivers/android/binder_alloc_selftest.c            |     2 +-
+ drivers/block/zram/zcomp.c                         |     6 -
+ drivers/dax/super.c                                |    67 +-
+ drivers/firmware/efi/efi.c                         |     2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_migrate.c           |    34 +-
+ drivers/gpu/drm/i915/gem/i915_gem_shrinker.c       |     3 +-
+ drivers/gpu/drm/i915/gem/i915_gem_userptr.c        |    14 +-
+ drivers/gpu/drm/msm/msm_gem_shrinker.c             |     2 +-
+ drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c   |     2 +-
+ drivers/gpu/drm/ttm/ttm_pool.c                     |     2 +-
+ drivers/iommu/tegra-smmu.c                         |     4 +-
+ drivers/md/bcache/btree.c                          |     2 +-
+ drivers/md/dm-bufio.c                              |     3 +-
+ drivers/md/dm-zoned-metadata.c                     |     4 +-
+ drivers/md/dm.c                                    |     2 +-
+ drivers/md/raid5.c                                 |     2 +-
+ drivers/misc/cxl/fault.c                           |    45 +-
+ drivers/misc/vmw_balloon.c                         |     2 +-
+ drivers/nvdimm/pmem.c                              |    17 +
+ drivers/tee/optee/call.c                           |    18 +-
+ drivers/virtio/virtio_balloon.c                    |     2 +-
+ drivers/xen/privcmd.c                              |     2 +-
+ drivers/xen/xenbus/xenbus_probe_backend.c          |     2 +-
+ fs/btrfs/super.c                                   |     2 +
+ fs/buffer.c                                        |     4 +-
+ fs/coredump.c                                      |    34 +-
+ fs/dax.c                                           |   401 +-
+ fs/erofs/super.c                                   |    10 +-
+ fs/erofs/utils.c                                   |     2 +-
+ fs/exec.c                                          |    12 +-
+ fs/ext2/super.c                                    |     7 +-
+ fs/ext4/extents_status.c                           |     3 +-
+ fs/ext4/super.c                                    |     9 +-
+ fs/f2fs/super.c                                    |     2 +-
+ fs/fs-writeback.c                                  |    23 +-
+ fs/gfs2/glock.c                                    |     2 +-
+ fs/gfs2/main.c                                     |     2 +-
+ fs/jbd2/journal.c                                  |     3 +-
+ fs/mbcache.c                                       |     2 +-
+ fs/nfs/nfs42xattr.c                                |     7 +-
+ fs/nfs/super.c                                     |     2 +-
+ fs/nfsd/filecache.c                                |     2 +-
+ fs/nfsd/nfscache.c                                 |     3 +-
+ fs/ocfs2/namei.c                                   |    49 +-
+ fs/ocfs2/namei.h                                   |     2 +
+ fs/ocfs2/refcounttree.c                            |    15 +-
+ fs/ocfs2/xattr.c                                   |    12 +-
+ fs/ocfs2/xattr.h                                   |     1 +
+ fs/proc/array.c                                    |     1 -
+ fs/proc/base.c                                     |     5 +-
+ fs/proc/inode.c                                    |     2 -
+ fs/proc/internal.h                                 |     2 +-
+ fs/proc/kmsg.c                                     |     1 -
+ fs/proc/nommu.c                                    |     1 -
+ fs/proc/proc_net.c                                 |     3 -
+ fs/proc/proc_tty.c                                 |     2 -
+ fs/proc/root.c                                     |     3 -
+ fs/proc/task_mmu.c                                 |    81 +-
+ fs/proc/task_nommu.c                               |    45 +-
+ fs/proc/vmcore.c                                   |     1 -
+ fs/quota/dquot.c                                   |     2 +-
+ fs/remap_range.c                                   |    31 +-
+ fs/squashfs/Makefile                               |     4 +-
+ fs/squashfs/file.c                                 |   133 +-
+ fs/squashfs/page_actor.h                           |    46 -
+ fs/squashfs/super.c                                |    33 -
+ fs/super.c                                         |     6 +-
+ fs/ubifs/super.c                                   |     2 +-
+ fs/userfaultfd.c                                   |   138 +-
+ fs/xfs/Makefile                                    |     5 +
+ fs/xfs/xfs_buf.c                                   |    13 +-
+ fs/xfs/xfs_file.c                                  |    35 +-
+ fs/xfs/xfs_fsops.c                                 |     3 +
+ fs/xfs/xfs_icache.c                                |     2 +-
+ fs/xfs/xfs_inode.c                                 |    69 +-
+ fs/xfs/xfs_inode.h                                 |     1 +
+ fs/xfs/xfs_iomap.c                                 |    30 +-
+ fs/xfs/xfs_iomap.h                                 |     1 +
+ fs/xfs/xfs_mount.h                                 |     1 +
+ fs/xfs/xfs_notify_failure.c                        |   220 +
+ fs/xfs/xfs_qm.c                                    |     3 +-
+ fs/xfs/xfs_reflink.c                               |    12 +-
+ fs/xfs/xfs_super.h                                 |     1 +
+ include/linux/damon.h                              |    10 +
+ include/linux/dax.h                                |    56 +-
+ include/linux/fs.h                                 |    12 +-
+ include/linux/gfp.h                                |    12 +-
+ include/linux/highmem.h                            |    10 +
+ include/linux/huge_mm.h                            |    88 +-
+ include/linux/hugetlb.h                            |    35 +-
+ include/linux/khugepaged.h                         |    30 -
+ include/linux/maple_tree.h                         |   685 +
+ include/linux/memcontrol.h                         |   239 +-
+ include/linux/memory_hotplug.h                     |     9 -
+ include/linux/memremap.h                           |    31 +
+ include/linux/migrate.h                            |     1 +
+ include/linux/mm.h                                 |   123 +-
+ include/linux/mm_inline.h                          |     6 +
+ include/linux/mm_types.h                           |    48 +-
+ include/linux/mm_types_task.h                      |    12 -
+ include/linux/mmzone.h                             |    59 +-
+ include/linux/net.h                                |     2 -
+ include/linux/once.h                               |     2 -
+ include/linux/oom.h                                |    11 -
+ include/linux/page-flags.h                         |    23 +
+ include/linux/pagemap.h                            |     2 -
+ include/linux/pagevec.h                            |     1 -
+ include/linux/rmap.h                               |     4 +-
+ include/linux/sched.h                              |     1 -
+ include/linux/sched/coredump.h                     |     7 +-
+ include/linux/shrinker.h                           |    31 +-
+ include/linux/swapops.h                            |    12 +-
+ include/linux/userfaultfd_k.h                      |     7 +-
+ include/linux/vm_event_item.h                      |     4 -
+ include/linux/vmacache.h                           |    28 -
+ include/linux/vmstat.h                             |     6 -
+ include/ras/ras_event.h                            |     1 -
+ include/trace/events/maple_tree.h                  |   123 +
+ include/trace/events/mmap.h                        |    73 +
+ include/trace/events/mmflags.h                     |     1 -
+ include/trace/events/writeback.h                   |     5 +
+ include/uapi/linux/userfaultfd.h                   |     4 +
+ init/main.c                                        |    27 +-
+ init/version.c                                     |    17 +
+ ipc/shm.c                                          |    21 +-
+ kernel/acct.c                                      |    11 +-
+ kernel/bpf/task_iter.c                             |    10 +-
+ kernel/crash_core.c                                |    14 +
+ kernel/debug/debug_core.c                          |    12 -
+ kernel/events/core.c                               |     3 +-
+ kernel/events/uprobes.c                            |     9 +-
+ kernel/fork.c                                      |    57 +-
+ kernel/kallsyms.c                                  |    23 +-
+ kernel/kallsyms_internal.h                         |    30 +
+ kernel/rcu/tree.c                                  |     2 +-
+ kernel/resource.c                                  |    19 +-
+ kernel/sched/fair.c                                |    10 +-
+ lib/Kconfig                                        |     9 -
+ lib/Kconfig.debug                                  |    26 +-
+ lib/Makefile                                       |     3 +-
+ lib/debugobjects.c                                 |    10 +
+ lib/error-inject.c                                 |    12 +-
+ lib/lru_cache.c                                    |     4 +-
+ lib/maple_tree.c                                   |  7041 ++++
+ lib/stackdepot.c                                   |    59 +-
+ lib/test_hmm.c                                     |   337 +-
+ lib/test_hmm_uapi.h                                |    19 +-
+ lib/test_maple_tree.c                              | 38186 +++++++++++++++++++
+ lib/test_printf.c                                  |     8 +-
+ lib/test_vmalloc.c                                 |    15 +-
+ mm/Makefile                                        |     3 +-
+ mm/compaction.c                                    |    41 +-
+ mm/damon/Kconfig                                   |     8 +
+ mm/damon/Makefile                                  |     1 +
+ mm/damon/dbgfs.c                                   |    79 +-
+ mm/damon/lru_sort.c                                |   546 +
+ mm/damon/ops-common.c                              |    42 +
+ mm/damon/ops-common.h                              |     2 +
+ mm/damon/paddr.c                                   |    60 +-
+ mm/damon/reclaim.c                                 |    40 +-
+ mm/damon/sysfs.c                                   |    69 +-
+ mm/damon/vaddr-test.h                              |    36 +-
+ mm/damon/vaddr.c                                   |    53 +-
+ mm/debug.c                                         |    14 +-
+ mm/gup.c                                           |    62 +-
+ mm/huge_memory.c                                   |   248 +-
+ mm/hugetlb.c                                       |   144 +-
+ mm/hugetlb_vmemmap.c                               |    66 +-
+ mm/init-mm.c                                       |     4 +-
+ mm/internal.h                                      |    11 +-
+ mm/kasan/common.c                                  |     8 +-
+ mm/kasan/hw_tags.c                                 |    32 +-
+ mm/kasan/kasan.h                                   |     3 +-
+ mm/kasan/report.c                                  |    12 +-
+ mm/khugepaged.c                                    |   106 +-
+ mm/ksm.c                                           |    24 +-
+ mm/madvise.c                                       |    16 +-
+ mm/memcontrol.c                                    |   620 +-
+ mm/memory-failure.c                                |   329 +-
+ mm/memory.c                                        |    52 +-
+ mm/memory_hotplug.c                                |    35 +-
+ mm/mempolicy.c                                     |    62 +-
+ mm/memremap.c                                      |    10 +
+ mm/migrate.c                                       |    47 +-
+ mm/migrate_device.c                                |   115 +-
+ mm/mlock.c                                         |    41 +-
+ mm/mmap.c                                          |  2265 +-
+ mm/mprotect.c                                      |    86 +-
+ mm/mremap.c                                        |    41 +-
+ mm/msync.c                                         |     2 +-
+ mm/nommu.c                                         |   249 +-
+ mm/oom_kill.c                                      |     9 +-
+ mm/page_alloc.c                                    |   479 +-
+ mm/page_io.c                                       |     5 +-
+ mm/page_vma_mapped.c                               |     2 +-
+ mm/pagewalk.c                                      |     2 +-
+ mm/rmap.c                                          |    95 +-
+ mm/shmem.c                                         |     4 +-
+ mm/shrinker_debug.c                                |   285 +
+ mm/sparse.c                                        |     2 +-
+ mm/swap.c                                          |   634 +-
+ mm/swap.h                                          |    14 +-
+ mm/swap_state.c                                    |    56 +-
+ mm/swapfile.c                                      |    41 +-
+ mm/util.c                                          |    32 -
+ mm/vmacache.c                                      |   117 -
+ mm/vmalloc.c                                       |   111 +-
+ mm/vmscan.c                                        |   366 +-
+ mm/vmstat.c                                        |     4 -
+ mm/workingset.c                                    |     2 +-
+ mm/zsmalloc.c                                      |     3 +-
+ net/core/page_pool.c                               |     2 +-
+ net/sunrpc/auth.c                                  |     2 +-
+ tools/cgroup/memcg_shrinker.py                     |    71 +
+ tools/include/linux/gfp.h                          |     3 +-
+ tools/include/linux/slab.h                         |     4 +
+ tools/perf/builtin-kmem.c                          |     1 -
+ tools/testing/radix-tree/.gitignore                |     2 +
+ tools/testing/radix-tree/Makefile                  |     9 +-
+ tools/testing/radix-tree/generated/autoconf.h      |     1 +
+ tools/testing/radix-tree/linux.c                   |   160 +-
+ tools/testing/radix-tree/linux/kernel.h            |     1 +
+ tools/testing/radix-tree/linux/lockdep.h           |     2 +
+ tools/testing/radix-tree/linux/maple_tree.h        |     7 +
+ tools/testing/radix-tree/maple.c                   |    59 +
+ tools/testing/radix-tree/trace/events/maple_tree.h |     5 +
+ tools/testing/selftests/vm/hmm-tests.c             |   306 +-
+ tools/testing/selftests/vm/mremap_test.c           |    49 +-
+ tools/testing/selftests/vm/run_vmtests.sh          |    18 +-
+ tools/testing/selftests/vm/test_hmm.sh             |    24 +-
+ tools/testing/selftests/vm/userfaultfd.c           |    70 +-
+ 264 files changed, 55008 insertions(+), 4268 deletions(-)
+ create mode 100644 Documentation/admin-guide/mm/damon/lru_sort.rst
+ create mode 100644 Documentation/admin-guide/mm/shrinker_debugfs.rst
+ create mode 100644 Documentation/core-api/maple_tree.rst
+ create mode 100644 fs/xfs/xfs_notify_failure.c
+ create mode 100644 include/linux/maple_tree.h
+ delete mode 100644 include/linux/vmacache.h
+ create mode 100644 include/trace/events/maple_tree.h
+ create mode 100644 kernel/kallsyms_internal.h
+ create mode 100644 lib/maple_tree.c
+ create mode 100644 lib/test_maple_tree.c
+ create mode 100644 mm/damon/lru_sort.c
+ create mode 100644 mm/shrinker_debug.c
+ delete mode 100644 mm/vmacache.c
+ create mode 100644 tools/cgroup/memcg_shrinker.py
+ create mode 100644 tools/testing/radix-tree/linux/maple_tree.h
+ create mode 100644 tools/testing/radix-tree/maple.c
+ create mode 100644 tools/testing/radix-tree/trace/events/maple_tree.h
+Merging amdgpu/drm-next (fdf249c70a36 drm/amdgpu/display: reduce stack size in dml32_ModeSupportAndSystemConfigurationFull())
+$ git merge -m Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux amdgpu/drm-next
+Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+Auto-merging drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+Auto-merging drivers/gpu/drm/amd/amdkfd/kfd_device.c
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+Auto-merging drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+Auto-merging drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+Auto-merging drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+Auto-merging drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+Auto-merging include/linux/workqueue.h
+Auto-merging kernel/workqueue.c
+Merge made by the 'ort' strategy.
+ drivers/gpu/drm/amd/amdgpu/Makefile                |      3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h                |     16 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c           |      6 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c         |     15 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h         |     10 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |    366 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c            |      7 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c        |      7 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |    232 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c      |     13 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c        |     52 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            |     10 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c          |     19 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c            |     55 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h            |      2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h            |      7 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c            |      2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |      4 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c            |      4 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h            |      6 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c          |      1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h          |      1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c           |     12 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c            |     20 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c          |     20 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c            |    102 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h            |      1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c             |      2 +-
+ drivers/gpu/drm/amd/amdgpu/atombios_encoders.c     |     14 -
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c             |     41 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c             |     28 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c             |      3 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c             |     56 +-
+ drivers/gpu/drm/amd/amdgpu/imu_v11_0.c             |     46 +-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c          |    555 +
+ drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h          |     28 +
+ drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c              |      2 +-
+ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c              |      2 +-
+ drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c              |      2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c             |      2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c             |    126 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c             |      8 +-
+ drivers/gpu/drm/amd/amdgpu/soc21.c                 |     19 +-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_7.c              |     50 +-
+ drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c              |    563 +-
+ drivers/gpu/drm/amd/amdkfd/Kconfig                 |     14 +
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c           |     34 +
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c              |      2 -
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c            |      2 +-
+ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |     31 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c            |      5 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c           |      6 +-
+ .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |      2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c          |    323 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.h          |      4 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |    376 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |      5 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c  |      8 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |      3 +
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |     18 +-
+ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    |    151 +-
+ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h    |      6 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c  |     21 +-
+ drivers/gpu/drm/amd/display/dc/Makefile            |      2 +
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |    950 +-
+ .../display/dc/bios/bios_parser_types_internal2.h  |      1 +
+ .../gpu/drm/amd/display/dc/bios/command_table.c    |      4 +-
+ .../amd/display/dc/bios/command_table_helper2.c    |      2 +
+ drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile    |     34 +
+ drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c   |     17 +-
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   |     23 +-
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c        |     12 +
+ .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c   |     15 +-
+ .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h   |     60 +
+ .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c       |     11 +-
+ .../drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c |     12 +
+ .../drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c   |      8 +
+ .../amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c |      2 +-
+ .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c |      8 +
+ .../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c |      8 +
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h  |     65 +
+ .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c   |    862 +
+ .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h   |     39 +
+ .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c       |    140 +
+ .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h       |     47 +
+ .../dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h       |     63 +
+ .../amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h |    108 +
+ drivers/gpu/drm/amd/display/dc/core/dc.c           |    164 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_debug.c     |      2 +
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c      |    132 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |    361 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c |     38 +-
+ .../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c  |     45 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |     52 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |      5 +-
+ drivers/gpu/drm/amd/display/dc/dc.h                |     45 +-
+ drivers/gpu/drm/amd/display/dc/dc_bios_types.h     |      5 +
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c       |     33 +
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h       |      5 +
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h       |      1 +
+ drivers/gpu/drm/amd/display/dc/dc_link.h           |      5 +
+ drivers/gpu/drm/amd/display/dc/dc_stream.h         |     36 +-
+ drivers/gpu/drm/amd/display/dc/dc_types.h          |     23 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h       |     45 +
+ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |     27 +
+ .../gpu/drm/amd/display/dc/dce/dce_clock_source.h  |     15 +
+ .../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c  |      2 +
+ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c      |     64 +
+ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h      |      2 +
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c    |     47 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h    |     33 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  |      2 +
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |    144 +-
+ .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h  |      6 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  |      1 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  |      5 +
+ .../amd/display/dc/dcn10/dcn10_stream_encoder.c    |      8 +-
+ .../amd/display/dc/dcn10/dcn10_stream_encoder.h    |     29 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h  |     34 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c   |      3 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c  |      2 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h  |     25 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |     49 +-
+ .../amd/display/dc/dcn20/dcn20_stream_encoder.c    |      1 +
+ drivers/gpu/drm/amd/display/dc/dcn201/Makefile     |      1 -
+ drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c |      3 +
+ drivers/gpu/drm/amd/display/dc/dcn30/Makefile      |      6 +-
+ .../display/dc/dcn30/dcn30_dio_stream_encoder.c    |     32 +-
+ .../display/dc/dcn30/dcn30_dio_stream_encoder.h    |     35 +
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c   |     11 +-
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h   |     16 +
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c |     61 +-
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h |     11 +-
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c  |      2 +-
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c   |     14 +-
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h   |    147 +
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c  |      1 +
+ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h  |      9 +
+ .../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c  |      1 +
+ drivers/gpu/drm/amd/display/dc/dcn302/Makefile     |      8 +-
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c  |     40 +-
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h  |     16 +-
+ .../amd/display/dc/dcn31/dcn31_dio_link_encoder.c  |      6 +
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c  |      2 +-
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c |     24 +-
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c  |      1 +
+ drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h  |      6 +-
+ .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c  |      2 -
+ .../drm/amd/display/dc/dcn315/dcn315_resource.c    |      6 +-
+ .../drm/amd/display/dc/dcn316/dcn316_resource.c    |      6 +-
+ drivers/gpu/drm/amd/display/dc/dcn32/Makefile      |     45 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c  |    303 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h  |    159 +
+ .../amd/display/dc/dcn32/dcn32_dio_link_encoder.c  |    294 +
+ .../amd/display/dc/dcn32/dcn32_dio_link_encoder.h  |     60 +
+ .../display/dc/dcn32/dcn32_dio_stream_encoder.c    |    461 +
+ .../display/dc/dcn32/dcn32_dio_stream_encoder.h    |    266 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c   |    164 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h   |     38 +
+ .../display/dc/dcn32/dcn32_hpo_dp_link_encoder.c   |     90 +
+ .../display/dc/dcn32/dcn32_hpo_dp_link_encoder.h   |     63 +
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c    |    964 +
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h    |    174 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c  |    148 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h  |     69 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c |    958 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h |     66 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c  |    156 +
+ .../hw_translate_diag.c => dcn32/dcn32_init.h}     |     20 +-
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c  |    239 +
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h  |    225 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c   |    810 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h   |    213 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c  |    268 +
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h  |    254 +
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c  |   4002 +
+ .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h  |     88 +
+ drivers/gpu/drm/amd/display/dc/dcn321/Makefile     |     42 +
+ .../display/dc/dcn321/dcn321_dio_link_encoder.c    |    199 +
+ .../display/dc/dcn321/dcn321_dio_link_encoder.h    |     42 +
+ .../drm/amd/display/dc/dcn321/dcn321_resource.c    |   2335 +
+ .../hw_factory_diag.c => dcn321/dcn321_resource.h} |     46 +-
+ drivers/gpu/drm/amd/display/dc/dml/Makefile        |      7 +
+ drivers/gpu/drm/amd/display/dc/dml/dc_features.h   |      2 +-
+ .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c   |    110 +-
+ .../amd/display/dc/dml/dcn30/display_mode_vba_30.c |      8 +-
+ .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c |     40 +-
+ .../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c   |     73 +-
+ .../amd/display/dc/dml/dcn31/display_mode_vba_31.c |      2 +-
+ .../display/dc/dml/dcn31/display_rq_dlg_calc_31.c  |     16 +-
+ .../amd/display/dc/dml/dcn32/display_mode_vba_32.c |   3824 +
+ .../amd/display/dc/dml/dcn32/display_mode_vba_32.h |     57 +
+ .../dc/dml/dcn32/display_mode_vba_util_32.c        |   6253 +
+ .../dc/dml/dcn32/display_mode_vba_util_32.h        |   1175 +
+ .../display/dc/dml/dcn32/display_rq_dlg_calc_32.c  |    616 +
+ .../display/dc/dml/dcn32/display_rq_dlg_calc_32.h  |     70 +
+ .../drm/amd/display/dc/dml/display_mode_enums.h    |     88 +-
+ .../gpu/drm/amd/display/dc/dml/display_mode_lib.c  |     12 +
+ .../gpu/drm/amd/display/dc/dml/display_mode_lib.h  |     15 +
+ .../drm/amd/display/dc/dml/display_mode_structs.h  |    138 +
+ .../gpu/drm/amd/display/dc/dml/display_mode_vba.c  |    171 +
+ .../gpu/drm/amd/display/dc/dml/display_mode_vba.h  |    247 +-
+ drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c   |     71 +-
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c        |      4 +-
+ drivers/gpu/drm/amd/display/dc/gpio/Makefile       |      8 +-
+ .../amd/display/dc/gpio/dcn20/hw_translate_dcn20.c |     17 +-
+ .../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c |     17 +-
+ .../amd/display/dc/gpio/dcn30/hw_translate_dcn30.c |     19 +-
+ .../amd/display/dc/gpio/dcn32/hw_factory_dcn32.c   |    255 +
+ .../hw_factory_diag.h => dcn32/hw_factory_dcn32.h} |     13 +-
+ .../amd/display/dc/gpio/dcn32/hw_translate_dcn32.c |    349 +
+ .../hw_translate_dcn32.h}                          |     11 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   |     16 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c |     13 +-
+ drivers/gpu/drm/amd/display/dc/inc/core_status.h   |      2 +-
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h    |     10 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h    |      5 +
+ .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |     45 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h       |     31 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h   |      3 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h        |      6 -
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h       |      8 +
+ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |     23 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |      2 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h        |      5 +
+ .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h |      8 +
+ .../drm/amd/display/dc/inc/hw/timing_generator.h   |      8 +
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |      2 +
+ .../drm/amd/display/dc/inc/hw_sequencer_private.h  |     11 +
+ drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h  |      7 +
+ drivers/gpu/drm/amd/display/dc/inc/link_hwss.h     |      6 +-
+ drivers/gpu/drm/amd/display/dc/inc/resource.h      |      7 +
+ drivers/gpu/drm/amd/display/dc/irq/Makefile        |     10 +-
+ .../amd/display/dc/irq/dcn32/irq_service_dcn32.c   |    432 +
+ .../amd/display/dc/irq/dcn32/irq_service_dcn32.h   |     35 +
+ drivers/gpu/drm/amd/display/dmub/dmub_srv.h        |      8 +
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h    |    277 +-
+ drivers/gpu/drm/amd/display/dmub/src/Makefile      |      1 +
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c  |    493 +
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h  |    256 +
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c    |     51 +-
+ .../drm/amd/display/include/bios_parser_types.h    |     11 +
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h  |     14 +-
+ drivers/gpu/drm/amd/display/include/dal_types.h    |      2 +
+ .../drm/amd/display/include/ddc_service_types.h    |      4 +
+ drivers/gpu/drm/amd/display/include/fixed31_32.h   |      2 +-
+ .../drm/amd/display/include/link_service_types.h   |      3 +-
+ .../drm/amd/display/modules/freesync/freesync.c    |      5 +
+ .../amd/display/modules/hdcp/hdcp2_transition.c    |      2 +-
+ .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c    |      4 +
+ .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.h    |     11 +
+ .../gpu/drm/amd/display/modules/inc/mod_freesync.h |      3 +
+ .../amd/display/modules/info_packet/info_packet.c  |     29 +-
+ .../drm/amd/display/modules/power/power_helpers.c  |     84 +
+ .../drm/amd/display/modules/power/power_helpers.h  |      6 +
+ drivers/gpu/drm/amd/display/modules/vmid/vmid.c    |      2 +-
+ .../gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h  |      1 +
+ .../amd/include/asic_reg/dce/dce_11_0_sh_mask.h    |      2 +
+ .../amd/include/asic_reg/dcn/dcn_3_2_0_offset.h    |  14677 ++
+ .../amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h   | 222893 ++++++++++++++++++
+ .../amd/include/asic_reg/dcn/dcn_3_2_1_offset.h    |  14561 ++
+ .../amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h   |  56582 +++++
+ .../include/asic_reg/mmhub/mmhub_3_0_1_offset.h    |   1769 +
+ .../include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h   |   7483 +
+ .../amd/include/asic_reg/nbio/nbio_4_3_0_offset.h  |      2 +
+ .../amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h |      1 +
+ .../amd/include/asic_reg/nbio/nbio_7_7_0_offset.h  |      4 +
+ .../amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h |     10 +
+ drivers/gpu/drm/amd/include/atomfirmware.h         |    209 +-
+ drivers/gpu/drm/amd/include/mes_api_def.h          |      2 +-
+ drivers/gpu/drm/amd/include/mes_v11_api_def.h      |      2 +-
+ drivers/gpu/drm/amd/pm/amdgpu_dpm.c                |     14 +
+ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h            |      2 +
+ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c          |     31 +-
+ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h      |     12 +
+ .../drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h  |      2 +-
+ .../swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h  |     17 +-
+ .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h |      6 +
+ .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h |     62 +-
+ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h       |      2 +
+ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h       |     23 +-
+ drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c  |     10 +-
+ .../drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c    |      1 +
+ drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c    |      1 +
+ .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c    |     13 +-
+ drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c     |      9 +
+ drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c   |      1 +
+ drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c    |     14 +
+ drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c |     98 +-
+ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c     |     61 +-
+ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c   |     34 +-
+ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c   |     28 +-
+ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c   |     14 +
+ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c   |     19 +
+ .../gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c   |      1 +
+ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c             |     83 +-
+ drivers/gpu/drm/radeon/.gitignore                  |      2 +-
+ drivers/gpu/drm/radeon/Kconfig                     |      2 +-
+ drivers/gpu/drm/radeon/Makefile                    |      2 +-
+ drivers/gpu/drm/radeon/atombios_encoders.c         |     14 -
+ drivers/gpu/drm/radeon/ni_dpm.c                    |      6 +-
+ drivers/gpu/drm/radeon/radeon_acpi.c               |      2 -
+ drivers/gpu/drm/radeon/radeon_gem.c                |      2 +-
+ drivers/gpu/drm/radeon/radeon_legacy_encoders.c    |     15 -
+ drivers/gpu/drm/radeon/radeon_mode.h               |      4 -
+ drivers/gpu/drm/radeon/radeon_sa.c                 |      6 +-
+ include/linux/workqueue.h                          |      1 +
+ include/uapi/drm/drm_fourcc.h                      |      2 +
+ include/uapi/linux/kfd_ioctl.h                     |     14 +-
+ kernel/workqueue.c                                 |      9 +
+ 310 files changed, 353670 insertions(+), 2086 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+ rename drivers/gpu/drm/amd/display/dc/{gpio/diagnostics/hw_translate_diag.c => dcn32/dcn32_init.h} (74%)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+ rename drivers/gpu/drm/amd/display/dc/{gpio/diagnostics/hw_factory_diag.c => dcn321/dcn321_resource.h} (53%)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
+ rename drivers/gpu/drm/amd/display/dc/gpio/{diagnostics/hw_factory_diag.h => dcn32/hw_factory_dcn32.h} (81%)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
+ rename drivers/gpu/drm/amd/display/dc/gpio/{diagnostics/hw_translate_diag.h => dcn32/hw_translate_dcn32.h} (82%)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_0_1_sh_mask.h
+$ git am -3 ../patches/0001-fix-up-for-devcoredump-remove-the-useless-gfp_t-para.patch
+Applying: fix up for "devcoredump: remove the useless gfp_t parameter in dev_coredumpv and dev_coredumpm"
+$ git reset HEAD^
+Unstaged changes after reset:
+M	drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+$ git add -A .
+$ git commit -v -a --amend
+[master e8fe1cdc9702] Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux
+ Date: Thu Jun 23 15:31:40 2022 +1000
diff --git a/arch/Kconfig b/arch/Kconfig
index fcf9a41a4ef5..3baa8206f4e8 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -353,6 +353,12 @@ config HAVE_RSEQ
 	  This symbol should be selected by an architecture if it
 	  supports an implementation of restartable sequences.
 
+config HAVE_RUST
+	bool
+	help
+	  This symbol should be selected by an architecture if it
+	  supports Rust.
+
 config HAVE_FUNCTION_ARG_ACCESS_API
 	bool
 	help
@@ -774,7 +780,7 @@ config HAVE_ARCH_WITHIN_STACK_FRAMES
 	  and similar) by implementing an inline arch_within_stack_frames(),
 	  which is used by CONFIG_HARDENED_USERCOPY.
 
-config HAVE_CONTEXT_TRACKING
+config HAVE_CONTEXT_TRACKING_USER
 	bool
 	help
 	  Provide kernel/user boundaries probes necessary for subsystems
@@ -782,10 +788,10 @@ config HAVE_CONTEXT_TRACKING
 	  Syscalls need to be wrapped inside user_exit()-user_enter(), either
 	  optimized behind static key or through the slow path using TIF_NOHZ
 	  flag. Exceptions handlers must be wrapped as well. Irqs are already
-	  protected inside rcu_irq_enter/rcu_irq_exit() but preemption or signal
+	  protected inside ct_irq_enter/ct_irq_exit() but preemption or signal
 	  handling on irq exit still need to be protected.
 
-config HAVE_CONTEXT_TRACKING_OFFSTACK
+config HAVE_CONTEXT_TRACKING_USER_OFFSTACK
 	bool
 	help
 	  Architecture neither relies on exception_enter()/exception_exit()
@@ -797,7 +803,7 @@ config HAVE_CONTEXT_TRACKING_OFFSTACK
 
 	  - Critical entry code isn't preemptible (or better yet:
 	    not interruptible).
-	  - No use of RCU read side critical sections, unless rcu_nmi_enter()
+	  - No use of RCU read side critical sections, unless ct_nmi_enter()
 	    got called.
 	  - No use of instrumentation, unless instrumentation_begin() got
 	    called.
@@ -1396,6 +1402,9 @@ config ARCH_HAS_ELFCORE_COMPAT
 config ARCH_HAS_PARANOID_L1D_FLUSH
 	bool
 
+config ARCH_HAVE_TRACE_MMIO_ACCESS
+	bool
+
 config DYNAMIC_SIGFRAME
 	bool
 
diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c
index ec20c1004abf..ef427a6bdd1a 100644
--- a/arch/alpha/mm/fault.c
+++ b/arch/alpha/mm/fault.c
@@ -155,6 +155,10 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index bdb7e190a294..f5a936496f06 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -82,7 +82,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
 /*
  * __fls: Similar to fls, but zero based (0-31)
  */
-static inline __attribute__ ((const)) int __fls(unsigned long x)
+static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
 {
 	if (!x)
 		return 0;
@@ -131,7 +131,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
 /*
  * __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
  */
-static inline __attribute__ ((const)) int __fls(unsigned long x)
+static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
 {
 	/* FLS insn has exactly same semantics as the API */
 	return	__builtin_arc_fls(x);
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index d947473f1e6d..6c22a53711e9 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -393,7 +393,7 @@ irqreturn_t do_IPI(int irq, void *dev_id)
  * API called by platform code to hookup arch-common ISR to their IPI IRQ
  *
  * Note: If IPI is provided by platform (vs. say ARC MCIP), their intc setup/map
- * function needs to call call irq_set_percpu_devid() for IPI IRQ, otherwise
+ * function needs to call irq_set_percpu_devid() for IPI IRQ, otherwise
  * request_percpu_irq() below will fail
  */
 static DEFINE_PER_CPU(int, ipi_dev);
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 5446967ea98d..55c6de138eae 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -750,7 +750,7 @@ static inline void arc_slc_enable(void)
  *  -In SMP, if hardware caches are coherent
  *
  * There's a corollary case, where kernel READs from a userspace mapped page.
- * If the U-mapping is not congruent to to K-mapping, former needs flushing.
+ * If the U-mapping is not congruent to K-mapping, former needs flushing.
  */
 void flush_dcache_page(struct page *page)
 {
@@ -910,7 +910,7 @@ EXPORT_SYMBOL(flush_icache_range);
  * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
  *    However in one instance, when called by kprobe (for a breakpt in
  *    builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
- *    use a paddr to index the cache (despite VIPT). This is fine since since a
+ *    use a paddr to index the cache (despite VIPT). This is fine since a
  *    builtin kernel page will not have any virtual mappings.
  *    kprobe on loadable module will be kernel vaddr.
  */
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index dad27e4d69ff..5ca59a482632 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -146,6 +146,10 @@ void do_page_fault(unsigned long address, struct pt_regs *regs)
 		return;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	/*
 	 * Fault retry nuances, mmap_lock already relinquished by core mm
 	 */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7630ba9cb6cc..e86948d66415 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -84,7 +84,7 @@ config ARM
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
 	select HAVE_ARM_SMCCC if CPU_V7
 	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_BUILDTIME_MCOUNT_SORT
 	select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
@@ -116,6 +116,7 @@ config ARM
 	select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_RSEQ
+	select HAVE_RUST if CPU_32v6 || CPU_32v6K
 	select HAVE_STACKPROTECTOR
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_UID16
diff --git a/arch/arm/arm-soc-for-next-contents.txt b/arch/arm/arm-soc-for-next-contents.txt
new file mode 100644
index 000000000000..3e5fb3fcb70c
--- /dev/null
+++ b/arch/arm/arm-soc-for-next-contents.txt
@@ -0,0 +1,28 @@
+arm/soc
+
+arm/dt
+
+arm/drivers
+
+arm/defconfig
+
+arm/late
+
+arm/fixes
+	<no branch> (7c7eaeefb0ae226da9233d5db265652d900e1fcb)
+		git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux tags/imx-fixes-5.19
+	<no branch> (44dbdf3bb3f44bf08897ed5f22eb262edcf3d926)
+		git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux tags/scmi-fixes-5.19
+	patch
+		ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15
+		ARM: Fix refcount leak in axxia_boot_secondary
+	<no branch> (680c0aee97690c3f595e074a5f677599aac5d26b)
+		https://github.com/chesterlintw/linux-s32g tags/s32g2-fixes-5.19
+	<no branch> (37d838de369b07b596c19ff3662bf0293fdb09ee)
+		https://github.com/Broadcom/stblinux tags/arm-soc/for-5.19/drivers-fixes
+	<no branch> (46d6e11320d21dc40fce229ab3504125847de27e)
+		https://github.com/Broadcom/stblinux tags/arm-soc/for-5.19/maintainers-fixes
+	patch
+		bus: bt1-apb: Don't print error on -EPROBE_DEFER
+		bus: bt1-axi: Don't print error on -EPROBE_DEFER
+
diff --git a/arch/arm/boot/bootp/bootp.lds b/arch/arm/boot/bootp/bootp.lds
index fc54394f4340..160128186bf8 100644
--- a/arch/arm/boot/bootp/bootp.lds
+++ b/arch/arm/boot/bootp/bootp.lds
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  *  linux/arch/arm/boot/bootp/bootp.lds
  *
  *  Copyright (C) 2000-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 OUTPUT_ARCH(arm)
 ENTRY(_start)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 184899808ee7..38d9c60aece7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
 	bcm47094-luxul-xwr-3150-v1.dtb \
 	bcm47094-netgear-r8500.dtb \
 	bcm47094-phicomm-k3.dtb \
+	bcm53015-meraki-mr26.dtb \
 	bcm53016-meraki-mr32.dtb \
 	bcm94708.dtb \
 	bcm94709.dtb \
@@ -182,7 +183,13 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
 dtb-$(CONFIG_ARCH_BRCMSTB) += \
 	bcm7445-bcm97445svmb.dtb
 dtb-$(CONFIG_ARCH_BCMBCA) += \
-	bcm947622.dtb
+	bcm947622.dtb \
+	bcm963148.dtb \
+	bcm963178.dtb \
+	bcm96756.dtb \
+	bcm96846.dtb \
+	bcm96855.dtb \
+	bcm96878.dtb
 dtb-$(CONFIG_ARCH_CLPS711X) += \
 	ep7211-edb7211.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += \
@@ -550,6 +557,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-apalis-eval.dtb \
 	imx6q-apalis-ixora.dtb \
 	imx6q-apalis-ixora-v1.1.dtb \
+	imx6q-apalis-ixora-v1.2.dtb \
 	imx6q-apf6dev.dtb \
 	imx6q-arm2.dtb \
 	imx6q-b450v3.dtb \
@@ -741,8 +749,12 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-cl-som-imx7.dtb \
 	imx7d-colibri-aster.dtb \
 	imx7d-colibri-emmc-aster.dtb \
+	imx7d-colibri-emmc-iris.dtb \
+	imx7d-colibri-emmc-iris-v2.dtb \
 	imx7d-colibri-emmc-eval-v3.dtb \
 	imx7d-colibri-eval-v3.dtb \
+	imx7d-colibri-iris.dtb \
+	imx7d-colibri-iris-v2.dtb \
 	imx7d-flex-concentrator.dtb \
 	imx7d-flex-concentrator-mfg.dtb \
 	imx7d-mba7.dtb \
@@ -762,6 +774,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-zii-rpu2.dtb \
 	imx7s-colibri-aster.dtb \
 	imx7s-colibri-eval-v3.dtb \
+	imx7s-colibri-iris.dtb \
+	imx7s-colibri-iris-v2.dtb \
 	imx7s-mba7.dtb \
 	imx7s-warp.dtb
 dtb-$(CONFIG_SOC_IMX7ULP) += \
@@ -1586,7 +1600,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-lenovo-hr630.dtb \
 	aspeed-bmc-lenovo-hr855xg2.dtb \
 	aspeed-bmc-microsoft-olympus.dtb \
-	aspeed-bmc-nuvia-dc-scm.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mihawk.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
@@ -1599,6 +1612,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-opp-witherspoon.dtb \
 	aspeed-bmc-opp-zaius.dtb \
 	aspeed-bmc-portwell-neptune.dtb \
+	aspeed-bmc-qcom-dc-scm-v1.dtb \
 	aspeed-bmc-quanta-q71l.dtb \
 	aspeed-bmc-quanta-s6q.dtb \
 	aspeed-bmc-supermicro-x11spi.dtb \
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 3b0675a1c460..4be9887033f9 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -154,7 +154,7 @@ pcie@fbc00000 {
 			reg = <0x0 0xfbc00000 0x0 0x100000>;
 			interrupt-map-mask = <0xf800 0 0 7>;
 			/* Add legacy interrupts for SATA devices only */
-			interrupt-map =	<0x4000 0 0 1 &gic 0 43 4>,
+			interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
 					<0x4800 0 0 1 &gic 0 44 4>;
 
 			/* 32 bit non prefetchable memory space */
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 9a8698bd2852..32d397b3950b 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM33XX SoC
  *
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index de33c4f89f33..cb316135bc7c 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for am3517 SoC
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include "omap3.dtsi"
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 61a1d88f9df6..8613355bbd5e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for AM4372 SoC
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 7da718abbd85..29936bfbeeb7 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -168,26 +168,24 @@ tx_red {
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		keyswitch_in {
+		key-switch-in {
 			label = "keyswitch_in";
 			gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
 			linux,code = <28>;
 			wakeup-source;
 		};
 
-		error_in {
+		key-error-in {
 			label = "error_in";
 			gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
 			linux,code = <29>;
 			wakeup-source;
 		};
 
-		btn {
+		key-s {
 			label = "btn";
 			gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
 			linux,code = <31>;
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
index d20d95359b28..042a9cc920c6 100644
--- a/arch/arm/boot/dts/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -1,10 +1,5 @@
-/*
- * Axis ARTPEC-6 development board.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Axis ARTPEC-6 development board.
 
 /dts-v1/;
 #include "artpec6.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 1d24b394ea4c..a497dd135491 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -5,7 +5,7 @@
 
 / {
 	model = "AST2500 EVB";
-	compatible = "aspeed,ast2500";
+	compatible = "aspeed,ast2500-evb", "aspeed,ast2500";
 
 	aliases {
 		serial4 = &uart5;
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
index dd7148060c4a..d0a5c2ff0fec 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
@@ -5,6 +5,7 @@
 
 / {
 	model = "AST2600 A1 EVB";
+	compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600";
 
 	/delete-node/regulator-vcc-sdhci0;
 	/delete-node/regulator-vcc-sdhci1;
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 5a6063bd4508..c698e6538269 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -8,7 +8,7 @@
 
 / {
 	model = "AST2600 EVB";
-	compatible = "aspeed,ast2600";
+	compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600";
 
 	aliases {
 		serial4 = &uart5;
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
index 3395de96ee11..2e8b87783717 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
@@ -6,7 +6,7 @@
 
 / {
 	model = "Qualcomm Centriq 2400  REP AST2520";
-	compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500";
+	compatible = "qcom,centriq2400-rep-bmc", "aspeed,ast2500";
 
 	chosen {
 		stdout-path = &uart5;
diff --git a/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts b/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
deleted file mode 100644
index f4a97cfb0f23..000000000000
--- a/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
-
-/dts-v1/;
-
-#include "aspeed-g6.dtsi"
-
-/ {
-	model = "Nuvia DC-SCM BMC";
-	compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600";
-
-	aliases {
-		serial4 = &uart5;
-	};
-
-	chosen {
-		stdout-path = &uart5;
-		bootargs = "console=ttyS4,115200n8";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x40000000>;
-	};
-};
-
-&mdio3 {
-	status = "okay";
-
-	ethphy3: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
-};
-
-&mac2 {
-	status = "okay";
-
-	/* Bootloader sets up the MAC to insert delay */
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy3>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rgmii3_default>;
-};
-
-&mac3 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rmii4_default>;
-
-	use-ncsi;
-};
-
-&rtc {
-	status = "okay";
-};
-
-&fmc {
-	status = "okay";
-
-	flash@0 {
-		status = "okay";
-		m25p,fast-read;
-		label = "bmc";
-		spi-max-frequency = <133000000>;
-#include "openbmc-flash-layout-64.dtsi"
-	};
-
-	flash@1 {
-		status = "okay";
-		m25p,fast-read;
-		label = "alt-bmc";
-		spi-max-frequency = <133000000>;
-#include "openbmc-flash-layout-64-alt.dtsi"
-	};
-};
-
-&spi1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_spi1_default>;
-
-	flash@0 {
-		status = "okay";
-		m25p,fast-read;
-		label = "bios";
-		spi-max-frequency = <133000000>;
-	};
-};
-
-&gpio0 {
-	gpio-line-names =
-	/*A0-A7*/	"","","","","","","","",
-	/*B0-B7*/	"BMC_FLASH_MUX_SEL","","","","","","","",
-	/*C0-C7*/	"","","","","","","","",
-	/*D0-D7*/	"","","","","","","","",
-	/*E0-E7*/	"","","","","","","","",
-	/*F0-F7*/	"","","","","","","","",
-	/*G0-G7*/	"","","","","","","","",
-	/*H0-H7*/	"","","","","","","","",
-	/*I0-I7*/	"","","","","","","","",
-	/*J0-J7*/	"","","","","","","","",
-	/*K0-K7*/	"","","","","","","","",
-	/*L0-L7*/	"","","","","","","","",
-	/*M0-M7*/	"","","","","","","","",
-	/*N0-N7*/	"BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
-	/*O0-O7*/	"JTAG_MUX_A","JTAG_MUX_B","","","","","","",
-	/*P0-P7*/	"","","","","","","","",
-	/*Q0-Q7*/	"","","","","","","","",
-	/*R0-R7*/	"","","","","","","","",
-	/*S0-S7*/	"","","","","","","","",
-	/*T0-T7*/	"","","","","","","","",
-	/*U0-U7*/	"","","","","","","","",
-	/*V0-V7*/	"","","","SCMFPGA_SPARE_GPIO1_3V3",
-			"SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
-			"SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
-	/*W0-W7*/	"","","","","","","","",
-	/*X0-X7*/	"","","","","","","","",
-	/*Y0-Y7*/	"","","","","","","","",
-	/*Z0-Z7*/	"","","","","","","","",
-	/*AA0-AA7*/	"","","","","","","","",
-	/*AB0-AB7*/	"","","","","","","","",
-	/*AC0-AC7*/	"","","","","","","","";
-};
-
-&gpio1 {
-	gpio-line-names =
-	/*A0-A7*/	"GPI_1_BMC_1V8","","","","","",
-			"SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
-	/*B0-B7*/	"SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
-			"SCMFPGA_SPARE_GPIO5_1V8","","","","","",
-	/*C0-C7*/	"","","","","","","","",
-	/*D0-D7*/	"","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
-			"","TPM2_PIRQ_N","TPM2_RST_N","",
-	/*E0-E7*/	"","","","","","","","";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c4 {
-	status = "okay";
-};
-
-&i2c5 {
-	status = "okay";
-};
-
-&i2c6 {
-	status = "okay";
-};
-
-&i2c7 {
-	status = "okay";
-};
-
-&i2c8 {
-	status = "okay";
-};
-
-&i2c9 {
-	status = "okay";
-};
-
-&i2c10 {
-	status = "okay";
-};
-
-&i2c12 {
-	status = "okay";
-};
-
-&i2c13 {
-	status = "okay";
-};
-
-&i2c14 {
-	status = "okay";
-};
-
-&i2c15 {
-	status = "okay";
-};
-
-&vhub {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
index 61bc74b423cf..a5e64ccc2b3a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
@@ -24,17 +24,17 @@ memory@80000000 {
 	leds {
 		compatible = "gpio-leds";
 		postcode0 {
-			label="BMC_UP";
+			label = "BMC_UP";
 			gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 		postcode1 {
-			label="BMC_HB";
+			label = "BMC_HB";
 			gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 		postcode2 {
-			label="FAULT";
+			label = "FAULT";
 			gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 		};
 		// postcode3-7 are GPIOH3-H7
diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
new file mode 100644
index 000000000000..259ef3f54c5c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+	model = "Qualcomm DC-SCM V1 BMC";
+	compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+};
+
+&mdio3 {
+	status = "okay";
+
+	ethphy3: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mac2 {
+	status = "okay";
+
+	/* Bootloader sets up the MAC to insert delay */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy3>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rmii4_default>;
+
+	use-ncsi;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+
+	flash@1 {
+		status = "okay";
+		m25p,fast-read;
+		label = "alt-bmc";
+		spi-max-frequency = <133000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+	};
+};
+
+&spi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default>;
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bios";
+		spi-max-frequency = <133000000>;
+	};
+};
+
+&gpio0 {
+	gpio-line-names =
+	/*A0-A7*/	"","","","","","","","",
+	/*B0-B7*/	"BMC_FLASH_MUX_SEL","","","","","","","",
+	/*C0-C7*/	"","","","","","","","",
+	/*D0-D7*/	"","","","","","","","",
+	/*E0-E7*/	"","","","","","","","",
+	/*F0-F7*/	"","","","","","","","",
+	/*G0-G7*/	"","","","","","","","",
+	/*H0-H7*/	"","","","","","","","",
+	/*I0-I7*/	"","","","","","","","",
+	/*J0-J7*/	"","","","","","","","",
+	/*K0-K7*/	"","","","","","","","",
+	/*L0-L7*/	"","","","","","","","",
+	/*M0-M7*/	"","","","","","","","",
+	/*N0-N7*/	"BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
+	/*O0-O7*/	"JTAG_MUX_A","JTAG_MUX_B","","","","","","",
+	/*P0-P7*/	"","","","","","","","",
+	/*Q0-Q7*/	"","","","","","","","",
+	/*R0-R7*/	"","","","","","","","",
+	/*S0-S7*/	"","","","","","","","",
+	/*T0-T7*/	"","","","","","","","",
+	/*U0-U7*/	"","","","","","","","",
+	/*V0-V7*/	"","","","SCMFPGA_SPARE_GPIO1_3V3",
+			"SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
+			"SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
+	/*W0-W7*/	"","","","","","","","",
+	/*X0-X7*/	"","","","","","","","",
+	/*Y0-Y7*/	"","","","","","","","",
+	/*Z0-Z7*/	"","","","","","","","",
+	/*AA0-AA7*/	"","","","","","","","",
+	/*AB0-AB7*/	"","","","","","","","",
+	/*AC0-AC7*/	"","","","","","","","";
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*A0-A7*/	"GPI_1_BMC_1V8","","","","","",
+			"SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
+	/*B0-B7*/	"SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
+			"SCMFPGA_SPARE_GPIO5_1V8","","","","","",
+	/*C0-C7*/	"","","","","","","","",
+	/*D0-D7*/	"","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
+			"","TPM2_PIRQ_N","TPM2_RST_N","",
+	/*E0-E7*/	"","","","","","","","";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
index 69e1bd256271..46cbba6305b8 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts
@@ -65,19 +65,19 @@ leds {
 		compatible = "gpio-leds";
 
 		BMC_HEARTBEAT_N {
-			label="BMC_HEARTBEAT_N";
+			label = "BMC_HEARTBEAT_N";
 			gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		BMC_LED_STATUS_AMBER_N {
-			label="BMC_LED_STATUS_AMBER_N";
+			label = "BMC_LED_STATUS_AMBER_N";
 			gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
 
 		FM_ID_LED_N {
-			label="FM_ID_LED_N";
+			label = "FM_ID_LED_N";
 			gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts
index 2799b2a1f4d2..224f4d5ac4df 100644
--- a/arch/arm/boot/dts/at91-kizbox3-hs.dts
+++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts
@@ -186,7 +186,7 @@ id_usba {
 
 &pioA {
 	pinctrl_key_gpio_default: key_gpio_default {
-		pinmux=  <PIN_PA22__GPIO>,
+		pinmux = <PIN_PA22__GPIO>,
 		<PIN_PA24__GPIO>,
 		<PIN_PA26__GPIO>,
 		<PIN_PA29__GPIO>,
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
index 7719ea3d4933..886bc855daa4 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -85,7 +85,7 @@ gpio_keys {
 		sw1 {
 			label = "SW1";
 			gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
-			linux,code=<KEY_PROG1>;
+			linux,code = <KEY_PROG1>;
 			wakeup-source;
 		};
 	};
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index a4623cc67cc1..e87c4990bf5d 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -15,7 +15,7 @@ / {
 	compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
 
 	aliases {
-		i2c0	= &i2c0;
+		i2c0 = &i2c0;
 	};
 
 	clocks {
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 08f0d4b995ff..b1c390ae5f98 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -21,8 +21,8 @@ aliases {
 		serial0 = &uart1;	/* DBGU */
 		serial1 = &uart4;	/* mikro BUS 1 */
 		serial2 = &uart2;	/* mikro BUS 2 */
-		i2c1	= &i2c1;
-		i2c2	= &i2c3;
+		i2c1 = &i2c1;
+		i2c2 = &i2c3;
 	};
 
 	chosen {
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
index 5e8755f22784..48e85fc3d998 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
@@ -19,7 +19,7 @@ aliases {
 		serial1 = &uart6;	/* BT */
 		serial2 = &uart5;	/* mikro BUS 2 */
 		serial3 = &uart3;	/* mikro BUS 1 */
-		i2c1	= &i2c1;
+		i2c1 = &i2c1;
 	};
 
 	chosen {
diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 806eb1d911d7..5ff692ea8a20 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -24,8 +24,8 @@ aliases {
 		serial1 = &uart1;	/* mikro BUS 3 */
 		serial3 = &uart3;	/* mikro BUS 2 */
 		serial5 = &uart7;	/* flx2 */
-		i2c0	= &i2c0;
-		i2c1	= &i2c1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 
 	chosen {
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 8ed58af01391..64c3e63de179 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -20,9 +20,9 @@ / {
 
 	aliases {
 		serial0 = &uart0;	/* DBGU */
-		i2c0	= &i2c0;	/* mikroBUS 1 */
-		i2c1	= &i2c1;	/* XPRO EXT1 */
-		i2c2	= &i2c2;
+		i2c0 = &i2c0;	/* mikroBUS 1 */
+		i2c1 = &i2c1;	/* XPRO EXT1 */
+		i2c2 = &i2c2;
 	};
 
 	chosen {
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index cdfe891f9a9e..5959bf0c2fa3 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -205,10 +205,10 @@ vdd_1v35_reg: REG_DCDC1 {
 
 							regulator-state-mem {
 								regulator-on-in-suspend;
-								regulator-suspend-min-microvolt=<1400000>;
-								regulator-suspend-max-microvolt=<1400000>;
+								regulator-suspend-min-microvolt = <1400000>;
+								regulator-suspend-max-microvolt = <1400000>;
 								regulator-changeable-in-suspend;
-								regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>;
+								regulator-mode = <ACT8945A_REGULATOR_MODE_LOWPOWER>;
 							};
 						};
 
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi
index 3bcf4e0a3c85..f13ef80b6637 100644
--- a/arch/arm/boot/dts/axm5516-cpus.dtsi
+++ b/arch/arm/boot/dts/axm5516-cpus.dtsi
@@ -73,7 +73,7 @@ CPU0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x00>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -81,7 +81,7 @@ CPU1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x01>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -89,7 +89,7 @@ CPU2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x02>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -97,7 +97,7 @@ CPU3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x03>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -105,7 +105,7 @@ CPU4: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x100>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -113,7 +113,7 @@ CPU5: cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x101>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -121,7 +121,7 @@ CPU6: cpu@102 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x102>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -129,7 +129,7 @@ CPU7: cpu@103 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x103>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -137,7 +137,7 @@ CPU8: cpu@200 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x200>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -145,7 +145,7 @@ CPU9: cpu@201 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x201>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -153,7 +153,7 @@ CPU10: cpu@202 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x202>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -161,7 +161,7 @@ CPU11: cpu@203 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x203>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -169,7 +169,7 @@ CPU12: cpu@300 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x300>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -177,7 +177,7 @@ CPU13: cpu@301 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x301>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -185,7 +185,7 @@ CPU14: cpu@302 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x302>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 
@@ -193,7 +193,7 @@ CPU15: cpu@303 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x303>;
-			clock-frequency= <1400000000>;
+			clock-frequency = <1400000000>;
 			cpu-release-addr = <0>; // Fixed by the boot loader
 		};
 	};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 6197e7d80e3b..53696078bbf0 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2013 Broadcom Corporation
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts
index be468f4adc37..1854cd907a1b 100644
--- a/arch/arm/boot/dts/bcm21664-garnet.dts
+++ b/arch/arm/boot/dts/bcm21664-garnet.dts
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index cc58f2b926b9..2684c37cb3a0 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts
index f4d2fc20397c..82c5ea138e57 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts
@@ -31,9 +31,9 @@ &expgpio {
 			  "",
 			  "GLOBAL_RESET",
 			  "VDD_SD_IO_SEL",
-			  "CAM_GPIO",
+			  "GLOBAL_SHUTDOWN",
 			  "SD_PWR_ON",
-			  "SD_OC_N";
+			  "SHUTDOWN_REQUEST";
 };
 
 &genet_mdio {
diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi
index ca266c5d9f9b..98817a6675b9 100644
--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi
@@ -69,6 +69,10 @@ blconfig: nvram@0 {
 	};
 };
 
+&v3d {
+	clocks = <&firmware_clocks 5>;
+};
+
 &vchiq {
 	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 };
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 89af57482bc8..20e6771e8b1f 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -601,6 +601,17 @@ genet_mdio: mdio@e14 {
 				#size-cells = <0x0>;
 			};
 		};
+
+		v3d: gpu@7ec00000 {
+			compatible = "brcm,2711-v3d";
+			reg = <0x0 0x7ec00000 0x4000>,
+			      <0x0 0x7ec04000 0x4000>;
+			reg-names = "hub", "core0";
+
+			power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
+			resets = <&pm BCM2835_RESET_V3D>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 };
 
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index ead6e9804dbf..fce3d5260b00 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Broadcom Corporation
 
 /dts-v1/;
 
@@ -31,22 +21,22 @@ uart@3e000000 {
 	};
 
 	i2c@3e016000 {
-		status="okay";
+		status = "okay";
 		clock-frequency = <400000>;
 	};
 
 	i2c@3e017000 {
-		status="okay";
+		status = "okay";
 		clock-frequency = <400000>;
 	};
 
 	i2c@3e018000 {
-		status="okay";
+		status = "okay";
 		clock-frequency = <400000>;
 	};
 
 	i2c@3500d000 {
-		status="okay";
+		status = "okay";
 		clock-frequency = <100000>;
 
 		pmu: pmu@8 {
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index c113661a6668..d2d9c6e67f39 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -50,9 +50,9 @@ cpu_thermal: cpu-thermal {
 
 			trips {
 				cpu-crit {
-					temperature	= <90000>;
-					hysteresis	= <0>;
-					type		= "critical";
+					temperature = <90000>;
+					hysteresis = <0>;
+					type = "critical";
 				};
 			};
 
@@ -352,8 +352,6 @@ dpi: dpi@7e208000 {
 			clocks = <&clocks BCM2835_CLOCK_VPU>,
 				 <&clocks BCM2835_CLOCK_DPI>;
 			clock-names = "core", "pixel";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
index 8ed403767540..09ee3e46c0cc 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
@@ -70,19 +70,19 @@ usb2 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
index 667b118ba4ee..32619c6045d3 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
@@ -54,25 +54,25 @@ usb3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		brightness {
+		button-brightness {
 			label = "Backlight";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
index d659e409a17e..a658b9b7bcec 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
@@ -104,33 +104,33 @@ wireless1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
-		aoss {
+		button-aoss {
 			label = "AOSS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Commit mode set by switch? */
-		mode {
+		button-mode {
 			label = "Mode";
 			linux,code = <KEY_SETUP>;
 			gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Switch: AP mode */
-		sw_ap {
+		button-sw-ap {
 			label = "AP";
 			linux,code = <BTN_0>;
 			gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
 		};
 
-		eject {
+		button-eject {
 			label = "USB eject";
 			linux,code = <KEY_EJECTCD>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index ff31ce45831a..f8f53457dd43 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -100,33 +100,33 @@ wireless1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
-		aoss {
+		button-aoss {
 			label = "AOSS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Commit mode set by switch? */
-		mode {
+		button-mode {
 			label = "Mode";
 			linux,code = <KEY_SETUP>;
 			gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Switch: AP mode */
-		sw_ap {
+		button-sw-ap {
 			label = "AP";
 			linux,code = <BTN_0>;
 			gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
 		};
 
-		eject {
+		button-eject {
 			label = "USB eject";
 			linux,code = <KEY_EJECTCD>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
index 5bac1e15775a..0ed25bf71f0d 100644
--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
@@ -29,13 +29,13 @@ nvram@1c080000 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
index cd797b4202ad..f1412ba83def 100644
--- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
@@ -25,13 +25,13 @@ memory@0 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
index 5b4a481be4f4..14ee410183af 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
@@ -45,7 +45,7 @@ status {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index c81944cd6d0b..600ab087f5e5 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -52,7 +52,7 @@ status {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 43a5d675dd67..fd6d8d2a4456 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -63,19 +63,19 @@ wireless {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 4c60eda296d9..76fc1099d47d 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -59,19 +59,19 @@ wireless {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 9ca6d1b2590d..6bcdfb73cb9e 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -94,19 +94,19 @@ wan-red {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index 0e273c598732..ca47cc4f2ba1 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -60,13 +60,13 @@ usb3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index d00495a8b6fc..0edc2543e568 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -91,26 +91,26 @@ wireless1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		aoss {
+		button-aoss {
 			label = "AOSS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Switch device mode? */
-		mode {
+		button-mode {
 			label = "Mode";
 			linux,code = <KEY_SETUP>;
 			gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
 		};
 
-		eject {
+		button-eject {
 			label = "USB eject";
 			linux,code = <KEY_EJECTCD>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 8b1a05a0f1a1..1f0998f34afd 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -96,7 +96,7 @@ wireless1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
index 68aaf0af3945..c8c02377543b 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
@@ -45,7 +45,7 @@ status {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
index 9316a36434f7..3b35a7af4b1c 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
@@ -94,7 +94,7 @@ lan1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
index 12e34a0439b4..19a7971b5a00 100644
--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
@@ -77,13 +77,13 @@ usb2-port2 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index 7546c8d07bcd..f52a75c4ca09 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -47,16 +47,14 @@ wan {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index beae9eab9cb8..5ff6c588e16e 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -77,42 +77,40 @@ wireless-white {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		power {
+		button-power {
 			label = "Power";
 			linux,code = <KEY_POWER>;
 			gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
 		};
 
-		aoss {
+		button-aoss {
 			label = "AOSS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Commit mode set by switch? */
-		mode {
+		button-mode {
 			label = "Mode";
 			linux,code = <KEY_SETUP>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Switch: AP mode */
-		sw_ap {
+		button-sw-ap {
 			label = "AP";
 			linux,code = <BTN_0>;
 			gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
 		};
 
-		eject {
+		button-eject {
 			label = "USB eject";
 			linux,code = <KEY_EJECTCD>;
 			gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
index 7879f7d7d9c3..99253fd7adb3 100644
--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
@@ -29,16 +29,14 @@ nvram@1c080000 {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
index 56d309dbc6b0..de961fbb6200 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
@@ -72,22 +72,20 @@ usb2 {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
index 89f992af61d1..087f7f60de18 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -99,28 +99,26 @@ usb2 {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
 		};
 
-		brightness {
+		button-brightness {
 			label = "Backlight";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
index c2a266a439d0..11d1068160da 100644
--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -77,16 +77,14 @@ power {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
index d8503758342b..a5fec56d11c0 100644
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
@@ -72,25 +72,25 @@ wps {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
 		};
 
-		reset {
+		button-reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
 		};
 
-		wifi {
+		button-wifi {
 			label = "Wi-Fi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
 		};
 
-		led {
+		button-led {
 			label = "Backlight";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 60bfd52ee677..2c38b642a8b8 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -86,20 +86,20 @@ usb3-white {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
 		/* Switch: router / extender */
-		extender {
+		button-extender {
 			label = "Extender";
 			linux,code = <BTN_0>;
 			gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 9bef6b9bfa8d..86c7cc0fa70e 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -30,19 +30,19 @@ nvram@1c080000 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 				label = "WiFi";
 				linux,code = <KEY_RFKILL>;
 				gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
 		};
 
-		reset {
+		button-reset {
 				label = "Reset";
 				linux,code = <KEY_RESTART>;
 				gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
index b51a0ee7e584..9ad15bcae1ca 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
@@ -49,7 +49,7 @@ usb3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
index 6fa101f0a90d..ee24d3768536 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
@@ -43,7 +43,7 @@ status	{
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
index b959a9504eea..6549d07b9887 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
@@ -49,7 +49,7 @@ usb3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
index b0d8a688141d..654fcce9fded 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
@@ -34,10 +34,8 @@ status	{
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
index cbe8c8e4a301..bf053a2fcc7c 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -89,7 +89,7 @@ status	{
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
index 9efcb2424228..78a90dd57a4e 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
@@ -67,7 +67,7 @@ status	{
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index 42097a4c2659..f850dce37b20 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -65,25 +65,25 @@ usb3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		brightness {
+		button-brightness {
 			label = "Backlight";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
 		};
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
index a2566ad4619c..3bf6e24978ac 100644
--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
@@ -22,7 +22,7 @@ memory@0 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
index 57ca1cfaecd8..e20b6d2eb274 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
@@ -39,7 +39,7 @@ system {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
index 2e1a7e382cb7..9d863570fcf3 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
@@ -49,7 +49,7 @@ pcie0_leds {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index 07eb3a8287d6..55b92645b0f1 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -59,19 +59,19 @@ pcie0_leds {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		rfkill {
+		button-rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi
index c016e12b7372..2df04528af82 100644
--- a/arch/arm/boot/dts/bcm47622.dtsi
+++ b/arch/arm/boot/dts/bcm47622.dtsi
@@ -32,6 +32,7 @@ CA7_1: cpu@1 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		CA7_2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
@@ -39,6 +40,7 @@ CA7_2: cpu@2 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		CA7_3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
@@ -46,6 +48,7 @@ CA7_3: cpu@3 {
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};
+
 		L2_0: l2-cache0 {
 			compatible = "cache";
 		};
@@ -76,6 +79,7 @@ periph_clk: periph-clk {
 			#clock-cells = <0>;
 			clock-frequency = <200000000>;
 		};
+
 		uart_clk: uart-clk {
 			compatible = "fixed-factor-clock";
 			#clock-cells = <0>;
@@ -88,23 +92,23 @@ uart_clk: uart-clk {
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
-		cpu_off = <1>;
-		cpu_on = <2>;
 	};
 
 	axi@81000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0 0x81000000 0x818000>;
+		ranges = <0 0x81000000 0x8000>;
 
 		gic: interrupt-controller@1000 {
 			compatible = "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-			#address-cells = <0>;
 			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 			reg = <0x1000 0x1000>,
-				<0x2000 0x2000>;
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
new file mode 100644
index 000000000000..14f58033efeb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Meraki MR26 / Codename: Venom
+ *
+ * Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708";
+	model = "Meraki MR26";
+
+	memory@0 {
+		reg = <0x00000000 0x08000000>;
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			function = LED_FUNCTION_FAULT;
+			color = <LED_COLOR_ID_AMBER>;
+			gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+			panic-indicator;
+		};
+		led-1 {
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		key-restart {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <50000000>;
+	/delete-property/ clocks;
+};
+
+&uart1 {
+	status = "disabled";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	status = "disabled";
+};
+&gmac2 {
+	status = "disabled";
+};
+&gmac3 {
+	status = "disabled";
+};
+
+&nandcs {
+	nand-ecc-algo = "hw";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+
+		partition@200000 {
+			label = "u-boot-env";
+			reg = <0x200000 0x200000>;
+			/* empty */
+		};
+
+		partition@400000 {
+			label = "u-boot-backup";
+			reg = <0x400000 0x200000>;
+			/* empty */
+		};
+
+		partition@600000 {
+			label = "u-boot-env-backup";
+			reg = <0x600000 0x200000>;
+			/* empty */
+		};
+
+		partition@800000 {
+			label = "ubi";
+			reg = <0x800000 0x7780000>;
+		};
+	};
+};
+
+&srab {
+	status = "okay";
+
+	ports {
+		port@0 {
+			reg = <0>;
+			label = "poe";
+		};
+
+		port@5 {
+			reg = <5>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+
+			fixed-link {
+				speed = <1000>;
+				duplex-full;
+			};
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinmux_i2c>;
+
+	clock-frequency = <100000>;
+
+	ina219@40 {
+		compatible = "ti,ina219"; /* PoE power */
+		reg = <0x40>;
+		shunt-resistor = <60000>; /* = 60 mOhms */
+	};
+
+	eeprom@56 {
+		compatible = "atmel,24c64";
+		reg = <0x56>;
+		pagesize = <32>;
+		read-only;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* it's empty */
+	};
+};
+
+&thermal {
+	status = "disabled";
+	/* does not work, reads 418 degree Celsius */
+};
diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
index daca63f25134..e678bc03d816 100644
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
@@ -47,10 +47,8 @@ sysled2 {
 
 	keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 65f8a759f1e3..5fc1b847f4aa 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -568,9 +568,9 @@ cpu_thermal: cpu-thermal {
 
 			trips {
 				cpu-crit {
-					temperature	= <125000>;
-					hysteresis	= <0>;
-					type		= "critical";
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
 				};
 			};
 
diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi
new file mode 100644
index 000000000000..df5307b6b3af
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63148.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm63148", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		B15_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "brcm,brahma-b15";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B15_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "brcm,brahma-b15";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B15_0>, <&B15_1>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@80030000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x80030000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a15-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xfffe8000 0x8000>;
+
+		uart0: serial@600 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x600 0x20>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+			clock-names = "refclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi
new file mode 100644
index 000000000000..5463443f0762
--- /dev/null
+++ b/arch/arm/boot/dts/bcm63178.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm63178", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CA7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+		CA7_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CA7_0>, <&CA7_1>,
+			<&CA7_2>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+		cpu_off = <1>;
+		cpu_on = <2>;
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x81000000 0x4000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi
new file mode 100644
index 000000000000..ce1b59faf800
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6756.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm6756", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CA7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x3>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CA7_0>, <&CA7_1>,
+			<&CA7_2>, <&CA7_3>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi
new file mode 100644
index 000000000000..e610c102498f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6846.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm6846", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CA7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CA7_0>, <&CA7_1>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+		cpu_off = <1>;
+		cpu_on = <2>;
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x81000000 0x4000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff800000 0x800000>;
+
+		uart0: serial@640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x640 0x1b>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+			clock-names = "refclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi
new file mode 100644
index 000000000000..620f51aee1a2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6855.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm6855", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CA7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi
new file mode 100644
index 000000000000..a7dff596fe1e
--- /dev/null
+++ b/arch/arm/boot/dts/bcm6878.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "brcm,bcm6878", "brcm,bcmbca";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CA7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		CA7_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CA7_0>, <&CA7_1>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
index a76c74b44bba..363009e747b3 100644
--- a/arch/arm/boot/dts/bcm911360_entphn.dts
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -47,10 +47,10 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		hook {
+		button-hook {
 			label = "HOOK";
 			linux,code = <KEY_O>;
 			gpios = <&gpio_asiu 48 0>;
diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts
index b0b8c774a37f..16e70a264faf 100644
--- a/arch/arm/boot/dts/bcm947189acdbmr.dts
+++ b/arch/arm/boot/dts/bcm947189acdbmr.dts
@@ -44,13 +44,13 @@ wps {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
 		};
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts
index dd63a148a16b..4fe3b3653376 100644
--- a/arch/arm/boot/dts/bcm953012er.dts
+++ b/arch/arm/boot/dts/bcm953012er.dts
@@ -47,13 +47,13 @@ memory@0 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wps {
+		button-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		button-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
index 58b7d9fc7574..c54451dde6dd 100644
--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
@@ -13,7 +13,7 @@ keys {
 		autorepeat;
 		poll-interval = <20>;
 
-		reset {
+		button-reset {
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
index 576cfc52567b..1830844c8404 100644
--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
@@ -14,7 +14,7 @@ keys {
 		autorepeat;
 		poll-interval = <20>;
 
-		reset {
+		button-reset {
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts
new file mode 100644
index 000000000000..98f6a6d09f50
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963148.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63148.dtsi"
+
+/ {
+	model = "Broadcom BCM963148 Reference Board";
+	compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts
new file mode 100644
index 000000000000..fa096e9cde23
--- /dev/null
+++ b/arch/arm/boot/dts/bcm963178.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63178.dtsi"
+
+/ {
+	model = "Broadcom BCM963178 Reference Board";
+	compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts
new file mode 100644
index 000000000000..9a4a87ba9c8a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96756.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6756.dtsi"
+
+/ {
+	model = "Broadcom BCM96756 Reference Board";
+	compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts
new file mode 100644
index 000000000000..c70ebccabc19
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96846.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6846.dtsi"
+
+/ {
+	model = "Broadcom BCM96846 Reference Board";
+	compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts
new file mode 100644
index 000000000000..4438152561ac
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96855.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6855.dtsi"
+
+/ {
+	model = "Broadcom BCM96855 Reference Board";
+	compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts
new file mode 100644
index 000000000000..8fbc175cb452
--- /dev/null
+++ b/arch/arm/boot/dts/bcm96878.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6878.dtsi"
+
+/ {
+	model = "Broadcom BCM96878 Reference Board";
+	compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index a92630113f57..8104969c67c1 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <dt-bindings/bus/ti-sysc.h>
 #include <dt-bindings/clock/dm814.h>
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index eb0a95da94b2..649b33194455 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <dt-bindings/bus/ti-sysc.h>
 #include <dt-bindings/clock/dm816.h>
diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi
index cc4878aaa8ea..cfefa670515c 100644
--- a/arch/arm/boot/dts/dra62x.dtsi
+++ b/arch/arm/boot/dts/dra62x.dtsi
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include "dm814x.dtsi"
 
diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
index e75569383dd8..747ff0db90c7 100644
--- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC DSPEVE thermal
  *
  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
index a7077321613f..0a31313065df 100644
--- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for DRA7x SoC IVA thermal
  *
  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
index a9dce919d443..34eea3c048bd 100644
--- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
  *
  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 /*
diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
index e86da7a970b6..b9d040135c5f 100644
--- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
  *
  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 /*
diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi
index 1a49f15f2df2..935e2359f8df 100644
--- a/arch/arm/boot/dts/e60k02.dtsi
+++ b/arch/arm/boot/dts/e60k02.dtsi
@@ -22,14 +22,14 @@ chosen {
 	gpio_keys: gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "Power";
 			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			wakeup-source;
 		};
 
-		cover {
+		key-cover {
 			label = "Cover";
 			gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
 			linux,code = <SW_LID>;
diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi
index 156de653f2cd..27ef9a62b23c 100644
--- a/arch/arm/boot/dts/e70k02.dtsi
+++ b/arch/arm/boot/dts/e70k02.dtsi
@@ -26,14 +26,14 @@ chosen {
 	gpio_keys: gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "Power";
 			gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			wakeup-source;
 		};
 
-		cover {
+		key-cover {
 			label = "Cover";
 			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
 			linux,code = <SW_LID>;
@@ -41,13 +41,13 @@ cover {
 			wakeup-source;
 		};
 
-		pageup {
+		key-pageup {
 			label = "PageUp";
 			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_PAGEUP>;
 		};
 
-		pagedown {
+		key-pagedown {
 			label = "PageDown";
 			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_PAGEDOWN>;
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index 57a028a69373..ce5221c6b358 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -9,11 +9,11 @@ chosen {
 	};
 
 	psci {
-		compatible	= "arm,psci";
-		method		= "smc";
-		cpu_suspend	= <0x84000002>;
-		cpu_off		= <0x84000004>;
-		cpu_on		= <0x84000006>;
+		compatible = "arm,psci";
+		method = "smc";
+		cpu_suspend = <0x84000002>;
+		cpu_off = <0x84000004>;
+		cpu_on = <0x84000006>;
 	};
 
 	soc {
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index a8d8bb0419a0..f23a25cce119 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -33,3 +33,11 @@ &gpio0 {
 &gpio1 {
 	status = "okay";
 };
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 36597f587f46..7f839331a777 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/en7523-clk.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -83,6 +84,13 @@ L2_0: l2-cache0 {
 		};
 	};
 
+	scu: system-controller@1fa20000 {
+		compatible = "airoha,en7523-scu";
+		reg = <0x1fa20000 0x400>,
+		      <0x1fb00000 0x1000>;
+		#clock-cells = <1>;
+	};
+
 	gic: interrupt-controller@9000000 {
 		compatible = "arm,gic-v3";
 		interrupt-controller;
@@ -135,4 +143,62 @@ gpio1: gpio@1fbf0270 {
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
+
+	pcie0: pcie@1fa91000 {
+		compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+		device_type = "pci";
+		reg = <0x1fa91000 0x1000>;
+		reg-names = "port0";
+		linux,pci-domain = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&scu EN7523_CLK_PCIE>;
+		clock-names = "sys_ck0";
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x20000000  0x20000000  0 0x8000000>;
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+				<0 0 0 2 &pcie_intc0 1>,
+				<0 0 0 3 &pcie_intc0 2>,
+				<0 0 0 4 &pcie_intc0 3>;
+		pcie_intc0: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+	};
+
+	pcie1: pcie@1fa92000 {
+		compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+		device_type = "pci";
+		reg = <0x1fa92000 0x1000>;
+		reg-names = "port1";
+		linux,pci-domain = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie_irq";
+		clocks = <&scu EN7523_CLK_PCIE>;
+		clock-names = "sys_ck1";
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x28000000  0x28000000  0 0x8000000>;
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+				<0 0 0 2 &pcie_intc1 1>,
+				<0 0 0 3 &pcie_intc1 2>,
+				<0 0 0 4 &pcie_intc1 3>;
+		pcie_intc1: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/exynos-pinctrl.h
new file mode 100644
index 000000000000..e3a6df95281c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos-pinctrl.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE		0
+#define EXYNOS_PIN_PULL_DOWN		1
+#define EXYNOS_PIN_PULL_UP		3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT0		0
+#define EXYNOS_PIN_PDN_OUT1		1
+#define EXYNOS_PIN_PDN_INPUT		2
+#define EXYNOS_PIN_PDN_PREV		3
+
+/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
+#define EXYNOS4_PIN_DRV_LV1		0
+#define EXYNOS4_PIN_DRV_LV2		2
+#define EXYNOS4_PIN_DRV_LV3		1
+#define EXYNOS4_PIN_DRV_LV4		3
+
+/* Drive strengths for Exynos5260 */
+#define EXYNOS5260_PIN_DRV_LV1		0
+#define EXYNOS5260_PIN_DRV_LV2		1
+#define EXYNOS5260_PIN_DRV_LV4		2
+#define EXYNOS5260_PIN_DRV_LV6		3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
+ * GPIO_HSI block)
+ */
+#define EXYNOS5420_PIN_DRV_LV1		0
+#define EXYNOS5420_PIN_DRV_LV2		1
+#define EXYNOS5420_PIN_DRV_LV3		2
+#define EXYNOS5420_PIN_DRV_LV4		3
+
+#define EXYNOS_PIN_FUNC_INPUT		0
+#define EXYNOS_PIN_FUNC_OUTPUT		1
+#define EXYNOS_PIN_FUNC_2		2
+#define EXYNOS_PIN_FUNC_3		3
+#define EXYNOS_PIN_FUNC_4		4
+#define EXYNOS_PIN_FUNC_5		5
+#define EXYNOS_PIN_FUNC_6		6
+#define EXYNOS_PIN_FUNC_EINT		0xf
+#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 7b429622a288..0ac3f284fbb8 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -357,7 +357,7 @@ &mshc_1 {
 
 &pinctrl_1 {
 	bten: bten-pins {
-		samsung,pins ="gpx1-7";
+		samsung,pins = "gpx1-7";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
 		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index cc30d154ec94..011ba2eff29e 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 #define PIN_IN(_pin, _pull, _drv)					\
 	pin- ## _pin {							\
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 78dad233ff34..326b9e0ed8d3 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -376,7 +376,7 @@ hsotg: hsotg@12480000 {
 			status = "disabled";
 		};
 
-		mshc_0: mshc@12510000 {
+		mshc_0: mmc@12510000 {
 			compatible = "samsung,exynos5420-dw-mshc";
 			reg = <0x12510000 0x1000>;
 			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
@@ -388,7 +388,7 @@ mshc_0: mshc@12510000 {
 			status = "disabled";
 		};
 
-		mshc_1: mshc@12520000 {
+		mshc_1: mmc@12520000 {
 			compatible = "samsung,exynos5420-dw-mshc";
 			reg = <0x12520000 0x1000>;
 			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -400,7 +400,7 @@ mshc_1: mshc@12520000 {
 			status = "disabled";
 		};
 
-		mshc_2: mshc@12530000 {
+		mshc_2: mmc@12530000 {
 			compatible = "samsung,exynos5250-dw-mshc";
 			reg = <0x12530000 0x1000>;
 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts
index 3c0a18b30837..bba85011ecc9 100644
--- a/arch/arm/boot/dts/exynos4210-i9100.dts
+++ b/arch/arm/boot/dts/exynos4210-i9100.dts
@@ -89,21 +89,21 @@ vt_core_15v_reg: regulator-5 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		vol-down {
+		key-vol-down {
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
 			label = "volume down";
 			debounce-interval = <10>;
 		};
 
-		vol-up {
+		key-vol-up {
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
 			label = "volume up";
 			debounce-interval = <10>;
 		};
 
-		power {
+		key-power {
 			gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "power";
@@ -111,7 +111,7 @@ power {
 			wakeup-source;
 		};
 
-		ok {
+		key-ok {
 			gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_OK>;
 			label = "ok";
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index a08ce2f37ea2..5f37b751f700 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,6 +15,7 @@
 #include "exynos4210.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "exynos-mfc-reserved-memory.dtsi"
 
 / {
@@ -46,35 +47,35 @@ mmc_reg: voltage-regulator {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		up {
+		key-up {
 			label = "Up";
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_UP>;
 			wakeup-source;
 		};
 
-		down {
+		key-down {
 			label = "Down";
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_DOWN>;
 			wakeup-source;
 		};
 
-		back {
+		key-back {
 			label = "Back";
 			gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
 			wakeup-source;
 		};
 
-		home {
+		key-home {
 			label = "Home";
 			gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
 			wakeup-source;
 		};
 
-		menu {
+		key-menu {
 			label = "Menu";
 			gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
@@ -86,6 +87,7 @@ leds {
 		compatible = "gpio-leds";
 		status {
 			gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_HEARTBEAT;
 			linux,default-trigger = "heartbeat";
 		};
 	};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 6373009bb727..76f44ae0de46 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -11,7 +11,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_0 {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 01f44d95f671..b8e9dd23fc51 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -180,7 +180,7 @@ panel@0 {
 		vdd3-supply = <&vcclcd_reg>;
 		vci-supply = <&vlcd_reg>;
 		reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
-		power-on-delay= <50>;
+		power-on-delay = <50>;
 		reset-delay = <100>;
 		init-delay = <100>;
 		flip-horizontal;
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
index 03dffc690b79..94122e9c6625 100644
--- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -7,6 +7,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include "exynos4412-midas.dtsi"
 
 / {
@@ -25,8 +26,9 @@ led-controller {
 		pinctrl-1 = <&camera_flash_host>;
 		pinctrl-2 = <&camera_flash_isp>;
 
-		flash-led {
-			label = "flash";
+		led {
+			function = LED_FUNCTION_FLASH;
+			color = <LED_COLOR_ID_WHITE>;
 			led-max-microamp = <520833>;
 			flash-max-microamp = <1012500>;
 			flash-max-timeout-us = <1940000>;
@@ -107,7 +109,7 @@ panel@0 {
 		vdd3-supply = <&lcd_vdd3_reg>;
 		vci-supply = <&ldo25_reg>;
 		reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
-		power-on-delay= <50>;
+		power-on-delay = <50>;
 		reset-delay = <100>;
 		init-delay = <100>;
 		flip-horizontal;
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index a9406280b979..202ab0fee3b7 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -11,6 +11,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos4412-itop-scp-core.dtsi"
@@ -28,7 +29,8 @@ leds {
 		compatible = "gpio-leds";
 
 		led2 {
-			label = "red:system";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 			linux,default-trigger = "heartbeat";
@@ -36,6 +38,7 @@ led2 {
 
 		led3 {
 			label = "red:user";
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
@@ -44,31 +47,31 @@ led3 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		home {
+		key-home {
 			label = "GPIO Key Home";
 			linux,code = <KEY_HOME>;
 			gpios = <&gpx1 1 GPIO_ACTIVE_LOW>;
 		};
 
-		back {
+		key-back {
 			label = "GPIO Key Back";
 			linux,code = <KEY_BACK>;
 			gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
 		};
 
-		sleep {
+		key-sleep {
 			label = "GPIO Key Sleep";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
 		};
 
-		vol-up {
+		key-vol-up {
 			label = "GPIO Key Vol+";
 			linux,code = <KEY_UP>;
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 		};
 
-		vol-down {
+		key-vol-down {
 			label = "GPIO Key Vol-";
 			linux,code = <KEY_DOWN>;
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index 23f50c9be527..b967397a46c5 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -12,11 +12,12 @@
 /dts-v1/;
 #include "exynos4412.dtsi"
 #include "exynos4412-ppmu-common.dtsi"
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/maxim,max77686.h>
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 / {
 	compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 36c369c42b77..a5ad88b897ff 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -9,6 +9,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include "exynos4412-odroid-common.dtsi"
 #include "exynos4412-prime.dtsi"
 
@@ -37,7 +38,8 @@ vbus_otg_reg: regulator-1 {
 	leds {
 		compatible = "gpio-leds";
 		led1 {
-			label = "led1:heart";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpc1 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 1f17cc30ed14..68d589e081bc 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -9,6 +9,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include "exynos4412-odroid-common.dtsi"
 
 / {
@@ -27,13 +28,15 @@ memory@40000000 {
 	leds {
 		compatible = "gpio-leds";
 		led1 {
-			label = "led1:heart";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpc1 0 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 		led2 {
 			label = "led2:mmc0";
+			function = LED_FUNCTION_DISK_ACTIVITY;
 			gpios = <&gpc1 2 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 			linux,default-trigger = "mmc0";
diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi
index 97f131b1014b..7a515b87bc7c 100644
--- a/arch/arm/boot/dts/exynos4412-p4note.dtsi
+++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi
@@ -15,8 +15,8 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/samsung.h>
 #include <dt-bindings/power/summit,smb347-charger.h>
+#include "exynos-pinctrl.h"
 
 / {
 	compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4";
@@ -106,6 +106,16 @@ voltage-regulator-3 {
 		regulator-always-on;
 	};
 
+	panel_vdd: voltage-regulator-4 {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD_ENABLE";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_enable>;
+		gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
 	wlan_pwrseq: sdhci3-pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>;
@@ -216,6 +226,32 @@ power_supply: charger@6 {
 			monitored-battery = <&battery_cell>;
 		};
 	};
+
+	panel {
+		compatible = "samsung,ltl101al01";
+		pinctrl-0 = <&lvds_nshdn>;
+		pinctrl-names = "default";
+		power-supply = <&panel_vdd>;
+		enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>;
+		backlight = <&backlight>;
+
+		port {
+			lcd_ep: endpoint {
+				remote-endpoint = <&fimd_ep>;
+			};
+		};
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-0 = <&led_bl_reset>;
+		pinctrl-names = "default";
+		enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>;
+		pwms = <&pwm 1 78770 0>;
+		brightness-levels = <0 48 128 255>;
+		num-interpolated-steps = <8>;
+		default-brightness-level = <12>;
+	};
 };
 
 &adc {
@@ -295,22 +331,19 @@ &exynos_usbphy {
 };
 
 &fimd {
-	pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
+	pinctrl-0 = <&lcd_clk &lcd_data24>;
 	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 
-	display-timings {
-		timing0 {
-			clock-frequency = <66666666>;
-			hactive = <1280>;
-			vactive = <800>;
-			hfront-porch = <18>;
-			hback-porch = <36>;
-			hsync-len = <16>;
-			vback-porch = <16>;
-			vfront-porch = <4>;
-			vsync-len = <3>;
-			hsync-active = <1>;
+	samsung,invert-vclk;
+
+	port@3 {
+		reg = <3>;
+
+		fimd_ep: endpoint {
+			remote-endpoint = <&lcd_ep>;
 		};
 	};
 };
@@ -687,6 +720,12 @@ tsp_reg_gpio_3: tsp-reg-gpio-3-pins {
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
 	};
 
+	lcd_enable: lcd-enable-pins {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
 	sleep0: sleep-state {
 		PIN_SLP(gpa0-0, INPUT, NONE);
 		PIN_SLP(gpa0-1, OUT0, NONE);
@@ -809,12 +848,24 @@ uart_sel: uart-sel-pins {
 		/* 0 = CP, 1 = AP (serial output) */
 	};
 
+	led_bl_reset: led-bl-reset-pins {
+		samsung,pins = "gpm0-1";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
 	tsp_rst: tsp-rst-pins {
 		samsung,pins = "gpm0-4";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
 	};
 
+	lvds_nshdn: lvds-nshdn-pins {
+		samsung,pins = "gpm0-5";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+	};
+
 	tsp_irq: tsp-irq-pins {
 		samsung,pins = "gpm2-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
@@ -1100,6 +1151,13 @@ &pmu_system_controller {
 	assigned-clock-parents = <&clock CLK_XUSBXTI>;
 };
 
+&pwm {
+	pinctrl-0 = <&pwm1_out>;
+	pinctrl-names = "default";
+	samsung,pwm-outputs = <1>;
+	status = "okay";
+};
+
 &rtc {
 	clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
 	clock-names = "rtc", "rtc_src";
diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index 88b8afd55664..58847d4fa846 100644
--- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 #define PIN_SLP(_pin, _mode, _pull)					\
 	_pin {								\
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 017b26108bb0..04388c575efe 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include "exynos4412.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "FriendlyARM TINY4412 board based on Exynos4412";
@@ -30,6 +31,7 @@ leds {
 
 		led1 {
 			label = "led1";
+			function = LED_FUNCTION_HEARTBEAT;
 			gpios = <&gpm4 0 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 			linux,default-trigger = "heartbeat";
@@ -49,6 +51,7 @@ led3 {
 
 		led4 {
 			label = "led4";
+			function = LED_FUNCTION_DISK_ACTIVITY;
 			gpios = <&gpm4 3 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 			linux,default-trigger = "mmc0";
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 9ce9fb3fc190..c8da0d4b1b33 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -89,7 +89,7 @@ gic: interrupt-controller@10481000 {
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			interrupt-controller;
-			reg =	<0x10481000 0x1000>,
+			reg = <0x10481000 0x1000>,
 				<0x10482000 0x2000>,
 				<0x10484000 0x2000>,
 				<0x10486000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index f7795f2d0f0e..71c0e87d3a1d 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -30,42 +30,42 @@ chosen {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		menu {
+		key-menu {
 			label = "SW-TACT2";
 			gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
 			wakeup-source;
 		};
 
-		home {
+		key-home {
 			label = "SW-TACT3";
 			gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
 			wakeup-source;
 		};
 
-		up {
+		key-up {
 			label = "SW-TACT4";
 			gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_UP>;
 			wakeup-source;
 		};
 
-		down {
+		key-down {
 			label = "SW-TACT5";
 			gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_DOWN>;
 			wakeup-source;
 		};
 
-		back {
+		key-back {
 			label = "SW-TACT6";
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
 			wakeup-source;
 		};
 
-		wakeup {
+		key-wakeup {
 			label = "SW-TACT7";
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 918947a3897e..48732edadff1 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_0 {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index c15ecfc4077d..3d84b9c6dea3 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -32,7 +32,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&power_key_irq &lid_irq>;
 
-		power {
+		power-key {
 			label = "Power";
 			gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index 24609bb20158..5eca10ecd550 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -33,7 +33,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&power_key_irq>, <&lid_irq>;
 
-		power {
+		power-key {
 			label = "Power";
 			gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
index 150607f8103d..43e4a541f479 100644
--- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_0 {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index 6c7814b4372e..f7b923382892 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -6,7 +6,7 @@
  *              https://www.hardkernel.com
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_0 {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 946b791faf85..55b7759682a9 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -42,7 +42,7 @@ oscclk {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		wakeup {
+		key-wakeup {
 			label = "SW-TACT1";
 			gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index d6434ec86022..9e2123470cad 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -60,7 +60,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&power_key_irq &lid_irq>;
 
-		power {
+		power-key {
 			label = "Power";
 			gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 546ba274f4e5..14cf9c4ca0ed 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_0 {
 	gpy7: gpy7-gpio-bank {
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
index d91f7fa2cf80..3de7019572a2 100644
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
@@ -8,6 +8,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include "exynos5422-odroid-core.dtsi"
 
 / {
@@ -19,7 +20,8 @@ led-controller {
 		compatible = "pwm-leds";
 
 		led-1 {
-			label = "blue:heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
 			pwms = <&pwm 2 2000000 0>;
 			pwm-names = "pwm2";
 			max-brightness = <255>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 1c24f9b35973..f5fb617f46bd 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -9,6 +9,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos5422-odroidxu3-common.dtsi"
 
@@ -21,7 +22,8 @@ led-controller {
 		compatible = "pwm-leds";
 
 		led-1 {
-			label = "blue:heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
 			pwms = <&pwm 2 2000000 0>;
 			pwm-names = "pwm2";
 			max-brightness = <255>;
diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
index 982752e1df24..8c0e1716c0b3 100644
--- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
+++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	led-controller-1 {
@@ -16,6 +17,8 @@ led-controller-1 {
 
 		led-1 {
 			label = "green:mmc0";
+			function = LED_FUNCTION_DISK_ACTIVITY;
+			color = <LED_COLOR_ID_GREEN>;
 			pwms = <&pwm 1 2000000 0>;
 			pwm-names = "pwm1";
 			/*
@@ -27,7 +30,8 @@ led-1 {
 		};
 
 		led-2 {
-			label = "blue:heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
 			pwms = <&pwm 2 2000000 0>;
 			pwm-names = "pwm2";
 			max-brightness = <255>;
@@ -40,6 +44,8 @@ led-controller-2 {
 
 		led-3 {
 			label = "red:microSD";
+			function = LED_FUNCTION_DISK_ACTIVITY;
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 			linux,default-trigger = "mmc1";
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 4ee76281979c..0ebcb66c6319 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -59,7 +59,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&power_key_irq &lid_irq>;
 
-		power {
+		power-key {
 			label = "Power";
 			gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h
index 5c0f32ca3a93..468c079f3c2b 100644
--- a/arch/arm/boot/dts/imx23-pinfunc.h
+++ b/arch/arm/boot/dts/imx23-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Header providing constants for i.MX23 pinctrl bindings.
  *
  * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #ifndef __DT_BINDINGS_MX23_PINCTRL_H__
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index fa8044c21cb8..bc4de0c05511 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -68,7 +68,7 @@ osc {
 		};
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index b660c7d05584..e140307be2e7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -74,14 +74,14 @@ cpu: cpu@0 {
 		};
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&aitc>;
 		ranges;
 
-		aipi@10000000 { /* AIPI1 */
+		aipi1: aipi@10000000 { /* AIPI1 */
 			compatible = "fsl,aipi-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -453,7 +453,7 @@ gpt6: timer@1001f000 {
 			};
 		};
 
-		aipi@10020000 { /* AIPI2 */
+		aipi2: aipi@10020000 { /* AIPI2 */
 			compatible = "fsl,aipi-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h
index e11f69ba0fe4..d427e6c2fa78 100644
--- a/arch/arm/boot/dts/imx28-pinfunc.h
+++ b/arch/arm/boot/dts/imx28-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Header providing constants for i.MX28 pinctrl bindings.
  *
  * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #ifndef __DT_BINDINGS_MX28_PINCTRL_H__
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 2adb923c0b27..5c4938b0d5a1 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -48,7 +48,7 @@ avic: interrupt-controller@68000000 {
 		reg = <0x68000000 0x100000>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -63,7 +63,7 @@ iram: sram@1fffc000 {
 			ranges = <0 0x1fffc000 0x4000>;
 		};
 
-		bus@43f00000 { /* AIPS1 */
+		aips1: bus@43f00000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index be0de0fd31f9..c0c7575fbecf 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -94,14 +94,14 @@ usbphy0: usbphy-0 {
 		status = "okay";
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		interrupt-parent = <&tzic>;
 		ranges;
 
-		bus@50000000 { /* AIPS1 */
+		aips1: bus@50000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -385,7 +385,7 @@ uart4: serial@53ff0000 {
 			};
 		};
 
-		bus@60000000 {	/* AIPS2 */
+		aips2: bus@60000000 {	/* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index 85654d6baf28..f7408722d68a 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -174,7 +174,7 @@ fpga_irqc: fpga-irqc@15000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_interrupt_fpga>;
 			interrupt-parent = <&gpio2>;
-			interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
 		};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1e20a6639e42..592d9c23a447 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -114,7 +114,7 @@ display-subsystem {
 		ports = <&ipu_di0>, <&ipu_di1>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -171,7 +171,7 @@ ipu_di1_disp2: endpoint {
 			};
 		};
 
-		bus@70000000 { /* AIPS1 */
+		aips1: bus@70000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -460,7 +460,7 @@ clks: ccm@73fd4000{
 			};
 		};
 
-		bus@80000000 {	/* AIPS2 */
+		aips2: bus@80000000 {	/* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 67487f3caee1..b7a6469d3472 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -132,7 +132,7 @@ usbphy1: usbphy-1 {
 		status = "okay";
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -222,7 +222,7 @@ gpu: gpu@30000000 {
 			clock-names = "core_clk", "mem_iface_clk";
 		};
 
-		bus@50000000 { /* AIPS1 */
+		aips1: bus@50000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -655,7 +655,7 @@ uart4: serial@53ff0000 {
 			};
 		};
 
-		bus@60000000 {	/* AIPS2 */
+		aips2: bus@60000000 {	/* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts
index c4ce23d8ac9f..522660c912a0 100644
--- a/arch/arm/boot/dts/imx6dl-plym2m.dts
+++ b/arch/arm/boot/dts/imx6dl-plym2m.dts
@@ -196,7 +196,7 @@ adc_ts: adc@0 {
 		compatible = "ti,tsc2046e-adc";
 		reg = <0>;
 		pinctrl-0 = <&pinctrl_tsc2046>;
-		pinctrl-names ="default";
+		pinctrl-names = "default";
 		spi-max-frequency = <1000000>;
 		interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
 		#io-channel-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts
index b86deebef7b7..0a0b7acddfb2 100644
--- a/arch/arm/boot/dts/imx6dl-prtvt7.dts
+++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts
@@ -344,7 +344,7 @@ adc_ts: adc@0 {
 		compatible = "ti,tsc2046e-adc";
 		reg = <0>;
 		pinctrl-0 = <&pinctrl_tsc>;
-		pinctrl-names ="default";
+		pinctrl-names = "default";
 		spi-max-frequency = <1000000>;
 		interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
 		#io-channel-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts
index 516ec915a911..779b52858a25 100644
--- a/arch/arm/boot/dts/imx6dl-victgo.dts
+++ b/arch/arm/boot/dts/imx6dl-victgo.dts
@@ -144,7 +144,7 @@ adc_ts: adc@0 {
 		compatible = "ti,tsc2046e-adc";
 		reg = <0>;
 		pinctrl-0 = <&pinctrl_touchscreen>;
-		pinctrl-names ="default";
+		pinctrl-names = "default";
 		spi-max-frequency = <1000000>;
 		interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
 		#io-channel-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index fdd81fdc3f35..8e0ed209ede0 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -80,7 +80,7 @@ cpu@1 {
 		};
 	};
 
-	soc {
+	soc: soc {
 		ocram: sram@900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x20000>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index a0683b4aeca1..fa160a389870 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
  */
@@ -30,89 +30,26 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_keys>;
-
-		wakeup {
-			label = "Wake-Up";
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
-
-	lcd_display: disp0 {
-		compatible = "fsl,imx-parallel-display";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
-		status = "okay";
-
-		port@0 {
-			reg = <0>;
-
-			lcd_display_in: endpoint {
-				remote-endpoint = <&ipu1_di1_disp1>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			lcd_display_out: endpoint {
-				remote-endpoint = <&lcd_panel_in>;
-			};
-		};
-	};
-
-	panel: panel {
-		/*
-		 * edt,et057090dhu: EDT 5.7" LCD TFT
-		 * edt,et070080dh6: EDT 7.0" LCD TFT
-		 */
-		compatible = "edt,et057090dhu";
-		backlight = <&backlight>;
-		power-supply = <&reg_3v3_sw>;
-
-		port {
-			lcd_panel_in: endpoint {
-				remote-endpoint = <&lcd_display_out>;
-			};
-		};
-	};
-
 	reg_pcie_switch: regulator-pcie-switch {
 		compatible = "regulator-fixed";
-		regulator-name = "pcie_switch";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
+		enable-active-high;
 		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "pcie_switch";
 		startup-delay-us = <100000>;
-		enable-active-high;
 		status = "okay";
 	};
 
 	reg_3v3_sw: regulator-3v3-sw {
 		compatible = "regulator-fixed";
-		regulator-name = "3.3V_SW";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "3.3V_SW";
 	};
 };
 
-&backlight {
-	brightness-levels = <0 127 191 223 239 247 251 255>;
-	default-brightness-level = <1>;
-	power-supply = <&reg_3v3_sw>;
-	status = "okay";
-};
-
 &can1 {
 	xceiver-supply = <&reg_3v3_sw>;
 	status = "okay";
@@ -123,27 +60,10 @@ &can2 {
 	status = "okay";
 };
 
-&hdmi {
-	status = "okay";
-};
-
 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 &i2c1 {
 	status = "okay";
 
-	/*
-	 * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
-	 * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
-	 */
-	touchscreen@4a {
-		compatible = "atmel,maxtouch";
-		reg = <0x4a>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
-		status = "disabled";
-	};
-
 	pcie-switch@58 {
 		compatible = "plx,pex8605";
 		reg = <0x58>;
@@ -164,14 +84,6 @@ &i2c3 {
 	status = "okay";
 };
 
-&ipu1_di1_disp1 {
-	remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
-	status = "okay";
-};
-
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_reset_moci>;
@@ -198,11 +110,11 @@ &pwm4 {
 	status = "okay";
 };
 
-&reg_usb_otg_vbus {
+&reg_usb_host_vbus {
 	status = "okay";
 };
 
-&reg_usb_host_vbus {
+&reg_usb_otg_vbus {
 	status = "okay";
 };
 
@@ -246,28 +158,13 @@ &usbotg {
 
 /* MMC1 */
 &usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
-	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
 /* SD1 */
 &usdhc2 {
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
-	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
-
-&iomuxc {
-	/*
-	 * Mux the Apalis GPIOs
-	 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
-		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
-		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
-		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
-		    >;
-};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index 86e84781cf5d..44637d606e61 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -1,274 +1,37 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
  */
 
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6q.dtsi"
-#include "imx6qdl-apalis.dtsi"
+#include "imx6q-apalis-ixora-v1.2.dts"
 
 / {
 	model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1";
-	compatible = "toradex,apalis_imx6q-ixora-v1.1",
-		     "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
+	compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q",
 		     "fsl,imx6q";
 
-	aliases {
-		i2c0 = &i2c1;
-		i2c1 = &i2c3;
-		i2c2 = &i2c2;
-		rtc0 = &rtc_i2c;
-		rtc1 = &snvs_rtc;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_keys>;
-
-		wakeup {
-			label = "Wake-Up";
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
-
-	lcd_display: disp0 {
-		compatible = "fsl,imx-parallel-display";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
-		status = "okay";
-
-		port@0 {
-			reg = <0>;
-
-			lcd_display_in: endpoint {
-				remote-endpoint = <&ipu1_di1_disp1>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			lcd_display_out: endpoint {
-				remote-endpoint = <&lcd_panel_in>;
-			};
-		};
-	};
 
-	panel: panel {
-		/*
-		 * edt,et057090dhu: EDT 5.7" LCD TFT
-		 * edt,et070080dh6: EDT 7.0" LCD TFT
-		 */
-		compatible = "edt,et057090dhu";
-		backlight = <&backlight>;
-
-		port {
-			lcd_panel_in: endpoint {
-				remote-endpoint = <&lcd_display_out>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_leds_ixora>;
-
-		led4-green {
-			label = "LED_4_GREEN";
-			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-		};
-
-		led4-red {
-			label = "LED_4_RED";
-			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-		};
-
-		led5-green {
-			label = "LED_5_GREEN";
-			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		led5-red {
-			label = "LED_5_RED";
-			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
 };
 
-&backlight {
-	brightness-levels = <0 127 191 223 239 247 251 255>;
-	default-brightness-level = <1>;
-	status = "okay";
-};
+/delete-node/ &eeprom;
+/delete-node/ &reg_3v3_vmmc;
+/delete-node/ &reg_can1_supply;
+/delete-node/ &reg_can2_supply;
 
 &can1 {
-	status = "okay";
+	/delete-property/ xceiver-supply;
 };
 
 &can2 {
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-};
-
-/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
-&i2c1 {
-	status = "okay";
-
-	/*
-	 * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
-	 * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
-	 */
-	touchscreen@4a {
-		compatible = "atmel,maxtouch";
-		reg = <0x4a>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
-		status = "disabled";
-	};
-
-	/* M41T0M6 real time clock on carrier board */
-	rtc_i2c: rtc@68 {
-		compatible = "st,m41t0";
-		reg = <0x68>;
-	};
-};
-
-/*
- * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
- * board)
- */
-&i2c3 {
-	status = "okay";
-};
-
-&ipu1_di1_disp1 {
-	remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_reset_moci>;
-	/* active-high meaning opposite of regular PERST# active-low polarity */
-	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-	reset-gpio-active-high;
-	status = "okay";
-};
-
-&pwm1 {
-	status = "okay";
-};
-
-&pwm2 {
-	status = "okay";
-};
-
-&pwm3 {
-	status = "okay";
-};
-
-&pwm4 {
-	status = "okay";
-};
-
-&reg_usb_otg_vbus {
-	status = "okay";
-};
-
-&reg_usb_host_vbus {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&sound_spdif {
-	status = "okay";
-};
-
-&spdif {
-	status = "okay";
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
-
-&uart5 {
-	status = "okay";
-};
-
-&usbh1 {
-	vbus-supply = <&reg_usb_host_vbus>;
-	status = "okay";
-};
-
-&usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	status = "okay";
+	/delete-property/ xceiver-supply;
 };
 
 /* MMC1 */
 &usdhc1 {
+	/delete-property/ cap-power-off-card;
+	/delete-property/ pinctrl-1;
+	/delete-property/ vmmc-supply;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
-	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&iomuxc {
-	/*
-	 * Mux the Apalis GPIOs
-	 */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
-		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
-		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
-		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
-		    >;
-
-	pinctrl_leds_ixora: ledsixoragrp {
-		fsl,pins = <
-			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
-			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
-			MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
-			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
-		>;
-	};
 };
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
new file mode 100644
index 000000000000..f9f7d99bd4db
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2014-2022 Toradex
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2";
+	compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q",
+		     "fsl,imx6q";
+
+	aliases {
+		i2c0 = &i2c1;
+		i2c1 = &i2c3;
+		i2c2 = &i2c2;
+		rtc0 = &rtc_i2c;
+		rtc1 = &snvs_rtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_leds_ixora>;
+
+		led4-green {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "LED_4_GREEN";
+		};
+
+		led4-red {
+			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+			label = "LED_4_RED";
+		};
+
+		led5-green {
+			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+			label = "LED_5_GREEN";
+		};
+
+		led5-red {
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+			label = "LED_5_RED";
+		};
+	};
+
+	reg_3v3_vmmc: regulator-3v3-vmmc {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "3v3_vmmc";
+		startup-delay-us = <100>;
+	};
+
+	reg_can1_supply: regulator-can1-supply {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_enable_can1_power>;
+		regulator-name = "can1_supply";
+	};
+
+	reg_can2_supply: regulator-can2-supply {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_enable_can2_power>;
+		regulator-name = "can2_supply";
+	};
+};
+
+&can1 {
+	xceiver-supply = <&reg_can1_supply>;
+	status = "okay";
+};
+
+&can2 {
+	xceiver-supply = <&reg_can2_supply>;
+	status = "okay";
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart24_forceoff>;
+
+	/*
+	 * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis
+	 * UART2 and UART3. If one wants to disable the transceiver force
+	 * the GPIO to output-low, if one wants to control the transceiver
+	 * from user space delete the hog node.
+	 */
+	uart-2-4-on-x21-enable-hog {
+		gpio-hog;
+		gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */
+		output-high;
+	};
+};
+
+/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+	status = "okay";
+
+	/* M41T0M6 real time clock on carrier board */
+	rtc_i2c: rtc@68 {
+		compatible = "st,m41t0";
+		reg = <0x68>;
+	};
+
+	eeprom: eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+/*
+ * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
+ * board)
+ */
+&i2c3 {
+	status = "okay";
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_reset_moci>;
+	/* active-high meaning opposite of regular PERST# active-low polarity */
+	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+	reset-gpio-active-high;
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+&reg_usb_host_vbus {
+	status = "okay";
+};
+
+&reg_usb_otg_vbus {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&sound_spdif {
+	status = "okay";
+};
+
+&spdif {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+	pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>;
+	bus-width = <4>;
+	cap-power-off-card;
+	vmmc-supply = <&reg_3v3_vmmc>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+		>;
+	};
+
+	pinctrl_enable_can1_power: enablecan1powergrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+		>;
+	};
+
+	pinctrl_enable_can2_power: enablecan2powergrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0
+		>;
+	};
+
+	pinctrl_uart24_forceoff: uart24forceoffgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
+		>;
+	};
+
+	pinctrl_leds_ixora: ledsixoragrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+		>;
+	};
+
+	pinctrl_mmc_cd_sleep: mmccdslpgrp {
+		fsl,pins = <
+			 /* MMC1 CD */
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0
+		>;
+	};
+
+	pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD     0x3000
+			MX6QDL_PAD_SD1_CLK__SD1_CLK     0x3000
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x3000
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x3000
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x3000
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x3000
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 62e72773e53b..ce39c6a3f640 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
  */
@@ -30,95 +30,33 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_keys>;
-
-		wakeup {
-			label = "Wake-Up";
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
-
-	lcd_display: disp0 {
-		compatible = "fsl,imx-parallel-display";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
-		status = "okay";
-
-		port@0 {
-			reg = <0>;
-
-			lcd_display_in: endpoint {
-				remote-endpoint = <&ipu1_di1_disp1>;
-			};
-		};
-
-		port@1 {
-			reg = <1>;
-
-			lcd_display_out: endpoint {
-				remote-endpoint = <&lcd_panel_in>;
-			};
-		};
-	};
-
-	panel: panel {
-		/*
-		 * edt,et057090dhu: EDT 5.7" LCD TFT
-		 * edt,et070080dh6: EDT 7.0" LCD TFT
-		 */
-		compatible = "edt,et057090dhu";
-		backlight = <&backlight>;
-
-		port {
-			lcd_panel_in: endpoint {
-				remote-endpoint = <&lcd_display_out>;
-			};
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";
-
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_leds_ixora>;
 
 		led4-green {
-			label = "LED_4_GREEN";
 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+			label = "LED_4_GREEN";
 		};
 
 		led4-red {
-			label = "LED_4_RED";
 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+			label = "LED_4_RED";
 		};
 
 		led5-green {
-			label = "LED_5_GREEN";
 			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+			label = "LED_5_GREEN";
 		};
 
 		led5-red {
-			label = "LED_5_RED";
 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+			label = "LED_5_RED";
 		};
 	};
 };
 
-&backlight {
-	brightness-levels = <0 127 191 223 239 247 251 255>;
-	default-brightness-level = <1>;
-	status = "okay";
-};
-
 &can1 {
 	status = "okay";
 };
@@ -127,27 +65,10 @@ &can2 {
 	status = "okay";
 };
 
-&hdmi {
-	status = "okay";
-};
-
 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 &i2c1 {
 	status = "okay";
 
-	/*
-	 * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
-	 * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
-	 */
-	touchscreen@4a {
-		compatible = "atmel,maxtouch";
-		reg = <0x4a>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
-		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */
-		status = "disabled";
-	};
-
 	eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
@@ -168,14 +89,6 @@ &i2c3 {
 	status = "okay";
 };
 
-&ipu1_di1_disp1 {
-	remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
-	status = "okay";
-};
-
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_reset_moci>;
@@ -201,11 +114,11 @@ &pwm4 {
 	status = "okay";
 };
 
-&reg_usb_otg_vbus {
+&reg_usb_host_vbus {
 	status = "okay";
 };
 
-&reg_usb_host_vbus {
+&reg_usb_otg_vbus {
 	status = "okay";
 };
 
@@ -249,21 +162,13 @@ &usbotg {
 
 /* SD1 */
 &usdhc2 {
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
-	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
 &iomuxc {
-	/* Mux the Apalis GPIOs */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
-		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
-		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
-		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
-		    >;
-
 	pinctrl_leds_ixora: ledsixoragrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts
index 8768222e183e..731fbc7b317c 100644
--- a/arch/arm/boot/dts/imx6q-bosch-acc.dts
+++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts
@@ -594,7 +594,7 @@ &wdog1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_wdog1>;
 	fsl,ext-reset-output;
-	timeout-sec=<10>;
+	timeout-sec = <10>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index ccc2487d47ca..2fda68f9d3f6 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2013 Philipp Zabel
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Philipp Zabel
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
index 7f1f19b74bfa..a3f247c722b4 100644
--- a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
+++ b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts
@@ -125,3 +125,9 @@ MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x1b0b0
 		>;
 	};
 };
+
+&reg_tft_vcom {
+	regulator-min-microvolt = <3160000>;
+	regulator-max-microvolt = <3160000>;
+	voltage-table = <3160000 73>;
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 9caba4529c71..3b77eae40e39 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -159,14 +159,14 @@ cpu3: cpu@3 {
 		};
 	};
 
-	soc {
+	soc: soc {
 		ocram: sram@900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x40000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		bus@2000000 { /* AIPS1 */
+		aips1: bus@2000000 { /* AIPS1 */
 			spba-bus@2000000 {
 				ecspi5: spi@2018000 {
 					#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index bd763bae596b..7c17b91f0965 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -1,11 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2014-2020 Toradex
+ * Copyright 2014-2022 Toradex
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
 	model = "Toradex Apalis iMX6Q/D Module";
@@ -19,88 +20,182 @@ memory@10000000 {
 
 	backlight: backlight {
 		compatible = "pwm-backlight";
+		brightness-levels = <0 45 63 88 119 158 203 255>;
+		default-brightness-level = <4>;
+		enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_bl_on>;
-		pwms = <&pwm4 0 5000000>;
-		enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_module_3v3>;
+		pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>;
+		status = "disabled";
+	};
+
+	clk_ov5640_osc: clk-ov5640-osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		wakeup {
+			debounce-interval = <10>;
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			label = "Wake-Up";
+			linux,code = <KEY_WAKEUP>;
+			wakeup-source;
+		};
+	};
+
+	lcd_display: disp0 {
+		compatible = "fsl,imx-parallel-display";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interface-pix-fmt = "rgb24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
 		status = "disabled";
+
+		port@0 {
+			reg = <0>;
+
+			lcd_display_in: endpoint {
+				remote-endpoint = <&ipu1_di1_disp1>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			lcd_display_out: endpoint {
+				remote-endpoint = <&lcd_panel_in>;
+			};
+		};
+	};
+
+	panel_dpi: panel-dpi {
+		compatible = "edt,et057090dhu";
+		backlight = <&backlight>;
+
+		status = "disabled";
+
+		port {
+			lcd_panel_in: endpoint {
+				remote-endpoint = <&lcd_display_out>;
+			};
+		};
+	};
+
+	panel_lvds: panel-lvds {
+		compatible = "panel-lvds";
+		backlight = <&backlight>;
+		status = "disabled";
+
+		port {
+			lvds_panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
 	};
 
 	reg_module_3v3: regulator-module-3v3 {
 		compatible = "regulator-fixed";
-		regulator-name = "+V3.3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "+V3.3";
 	};
 
 	reg_module_3v3_audio: regulator-module-3v3-audio {
 		compatible = "regulator-fixed";
-		regulator-name = "+V3.3_AUDIO";
-		regulator-min-microvolt = <3300000>;
+		regulator-always-on;
 		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "+V3.3_AUDIO";
+	};
+
+	reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "DOVDD/DVDD_1.8V";
+		/* Note: The CSI module uses on-board 3.3V_SW supply */
+		vin-supply = <&reg_module_3v3>;
+	};
+
+	reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd {
+		compatible = "regulator-fixed";
 		regulator-always-on;
+		regulator-max-microvolt = <2800000>;
+		regulator-min-microvolt = <2800000>;
+		regulator-name = "AVDD/AFVDD_2.8V";
+		/* Note: The CSI module uses on-board 3.3V_SW supply */
+		vin-supply = <&reg_module_3v3>;
 	};
 
 	reg_usb_otg_vbus: regulator-usb-otg-vbus {
 		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
-		regulator-name = "usb_otg_vbus";
-		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb_otg_vbus";
 		status = "disabled";
 	};
 
 	/* on module USB hub */
 	reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
 		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
-		regulator-name = "usb_host_vbus_hub";
-		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb_host_vbus_hub";
 		startup-delay-us = <2000>;
-		enable-active-high;
 		status = "okay";
 	};
 
 	reg_usb_host_vbus: regulator-usb-host-vbus {
 		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
-		regulator-name = "usb_host_vbus";
-		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb_host_vbus";
 		vin-supply = <&reg_usb_host_vbus_hub>;
 		status = "disabled";
 	};
 
 	sound {
 		compatible = "fsl,imx-audio-sgtl5000";
-		model = "imx6q-apalis-sgtl5000";
-		ssi-controller = <&ssi1>;
 		audio-codec = <&codec>;
 		audio-routing =
 			"LINE_IN", "Line In Jack",
 			"MIC_IN", "Mic Jack",
 			"Mic Jack", "Mic Bias",
 			"Headphone Jack", "HP_OUT";
-		mux-int-port = <1>;
+		model = "imx6q-apalis-sgtl5000";
 		mux-ext-port = <4>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
 	};
 
 	sound_spdif: sound-spdif {
 		compatible = "fsl,imx-audio-spdif";
-		model = "imx-spdif";
 		spdif-controller = <&spdif>;
 		spdif-in;
 		spdif-out;
+		model = "imx-spdif";
 		status = "disabled";
 	};
 };
@@ -125,6 +220,10 @@ &can2 {
 	status = "disabled";
 };
 
+&clks {
+	fsl,pmic-stby-poweroff;
+};
+
 /* Apalis SPI1 */
 &ecspi1 {
 	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
@@ -141,6 +240,214 @@ &ecspi2 {
 	status = "disabled";
 };
 
+&gpio1 {
+	gpio-line-names = "MXM3_84",
+			  "MXM3_4",
+			  "MXM3_15/GPIO7",
+			  "MXM3_96",
+			  "MXM3_37",
+			  "",
+			  "MXM3_17/GPIO8",
+			  "MXM3_14",
+			  "MXM3_12",
+			  "MXM3_2",
+			  "MXM3_184",
+			  "MXM3_180",
+			  "MXM3_178",
+			  "MXM3_176",
+			  "MXM3_188",
+			  "MXM3_186",
+			  "MXM3_160",
+			  "MXM3_162",
+			  "MXM3_150",
+			  "MXM3_144",
+			  "MXM3_154",
+			  "MXM3_146",
+			  "",
+			  "",
+			  "MXM3_72";
+};
+
+&gpio2 {
+	gpio-line-names = "MXM3_148",
+			  "MXM3_152",
+			  "MXM3_156",
+			  "MXM3_158",
+			  "MXM3_1/GPIO1",
+			  "MXM3_3/GPIO2",
+			  "MXM3_5/GPIO3",
+			  "MXM3_7/GPIO4",
+			  "MXM3_95",
+			  "MXM3_6",
+			  "MXM3_8",
+			  "MXM3_123",
+			  "MXM3_126",
+			  "MXM3_128",
+			  "MXM3_130",
+			  "MXM3_132",
+			  "MXM3_253",
+			  "MXM3_251",
+			  "MXM3_283",
+			  "MXM3_281",
+			  "MXM3_279",
+			  "MXM3_277",
+			  "MXM3_243",
+			  "MXM3_235",
+			  "MXM3_231",
+			  "MXM3_229",
+			  "MXM3_233",
+			  "MXM3_198",
+			  "MXM3_275",
+			  "MXM3_273",
+			  "MXM3_207",
+			  "MXM3_122";
+};
+
+&gpio3 {
+	gpio-line-names = "MXM3_271",
+			  "MXM3_269",
+			  "MXM3_301",
+			  "MXM3_299",
+			  "MXM3_297",
+			  "MXM3_295",
+			  "MXM3_293",
+			  "MXM3_291",
+			  "MXM3_289",
+			  "MXM3_287",
+			  "MXM3_249",
+			  "MXM3_247",
+			  "MXM3_245",
+			  "MXM3_286",
+			  "MXM3_239",
+			  "MXM3_35",
+			  "MXM3_205",
+			  "MXM3_203",
+			  "MXM3_201",
+			  "MXM3_116",
+			  "MXM3_114",
+			  "MXM3_262",
+			  "MXM3_274",
+			  "MXM3_124",
+			  "MXM3_110",
+			  "MXM3_120",
+			  "MXM3_263",
+			  "MXM3_265",
+			  "",
+			  "MXM3_135",
+			  "MXM3_261",
+			  "MXM3_259";
+};
+
+&gpio4 {
+	gpio-line-names = "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MXM3_194",
+			  "MXM3_136",
+			  "MXM3_134",
+			  "MXM3_140",
+			  "MXM3_138",
+			  "",
+			  "MXM3_220",
+			  "",
+			  "",
+			  "MXM3_18",
+			  "MXM3_16",
+			  "",
+			  "",
+			  "MXM3_214",
+			  "MXM3_216",
+			  "MXM3_164";
+};
+
+&gpio5 {
+	gpio-line-names = "MXM3_159",
+			  "",
+			  "",
+			  "",
+			  "MXM3_257",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MXM3_200",
+			  "MXM3_196",
+			  "MXM3_204",
+			  "MXM3_202",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MXM3_191",
+			  "MXM3_197",
+			  "MXM3_77",
+			  "MXM3_195",
+			  "MXM3_221",
+			  "MXM3_225",
+			  "MXM3_223",
+			  "MXM3_227",
+			  "MXM3_209",
+			  "MXM3_211",
+			  "MXM3_118",
+			  "MXM3_112",
+			  "MXM3_187",
+			  "MXM3_185";
+};
+
+&gpio6 {
+	gpio-line-names = "MXM3_183",
+			  "MXM3_181",
+			  "MXM3_179",
+			  "MXM3_177",
+			  "MXM3_175",
+			  "MXM3_173",
+			  "MXM3_255",
+			  "MXM3_83",
+			  "MXM3_91",
+			  "MXM3_13/GPIO6",
+			  "MXM3_11/GPIO5",
+			  "MXM3_79",
+			  "",
+			  "",
+			  "MXM3_190",
+			  "MXM3_193",
+			  "MXM3_89";
+};
+
+&gpio7 {
+	gpio-line-names = "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "",
+			  "MXM3_99",
+			  "MXM3_85",
+			  "MXM3_217",
+			  "MXM3_215";
+};
+
+&gpr {
+	ipu1_csi0_mux {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		port@1 {
+			reg = <1>;
+			ipu1_csi0_mux_from_parallel_sensor: endpoint {
+				remote-endpoint = <&adv7280_to_ipu1_csi0_mux>;
+			};
+		};
+	};
+};
+
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
@@ -177,6 +484,16 @@ &i2c1 {
 	scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "disabled";
+
+	atmel_mxt_ts: touchscreen@4a {
+		compatible = "atmel,maxtouch";
+		/* These GPIOs are muxed with the iomuxc node */
+		interrupt-parent = <&gpio6>;
+		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;	/* MXM3_11 */
+		reg = <0x4a>;
+		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;	/* MXM3_13 */
+		status = "disabled";
+	};
 };
 
 /*
@@ -192,103 +509,105 @@ &i2c2 {
 	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
-	pmic: pfuze100@8 {
+	pmic: pmic@8 {
 		compatible = "fsl,pfuze100";
+		fsl,pmic-stby-poweroff;
 		reg = <0x08>;
 
 		regulators {
 			sw1a_reg: sw1ab {
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1875000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1875000>;
+				regulator-min-microvolt = <300000>;
 				regulator-ramp-delay = <6250>;
 			};
 
 			sw1c_reg: sw1c {
-				regulator-min-microvolt = <300000>;
-				regulator-max-microvolt = <1875000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1875000>;
+				regulator-min-microvolt = <300000>;
 				regulator-ramp-delay = <6250>;
 			};
 
 			sw3a_reg: sw3a {
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1975000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1975000>;
+				regulator-min-microvolt = <400000>;
 			};
 
 			swbst_reg: swbst {
-				regulator-min-microvolt = <5000000>;
-				regulator-max-microvolt = <5150000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <5150000>;
+				regulator-min-microvolt = <5000000>;
 			};
 
 			snvs_reg: vsnvs {
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3000000>;
+				regulator-min-microvolt = <1000000>;
 			};
 
 			vref_reg: vrefddr {
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
 			};
 
 			vgen1_reg: vgen1 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1550000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1550000>;
+				regulator-min-microvolt = <800000>;
 			};
 
 			vgen2_reg: vgen2 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1550000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1550000>;
+				regulator-min-microvolt = <800000>;
 			};
 
 			vgen3_reg: vgen3 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
 			};
 
 			vgen4_reg: vgen4 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microvolt = <1800000>;
 			};
 
 			vgen5_reg: vgen5 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
 			};
 
 			vgen6_reg: vgen6 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
 			};
 		};
 	};
 
 	codec: sgtl5000@a {
 		compatible = "fsl,sgtl5000";
-		reg = <0x0a>;
+		#sound-dai-cells = <0>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_sgtl5000>;
-		clocks = <&clks IMX6QDL_CLK_CKO>;
+		reg = <0x0a>;
 		VDDA-supply = <&reg_module_3v3_audio>;
 		VDDIO-supply = <&reg_module_3v3>;
 		VDDD-supply = <&vgen4_reg>;
@@ -297,15 +616,15 @@ codec: sgtl5000@a {
 	/* STMPE811 touch screen controller */
 	stmpe811@41 {
 		compatible = "st,stmpe811";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_touch_int>;
-		reg = <0x41>;
+		blocks = <0x5>;
+		id = <0>;
 		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-parent = <&gpio4>;
 		interrupt-controller;
-		id = <0>;
-		blocks = <0x5>;
+		interrupt-parent = <&gpio4>;
 		irq-trigger = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_touch_int>;
+		reg = <0x41>;
 		/* 3.25 MHz ADC clock speed */
 		st,adc-freq = <1>;
 		/* 12-bit ADC */
@@ -315,7 +634,7 @@ stmpe811@41 {
 		/* ADC conversion time: 80 clocks */
 		st,sample-time = <4>;
 
-		stmpe_touchscreen: stmpe-touchscreen {
+		stmpe_ts: stmpe_touchscreen {
 			compatible = "st,stmpe-ts";
 			/* 8 sample average control */
 			st,ave-ctrl = <3>;
@@ -330,13 +649,14 @@ stmpe_touchscreen: stmpe-touchscreen {
 			st,settling = <3>;
 			/* 5 ms touch detect interrupt delay */
 			st,touch-det-delay = <5>;
+			status = "disabled";
 		};
 
-		stmpe_adc: stmpe-adc {
+		stmpe_adc: stmpe_adc {
 			compatible = "st,stmpe-adc";
+			#io-channel-cells = <1>;
 			/* forbid to use ADC channels 3-0 (touch) */
 			st,norequest-mask = <0x0F>;
-			#io-channel-cells = <1>;
 		};
 	};
 };
@@ -353,6 +673,90 @@ &i2c3 {
 	scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "disabled";
+
+	adv_7280: adv7280@21 {
+		compatible = "adi,adv7280";
+		adv,force-bt656-4;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ipu1_csi0>;
+		reg = <0x21>;
+		status = "disabled";
+
+		port {
+			adv7280_to_ipu1_csi0_mux: endpoint {
+				bus-width = <8>;
+				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+			};
+		};
+	};
+
+	ov5640_csi_cam: ov5640_mipi@3c {
+		compatible = "ovti,ov5640";
+		AVDD-supply = <&reg_ov5640_2v8_a_vdd>;
+		DOVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
+		DVDD-supply = <&reg_ov5640_1v8_d_o_vdd>;
+		clock-names = "xclk";
+		clocks = <&clks IMX6QDL_CLK_CKO2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_cam_mclk>;
+		/* These GPIOs are muxed with the iomuxc node */
+		powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+		reg = <0x3c>;
+		reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+		status = "disabled";
+
+		port {
+			ov5640_to_mipi_csi2: endpoint {
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&mipi_csi_from_ov5640>;
+			};
+		};
+	};
+};
+
+&ipu1_di1_disp1 {
+	remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+	lvds-channel@0 {
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&lvds_panel_in>;
+			};
+		};
+	};
+
+	lvds-channel@1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+
+		port@4 {
+			reg = <4>;
+
+			lvds1_out: endpoint {
+			};
+		};
+	};
+};
+
+&mipi_csi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	port@0 {
+		reg = <0>;
+
+		mipi_csi_from_ov5640: endpoint {
+			clock-lanes = <0>;
+			data-lanes = <1 2>;
+			remote-endpoint = <&ov5640_to_mipi_csi2>;
+		};
+	};
 };
 
 &pwm1 {
@@ -374,7 +778,6 @@ &pwm3 {
 };
 
 &pwm4 {
-	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm4>;
 	status = "disabled";
@@ -391,72 +794,73 @@ &ssi1 {
 };
 
 &uart1 {
+	fsl,dte-mode;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
-	fsl,dte-mode;
 	uart-has-rtscts;
 	status = "disabled";
 };
 
 &uart2 {
+	fsl,dte-mode;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2_dte>;
-	fsl,dte-mode;
 	uart-has-rtscts;
 	status = "disabled";
 };
 
 &uart4 {
+	fsl,dte-mode;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart4_dte>;
-	fsl,dte-mode;
 	status = "disabled";
 };
 
 &uart5 {
+	fsl,dte-mode;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart5_dte>;
-	fsl,dte-mode;
 	status = "disabled";
 };
 
 &usbotg {
+	disable-over-current;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg>;
-	disable-over-current;
 	status = "disabled";
 };
 
 /* MMC1 */
 &usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
-	vqmmc-supply = <&reg_module_3v3>;
 	bus-width = <8>;
+	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
 	disable-wp;
 	no-1-8-v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+	vqmmc-supply = <&reg_module_3v3>;
 	status = "disabled";
 };
 
 /* SD1 */
 &usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	vqmmc-supply = <&reg_module_3v3>;
 	bus-width = <4>;
 	disable-wp;
 	no-1-8-v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	vqmmc-supply = <&reg_module_3v3>;
 	status = "disabled";
 };
 
 /* eMMC */
 &usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	vqmmc-supply = <&reg_module_3v3>;
 	bus-width = <8>;
 	no-1-8-v;
 	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_module_3v3>;
 	status = "okay";
 };
 
@@ -465,49 +869,57 @@ &weim {
 };
 
 &iomuxc {
-	pinctrl_apalis_gpio1: gpio2io04grp {
+	/* Mux the Apalis GPIOs */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
+		    >;
+
+	pinctrl_apalis_gpio1: apalisgpio1grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio2: gpio2io05grp {
+	pinctrl_apalis_gpio2: apalisgpio2grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio3: gpio2io06grp {
+	pinctrl_apalis_gpio3: apalisgpio3grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio4: gpio2io07grp {
+	pinctrl_apalis_gpio4: apalisgpio4grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio5: gpio6io10grp {
+	pinctrl_apalis_gpio5: apalisgpio5grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio6: gpio6io09grp {
+	pinctrl_apalis_gpio6: apalisgpio6grp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio7: gpio1io02grp {
+	pinctrl_apalis_gpio7: apalisgpio7grp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 		>;
 	};
 
-	pinctrl_apalis_gpio8: gpio1io06grp {
+	pinctrl_apalis_gpio8: apalisgpio8grp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 		>;
@@ -600,7 +1012,7 @@ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
 		>;
 	};
 
-	pinctrl_gpio_bl_on: gpioblon {
+	pinctrl_gpio_bl_on: gpioblongrp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 		>;
@@ -745,7 +1157,7 @@ MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 		>;
 	};
 
-	pinctrl_mmc_cd: gpiommccdgrp {
+	pinctrl_mmc_cd: mmccdgrp {
 		fsl,pins = <
 			 /* MMC1 CD */
 			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
@@ -776,35 +1188,35 @@ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 		>;
 	};
 
-	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+	pinctrl_regulator_usbh_pwr: regusbhpwrgrp {
 		fsl,pins = <
 			/* USBH_EN */
 			MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 		>;
 	};
 
-	pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
+	pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp {
 		fsl,pins = <
 			/* USBH_HUB_EN */
 			MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 		>;
 	};
 
-	pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
+	pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp {
 		fsl,pins = <
 			/* USBO1 power en */
 			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 		>;
 	};
 
-	pinctrl_reset_moci: gpioresetmocigrp {
+	pinctrl_reset_moci: resetmocigrp {
 		fsl,pins = <
 			/* RESET_MOCI control */
 			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 		>;
 	};
 
-	pinctrl_sd_cd: gpiosdcdgrp {
+	pinctrl_sd_cd: sdcdgrp {
 		fsl,pins = <
 			/* SD1 CD */
 			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
@@ -824,13 +1236,22 @@ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 		>;
 	};
 
-	pinctrl_touch_int: gpiotouchintgrp {
+	pinctrl_touch_int: touchintgrp {
 		fsl,pins = <
 			/* STMPE811 interrupt */
 			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 		>;
 	};
 
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+		>;
+	};
+
 	pinctrl_uart1_dce: uart1dcegrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
@@ -848,15 +1269,6 @@ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 		>;
 	};
 
-	/* Additional DTR, DSR, DCD */
-	pinctrl_uart1_ctrl: uart1ctrlgrp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
-			MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
-			MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
-		>;
-	};
-
 	pinctrl_uart2_dce: uart2dcegrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
@@ -910,7 +1322,7 @@ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 		>;
 	};
 
-	pinctrl_usdhc1_4bit: usdhc1grp_4bit {
+	pinctrl_usdhc1_4bit: usdhc1-4bitgrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
@@ -921,7 +1333,7 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 		>;
 	};
 
-	pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+	pinctrl_usdhc1_8bit: usdhc1-8bitgrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 			MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index c383e0e4110c..023e76215064 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
 	model = "Toradex Colibri iMX6DL/S Module";
@@ -13,13 +14,13 @@ / {
 
 	backlight: backlight {
 		compatible = "pwm-backlight";
-		brightness-levels = <0 127 191 223 239 247 251 255>;
-		default-brightness-level = <1>;
+		brightness-levels = <0 45 63 88 119 158 203 255>;
+		default-brightness-level = <4>;
 		enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_bl_on>;
 		power-supply = <&reg_module_3v3>;
-		pwms = <&pwm3 0 5000000>;
+		pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
 		status = "disabled";
 	};
 
@@ -520,6 +521,8 @@ codec: sgtl5000@a {
 		compatible = "fsl,sgtl5000";
 		clocks = <&clks IMX6QDL_CLK_CKO>;
 		lrclk-strength = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
 		reg = <0x0a>;
 		#sound-dai-cells = <0>;
 		VDDA-supply = <&reg_module_3v3_audio>;
@@ -593,7 +596,7 @@ atmel_mxt_ts: touchscreen@4a {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_atmel_conn>;
 		reg = <0x4a>;
-		reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;	/* SODIMM 106 */
+		reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;	/* SODIMM 106 */
 		status = "disabled";
 	};
 };
@@ -618,7 +621,6 @@ &pwm2 {
 
 /* Colibri PWM<A> */
 &pwm3 {
-	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm3>;
 	status = "disabled";
@@ -739,8 +741,6 @@ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1  /* SODIMM_106 */
 
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
-			/* SGTL5000 sys_mclk */
-			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x000b0
 			MX6QDL_PAD_KEY_COL0__AUD5_TXC	0x130b0
 			MX6QDL_PAD_KEY_ROW0__AUD5_TXD	0x130b0
 			MX6QDL_PAD_KEY_COL1__AUD5_TXFS	0x130b0
@@ -991,6 +991,13 @@ MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x0f058
 		>;
 	};
 
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			/* SGTL5000 sys_mclk */
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x000b0
+		>;
+	};
+
 	pinctrl_spdif: spdifgrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
index 69ae430a53bd..8254bce1b8a2 100644
--- a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi
@@ -15,13 +15,13 @@ touchscreen@0 {
 		reg = <0>;
 		spi-max-frequency = <1000000>;
 		interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>;
-		vcc-supply  = <&reg_3v3>;
+		vcc-supply = <&reg_3v3>;
 		pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
 		ti,x-plate-ohms = /bits/ 16 <850>;
 		ti,y-plate-ohms = /bits/ 16 <295>;
 		ti,pressure-min = /bits/ 16 <2>;
 		ti,pressure-max = /bits/ 16 <1500>;
-		ti,vref-mv	= /bits/ 16 <3300>;
+		ti,vref-mv = /bits/ 16 <3300>;
 		ti,settle-delay-usec = /bits/ 16 <15>;
 		ti,vref-delay-usecs = /bits/ 16 <0>;
 		ti,penirq-recheck-delay-usecs = /bits/ 16 <100>;
diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
index 77a91a97e6cf..3def1b621c8e 100644
--- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi
@@ -149,6 +149,16 @@ reg_can2_stby: regulator-can2-stby {
 		gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
 	};
 
+	reg_tft_vcom: regulator-tft-vcom {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 20000 0>;
+		regulator-name = "tft_vcom";
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+		regulator-always-on;
+		voltage-table = <3600000 26>;
+	};
+
 	reg_vcc_mmc: regulator-vcc-mmc {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d27beb47f9a3..4f7fefc14d0a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -143,7 +143,7 @@ usbphynop2: usbphynop2 {
 		#phy-cells = <0>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -290,7 +290,7 @@ pcie: pcie@1ffc000 {
 			status = "disabled";
 		};
 
-		bus@2000000 { /* AIPS1 */
+		aips1: bus@2000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -762,7 +762,7 @@ reg_pu: regulator-vddpu {
 					regulator-name = "vddpu";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
-					regulator-enable-ramp-delay = <150>;
+					regulator-enable-ramp-delay = <380>;
 					anatop-reg-offset = <0x140>;
 					anatop-vol-bit-shift = <9>;
 					anatop-vol-bit-width = <5>;
@@ -941,7 +941,7 @@ sdma: sdma@20ec000 {
 			};
 		};
 
-		bus@2100000 { /* AIPS2 */
+		aips2: bus@2100000 { /* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
index a17b8bbbdb95..663ee9df79e6 100644
--- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
@@ -27,7 +27,7 @@ gpio_keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		cover {
+		key-cover {
 			label = "Cover";
 			gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
 			linux,code = <SW_LID>;
@@ -35,19 +35,19 @@ cover {
 			wakeup-source;
 		};
 
-		fl {
+		key-fl {
 			label = "Frontlight";
 			gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BRIGHTNESS_CYCLE>;
 		};
 
-		home {
+		key-home {
 			label = "Home";
 			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
 		};
 
-		power {
+		key-power {
 			label = "Power";
 			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
@@ -60,7 +60,7 @@ leds: leds {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_led>;
 
-		on {
+		led-0 {
 			label = "tolinoshine2hd:white:on";
 			gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "timer";
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fc6334336b3d..4d075e2bf749 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -154,7 +154,7 @@ usbphynop1: usbphynop1 {
 		#phy-cells = <0>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
index a6cf0f21c66d..43868311f48a 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
@@ -72,7 +72,6 @@ reg_vref_adc: regulator-vref-adc {
 &adc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_adc1>;
-	num-channels = <3>;
 	vref-supply = <&reg_vref_adc>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 0d4ba9494cf2..38ea4dcfa228 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -83,11 +83,6 @@ &adc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_adc1>;
 	vref-supply = <&reg_adc1_vref_3v3>;
-	/*
-	 * driver can not separate a specific channel so we request 4 channels
-	 * here - we need only the fourth channel
-	 */
-	num-channels = <4>;
 	status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
index caf2c5d03f7e..4b87e2dc70dc 100644
--- a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
@@ -14,7 +14,7 @@ / {
 };
 
 &usdhc2 {
-	fsl,tuning-step= <6>;
+	fsl,tuning-step = <6>;
 };
 
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index afeec01f6522..c95efd1d8c2d 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -64,20 +64,18 @@ cpu0: cpu@0 {
 			clock-frequency = <696000000>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
-			operating-points = <
+			operating-points =
 				/* kHz	uV */
-				696000	1275000
-				528000	1175000
-				396000	1025000
-				198000	950000
-			>;
-			fsl,soc-operating-points = <
+				<696000	1275000>,
+				<528000	1175000>,
+				<396000	1025000>,
+				<198000	950000>;
+			fsl,soc-operating-points =
 				/* KHz	uV */
-				696000	1275000
-				528000	1175000
-				396000	1175000
-				198000	1175000
-			>;
+				<696000	1275000>,
+				<528000	1175000>,
+				<396000	1175000>,
+				<198000	1175000>;
 			clocks = <&clks IMX6UL_CLK_ARM>,
 				 <&clks IMX6UL_CLK_PLL2_BUS>,
 				 <&clks IMX6UL_CLK_PLL2_PFD2>,
@@ -139,7 +137,7 @@ pmu {
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -149,6 +147,9 @@ soc {
 		ocram: sram@900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x20000>;
+			ranges = <0 0x00900000 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 		};
 
 		intc: interrupt-controller@a01000 {
@@ -543,7 +544,7 @@ fec2: ethernet@20b4000 {
 			};
 
 			kpp: keypad@20b8000 {
-				compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+				compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
 				reg = <0x020b8000 0x4000>;
 				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6UL_CLK_KPP>;
@@ -923,7 +924,6 @@ adc1: adc@2198000 {
 				reg = <0x02198000 0x4000>;
 				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6UL_CLK_ADC1>;
-				num-channels = <2>;
 				clock-names = "adc";
 				fsl,adck-max-frequency = <30000000>, <40000000>,
 							 <20000000>;
@@ -998,7 +998,7 @@ cpu_speed_grade: speed-grade@10 {
 			};
 
 			csi: csi@21c4000 {
-				compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
+				compatible = "fsl,imx6ul-csi";
 				reg = <0x021c4000 0x4000>;
 				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6UL_CLK_CSI>;
@@ -1007,7 +1007,7 @@ csi: csi@21c4000 {
 			};
 
 			lcdif: lcdif@21c8000 {
-				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+				compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
 				reg = <0x021c8000 0x4000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
@@ -1028,7 +1028,7 @@ pxp: pxp@21cc000 {
 			qspi: spi@21e0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+				compatible = "fsl,imx6ul-qspi";
 				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 				reg-names = "QuadSPI", "QuadSPI-memory";
 				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 15621e03fa4d..623bb7585ad1 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -94,7 +94,6 @@ reg_eth_phy: regulator-eth-phy {
 };
 
 &adc1 {
-	num-channels = <10>;
 	vref-supply = <&reg_module_3v3_avdd>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_adc1>;
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
index 326e6da91ed4..8541cb3f3b3e 100644
--- a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
@@ -14,7 +14,7 @@ / {
 };
 
 &usdhc2 {
-	fsl,tuning-step= <6>;
+	fsl,tuning-step = <6>;
 	/* Errata ERR010450 Workaround */
 	max-frequency = <99000000>;
 	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
index 8e4d5cd18614..be593d47e3b1 100644
--- a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
+++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
@@ -14,7 +14,7 @@ / {
 };
 
 &usdhc2 {
-	fsl,tuning-step= <6>;
+	fsl,tuning-step = <6>;
 	/* Errata ERR010450 Workaround */
 	max-frequency = <99000000>;
 	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 9bf67490ac49..2bccd45e9fc2 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -50,7 +50,7 @@ &usdhc2 {
 };
 
 / {
-	soc {
+	soc: soc {
 		aips3: bus@2200000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
index 59bcfc9a6b10..c92e4e2f6ab9 100644
--- a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
+++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts
@@ -29,6 +29,10 @@ &gpmi {
 	status = "okay";
 };
 
+&snvs_poweroff {
+	status = "okay";
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3>;
diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
index b770fc937970..fa488a6de0d4 100644
--- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
@@ -1,169 +1,79 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017-2020 Toradex AG
- *
+ * Copyright 2017-2022 Toradex
  */
 
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpiokeys>;
-
-		power {
-			label = "Wake-Up";
-			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
-
-	panel: panel {
-		compatible = "edt,et057090dhu";
-		backlight = <&bl>;
-		power-supply = <&reg_3v3>;
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&lcdif_out>;
-			};
-		};
-	};
-
-	reg_3v3: regulator-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	reg_5v0: regulator-5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_usbh_vbus: regulator-usbh-vbus {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh_reg>;
-		regulator-name = "VCC_USB[1-4]";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
-		vin-supply = <&reg_5v0>;
-	};
-};
-
+/* Colibri AD0 to AD3 */
 &adc1 {
 	status = "okay";
 };
 
-/*
- * ADC2 is not available on the Aster board and
- * conflicts with AD7879 resistive touchscreen.
- */
-&adc2 {
-	status = "disabled";
-};
-
-&bl {
-	brightness-levels = <0 4 8 16 32 64 128 255>;
-	default-brightness-level = <6>;
-	power-supply = <&reg_3v3>;
+/* Colibri SSP */
+&ecspi3 {
+	cs-gpios = <
+		&gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or  */
+		&gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */
+		&gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */
+	>;
 	status = "okay";
 };
 
+/* Colibri Fast Ethernet */
 &fec1 {
 	status = "okay";
 };
 
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
 &i2c4 {
 	status = "okay";
-
-	/* Microchip/Atmel maxtouch controller */
-	touchscreen@4a {
-		compatible = "atmel,maxtouch";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpiotouch>;
-		reg = <0x4a>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;	/* SODIMM 107 */
-		reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;	/* SODIMM 106 */
-	};
-
-	/* M41T0M6 real time clock on carrier board */
-	rtc: rtc@68 {
-		compatible = "st,m41t0";
-		reg = <0x68>;
-	};
-};
-
-&iomuxc {
-	pinctrl_gpiotouch: touchgpios {
-		fsl,pins = <
-			MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x74
-			MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x14
-		>;
-	};
-};
-
-&lcdif {
-	status = "okay";
-
-	port {
-		lcdif_out: endpoint {
-			remote-endpoint = <&panel_in>;
-		};
-	};
 };
 
+/* Colibri PWM<A> */
 &pwm1 {
 	status = "okay";
 };
 
+/* Colibri PWM<B> */
 &pwm2 {
 	status = "okay";
 };
 
+/* Colibri PWM<C> */
 &pwm3 {
 	status = "okay";
 };
 
+/* Colibri PWM<D> */
 &pwm4 {
 	status = "okay";
 };
 
+/* M41T0M6 real time clock */
+&rtc {
+	status = "okay";
+};
+
+/* Colibri UART_A */
 &uart1 {
 	status = "okay";
 };
 
+/* Colibri UART_B */
 &uart2 {
 	status = "okay";
 };
 
+/* Colibri UART_C */
 &uart3 {
 	status = "okay";
 };
 
+/* Colibri USBC */
 &usbotg1 {
 	status = "okay";
 };
 
+/* Colibri MMC/SD */
 &usdhc1 {
-	keep-power-in-suspend;
-	no-1-8-v;
-	wakeup-source;
-	vmmc-supply = <&reg_3v3>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 3b9df8c82ae3..826f13da5b81 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -1,194 +1,110 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
 / {
-	aliases {
-		rtc0 = &rtc;
-		rtc1 = &snvs_rtc;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	/* fixed crystal dedicated to mpc258x */
+	/* Fixed crystal dedicated to MCP2515. */
 	clk16m: clk16m {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <16000000>;
 	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpiokeys>;
-
-		power {
-			label = "Wake-Up";
-			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_WAKEUP>;
-			debounce-interval = <10>;
-			wakeup-source;
-		};
-	};
-
-	panel: panel {
-		compatible = "edt,et057090dhu";
-		backlight = <&bl>;
-		power-supply = <&reg_3v3>;
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&lcdif_out>;
-			};
-		};
-	};
-
-	reg_3v3: regulator-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	reg_5v0: regulator-5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_usbh_vbus: regulator-usbh-vbus {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh_reg>;
-		regulator-name = "VCC_USB[1-4]";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
-		vin-supply = <&reg_5v0>;
-	};
-};
-
-&bl {
-	brightness-levels = <0 4 8 16 32 64 128 255>;
-	default-brightness-level = <6>;
-	power-supply = <&reg_3v3>;
-
-	status = "okay";
 };
 
+/* Colibri AD0 to AD3 */
 &adc1 {
 	status = "okay";
 };
 
-&adc2 {
-	status = "okay";
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	interrupt-parent = <&gpio1>;
+	interrupts = <9 IRQ_TYPE_EDGE_FALLING>;		/* SODIMM 28 / INT */
+	pinctrl-0 = <&pinctrl_atmel_adapter>;
+	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;	/* SODIMM 30 / RST */
+	status = "disabled";
 };
 
+/* Colibri SSP */
 &ecspi3 {
 	status = "okay";
 
 	mcp2515: can@0 {
+		clocks = <&clk16m>;
 		compatible = "microchip,mcp2515";
+		interrupt-parent = <&gpio5>;
+		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_can_int>;
 		reg = <0>;
-		clocks = <&clk16m>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
 		spi-max-frequency = <10000000>;
 		vdd-supply = <&reg_3v3>;
 		xceiver-supply = <&reg_5v0>;
-		status = "okay";
 	};
 };
 
+/* Colibri Fast Ethernet */
 &fec1 {
 	status = "okay";
 };
 
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
 &i2c4 {
 	status = "okay";
-
-	/*
-	 * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
-	 * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
-	 */
-	touchscreen@4a {
-		compatible = "atmel,maxtouch";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpiotouch>;
-		reg = <0x4a>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;		/* SODIMM 28 */
-		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;	/* SODIMM 30 */
-		status = "disabled";
-	};
-
-	/* M41T0M6 real time clock on carrier board */
-	rtc: rtc@68 {
-		compatible = "st,m41t0";
-		reg = <0x68>;
-	};
-};
-
-&lcdif {
-	status = "okay";
-
-	port {
-		lcdif_out: endpoint {
-			remote-endpoint = <&panel_in>;
-		};
-	};
 };
 
+/* Colibri PWM<A> */
 &pwm1 {
 	status = "okay";
 };
 
+/* Colibri PWM<B> */
 &pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
 	status = "okay";
 };
 
+/* Colibri PWM<C> */
 &pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
 	status = "okay";
 };
 
+/* Colibri PWM<D> */
 &pwm4 {
 	status = "okay";
 };
 
+/* M41T0M6 real time clock */
+&rtc {
+	status = "okay";
+};
+
+/* Colibri UART_A */
 &uart1 {
 	status = "okay";
 };
 
+/* Colibri UART_B */
 &uart2 {
 	status = "okay";
 };
 
+/* Colibri UART_C */
 &uart3 {
 	status = "okay";
 };
 
+/* Colibri USBC */
 &usbotg1 {
 	status = "okay";
 };
 
+/* Colibri MMC/SD */
 &usdhc1 {
-	keep-power-in-suspend;
-	wakeup-source;
-	vmmc-supply = <&reg_3v3>;
 	status = "okay";
 };
-
-&iomuxc {
-	pinctrl_gpiotouch: touchgpios {
-		fsl,pins = <
-			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x74
-			MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x14
-		>;
-	};
-};
diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..6e199613583c
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/ {
+	reg_3v3_vmmc: regulator-3v3-vmmc {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "3v3_vmmc";
+		startup-delay-us = <100>;
+	};
+};
+
+/* Colibri AD0 to AD3 */
+&adc1 {
+	status = "okay";
+};
+
+/* Colibri SSP */
+&ecspi3 {
+	status = "okay";
+};
+
+/* Colibri Fast Ethernet */
+&fec1 {
+	status = "okay";
+};
+
+&gpio2 {
+	/*
+	 * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to
+	 * turn the transceiver off, that property has to be deleted and the gpio handled in
+	 * userspace.
+	 * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on.
+	 */
+	uart-b-c-on-x14-enable-hog {
+		gpio-hog;
+		gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+		output-high;
+	};
+};
+
+&gpio5 {
+	uart-a-on-x13-enable-hog {
+		gpio-hog;
+		gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+		output-high;
+	};
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c4 {
+	status = "okay";
+};
+
+/* Colibri PWM<A> */
+&pwm1 {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	status = "okay";
+};
+
+/* Colibri PWM<D> */
+&pwm4 {
+	status = "okay";
+};
+
+/* M41T0M6 real time clock */
+&rtc {
+	status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+	status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+	status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+	status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg1 {
+	status = "okay";
+};
+
+/* Colibri MMC/SD, UHS-I capable uSD slot */
+&usdhc1 {
+	cap-power-off-card;
+	/delete-property/ keep-power-in-suspend;
+	/delete-property/ no-1-8-v;
+	vmmc-supply = <&reg_3v3_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi
new file mode 100644
index 000000000000..175c5d478d2e
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/* Colibri AD0 to AD3 */
+&adc1 {
+	status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	interrupt-parent = <&gpio1>;
+	interrupts = <9 IRQ_TYPE_EDGE_FALLING>;		/* SODIMM 28 / INT */
+	pinctrl-0 = <&pinctrl_atmel_adapter>;
+	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;	/* SODIMM 30 / RST */
+};
+
+/* Colibri SSP */
+&ecspi3 {
+	status = "okay";
+};
+
+/* Colibri Fast Ethernet */
+&fec1 {
+	status = "okay";
+};
+
+&gpio2 {
+	/*
+	 * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the
+	 * transceiver off, that property has to be deleted and the gpio handled in userspace.
+	 * The same applies to uart1_tx_on where the UART1 transceiver is turned on.
+	 */
+	uart25-tx-on-hog {
+		gpio-hog;
+		gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
+		output-high;
+	};
+};
+
+&gpio5 {
+	uart1-tx-on-hog {
+		gpio-hog;
+		gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
+		output-high;
+	};
+};
+
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
+&i2c4 {
+	status = "okay";
+};
+
+/* Colibri PWM<A> */
+&pwm1 {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<D> */
+&pwm4 {
+	status = "okay";
+};
+
+/* M41T0M6 real time clock */
+&rtc {
+	status = "okay";
+};
+
+/* Colibri UART_A */
+&uart1 {
+	status = "okay";
+};
+
+/* Colibri UART_B */
+&uart2 {
+	status = "okay";
+};
+
+/* Colibri UART_C */
+&uart3 {
+	status = "okay";
+};
+
+/* Colibri USBC */
+&usbotg1 {
+	status = "okay";
+};
+
+/* Colibri MMC/SD */
+&usdhc1 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index f1c60b0cb143..a8c31ee65623 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -1,96 +1,198 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
+#include <dt-bindings/pwm/pwm.h>
+
 / {
-	bl: backlight {
+	aliases {
+		rtc0 = &rtc;
+		rtc1 = &snvs_rtc;
+	};
+
+	backlight: backlight {
+		brightness-levels = <0 45 63 88 119 158 203 255>;
 		compatible = "pwm-backlight";
+		default-brightness-level = <4>;
+		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_bl_on>;
-		pwms = <&pwm1 0 5000000 0>;
-		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_module_3v3>;
+		pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
+		status = "disabled";
 	};
 
-	reg_module_3v3: regulator-module-3v3 {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	extcon_usbc_det: usbc-det {
+		compatible = "linux,extcon-usb-gpio";
+		debounce = <25>;
+		id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbc_det>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpiokeys>;
+
+		wakeup {
+			debounce-interval = <10>;
+			gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
+			label = "Wake-Up";
+			linux,code = <KEY_WAKEUP>;
+			wakeup-source;
+		};
+	};
+
+	panel_dpi: panel-dpi {
+		backlight = <&backlight>;
+		compatible = "edt,et057090dhu";
+		power-supply = <&reg_3v3>;
+		status = "disabled";
+
+		port {
+			lcd_panel_in: endpoint {
+				remote-endpoint = <&lcdif_out>;
+			};
+		};
+	};
+
+	reg_3v3: regulator-3v3 {
 		compatible = "regulator-fixed";
-		regulator-name = "+V3.3";
-		regulator-min-microvolt = <3300000>;
+		regulator-always-on;
 		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "3.3V";
+	};
+
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
 		regulator-always-on;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "5V";
+	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "+V3.3";
 	};
 
 	reg_module_3v3_avdd: regulator-module-3v3-avdd {
 		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
 		regulator-name = "+V3.3_AVDD_AUDIO";
+	};
+
+	reg_module_3v3_eth: regulator-module-3v3-eth {
+		compatible = "regulator-fixed";
+		off-on-delay-us = <200000>;
+		regulator-name = "+V3.3_ETH";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		regulator-boot-on;
+		startup-delay-us = <200000>;
+		vin-supply = <&reg_LDO1>;
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh_reg>;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "VCC_USB[1-4]";
+		vin-supply = <&reg_5v0>;
 	};
 
 	sound {
 		compatible = "simple-audio-card";
-		simple-audio-card,name = "imx7-sgtl5000";
-		simple-audio-card,format = "i2s";
 		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,format = "i2s";
 		simple-audio-card,frame-master = <&dailink_master>;
+		simple-audio-card,name = "imx7-sgtl5000";
+
 		simple-audio-card,cpu {
 			sound-dai = <&sai1>;
 		};
 
 		dailink_master: simple-audio-card,codec {
-			sound-dai = <&codec>;
 			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+			sound-dai = <&codec>;
 		};
 	};
 };
 
+/* Colibri AD0 to AD3 */
 &adc1 {
 	vref-supply = <&reg_DCDC3>;
 };
 
-&adc2 {
-	vref-supply = <&reg_DCDC3>;
-};
+/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */
 
 &cpu0 {
 	cpu-supply = <&reg_DCDC2>;
 };
 
+/* Colibri SSP */
 &ecspi3 {
+	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
-	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
 };
 
+/* Colibri Fast Ethernet */
 &fec1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_enet1>;
-	pinctrl-1 = <&pinctrl_enet1_sleep>;
-	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
-		<&clks IMX7D_ENET_AXI_ROOT_CLK>,
-		<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
-		<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
-	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
-	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
-			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 	assigned-clock-rates = <0>, <100000000>;
-	phy-mode = "rmii";
-	phy-supply = <&reg_LDO1>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+		 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+		 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+		 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
 	fsl,magic-packet;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rmii";
+	phy-supply = <&reg_module_3v3_eth>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-1 = <&pinctrl_enet1_sleep>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Micrel KSZ8041RNL */
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			max-speed = <100>;
+			micrel,led-mode = <0>;
+			reg = <0>;
+		};
+	};
 };
 
 &flexcan1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan1>;
-	status = "disabled";
 };
 
 &flexcan2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;
-	status = "disabled";
 };
 
 &gpio1 {
@@ -271,14 +373,16 @@ &gpio7 {
 			  "SODIMM_137";
 };
 
+/* NAND on such SKUs */
 &gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
 	fsl,use-minimum-ecc;
-	nand-on-flash-bbt;
 	nand-ecc-mode = "hw";
+	nand-on-flash-bbt;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
 };
 
+/* On-module Power I2C */
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default", "gpio";
@@ -286,33 +390,33 @@ &i2c1 {
 	pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
 	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
 	status = "okay";
 
 	codec: sgtl5000@a {
-		compatible = "fsl,sgtl5000";
 		#sound-dai-cells = <0>;
-		reg = <0x0a>;
 		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
+		compatible = "fsl,sgtl5000";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_sai1_mclk>;
+		reg = <0xa>;
 		VDDA-supply = <&reg_module_3v3_avdd>;
-		VDDIO-supply = <&reg_module_3v3>;
 		VDDD-supply = <&reg_DCDC3>;
+		VDDIO-supply = <&reg_module_3v3>;
 	};
 
-	ad7879@2c {
+	ad7879_ts: touchscreen@2c {
+		adi,acquisition-time = /bits/ 8 <1>;
+		adi,averaging = /bits/ 8 <1>;
+		adi,conversion-interval = /bits/ 8 <255>;
+		adi,first-conversion-delay = /bits/ 8 <3>;
+		adi,median-filter-size = /bits/ 8 <2>;
+		adi,resistance-plate-x = <120>;
 		compatible = "adi,ad7879-1";
-		reg = <0x2c>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+		reg = <0x2c>;
 		touchscreen-max-pressure = <4096>;
-		adi,resistance-plate-x = <120>;
-		adi,first-conversion-delay = /bits/ 8 <3>;
-		adi,acquisition-time = /bits/ 8 <1>;
-		adi,median-filter-size = /bits/ 8 <2>;
-		adi,averaging = /bits/ 8 <1>;
-		adi,conversion-interval = /bits/ 8 <255>;
+		status = "disabled";
 	};
 
 	pmic@33 {
@@ -320,71 +424,81 @@ pmic@33 {
 		reg = <0x33>;
 
 		regulators {
-			reg_DCDC1: DCDC1 {  /* V1.0_SOC */
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1100000>;
-				regulator-boot-on;
+			reg_DCDC1: DCDC1 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1100000>;
+				regulator-min-microvolt = <1000000>;
+				regulator-name = "+V1.0_SOC";
 			};
 
-			reg_DCDC2: DCDC2 { /* V1.1_ARM */
-				regulator-min-microvolt = <975000>;
-				regulator-max-microvolt = <1100000>;
-				regulator-boot-on;
+			reg_DCDC2: DCDC2 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1100000>;
+				regulator-min-microvolt = <975000>;
+				regulator-name = "+V1.1_ARM";
 			};
 
-			reg_DCDC3: DCDC3 { /* V1.8 */
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
+			reg_DCDC3: DCDC3 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "+V1.8";
 			};
 
-			reg_DCDC4: DCDC4 { /* V1.35_DRAM */
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-boot-on;
+			reg_DCDC4: DCDC4 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1350000>;
+				regulator-min-microvolt = <1350000>;
+				regulator-name = "+V1.35_DRAM";
 			};
 
-			reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
+			reg_LDO1: LDO1 {
 				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <3300000>;
+				regulator-name = "PWR_EN_+V3.3_ETH";
 			};
 
-			reg_LDO2: LDO2 { /* +V1.8_SD */
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
+			reg_LDO2: LDO2 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "+V1.8_SD";
 			};
 
-			reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
+			reg_LDO3: LDO3 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <3300000>;
+				regulator-name = "PWR_EN_+V3.3_LPSR";
 			};
 
-			reg_LDO4: LDO4 { /* V1.8_LPSR */
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
+			reg_LDO4: LDO4 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "+V1.8_LPSR";
 			};
 
-			reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
+			reg_LDO5: LDO5 {
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <3300000>;
+				regulator-name = "PWR_EN_+V3.3";
 			};
 		};
 	};
 };
 
+/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
 &i2c4 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default", "gpio";
@@ -392,36 +506,69 @@ &i2c4 {
 	pinctrl-1 = <&pinctrl_i2c4_recovery>;
 	scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "disabled";
+
+	/* Atmel maxtouch controller */
+	atmel_mxt_ts: touchscreen@4a {
+		compatible = "atmel,maxtouch";
+		interrupt-parent = <&gpio2>;
+		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;        /* SODIMM 107 / INT */
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_atmel_connector>;
+		reg = <0x4a>;
+		reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;      /* SODIMM 106 / RST */
+		status = "disabled";
+	};
+
+	/* M41T0M6 real time clock on carrier board */
+	rtc: rtc@68 {
+		compatible = "st,m41t0";
+		reg = <0x68>;
+		status = "disabled";
+	};
 };
 
 &lcdif {
+	assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcdif_dat
 		     &pinctrl_lcdif_ctrl>;
+	status = "disabled";
+
+	port {
+		lcdif_out: endpoint {
+			remote-endpoint = <&lcd_panel_in>;
+		};
+	};
 };
 
+/* Colibri PWM<A> */
 &pwm1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
 };
 
+/* Colibri PWM<B> */
 &pwm2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm2>;
 };
 
+/* Colibri PWM<C> */
 &pwm3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm3>;
 };
 
+/* Colibri PWM<D> */
 &pwm4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm4>;
 };
 
 &reg_1p0d {
-	vin-supply = <&reg_DCDC3>;
+	vin-supply = <&reg_DCDC3>; /* VDDA_1P8_IN */
 };
 
 &sai1 {
@@ -430,237 +577,257 @@ &sai1 {
 	status = "okay";
 };
 
+/* Colibri UART_A */
 &uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
 	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
-	uart-has-rtscts;
 	fsl,dte-mode;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
+	uart-has-rtscts;
 };
 
+/* Colibri UART_B */
 &uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
 	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
-	uart-has-rtscts;
 	fsl,dte-mode;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
 };
 
+/* Colibri UART_C */
 &uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
 	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 	fsl,dte-mode;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
 };
 
+/* Colibri USBC */
 &usbotg1 {
-	dr_mode = "host";
+	dr_mode = "otg";
+	extcon = <0>, <&extcon_usbc_det>;
 };
 
+/* Colibri MMC/SD */
 &usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
 	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 	disable-wp;
+	no-1-8-v;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
+	pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
+	vmmc-supply = <&reg_3v3>;
 	vqmmc-supply = <&reg_LDO2>;
+	wakeup-source;
 };
 
+/* eMMC on 1GB (eMMC) SKUs */
 &usdhc3 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 	assigned-clock-rates = <400000000>;
 	bus-width = <8>;
 	fsl,tuning-step = <2>;
-	vmmc-supply = <&reg_module_3v3>;
-	vqmmc-supply = <&reg_DCDC3>;
 	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 	sdhci-caps-mask = <0x80000000 0x0>;
+	vmmc-supply = <&reg_module_3v3>;
+	vqmmc-supply = <&reg_DCDC3>;
 };
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
-		     &pinctrl_gpio7 &pinctrl_usbc_det>;
-
-	pinctrl_gpio1: gpio1-grp {
-		fsl,pins = <
-			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
-			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
-			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
-			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
-			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x14 /* SODIMM 95 */
-			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11	0x14 /* SODIMM 99 */
-			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
-			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
-			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
-			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
-			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
-			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
-			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
-			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
-			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
-			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
-			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
-			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
-			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
-			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
-			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
-			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
-			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
-			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
-			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
-			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
-			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
-			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
-			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
-			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
-			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
-			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
-			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
-			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
-			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
-			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
-			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
-			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
-			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
-			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
-		>;
-	};
-
-	pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
+	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+
+	/*
+	 * Atmel MXT touchsceen + Capacitive Touch Adapter
+	 * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
+	 * Don't use them simultaneously.
+	 */
+	pinctrl_atmel_adapter: atmelconnectorgrp {
 		fsl,pins = <
-			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x14 /* SODIMM 65 */
-			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x74 /* SODIMM 69 */
-			MX7D_PAD_I2C4_SDA__GPIO4_IO15		0x14 /* SODIMM 75 */
-			MX7D_PAD_ECSPI1_MISO__GPIO4_IO18	0x14 /* SODIMM 79 */
-			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x14 /* SODIMM 81 */
-			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x14 /* SODIMM 85 */
-			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19		0x14 /* SODIMM 97 */
-			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x14 /* SODIMM 101 */
-			MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17	0x14 /* SODIMM 103 */
-			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x14 /* SODIMM 94 */
-			MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x14 /* SODIMM 96 */
-			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
+			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x74 /* SODIMM 28 / INT */
+			MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x14 /* SODIMM 30 / RST */
 		>;
 	};
 
-	pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
+	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+	pinctrl_atmel_connector: atmeladaptergrp {
 		fsl,pins = <
-			MX7D_PAD_LCD_DATA18__GPIO3_IO23		0x14 /* SODIMM 136 */
-			MX7D_PAD_LCD_DATA19__GPIO3_IO24		0x14 /* SODIMM 138 */
-			MX7D_PAD_LCD_DATA20__GPIO3_IO25		0x14 /* SODIMM 140 */
-			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x14 /* SODIMM 142 */
-			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x74 /* SODIMM 144 */
-			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x74 /* SODIMM 146 */
+			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x14 /* SODIMM 106 / RST */
+			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x74 /* SODIMM 107 / INT */
 		>;
 	};
 
-	pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
+	pinctrl_can_int: canintgrp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO15__GPIO1_IO15		0x14 /* SODIMM 178 */
-			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x14 /* SODIMM 188 */
+			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
 		>;
 	};
 
-	pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
+	pinctrl_ecspi3: ecspi3grp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x14 /* SODIMM 55 */
-			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x14 /* SODIMM 63 */
+			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2 /* SODIMM 90 */
+			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2 /* SODIMM 92 */
+			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2 /* SODIMM 88 */
 		>;
 	};
 
-	pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
+	pinctrl_ecspi3_cs: ecspi3csgrp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x79
-		>;
-	};
-
-	pinctrl_can_int: can-int-grp {
-		fsl,pins = <
-			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
+			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14 /* SODIMM 86 */
 		>;
 	};
 
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x73
 			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x73
 			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x73
 			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER		0x73
-
-			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x73
+			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x73
 			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x73
 			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x73
+			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x73
 			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x73
 			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
 			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
 		>;
 	};
 
-	pinctrl_enet1_sleep: enet1sleepgrp {
+	pinctrl_enet1_sleep: enet1-sleepgrp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4		0x0
 			MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0		0x0
 			MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1		0x0
 			MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5		0x0
-
-			MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10		0x0
+			MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4		0x0
 			MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6		0x0
 			MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7		0x0
+			MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10		0x0
 			MX7D_PAD_GPIO1_IO12__GPIO1_IO12			0x0
 			MX7D_PAD_SD2_CD_B__GPIO5_IO9			0x0
 			MX7D_PAD_SD2_WP__GPIO5_IO10			0x0
 		>;
 	};
 
-	pinctrl_ecspi3_cs: ecspi3-cs-grp {
+	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
-			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
+			MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX	0x79 /* SODIMM 63 */
+			MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX	0x79 /* SODIMM 55 */
 		>;
 	};
 
-	pinctrl_ecspi3: ecspi3-grp {
+	pinctrl_flexcan2: flexcan2grp {
 		fsl,pins = <
-			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
-			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
-			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
+			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x79 /* SODIMM 188 */
+			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x79 /* SODIMM 178 */
 		>;
 	};
 
-	pinctrl_flexcan1: flexcan1-grp {
+	pinctrl_gpio1: gpio1grp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX	0x79 /* SODIMM 55 */
-			MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX	0x79 /* SODIMM 63 */
+			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
+			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
+			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
+			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
+			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
+			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
+			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
+			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
+			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
+			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
+			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
+			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
+			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
+			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
+			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
+			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
+			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
+			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
+			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
+			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
+			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
+			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
+			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
+			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
+			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
+			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
+			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
+			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
+			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
+			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
+			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
+			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
+			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
+			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
+			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
+			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
+			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
+			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
 		>;
 	};
 
-	pinctrl_flexcan2: flexcan2-grp {
+	pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x79 /* SODIMM 188 */
-			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x79 /* SODIMM 178 */
+			MX7D_PAD_ECSPI1_MISO__GPIO4_IO18	0x14 /* SODIMM 79 */
+			MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17	0x14 /* SODIMM 103 */
+			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x14 /* SODIMM 101 */
+			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19		0x14 /* SODIMM 97 */
+			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x14 /* SODIMM 85 */
+			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x14 /* SODIMM 65 */
+			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x14 /* SODIMM 81 */
+			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x14 /* SODIMM 94 */
+			MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x14 /* SODIMM 96 */
+			MX7D_PAD_I2C4_SDA__GPIO4_IO15		0x14 /* SODIMM 75 */
+			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x74 /* SODIMM 69 */
+			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
+		>;
+	};
+
+	pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA18__GPIO3_IO23		0x14 /* SODIMM 136 */
+			MX7D_PAD_LCD_DATA19__GPIO3_IO24		0x14 /* SODIMM 138 */
+			MX7D_PAD_LCD_DATA20__GPIO3_IO25		0x14 /* SODIMM 140 */
+			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x14 /* SODIMM 142 */
+			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x74 /* SODIMM 144 */
+			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x74 /* SODIMM 146 */
+		>;
+	};
+
+	pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x14 /* SODIMM 188 */
+			MX7D_PAD_GPIO1_IO15__GPIO1_IO15		0x14 /* SODIMM 178 */
+		>;
+	};
+
+	pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
+		fsl,pins = <
+			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x14 /* SODIMM 63 */
+			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x14 /* SODIMM 55 */
 		>;
 	};
 
-	pinctrl_gpio_bl_on: gpio-bl-on {
+	pinctrl_gpio_bl_on: gpioblongrp {
 		fsl,pins = <
 			MX7D_PAD_SD1_WP__GPIO5_IO1		0x14 /* SODIMM 71 */
 		>;
 	};
 
-	pinctrl_gpmi_nand: gpmi-nand-grp {
+	pinctrl_gpmi_nand: gpminandgrp {
 		fsl,pins = <
-			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
-			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
 			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
 			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
-			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
-			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
+			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
 			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
 			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
 			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
@@ -669,13 +836,21 @@ MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
 			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
 			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
 			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
 		>;
 	};
 
-	pinctrl_i2c4: i2c4-grp {
+	pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
 		fsl,pins = <
-			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f
-			MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL	0x4000007f
+			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x79
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL	0x4000007f /* SODIMM 196 */
+			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f /* SODIMM 194 */
 		>;
 	};
 
@@ -686,155 +861,176 @@ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9	0x4000007f
 		>;
 	};
 
-	pinctrl_lcdif_dat: lcdif-dat-grp {
+	pinctrl_lcdif_dat: lcdifdatgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79 /* SODIMM 76 */
+			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79 /* SODIMM 70 */
+			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79 /* SODIMM 60 */
+			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79 /* SODIMM 58 */
+			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79 /* SODIMM 78 */
+			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79 /* SODIMM 72 */
+			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79 /* SODIMM 80 */
+			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79 /* SODIMM 46 */
+			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79 /* SODIMM 62 */
+			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79 /* SODIMM 48 */
+			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79 /* SODIMM 74 */
+			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79 /* SODIMM 50 */
+			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79 /* SODIMM 52 */
+			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79 /* SODIMM 54 */
+			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79 /* SODIMM 66 */
+			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79 /* SODIMM 64 */
+			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79 /* SODIMM 57 */
+			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79 /* SODIMM 61 */
+		>;
+	};
+
+	pinctrl_lcdif_dat_24: lcdifdat24grp {
 		fsl,pins = <
-			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
-			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
-			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
-			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
-			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
-			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
-			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
-			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
-			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
-			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
-			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
-			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
-			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
-			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
-			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
-			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
-			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
-			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
+			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79 /* SODIMM 136 */
+			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79 /* SODIMM 138 */
+			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79 /* SODIMM 140 */
+			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79 /* SODIMM 142 */
+			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79 /* SODIMM 144 */
+			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79 /* SODIMM 146 */
 		>;
 	};
 
-	pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
+	pinctrl_lcdif_ctrl: lcdifctrlgrp {
 		fsl,pins = <
-			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
-			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
-			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
-			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
-			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
-			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
+			MX7D_PAD_LCD_CLK__LCD_CLK		0x79 /* SODIMM 56 */
+			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79 /* SODIMM 44 */
+			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79 /* SODIMM 68 */
+			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79 /* SODIMM 82 */
 		>;
 	};
 
-	pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+	pinctrl_lvds_transceiver: lvdstx {
 		fsl,pins = <
-			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
-			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
-			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
-			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
+			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
+			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x74 /* SODIMM 55 */
+			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
+			MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
 		>;
 	};
 
-	pinctrl_pwm1: pwm1-grp {
+	pinctrl_pwm1: pwm1grp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO08__PWM1_OUT		0x79
-			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x4
+			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x4  /* SODIMM 59 */
+			MX7D_PAD_GPIO1_IO08__PWM1_OUT		0x79 /* SODIMM 59 */
 		>;
 	};
 
-	pinctrl_pwm2: pwm2-grp {
+	pinctrl_pwm2: pwm2grp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x79
+			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x79 /* SODIMM 28 */
 		>;
 	};
 
-	pinctrl_pwm3: pwm3-grp {
+	pinctrl_pwm3: pwm3grp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO10__PWM3_OUT		0x79
+			MX7D_PAD_GPIO1_IO10__PWM3_OUT		0x79 /* SODIMM 30 */
 		>;
 	};
 
-	pinctrl_pwm4: pwm4-grp {
+	pinctrl_pwm4: pwm4grp {
 		fsl,pins = <
-			MX7D_PAD_GPIO1_IO11__PWM4_OUT		0x79
-			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x4
+			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x4  /* SODIMM 67 */
+			MX7D_PAD_GPIO1_IO11__PWM4_OUT		0x79 /* SODIMM 67 */
 		>;
 	};
 
-	pinctrl_uart1: uart1-grp {
+	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79
-			MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79
-			MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS	0x79
-			MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS	0x79
+			MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS	0x79 /* SODIMM 25 */
+			MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS	0x79 /* SODIMM 27 */
+			MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79 /* SODIMM 35 */
+			MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79 /* SODIMM 33 */
 		>;
 	};
 
-	pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
+	pinctrl_uart1_ctrl1: uart1ctrl1grp {
 		fsl,pins = <
-			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x14 /* DCD */
-			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* DTR */
+			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* SODIMM 23 / DTR */
+			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x14 /* SODIMM 31 / DCD */
 		>;
 	};
 
-	pinctrl_uart2: uart2-grp {
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS	0x79 /* SODIMM 32 / CTS */
+			MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS	0x79 /* SODIMM 34 / RTS */
+			MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX	0x79 /* SODIMM 38 */
+			MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX	0x79 /* SODIMM 36 */
+		>;
+	};
+	pinctrl_uart3: uart3grp {
 		fsl,pins = <
-			MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
-			MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
-			MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
-			MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
+			MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79 /* SODIMM 21 */
+			MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79 /* SODIMM 19 */
 		>;
 	};
-	pinctrl_uart3: uart3-grp {
+
+	pinctrl_usbc_det: usbcdetgrp {
 		fsl,pins = <
-			MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
-			MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
+			MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x14 /* SODIMM 137 / USBC_DET */
 		>;
 	};
 
-	pinctrl_usbc_det: gpio-usbc-det {
+	pinctrl_usbh_reg: usbhreggrp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_CRS__GPIO7_IO14	0x14
+			MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14 /* SODIMM 129 / USBH_PEN */
 		>;
 	};
 
-	pinctrl_usbh_reg: gpio-usbh-vbus {
+	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
-			MX7D_PAD_UART3_CTS_B__GPIO4_IO7	0x14 /* SODIMM 129 USBH PEN */
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x19 /* SODIMM 47 */
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x59 /* SODIMM 190 */
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59 /* SODIMM 192 */
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59 /* SODIMM 49 */
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59 /* SODIMM 51 */
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59 /* SODIMM 53 */
 		>;
 	};
 
-	pinctrl_usdhc1: usdhc1-grp {
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <
-			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
-			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
-			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
-			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
-			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
-			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
 		>;
 	};
 
-	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <
-			MX7D_PAD_SD1_CMD__SD1_CMD	0x5a
-			MX7D_PAD_SD1_CLK__SD1_CLK	0x1a
-			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5a
-			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5a
-			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5a
-			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5a
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
 		>;
 	};
 
-	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+	/* Avoid backfeeding with removed card power. */
+	pinctrl_usdhc1_sleep: usdhc1-slpgrp {
 		fsl,pins = <
-			MX7D_PAD_SD1_CMD__SD1_CMD	0x5b
-			MX7D_PAD_SD1_CLK__SD1_CLK	0x1b
-			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x5b
-			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x5b
-			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x5b
-			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x5b
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x10
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x10
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x10
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x10
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x10
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x10
 		>;
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
 		fsl,pins = <
-			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
 			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
 			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
 			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
 			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
@@ -847,10 +1043,10 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 		>;
 	};
 
-	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 		fsl,pins = <
-			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
 			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
 			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
 			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
 			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
@@ -863,10 +1059,10 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 		>;
 	};
 
-	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 		fsl,pins = <
-			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
 			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
 			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
 			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
 			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
@@ -879,16 +1075,16 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 		>;
 	};
 
-	pinctrl_sai1: sai1-grp {
+	pinctrl_sai1: sai1grp {
 		fsl,pins = <
-			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
-			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
 			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
+			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
+			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
 		>;
 	};
 
-	pinctrl_sai1_mclk: sai1grp_mclk {
+	pinctrl_sai1_mclk: sai1mclkgrp {
 		fsl,pins = <
 			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 		>;
@@ -899,23 +1095,35 @@ &iomuxc_lpsr {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio_lpsr>;
 
-	pinctrl_gpio_lpsr: gpio1-grp {
+	pinctrl_cd_usdhc1: cdusdhc1grp {
 		fsl,pins = <
-			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59
-			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59
+			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* SODIMM 43 / MMC_CD */
+		>;
+	};
+
+	pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x0
+		>;
+	};
+
+	pinctrl_gpio_lpsr: gpiolpsrgrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59 /* SODIMM 135 */
+			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59 /* SODIMM 22 */
 		>;
 	};
 
 	pinctrl_gpiokeys: gpiokeysgrp {
 		fsl,pins = <
-			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x19
+			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x19 /* SODIMM 45 / WAKE_UP */
 		>;
 	};
 
-	pinctrl_i2c1: i2c1-grp {
+	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
 			MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f
+			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
 		>;
 	};
 
@@ -926,16 +1134,10 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x4000007f
 		>;
 	};
 
-	pinctrl_cd_usdhc1: usdhc1-cd-grp {
-		fsl,pins = <
-			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* CD */
-		>;
-	};
-
-	pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
+	pinctrl_uart1_ctrl2: uart1ctrl2grp {
 		fsl,pins = <
-			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* DSR */
-			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* RI */
+			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* SODIMM 37 / RI */
+			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* SODIMM 29 / DSR */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts
index f3f0537d5a37..90aaeddfb4f6 100644
--- a/arch/arm/boot/dts/imx7d-colibri-aster.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts
@@ -1,7 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017-2020 Toradex AG
- *
+ * Copyright 2017-2022 Toradex
  */
 
 /dts-v1/;
@@ -10,11 +9,32 @@
 
 / {
 	model = "Toradex Colibri iMX7D on Aster Carrier Board";
-	compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d",
+	compatible = "toradex,colibri-imx7d-aster",
+		     "toradex,colibri-imx7d",
 		     "fsl,imx7d";
 };
 
+&ad7879_ts {
+	status = "okay";
+};
+
+&atmel_mxt_ts {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri USBH */
 &usbotg2 {
-	vbus-supply = <&reg_usbh_vbus>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
index 20480276cb0e..3ec9ef6baaa4 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017-2020 Toradex AG
+ * Copyright 2017-2022 Toradex
  *
  */
 
@@ -11,10 +11,12 @@
 / {
 	model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
 	compatible = "toradex,colibri-imx7d-emmc-aster",
-		     "toradex,colibri-imx7d-emmc", "fsl,imx7d";
+		     "toradex,colibri-imx7d-emmc",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
 };
 
+/* Colibri USBH */
 &usbotg2 {
-	vbus-supply = <&reg_usbh_vbus>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
index 8ee73c870b12..6d505cb02aad 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
  */
 
 /dts-v1/;
@@ -10,10 +10,12 @@
 / {
 	model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3";
 	compatible = "toradex,colibri-imx7d-emmc-eval-v3",
-		     "toradex,colibri-imx7d-emmc", "fsl,imx7d";
+		     "toradex,colibri-imx7d-emmc",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
 };
 
+/* Colibri USBH */
 &usbotg2 {
-	vbus-supply = <&reg_usbh_vbus>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
new file mode 100644
index 000000000000..7347659557f3
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board";
+	compatible = "toradex,colibri-imx7d-emmc-iris-v2",
+		     "toradex,colibri-imx7d-emmc",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
new file mode 100644
index 000000000000..5324c92e368d
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board";
+	compatible = "toradex,colibri-imx7d-emmc-iris",
+		     "toradex,colibri-imx7d-emmc",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index af39e5370fa1..2fb4d2133a1b 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -1,18 +1,28 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
  */
 
 #include "imx7d.dtsi"
 #include "imx7-colibri.dtsi"
 
 / {
+	aliases {
+		/* Required to properly pass MAC addresses from bootloader. */
+		ethernet0 = &fec1;
+		ethernet1 = &fec2;
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>;
 	};
 };
 
+&cpu1 {
+	cpu-supply = <&reg_DCDC2>;
+};
+
 &gpio6 {
 	gpio-line-names = "",
 			  "",
@@ -39,10 +49,13 @@ &gpio6 {
 			  "SODIMM_34";
 };
 
+/* Colibri USBH */
 &usbotg2 {
 	dr_mode = "host";
+	vbus-supply = <&reg_usbh_vbus>;
 };
 
+/* eMMC */
 &usdhc3 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index 87b132bcd272..c7a8b5aa2408 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
 /dts-v1/;
@@ -9,11 +9,48 @@
 
 / {
 	model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
-	compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
+	compatible = "toradex,colibri-imx7d-eval-v3",
+		     "toradex,colibri-imx7d",
 		     "fsl,imx7d";
 };
 
+&ad7879_ts {
+	status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	status = "disabled";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri USBH */
 &usbotg2 {
-	vbus-supply = <&reg_usbh_vbus>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
new file mode 100644
index 000000000000..5762f51d5f0f
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7D on Iris V2 Carrier Board";
+	compatible = "toradex,colibri-imx7d-iris-v2",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
+};
+
+&ad7879_ts {
+	status = "okay";
+};
+
+&atmel_mxt_ts {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&gpio2 {
+	/*
+	 * This switches the LVDS transceiver to VESA color mapping mode.
+	 */
+	lvds-color-map-hog {
+		gpio-hog;
+		gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+		line-name = "LVDS_COLOR_MAP";
+		output-low;
+	};
+};
+
+&gpio7 {
+	/*
+	 * This switches the LVDS transceiver to the 24-bit RGB mode.
+	 */
+	lvds-rgb-mode-hog {
+		gpio-hog;
+		gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+		line-name = "LVDS_RGB_MODE";
+		output-low;
+	};
+
+	/*
+	 * This switches the LVDS transceiver to the single-channel
+	 * output mode.
+	 */
+	lvds-ch-mode-hog {
+		gpio-hog;
+		gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+		line-name = "LVDS_CH_MODE";
+		output-high;
+	};
+
+	/* This turns the LVDS transceiver on */
+	lvds-power-on-hog {
+		gpio-hog;
+		gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+		line-name = "LVDS_POWER_ON";
+		output-high;
+	};
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts
new file mode 100644
index 000000000000..9c63cb9d9a64
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7D on Iris Carrier Board";
+	compatible = "toradex,colibri-imx7d-iris",
+		     "toradex,colibri-imx7d",
+		     "fsl,imx7d";
+};
+
+&ad7879_ts {
+	status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	status = "disabled";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri USBH */
+&usbotg2 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 219a0404a058..531a45b176a1 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -1,12 +1,18 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
 #include "imx7d.dtsi"
 #include "imx7-colibri.dtsi"
 
 / {
+	aliases {
+		/* Required to properly pass MAC addresses from bootloader. */
+		ethernet0 = &fec1;
+		ethernet1 = &fec2;
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x20000000>;
@@ -17,10 +23,13 @@ &cpu1 {
 	cpu-supply = <&reg_DCDC2>;
 };
 
+/* NAND */
 &gpmi {
 	status = "okay";
 };
 
+/* Colibri USBH */
 &usbotg2 {
 	dr_mode = "host";
+	vbus-supply = <&reg_usbh_vbus>;
 };
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index f053f5122741..78f4224a9bf4 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -201,7 +201,7 @@ tsc2046@0 {
 		compatible = "ti,tsc2046";
 		reg = <0>;
 		spi-max-frequency = <1000000>;
-		pinctrl-names ="default";
+		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 		interrupt-parent = <&gpio2>;
 		interrupts = <29 0>;
diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts
index c6b32064a009..21b509c43393 100644
--- a/arch/arm/boot/dts/imx7d-smegw01.dts
+++ b/arch/arm/boot/dts/imx7d-smegw01.dts
@@ -216,10 +216,8 @@ &usdhc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	bus-width = <4>;
+	no-1-8-v;
 	non-removable;
-	cap-sd-highspeed;
-	sd-uhs-ddr50;
-	mmc-ddr-1_8v;
 	vmmc-supply = <&reg_wifi>;
 	enable-sdio-wakeup;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index f8cba47536a0..7ceb7c09f7ad 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -78,7 +78,7 @@ usbphynop2: usbphynop2 {
 		#phy-cells = <0>;
 	};
 
-	soc {
+	soc: soc {
 		etm@3007d000 {
 			compatible = "arm,coresight-etm3x", "arm,primecell";
 			reg = <0x3007d000 0x1000>;
diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts
index fca4e0a95c1b..58ebb02d948a 100644
--- a/arch/arm/boot/dts/imx7s-colibri-aster.dts
+++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2017-2020 Toradex AG
+ * Copyright 2017-2022 Toradex
  *
  */
 
@@ -10,6 +10,27 @@
 
 / {
 	model = "Toradex Colibri iMX7S on Aster Carrier Board";
-	compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s",
+	compatible = "toradex,colibri-imx7s-aster",
+		     "toradex,colibri-imx7s",
 		     "fsl,imx7s";
 };
+
+&ad7879_ts {
+	status = "okay";
+};
+
+&atmel_mxt_ts {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
index aa70d3f2e2e2..38de76630d6a 100644
--- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
 /dts-v1/;
@@ -9,6 +9,43 @@
 
 / {
 	model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3";
-	compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s",
+	compatible = "toradex,colibri-imx7s-eval-v3",
+		     "toradex,colibri-imx7s",
 		     "fsl,imx7s";
 };
+
+&ad7879_ts {
+	status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	status = "disabled";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
new file mode 100644
index 000000000000..72b5c17ab1ab
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-iris-v2.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7S on Iris V2 Carrier Board";
+	compatible = "toradex,colibri-imx7s-iris-v2",
+		     "toradex,colibri-imx7s",
+		     "fsl,imx7s";
+};
+
+&ad7879_ts {
+	status = "okay";
+};
+
+&atmel_mxt_ts {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&gpio2 {
+	/*
+	 * This switches the LVDS transceiver to VESA color mapping mode.
+	 */
+	lvds-color-map-hog {
+		gpio-hog;
+		gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+		line-name = "LVDS_COLOR_MAP";
+		output-low;
+	};
+};
+
+&gpio7 {
+	/*
+	 * This switches the LVDS transceiver to the 24-bit RGB mode.
+	 */
+	lvds-rgb-mode-hog {
+		gpio-hog;
+		gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+		line-name = "LVDS_RGB_MODE";
+		output-low;
+	};
+
+	/*
+	 * This switches the LVDS transceiver to the single-channel
+	 * output mode.
+	 */
+	lvds-ch-mode-hog {
+		gpio-hog;
+		gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+		line-name = "LVDS_CH_MODE";
+		output-high;
+	};
+
+	/* This turns the LVDS transceiver on */
+	lvds-power-on-hog {
+		gpio-hog;
+		gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+		line-name = "LVDS_POWER_ON";
+		output-high;
+	};
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts
new file mode 100644
index 000000000000..26ba72c17feb
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-iris.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-iris.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX7S on Iris Carrier Board";
+	compatible = "toradex,colibri-imx7s-iris",
+		     "toradex,colibri-imx7s",
+		     "fsl,imx7s";
+};
+
+&ad7879_ts {
+	status = "okay";
+};
+
+/*
+ * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
+ */
+&atmel_mxt_ts {
+	status = "disabled";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&panel_dpi {
+	status = "okay";
+};
+
+/* Colibri PWM<B> */
+&pwm2 {
+	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
+
+/* Colibri PWM<C> */
+&pwm3 {
+	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index 94de220a5965..ef51395d3537 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2016-2020 Toradex
+ * Copyright 2016-2022 Toradex
  */
 
 #include "imx7s.dtsi"
@@ -13,6 +13,7 @@ memory@80000000 {
 	};
 };
 
+/* NAND */
 &gpmi {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 008e3da460f1..29148285f9fc 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -120,6 +120,7 @@ usbphynop3: usbphynop3 {
 		compatible = "usb-nop-xceiv";
 		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_hsic_phy>;
 		#phy-cells = <0>;
 	};
 
@@ -175,7 +176,7 @@ timer {
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	soc {
+	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
@@ -1153,7 +1154,6 @@ usbh: usb@30b30000 {
 				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x30b30000 0x200>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-				power-domains = <&pgc_hsic_phy>;
 				clocks = <&clks IMX7D_USB_CTRL_CLK>;
 				fsl,usbphy = <&usbphynop3>;
 				fsl,usbmisc = <&usbmisc3 0>;
diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi
index 77b911b06041..03e6a858a7be 100644
--- a/arch/arm/boot/dts/imxrt1050.dtsi
+++ b/arch/arm/boot/dts/imxrt1050.dtsi
@@ -83,7 +83,7 @@ edma1: dma-controller@400e8000 {
 		};
 
 		usdhc1: mmc@402c0000 {
-			compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+			compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
 			reg = <0x402c0000 0x4000>;
 			interrupts = <110>;
 			clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
@@ -95,7 +95,7 @@ usdhc1: mmc@402c0000 {
 			no-1-8-v;
 			max-frequency = <4000000>;
 			fsl,tuning-start-tap = <20>;
-			fsl,tuning-step= <2>;
+			fsl,tuning-step = <2>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
index 71064483d34f..42cf74db673c 100644
--- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x2000>;
-	linkram0	= <0x100000 0x4000>;
-	linkram1	= <0 0x10000>;
+	queue-range = <0 0x2000>;
+	linkram0 = <0x100000 0x4000>;
+	linkram1 = <0 0x10000>;
 
 	qmgrs {
 		#address-cells = <1>;
@@ -176,40 +176,40 @@ cpts_refclk_mux: cpts-refclk-mux {
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy0>;
+					link-interface = <1>;
+					phy-handle = <&ethphy0>;
 				};
 				gbe1: interface-1 {
 					slave-port = <1>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy1>;
+					link-interface = <1>;
+					phy-handle = <&ethphy1>;
 				};
 			};
 
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-4 {
 					slave-port = <4>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-5 {
 					slave-port = <5>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-6 {
 					slave-port = <6>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-7 {
 					slave-port = <7>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index b8f152e7af7f..65c32946c522 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -141,7 +141,7 @@ pcie1: pcie@21020000 {
 			clock-names = "pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
-			reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+			reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
 			ranges = <0x82000000 0 0x60000000 0x60000000
 				  0 0x10000000>;
 
@@ -185,14 +185,14 @@ pcie_intc1: legacy-interrupt-controller {
 		};
 
 		mdio: mdio@24200f00 {
-			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x24200f00 0x100>;
 			status = "disabled";
 			clocks = <&clkcpgmac>;
 			clock-names = "fck";
-			bus_freq	= <2500000>;
+			bus_freq = <2500000>;
 		};
 		/include/ "keystone-k2e-netcp.dtsi"
 };
diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
index d0e6a9a43402..f6306933ff42 100644
--- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi
@@ -125,7 +125,7 @@ gbe: gbe@200000 {
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <5>;
+					link-interface = <5>;
 				};
 			};
 		};
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 37198294f4b2..380dd9d637ee 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -262,7 +262,7 @@ pmmc: system-controller@2921c00 {
 			 */
 			ti,system-reboot-controller;
 			mbox-names = "rx", "tx";
-			mboxes= <&msgmgr 5 2>,
+			mboxes = <&msgmgr 5 2>,
 				<&msgmgr 0 0>;
 			reg-names = "debug_messages";
 			reg = <0x02921c00 0x400>;
@@ -326,13 +326,13 @@ gpio1: gpio@260a000 {
 
 		dss: dss@02540000 {
 			compatible = "ti,k2g-dss";
-			reg =	<0x02540000 0x400>,
+			reg = <0x02540000 0x400>,
 				<0x02550000 0x1000>,
 				<0x02557000 0x1000>,
 				<0x0255a800 0x100>,
 				<0x0255ac00 0x100>;
 			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
-			clocks =	<&k2g_clks 0x2 0>,
+			clocks = <&k2g_clks 0x2 0>,
 					<&k2g_clks 0x2 1>;
 			clock-names = "fck", "vp1";
 			interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
@@ -348,7 +348,7 @@ dss: dss@02540000 {
 
 		edma0: edma@2700000 {
 			compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
-			reg =	<0x02700000 0x8000>;
+			reg = <0x02700000 0x8000>;
 			reg-names = "edma3_cc";
 			interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
 					<GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
@@ -367,19 +367,19 @@ edma0: edma@2700000 {
 
 		edma0_tptc0: tptc@2760000 {
 			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-			reg =	<0x02760000 0x400>;
+			reg = <0x02760000 0x400>;
 			power-domains = <&k2g_pds 0x3f>;
 		};
 
 		edma0_tptc1: tptc@2768000 {
 			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-			reg =	<0x02768000 0x400>;
+			reg = <0x02768000 0x400>;
 			power-domains = <&k2g_pds 0x3f>;
 		};
 
 		edma1: edma@2728000 {
 			compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
-			reg =	<0x02728000 0x8000>;
+			reg = <0x02728000 0x8000>;
 			reg-names = "edma3_cc";
 			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
 					<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
@@ -402,13 +402,13 @@ edma1: edma@2728000 {
 
 		edma1_tptc0: tptc@27b0000 {
 			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-			reg =	<0x027b0000 0x400>;
+			reg = <0x027b0000 0x400>;
 			power-domains = <&k2g_pds 0x4f>;
 		};
 
 		edma1_tptc1: tptc@27b8000 {
 			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
-			reg =	<0x027b8000 0x400>;
+			reg = <0x027b8000 0x400>;
 			power-domains = <&k2g_pds 0x4f>;
 		};
 
diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
index 022d93c366c7..8a421c65f920 100644
--- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x4000>;
-	linkram0	= <0x100000 0x8000>;
-	linkram1	= <0x0 0x10000>;
+	queue-range = <0 0x4000>;
+	linkram0 = <0x100000 0x8000>;
+	linkram1 = <0x0 0x10000>;
 
 	qmgrs {
 		#address-cells = <1>;
@@ -150,7 +150,7 @@ netcp: netcp@2000000 {
 	#size-cells = <1>;
 
 	/* NetCP address range */
-	ranges  = <0 0x2000000 0x100000>;
+	ranges = <0 0x2000000 0x100000>;
 
 	clocks = <&clkpa>, <&clkcpgmac>;
 	clock-names = "pa_clk", "ethss_clk";
@@ -207,11 +207,11 @@ gbe1: interface-1 {
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index 8a9447703310..da6d3934c2e8 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -282,14 +282,14 @@ dsp7: dsp@17800000 {
 		};
 
 		mdio: mdio@2090300 {
-			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x02090300 0x100>;
 			status = "disabled";
 			clocks = <&clkcpgmac>;
 			clock-names = "fck";
-			bus_freq	= <2500000>;
+			bus_freq = <2500000>;
 		};
 		/include/ "keystone-k2hk-netcp.dtsi"
 };
diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
index e96ca664abc2..5ec6680a533d 100644
--- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
@@ -12,9 +12,9 @@ qmss: qmss@2a40000 {
 	#size-cells = <1>;
 	clocks = <&chipclk13>;
 	ranges;
-	queue-range	= <0 0x2000>;
-	linkram0	= <0x100000 0x4000>;
-	linkram1	= <0x70000000 0x10000>; /* 1MB OSR mem */
+	queue-range = <0 0x2000>;
+	linkram0 = <0x100000 0x4000>;
+	linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
 
 	qmgrs {
 		#address-cells = <1>;
@@ -174,24 +174,24 @@ cpts_refclk_mux: cpts-refclk-mux {
 			interfaces {
 				gbe0: interface-0 {
 					slave-port = <0>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy0>;
+					link-interface = <1>;
+					phy-handle = <&ethphy0>;
 				};
 				gbe1: interface-1 {
 					slave-port = <1>;
-					link-interface	= <1>;
-					phy-handle	= <&ethphy1>;
+					link-interface = <1>;
+					phy-handle = <&ethphy1>;
 				};
 			};
 
 			secondary-slave-ports {
 				port-2 {
 					slave-port = <2>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 				port-3 {
 					slave-port = <3>;
-					link-interface	= <2>;
+					link-interface = <2>;
 				};
 			};
 		};
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index dff5fea72b2f..421a02bbc9d3 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -47,7 +47,7 @@ uart2: serial@2348400 {
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02348400 0x100>;
-			clocks	= <&clkuart2>;
+			clocks = <&clkuart2>;
 			interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -57,7 +57,7 @@ uart3:	serial@2348800 {
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02348800 0x100>;
-			clocks	= <&clkuart3>;
+			clocks = <&clkuart3>;
 			interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -388,14 +388,14 @@ dsp3: dsp@13800000 {
 		};
 
 		mdio: mdio@26200f00 {
-			compatible	= "ti,keystone_mdio", "ti,davinci_mdio";
+			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x26200f00 0x100>;
 			status = "disabled";
 			clocks = <&clkcpgmac>;
 			clock-names = "fck";
-			bus_freq	= <2500000>;
+			bus_freq = <2500000>;
 		};
 		/include/ "keystone-k2l-netcp.dtsi"
 };
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index fc9fdc857ae8..50789f9e2215 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -14,7 +14,7 @@ / {
 	interrupt-parent = <&gic>;
 
 	aliases {
-		serial0	= &uart0;
+		serial0 = &uart0;
 		spi0 = &spi0;
 		spi1 = &spi1;
 		spi2 = &spi2;
@@ -61,11 +61,11 @@ pmu {
 	};
 
 	psci {
-		compatible	= "arm,psci";
-		method		= "smc";
-		cpu_suspend	= <0x84000001>;
-		cpu_off		= <0x84000002>;
-		cpu_on		= <0x84000003>;
+		compatible = "arm,psci";
+		method = "smc";
+		cpu_suspend = <0x84000001>;
+		cpu_off = <0x84000002>;
+		cpu_on = <0x84000003>;
 	};
 
 	soc0: soc@0 {
@@ -119,7 +119,7 @@ uart0: serial@2530c00 {
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02530c00 0x100>;
-			clocks	= <&clkuart0>;
+			clocks = <&clkuart0>;
 			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -129,7 +129,7 @@ uart1:	serial@2531000 {
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			reg = <0x02531000 0x100>;
-			clocks	= <&clkuart1>;
+			clocks = <&clkuart1>;
 			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
 		};
 
@@ -301,7 +301,7 @@ pcie0: pcie@21800000 {
 			clock-names = "pcie";
 			#address-cells = <3>;
 			#size-cells = <2>;
-			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+			reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
 			ranges = <0x82000000 0 0x50000000 0x50000000
 				  0 0x10000000>;
 
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi
index 10b8249b8ab6..c6f8942f8d3d 100644
--- a/arch/arm/boot/dts/lpc18xx.dtsi
+++ b/arch/arm/boot/dts/lpc18xx.dtsi
@@ -183,7 +183,7 @@ mac: ethernet@40010000 {
 			compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
 			reg = <0x40010000 0x2000>;
 			interrupts = <5>;
-			interrupt-names	= "macirq";
+			interrupt-names = "macirq";
 			clocks = <&ccu1 CLK_CPU_ETHERNET>;
 			clock-names = "stmmaceth";
 			resets = <&rgu 22>;
diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts
index 66bcdaf4b6f9..ce8e26d7791f 100644
--- a/arch/arm/boot/dts/ls1021a-iot.dts
+++ b/arch/arm/boot/dts/ls1021a-iot.dts
@@ -142,7 +142,7 @@ pca9555: gpio@23 {
 	};
 
 	sgtl5000: audio-codec@2a {
-		#sound-dai-cells=<0x0>;
+		#sound-dai-cells = <0x0>;
 		compatible = "fsl,sgtl5000";
 		reg = <0x2a>;
 		VDDA-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 26eaba3fa96f..8e3860d5d916 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -214,14 +214,14 @@ aobus: aobus@c8100000 {
 			ranges = <0x0 0xc8100000 0x100000>;
 
 			ao_arc_rproc: remoteproc@1c {
-				compatible= "amlogic,meson-mx-ao-arc";
+				compatible = "amlogic,meson-mx-ao-arc";
 				reg = <0x1c 0x8>, <0x38 0x8>;
 				reg-names = "remap", "cpu";
 				status = "disabled";
 			};
 
 			ir_receiver: ir-receiver@480 {
-				compatible= "amlogic,meson6-ir";
+				compatible = "amlogic,meson6-ir";
 				reg = <0x480 0x20>;
 				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
 				status = "disabled";
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 9997a5d0333a..0f8bac8bac8b 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -430,7 +430,7 @@ mux {
 };
 
 &ao_arc_rproc {
-	compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
+	compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
 	amlogic,secbus2 = <&secbus2>;
 	sram = <&ao_arc_sram>;
 	resets = <&reset RESET_MEDIA_CPU>;
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 94f1c03decce..cf9c04a61ba3 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -384,7 +384,7 @@ mux {
 };
 
 &ao_arc_rproc {
-	compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
+	compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
 	amlogic,secbus2 = <&secbus2>;
 	sram = <&ao_arc_sram>;
 	resets = <&reset RESET_MEDIA_CPU>;
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index ef583cfd3baf..b8eba3ba153c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -427,9 +427,9 @@ audsys: clock-controller@11220000 {
 
 		afe: audio-controller {
 			compatible = "mediatek,mt2701-audio";
-			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-			interrupt-names	= "afe", "asys";
+			interrupt-names = "afe", "asys";
 			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 
 			clocks = <&infracfg CLK_INFRA_AUDIO>,
@@ -559,7 +559,7 @@ jpegdec: jpegdec@15004000 {
 		compatible = "mediatek,mt2701-jpgdec";
 		reg = <0 0x15004000 0 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
-		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
+		clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
 			  <&imgsys CLK_IMG_JPGDEC>;
 		clock-names = "jpgdec-smi",
 			      "jpgdec";
@@ -573,7 +573,7 @@ jpegenc: jpegenc@1500a000 {
 			     "mediatek,mtk-jpgenc";
 		reg = <0 0x1500a000 0 0x1000>;
 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
-		clocks =  <&imgsys CLK_IMG_VENC>;
+		clocks = <&imgsys CLK_IMG_VENC>;
 		clock-names = "jpgenc";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index f4848362b3be..25d31e40a553 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -241,7 +241,7 @@ infracfg: syscon@10001000 {
 	};
 
 	pericfg: syscon@10003000 {
-		compatible =  "mediatek,mt7623-pericfg",
+		compatible = "mediatek,mt7623-pericfg",
 			      "mediatek,mt2701-pericfg",
 			      "syscon";
 		reg = <0 0x10003000 0 0x1000>;
@@ -628,9 +628,9 @@ audsys: clock-controller@11220000 {
 		afe: audio-controller {
 			compatible = "mediatek,mt7623-audio",
 				     "mediatek,mt2701-audio";
-			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-			interrupt-names	= "afe", "asys";
+			interrupt-names = "afe", "asys";
 			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 
 			clocks = <&infracfg CLK_INFRA_AUDIO>,
diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
index 13c86936d1c8..e8b4b6d30d19 100644
--- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
+++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
@@ -45,13 +45,13 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&key_pins_a>;
 
-		factory {
+		button-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts
index 88d8f0b2f4c2..61f5da68d4b0 100644
--- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts
@@ -45,13 +45,13 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&key_pins_a>;
 
-		factory {
+		button-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 027c1b0c6a98..5008115d2494 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -91,13 +91,13 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&key_pins_a>;
 
-		factory {
+		button-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
index 1b9b9a8145a7..bf67a8e9be59 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
@@ -60,13 +60,13 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&key_pins_a>;
 
-		factory {
+		button-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
index eb536cbebd9b..84e14bee7235 100644
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -23,13 +23,13 @@ chosen {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		reset {
+		button-reset {
 			label = "factory";
 			linux,code = <KEY_RESTART>;
 			gpios = <&pio 60 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		button-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 58 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h
index c6da987b20cb..31297abcbc71 100644
--- a/arch/arm/boot/dts/mxs-pinfunc.h
+++ b/arch/arm/boot/dts/mxs-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Header providing constants for i.MX28 pinctrl bindings.
  *
  * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #ifndef __DT_BINDINGS_MXS_PINCTRL_H__
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 3696980a3da1..9633b50a9c6d 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -128,7 +128,7 @@ gmac0: eth@f0802000 {
 			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
 			ethernet = <0>;
-			clocks	= <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+			clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
 			clock-names = "stmmaceth", "clk_gmac";
 			pinctrl-names = "default";
 			pinctrl-0 = <&rg1_pins
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 13eee0fe5642..30eed40b89b5 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -51,7 +51,7 @@ gmac1: eth@f0804000 {
 			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
 			ethernet = <1>;
-			clocks	= <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
+			clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
 			clock-names = "stmmaceth", "clk_gmac";
 			pinctrl-names = "default";
 			pinctrl-0 = <&rg2_pins
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 5750ca1233cc..afabb36a8ac1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP2 SoC
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bb529a2a295d..821da51cb870 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP2420 SoC
  *
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include "omap2.dtsi"
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 23115ba61bc0..b9a9e6e45266 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP243x SoC
  *
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include "omap2.dtsi"
diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
index a9069cca5888..0da759f8e2c2 100644
--- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC CPU thermal
  *
  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 64b7e6fddd1b..825075ff0e34 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 8b8451399784..2eb73ae7ef3e 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP34xx/OMAP35xx SoC
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 22b33098b1a2..32ac7924a130 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP3 SoC
  *
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/bus/ti-sysc.h>
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index 03d054b2bf9a..4d7eeb133dad 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4/5 SoC CPU thermal
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 8466161197ae..238aceb799f8 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP443x SoC
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include "omap4.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 3d6db1db94e0..1b27a862ae81 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP4460 SoC
  *
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 #include "omap4.dtsi"
 
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
index 02e76338bfbc..e0d8e39a0014 100644
--- a/arch/arm/boot/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC CORE thermal
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
index bf8fa9372e57..1b4b7d9136c8 100644
--- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree Source for OMAP543x SoC GPU thermal
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <dt-bindings/thermal/thermal.h>
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
index 422958d13d42..03471d30bfd9 100644
--- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0043e0040153..f17e25ac98dd 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 /*
  * TODO: add Orion USB device port init when kernel.org support is added.
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
index 0ca6208a267d..d57859998350 100644
--- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
index f667012b26ca..819f9efb7058 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
 
 #include "orion5x.dtsi"
 
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
index d1ed71c60209..86b87fb26dc9 100644
--- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 #include "orion5x.dtsi"
 
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index ea081afa469d..4f4888ec9138 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
 
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index 487324f7c54e..fd78aa02a3c5 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 61e631b3fd8b..2d41f5c166ee 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -1,10 +1,5 @@
-/*
- * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
index 8a6721d436bd..147c99191dc2 100644
--- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
+++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi
@@ -189,31 +189,31 @@ max8660: regulator@34 {
 
 		regulators {
 			regulator-v3 {
-				regulator-compatible= "V3(DCDC)";
+				regulator-compatible = "V3(DCDC)";
 				regulator-min-microvolt = <725000>;
 				regulator-max-microvolt = <1800000>;
 			};
 
 			regulator-v4 {
-				regulator-compatible= "V4(DCDC)";
+				regulator-compatible = "V4(DCDC)";
 				regulator-min-microvolt = <725000>;
 				regulator-max-microvolt = <1800000>;
 			};
 
 			regulator-v5 {
-				regulator-compatible= "V5(LDO)";
+				regulator-compatible = "V5(LDO)";
 				regulator-min-microvolt = <1700000>;
 				regulator-max-microvolt = <2000000>;
 			};
 
 			reg_vcc_sdio: regulator-v6 {
-				regulator-compatible= "V6(LDO)";
+				regulator-compatible = "V6(LDO)";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
 			};
 
 			regulator-v7 {
-				regulator-compatible= "V7(LDO)";
+				regulator-compatible = "V7(LDO)";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
 			};
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2638b380be20..eb6b1a1ff117 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -341,7 +341,6 @@ hdmi-tx@4a00000 {
 			status = "okay";
 
 			core-vdda-supply = <&pm8921_hdmi_switch>;
-			hdmi-mux-supply = <&ext_3p3v>;
 
 			hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
 
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 34c0ba7fa358..028d52b5d075 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -796,15 +796,15 @@ ref_muxoff: adc-channel@f {
 		};
 
 		qfprom: qfprom@700000 {
-			compatible	= "qcom,qfprom";
-			reg		= <0x00700000 0x1000>;
-			#address-cells	= <1>;
-			#size-cells	= <1>;
+			compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
+			reg = <0x00700000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 			ranges;
-			tsens_calib: calib {
+			tsens_calib: calib@404 {
 				reg = <0x404 0x10>;
 			};
-			tsens_backup: backup_calib {
+			tsens_backup: backup_calib@414 {
 				reg = <0x414 0x10>;
 			};
 		};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index da50a1a0197f..cb01faa23eb7 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -240,10 +240,10 @@ apcs: syscon@f9011000 {
 		};
 
 		qfprom: qfprom@fc4bc000 {
+			compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
+			reg = <0xfc4bc000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "qcom,qfprom";
-			reg = <0xfc4bc000 0x1000>;
 			tsens_calib: calib@d0 {
 				reg = <0xd0 0x18>;
 			};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
index faeaa6bf0def..44a9597d8bfd 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -93,7 +93,7 @@ flash@0 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0>;
-				compatible = "n25q128a11";
+				compatible = "micron,n25q128a11", "jedec,spi-nor";
 				spi-max-frequency = <24000000>;
 			};
 		};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
index d596dd1180ae..c7a6e77da272 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -56,7 +56,7 @@ flash@0 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0>;
-				compatible = "n25q128a11";
+				compatible = "micron,n25q128a11", "jedec,spi-nor";
 				spi-max-frequency = <24000000>;
 			};
 		};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 808ea1862283..b3c0d140e6a0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -723,7 +723,7 @@ qcom,ssbi@500000 {
 		};
 
 		qfprom: qfprom@700000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
 			reg = <0x00700000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 814ad0b46232..df49be66d0b8 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1118,10 +1118,10 @@ restart@fc4ab000 {
 		};
 
 		qfprom: qfprom@fc4bc000 {
+			compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
+			reg = <0xfc4bc000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "qcom,qfprom";
-			reg = <0xfc4bc000 0x1000>;
 			tsens_calib: calib@d0 {
 				reg = <0xd0 0x18>;
 			};
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 9c0d9686fe01..69a5a44b8a2f 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -71,10 +71,10 @@ lbsc {
 	leds {
 		compatible = "gpio-leds";
 
-		red {
+		led-red {
 			gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
 		};
-		green {
+		led-green {
 			gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 3f8f3ce87e12..ca39e1d681c1 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -23,6 +23,10 @@ aliases {
 	};
 };
 
+&rtc0 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 390aa33cd55a..962b4d1291db 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -48,7 +48,7 @@ gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		power {
+		key-power {
 			gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
@@ -56,7 +56,7 @@ power {
 			wakeup-source;
 			debounce-interval = <100>;
 		};
-		volume-down {
+		key-volume-down {
 			gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
 			linux,code = <KEY_VOLUMEDOWN>;
 			label = "GPIO Key Vol-";
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 667d57a4ff45..cfa318a506eb 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -160,6 +160,24 @@ &mmc1 {
 	status = "okay";
 };
 
+&nfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		label = "rk-nand";
+		nand-bus-width = <8>;
+		nand-ecc-mode = "hw";
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <40>;
+		nand-is-boot-medium;
+		rockchip,boot-blks = <8>;
+		rockchip,boot-ecc-strength = <24>;
+	};
+};
+
 &pinctrl {
 	usb-host {
 		host_drv: host-drv {
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index 12b2e59aebc4..dbbc5170094e 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -32,7 +32,7 @@ ir: ir-receiver {
 	keys: gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
index 35b7a5798eee..9312be362a7a 100644
--- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts
+++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
@@ -37,7 +37,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key &usb_int>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
@@ -46,7 +46,7 @@ power {
 			wakeup-source;
 		};
 
-		wake_on_usb: wake-on-usb {
+		wake_on_usb: key-wake-on-usb {
 			label = "Wake-on-USB";
 			gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index fc478ac4e781..0a1ae689b162 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -29,7 +29,7 @@ gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 36c0945f43b2..a9ed3cd2c2da 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -24,7 +24,7 @@ gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 797476e8bef1..5c3d08e3eea3 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -107,7 +107,7 @@ vdd_log: vdd-log-regulator {
 		regulator-boot-on;
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 		pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index c4ca73b40d4a..399d6b9c5fd4 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -118,7 +118,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 9a4a9749c405..a5a0826341e6 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -27,7 +27,7 @@ button-recovery {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 7fb582302b32..052afe5543e2 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -49,7 +49,7 @@ ir: ir-receiver {
 	keys: gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 1e33859de484..1a5156951492 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -20,14 +20,14 @@ user_buttons: user-buttons {
 		pinctrl-names = "default";
 		pinctrl-0 = <&user_button_pins>;
 
-		button@0 {
+		button-0 {
 			label = "home";
 			linux,code = <KEY_HOME>;
 			gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
 			wakeup-source;
 		};
 
-		button@1 {
+		button-1 {
 			label = "menu";
 			linux,code = <KEY_MENU>;
 			gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 8c7376d64bc4..fd90f3b8fc32 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -30,7 +30,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index 55467bc30fa6..633e5a032463 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -31,7 +31,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index c4d1d142d8c6..80e0f07c8e87 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -28,7 +28,7 @@ button-recovery {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index 9c1e38c54eae..09618bb7d872 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -26,14 +26,12 @@ ext_gmac: external-gmac-clock {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		button@0 {
+		button {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
index a10d25ac8f7b..f9dde0eef527 100644
--- a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
@@ -13,10 +13,10 @@ bluetooth {
 			    <&bt_dev_wake>;
 
 		compatible = "brcm,bcm43540-bt";
-		host-wakeup-gpios	= <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
-		shutdown-gpios		= <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
-		device-wakeup-gpios	= <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-		max-speed		= <3000000>;
-		brcm,bt-pcm-int-params	= [01 02 00 01 01];
+		host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		max-speed = <3000000>;
+		brcm,bt-pcm-int-params = [01 02 00 01 01];
 	};
 };
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index 05112c25176d..700bb548d6b2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -32,7 +32,7 @@ lid_switch: lid-switch {
 		pinctrl-names = "default";
 		pinctrl-0 = <&ap_lid_int_l>;
 
-		lid {
+		switch-lid {
 			label = "Lid";
 			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
 			wakeup-source;
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index 82fc6fba9999..dcdcc55c4098 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -21,14 +21,14 @@ volume_buttons: volume-buttons {
 		pinctrl-names = "default";
 		pinctrl-0 = <&volum_down_l &volum_up_l>;
 
-		volum_down {
+		key-volum-down {
 			label = "Volum_down";
 			gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
 			debounce-interval = <100>;
 		};
 
-		volum_up {
+		key-volum-up {
 			label = "Volum_up";
 			gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index 4e9fdb0f722d..e2a4e6232eb5 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -45,7 +45,7 @@ &edp {
 &lid_switch {
 	pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
 
-	power {
+	key-power {
 		gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
 	};
 };
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 54a6838d73f5..e406c8c7c7e5 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -29,7 +29,7 @@ power_button: power-button {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key_l>;
 
-		power {
+		key-power {
 			label = "Power";
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts
index 0c99a5934ebf..2d9994379eb2 100644
--- a/arch/arm/boot/dts/rv1108-elgin-r1.dts
+++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts
@@ -83,7 +83,7 @@ rk805: pmic@18 {
 
 		regulators {
 			vdd_core: DCDC_REG1 {
-				regulator-name= "vdd_core";
+				regulator-name = "vdd_core";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <1500000>;
 				regulator-always-on;
@@ -95,7 +95,7 @@ regulator-state-mem {
 			};
 
 			vdd_buck2: DCDC_REG2 {
-				regulator-name= "vdd_buck2";
+				regulator-name = "vdd_buck2";
 				regulator-min-microvolt = <2200000>;
 				regulator-max-microvolt = <2200000>;
 				regulator-always-on;
@@ -106,7 +106,7 @@ regulator-state-mem {
 			};
 
 			vcc_ddr: DCDC_REG3 {
-				regulator-name= "vcc_ddr";
+				regulator-name = "vcc_ddr";
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-state-mem {
@@ -115,7 +115,7 @@ regulator-state-mem {
 			};
 
 			vcc_io: DCDC_REG4 {
-				regulator-name= "vcc_io";
+				regulator-name = "vcc_io";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-always-on;
@@ -127,7 +127,7 @@ regulator-state-mem {
 			};
 
 			vdd_10: LDO_REG1 {
-				regulator-name= "vdd_10";
+				regulator-name = "vdd_10";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
@@ -138,7 +138,7 @@ regulator-state-mem {
 			};
 
 			vcc_18: LDO_REG2 {
-				regulator-name= "vcc_18";
+				regulator-name = "vcc_18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
@@ -149,7 +149,7 @@ regulator-state-mem {
 			};
 
 			vdd10_pmu: LDO_REG3 {
-				regulator-name= "vdd10_pmu";
+				regulator-name = "vdd10_pmu";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 46cad7cb94bf..ef150f4ee99d 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -96,7 +96,7 @@ rk805: pmic@18 {
 
 		regulators {
 			vdd_core: DCDC_REG1 {
-				regulator-name= "vdd_core";
+				regulator-name = "vdd_core";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <1500000>;
 				regulator-always-on;
@@ -108,7 +108,7 @@ regulator-state-mem {
 			};
 
 			vdd_cam: DCDC_REG2 {
-				regulator-name= "vdd_cam";
+				regulator-name = "vdd_cam";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <2000000>;
 				regulator-state-mem {
@@ -117,7 +117,7 @@ regulator-state-mem {
 			};
 
 			vcc_ddr: DCDC_REG3 {
-				regulator-name= "vcc_ddr";
+				regulator-name = "vcc_ddr";
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-state-mem {
@@ -126,7 +126,7 @@ regulator-state-mem {
 			};
 
 			vcc_io: DCDC_REG4 {
-				regulator-name= "vcc_io";
+				regulator-name = "vcc_io";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-always-on;
@@ -138,7 +138,7 @@ regulator-state-mem {
 			};
 
 			vdd_10: LDO_REG1 {
-				regulator-name= "vdd_10";
+				regulator-name = "vdd_10";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
@@ -149,7 +149,7 @@ regulator-state-mem {
 			};
 
 			vcc_18: LDO_REG2 {
-				regulator-name= "vcc_18";
+				regulator-name = "vcc_18";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
@@ -160,7 +160,7 @@ regulator-state-mem {
 			};
 
 			vdd10_pmu: LDO_REG3 {
-				regulator-name= "vdd10_pmu";
+				regulator-name = "vdd10_pmu";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index c158a7ea86ec..abf3006f0a84 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -748,7 +748,7 @@ sfc_clk: sfc-clk {
 
 		gmac {
 			rmii_pins: rmii-pins {
-				rockchip,pins =	<1 RK_PC5 2 &pcfg_pull_none>,
+				rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
 						<1 RK_PC3 2 &pcfg_pull_none>,
 						<1 RK_PC4 2 &pcfg_pull_none>,
 						<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h
new file mode 100644
index 000000000000..76b6171ae149
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2410-pinctrl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung S3C2410 DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__
+
+#define S3C2410_PIN_FUNC_INPUT		0
+#define S3C2410_PIN_FUNC_OUTPUT		1
+#define S3C2410_PIN_FUNC_2		2
+#define S3C2410_PIN_FUNC_3		3
+
+#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
index 20a7d72827c2..3268366bd8bc 100644
--- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
@@ -5,7 +5,7 @@
  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "s3c2410-pinctrl.h"
 
 &pinctrl_0 {
 	/*
@@ -82,91 +82,91 @@ gpm: gpm-gpio-bank {
 
 	uart0_data: uart0-data-pins {
 		samsung,pins = "gph-0", "gph-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart0_fctl: uart0-fctl-pins {
 		samsung,pins = "gph-8", "gph-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart1_data: uart1-data-pins {
 		samsung,pins = "gph-2", "gph-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart1_fctl: uart1-fctl-pins {
 		samsung,pins = "gph-10", "gph-11";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart2_data: uart2-data-pins {
 		samsung,pins = "gph-4", "gph-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart2_fctl: uart2-fctl-pins {
 		samsung,pins = "gph-6", "gph-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	uart3_data: uart3-data-pins {
 		samsung,pins = "gph-6", "gph-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	extuart_clk: extuart-clk-pins {
 		samsung,pins = "gph-12";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	i2c0_bus: i2c0-bus-pins {
 		samsung,pins = "gpe-14", "gpe-15";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	spi0_bus: spi0-bus-pins {
 		samsung,pins = "gpe-11", "gpe-12", "gpe-13";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd0_clk: sd0-clk-pins {
 		samsung,pins = "gpe-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd0_cmd: sd0-cmd-pins {
 		samsung,pins = "gpe-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd0_bus1: sd0-bus1-pins {
 		samsung,pins = "gpe-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd0_bus4: sd0-bus4-pins {
 		samsung,pins = "gpe-8", "gpe-9", "gpe-10";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd1_cmd: sd1-cmd-pins {
 		samsung,pins = "gpl-8";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd1_clk: sd1-clk-pins {
 		samsung,pins = "gpl-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd1_bus1: sd1-bus1-pins {
 		samsung,pins = "gpl-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 
 	sd1_bus4: sd1-bus4-pins {
 		samsung,pins = "gpl-1", "gpl-2", "gpl-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
 	};
 };
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
index 0a3186d57cb5..f53959b7d031 100644
--- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * listed as device tree nodes in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "s3c64xx-pinctrl.h"
 
 &pinctrl0 {
 	/*
@@ -133,219 +133,219 @@ gpq: gpq-gpio-bank {
 
 	uart0_data: uart0-data-pins {
 		samsung,pins = "gpa-0", "gpa-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	uart0_fctl: uart0-fctl-pins {
 		samsung,pins = "gpa-2", "gpa-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	uart1_data: uart1-data-pins {
 		samsung,pins = "gpa-4", "gpa-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	uart1_fctl: uart1-fctl-pins {
 		samsung,pins = "gpa-6", "gpa-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	uart2_data: uart2-data-pins {
 		samsung,pins = "gpb-0", "gpb-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	uart3_data: uart3-data-pins {
 		samsung,pins = "gpb-2", "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	ext_dma_0: ext-dma-0-pins {
 		samsung,pins = "gpb-0", "gpb-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	ext_dma_1: ext-dma-1-pins {
 		samsung,pins = "gpb-2", "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	irda_data_0: irda-data-0-pins {
 		samsung,pins = "gpb-0", "gpb-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	irda_data_1: irda-data-1-pins {
 		samsung,pins = "gpb-2", "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	irda_sdbw: irda-sdbw-pins {
 		samsung,pins = "gpb-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2c0_bus: i2c0-bus-pins {
 		samsung,pins = "gpb-5", "gpb-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	i2c1_bus: i2c1-bus-pins {
 		/* S3C6410-only */
 		samsung,pins = "gpb-2", "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_6>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_6>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	spi0_bus: spi0-bus-pins {
 		samsung,pins = "gpc-0", "gpc-1", "gpc-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	spi0_cs: spi0-cs-pins {
 		samsung,pins = "gpc-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	spi1_bus: spi1-bus-pins {
 		samsung,pins = "gpc-4", "gpc-5", "gpc-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	spi1_cs: spi1-cs-pins {
 		samsung,pins = "gpc-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd0_cmd: sd0-cmd-pins {
 		samsung,pins = "gpg-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd0_clk: sd0-clk-pins {
 		samsung,pins = "gpg-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd0_bus1: sd0-bus1-pins {
 		samsung,pins = "gpg-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd0_bus4: sd0-bus4-pins {
 		samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd0_cd: sd0-cd-pins {
 		samsung,pins = "gpg-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	sd1_cmd: sd1-cmd-pins {
 		samsung,pins = "gph-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd1_clk: sd1-clk-pins {
 		samsung,pins = "gph-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd1_bus1: sd1-bus1-pins {
 		samsung,pins = "gph-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd1_bus4: sd1-bus4-pins {
 		samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd1_bus8: sd1-bus8-pins {
 		samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
 				"gph-6", "gph-7", "gph-8", "gph-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd1_cd: sd1-cd-pins {
 		samsung,pins = "gpg-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
 	};
 
 	sd2_cmd: sd2-cmd-pins {
 		samsung,pins = "gpc-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd2_clk: sd2-clk-pins {
 		samsung,pins = "gpc-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd2_bus1: sd2-bus1-pins {
 		samsung,pins = "gph-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	sd2_bus4: sd2-bus4-pins {
 		samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2s0_bus: i2s0-bus-pins {
 		samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2s0_cdclk: i2s0-cdclk-pins {
 		samsung,pins = "gpd-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2s1_bus: i2s1-bus-pins {
 		samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2s1_cdclk: i2s1-cdclk-pins {
 		samsung,pins = "gpe-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
@@ -353,50 +353,50 @@ i2s2_bus: i2s2-bus-pins {
 		/* S3C6410-only */
 		samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
 				"gph-8", "gph-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	i2s2_cdclk: i2s2-cdclk-pins {
 		/* S3C6410-only */
 		samsung,pins = "gph-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pcm0_bus: pcm0-bus-pins {
 		samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pcm0_extclk: pcm0-extclk-pins {
 		samsung,pins = "gpd-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pcm1_bus: pcm1-bus-pins {
 		samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pcm1_extclk: pcm1-extclk-pins {
 		samsung,pins = "gpe-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	ac97_bus_0: ac97-bus-0-pins {
 		samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	ac97_bus_1: ac97-bus-1-pins {
 		samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
@@ -404,242 +404,242 @@ cam_port: cam-port-pins {
 		samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
 				"gpf-5", "gpf-6", "gpf-7", "gpf-8",
 				"gpf-9", "gpf-10", "gpf-11", "gpf-12";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	cam_rst: cam-rst-pins {
 		samsung,pins = "gpf-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	cam_field: cam-field-pins {
 		/* S3C6410-only */
 		samsung,pins = "gpb-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pwm_extclk: pwm-extclk-pins {
 		samsung,pins = "gpf-13";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pwm0_out: pwm0-out-pins {
 		samsung,pins = "gpf-14";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	pwm1_out: pwm1-out-pins {
 		samsung,pins = "gpf-15";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	clkout0: clkout-0-pins {
 		samsung,pins = "gpf-14";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col0_0: keypad-col0-0-pins {
 		samsung,pins = "gph-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col1_0: keypad-col1-0-pins {
 		samsung,pins = "gph-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col2_0: keypad-col2-0-pins {
 		samsung,pins = "gph-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col3_0: keypad-col3-0-pins {
 		samsung,pins = "gph-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col4_0: keypad-col4-0-pins {
 		samsung,pins = "gph-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col5_0: keypad-col5-0-pins {
 		samsung,pins = "gph-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col6_0: keypad-col6-0-pins {
 		samsung,pins = "gph-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col7_0: keypad-col7-0-pins {
 		samsung,pins = "gph-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col0_1: keypad-col0-1-pins {
 		samsung,pins = "gpl-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col1_1: keypad-col1-1-pins {
 		samsung,pins = "gpl-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col2_1: keypad-col2-1-pins {
 		samsung,pins = "gpl-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col3_1: keypad-col3-1-pins {
 		samsung,pins = "gpl-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col4_1: keypad-col4-1-pins {
 		samsung,pins = "gpl-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col5_1: keypad-col5-1-pins {
 		samsung,pins = "gpl-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col6_1: keypad-col6-1-pins {
 		samsung,pins = "gpl-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_col7_1: keypad-col7-1-pins {
 		samsung,pins = "gpl-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row0_0: keypad-row0-0-pins {
 		samsung,pins = "gpk-8";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row1_0: keypad-row1-0-pins {
 		samsung,pins = "gpk-9";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row2_0: keypad-row2-0-pins {
 		samsung,pins = "gpk-10";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row3_0: keypad-row3-0-pins {
 		samsung,pins = "gpk-11";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row4_0: keypad-row4-0-pins {
 		samsung,pins = "gpk-12";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row5_0: keypad-row5-0-pins {
 		samsung,pins = "gpk-13";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row6_0: keypad-row6-0-pins {
 		samsung,pins = "gpk-14";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row7_0: keypad-row7-0-pins {
 		samsung,pins = "gpk-15";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row0_1: keypad-row0-1-pins {
 		samsung,pins = "gpn-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row1_1: keypad-row1-1-pins {
 		samsung,pins = "gpn-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row2_1: keypad-row2-1-pins {
 		samsung,pins = "gpn-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row3_1: keypad-row3-1-pins {
 		samsung,pins = "gpn-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row4_1: keypad-row4-1-pins {
 		samsung,pins = "gpn-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row5_1: keypad-row5-1-pins {
 		samsung,pins = "gpn-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row6_1: keypad-row6-1-pins {
 		samsung,pins = "gpn-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	keypad_row7_1: keypad-row7-1-pins {
 		samsung,pins = "gpn-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	lcd_ctrl: lcd-ctrl-pins {
 		samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
@@ -648,7 +648,7 @@ lcd_data16: lcd-data-width16-pins {
 				"gpi-7", "gpi-10", "gpi-11", "gpi-12",
 				"gpi-13", "gpi-14", "gpi-15", "gpj-3",
 				"gpj-4", "gpj-5", "gpj-6", "gpj-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
@@ -658,7 +658,7 @@ lcd_data18: lcd-data-width18-pins {
 				"gpi-12", "gpi-13", "gpi-14", "gpi-15",
 				"gpj-2", "gpj-3", "gpj-4", "gpj-5",
 				"gpj-6", "gpj-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
@@ -669,14 +669,14 @@ lcd_data24: lcd-data-width24-pins {
 				"gpi-12", "gpi-13", "gpi-14", "gpi-15",
 				"gpj-0", "gpj-1", "gpj-2", "gpj-3",
 				"gpj-4", "gpj-5", "gpj-6", "gpj-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 
 	hsi_bus: hsi-bus-pins {
 		samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
 				"gpk-4", "gpk-5", "gpk-6", "gpk-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
 		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
 	};
 };
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/s3c64xx-pinctrl.h
new file mode 100644
index 000000000000..645c591db357
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung S3C64xx DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__
+
+#define S3C64XX_PIN_PULL_NONE		0
+#define S3C64XX_PIN_PULL_DOWN		1
+#define S3C64XX_PIN_PULL_UP		2
+
+#define S3C64XX_PIN_FUNC_INPUT		0
+#define S3C64XX_PIN_FUNC_OUTPUT		1
+#define S3C64XX_PIN_FUNC_2		2
+#define S3C64XX_PIN_FUNC_3		3
+#define S3C64XX_PIN_FUNC_4		4
+#define S3C64XX_PIN_FUNC_5		5
+#define S3C64XX_PIN_FUNC_6		6
+#define S3C64XX_PIN_FUNC_EINT		7
+
+#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
index bc0b7354b6c0..0f5c6cd0f3a1 100644
--- a/arch/arm/boot/dts/s5pv210-aquila.dts
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -392,7 +392,7 @@ timing0: timing {
 &pinctrl0 {
 	t_flash_detect: t-flash-detect-pins {
 		samsung,pins = "gph3-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 };
diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi
index daa1067055c8..5541df4df628 100644
--- a/arch/arm/boot/dts/s5pv210-aries.dtsi
+++ b/arch/arm/boot/dts/s5pv210-aries.dtsi
@@ -646,183 +646,183 @@ &mfc {
 &pinctrl0 {
 	bt_reset: bt-reset-pins {
 		samsung,pins = "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	wlan_bt_en: wlan-bt-en-pins {
 		samsung,pins = "gpb-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 		samsung,pin-val = <1>;
 	};
 
 	codec_ldo: codec-ldo-pins {
 		samsung,pins = "gpf3-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	prox_i2c_pins: gp2a-i2c-pins {
 		samsung,pins = "gpg0-2", "gpg2-2";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	wlan_gpio_rst: wlan-gpio-rst-pins {
 		samsung,pins = "gpg1-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	bt_wake: bt-wake-pins {
 		samsung,pins = "gpg3-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	gp2a_irq: gp2a-irq-pins {
 		samsung,pins = "gph0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pmic_dvs_pins: pmic-dvs-pins {
 		samsung,pins = "gph0-3", "gph0-4", "gph0-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 		samsung,pin-val = <0>;
 	};
 
 	pmic_irq: pmic-irq-pins {
 		samsung,pins = "gph0-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	wifi_host_wake: wifi-host-wake-pins {
 		samsung,pins = "gph2-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	bt_host_wake: bt-host-wake-pins {
 		samsung,pins = "gph2-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	musb_irq: musq-irq-pins {
 		samsung,pins = "gph2-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	tf_detect: tf-detect-pins {
 		samsung,pins = "gph3-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	wifi_wake: wifi-wake-pins {
 		samsung,pins = "gph3-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	magnetometer_i2c_pins: yas529-i2c-pins-pins {
 		samsung,pins = "gpj0-0", "gpj0-1";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	ts_irq: ts-irq-pins {
 		samsung,pins = "gpj0-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	vibrator_ena: vibrator-ena-pins {
 		samsung,pins = "gpj1-1";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	gp2a_power: gp2a-power-pins {
 		samsung,pins = "gpj1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	touchkey_i2c_pins: touchkey-i2c-pins {
 		samsung,pins = "gpj3-0", "gpj3-1";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	touchkey_vdd_ena: touchkey-vdd-ena-pins {
 		samsung,pins = "gpj3-2";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	musb_i2c_pins: musb-i2c-pins {
 		samsung,pins = "gpj3-4", "gpj3-5";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	accel_i2c_pins: accel-i2c-pins {
 		samsung,pins = "gpj3-6", "gpj3-7";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pmic_i2c_pins: pmic-i2c-pins-pins {
 		samsung,pins = "gpj4-0", "gpj4-3";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	touchkey_irq: touchkey-irq-pins {
 		samsung,pins = "gpj4-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	lcd_spi_pins: spi-lcd-pins {
 		samsung,pins = "mp01-1", "mp04-1", "mp04-3";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	fg_i2c_pins: fg-i2c-pins {
 		samsung,pins = "mp05-0", "mp05-1";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	sound_i2c_pins: sound-i2c-pins {
 		samsung,pins = "mp05-2", "mp05-3";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	panel_rst: panel-rst-pins {
 		samsung,pins = "mp05-5";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
index dfb2ee65e4a8..eaa7c4f0e257 100644
--- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts
+++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
@@ -17,20 +17,20 @@ chosen {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "power";
 			gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			wakeup-source;
 		};
 
-		vol-down {
+		key-vol-down {
 			label = "volume_down";
 			gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 
-		vol-up {
+		key-vol-up {
 			label = "volume_up";
 			gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
@@ -128,33 +128,33 @@ &pinctrl0 {
 
 	headset_det: headset-det-pins {
 		samsung,pins = "gph0-6", "gph3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	fg_irq: fg-irq-pins {
 		samsung,pins = "gph3-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	headset_micbias_ena: headset-micbias-ena-pins {
 		samsung,pins = "gpj2-5";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	earpath_sel: earpath-sel-pins {
 		samsung,pins = "gpj2-6";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	main_micbias_ena: main-micbias-ena-pins {
 		samsung,pins = "gpj4-2";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	/* Based on vendor kernel v2.6.35.7 */
diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts
index a78caaa1f3c5..cdd3653d487f 100644
--- a/arch/arm/boot/dts/s5pv210-galaxys.dts
+++ b/arch/arm/boot/dts/s5pv210-galaxys.dts
@@ -24,26 +24,26 @@ nand_pwrseq: nand-pwrseq {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "power";
 			gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			wakeup-source;
 		};
 
-		vol-down {
+		key-vol-down {
 			label = "volume_down";
 			gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 
-		vol-up {
+		key-vol-up {
 			label = "volume_up";
 			gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
 		};
 
-		home {
+		key-home {
 			label = "home";
 			gpios = <&gph3 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
@@ -152,47 +152,47 @@ &pinctrl0 {
 
 	fm_i2c_pins: fm-i2c-pins-pins {
 		samsung,pins = "gpd1-2", "gpd1-3";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	headset_det: headset-det-pins {
 		samsung,pins = "gph0-6", "gph3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
 	};
 
 	fm_irq: fm-irq-pins {
 		samsung,pins = "gpj2-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	fm_rst: fm-rst-pins {
 		samsung,pins = "gpj2-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	earpath_sel: earpath-sel-pins {
 		samsung,pins = "gpj2-6";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	massmemory_en: massmemory-en-pins {
 		samsung,pins = "gpj2-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	micbias_reg_ena: micbias-reg-ena-pins {
 		samsung,pins = "gpj4-2";
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	/* Based on CyanogenMod 3.0.101 kernel */
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
index ae34e7e57892..6d6daef9fb7a 100644
--- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -16,13 +16,13 @@
  * nodes can be added to this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "s5pv210-pinctrl.h"
 
 #define PIN_SLP(_pin, _mode, _pull)					\
 	_pin {								\
 		samsung,pins = #_pin;					\
-		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>;	\
-		samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>;	\
+		samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>;	\
+		samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>;	\
 	}
 
 &pinctrl0 {
@@ -280,559 +280,559 @@ gph3: gph3-gpio-bank {
 
 	uart0_data: uart0-data-pins {
 		samsung,pins = "gpa0-0", "gpa0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart0_fctl: uart0-fctl-pins {
 		samsung,pins = "gpa0-2", "gpa0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart1_data: uart1-data-pins {
 		samsung,pins = "gpa0-4", "gpa0-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart1_fctl: uart1-fctl-pins {
 		samsung,pins = "gpa0-6", "gpa0-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart2_data: uart2-data-pins {
 		samsung,pins = "gpa1-0", "gpa1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart2_fctl: uart2-fctl-pins {
 		samsung,pins = "gpa1-2", "gpa1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart3_data: uart3-data-pins {
 		samsung,pins = "gpa1-2", "gpa1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	uart_audio: uart-audio-pins {
 		samsung,pins = "gpa1-2", "gpa1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	spi0_bus: spi0-bus-pins {
 		samsung,pins = "gpb-0", "gpb-2", "gpb-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	spi1_bus: spi1-bus-pins {
 		samsung,pins = "gpb-4", "gpb-6", "gpb-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2s0_bus: i2s0-bus-pins {
 		samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
 				"gpi-4", "gpi-5", "gpi-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2s1_bus: i2s1-bus-pins {
 		samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
 				"gpc0-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2s2_bus: i2s2-bus-pins {
 		samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
 				"gpc1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pcm1_bus: pcm1-bus-pins {
 		samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
 				"gpc0-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	ac97_bus: ac97-bus-pins {
 		samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
 				"gpc0-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2s2_bus: i2s2-bus-pins {
 		samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
 				"gpc1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pcm2_bus: pcm2-bus-pins {
 		samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
 				"gpc1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	spdif_bus: spdif-bus-pins {
 		samsung,pins = "gpc1-0", "gpc1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_4>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	spi2_bus: spi2-bus-pins {
 		samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_5>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2c0_bus: i2c0-bus-pins {
 		samsung,pins = "gpd1-0", "gpd1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2c1_bus: i2c1-bus-pins {
 		samsung,pins = "gpd1-2", "gpd1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	i2c2_bus: i2c2-bus-pins {
 		samsung,pins = "gpd1-4", "gpd1-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pwm0_out: pwm0-out-pins {
 		samsung,pins = "gpd0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pwm1_out: pwm1-out-pins {
 		samsung,pins = "gpd0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pwm2_out: pwm2-out-pins {
 		samsung,pins = "gpd0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	pwm3_out: pwm3-out-pins {
 		samsung,pins = "gpd0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row0: keypad-row-0-pins {
 		samsung,pins = "gph3-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row1: keypad-row-1-pins {
 		samsung,pins = "gph3-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row2: keypad-row-2-pins {
 		samsung,pins = "gph3-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row3: keypad-row-3-pins {
 		samsung,pins = "gph3-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row4: keypad-row-4-pins {
 		samsung,pins = "gph3-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row5: keypad-row-5-pins {
 		samsung,pins = "gph3-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row6: keypad-row-6-pins {
 		samsung,pins = "gph3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_row7: keypad-row-7-pins {
 		samsung,pins = "gph3-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col0: keypad-col-0-pins {
 		samsung,pins = "gph2-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col1: keypad-col-1-pins {
 		samsung,pins = "gph2-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col2: keypad-col-2-pins {
 		samsung,pins = "gph2-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col3: keypad-col-3-pins {
 		samsung,pins = "gph2-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col4: keypad-col-4-pins {
 		samsung,pins = "gph2-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col5: keypad-col-5-pins {
 		samsung,pins = "gph2-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col6: keypad-col-6-pins {
 		samsung,pins = "gph2-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	keypad_col7: keypad-col-7-pins {
 		samsung,pins = "gph2-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	sd0_clk: sd0-clk-pins {
 		samsung,pins = "gpg0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd0_cmd: sd0-cmd-pins {
 		samsung,pins = "gpg0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd0_cd: sd0-cd-pins {
 		samsung,pins = "gpg0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd0_bus1: sd0-bus-width1-pins {
 		samsung,pins = "gpg0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd0_bus4: sd0-bus-width4-pins {
 		samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd0_bus8: sd0-bus-width8-pins {
 		samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd1_clk: sd1-clk-pins {
 		samsung,pins = "gpg1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd1_cmd: sd1-cmd-pins {
 		samsung,pins = "gpg1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd1_cd: sd1-cd-pins {
 		samsung,pins = "gpg1-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd1_bus1: sd1-bus-width1-pins {
 		samsung,pins = "gpg1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd1_bus4: sd1-bus-width4-pins {
 		samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_clk: sd2-clk-pins {
 		samsung,pins = "gpg2-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_cmd: sd2-cmd-pins {
 		samsung,pins = "gpg2-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_cd: sd2-cd-pins {
 		samsung,pins = "gpg2-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_bus1: sd2-bus-width1-pins {
 		samsung,pins = "gpg2-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_bus4: sd2-bus-width4-pins {
 		samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd2_bus8: sd2-bus-width8-pins {
 		samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd3_clk: sd3-clk-pins {
 		samsung,pins = "gpg3-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd3_cmd: sd3-cmd-pins {
 		samsung,pins = "gpg3-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd3_cd: sd3-cd-pins {
 		samsung,pins = "gpg3-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd3_bus1: sd3-bus-width1-pins {
 		samsung,pins = "gpg3-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	sd3_bus4: sd3-bus-width4-pins {
 		samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_UP>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	eint0: ext-int0-pins {
 		samsung,pins = "gph0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	eint8: ext-int8-pins {
 		samsung,pins = "gph1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	eint15: ext-int15-pins {
 		samsung,pins = "gph1-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	eint16: ext-int16-pins {
 		samsung,pins = "gph2-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	eint31: ext-int31-pins {
 		samsung,pins = "gph3-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_F>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	cam_port_a_io: cam-port-a-io-pins {
 		samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
 				"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
 				"gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	cam_port_a_clk_active: cam-port-a-clk-active-pins {
 		samsung,pins = "gpe1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	cam_port_a_clk_idle: cam-port-a-clk-idle-pins {
 		samsung,pins = "gpe1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	cam_port_b_io: cam-port-b-io-pins {
 		samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
 				"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
 				"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	cam_port_b_clk_active: cam-port-b-clk-active-pins {
 		samsung,pins = "gpj1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV4>;
 	};
 
 	cam_port_b_clk_idle: cam-port-b-clk-idle-pins {
 		samsung,pins = "gpj1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	lcd_ctrl: lcd-ctrl-pins {
 		samsung,pins = "gpd0-0", "gpd0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_3>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	lcd_sync: lcd-sync-pins {
 		samsung,pins = "gpf0-0", "gpf0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	lcd_clk: lcd-clk-pins {
 		samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 
 	lcd_data24: lcd-data-width24-pins {
@@ -842,8 +842,8 @@ lcd_data24: lcd-data-width24-pins {
 				"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
 				"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
 				"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <S5PV210_PIN_FUNC_2>;
+		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
+		samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
 	};
 };
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/s5pv210-pinctrl.h
new file mode 100644
index 000000000000..29bdf376d8f1
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung S5PV210 DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__
+#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__
+
+#define S5PV210_PIN_PULL_NONE		0
+#define S5PV210_PIN_PULL_DOWN		1
+#define S5PV210_PIN_PULL_UP		2
+
+/* Pin function in power down mode */
+#define S5PV210_PIN_PDN_OUT0		0
+#define S5PV210_PIN_PDN_OUT1		1
+#define S5PV210_PIN_PDN_INPUT		2
+#define S5PV210_PIN_PDN_PREV		3
+
+#define S5PV210_PIN_DRV_LV1		0
+#define S5PV210_PIN_DRV_LV2		2
+#define S5PV210_PIN_DRV_LV3		1
+#define S5PV210_PIN_DRV_LV4		3
+
+#define S5PV210_PIN_FUNC_INPUT		0
+#define S5PV210_PIN_FUNC_OUTPUT		1
+#define S5PV210_PIN_FUNC_2		2
+#define S5PV210_PIN_FUNC_3		3
+#define S5PV210_PIN_FUNC_4		4
+#define S5PV210_PIN_FUNC_5		5
+#define S5PV210_PIN_FUNC_6		6
+#define S5PV210_PIN_FUNC_EINT		0xf
+#define S5PV210_PIN_FUNC_F		S5PV210_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index c328b67bea0c..a0e21022dbc5 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -464,7 +464,7 @@ pwm0: pwm@f8034000 {
 				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
 				#pwm-cells = <3>;
-				status="disabled";
+				status = "disabled";
 			};
 
 			hlcdc: hlcdc@f8038000 {
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
index a61a078ea042..69381819e07b 100644
--- a/arch/arm/boot/dts/sd5203.dts
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -15,7 +15,7 @@ / {
 	#size-cells = <1>;
 
 	chosen {
-		bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+		bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
 	};
 
 	aliases {
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index ddd1cf4d0554..05408df38203 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -170,7 +170,7 @@ sdhci@b3000000 {
 
 		smi: flash@ea000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@e6000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index 3a51a41eb5e4..7700f2afc128 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -168,7 +168,7 @@ sdhci@b3000000 {
 
 		smi: flash@ea000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@e6000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 13e1bdb3ddbf..818886e11713 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -88,7 +88,7 @@ pinmux: pinmux@e0700000 {
 		};
 
 		pwm: pwm@e0180000 {
-			compatible ="st,spear13xx-pwm";
+			compatible = "st,spear13xx-pwm";
 			reg = <0xe0180000 0x1000>;
 			#pwm-cells = <2>;
 			status = "disabled";
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index 2beb30ca2cba..303ef29fb805 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -80,7 +80,7 @@ sdhci@70000000 {
 
 		smi: flash@fc000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@f8000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index 1c41e4a40334..ea0b53036f7b 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -94,7 +94,7 @@ gmac: eth@e0800000 {
 
 		smi: flash@fc000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@f8000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index c322407a0ade..3c026d021c92 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -95,7 +95,7 @@ sdhci@70000000 {
 
 		smi: flash@fc000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@f8000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
index b587e4ec11e5..34503ac9c51c 100644
--- a/arch/arm/boot/dts/spear320-hmi.dts
+++ b/arch/arm/boot/dts/spear320-hmi.dts
@@ -167,7 +167,7 @@ sdhci@70000000 {
 
 		smi: flash@fc000000 {
 			status = "okay";
-			clock-rate=<50000000>;
+			clock-rate = <50000000>;
 
 			flash@f8000000 {
 				#address-cells = <1>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 47ac4474ed96..b12474446a48 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -78,7 +78,7 @@ spi2: spi@a6000000 {
 		};
 
 		pwm: pwm@a8000000 {
-			compatible ="st,spear-pwm";
+			compatible = "st,spear-pwm";
 			reg = <0xa8000000 0x1000>;
 			#pwm-cells = <2>;
 			status = "disabled";
diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi
index 35137c6e52ee..dd30d08ccb9b 100644
--- a/arch/arm/boot/dts/ste-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-ab8500.dtsi
@@ -195,7 +195,7 @@ ab8500_charger {
 							  "CH_WD_EXP",
 							  "VBUS_CH_DROP_END";
 					monitored-battery = <&battery>;
-					vddadc-supply	= <&ab8500_ldo_tvout_reg>;
+					vddadc-supply = <&ab8500_ldo_tvout_reg>;
 					io-channels = <&gpadc 0x03>,
 						      <&gpadc 0x0a>,
 						      <&gpadc 0x09>,
@@ -207,8 +207,8 @@ ab8500_charger {
 				};
 
 				ab8500_chargalg {
-					compatible	= "stericsson,ab8500-chargalg";
-					monitored-battery	= <&battery>;
+					compatible = "stericsson,ab8500-chargalg";
+					monitored-battery = <&battery>;
 				};
 
 				ab8500_usb: phy {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 8f504edefd3f..e66fa59c2de6 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -353,11 +353,11 @@ lcd_hrefv60_mode: lcd_hrefv60 {
 					 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 					 */
 					hrefv60_cfg1 {
-						pins ="GPIO65_F1";
+						pins = "GPIO65_F1";
 						ste,config = <&gpio_out_hi>;
 					};
 					hrefv60_cfg2 {
-						pins ="GPIO66_G3";
+						pins = "GPIO66_G3";
 						ste,config = <&gpio_out_lo>;
 					};
 				};
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 1713f7878117..33cf54cb46cc 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -137,8 +137,8 @@ picophyreset: picophyreset-controller {
 	};
 
 	irq-syscfg {
-		compatible    = "st,stih407-irq-syscfg";
-		st,syscfg     = <&syscfg_core>;
+		compatible = "st,stih407-irq-syscfg";
+		st,syscfg = <&syscfg_core>;
 		st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 				<ST_IRQ_SYSCFG_PMU_1>;
 		st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
@@ -157,8 +157,8 @@ usb2_picophy0: phy1 {
 	miphy28lp_phy: miphy28lp {
 		compatible = "st,miphy28lp-phy";
 		st,syscfg = <&syscfg_core>;
-		#address-cells	= <1>;
-		#size-cells	= <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 		ranges;
 
 		phy_port0: port@9b22000 {
@@ -208,26 +208,26 @@ phy_port2: port@8f95000 {
 	};
 
 	st231_gp0: st231-gp0 {
-		compatible	= "st,st231-rproc";
-		memory-region	= <&gp0_reserved>;
-		resets		= <&softreset STIH407_ST231_GP0_SOFTRESET>;
-		reset-names	= "sw_reset";
-		clocks		= <&clk_s_c0_flexgen CLK_ST231_GP_0>;
-		clock-frequency	= <600000000>;
-		st,syscfg	= <&syscfg_core 0x22c>;
+		compatible = "st,st231-rproc";
+		memory-region = <&gp0_reserved>;
+		resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
+		reset-names = "sw_reset";
+		clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+		clock-frequency = <600000000>;
+		st,syscfg = <&syscfg_core 0x22c>;
 		#mbox-cells = <1>;
 		mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
 		mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
 	};
 
 	st231_delta: st231-delta {
-		compatible	= "st,st231-rproc";
-		memory-region	= <&delta_reserved>;
-		resets		= <&softreset STIH407_ST231_DMU_SOFTRESET>;
-		reset-names	= "sw_reset";
-		clocks		= <&clk_s_c0_flexgen CLK_ST231_DMU>;
-		clock-frequency	= <600000000>;
-		st,syscfg	= <&syscfg_core 0x224>;
+		compatible = "st,st231-rproc";
+		memory-region = <&delta_reserved>;
+		resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
+		reset-names = "sw_reset";
+		clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
+		clock-frequency = <600000000>;
+		st,syscfg = <&syscfg_core 0x224>;
 		#mbox-cells = <1>;
 		mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
 		mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
@@ -710,78 +710,78 @@ sata1: sata@9b28000 {
 
 
 		st_dwc3: dwc3@8f94000 {
-			compatible	= "st,stih407-dwc3";
-			reg		= <0x08f94000 0x1000>, <0x110 0x4>;
-			reg-names	= "reg-glue", "syscfg-reg";
-			st,syscfg	= <&syscfg_core>;
-			resets		= <&powerdown STIH407_USB3_POWERDOWN>,
-					  <&softreset STIH407_MIPHY2_SOFTRESET>;
-			reset-names	= "powerdown", "softreset";
-			#address-cells	= <1>;
-			#size-cells	= <1>;
-			pinctrl-names	= "default";
-			pinctrl-0	= <&pinctrl_usb3>;
+			compatible = "st,stih407-dwc3";
+			reg = <0x08f94000 0x1000>, <0x110 0x4>;
+			reg-names = "reg-glue", "syscfg-reg";
+			st,syscfg = <&syscfg_core>;
+			resets = <&powerdown STIH407_USB3_POWERDOWN>,
+				 <&softreset STIH407_MIPHY2_SOFTRESET>;
+			reset-names = "powerdown", "softreset";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb3>;
 			ranges;
 
 			status = "disabled";
 
 			dwc3: dwc3@9900000 {
-				compatible	= "snps,dwc3";
-				reg		= <0x09900000 0x100000>;
-				interrupts	= <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-				dr_mode		= "host";
-				phy-names	= "usb2-phy", "usb3-phy";
-				phys		= <&usb2_picophy0>,
-						  <&phy_port2 PHY_TYPE_USB3>;
+				compatible = "snps,dwc3";
+				reg = <0x09900000 0x100000>;
+				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				phy-names = "usb2-phy", "usb3-phy";
+				phys = <&usb2_picophy0>,
+				       <&phy_port2 PHY_TYPE_USB3>;
 				snps,dis_u3_susphy_quirk;
 			};
 		};
 
 		/* COMMS PWM Module */
 		pwm0: pwm@9810000 {
-			compatible	= "st,sti-pwm";
-			#pwm-cells	= <2>;
-			reg		= <0x9810000 0x68>;
-			interrupts      = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names	= "default";
-			pinctrl-0	= <&pinctrl_pwm0_chan0_default>;
-			clock-names	= "pwm";
-			clocks		= <&clk_sysin>;
+			compatible = "st,sti-pwm";
+			#pwm-cells = <2>;
+			reg = <0x9810000 0x68>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
+			clock-names = "pwm";
+			clocks = <&clk_sysin>;
 			st,pwm-num-chan = <1>;
 
-			status		= "disabled";
+			status = "disabled";
 		};
 
 		/* SBC PWM Module */
 		pwm1: pwm@9510000 {
-			compatible	= "st,sti-pwm";
-			#pwm-cells	= <2>;
-			reg		= <0x9510000 0x68>;
-			interrupts      = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names	= "default";
-			pinctrl-0	= <&pinctrl_pwm1_chan0_default
-					&pinctrl_pwm1_chan1_default
-					&pinctrl_pwm1_chan2_default
-					&pinctrl_pwm1_chan3_default>;
-			clock-names	= "pwm";
-			clocks		= <&clk_sysin>;
+			compatible = "st,sti-pwm";
+			#pwm-cells = <2>;
+			reg = <0x9510000 0x68>;
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pwm1_chan0_default
+				     &pinctrl_pwm1_chan1_default
+				     &pinctrl_pwm1_chan2_default
+				     &pinctrl_pwm1_chan3_default>;
+			clock-names = "pwm";
+			clocks = <&clk_sysin>;
 			st,pwm-num-chan = <4>;
 
-			status		= "disabled";
+			status = "disabled";
 		};
 
 		rng10: rng@8a89000 {
-			compatible      = "st,rng";
-			reg		= <0x08a89000 0x1000>;
-			clocks          = <&clk_sysin>;
-			status		= "okay";
+			compatible = "st,rng";
+			reg = <0x08a89000 0x1000>;
+			clocks = <&clk_sysin>;
+			status = "okay";
 		};
 
 		rng11: rng@8a8a000 {
-			compatible      = "st,rng";
-			reg		= <0x08a8a000 0x1000>;
-			clocks          = <&clk_sysin>;
-			status		= "okay";
+			compatible = "st,rng";
+			reg = <0x08a8a000 0x1000>;
+			clocks = <&clk_sysin>;
+			status = "okay";
 		};
 
 		ethernet0: dwmac@9630000 {
@@ -812,36 +812,36 @@ ethernet0: dwmac@9630000 {
 		};
 
 		mailbox0: mailbox@8f00000  {
-			compatible	= "st,stih407-mailbox";
-			reg		= <0x8f00000 0x1000>;
-			interrupts	= <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells	= <2>;
-			mbox-name	= "a9";
-			status		= "okay";
+			compatible = "st,stih407-mailbox";
+			reg = <0x8f00000 0x1000>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <2>;
+			mbox-name = "a9";
+			status = "okay";
 		};
 
 		mailbox1: mailbox@8f01000 {
-			compatible	= "st,stih407-mailbox";
-			reg		= <0x8f01000 0x1000>;
-			#mbox-cells	= <2>;
-			mbox-name	= "st231_gp_1";
-			status		= "okay";
+			compatible = "st,stih407-mailbox";
+			reg = <0x8f01000 0x1000>;
+			#mbox-cells = <2>;
+			mbox-name = "st231_gp_1";
+			status = "okay";
 		};
 
 		mailbox2: mailbox@8f02000 {
-			compatible	= "st,stih407-mailbox";
-			reg		= <0x8f02000 0x1000>;
-			#mbox-cells	= <2>;
-			mbox-name	= "st231_gp_0";
-			status		= "okay";
+			compatible = "st,stih407-mailbox";
+			reg = <0x8f02000 0x1000>;
+			#mbox-cells = <2>;
+			mbox-name = "st231_gp_0";
+			status = "okay";
 		};
 
 		mailbox3: mailbox@8f03000 {
-			compatible	= "st,stih407-mailbox";
-			reg		= <0x8f03000 0x1000>;
-			#mbox-cells	= <2>;
-			mbox-name	= "st231_audio_video";
-			status		= "okay";
+			compatible = "st,stih407-mailbox";
+			reg = <0x8f03000 0x1000>;
+			#mbox-cells = <2>;
+			mbox-name = "st231_audio_video";
+			status = "okay";
 		};
 
 		/* fdma audio */
@@ -913,7 +913,7 @@ sti_uni_player0: sti-uni-player@8d80000 {
 			dmas = <&fdma0 2 0 1>;
 			dma-names = "tx";
 
-			status		= "disabled";
+			status = "disabled";
 		};
 
 		sti_uni_player1: sti-uni-player@8d81000 {
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 9e212b0af89d..aca43d2bdaad 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -13,7 +13,7 @@ sti-display-subsystem@0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			reg = <0 0>;
-			assigned-clocks	= <&clk_s_d2_quadfs 0>,
+			assigned-clocks = <&clk_s_d2_quadfs 0>,
 					  <&clk_s_d2_quadfs 1>,
 					  <&clk_s_c0_pll1 0>,
 					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
@@ -106,7 +106,7 @@ sti_hdmi: sti-hdmi@8d04000 {
 				reg-names = "hdmi-reg";
 				#sound-dai-cells = <0>;
 				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names	= "irq";
+				interrupt-names = "irq";
 				clock-names = "pix",
 					      "tmds",
 					      "phy",
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index ce2f62cf129b..a39dd5f7bcae 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -105,7 +105,7 @@ sti-display-subsystem@0 {
 			#size-cells = <1>;
 
 			reg = <0 0>;
-			assigned-clocks	= <&clk_s_d2_quadfs 0>,
+			assigned-clocks = <&clk_s_d2_quadfs 0>,
 					  <&clk_s_d2_quadfs 1>,
 					  <&clk_s_c0_pll1 0>,
 					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
@@ -198,7 +198,7 @@ sti_hdmi: sti-hdmi@8d04000 {
 				reg-names = "hdmi-reg";
 				#sound-dai-cells = <0>;
 				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names	= "irq";
+				interrupt-names = "irq";
 				clock-names = "pix",
 					      "tmds",
 					      "phy",
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 4c72dedcd1be..2aa94605d3d4 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -175,11 +175,11 @@ demux@8a20000 {
 
 			/* tsin0 is TSA on NIMA */
 			tsin0: port {
-				tsin-num	= <0>;
+				tsin-num = <0>;
 				serial-not-parallel;
-				i2c-bus		= <&ssc2>;
-				reset-gpios	= <&pio15 4 GPIO_ACTIVE_HIGH>;
-				dvb-card	= <STV0367_TDA18212_NIMA_1>;
+				i2c-bus = <&ssc2>;
+				reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
+				dvb-card = <STV0367_TDA18212_NIMA_1>;
 			};
 		};
 
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 0d98aca01736..3de0e9dbe030 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -251,10 +251,10 @@ ltdc_out_rgb: endpoint {
 
 &mac {
 	status = "okay";
-	pinctrl-0	= <&ethernet_mii>;
-	pinctrl-names	= "default";
-	phy-mode	= "mii";
-	phy-handle	= <&phy1>;
+	pinctrl-0 = <&ethernet_mii>;
+	pinctrl-names = "default";
+	phy-mode = "mii";
+	phy-handle = <&phy1>;
 	mdio0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 91dde07a38ba..2059593da21d 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -375,7 +375,7 @@ sdmmc1: mmc@52007000 {
 			arm,primecell-periphid = <0x10153180>;
 			reg = <0x52007000 0x1000>;
 			interrupts = <49>;
-			interrupt-names	= "cmd_irq";
+			interrupt-names = "cmd_irq";
 			clocks = <&rcc SDMMC1_CK>;
 			clock-names = "apb_pclk";
 			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
@@ -389,7 +389,7 @@ sdmmc2: mmc@48022400 {
 			arm,primecell-periphid = <0x10153180>;
 			reg = <0x48022400 0x400>;
 			interrupts = <124>;
-			interrupt-names	= "cmd_irq";
+			interrupt-names = "cmd_irq";
 			clocks = <&rcc SDMMC2_CK>;
 			clock-names = "apb_pclk";
 			resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 59e01ce10318..2b452883a708 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -77,10 +77,10 @@ &clk_hse {
 
 &mac {
 	status = "disabled";
-	pinctrl-0	= <&ethernet_rmii>;
-	pinctrl-names	= "default";
-	phy-mode	= "rmii";
-	phy-handle	= <&phy0>;
+	pinctrl-0 = <&ethernet_rmii>;
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	phy-handle = <&phy0>;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 38cc7faf6884..5c5d8059bdc7 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -115,10 +115,10 @@ &rtc {
 
 &mac {
 	status = "disabled";
-	pinctrl-0	= <&ethernet_rmii>;
-	pinctrl-names	= "default";
-	phy-mode	= "rmii";
-	phy-handle	= <&phy0>;
+	pinctrl-0 = <&ethernet_rmii>;
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	phy-handle = <&phy0>;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
index 9bb73bb61901..f3e70d3b65ac 100644
--- a/arch/arm/boot/dts/stm32h750i-art-pi.dts
+++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
@@ -126,10 +126,10 @@ &dma2 {
 
 &mac {
 	status = "disabled";
-	pinctrl-0	= <&ethernet_rmii>;
-	pinctrl-names	= "default";
-	phy-mode	= "rmii";
-	phy-handle	= <&phy0>;
+	pinctrl-0 = <&ethernet_rmii>;
+	pinctrl-names = "default";
+	phy-mode = "rmii";
+	phy-handle = <&phy0>;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index f9ebc47e6421..1dd647b9a791 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -4,6 +4,8 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp13-clks.h>
+#include <dt-bindings/reset/stm32mp13-resets.h>
 
 / {
 	#address-cells = <1>;
@@ -27,59 +29,30 @@ arm-pmu {
 		interrupt-parent = <&intc>;
 	};
 
-	clocks {
-		clk_axi: clk-axi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <266500000>;
+	firmware {
+		optee {
+			method = "smc";
+			compatible = "linaro,optee-tz";
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		clk_hse: clk-hse {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-		};
-
-		clk_hsi: clk-hsi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <64000000>;
-		};
-
-		clk_lsi: clk-lsi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32000>;
-		};
-
-		clk_pclk3: clk-pclk3 {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <104438965>;
-		};
-
-		clk_pclk4: clk-pclk4 {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <133250000>;
-		};
-
-		clk_pll4_p: clk-pll4_p {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
+		scmi: scmi {
+			compatible = "linaro,scmi-optee";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			linaro,optee-channel-id = <0>;
+			shmem = <&scmi_shm>;
 
-		clk_pll4_r: clk-pll4_r {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <99000000>;
-		};
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
 
-		clk_rtc_k: clk-rtc-k {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
+			scmi_reset: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
 		};
 	};
 
@@ -113,11 +86,25 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
+		scmi_sram: sram@2ffff000 {
+			compatible = "mmio-sram";
+			reg = <0x2ffff000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x2ffff000 0x1000>;
+
+			scmi_shm: scmi-sram@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0 0x80>;
+			};
+		};
+
 		uart4: serial@40010000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x40010000 0x400>;
 			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_hsi>;
+			clocks = <&rcc UART4_K>;
+			resets = <&rcc UART4_R>;
 			status = "disabled";
 		};
 
@@ -132,7 +119,8 @@ dma1: dma-controller@48000000 {
 				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_pclk4>;
+			clocks = <&rcc DMA1>;
+			resets = <&rcc DMA1_R>;
 			#dma-cells = <4>;
 			st,mem2mem;
 			dma-requests = <8>;
@@ -149,7 +137,8 @@ dma2: dma-controller@48001000 {
 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_pclk4>;
+			clocks = <&rcc DMA2>;
+			resets = <&rcc DMA2_R>;
 			#dma-cells = <4>;
 			st,mem2mem;
 			dma-requests = <8>;
@@ -158,13 +147,27 @@ dma2: dma-controller@48001000 {
 		dmamux1: dma-router@48002000 {
 			compatible = "st,stm32h7-dmamux";
 			reg = <0x48002000 0x40>;
-			clocks = <&clk_pclk4>;
+			clocks = <&rcc DMAMUX1>;
+			resets = <&rcc DMAMUX1_R>;
 			#dma-cells = <3>;
 			dma-masters = <&dma1 &dma2>;
 			dma-requests = <128>;
 			dma-channels = <16>;
 		};
 
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp13-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			clock-names = "hse", "hsi", "csi", "lse", "lsi";
+			clocks = <&scmi_clk CK_SCMI_HSE>,
+				 <&scmi_clk CK_SCMI_HSI>,
+				 <&scmi_clk CK_SCMI_CSI>,
+				 <&scmi_clk CK_SCMI_LSE>,
+				 <&scmi_clk CK_SCMI_LSI>;
+		};
+
 		exti: interrupt-controller@5000d000 {
 			compatible = "st,stm32mp13-exti", "syscon";
 			interrupt-controller;
@@ -175,14 +178,14 @@ exti: interrupt-controller@5000d000 {
 		syscfg: syscon@50020000 {
 			compatible = "st,stm32mp157-syscfg", "syscon";
 			reg = <0x50020000 0x400>;
-			clocks = <&clk_pclk3>;
+			clocks = <&rcc SYSCFG>;
 		};
 
 		mdma: dma-controller@58000000 {
 			compatible = "st,stm32h7-mdma";
 			reg = <0x58000000 0x1000>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_pclk4>;
+			clocks = <&rcc MDMA>;
 			#dma-cells = <5>;
 			dma-channels = <32>;
 			dma-requests = <48>;
@@ -194,8 +197,9 @@ sdmmc1: mmc@58005000 {
 			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
-			clocks = <&clk_pll4_p>;
+			clocks = <&rcc SDMMC1_K>;
 			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC1_R>;
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			max-frequency = <130000000>;
@@ -208,8 +212,9 @@ sdmmc2: mmc@58007000 {
 			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "cmd_irq";
-			clocks = <&clk_pll4_p>;
+			clocks = <&rcc SDMMC2_K>;
 			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC2_R>;
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			max-frequency = <130000000>;
@@ -219,7 +224,7 @@ sdmmc2: mmc@58007000 {
 		iwdg2: watchdog@5a002000 {
 			compatible = "st,stm32mp1-iwdg";
 			reg = <0x5a002000 0x400>;
-			clocks = <&clk_pclk4>, <&clk_lsi>;
+			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
 			clock-names = "pclk", "lsi";
 			status = "disabled";
 		};
@@ -228,7 +233,8 @@ rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
 			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_pclk4>, <&clk_rtc_k>;
+			clocks = <&scmi_clk CK_SCMI_RTCAPB>,
+				 <&scmi_clk CK_SCMI_RTC>;
 			clock-names = "pclk", "rtc_ck";
 			status = "disabled";
 		};
@@ -269,7 +275,7 @@ gpioa: gpio@50002000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x0 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOA>;
 				st,bank-name = "GPIOA";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 0 16>;
@@ -281,7 +287,7 @@ gpiob: gpio@50003000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x1000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOB>;
 				st,bank-name = "GPIOB";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 16 16>;
@@ -293,7 +299,7 @@ gpioc: gpio@50004000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x2000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOC>;
 				st,bank-name = "GPIOC";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 32 16>;
@@ -305,7 +311,7 @@ gpiod: gpio@50005000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x3000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOD>;
 				st,bank-name = "GPIOD";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 48 16>;
@@ -317,7 +323,7 @@ gpioe: gpio@50006000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x4000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOE>;
 				st,bank-name = "GPIOE";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 64 16>;
@@ -329,7 +335,7 @@ gpiof: gpio@50007000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x5000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOF>;
 				st,bank-name = "GPIOF";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 80 16>;
@@ -341,7 +347,7 @@ gpiog: gpio@50008000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x6000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOG>;
 				st,bank-name = "GPIOG";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 96 16>;
@@ -353,7 +359,7 @@ gpioh: gpio@50009000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x7000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOH>;
 				st,bank-name = "GPIOH";
 				ngpios = <15>;
 				gpio-ranges = <&pinctrl 0 112 15>;
@@ -365,7 +371,7 @@ gpioi: gpio@5000a000 {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				reg = <0x8000 0x400>;
-				clocks = <&clk_pclk4>;
+				clocks = <&rcc GPIOI>;
 				st,bank-name = "GPIOI";
 				ngpios = <8>;
 				gpio-ranges = <&pinctrl 0 128 8>;
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index 0fb1386257cf..531c263c9f46 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -15,7 +15,7 @@ m_can1: can@4400e000 {
 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "int0", "int1";
-			clocks = <&clk_hse>, <&clk_pll4_r>;
+			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
 			clock-names = "hclk", "cclk";
 			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 			status = "disabled";
@@ -28,7 +28,7 @@ m_can2: can@4400f000 {
 			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "int0", "int1";
-			clocks = <&clk_hse>, <&clk_pll4_r>;
+			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
 			clock-names = "hclk", "cclk";
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts
index 09d6226d598f..e6b8ffd332c7 100644
--- a/arch/arm/boot/dts/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/stm32mp135f-dk.dts
@@ -26,6 +26,17 @@ memory@c0000000 {
 		reg = <0xc0000000 0x20000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		optee@dd000000 {
+			reg = <0xdd000000 0x3000000>;
+			no-map;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index fa6889e30591..4d00e7592882 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -10,7 +10,8 @@ cryp: crypto@54002000 {
 			compatible = "st,stm32mp1-cryp";
 			reg = <0x54002000 0x400>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_axi>;
+			clocks = <&rcc CRYP1>;
+			resets = <&rcc CRYP1_R>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index fa6889e30591..4d00e7592882 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -10,7 +10,8 @@ cryp: crypto@54002000 {
 			compatible = "st,stm32mp1-cryp";
 			reg = <0x54002000 0x400>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_axi>;
+			clocks = <&rcc CRYP1>;
+			resets = <&rcc CRYP1_R>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
new file mode 100644
index 000000000000..e90cf3acd0b3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		scmi: scmi {
+			compatible = "linaro,scmi-optee";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			linaro,optee-channel-id = <0>;
+			shmem = <&scmi_shm>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_reset: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	soc {
+		scmi_sram: sram@2ffff000 {
+			compatible = "mmio-sram";
+			reg = <0x2ffff000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x2ffff000 0x1000>;
+
+			scmi_shm: scmi-sram@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0 0x80>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 1b2fd3426a81..edc0a1641c7b 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -115,33 +115,6 @@ booster: regulator-booster {
 		status = "disabled";
 	};
 
-	firmware {
-		optee: optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-			status = "disabled";
-		};
-
-		scmi: scmi {
-			compatible = "linaro,scmi-optee";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			linaro,optee-channel-id = <0>;
-			shmem = <&scmi_shm>;
-			status = "disabled";
-
-			scmi_clk: protocol@14 {
-				reg = <0x14>;
-				#clock-cells = <1>;
-			};
-
-			scmi_reset: protocol@16 {
-				reg = <0x16>;
-				#reset-cells = <1>;
-			};
-		};
-	};
-
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -149,20 +122,6 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
-		scmi_sram: sram@2ffff000 {
-			compatible = "mmio-sram";
-			reg = <0x2ffff000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x2ffff000 0x1000>;
-
-			scmi_shm: scmi-sram@0 {
-				compatible = "arm,scmi-shmem";
-				reg = <0 0x80>;
-				status = "disabled";
-			};
-		};
-
 		timers2: timer@40000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1158,10 +1117,9 @@ ipcc: mailbox@4c001000 {
 			reg = <0x4c001000 0x400>;
 			st,proc-id = <0>;
 			interrupts-extended =
-				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-				<&exti 61 1>;
-			interrupt-names = "rx", "tx", "wakeup";
+				<&exti 61 1>,
+				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "rx", "tx";
 			clocks = <&rcc IPCC>;
 			wakeup-source;
 			status = "disabled";
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
index e3d3f3f30c7d..36371d6ed660 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157a-dk1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
@@ -54,10 +55,6 @@ &mlahb {
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -76,11 +73,3 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
index 45dcd299aa9e..03226a596904 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-dk2.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
@@ -63,10 +64,6 @@ &mlahb {
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -85,11 +82,3 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
index 458e0ca3cded..c1a79272c068 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-ed1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
@@ -59,10 +60,6 @@ &mlahb {
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -81,11 +78,3 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
index df9c113edb4b..7842384ddbe4 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-ev1.dts"
+#include "stm32mp15-scmi.dtsi"
 
 / {
 	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
@@ -68,10 +69,6 @@ &mlahb {
 	resets = <&scmi_reset RST_SCMI_MCU>;
 };
 
-&optee {
-	status = "okay";
-};
-
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
@@ -90,11 +87,3 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
-
-&scmi {
-	status = "okay";
-};
-
-&scmi_shm {
-	status = "okay";
-};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
index 75172314d7af..9937b28548c2 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
@@ -18,6 +18,11 @@ vdd_io: regulator-buck-io {
 	};
 };
 
+&vdd {
+	regulator-min-microvolt = <2900000>;
+	regulator-max-microvolt = <2900000>;
+};
+
 &pwr_regulators {
 	vdd-supply = <&vdd_io>;
 };
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
index 6336c3ca0f0e..134a798ad3f2 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -119,8 +119,8 @@ vdd_ddr: buck2 {
 
 			vdd: buck3 {
 				regulator-name = "vdd";
-				regulator-min-microvolt = <2900000>;
-				regulator-max-microvolt = <2900000>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 				regulator-always-on;
 				regulator-initial-mode = <0>;
 				regulator-over-current-protection;
diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
index 6706d8311a66..935b7084b5a2 100644
--- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
@@ -50,12 +50,6 @@ retram: retram@38000000 {
 			no-map;
 		};
 	};
-
-	reg_sip_eeprom: regulator_eeprom {
-		compatible = "regulator-fixed";
-		regulator-name = "sip_eeprom";
-		regulator-always-on;
-	};
 };
 
 &i2c4 {
@@ -78,6 +72,7 @@ regulators {
 			compatible = "st,stpmic1-regulators";
 
 			ldo1-supply = <&v3v3>;
+			ldo3-supply = <&vdd_ddr>;
 			ldo6-supply = <&v3v3>;
 			pwr_sw1-supply = <&bst_out>;
 
@@ -203,7 +198,7 @@ pmic_watchdog: watchdog {
 
 	sip_eeprom: eeprom@50 {
 		compatible = "atmel,24c32";
-		vcc-supply = <&reg_sip_eeprom>;
+		vcc-supply = <&vdd>;
 		reg = <0x50>;
 	};
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 0a562b2cc5bc..62e7aa587f89 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -63,7 +63,7 @@ gpio-keys {
 		compatible = "gpio-keys-polled";
 		poll-interval = <20>;
 
-		left-joystick-left {
+		event-left-joystick-left {
 			label = "Left Joystick Left";
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
@@ -71,7 +71,7 @@ left-joystick-left {
 			gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
 		};
 
-		left-joystick-right {
+		event-left-joystick-right {
 			label = "Left Joystick Right";
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
@@ -79,7 +79,7 @@ left-joystick-right {
 			gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
 		};
 
-		left-joystick-up {
+		event-left-joystick-up {
 			label = "Left Joystick Up";
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
@@ -87,7 +87,7 @@ left-joystick-up {
 			gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
 		};
 
-		left-joystick-down {
+		event-left-joystick-down {
 			label = "Left Joystick Down";
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
@@ -95,7 +95,7 @@ left-joystick-down {
 			gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
 		};
 
-		right-joystick-left {
+		event-right-joystick-left {
 			label = "Right Joystick Left";
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
@@ -103,7 +103,7 @@ right-joystick-left {
 			gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
 		};
 
-		right-joystick-right {
+		event-right-joystick-right {
 			label = "Right Joystick Right";
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
@@ -111,7 +111,7 @@ right-joystick-right {
 			gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
 		};
 
-		right-joystick-up {
+		event-right-joystick-up {
 			label = "Right Joystick Up";
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
@@ -119,7 +119,7 @@ right-joystick-up {
 			gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
 		};
 
-		right-joystick-down {
+		event-right-joystick-down {
 			label = "Right Joystick Down";
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
@@ -127,7 +127,7 @@ right-joystick-down {
 			gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
 		};
 
-		dpad-left {
+		event-dpad-left {
 			label = "DPad Left";
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
@@ -135,7 +135,7 @@ dpad-left {
 			gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
 		};
 
-		dpad-right {
+		event-dpad-right {
 			label = "DPad Right";
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
@@ -143,7 +143,7 @@ dpad-right {
 			gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
 		};
 
-		dpad-up {
+		event-dpad-up {
 			label = "DPad Up";
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
@@ -151,7 +151,7 @@ dpad-up {
 			gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
 		};
 
-		dpad-down {
+		event-dpad-down {
 			label = "DPad Down";
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
@@ -159,49 +159,49 @@ dpad-down {
 			gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
 		};
 
-		x {
+		event-x {
 			label = "Button X";
 			linux,code = <BTN_X>;
 			gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
 		};
 
-		y {
+		event-y {
 			label = "Button Y";
 			linux,code = <BTN_Y>;
 			gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
 		};
 
-		a {
+		event-a {
 			label = "Button A";
 			linux,code = <BTN_A>;
 			gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
 		};
 
-		b {
+		event-b {
 			label = "Button B";
 			linux,code = <BTN_B>;
 			gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
 		};
 
-		select {
+		event-select {
 			label = "Select Button";
 			linux,code = <BTN_SELECT>;
 			gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
 		};
 
-		start {
+		event-start {
 			label = "Start Button";
 			linux,code = <BTN_START>;
 			gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
 		};
 
-		top-left {
+		event-top-left {
 			label = "Top Left Button";
 			linux,code = <BTN_TL>;
 			gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
 		};
 
-		top-right {
+		event-top-right {
 			label = "Top Right Button";
 			linux,code = <BTN_TR>;
 			gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 1ac82376baef..a332d61fd561 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -77,19 +77,19 @@ led-1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		back {
+		key-back {
 			label = "Key Back";
 			linux,code = <KEY_BACK>;
 			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
 		};
 
-		home {
+		key-home {
 			label = "Key Home";
 			linux,code = <KEY_HOME>;
 			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
 		};
 
-		menu {
+		key-menu {
 			label = "Key Menu";
 			linux,code = <KEY_MENU>;
 			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
index 2ce361f8fede..3a6c4bd0a44f 100644
--- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
+++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
@@ -67,18 +67,18 @@ leds {
 		compatible = "gpio-leds";
 
 		led-0 {
-			label ="licheepi:red:usr";
+			label = "licheepi:red:usr";
 			gpios = <&pio 2 5 GPIO_ACTIVE_LOW>;
 		};
 
 		led-1 {
-			label ="licheepi:green:usr";
+			label = "licheepi:green:usr";
 			gpios = <&pio 2 19 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
 		led-2 {
-			label ="licheepi:blue:usr";
+			label = "licheepi:blue:usr";
 			gpios = <&pio 2 4 GPIO_ACTIVE_LOW>;
 		};
 
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 715d74854449..6cdadba6a3ac 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/thermal/thermal.h>
 
 #include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 / {
@@ -598,7 +599,7 @@ ohci2: usb@1c1c400 {
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun6i-a31-ccu";
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -612,7 +613,8 @@ pio: pinctrl@1c20800 {
 				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -1319,7 +1321,7 @@ prcm@1f01400 {
 			ar100: ar100_clk {
 				compatible = "allwinner,sun6i-a31-ar100-clk";
 				#clock-cells = <0>;
-				clocks = <&rtc 0>, <&osc24M>,
+				clocks = <&rtc CLK_OSC32K>, <&osc24M>,
 					 <&ccu CLK_PLL_PERIPH>,
 					 <&ccu CLK_PLL_PERIPH>;
 				clock-output-names = "ar100";
@@ -1354,7 +1356,7 @@ apb0_gates: apb0_gates_clk {
 			ir_clk: ir_clk {
 				#clock-cells = <0>;
 				compatible = "allwinner,sun4i-a10-mod0-clk";
-				clocks = <&rtc 0>, <&osc24M>;
+				clocks = <&rtc CLK_OSC32K>, <&osc24M>;
 				clock-output-names = "ir";
 			};
 
@@ -1385,9 +1387,8 @@ r_pio: pinctrl@1f02c00 {
 			interrupt-parent = <&r_intc>;
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
+			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apb0_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 4f8d55d3ba79..928b86a95f34 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -78,19 +78,19 @@ led-1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		back {
+		key-back {
 			label = "Key Back";
 			linux,code = <KEY_BACK>;
 			gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
 		};
 
-		home {
+		key-home {
 			label = "Key Home";
 			linux,code = <KEY_HOME>;
 			gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
 		};
 
-		menu {
+		key-menu {
 			label = "Key Menu";
 			linux,code = <KEY_MENU>;
 			gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 4461d5098b20..f630ab55bb6a 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -44,6 +44,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
@@ -329,7 +330,7 @@ ohci0: usb@1c1a400 {
 
 		ccu: clock@1c20000 {
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -340,7 +341,8 @@ pio: pinctrl@1c20800 {
 			reg = <0x01c20800 0x400>;
 			interrupt-parent = <&r_intc>;
 			/* interrupts get set in SoC specific dtsi file */
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -810,9 +812,8 @@ r_pio: pinctrl@1f02c00 {
 			reg = <0x01f02c00 0x400>;
 			interrupt-parent = <&r_intc>;
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
+			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apb0_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
index d5c7b7984d85..d729b7c705db 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -47,10 +47,10 @@ pwr_led {
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		switch-4 {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -106,7 +106,7 @@ poweroff {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -181,7 +181,7 @@ &uart1 {
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		max-speed = <1500000>;
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index cd9f655e4f92..27a0d51289dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -93,10 +93,10 @@ led-1 {
 		};
 	};
 
-	r-gpio-keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -125,7 +125,7 @@ spdif_out: spdif-out {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
index ff0a7a952e0c..f5c8ccc5b872 100644
--- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
+++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts
@@ -39,16 +39,16 @@ status_led {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
 		};
 
-		user {
+		key-user {
 			label = "user";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
index 8e7dfcffe1fb..43641cb82398 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
@@ -37,10 +37,10 @@ led-1 {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		k1 {
+		key-0 {
 			label = "k1";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
@@ -90,7 +90,7 @@ reg_vdd_sys: vdd-sys {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 
@@ -151,7 +151,7 @@ &uart2 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
index cd3df12b6573..9e1a33f94cad 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -127,7 +127,7 @@ &uart3 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
index 26e2e6172e0d..42cd1131adf3 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
@@ -46,7 +46,7 @@ reg_vdd_cpux: gpio-regulator {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 
@@ -147,7 +147,7 @@ &uart3 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index a9f749f49beb..cf8413fba6c1 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -73,10 +73,10 @@ led-1 {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		k1 {
+		key-0 {
 			label = "k1";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 9daffd90c12f..f1f9dbead32a 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -88,16 +88,16 @@ pwr_led {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw2 {
+		switch-2 {
 			label = "sw2";
 			linux,code = <BTN_1>;
 			gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
 		};
 
-		sw4 {
+		switch-4 {
 			label = "sw4";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index 6f9c97add54e..305b34a321f5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -87,10 +87,10 @@ status_led {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		switch-4 {
 			label = "sw4";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 4759ba3f2986..59f6f6d5e7ca 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -86,10 +86,10 @@ status_led {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		switch-4 {
 			label = "sw4";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 90f75fa85e68..b96e015f54ee 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -86,10 +86,10 @@ status_led {
 		};
 	};
 
-	r_gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		switch-4 {
 			label = "sw4";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index bf5b5e2f6168..bc394686fedb 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -91,7 +91,7 @@ reg_vcc5v0: vcc5v0 {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -283,7 +283,7 @@ &uart1 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_dldo1>;
 		vddio-supply = <&reg_aldo3>;
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 03d3e5f45a09..75d55a46b50e 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -42,6 +42,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r40-ccu.h>
 #include <dt-bindings/clock/sun8i-tcon-top.h>
@@ -485,7 +486,7 @@ spi3: spi@1c1f000 {
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-r40-ccu";
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -504,7 +505,8 @@ pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun8i-r40-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -1231,7 +1233,7 @@ hdmi: hdmi@1ee0000 {
 			reg-io-width = <1>;
 			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
-				 <&ccu CLK_HDMI>, <&rtc 0>;
+				 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
 			clock-names = "iahb", "isfr", "tmds", "cec";
 			resets = <&ccu RST_BUS_HDMI1>;
 			reset-names = "ctrl";
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 084323d5c61c..db194c606fdc 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -42,6 +42,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 #include <dt-bindings/clock/sun8i-de2.h>
@@ -321,7 +322,7 @@ usbphy: phy@1c19400 {
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-v3s-ccu";
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -342,7 +343,8 @@ pio: pinctrl@1c20800 {
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index ce4fa6706d06..7d3f3300f431 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1218,7 +1218,6 @@ r_pio: pinctrl@8002c00 {
 				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apbs_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index d03f5853ef7b..e899d14f38c3 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -77,10 +77,10 @@ pwr_led {
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		switch-4 {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
@@ -101,7 +101,7 @@ reg_gmac_3v3: gmac-3v3 {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -221,7 +221,7 @@ &uart1 {
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		max-speed = <1500000>;
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
index fc67e30fe212..60804b0e6c56 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
@@ -22,7 +22,7 @@ wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
 		post-power-on-delay-ms = <200>;
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -124,7 +124,7 @@ &uart1 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_vcc3v3>;
 		vddio-supply = <&reg_vcc3v3>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d7e9f977f986..09aefb4e90f8 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,6 +40,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-h3-ccu.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
@@ -386,7 +387,7 @@ ohci3: usb@1c1d400 {
 		ccu: clock@1c20000 {
 			/* compatible is in per SoC .dtsi file */
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -398,7 +399,8 @@ pio: pinctrl@1c20800 {
 			interrupt-parent = <&r_intc>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
@@ -818,7 +820,7 @@ hdmi: hdmi@1ee0000 {
 			reg-io-width = <1>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
-				 <&ccu CLK_HDMI>, <&rtc 0>;
+				 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
 			clock-names = "iahb", "isfr", "tmds", "cec";
 			resets = <&ccu RST_BUS_HDMI1>;
 			reset-names = "ctrl";
@@ -878,7 +880,7 @@ r_intc: interrupt-controller@1f00c00 {
 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun8i-h3-r-ccu";
 			reg = <0x01f01400 0x100>;
-			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
 				 <&ccu CLK_PLL_PERIPH0>;
 			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
@@ -931,7 +933,8 @@ r_pio: pinctrl@1f02c00 {
 			reg = <0x01f02c00 0x400>;
 			interrupt-parent = <&r_intc>;
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
index 9e14fe5fdcde..89731bb34c6b 100644
--- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -42,10 +42,10 @@ status_led {
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		power {
+		key-power {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index a170a4ba36c1..bf1126d26aff 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -417,7 +417,7 @@ bluetooth {
 			vddio-supply = <&vdd_1v8_sys>;
 
 			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
-			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+			shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts
index a054d39db466..f3b0166f7a9c 100644
--- a/arch/arm/boot/dts/tegra20-asus-tf101.dts
+++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts
@@ -477,7 +477,7 @@ bluetooth {
 			vddio-supply = <&vdd_1v8_sys>;
 
 			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
-			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+			shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 2c2ad2a38f04..55e6171a411d 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -63,7 +63,7 @@ trustzone@bfe00000 {
 	gpio@6000d000 {
 		init-mode-hog {
 			gpio-hog;
-			gpios =	<TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
+			gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
 				<TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
 				<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
 			output-low;
@@ -820,7 +820,7 @@ bluetooth {
 			vddio-supply = <&vdd_1v8>;
 
 			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
-			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+			shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -833,7 +833,7 @@ i2c@7000c400 {
 		status = "okay";
 
 		touchscreen@10 {
-			compatible ="elan,ektf3624";
+			compatible = "elan,ektf3624";
 			reg = <0x10>;
 
 			interrupt-parent = <&gpio>;
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
index cd63e0ef7445..1b241f0542b8 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
@@ -25,7 +25,7 @@ panel-timing {
 	gpio@6000d000 {
 		init-mode-3g-hog {
 			gpio-hog;
-			gpios =	<TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
+			gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
 				<TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>,
 				<TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
 				<TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 22231d450b1b..310dff05910d 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -239,7 +239,7 @@ gen2-i2c-scl-pt5 {
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 			};
 			spdif-in-pk6 {
-				nvidia,pins =	"spdif_in_pk6";
+				nvidia,pins = "spdif_in_pk6";
 				nvidia,function = "hda";
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -364,7 +364,7 @@ gmi-wp-n-pc7 {
 			};
 			/* Multiplexed and therefore disabled */
 			cam-mclk-pcc0 {
-				nvidia,pins =	"cam_mclk_pcc0";
+				nvidia,pins = "cam_mclk_pcc0";
 				nvidia,function = "vi_alt3";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
@@ -511,7 +511,7 @@ uart2-rxd {
 
 			/* Colibri USBC_DET */
 			spdif-out-pk5 {
-				nvidia,pins =	"spdif_out_pk5";
+				nvidia,pins = "spdif_out_pk5";
 				nvidia,function = "rsvd2";
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index a9ed79b7f871..9270512c14ea 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -106,6 +106,7 @@ CONFIG_REGULATOR_GPIO=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_DRM=y
+CONFIG_DRM_V3D=y
 CONFIG_DRM_VC4=y
 CONFIG_FB_SIMPLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ce9826bce29b..948d18e59cf5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -747,6 +747,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
 CONFIG_DRM_IMX_TVE=m
 CONFIG_DRM_IMX_LDB=m
 CONFIG_DRM_IMX_HDMI=m
+CONFIG_DRM_V3D=m
 CONFIG_DRM_VC4=m
 CONFIG_DRM_ETNAVIV=m
 CONFIG_DRM_MXSFB=m
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 362643cbeffd..a29bebb3742e 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -6,7 +6,6 @@ CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_SMP=y
@@ -25,6 +24,7 @@ CONFIG_CPUFREQ_DT=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_SLAB=y
 CONFIG_CMA=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -106,6 +106,7 @@ CONFIG_WATCHDOG=y
 CONFIG_DA9063_WATCHDOG=y
 CONFIG_RENESAS_WDT=y
 CONFIG_RENESAS_RZAWDT=y
+CONFIG_RENESAS_RZN1WDT=y
 CONFIG_MFD_AS3711=y
 CONFIG_MFD_DA9063=y
 CONFIG_MFD_STMPE=y
@@ -177,6 +178,7 @@ CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_RX8581=y
 CONFIG_RTC_DRV_DA9063=y
 CONFIG_RTC_DRV_SH=y
+CONFIG_RTC_DRV_RZN1=y
 CONFIG_DMADEVICES=y
 CONFIG_RCAR_DMAC=y
 CONFIG_RENESAS_USB_DMAC=y
diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
index e4dba5461cb3..149a5bd6b88c 100644
--- a/arch/arm/crypto/Kconfig
+++ b/arch/arm/crypto/Kconfig
@@ -63,7 +63,7 @@ config CRYPTO_SHA512_ARM
 	  using optimized ARM assembler and NEON, when available.
 
 config CRYPTO_BLAKE2S_ARM
-	tristate "BLAKE2s digest algorithm (ARM)"
+	bool "BLAKE2s digest algorithm (ARM)"
 	select CRYPTO_ARCH_HAVE_LIB_BLAKE2S
 	help
 	  BLAKE2s digest algorithm optimized with ARM scalar instructions.  This
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 0274f81cc8ea..971e74546fb1 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -9,8 +9,7 @@ obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
 obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
 obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
 obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
-obj-$(CONFIG_CRYPTO_BLAKE2S_ARM) += blake2s-arm.o
-obj-$(if $(CONFIG_CRYPTO_BLAKE2S_ARM),y) += libblake2s-arm.o
+obj-$(CONFIG_CRYPTO_BLAKE2S_ARM) += libblake2s-arm.o
 obj-$(CONFIG_CRYPTO_BLAKE2B_NEON) += blake2b-neon.o
 obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
 obj-$(CONFIG_CRYPTO_POLY1305_ARM) += poly1305-arm.o
@@ -32,7 +31,6 @@ sha256-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha256_neon_glue.o
 sha256-arm-y	:= sha256-core.o sha256_glue.o $(sha256-arm-neon-y)
 sha512-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha512-neon-glue.o
 sha512-arm-y	:= sha512-core.o sha512-glue.o $(sha512-arm-neon-y)
-blake2s-arm-y   := blake2s-shash.o
 libblake2s-arm-y:= blake2s-core.o blake2s-glue.o
 blake2b-neon-y  := blake2b-neon-core.o blake2b-neon-glue.o
 sha1-arm-ce-y	:= sha1-ce-core.o sha1-ce-glue.o
diff --git a/arch/arm/crypto/blake2s-shash.c b/arch/arm/crypto/blake2s-shash.c
deleted file mode 100644
index 763c73beea2d..000000000000
--- a/arch/arm/crypto/blake2s-shash.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * BLAKE2s digest algorithm, ARM scalar implementation
- *
- * Copyright 2020 Google LLC
- */
-
-#include <crypto/internal/blake2s.h>
-#include <crypto/internal/hash.h>
-
-#include <linux/module.h>
-
-static int crypto_blake2s_update_arm(struct shash_desc *desc,
-				     const u8 *in, unsigned int inlen)
-{
-	return crypto_blake2s_update(desc, in, inlen, false);
-}
-
-static int crypto_blake2s_final_arm(struct shash_desc *desc, u8 *out)
-{
-	return crypto_blake2s_final(desc, out, false);
-}
-
-#define BLAKE2S_ALG(name, driver_name, digest_size)			\
-	{								\
-		.base.cra_name		= name,				\
-		.base.cra_driver_name	= driver_name,			\
-		.base.cra_priority	= 200,				\
-		.base.cra_flags		= CRYPTO_ALG_OPTIONAL_KEY,	\
-		.base.cra_blocksize	= BLAKE2S_BLOCK_SIZE,		\
-		.base.cra_ctxsize	= sizeof(struct blake2s_tfm_ctx), \
-		.base.cra_module	= THIS_MODULE,			\
-		.digestsize		= digest_size,			\
-		.setkey			= crypto_blake2s_setkey,	\
-		.init			= crypto_blake2s_init,		\
-		.update			= crypto_blake2s_update_arm,	\
-		.final			= crypto_blake2s_final_arm,	\
-		.descsize		= sizeof(struct blake2s_state),	\
-	}
-
-static struct shash_alg blake2s_arm_algs[] = {
-	BLAKE2S_ALG("blake2s-128", "blake2s-128-arm", BLAKE2S_128_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-160", "blake2s-160-arm", BLAKE2S_160_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-224", "blake2s-224-arm", BLAKE2S_224_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-256", "blake2s-256-arm", BLAKE2S_256_HASH_SIZE),
-};
-
-static int __init blake2s_arm_mod_init(void)
-{
-	return IS_REACHABLE(CONFIG_CRYPTO_HASH) ?
-		crypto_register_shashes(blake2s_arm_algs,
-					ARRAY_SIZE(blake2s_arm_algs)) : 0;
-}
-
-static void __exit blake2s_arm_mod_exit(void)
-{
-	if (IS_REACHABLE(CONFIG_CRYPTO_HASH))
-		crypto_unregister_shashes(blake2s_arm_algs,
-					  ARRAY_SIZE(blake2s_arm_algs));
-}
-
-module_init(blake2s_arm_mod_init);
-module_exit(blake2s_arm_mod_exit);
-
-MODULE_DESCRIPTION("BLAKE2s digest algorithm, ARM scalar implementation");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Eric Biggers <ebiggers@google.com>");
-MODULE_ALIAS_CRYPTO("blake2s-128");
-MODULE_ALIAS_CRYPTO("blake2s-128-arm");
-MODULE_ALIAS_CRYPTO("blake2s-160");
-MODULE_ALIAS_CRYPTO("blake2s-160-arm");
-MODULE_ALIAS_CRYPTO("blake2s-224");
-MODULE_ALIAS_CRYPTO("blake2s-224-arm");
-MODULE_ALIAS_CRYPTO("blake2s-256");
-MODULE_ALIAS_CRYPTO("blake2s-256-arm");
diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
index 39769ffa0051..9694808ee97c 100644
--- a/arch/arm/include/asm/hardware/cache-aurora-l2.h
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AURORA shared L2 cache controller support
  *
@@ -5,10 +6,6 @@
  *
  * Yehuda Yitschak <yehuday@marvell.com>
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
index 12e1588dc4f1..eb2e7b7f70a8 100644
--- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h
+++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
@@ -1,13 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/include/asm/hardware/cache-feroceon-l2.h
  *
  * Copyright (C) 2008 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 extern void __init feroceon_l2_init(int l2_wt_override);
 extern int __init feroceon_of_init(void);
-
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 295e2e40151b..4e493facaa31 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/include/asm/hardware/cache-tauros2.h
  *
  * Copyright (C) 2008 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define CACHE_TAUROS2_PREFETCH_ON	(1 << 0)
diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index f684e3a815f6..f6175e6e28cd 100644
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2016 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2016 Broadcom */
 #include <linux/serial_reg.h>
 #include <asm/cputype.h>
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 7aa3ded4af92..405a607b754f 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -28,7 +28,7 @@
 #include "entry-header.S"
 
 saved_psr	.req	r8
-#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
+#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING_USER)
 saved_pc	.req	r9
 #define TRACE(x...) x
 #else
@@ -38,7 +38,7 @@ saved_pc	.req	lr
 
 	.section .entry.text,"ax",%progbits
 	.align	5
-#if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING) || \
+#if !(IS_ENABLED(CONFIG_TRACE_IRQFLAGS) || IS_ENABLED(CONFIG_CONTEXT_TRACKING_USER) || \
 	IS_ENABLED(CONFIG_DEBUG_RSEQ))
 /*
  * This is the fast syscall return path.  We do as little as possible here,
@@ -302,6 +302,7 @@ local_restart:
 	b	ret_fast_syscall
 #endif
 ENDPROC(vector_swi)
+	.ltorg
 
 	/*
 	 * This is the really slow path.  We're going to be doing
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 5865621bf691..99411fa91350 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -366,25 +366,25 @@ ALT_UP_B(.L1_\@)
  * between user and kernel mode.
  */
 	.macro ct_user_exit, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
 	.if	\save
 	stmdb   sp!, {r0-r3, ip, lr}
-	bl	context_tracking_user_exit
+	bl	user_exit_callable
 	ldmia	sp!, {r0-r3, ip, lr}
 	.else
-	bl	context_tracking_user_exit
+	bl	user_exit_callable
 	.endif
 #endif
 	.endm
 
 	.macro ct_user_enter, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
 	.if	\save
 	stmdb   sp!, {r0-r3, ip, lr}
-	bl	context_tracking_user_enter
+	bl	user_enter_callable
 	ldmia	sp!, {r0-r3, ip, lr}
 	.else
-	bl	context_tracking_user_enter
+	bl	user_enter_callable
 	.endif
 #endif
 	.endm
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 5c6f8d11a3ce..034cb48c9eeb 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -70,6 +70,7 @@ static void __init init_irq_stacks(void)
 	}
 }
 
+#ifndef CONFIG_PREEMPT_RT
 static void ____do_softirq(void *arg)
 {
 	__do_softirq();
@@ -80,7 +81,7 @@ void do_softirq_own_stack(void)
 	call_with_stack(____do_softirq, NULL,
 			__this_cpu_read(irq_stack_ptr));
 }
-
+#endif
 #endif
 
 int arch_show_interrupts(struct seq_file *p, int prec)
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
index 512943eae30a..2e203626eda5 100644
--- a/arch/arm/mach-axxia/platsmp.c
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -39,6 +39,7 @@ static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
 		return -ENOENT;
 
 	syscon = of_iomap(syscon_np, 0);
+	of_node_put(syscon_np);
 	if (!syscon)
 		return -ENOMEM;
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b2394ddb0558..61806baf2f48 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,14 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
 #
 # Copyright (C) 2012-2015 Broadcom Corporation
 #
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation version 2.
-#
-# This program is distributed "as is" WITHOUT ANY WARRANTY of any
-# kind, whether express or implied; without even the implied warranty
-# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
 
 # Cygnus
 obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
diff --git a/arch/arm/mach-bcm/bcm63xx.c b/arch/arm/mach-bcm/bcm63xx.c
index c4c66ae51308..f855e361dfba 100644
--- a/arch/arm/mach-bcm/bcm63xx.c
+++ b/arch/arm/mach-bcm/bcm63xx.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <linux/of_platform.h>
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
index 7ae894c7849b..2469b66cc59e 100644
--- a/arch/arm/mach-bcm/bcm_cygnus.c
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-bcm/bcm_hr2.c b/arch/arm/mach-bcm/bcm_hr2.c
index c104f28995d7..a19cc206ec76 100644
--- a/arch/arm/mach-bcm/bcm_hr2.c
+++ b/arch/arm/mach-bcm/bcm_hr2.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2017 Broadcom
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 43829e49ad93..185335843bbd 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013 Broadcom Corporation
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
@@ -52,6 +42,7 @@ int __init bcm_kona_smc_init(void)
 		return -ENODEV;
 
 	prop_val = of_get_address(node, 0, &prop_size, NULL);
+	of_node_put(node);
 	if (!prop_val)
 		return -EINVAL;
 
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
index 2e29ec67e414..17f3811fa543 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.h
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2013 Broadcom Corporation */
 
 #ifndef BCM_KONA_SMC_H
 #define BCM_KONA_SMC_H
diff --git a/arch/arm/mach-bcm/bcm_nsp.c b/arch/arm/mach-bcm/bcm_nsp.c
index a1101a3d318e..65ed9f8a518a 100644
--- a/arch/arm/mach-bcm/bcm_nsp.c
+++ b/arch/arm/mach-bcm/bcm_nsp.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015 Broadcom Corporation
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
index c5bf01641172..9ce9ed092b09 100644
--- a/arch/arm/mach-bcm/board_bcm21664.c
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-bcm/board_bcm23550.c b/arch/arm/mach-bcm/board_bcm23550.c
index 0ac01debd077..dd6e9cb785e0 100644
--- a/arch/arm/mach-bcm/board_bcm23550.c
+++ b/arch/arm/mach-bcm/board_bcm23550.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2016 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2016 Broadcom
 
 #include <linux/of_platform.h>
 
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 1238ac801530..91f6d633ee8e 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2014 Broadcom Corporation
 
 #include <linux/clocksource.h>
 #include <linux/of_address.h>
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
index 5f127d5f1045..2e3385ced82a 100644
--- a/arch/arm/mach-bcm/brcmstb.c
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2013-2014 Broadcom Corporation
 
 #include <linux/init.h>
 #include <linux/irqchip.h>
diff --git a/arch/arm/mach-bcm/kona_l2_cache.c b/arch/arm/mach-bcm/kona_l2_cache.c
index 59ad86304092..457c66e1d7ae 100644
--- a/arch/arm/mach-bcm/kona_l2_cache.c
+++ b/arch/arm/mach-bcm/kona_l2_cache.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2012-2014 Broadcom Corporation
 
 
 #include <linux/init.h>
diff --git a/arch/arm/mach-bcm/kona_l2_cache.h b/arch/arm/mach-bcm/kona_l2_cache.h
index 46f84a95ab1c..77c5dc033910 100644
--- a/arch/arm/mach-bcm/kona_l2_cache.h
+++ b/arch/arm/mach-bcm/kona_l2_cache.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2012-2014 Broadcom Corporation */
 
 #ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE
 void	kona_l2_cache_init(void);
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index 9b457714a41c..8989299ebdd6 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Broadcom STB CPU SMP and hotplug support for ARM
  *
  * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index a0aaab5c7aa6..6299e5c8f4ea 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -1,13 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DA830/OMAP L137 EVM board
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
  *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007, 2009 (c) MontaVista Software, Inc.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index efc26b472ef8..92d74bc71967 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DA850/OMAP-L138 EVM board
  *
@@ -6,10 +7,7 @@
  * Derived from: arch/arm/mach-davinci/board-da830-evm.c
  * Original Copyrights follow:
  *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007, 2009 (c) MontaVista Software, Inc.
  */
 #include <linux/console.h>
 #include <linux/delay.h>
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index f7c56f662d4c..b48ab1c3e48b 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci EVM board support
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 0f2b61266197..32b9d607d025 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * DM355 leopard board support
  *
  * Based on board-dm355-evm.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 9adcb5879d14..d8c6c360818b 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM365 EVM board support
  *
  * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -861,4 +853,3 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 	.init_late	= davinci_init_late,
 	.dma_zone_size	= SZ_128M,
 MACHINE_END
-
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 9f405af36a6f..ebdd5c334ac1 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci EVM board support
  *
  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 84ad065e98c2..28861fee493b 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM646X EVM board
  *
@@ -5,11 +6,6 @@
  * Copyright (C) 2006 Texas Instruments.
  *
  * (C) 2007-2008, MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
  */
 
 /**************************************************************************
@@ -870,4 +866,3 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
 	.init_late	= davinci_init_late,
 	.dma_zone_size	= SZ_128M,
 MACHINE_END
-
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 3f084bdb9bc5..a46e7b9ff8e0 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Critical Link MityOMAP-L138 SoM
  *
  * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of
- * any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "MityOMAPL138: " fmt
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 94be492b8a9e..9748a2c12cc4 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Neuros Technologies OSD2 board support
  *
@@ -18,10 +19,6 @@
  *
  * For more information please refer to
  * 		http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 20f71856bf7e..8a80115999ad 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Hawkboard.org based on TI's OMAP-L138 Platform
  *
  * Initial code: Syed Mohammed Khasim
  *
  * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of
- * any kind, whether express or implied.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 0a6f826ff136..c1ce6b2a8d48 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Code commons to all DaVinci SoCs.
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
  */
 #include <linux/module.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h
index 139b83de011d..772b51e0ac5e 100644
--- a/arch/arm/mach-davinci/common.h
+++ b/arch/arm/mach-davinci/common.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Header for code common to all DaVinci machines.
  *
  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  */
 
 #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h
index 0d9193aefab5..976d43073597 100644
--- a/arch/arm/mach-davinci/cpuidle.h
+++ b/arch/arm/mach-davinci/cpuidle.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * TI DaVinci cpuidle platform support
  *
  * 2009 (C) Texas Instruments, Inc. https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 #ifndef _MACH_DAVINCI_CPUIDLE_H
 #define _MACH_DAVINCI_CPUIDLE_H
diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h
index 1fe9f84d5ee6..4590afdbe449 100644
--- a/arch/arm/mach-davinci/cputype.h
+++ b/arch/arm/mach-davinci/cputype.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * DaVinci CPU type detection
  *
@@ -8,10 +9,7 @@
  * compiled in to the kernel, the macros return 0 so that
  * resulting code can be optimized out.
  *
- * 2009 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) Deep Root Systems, LLC.
  */
 #ifndef _ASM_ARCH_CPU_H
 #define _ASM_ARCH_CPU_H
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 1b86657c6e9d..eab5fac18806 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DA830/OMAP L137 chip specific setup
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
  */
 #include <linux/clk-provider.h>
 #include <linux/clk/davinci.h>
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index cd514c136de0..635e88daf5dd 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DA850/OMAP-L138 chip specific setup
  *
@@ -6,10 +7,7 @@
  * Derived from: arch/arm/mach-davinci/da830.c
  * Original Copyrights follow:
  *
- * 2009 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2009 (c) MontaVista Software, Inc.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h
index 699df08714ba..382811dbbc3b 100644
--- a/arch/arm/mach-davinci/da8xx.h
+++ b/arch/arm/mach-davinci/da8xx.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Chip specific defines for DA8XX/OMAP L1XX SoC
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007, 2009-2010 (c) MontaVista Software, Inc.
  */
 #ifndef __ASM_ARCH_DAVINCI_DA8XX_H
 #define __ASM_ARCH_DAVINCI_DA8XX_H
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index e895eaf9c7cc..b7172797692b 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -1,18 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * This file contains the processor specific definitions
  * of the TI DM644x, DM355, DM365, and DM646x.
  *
  * Copyright (C) 2011 Texas Instruments Incorporated
  * Copyright (c) 2007 Deep Root Systems, LLC
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #ifndef __DAVINCI_H
 #define __DAVINCI_H
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 1d7443c59b14..a12ba859beca 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM355 chip specific setup
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) Deep Root Systems, LLC.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 73ccc916f60a..7538bb87f373 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM365 chip specific setup
  *
  * Copyright (C) 2009 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 1ce48d0fb16d..c8a276c42957 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM644x chip specific setup
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) Deep Root Systems, LLC.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 971b2d4e2595..fbee617d00ca 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -1,12 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI DaVinci DM646x chip specific setup
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) Deep Root Systems, LLC.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-davinci/hardware.h b/arch/arm/mach-davinci/hardware.h
index 16bb42291d39..7848b6a240b4 100644
--- a/arch/arm/mach-davinci/hardware.h
+++ b/arch/arm/mach-davinci/hardware.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Hardware definitions common to all DaVinci family processors
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) Deep Root Systems, LLC.
  */
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index bab1eea7fca6..814a6b714010 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Utility to set the DAVINCI MUX register from a table in mux.h
  *
@@ -8,10 +9,7 @@
  *
  * Written by Tony Lindgren
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  *
  * Copyright (C) 2008 Texas Instruments.
  */
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
index b0d1c4fb78dc..b5effe16402c 100644
--- a/arch/arm/mach-davinci/mux.h
+++ b/arch/arm/mach-davinci/mux.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Pin-multiplex helper macros for TI DaVinci family devices
  *
  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  *
  * Copyright (C) 2008 Texas Instruments.
  */
diff --git a/arch/arm/mach-davinci/pm.h b/arch/arm/mach-davinci/pm.h
index 5a5f0ecc0704..6f50d6eb8da8 100644
--- a/arch/arm/mach-davinci/pm.h
+++ b/arch/arm/mach-davinci/pm.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * TI DaVinci platform support for power management.
  *
  * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #ifndef _MACH_DAVINCI_PM_H
 #define _MACH_DAVINCI_PM_H
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c
index e251fd593bfd..6b21d5bd999c 100644
--- a/arch/arm/mach-davinci/pm_domain.c
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Runtime PM support code for DaVinci
  *
  * Author: Kevin Hilman
  *
  * Copyright (C) 2012 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/init.h>
 #include <linux/pm_runtime.h>
diff --git a/arch/arm/mach-davinci/serial.h b/arch/arm/mach-davinci/serial.h
index 14473cb19852..c4a4ba553d45 100644
--- a/arch/arm/mach-davinci/serial.h
+++ b/arch/arm/mach-davinci/serial.h
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * DaVinci serial device definitions
  *
  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
  */
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
diff --git a/arch/arm/mach-dove/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h
index ace0b0bfbf11..6fbc152d0950 100644
--- a/arch/arm/mach-dove/bridge-regs.h
+++ b/arch/arm/mach-dove/bridge-regs.h
@@ -1,10 +1,5 @@
-/*
- * Mbus-L to Mbus Bridge Registers
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Mbus-L to Mbus Bridge Registers */
 
 #ifndef __ASM_ARCH_BRIDGE_REGS_H
 #define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 9f25c993d863..beb532537c22 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/cm-a510.c
  *
@@ -5,10 +6,6 @@
  * Konstantin Sinyuk <kostyas@compulab.co.il>
  *
  * Based on Marvell DB-MV88AP510-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dbe970e37895..cd4ae7e4768d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/common.c
  *
  * Core functions for Marvell Dove 88AP510 System On Chip
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 1d725224d146..57ebc413d68c 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/mach-dove/common.h
  *
  * Core functions for Marvell Dove 88AP510 System On Chip
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ARCH_DOVE_COMMON_H
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 418ab21b9d9b..d5bf54040577 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/dove-db-setup.c
  *
  * Marvell DB-MV88AP510-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/dove.h b/arch/arm/mach-dove/dove.h
index 320ed1696abd..e5054e3b0b78 100644
--- a/arch/arm/mach-dove/dove.h
+++ b/arch/arm/mach-dove/dove.h
@@ -1,10 +1,5 @@
-/*
- * Generic definitions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Generic definitions for Marvell Dove 88AP510 SoC */
 
 #ifndef __ASM_ARCH_DOVE_H
 #define __ASM_ARCH_DOVE_H
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index d36f6b8269c2..027a8f87bc2e 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/irq.c
  *
  * Dove IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/init.h>
 #include <linux/irq.h>
diff --git a/arch/arm/mach-dove/irqs.h b/arch/arm/mach-dove/irqs.h
index a0742179faff..5467098c7042 100644
--- a/arch/arm/mach-dove/irqs.h
+++ b/arch/arm/mach-dove/irqs.h
@@ -1,10 +1,5 @@
-/*
- * IRQ definitions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* IRQ definitions for Marvell Dove 88AP510 SoC */
 
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 6acd8488bb05..93cb137da5f8 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/mpp.c
  *
  * MPP functions for Marvell Dove SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 2a493bdfffc6..91420da4cfd2 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-dove/pcie.c
  *
  * PCIe functions for Marvell Dove 88AP510 SoC
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-dove/pm.h b/arch/arm/mach-dove/pm.h
index 01267746d707..a4c3aba1e2d0 100644
--- a/arch/arm/mach-dove/pm.h
+++ b/arch/arm/mach-dove/pm.h
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef __ASM_ARCH_PM_H
 #define __ASM_ARCH_PM_H
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 8b48326be9fd..51a247ca4da8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -149,6 +149,7 @@ static void exynos_map_pmu(void)
 	np = of_find_matching_node(NULL, exynos_dt_pmu_match);
 	if (np)
 		pmu_base_addr = of_iomap(np, 0);
+	of_node_put(np);
 }
 
 static void __init exynos_init_irq(void)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 696c59fe4588..77e435df8dfe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -96,7 +96,7 @@ config SOC_IMX5
 	select HAVE_IMX_SRC
 	select MXC_TZIC
 
-config	SOC_IMX50
+config SOC_IMX50
 	bool "i.MX50 support"
 	select PINCTRL_IMX50
 	select SOC_IMX5
@@ -111,7 +111,7 @@ config SOC_IMX51
 	help
 	  This enables support for Freescale i.MX51 processor
 
-config	SOC_IMX53
+config SOC_IMX53
 	bool "i.MX53 support"
 	select PINCTRL_IMX53
 	select SOC_IMX5
@@ -216,7 +216,7 @@ config SOC_IMX7D
 	select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
 	select ARM_ERRATA_814220 if ARCH_MULTI_V7
 	help
-		This enables support for Freescale i.MX7 Dual processor.
+	  This enables support for Freescale i.MX7 Dual processor.
 
 config SOC_IMX7ULP
 	bool "i.MX7ULP support"
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index b2e1963f473d..3e63445cde06 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -32,6 +32,8 @@ static int mx25_read_cpu_rev(void)
 		return IMX_CHIP_REVISION_1_0;
 	case 0x01:
 		return IMX_CHIP_REVISION_1_1;
+	case 0x02:
+		return IMX_CHIP_REVISION_1_2;
 	default:
 		return IMX_CHIP_REVISION_UNKNOWN;
 	}
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 094337dc1bc7..d086cbae09c3 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
  */
 
+#include <linux/context_tracking.h>
 #include <linux/cpuidle.h>
 #include <linux/module.h>
 #include <asm/cpuidle.h>
@@ -24,9 +25,9 @@ static int imx6q_enter_wait(struct cpuidle_device *dev,
 		imx6_set_lpm(WAIT_UNCLOCKED);
 	raw_spin_unlock(&cpuidle_lock);
 
-	rcu_idle_enter();
+	ct_idle_enter();
 	cpu_do_idle();
-	rcu_idle_exit();
+	ct_idle_exit();
 
 	raw_spin_lock(&cpuidle_lock);
 	if (num_idle_cpus-- == num_online_cpus())
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
index fdcee78d1bc4..4729eb83401a 100644
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ b/arch/arm/mach-lpc18xx/board-dt.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree board file for NXP LPC18xx/43xx
  *
  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index b27fa1b9f56c..2572bd89a5e8 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -1,13 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-lpc32xx/pm.c
  *
  * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
  * Modified by Kevin Wells <kevin.wells@nxp.com>
  *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
  */
 
 /*
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index 3f0a8282ef6f..a95c5e0e4038 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -1,13 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/mach-lpc32xx/suspend.S
  *
  * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
  * Modified by Kevin Wells <kevin.wells@nxp.com>
  *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
index 4b8ad728bb42..32ac60b89fdc 100644
--- a/arch/arm/mach-meson/platsmp.c
+++ b/arch/arm/mach-meson/platsmp.c
@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
 	}
 
 	sram_base = of_iomap(node, 0);
+	of_node_put(node);
 	if (!sram_base) {
 		pr_err("Couldn't map SRAM registers\n");
 		return;
@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
 	}
 
 	scu_base = of_iomap(node, 0);
+	of_node_put(node);
 	if (!scu_base) {
 		pr_err("Couldn't map SCU registers\n");
 		return;
diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h
index 2f54e1753d45..d57ac967c4b3 100644
--- a/arch/arm/mach-mv78xx0/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/bridge-regs.h
@@ -1,8 +1,4 @@
-/*
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef __ASM_ARCH_BRIDGE_REGS_H
 #define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index e112f2e7cc9a..9aa765d4cdc8 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
  *
  * Buffalo WXL (Terastation Duo) Setup routines
  *
  * sebastien requiem <sebastien@requiem.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index dd762d1b083f..461a68945c26 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78xx0/common.c
  *
  * Core functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 6889af26077d..d8c6c2400e27 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/mach-mv78xx0/common.h
  *
  * Core functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ARCH_MV78XX0_COMMON_H
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index cf16e08d4cf5..da633a33a0c1 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
  *
  * Marvell DB-78x00-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 0b5f055ca1c3..a34b6855fb19 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78xx0/irq.c
  *
  * MV78xx0 IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h
index 67e0fe730a13..12b357d383d8 100644
--- a/arch/arm/mach-mv78xx0/irqs.h
+++ b/arch/arm/mach-mv78xx0/irqs.h
@@ -1,10 +1,5 @@
-/*
- * IRQ definitions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* IRQ definitions for Marvell MV78xx0 SoCs */
 
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 72843c02e95a..aff0e612cbba 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78x00/mpp.c
  *
  * MPP functions for Marvell MV78x00 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 3752302ae2ee..47db52f45546 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins
  *
- *
  * sebastien requiem <sebastien@requiem.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MV78X00_MPP_H
diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h
index c1a9a1d1b295..3f19bef7d7ac 100644
--- a/arch/arm/mach-mv78xx0/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/mv78xx0.h
@@ -1,10 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Generic definitions for Marvell MV78xx0 SoC flavors:
  *  MV781x0 and MV782x0.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ASM_ARCH_MV78XX0_H
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index e15646af7f26..9de2e47721b8 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78xx0/pcie.c
  *
  * PCIe functions for Marvell MV78xx0 SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 308ab71ec822..80ca8b1a81de 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mv78x00/rd78x00-masa-setup.c
  *
  * Marvell RD-78x00-mASA Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 09413b678409..c96ecdafe31f 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Generic definitions for Marvell Armada_370_XP SoCs
  *
@@ -6,10 +7,6 @@
  * Lior Amsalem <alior@marvell.com>
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_ARMADA_370_XP_H
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index d2df5ef9382b..fd5d0c8ff695 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Device Tree support for Armada 370 and XP platforms.
  *
@@ -6,10 +7,6 @@
  * Lior Amsalem <alior@marvell.com>
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 49e3c8d20c2f..883dab1b54f3 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
  * platforms.
@@ -8,10 +9,6 @@
  * Gregory Clement <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
  * responsible for ensuring hardware coherency between all CPUs and between
  * CPUs and I/O masters. This file initializes the coherency fabric and
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 6067f14263f7..cae866ab4867 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/mach-mvebu/include/mach/coherency.h
  *
- *
  * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
  *
  * Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_370_XP_COHERENCY_H
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index a3a64bf97250..eb81656e32d4 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Coherency fabric: low level functions
  *
@@ -5,10 +6,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * This file implements the assembly function to add a CPU to the
  * coherency fabric. This function is called by each of the secondary
  * CPUs during their early boot in an SMP kernel, this why this
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 6b775492cfad..fbfa3c4f30df 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Core functions for Marvell System On Chip
  *
@@ -6,10 +7,6 @@
  * Lior Amsalem <alior@marvell.com>
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ARCH_MVEBU_COMMON_H
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
index f33a31c6aff8..66b6c0c6ce1d 100644
--- a/arch/arm/mach-mvebu/cpu-reset.c
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2014 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "mvebu-cpureset: " fmt
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index d076c5771adc..c938ba725d3e 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-mvebu/dove.c
  *
  * Marvell Dove 88AP510 System On Chip FDT Board
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/init.h>
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index b093a196e801..df723cf85cae 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * SMP support: Entry point for secondary CPUs of Marvell EBU
  * Cortex-A9 based SOCs (Armada 375 and Armada 38x).
@@ -6,10 +7,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/linkage.h>
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index 2c4032e368ba..f05c59dad32a 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * SMP support: Entry point for secondary CPUs
  *
@@ -7,10 +8,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * This file implements the assembly entry point for secondary CPUs in
  * an SMP kernel. The only thing we need to do is to add the CPU to
  * the coherency fabric by writing to 2 registers. Currently the base
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 06b1706595f4..8ff34753e760 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
  *
  * arch/arm/mach-mvebu/kirkwood.c
  *
  * Flattened Device Tree board initialization
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h
index 89f3d1f51643..15135994ce2f 100644
--- a/arch/arm/mach-mvebu/kirkwood.h
+++ b/arch/arm/mach-mvebu/kirkwood.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/mach-mvebu/kirkwood.h
  *
  * Generic definitions for Marvell Kirkwood SoC flavors:
  * 88F6180, 88F6192 and 88F6281.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define KIRKWOOD_REGS_PHYS_BASE	0xf1000000
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index a99434bcee84..f436c7b8c7ae 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * ID and revision information for mvebu SoCs
  *
@@ -5,10 +6,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * All the mvebu SoCs have information related to their variant and
  * revision that can be read from the PCI control register. This is
  * done before the PCI initialization to avoid any conflict. Once the
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h
index e124a0b82a3e..225649b2288a 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.h
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Marvell EBU SoC ID and revision definitions.
  *
  * Copyright (C) 2014 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __LINUX_MVEBU_SOC_ID_H
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index d715dec1c197..785ee2af5baa 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Symmetric Multi Processing (SMP) support for Marvell EBU Cortex-A9
  * based SOCs (Armada 375/38x).
@@ -6,10 +7,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/init.h>
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index c130497dc6cc..18384ea6862c 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Symmetric Multi Processing (SMP) support for Armada XP
  *
@@ -8,10 +9,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
  * This file implements the routines for preparing the SMP infrastructure
  * and waking up the secondary CPUs
diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c
index 070552511699..7fa1806acd65 100644
--- a/arch/arm/mach-mvebu/pm-board.c
+++ b/arch/arm/mach-mvebu/pm-board.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Board-level suspend/resume support.
  *
  * Copyright (C) 2014-2015 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mvebu/pm.c b/arch/arm/mach-mvebu/pm.c
index c487be61d6d8..b149d9b77505 100644
--- a/arch/arm/mach-mvebu/pm.c
+++ b/arch/arm/mach-mvebu/pm.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Suspend/resume support. Currently supporting Armada XP only.
  *
  * Copyright (C) 2014 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/cpu_pm.h>
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 73d5d72dfc3e..af27a7156675 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
  *
@@ -7,10 +8,6 @@
  * Gregory Clement <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The Armada 370 and Armada XP SOCs have a power management service
  * unit which is responsible for powering down and waking up CPUs and
  * other SOC units
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
index ea79269c2702..1e847388e8dd 100644
--- a/arch/arm/mach-mvebu/pmsu.h
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Power Management Service Unit (PMSU) support for Armada 370/XP platforms.
  *
  * Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_MVEBU_PMSU_H
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
index 7aae9a25cfeb..f7d21385fd88 100644
--- a/arch/arm/mach-mvebu/pmsu_ll.S
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2014 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Gregory Clement <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/linkage.h>
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 04d9ebe6a90a..48224b6ed6dc 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * System controller support for Armada 370, 375 and XP platforms.
  *
@@ -7,10 +8,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The Armada 370, 375 and Armada XP SoCs have a range of
  * miscellaneous registers, that do not belong to a particular device,
  * but rather provide system-level features. This basic
diff --git a/arch/arm/mach-omap1/board-sx1.h b/arch/arm/mach-omap1/board-sx1.h
index 355adbdaae33..fafe54a2e444 100644
--- a/arch/arm/mach-omap1/board-sx1.h
+++ b/arch/arm/mach-omap1/board-sx1.h
@@ -1,15 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Siemens SX1 board definitions
  *
  * Copyright: Vovan888 at gmail com
- *
- * This package is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
 #ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 3faf2b7c2d09..c675f11de99d 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP15xx specific gpio init
  *
@@ -5,15 +6,6 @@
  *
  * Author:
  *	Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 2a25751007d4..cf052714b3f8 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP16xx specific gpio init
  *
@@ -5,15 +6,6 @@
  *
  * Author:
  *	Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 46b7d5d4d255..c372b357eab4 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP7xx specific gpio init
  *
@@ -5,15 +6,6 @@
  *
  * Author:
  *	Charulatha V <charu@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-omap1/mtd-xip.h b/arch/arm/mach-omap1/mtd-xip.h
index b675d501b13d..5ae312ff08a1 100644
--- a/arch/arm/mach-omap1/mtd-xip.h
+++ b/arch/arm/mach-omap1/mtd-xip.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * MTD primitives for XIP support. Architecture specific functions.
  *
@@ -5,10 +6,7 @@
  *
  * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
  *
- * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
+ * (c) 2005 MontaVista Software, Inc.
  */
 
 #ifndef __ARCH_OMAP_MTD_XIP_H__
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 667c1637ff91..c04619ac0631 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Runtime PM support code for OMAP1
  *
  * Author: Kevin Hilman, Deep Root Systems, LLC
  *
  * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -43,4 +40,3 @@ static int __init omap1_pm_runtime_init(void)
 	return 0;
 }
 core_initcall(omap1_pm_runtime_init);
-
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 9ed64345f06e..f5cd4bbf7566 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP1 Dual-Mode Timers - platform device registration
  *
@@ -9,15 +10,6 @@
  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
  * Thara Gopinath <thara@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a8adbb4d478a..f7f940282c3f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -105,6 +105,7 @@ config ARCH_OMAP2PLUS
 	select MACH_OMAP_GENERIC
 	select MEMORY
 	select MFD_SYSCON
+	select OMAP_DM_SYSTIMER
 	select OMAP_DM_TIMER
 	select OMAP_GPMC
 	select PINCTRL
@@ -209,6 +210,7 @@ config SOC_OMAP2420
 	bool "OMAP2420 support"
 	depends on ARCH_OMAP2
 	default y
+	select OMAP_DM_SYSTIMER
 	select OMAP_DM_TIMER
 	select SOC_HAS_OMAP2_SDRC
 
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index bf2b5f87e404..32bcfcf34817 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * This file contains the address info for various AM33XX modules.
  *
  * Copyright (C) 2011 Texas Instruments, Inc. - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_AM33XX_H
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index b4d5144df445..87f4e927eb18 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM33XX Clock Domain data.
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
  * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 127dc7ace71f..549cf61487a5 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI81XX Clock Domain data.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index e7ae2bb515e3..1b97219aaba4 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AM33XX Power Management register bits
  *
@@ -5,15 +6,6 @@
  * Vaibhav Hiremath <hvaibhav@ti.com>
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index ac4882ebdca3..d61fa06117b4 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM33XX CM functions
  *
@@ -5,15 +6,6 @@
  * Vaibhav Hiremath <hvaibhav@ti.com>
  *
  * Reference taken from from OMAP4 cminst44xx.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index af63d1892c33..456267a7af71 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AM33XX CM offset macros
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
  * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index bd91223e838e..ffcde1812c6c 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Clock domain register offsets for TI81XX.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 21413a9b7b6c..47149b278ad5 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP2plus display device setup / initialization.
  *
  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
  *	Senthilvadivu Guruswamy
  *	Sumit Semwal
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/string.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 450ab990c66a..9b5c728fb7da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -1,18 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * DM81xx hwmod data.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 533dd643069a..88375ab38e31 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * OMAP SoC specific OPP Data helpers
  *
@@ -6,15 +7,6 @@
  *	Kevin Hilman
  * Copyright (C) 2010 Nokia Corporation.
  *      Eduardo Valentin
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
 #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index b610c5fb423b..90257e2fb3d6 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP3 OPP table definitions.
  *
@@ -7,15 +8,6 @@
  * Copyright (C) 2010-2011 Nokia Corporation.
  *      Eduardo Valentin
  *      Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/module.h>
 
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index d937c5ef41c6..a9851886017d 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP4 OPP table definitions.
  *
@@ -8,15 +9,6 @@
  * Copyright (C) 2010-2011 Nokia Corporation.
  *      Eduardo Valentin
  *      Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/module.h>
 
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 626055e59aed..1d58fd1a2dce 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM33XX Power domain data
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index b65cccab6ad9..38ed69b150cb 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AM43x PRCM defines
  *
  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 7dfdff09ddeb..3748c5266ae1 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AM33XX PRM_XXX register bits
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 9144cc0479af..4b65a0f9cf7d 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM33XX PRM functions
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index a469a36c00d8..3081f3deb650 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * AM33XX PRM instance offset macros
  *
  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index 192b0e7d3eb4..fe9f7f388cbd 100644
--- a/arch/arm/mach-omap2/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -1,16 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * This file contains the address data for various TI81XX modules.
  *
  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef __ASM_ARCH_TI81XX_H
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 86f1ac4c2412..ea02d40405c4 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP Voltage Controller (VC) interface
  *
  * Copyright (C) 2011 Texas Instruments, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/kernel.h>
 #include <linux/delay.h>
@@ -895,4 +892,3 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 	else if (cpu_is_omap44xx())
 		omap4_vc_init_channel(voltdm);
 }
-
diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c
index a89376a5cd92..0297e302d7bc 100644
--- a/arch/arm/mach-orion5x/board-d2net.c
+++ b/arch/arm/mach-orion5x/board-d2net.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/board-d2net.c
  *
  * LaCie d2Network and Big Disk Network NAS setup
  *
  * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 3d36f1d95196..e3736ffc8347 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright 2012 (C), Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
  * arch/arm/mach-orion5x/board-dt.c
  *
  * Flattened Device Tree board initialization
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c
index b7b0f52f4c0a..596601367989 100644
--- a/arch/arm/mach-orion5x/board-rd88f5182.c
+++ b/arch/arm/mach-orion5x/board-rd88f5182.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/rd88f5182-setup.c
  *
  * Marvell Orion-NAS Reference Design Setup
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/bridge-regs.h b/arch/arm/mach-orion5x/bridge-regs.h
index 305598eaaee1..fe85bc5b131f 100644
--- a/arch/arm/mach-orion5x/bridge-regs.h
+++ b/arch/arm/mach-orion5x/bridge-regs.h
@@ -1,10 +1,5 @@
-/*
- * Orion CPU Bridge Registers
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Orion CPU Bridge Registers */
 
 #ifndef __ASM_ARCH_BRIDGE_REGS_H
 #define __ASM_ARCH_BRIDGE_REGS_H
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 7bcb41137bbf..2e711b7252c6 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/common.c
  *
  * Core functions for Marvell Orion 5x SoCs
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 39eae10ac8de..fe1a4cef1ba2 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/db88f5281-setup.c
  *
  * Marvell Orion-2 Development Board Setup
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 1ae775d02d90..e17727e53cb4 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/irq.c
  *
  * Core IRQ functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/irqs.h b/arch/arm/mach-orion5x/irqs.h
index 506c8e0b30c4..a70c47cfa6bc 100644
--- a/arch/arm/mach-orion5x/irqs.h
+++ b/arch/arm/mach-orion5x/irqs.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * IRQ definitions for Orion SoC
  *
  *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- *  This file is licensed under the terms of the GNU General Public
- *  License version 2. This program is licensed "as is" without any
- *  warranty of any kind, whether express or implied.
  */
 
 #ifndef __ASM_ARCH_IRQS_H
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 83d43cff4bd7..acba06618080 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/kurobox_pro-setup.c
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 47ba6e0502f5..af07f617465f 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/ls_hgl-setup.c
  *
  * Maintainer: Zhu Qingsen <zhuqs@cn.fujitsu.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 19ef18594415..b9855dce6ba0 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/mpp.c
  *
  * MPP functions for Marvell Orion 5x SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index bf6be4cfd238..695cc683cd83 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/net2big-setup.c
  *
  * LaCie 2Big Network NAS setup
  *
  * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
@@ -432,4 +429,3 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
 	.fixup		= tag_fixup_mem32,
 	.restart	= orion5x_restart,
 MACHINE_END
-
diff --git a/arch/arm/mach-orion5x/orion5x.h b/arch/arm/mach-orion5x/orion5x.h
index 2b66120fba86..26f1ccb8cb28 100644
--- a/arch/arm/mach-orion5x/orion5x.h
+++ b/arch/arm/mach-orion5x/orion5x.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Generic definitions of Orion SoC flavors:
  *  Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __ASM_ARCH_ORION5X_H
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 92e938bba20d..997fe39a86da 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/pci.c
  *
  * PCI and PCIe functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index c65ab7db36ad..432fc8357d9e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
  *
  * Marvell Orion-VoIP FXO Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 76b8138d9d79..d4b1a9c3cd36 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
  *
  * Marvell Orion-VoIP GE Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index fe3e67c81fb8..6ffcfc6445e2 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/rd88f5182-setup.c
  *
  * Marvell Orion-NAS Reference Design Setup
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 5f388a1ed1e4..93f74fd6b4da 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c
  *
  * Marvell Orion-1-90 AP GE Reference Design Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index a39764faf2a0..af810e7ccd79 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-orion5x/ts78xx-setup.c
  *
  * Maintainer: Alexander Clouter <alex@digriz.org.uk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 83589a28a491..e5f327054dd3 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -1,10 +1,5 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// arch/arm/mach-orion5x/wnr854t-setup.c
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index cea08d4a2597..e6a2da6662df 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -1,10 +1,5 @@
-/*
- * arch/arm/mach-orion5x/wrt350n-v2-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// arch/arm/mach-orion5x/wrt350n-v2-setup.c
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 08f8737aa8fd..bd948019b687 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Hardware definitions for the Toshiba eseries PDAs
  *
  * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
  */
 
 #include <linux/clkdev.h>
@@ -139,7 +134,6 @@ static void __init __maybe_unused eseries_register_clks(void)
 
 static struct tc6387xb_platform_data e330_tc6387xb_info = {
 	.enable   = &eseries_tmio_enable,
-	.disable  = &eseries_tmio_disable,
 	.suspend  = &eseries_tmio_suspend,
 	.resume   = &eseries_tmio_resume,
 };
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 938310b708a0..ad32b9c0ebce 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -1,12 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * PXA27x standby mode
  *
  * Author: David Burrage
  *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2005 (c) MontaVista Software, Inc.
  */
 
 #include <linux/linkage.h>
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 87389d9456b9..30d781d80fe0 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -311,7 +311,7 @@ void __init rockchip_suspend_init(void)
 					     &match);
 	if (!match) {
 		pr_err("Failed to find PMU node\n");
-		return;
+		goto out_put;
 	}
 	pm_data = (struct rockchip_pm_data *) match->data;
 
@@ -320,9 +320,12 @@ void __init rockchip_suspend_init(void)
 
 		if (ret) {
 			pr_err("%s: matches init error %d\n", __func__, ret);
-			return;
+			goto out_put;
 		}
 	}
 
 	suspend_set_ops(pm_data->ops);
+
+out_put:
+	of_node_put(np);
 }
diff --git a/arch/arm/mach-s3c/Kconfig b/arch/arm/mach-s3c/Kconfig
index 54548c051402..a64143574546 100644
--- a/arch/arm/mach-s3c/Kconfig
+++ b/arch/arm/mach-s3c/Kconfig
@@ -43,12 +43,12 @@ config SAMSUNG_ATAGS
 	def_bool n
 	depends on ATAGS
 	help
-	   This option enables ATAGS based boot support code for
-	   Samsung platforms, including static platform devices, legacy
-	   clock, timer and interrupt initialization, etc.
+	  This option enables ATAGS based boot support code for
+	  Samsung platforms, including static platform devices, legacy
+	  clock, timer and interrupt initialization, etc.
 
-	   Platforms that support only DT based boot need not to select
-	   this option.
+	  Platforms that support only DT based boot need not to select
+	  this option.
 
 if SAMSUNG_ATAGS
 
@@ -102,7 +102,7 @@ config S3C_DEV_HSMMC3
 config S3C_DEV_HWMON
 	bool
 	help
-	    Compile in platform device definitions for HWMON
+	  Compile in platform device definitions for HWMON
 
 config S3C_DEV_I2C1
 	bool
@@ -194,7 +194,7 @@ config S3C64XX_DEV_SPI0
 config SAMSUNG_DEV_TS
 	bool
 	help
-	    Common in platform device definitions for touchscreen device
+	  Common in platform device definitions for touchscreen device
 
 config SAMSUNG_DEV_KEYPAD
 	bool
diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx
index 662c5aec2ea3..ba8f4f7101de 100644
--- a/arch/arm/mach-s3c/Kconfig.s3c24xx
+++ b/arch/arm/mach-s3c/Kconfig.s3c24xx
@@ -37,8 +37,6 @@ config PLAT_S3C24XX
 	help
 	  Base platform code for any Samsung S3C24XX device
 
-
-
 menu "Samsung S3C24XX SoCs Support"
 
 comment "S3C24XX SoCs"
@@ -293,7 +291,7 @@ config MACH_VR1000
 	help
 	  Say Y here if you are using the Thorcom VR1000 board.
 
-endif	# CPU_S3C2410
+endif # CPU_S3C2410
 
 config S3C2412_PM_SLEEP
 	bool
@@ -367,7 +365,7 @@ config MACH_VSTMS
 	help
 	  Say Y here if you are using an VSTMS board
 
-endif	# CPU_S3C2412
+endif # CPU_S3C2412
 
 if CPU_S3C2416
 
@@ -415,7 +413,7 @@ config MACH_S3C2416_DT
 	  Note: This is under development and not all peripherals can be supported
 	  with this machine file.
 
-endif	# CPU_S3C2416
+endif # CPU_S3C2416
 
 if CPU_S3C2440 || CPU_S3C2442
 
@@ -444,7 +442,7 @@ config S3C2440_PLL_16934400
 	default y if S3C24XX_PLL
 	help
 	  PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
-endif
+endif # CPU_S3C2440 || CPU_S3C2442
 
 if CPU_S3C2440
 
@@ -540,7 +538,7 @@ config SMDK2440_CPU2440
 	default y if ARCH_S3C2440
 	select S3C2440_XTAL_16934400
 
-endif	# CPU_S3C2440
+endif # CPU_S3C2440
 
 if CPU_S3C2442
 
@@ -559,7 +557,7 @@ config MACH_NEO1973_GTA02
 	select POWER_SUPPLY
 	select S3C_DEV_USB_HOST
 	help
-	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
+	  Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
 
 config MACH_RX1950
 	bool "HP iPAQ rx1950"
@@ -570,9 +568,9 @@ config MACH_RX1950
 	select S3C2440_XTAL_16934400
 	select S3C_DEV_NAND
 	help
-	   Say Y here if you're using HP iPAQ rx1950
+	  Say Y here if you're using HP iPAQ rx1950
 
-endif	# CPU_S3C2442
+endif # CPU_S3C2442
 
 if CPU_S3C2443 || CPU_S3C2416
 
@@ -581,7 +579,7 @@ config S3C2443_SETUP_SPI
 	help
 	  Common setup code for SPI GPIO configurations
 
-endif	# CPU_S3C2443 || CPU_S3C2416
+endif # CPU_S3C2443 || CPU_S3C2416
 
 if CPU_S3C2443
 
@@ -594,13 +592,13 @@ config MACH_SMDK2443
 	help
 	  Say Y here if you are using an SMDK2443
 
-endif	# CPU_S3C2443
+endif # CPU_S3C2443
 
 config PM_H1940
 	bool
 	help
 	  Internal node for H1940 and related PM
 
-endmenu	# Samsung S3C24XX SoCs Support
+endmenu # "Samsung S3C24XX SoCs Support"
 
-endif	# ARCH_S3C24XX
+endif # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c/Kconfig.s3c64xx b/arch/arm/mach-s3c/Kconfig.s3c64xx
index 2b27bff4d928..bfc222f5bcd9 100644
--- a/arch/arm/mach-s3c/Kconfig.s3c64xx
+++ b/arch/arm/mach-s3c/Kconfig.s3c64xx
@@ -104,7 +104,7 @@ config S3C64XX_SETUP_SDHCI_GPIO
 config S3C64XX_SETUP_SPI
 	bool
 	help
-	 Common setup code for SPI GPIO configurations
+	  Common setup code for SPI GPIO configurations
 
 config S3C64XX_SETUP_USB_PHY
 	bool
@@ -114,7 +114,7 @@ config S3C64XX_SETUP_USB_PHY
 # S36400 Macchine support
 
 config MACH_SMDK6400
-       bool "SMDK6400"
+	bool "SMDK6400"
 	depends on ATAGS
 	select CPU_S3C6400
 	select S3C64XX_SETUP_SDHCI
@@ -205,7 +205,7 @@ config SMDK6410_SD_CH0
 	bool "Use channel 0 only"
 	depends on MACH_SMDK6410
 	help
-          Select CON7 (channel 0) as the MMC/SD slot, as
+	  Select CON7 (channel 0) as the MMC/SD slot, as
 	  at least some SMDK6410 boards come with the
 	  resistors fitted so that the card detects for
 	  channels 0 and 1 are the same.
@@ -214,7 +214,7 @@ config SMDK6410_SD_CH1
 	bool "Use channel 1 only"
 	depends on MACH_SMDK6410
 	help
-          Select CON6 (channel 1) as the MMC/SD slot, as
+	  Select CON6 (channel 1) as the MMC/SD slot, as
 	  at least some SMDK6410 boards come with the
 	  resistors fitted so that the card detects for
 	  channels 0 and 1 are the same.
@@ -260,7 +260,7 @@ config MACH_NCP
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_I2C1
 	help
-          Machine support for the Samsung NCP
+	  Machine support for the Samsung NCP
 
 config MACH_HMT
 	bool "Airgoo HMT"
@@ -292,21 +292,21 @@ config MACH_SMARTQ
 	select SAMSUNG_DEV_PWM
 	select SAMSUNG_DEV_TS
 	help
-	    Shared machine support for SmartQ 5/7
+	  Shared machine support for SmartQ 5/7
 
 config MACH_SMARTQ5
 	bool "SmartQ 5"
 	depends on ATAGS
 	select MACH_SMARTQ
 	help
-	    Machine support for the SmartQ 5
+	  Machine support for the SmartQ 5
 
 config MACH_SMARTQ7
 	bool "SmartQ 7"
 	depends on ATAGS
 	select MACH_SMARTQ
 	help
-	    Machine support for the SmartQ 7
+	  Machine support for the SmartQ 7
 
 config MACH_WLF_CRAGG_6410
 	bool "Wolfson Cragganmore 6410"
diff --git a/arch/arm/mach-s3c/mach-mini2440.c b/arch/arm/mach-s3c/mach-mini2440.c
index 131015cc0c34..a6d17ffcdba1 100644
--- a/arch/arm/mach-s3c/mach-mini2440.c
+++ b/arch/arm/mach-s3c/mach-mini2440.c
@@ -624,7 +624,7 @@ static char mini2440_features_str[12] __initdata = "0tb";
 static int __init mini2440_features_setup(char *str)
 {
 	if (str)
-		strlcpy(mini2440_features_str, str,
+		strscpy(mini2440_features_str, str,
 			sizeof(mini2440_features_str));
 	return 1;
 }
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index 8ec2b92dca19..43b7996ab754 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * spear machine family generic header file
  *
  * Copyright (C) 2009-2012 ST Microelectronics
  * Rajeev Kumar <rajeev-dlh.kumar@st.com>
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_GENERIC_H
diff --git a/arch/arm/mach-spear/misc_regs.h b/arch/arm/mach-spear/misc_regs.h
index 53cd74301f58..72aa801a3a89 100644
--- a/arch/arm/mach-spear/misc_regs.h
+++ b/arch/arm/mach-spear/misc_regs.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Miscellaneous registers definitions for SPEAr3xx machine family
  *
  * Copyright (C) 2009 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_MISC_REGS_H
diff --git a/arch/arm/mach-spear/pl080.c b/arch/arm/mach-spear/pl080.c
index 38b479f413dc..d6b8627d2544 100644
--- a/arch/arm/mach-spear/pl080.c
+++ b/arch/arm/mach-spear/pl080.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/plat-spear/pl080.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/amba/pl08x.h>
diff --git a/arch/arm/mach-spear/pl080.h b/arch/arm/mach-spear/pl080.h
index 608dec6725ae..3732d940dbfb 100644
--- a/arch/arm/mach-spear/pl080.h
+++ b/arch/arm/mach-spear/pl080.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * arch/arm/plat-spear/include/plat/pl080.h
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __PLAT_PL080_H
diff --git a/arch/arm/mach-spear/restart.c b/arch/arm/mach-spear/restart.c
index 43417d0db6d9..76fb16cc8132 100644
--- a/arch/arm/mach-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/plat-spear/restart.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2009 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/io.h>
 #include <linux/amba/sp810.h>
diff --git a/arch/arm/mach-spear/spear.h b/arch/arm/mach-spear/spear.h
index 5ed841ccf8a3..432efd407c76 100644
--- a/arch/arm/mach-spear/spear.h
+++ b/arch/arm/mach-spear/spear.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * SPEAr3xx/6xx Machine family specific definition
  *
  * Copyright (C) 2009,2012 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar@st.com>
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __MACH_SPEAR_H
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 549ab2be1b74..89d388388e02 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear13xx/spear1310.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr1310: " fmt
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index a212af90c0bc..a391f154eff9 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear13xx/spear1340.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr1340: " fmt
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 9d4bdce2e865..ac5b76bbeab5 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear13xx/spear13xx.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr13xx: " fmt
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c
index 1f2a6bbcf096..1d6b6e10fcf6 100644
--- a/arch/arm/mach-spear/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear3xx/spear300.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c
index f0fc140a59cf..da4643b9f3bb 100644
--- a/arch/arm/mach-spear/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear3xx/spear310.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr310: " fmt
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
index cb464ae7c08a..12aa82b987ac 100644
--- a/arch/arm/mach-spear/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear3xx/spear320.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr320: " fmt
diff --git a/arch/arm/mach-spear/spear3xx.c b/arch/arm/mach-spear/spear3xx.c
index fab3d6df69ff..2ba406e92c41 100644
--- a/arch/arm/mach-spear/spear3xx.c
+++ b/arch/arm/mach-spear/spear3xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear3xx/spear3xx.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2009-2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "SPEAr3xx: " fmt
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index d061080b191f..58183493e06d 100644
--- a/arch/arm/mach-spear/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear6xx/spear6xx.c
  *
@@ -7,10 +8,6 @@
  * Rajeev Kumar<rajeev-dlh.kumar@st.com>
  *
  * Copyright 2012 Stefan Roese <sr@denx.de>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/amba/pl08x.h>
diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c
index d1fdb6066f7b..6baf952fa902 100644
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/plat-spear/time.c
  *
  * Copyright (C) 2010 ST Microelectronics
  * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/arch/arm/mach-versatile/spc.c b/arch/arm/mach-versatile/spc.c
index 6e6985e756af..5e44170e1a9a 100644
--- a/arch/arm/mach-versatile/spc.c
+++ b/arch/arm/mach-versatile/spc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Versatile Express Serial Power Controller (SPC) support
  *
@@ -6,15 +7,6 @@
  * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
  *          Achin Gupta           <achin.gupta@arm.com>
  *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 5c1b7a7b9af6..25dbd84a1aaf 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
  *
  * Copyright (C) 2008 Marvell Semiconductor
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * References:
  * - Unified Layer 2 Cache for Feroceon CPU Cores,
  *   Document ID MV-S104858-00, Rev. A, October 23 2007.
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 88255bea65e4..b1e1aba602f7 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
  *
  * Copyright (C) 2008 Marvell Semiconductor
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * References:
  * - PJ1 CPU Core Datasheet,
  *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index a062e07516dd..46cccd6bf705 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -322,6 +322,10 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 		return 0;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return 0;
+
 	if (!(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_RETRY) {
 			flags |= FAULT_FLAG_TRIED;
diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
index fb9f3eb6bf48..9edb0c5eb369 100644
--- a/arch/arm/mm/proc-v7-bugs.c
+++ b/arch/arm/mm/proc-v7-bugs.c
@@ -209,10 +209,10 @@ static int spectre_bhb_install_workaround(int method)
 			return SPECTRE_VULNERABLE;
 
 		spectre_bhb_method = method;
-	}
 
-	pr_info("CPU%u: Spectre BHB: using %s workaround\n",
-		smp_processor_id(), spectre_bhb_method_name(method));
+		pr_info("CPU%u: Spectre BHB: enabling %s workaround for all CPUs\n",
+			smp_processor_id(), spectre_bhb_method_name(method));
+	}
 
 	return SPECTRE_MITIGATED;
 }
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 9e457156ad4d..6a1c9fca5260 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -712,22 +712,6 @@ static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
 	}
 }
 
-/* ALU operation (32 bit)
- * dst = dst (op) src
- */
-static inline void emit_a32_alu_r(const s8 dst, const s8 src,
-				  struct jit_ctx *ctx, const bool is64,
-				  const bool hi, const u8 op) {
-	const s8 *tmp = bpf2a32[TMP_REG_1];
-	s8 rn, rd;
-
-	rn = arm_bpf_get_reg32(src, tmp[1], ctx);
-	rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
-	/* ALU operation */
-	emit_alu_r(rd, rn, is64, hi, op, ctx);
-	arm_bpf_put_reg32(dst, rd, ctx);
-}
-
 /* ALU operation (64 bit) */
 static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
 				  const s8 src[], struct jit_ctx *ctx,
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1652a9800ebe..9728103a13aa 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -49,6 +49,7 @@ config ARM64
 	select ARCH_HAS_ZONE_DMA_SET if EXPERT
 	select ARCH_HAVE_ELF_PROT
 	select ARCH_HAVE_NMI_SAFE_CMPXCHG
+	select ARCH_HAVE_TRACE_MMIO_ACCESS
 	select ARCH_INLINE_READ_LOCK if !PREEMPTION
 	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
 	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
@@ -174,7 +175,7 @@ config ARM64
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_CMPXCHG_DOUBLE
 	select HAVE_CMPXCHG_LOCAL
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS
 	select HAVE_DYNAMIC_FTRACE
@@ -201,6 +202,7 @@ config ARM64
 	select HAVE_FUNCTION_ARG_ACCESS_API
 	select MMU_GATHER_RCU_TABLE_FREE
 	select HAVE_RSEQ
+	select HAVE_RUST
 	select HAVE_STACKPROTECTOR
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4e6d635a1731..88ddc2e5b152 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -63,6 +63,15 @@ config ARCH_BCM_IPROC
 	help
 	  This enables support for Broadcom iProc based SoCs
 
+config ARCH_BCMBCA
+	bool "Broadcom Broadband SoC"
+	help
+	  Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
+	  BCA chipset.
+
+	  This enables support for Broadcom BCA ARM-based broadband chipsets,
+	  including the DSL, PON and Wireless family of chips.
+
 config ARCH_BERLIN
 	bool "Marvell Berlin SoC Family"
 	select DW_APB_ICTL
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index f17cc89f472d..8233582f6288 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -58,7 +58,7 @@ ov5640_ep: endpoint {
 
 	wifi_pwrseq: wifi-pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
 	};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 997a19372683..e6d5bc0f7a61 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -56,7 +56,7 @@ led-2 {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -355,7 +355,7 @@ &uart1 {
 
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_dldo2>;
 		vddio-supply = <&reg_dldo4>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index e47ff06a6fa9..0af6dcdf7515 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -43,7 +43,7 @@ led {
 
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
 	};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index c519d9fa6967..e2f963332925 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -71,7 +71,7 @@ reg_usb1_vbus: usb1-vbus {
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 	};
 };
@@ -369,7 +369,7 @@ &uart1 {
 	bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		max-speed = <1500000>;
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		vbat-supply = <&reg_dldo2>;
 		vddio-supply = <&reg_dldo4>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 63571df24da4..620cb3ef5f6c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -35,10 +35,10 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		lid_switch {
+		lid-switch {
 			label = "Lid Switch";
 			gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
 			linux,input-type = <EV_SW>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index de77c87481fd..77b5349f6087 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -4,6 +4,7 @@
 //    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -660,7 +661,7 @@ ohci1: usb@1c1b400 {
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun50i-a64-ccu";
 			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -673,7 +674,8 @@ pio: pinctrl@1c20800 {
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
@@ -1226,7 +1228,7 @@ hdmi: hdmi@1ee0000 {
 			reg-io-width = <1>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
-				 <&ccu CLK_HDMI>, <&rtc 0>;
+				 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
 			clock-names = "iahb", "isfr", "tmds", "cec";
 			resets = <&ccu RST_BUS_HDMI1>;
 			reset-names = "ctrl";
@@ -1287,7 +1289,7 @@ r_intc: interrupt-controller@1f00c00 {
 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun50i-a64-r-ccu";
 			reg = <0x01f01400 0x100>;
-			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
 				 <&ccu CLK_PLL_PERIPH0>;
 			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
index 55b369534a08..a3e040da38a0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
@@ -52,10 +52,10 @@ led-2 {
 		};
 	};
 
-	r-gpio-keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		reset {
+		key-reset {
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 1010c1b22d2e..b5c1ff19b4c4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -54,10 +54,10 @@ led-1 {
 		};
 	};
 
-	r-gpio-keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		key-sw4 {
 			label = "sw4";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index 74e0444af19b..d7f8bad6bb98 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -48,10 +48,10 @@ led-1 {
 		};
 	};
 
-	r-gpio-keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
-		sw4 {
+		key-sw4 {
 			label = "sw4";
 			linux,code = <BTN_0>;
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index c45d7b7fb39a..6fc65e8db220 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -86,7 +86,7 @@ reg_vcc_wifi_io: vcc-wifi-io {
 
 	wifi_pwrseq: wifi-pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
 		post-power-on-delay-ms = <200>;
@@ -314,7 +314,7 @@ &uart1 {
 
 	bluetooth {
 		compatible = "brcm,bcm4345c5";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
 		host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
index e8770858b5d0..fb31dcb1cb6d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
@@ -13,7 +13,7 @@ aliases {
 
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
 		post-power-on-delay-ms = <200>;
@@ -64,7 +64,7 @@ &uart1 {
 
 	bluetooth {
 		compatible = "brcm,bcm4345c5";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "lpo";
 		device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
 		host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
index edb71e4a0304..4903d6358112 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
@@ -78,7 +78,7 @@ spdif_out: spdif-out {
 
 	wifi_pwrseq: wifi-pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		clocks = <&rtc 1>;
+		clocks = <&rtc CLK_OSC32K_FANOUT>;
 		clock-names = "ext_clock";
 		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
 	};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index fbe94abbb1f9..5a28303d3d4c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/sun50i-h6-ccu.h>
 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/clock/sun6i-rtc.h>
 #include <dt-bindings/clock/sun8i-de2.h>
 #include <dt-bindings/clock/sun8i-tcon-top.h>
 #include <dt-bindings/reset/sun50i-h6-ccu.h>
@@ -237,7 +238,7 @@ ve_sram: sram-section@0 {
 		ccu: clock@3001000 {
 			compatible = "allwinner,sun50i-h6-ccu";
 			reg = <0x03001000 0x1000>;
-			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
 			clock-names = "hosc", "losc", "iosc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -317,7 +318,7 @@ pio: pinctrl@300b000 {
 				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
+			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
@@ -725,7 +726,7 @@ dwc3: usb@5200000 {
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_XHCI>,
 				 <&ccu CLK_BUS_XHCI>,
-				 <&rtc 0>;
+				 <&rtc CLK_OSC32K>;
 			clock-names = "ref", "bus_early", "suspend";
 			resets = <&ccu RST_BUS_XHCI>;
 			/*
@@ -931,7 +932,7 @@ rtc: rtc@7000000 {
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-h6-r-ccu";
 			reg = <0x07010000 0x400>;
-			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
 				 <&ccu CLK_PLL_PERIPH0>;
 			clock-names = "hosc", "losc", "iosc", "pll-periph";
 			#clock-cells = <1>;
@@ -960,7 +961,8 @@ r_pio: pinctrl@7022000 {
 			interrupt-parent = <&r_intc>;
 			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
+			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
+				 <&rtc CLK_OSC32K>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
index c290d1ce2b03..02bff65e5fd6 100644
--- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
@@ -20,8 +20,8 @@ chosen {
 	};
 
 	psci {
-		compatible   = "arm,psci-0.2";
-		method       = "smc";
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 };
 
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
index e0926f6bb7c3..07dab1f1e3c8 100644
--- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
@@ -20,8 +20,8 @@ chosen {
 	};
 
 	psci {
-		compatible   = "arm,psci-0.2";
-		method       = "smc";
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 };
 
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 3f5254eeb47b..04f797b5a012 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1535,7 +1535,7 @@ aobus: bus@ff800000 {
 
 			sysctrl_AO: sys-ctrl@0 {
 				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
-				reg =  <0x0 0x0 0x0 0x100>;
+				reg = <0x0 0x0 0x0 0x100>;
 
 				clkc_AO: clock-controller {
 					compatible = "amlogic,meson-axg-aoclkc";
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts
index 6c7bfacbad78..1fa6e75abd21 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts
@@ -20,10 +20,16 @@ aliases {
 		rtc1 = &vrtc;
 	};
 
+	gpio_fan: gpio-fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+		/* Using Dummy Speed */
+		gpio-fan,speed-map = <0 0>, <1 1>;
+		#cooling-cells = <2>;
+	};
+
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
 		power-button {
@@ -96,6 +102,23 @@ &clkc_audio {
 	status = "okay";
 };
 
+&cpu_thermal {
+	trips {
+		cpu_active: cpu-active {
+			temperature = <70000>; /* millicelsius */
+			hysteresis = <2000>; /* millicelsius */
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map {
+			trip = <&cpu_active>;
+			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
 &frddr_a {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts
index 707daf92787b..afe375fa83ca 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts
@@ -21,8 +21,6 @@ aliases {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
 		power-button {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index aa14ea017a61..023a52005494 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -450,7 +450,7 @@ aobus: bus@c8100000 {
 
 			sysctrl_AO: sys-ctrl@0 {
 				compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
-				reg =  <0x0 0x0 0x0 0x100>;
+				reg = <0x0 0x0 0x0 0x100>;
 
 				clkc_AO: clock-controller {
 					compatible = "amlogic,meson-gx-aoclkc";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts
index e8394a8269ee..6d8cc00fedc7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts
@@ -26,8 +26,6 @@ status {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <20>;
 
 		button-reset {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
index f887bfb445fd..63137ce3cb9d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -42,11 +42,9 @@ led-blue {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
index 6eae692792ec..505ffcd8eb76 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
@@ -37,11 +37,9 @@ led-ethernet {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
index c529b6c860a4..a4fa186f0458 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts
@@ -30,11 +30,9 @@ button-function {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index b2ab05c22090..c1470416faad 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -30,11 +30,9 @@ button-function {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts
index 4b0ff707e21b..595b49085074 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts
@@ -16,11 +16,9 @@ / {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <20>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
index fcb304c5a40f..6831137c5c10 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
@@ -216,7 +216,7 @@ &uart_A {
 
 	bluetooth {
 		compatible = "realtek,rtl8822cs-bt";
-		enable-gpios  = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
 		host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
        };
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
index ebebf344b715..f5b3424c0f61 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
@@ -35,11 +35,9 @@ button-function {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
index ea9f234d1fc7..b8ef3bd8b840 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
@@ -41,11 +41,9 @@ button-function {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index 8edbfe040805..d4858afa0e9c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -30,11 +30,9 @@ button-function {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
-		button@0 {
+		button {
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts
index 1e7f77f9b533..f8c40340b9c5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts
@@ -45,8 +45,6 @@ button-update {
 
 	gpio-keys-polled {
 		compatible = "gpio-keys-polled";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <100>;
 
 		button-power {
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..ad50cba42d19 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -127,6 +127,12 @@ uart_B: serial@7a000 {
 				clocks = <&xtal>, <&xtal>, <&xtal>;
 				clock-names = "xtal", "pclk", "baud";
 			};
+
+			reset: reset-controller@2000 {
+				compatible = "amlogic,meson-s4-reset";
+				reg = <0x0 0x2000 0x0 0x98>;
+				#reset-cells = <1>;
+			};
 		};
 	};
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
index a5d79f2f7c19..603337ca5608 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
@@ -48,7 +48,7 @@ emmc_pwrseq: emmc-pwrseq {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		key1 {
+		key-1 {
 			label = "A";
 			linux,code = <BTN_0>;
 			gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
@@ -56,7 +56,7 @@ key1 {
 			interrupts = <34 IRQ_TYPE_EDGE_BOTH>;
 		};
 
-		key2 {
+		key-2 {
 			label = "B";
 			linux,code = <BTN_1>;
 			gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
@@ -64,7 +64,7 @@ key2 {
 			interrupts = <35 IRQ_TYPE_EDGE_BOTH>;
 		};
 
-		key3 {
+		key-3 {
 			label = "C";
 			linux,code = <BTN_2>;
 			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
@@ -72,7 +72,7 @@ key3 {
 			interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
 		};
 
-		mic_mute {
+		key-mic-mute {
 			label = "MicMute";
 			linux,code = <SW_MUTE_DEVICE>;
 			linux,input-type = <EV_SW>;
@@ -81,7 +81,7 @@ mic_mute {
 			interrupts = <99 IRQ_TYPE_EDGE_BOTH>;
 		};
 
-		power_key {
+		key-power {
 			label = "PowerKey";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts
index 217d7728b63a..049e7a5edca7 100644
--- a/arch/arm64/boot/dts/apm/apm-merlin.dts
+++ b/arch/arm64/boot/dts/apm/apm-merlin.dts
@@ -22,7 +22,7 @@ memory {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		button@1 {
+		button {
 			label = "POWER";
 			linux,code = <116>;
 			linux,input-type = <0x1>;
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index e927811ade28..efac50aeca64 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -22,7 +22,7 @@ memory {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		button@1 {
+		button {
 			label = "POWER";
 			linux,code = <116>;
 			linux,input-type = <0x1>;
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index a83c82c50e29..251f2ca0a649 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -601,7 +601,7 @@ serial0: serial@10600000 {
 		usb0: dwusb@19000000 {
 			status = "disabled";
 			compatible = "snps,dwc3";
-			reg =  <0x0 0x19000000 0x0 0x100000>;
+			reg = <0x0 0x19000000 0x0 0x100000>;
 			interrupts = <0x0 0x5d 0x4>;
 			dma-coherent;
 			dr_mode = "host";
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 0f37e77f5459..d49ea382154d 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -927,7 +927,7 @@ sata3: sata@1a800000 {
 		usb0: dwusb@19000000 {
 			status = "disabled";
 			compatible = "snps,dwc3";
-			reg =  <0x0 0x19000000 0x0 0x100000>;
+			reg = <0x0 0x19000000 0x0 0x100000>;
 			interrupts = <0x0 0x89 0x4>;
 			dma-coherent;
 			dr_mode = "host";
@@ -936,7 +936,7 @@ usb0: dwusb@19000000 {
 		usb1: dwusb@19800000 {
 			status = "disabled";
 			compatible = "snps,dwc3";
-			reg =  <0x0 0x19800000 0x0 0x100000>;
+			reg = <0x0 0x19800000 0x0 0x100000>;
 			interrupts = <0x0 0x8a 0x4>;
 			dma-coherent;
 			dr_mode = "host";
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index a496e39e6204..5f6f30c801a7 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -186,7 +186,7 @@ smmu: iommu@2b400000 {
 	};
 
 	panel {
-		compatible = "arm,rtsm-display", "panel-dpi";
+		compatible = "arm,rtsm-display";
 		port {
 			panel_in: endpoint {
 				remote-endpoint = <&clcd_pads>;
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 065381c1cbf5..8d0d45d168d1 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -581,36 +581,36 @@ cti_sys0: cti@20020000 { /* sys_cti_0 */
 
 		trig-conns@0 {
 			reg = <0>;
-			arm,trig-in-sigs=<2 3>;
-			arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
-			arm,trig-out-sigs=<0 1>;
-			arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+			arm,trig-in-sigs = <2 3>;
+			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
+			arm,trig-out-sigs = <0 1>;
+			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
 			arm,cs-dev-assoc = <&etr_sys>;
 		};
 
 		trig-conns@1 {
 			reg = <1>;
-			arm,trig-in-sigs=<0 1>;
-			arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
-			arm,trig-out-sigs=<7 6>;
-			arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+			arm,trig-in-sigs = <0 1>;
+			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
+			arm,trig-out-sigs = <7 6>;
+			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
 			arm,cs-dev-assoc = <&etf_sys0>;
 		};
 
 		trig-conns@2 {
 			reg = <2>;
-			arm,trig-in-sigs=<4 5 6 7>;
-			arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW
+			arm,trig-in-sigs = <4 5 6 7>;
+			arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW
 					   STM_TOUT_HETE STM_ASYNCOUT>;
-			arm,trig-out-sigs=<4 5>;
-			arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>;
+			arm,trig-out-sigs = <4 5>;
+			arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>;
 			arm,cs-dev-assoc = <&stm_sys>;
 		};
 
 		trig-conns@3 {
 			reg = <3>;
-			arm,trig-out-sigs=<2 3>;
-			arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+			arm,trig-out-sigs = <2 3>;
+			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
 			arm,cs-dev-assoc = <&tpiu_sys>;
 		};
 	};
@@ -628,24 +628,24 @@ cti_sys1: cti@20110000 { /* sys_cti_1 */
 
 		trig-conns@0 {
 			reg = <0>;
-			arm,trig-in-sigs=<0>;
-			arm,trig-in-types=<GEN_INTREQ>;
-			arm,trig-out-sigs=<0>;
-			arm,trig-out-types=<GEN_HALTREQ>;
+			arm,trig-in-sigs = <0>;
+			arm,trig-in-types = <GEN_INTREQ>;
+			arm,trig-out-sigs = <0>;
+			arm,trig-out-types = <GEN_HALTREQ>;
 			arm,trig-conn-name = "sys_profiler";
 		};
 
 		trig-conns@1 {
 			reg = <1>;
-			arm,trig-out-sigs=<2 3>;
-			arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+			arm,trig-out-sigs = <2 3>;
+			arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
 			arm,trig-conn-name = "watchdog";
 		};
 
 		trig-conns@2 {
 			reg = <2>;
-			arm,trig-out-sigs=<1 6>;
-			arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+			arm,trig-out-sigs = <1 6>;
+			arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
 			arm,trig-conn-name = "g_counter";
 		};
 	};
diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
index 2e43f4531308..ba88d1596f6f 100644
--- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
@@ -96,24 +96,24 @@ cti_sys2: cti@20160000 { /* sys_cti_2 */
 
 		trig-conns@0 {
 			reg = <0>;
-			arm,trig-in-sigs=<0 1>;
-			arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
-			arm,trig-out-sigs=<0 1>;
-			arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+			arm,trig-in-sigs = <0 1>;
+			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
+			arm,trig-out-sigs = <0 1>;
+			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
 			arm,cs-dev-assoc = <&etf_sys1>;
 		};
 
 		trig-conns@1 {
 			reg = <1>;
-			arm,trig-in-sigs=<2 3 4>;
-			arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
+			arm,trig-in-sigs = <2 3 4>;
+			arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
 			arm,trig-conn-name = "ela_clus_0";
 		};
 
 		trig-conns@2 {
 			reg = <2>;
-			arm,trig-in-sigs=<5 6 7>;
-			arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
+			arm,trig-in-sigs = <5 6 7>;
+			arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
 			arm,trig-conn-name = "ela_clus_1";
 		};
 	};
diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi
index 4135d62e44a2..ec85cd2c733c 100644
--- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi
@@ -187,7 +187,6 @@ &gpu {
 &mailbox {
 	compatible = "arm,mhu-doorbell", "arm,primecell";
 	#mbox-cells = <2>;
-	mbox-name = "ARM-MHU";
 };
 
 &smmu_etr {
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index 5082fcd1fea5..e8584d3b698f 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
 			      bcm2837-rpi-zero-2-w.dtb
 
 subdir-y	+= bcm4908
+subdir-y	+= bcmbca
 subdir-y	+= northstar2
 subdir-y	+= stingray
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
index b63eefab48bd..064f7f549665 100644
--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
@@ -83,25 +83,25 @@ gpio-keys-polled {
 		compatible = "gpio-keys-polled";
 		poll-interval = <100>;
 
-		brightness {
+		key-brightness {
 			label = "LEDs";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		key-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
 		};
 
-		wifi {
+		key-wifi {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		key-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
index 169fbb7cfd34..04f8524b5335 100644
--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
@@ -18,25 +18,25 @@ gpio-keys-polled {
 		compatible = "gpio-keys-polled";
 		poll-interval = <100>;
 
-		wifi {
+		key-wifi {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
 			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
 		};
 
-		wps {
+		key-wps {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
 		};
 
-		restart {
+		key-restart {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
 		};
 
-		brightness {
+		key-brightness {
 			label = "LEDs";
 			linux,code = <KEY_BRIGHTNESS_ZERO>;
 			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
new file mode 100644
index 000000000000..e16485d503fd
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
+				bcm963158.dtb \
+				bcm96858.dtb \
+				bcm963146.dtb \
+				bcm96856.dtb
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
new file mode 100644
index 000000000000..3d016c2ce675
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "brcm,bcm4912", "brcm,bcmbca";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_2: cpu@2 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_3: cpu@3 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>,
+			<&B53_2>, <&B53_3>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
new file mode 100644
index 000000000000..04de96bd0a03
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "brcm,bcm63146", "brcm,bcmbca";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
new file mode 100644
index 000000000000..13629702f70b
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "brcm,bcm63158", "brcm,bcmbca";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_2: cpu@2 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_3: cpu@3 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>,
+			<&B53_2>, <&B53_3>;
+	};
+
+	clocks: clocks {
+		periph_clk: periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+		uart_clk: uart-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_clk>;
+			clock-div = <4>;
+			clock-mult = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			reg = <0x1000 0x1000>,
+				<0x2000 0x2000>,
+				<0x4000 0x2000>,
+				<0x6000 0x2000>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x800000>;
+
+		uart0: serial@12000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x12000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&uart_clk>, <&uart_clk>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
new file mode 100644
index 000000000000..0bce6497219f
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "brcm,bcm6856", "brcm,bcmbca";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>;
+	};
+
+	clocks: clocks {
+		periph_clk:periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>, /* GICD */
+				<0x2000 0x2000>, /* GICC */
+				<0x4000 0x2000>, /* GICH */
+				<0x6000 0x2000>; /* GICV */
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x800000>;
+
+		uart0: serial@640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x640 0x18>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+			clock-names = "refclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
new file mode 100644
index 000000000000..29a880c6c858
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "brcm,bcm6858", "brcm,bcmbca";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		B53_0: cpu@0 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_1: cpu@1 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_2: cpu@2 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+
+		B53_3: cpu@3 {
+			compatible = "brcm,brahma-b53";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&L2_0>;
+			enable-method = "psci";
+		};
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu: pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&B53_0>, <&B53_1>,
+			<&B53_2>, <&B53_3>;
+	};
+
+	clocks: clocks {
+		periph_clk:periph-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	axi@81000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x81000000 0x8000>;
+
+		gic: interrupt-controller@1000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1000 0x1000>, /* GICD */
+				<0x2000 0x2000>, /* GICC */
+				<0x4000 0x2000>, /* GICH */
+				<0x6000 0x2000>; /* GICV */
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	bus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x62000>;
+
+		uart0: serial@640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x640 0x18>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+			clock-names = "refclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
new file mode 100644
index 000000000000..a3623e6f6919
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm4912.dtsi"
+
+/ {
+	model = "Broadcom BCM94912 Reference Board";
+	compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
new file mode 100644
index 000000000000..e39f1e6d4774
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63146.dtsi"
+
+/ {
+	model = "Broadcom BCM963146 Reference Board";
+	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
new file mode 100644
index 000000000000..eba07e0b1ca6
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63158.dtsi"
+
+/ {
+	model = "Broadcom BCM963158 Reference Board";
+	compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
new file mode 100644
index 000000000000..032aeb75c983
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6856.dtsi"
+
+/ {
+	model = "Broadcom BCM96856 Reference Board";
+	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
new file mode 100644
index 000000000000..0cbf582f5d54
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6858.dtsi"
+
+/ {
+	model = "Broadcom BCM96858 Reference Board";
+	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 09d4aa8ae1d6..8f8c25e51194 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -567,7 +567,7 @@ enet: ethernet@340000{
 			reg-names = "amac_base";
 			dma-coherent;
 			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
-			status= "disabled";
+			status = "disabled";
 		};
 
 		nand: nand@360000 {
diff --git a/arch/arm64/boot/dts/exynos/exynos-pinctrl.h b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h
new file mode 100644
index 000000000000..7dd94a9b3652
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Samsung Exynos DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
+
+#define EXYNOS_PIN_PULL_NONE		0
+#define EXYNOS_PIN_PULL_DOWN		1
+#define EXYNOS_PIN_PULL_UP		3
+
+/* Pin function in power down mode */
+#define EXYNOS_PIN_PDN_OUT0		0
+#define EXYNOS_PIN_PDN_OUT1		1
+#define EXYNOS_PIN_PDN_INPUT		2
+#define EXYNOS_PIN_PDN_PREV		3
+
+/*
+ * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
+ * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
+ */
+#define EXYNOS5420_PIN_DRV_LV1		0
+#define EXYNOS5420_PIN_DRV_LV2		1
+#define EXYNOS5420_PIN_DRV_LV3		2
+#define EXYNOS5420_PIN_DRV_LV4		3
+
+/* Drive strengths for Exynos5433 */
+#define EXYNOS5433_PIN_DRV_FAST_SR1	0
+#define EXYNOS5433_PIN_DRV_FAST_SR2	1
+#define EXYNOS5433_PIN_DRV_FAST_SR3	2
+#define EXYNOS5433_PIN_DRV_FAST_SR4	3
+#define EXYNOS5433_PIN_DRV_FAST_SR5	4
+#define EXYNOS5433_PIN_DRV_FAST_SR6	5
+#define EXYNOS5433_PIN_DRV_SLOW_SR1	8
+#define EXYNOS5433_PIN_DRV_SLOW_SR2	9
+#define EXYNOS5433_PIN_DRV_SLOW_SR3	0xa
+#define EXYNOS5433_PIN_DRV_SLOW_SR4	0xb
+#define EXYNOS5433_PIN_DRV_SLOW_SR5	0xc
+#define EXYNOS5433_PIN_DRV_SLOW_SR6	0xf
+
+/* Drive strengths for Exynos7 (except FSYS1) */
+#define EXYNOS7_PIN_DRV_LV1		0
+#define EXYNOS7_PIN_DRV_LV2		2
+#define EXYNOS7_PIN_DRV_LV3		1
+#define EXYNOS7_PIN_DRV_LV4		3
+
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1	0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2	4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3	2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4	6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5	1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6	5
+
+/* Drive strengths for Exynos850 GPIO_HSI block */
+#define EXYNOS850_HSI_PIN_DRV_LV1	0	/* 1x   */
+#define EXYNOS850_HSI_PIN_DRV_LV1_5	1	/* 1.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV2	2	/* 2x   */
+#define EXYNOS850_HSI_PIN_DRV_LV2_5	3	/* 2.5x */
+#define EXYNOS850_HSI_PIN_DRV_LV3	4	/* 3x   */
+#define EXYNOS850_HSI_PIN_DRV_LV4	5	/* 4x   */
+
+#define EXYNOS_PIN_FUNC_INPUT		0
+#define EXYNOS_PIN_FUNC_OUTPUT		1
+#define EXYNOS_PIN_FUNC_2		2
+#define EXYNOS_PIN_FUNC_3		3
+#define EXYNOS_PIN_FUNC_4		4
+#define EXYNOS_PIN_FUNC_5		5
+#define EXYNOS_PIN_FUNC_6		6
+#define EXYNOS_PIN_FUNC_EINT		0xf
+#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
index 4b46af3e164d..681553577ebc 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * tree nodes are listed in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 #define PIN(_pin, _func, _pull, _drv)					\
 	pin- ## _pin {							\
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 75b548e495a0..bd6a354b9cb5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1820,7 +1820,7 @@ usbhost_dwc3: usb@15a00000 {
 			};
 		};
 
-		mshc_0: mshc@15540000 {
+		mshc_0: mmc@15540000 {
 			compatible = "samsung,exynos7-dw-mshc-smu";
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
@@ -1833,7 +1833,7 @@ mshc_0: mshc@15540000 {
 			status = "disabled";
 		};
 
-		mshc_1: mshc@15550000 {
+		mshc_1: mmc@15550000 {
 			compatible = "samsung,exynos7-dw-mshc-smu";
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
@@ -1846,7 +1846,7 @@ mshc_1: mshc@15550000 {
 			status = "disabled";
 		};
 
-		mshc_2: mshc@15560000 {
+		mshc_2: mmc@15560000 {
 			compatible = "samsung,exynos7-dw-mshc-smu";
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 0895e818d3c1..e38c59cf18dc 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -357,7 +357,7 @@ &pinctrl_alive {
 	pmic_irq: pmic-irq-pins {
 		samsung,pins = "gpa0-2";
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 };
 
@@ -397,14 +397,14 @@ usb30_vbus_en: usb30-vbus-en-pins {
 		samsung,pins = "gph1-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	usb3drd_boost_en: usb3drd-boost-en-pins {
 		samsung,pins = "gpf4-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index be9b971f3697..ee9c24a226f3 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -9,7 +9,7 @@
  * device tree nodes in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_alive {
 	gpa0: gpa0-gpio-bank {
@@ -188,161 +188,161 @@ hs_i2c10_bus: hs-i2c10-bus-pins {
 		samsung,pins = "gpb0-1", "gpb0-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c11_bus: hs-i2c11-bus-pins {
 		samsung,pins = "gpb0-3", "gpb0-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c2_bus: hs-i2c2-bus-pins {
 		samsung,pins = "gpd0-3", "gpd0-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart0_data: uart0-data-pins {
 		samsung,pins = "gpd0-0", "gpd0-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart0_fctl: uart0-fctl-pins {
 		samsung,pins = "gpd0-2", "gpd0-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart2_data: uart2-data-pins {
 		samsung,pins = "gpd1-4", "gpd1-5";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c3_bus: hs-i2c3-bus-pins {
 		samsung,pins = "gpd1-3", "gpd1-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart1_data: uart1-data-pins {
 		samsung,pins = "gpd1-0", "gpd1-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart1_fctl: uart1-fctl-pins {
 		samsung,pins = "gpd1-2", "gpd1-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c0_bus: hs-i2c0-bus-pins {
 		samsung,pins = "gpd2-1", "gpd2-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c1_bus: hs-i2c1-bus-pins {
 		samsung,pins = "gpd2-3", "gpd2-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c9_bus: hs-i2c9-bus-pins {
 		samsung,pins = "gpd2-7", "gpd2-6";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	pwm0_out: pwm0-out-pins {
 		samsung,pins = "gpd2-4";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	pwm1_out: pwm1-out-pins {
 		samsung,pins = "gpd2-5";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	pwm2_out: pwm2-out-pins {
 		samsung,pins = "gpd2-6";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	pwm3_out: pwm3-out-pins {
 		samsung,pins = "gpd2-7";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c8_bus: hs-i2c8-bus-pins {
 		samsung,pins = "gpd5-3", "gpd5-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	uart3_data: uart3-data-pins {
 		samsung,pins = "gpd5-0", "gpd5-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	spi2_bus: spi2-bus-pins {
 		samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	spi1_bus: spi1-bus-pins {
 		samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	spi0_bus: spi0-bus-pins {
 		samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c4_bus: hs-i2c4-bus-pins {
 		samsung,pins = "gpg3-1", "gpg3-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	hs_i2c5_bus: hs-i2c5-bus-pins {
 		samsung,pins = "gpg3-3", "gpg3-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
@@ -359,7 +359,7 @@ hs_i2c6_bus: hs-i2c6-bus-pins {
 		samsung,pins = "gpj0-1", "gpj0-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
@@ -376,7 +376,7 @@ hs_i2c7_bus: hs-i2c7-bus-pins {
 		samsung,pins = "gpj1-1", "gpj1-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
@@ -393,7 +393,7 @@ spi3_bus: spi3-bus-pins {
 		samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
@@ -410,7 +410,7 @@ spi4_bus: spi4-bus-pins {
 		samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
 
@@ -427,35 +427,35 @@ sd2_clk: sd2-clk-pins {
 		samsung,pins = "gpr4-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 
 	sd2_cmd: sd2-cmd-pins {
 		samsung,pins = "gpr4-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 
 	sd2_cd: sd2-cd-pins {
 		samsung,pins = "gpr4-2";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 
 	sd2_bus1: sd2-bus-width1-pins {
 		samsung,pins = "gpr4-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 
 	sd2_bus4: sd2-bus-width4-pins {
 		samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
 	};
 };
 
@@ -683,20 +683,20 @@ spi5_bus: spi5-bus-pins {
 		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 
 	ufs_refclk_out: ufs-refclk-out-pins {
 		samsung,pins = "gpg2-4";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>;
 	};
 
 	ufs_rst_n: ufs-rst-n-pins {
 		samsung,pins = "gph1-5";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
 	};
 };
diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
index 4cf9aa25f618..5db9a81ac7bb 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
@@ -60,6 +60,26 @@ power-key {
 	};
 };
 
+&mmc_0 {
+	status = "okay";
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	cap-mmc-highspeed;
+	non-removable;
+	mmc-hs400-enhanced-strobe;
+	card-detect-delay = <200>;
+	clock-frequency = <800000000>;
+	bus-width = <8>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <2 4>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs
+		     &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+};
+
 &oscclk {
 	clock-frequency = <26000000>;
 };
diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
index a50c1dbd5545..34bb12191955 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
@@ -9,8 +9,8 @@
  * device tree nodes in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_alive {
 	etc0: etc0-gpio-bank {
diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
index 3170661f5b67..23c2e0bb0a2c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 {
 			clock-names = "oscclk";
 		};
 
+		cmu_fsys: clock-controller@13400000 {
+			compatible = "samsung,exynos7885-cmu-fsys";
+			reg = <0x13400000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_FSYS_BUS>,
+				 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
+				 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
+				 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
+				 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
+			clock-names = "oscclk",
+				      "dout_fsys_bus",
+				      "dout_fsys_mmc_card",
+				      "dout_fsys_mmc_embd",
+				      "dout_fsys_mmc_sdio",
+				      "dout_fsys_usb30drd";
+		};
+
 		pinctrl_alive: pinctrl@11cb0000 {
 			compatible = "samsung,exynos7885-pinctrl";
 			reg = <0x11cb0000 0x1000>;
@@ -274,14 +293,27 @@ pmu_system_controller: system-controller@11c80000 {
 			reg = <0x11c80000 0x10000>;
 		};
 
+		mmc_0: mmc@13500000 {
+			compatible = "samsung,exynos7-dw-mshc-smu";
+			reg = <0x13500000 0x2000>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
+				 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x40>;
+			status = "disabled";
+		};
+
 		serial_0: serial@13800000 {
 			compatible = "samsung,exynos5433-uart";
 			reg = <0x13800000 0x100>;
 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART0_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <64>;
 			status = "disabled";
@@ -293,8 +325,8 @@ serial_1: serial@13810000 {
 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART1_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
@@ -306,8 +338,8 @@ serial_2: serial@13820000 {
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart2_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART2_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
index f43e4a206282..424bc80bde68 100644
--- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
@@ -10,7 +10,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_alive {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
index ef0349d1c3d0..2a616d23c09f 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
@@ -8,7 +8,7 @@
  * device tree nodes in this file.
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos-pinctrl.h"
 
 &pinctrl_alive {
 	gpa0: gpa0-gpio-bank {
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
index 17e568853eb6..2b30a7458297 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts
@@ -39,6 +39,14 @@ ufs_0_fixed_vcc_reg: regulator-0 {
 		regulator-boot-on;
 		enable-active-high;
 	};
+
+	ufs_1_fixed_vcc_reg: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "ufs-vcc";
+		gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
 };
 
 &serial_0 {
@@ -49,12 +57,22 @@ &ufs_0_phy {
 	status = "okay";
 };
 
+&ufs_1_phy {
+	status = "okay";
+};
+
 &ufs_0 {
 	status = "okay";
 	vcc-supply = <&ufs_0_fixed_vcc_reg>;
 	vcc-fixed-regulator;
 };
 
+&ufs_1 {
+	status = "okay";
+	vcc-supply = <&ufs_1_fixed_vcc_reg>;
+	vcc-fixed-regulator;
+};
+
 &usi_0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 0ce46ec5cdc3..00411d4c9c5a 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/samsung,exynosautov9.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/samsung,boot-mode.h>
 #include <dt-bindings/soc/samsung,exynos-usi.h>
 
 / {
@@ -312,6 +313,22 @@ pinctrl_peric1: pinctrl@10830000 {
 		pmu_system_controller: system-controller@10460000 {
 			compatible = "samsung,exynos7-pmu", "syscon";
 			reg = <0x10460000 0x10000>;
+
+			reboot: syscon-reboot {
+				compatible = "syscon-reboot";
+				regmap = <&pmu_system_controller>;
+				offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
+				value = <0x2>;
+				mask = <0x2>;
+			};
+
+			reboot-mode {
+				compatible = "syscon-reboot-mode";
+				offset = <0x810>; /* SYSIP_DAT0 */
+				mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>;
+				mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>;
+				mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>;
+			};
 		};
 
 		syscon_fsys2: syscon@17c20000 {
@@ -352,7 +369,7 @@ serial_0: serial@10300000 {
 			};
 		};
 
-		ufs_0_phy: ufs0-phy@17e04000 {
+		ufs_0_phy: phy@17e04000 {
 			compatible = "samsung,exynosautov9-ufs-phy";
 			reg = <0x17e04000 0xc00>;
 			reg-names = "phy-pma";
@@ -363,13 +380,13 @@ ufs_0_phy: ufs0-phy@17e04000 {
 			status = "disabled";
 		};
 
-		ufs_0: ufs0@17e00000 {
-			compatible ="samsung,exynosautov9-ufs";
+		ufs_0: ufs@17e00000 {
+			compatible = "samsung,exynosautov9-ufs";
 
-			reg = <0x17e00000 0x100>,  /* 0: HCI standard */
-				<0x17e01100 0x410>,  /* 1: Vendor-specific */
-				<0x17e80000 0x8000>,  /* 2: UNIPRO */
-				<0x17dc0000 0x2200>;  /* 3: UFS protector */
+			reg = <0x17e00000 0x100>,
+			      <0x17e01100 0x410>,
+			      <0x17e80000 0x8000>,
+			      <0x17dc0000 0x2200>;
 			reg-names = "hci", "vs_hci", "unipro", "ufsp";
 			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>,
@@ -383,6 +400,58 @@ ufs_0: ufs0@17e00000 {
 			samsung,sysreg = <&syscon_fsys2 0x710>;
 			status = "disabled";
 		};
+
+		ufs_1_phy: phy@17f04000 {
+			compatible = "samsung,exynosautov9-ufs-phy";
+			reg = <0x17f04000 0xc00>;
+			reg-names = "phy-pma";
+			samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
+			#phy-cells = <0>;
+			clocks = <&xtcxo>;
+			clock-names = "ref_clk";
+			status = "disabled";
+		};
+
+		ufs_1: ufs@17f00000 {
+			compatible = "samsung,exynosautov9-ufs";
+
+			reg = <0x17f00000 0x100>,
+			      <0x17f01100 0x410>,
+			      <0x17f80000 0x8000>,
+			      <0x17de0000 0x2200>;
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
+				 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
+			phys = <&ufs_1_phy>;
+			phy-names = "ufs-phy";
+			samsung,sysreg = <&syscon_fsys2 0x714>;
+			status = "disabled";
+		};
+
+		watchdog_cl0: watchdog@10050000 {
+			compatible = "samsung,exynosautov9-wdt";
+			reg = <0x10050000 0x100>;
+			interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <0>;
+		};
+
+		watchdog_cl1: watchdog@10060000 {
+			compatible = "samsung,exynosautov9-wdt";
+			reg = <0x10060000 0x100>;
+			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <1>;
+		};
 	};
 };
 
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 238a83e5b8c6..ed4d80618564 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
@@ -107,6 +108,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
 
 imx8mm-venice-gw72xx-0x-imx219-dtbs	:= imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo
 imx8mm-venice-gw72xx-0x-rs232-rts-dtbs	:= imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index e22c5e77fecd..5a8d85a7d161 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -69,7 +69,7 @@ &dspi {
 	flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "n25q128a11", "jedec,spi-nor";
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <10000000>;
 	};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 50a72cda4727..755720196648 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -204,7 +204,7 @@ sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -212,7 +212,7 @@ sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -220,7 +220,7 @@ sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -228,7 +228,7 @@ sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -465,7 +465,7 @@ QORIQ_CLK_PLL_DIV(4)>,
 			status = "disabled";
 		};
 
-		edma0: edma@2c00000 {
+		edma0: dma-controller@2c00000 {
 			#dma-cells = <2>;
 			compatible = "fsl,vf610-edma";
 			reg = <0x0 0x2c00000 0x0 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 5baf060acf93..0bb2f28a0441 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -93,7 +93,7 @@ mdio-mux {
 		compatible = "mdio-mux-multiplexer";
 		mux-controls = <&mux 0>;
 		mdio-parent-bus = <&enetc_mdio_pf3>;
-		#address-cells=<1>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
 		/* on-board RGMII PHY */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 92465f777603..3376eeab84ba 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -96,7 +96,7 @@ optee: optee  {
 	};
 
 	reboot {
-		compatible ="syscon-reboot";
+		compatible = "syscon-reboot";
 		regmap = <&rst>;
 		offset = <0>;
 		mask = <0x02>;
@@ -120,13 +120,13 @@ pmu {
 	};
 
 	gic: interrupt-controller@6000000 {
-		compatible= "arm,gic-v3";
+		compatible = "arm,gic-v3";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
-		reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 			<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
-		#interrupt-cells= <3>;
+		#interrupt-cells = <3>;
 		interrupt-controller;
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 					 IRQ_TYPE_LEVEL_LOW)>;
@@ -769,28 +769,28 @@ crypto: crypto@8000000 {
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	= <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	= <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	= <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	= <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 21200cbf7161..6cc959b2985b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -144,7 +144,7 @@ sysclk: sysclk {
 	};
 
 	reboot {
-		compatible ="syscon-reboot";
+		compatible = "syscon-reboot";
 		regmap = <&dcfg>;
 		offset = <0xb0>;
 		mask = <0x02>;
@@ -354,7 +354,7 @@ sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <0 71 0x4>;
 			};
 
@@ -362,7 +362,7 @@ sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <0 72 0x4>;
 			};
 
@@ -370,7 +370,7 @@ sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <0 73 0x4>;
 			};
 
@@ -378,7 +378,7 @@ sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <0 74 0x4>;
 			};
 		};
@@ -784,7 +784,7 @@ wdog0: watchdog@2ad0000 {
 			big-endian;
 		};
 
-		edma0: edma@2c00000 {
+		edma0: dma-controller@2c00000 {
 			#dma-cells = <2>;
 			compatible = "fsl,vf610-edma";
 			reg = <0x0 0x2c00000 0x0 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0085e83adf65..57a147a53236 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -112,7 +112,7 @@ sysclk: sysclk {
 	};
 
 	reboot {
-		compatible ="syscon-reboot";
+		compatible = "syscon-reboot";
 		regmap = <&dcfg>;
 		offset = <0xb0>;
 		mask = <0x02>;
@@ -360,7 +360,7 @@ sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -368,7 +368,7 @@ sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -376,7 +376,7 @@ sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
@@ -384,7 +384,7 @@ sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.4-job-ring",
 					     "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
@@ -683,7 +683,7 @@ wdog0: watchdog@2ad0000 {
 			big-endian;
 		};
 
-		edma0: edma@2c00000 {
+		edma0: dma-controller@2c00000 {
 			#dma-cells = <2>;
 			compatible = "fsl,vf610-edma";
 			reg = <0x0 0x2c00000 0x0 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
index d3f03dcbb8c3..ef6c8967533e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
@@ -35,14 +35,14 @@ buttons {
 		 * external power off (e.g ATX Power Button)
 		 * asserted
 		 */
-		powerdn {
+		button-powerdn {
 			label = "External Power Down";
 			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 		};
 
 		/* Rear Panel 'ADMIN' button (GPIO_H) */
-		admin {
+		button-admin {
 			label = "ADMIN button";
 			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_WPS_BUTTON>;
@@ -52,17 +52,17 @@ admin {
 	leds {
 		compatible = "gpio-leds";
 
-		sfp1down {
+		led-0 {
 			label = "ten64:green:sfp1:down";
 			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		sfp2up {
+		led-1 {
 			label = "ten64:green:sfp2:up";
 			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
 		};
 
-		admin {
+		led-2 {
 			label = "ten64:admin";
 			gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
 		};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f476b7d8b056..1456364ab795 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -526,28 +526,28 @@ crypto: crypto@8000000 {
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 4ba1e0499dfd..3692d4cf6fcf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -73,7 +73,7 @@ rstcr: syscon@1e60000 {
 	};
 
 	reboot {
-		compatible ="syscon-reboot";
+		compatible = "syscon-reboot";
 		regmap = <&rstcr>;
 		offset = <0x0>;
 		mask = <0x2>;
@@ -479,28 +479,28 @@ crypto: crypto@8000000 {
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg	   = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 2ecfa90f5e28..4d721197d837 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -36,7 +36,7 @@ mdio-mux-1 {
 		compatible = "mdio-mux-multiplexer";
 		mux-controls = <&mux 0>;
 		mdio-parent-bus = <&emdio1>;
-		#address-cells=<1>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
 		mdio@0 { /* On-board PHY #1 RGMI1*/
@@ -104,7 +104,7 @@ mdio-mux-2 {
 		compatible = "mdio-mux-multiplexer";
 		mux-controls = <&mux 1>;
 		mdio-parent-bus = <&emdio2>;
-		#address-cells=<1>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
 		mdio@0 { /* Slot #1 (secondary EMI) */
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 47ea854720ce..2f834f688bbe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -632,28 +632,28 @@ crypto: crypto@8000000 {
 			sec_jr0: jr@10000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg        = <0x10000 0x10000>;
+				reg = <0x10000 0x10000>;
 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr1: jr@20000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg        = <0x20000 0x10000>;
+				reg = <0x20000 0x10000>;
 				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr2: jr@30000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg        = <0x30000 0x10000>;
+				reg = <0x30000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sec_jr3: jr@40000 {
 				compatible = "fsl,sec-v5.0-job-ring",
 					     "fsl,sec-v4.0-job-ring";
-				reg        = <0x40000 0x10000>;
+				reg = <0x40000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index a1644ceed154..9f5ff1ffe7d5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -34,7 +34,7 @@ mdio-mux-1 {
 		compatible = "mdio-mux-multiplexer";
 		mux-controls = <&mux 0>;
 		mdio-parent-bus = <&emdio1>;
-		#address-cells=<1>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
 		mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
@@ -114,7 +114,7 @@ mdio-mux-2 {
 		compatible = "mdio-mux-multiplexer";
 		mux-controls = <&mux 1>;
 		mdio-parent-bus = <&emdio2>;
-		#address-cells=<1>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
 		mdio@0 { /* Slot #1 (secondary EMI) */
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index a79f42a9618e..82a1c4488378 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -54,7 +54,7 @@ usdhc2: mmc@5b020000 {
 		clock-names = "ipg", "per", "ahb";
 		power-domains = <&pd IMX_SC_R_SDHC_1>;
 		fsl,tuning-start-tap = <20>;
-		fsl,tuning-step= <2>;
+		fsl,tuning-step = <2>;
 		status = "disabled";
 	};
 
@@ -83,8 +83,8 @@ fec1: ethernet@5b040000 {
 		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
 				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
 		assigned-clock-rates = <250000000>, <125000000>;
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
+		fsl,num-tx-queues = <3>;
+		fsl,num-rx-queues = <3>;
 		power-domains = <&pd IMX_SC_R_ENET_0>;
 		status = "disabled";
 	};
@@ -103,8 +103,8 @@ fec2: ethernet@5b050000 {
 		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
 				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
 		assigned-clock-rates = <250000000>, <125000000>;
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
+		fsl,num-tx-queues = <3>;
+		fsl,num-rx-queues = <3>;
 		power-domains = <&pd IMX_SC_R_ENET_1>;
 		status = "disabled";
 	};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index f338a886d811..03266bd90a06 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -285,14 +285,14 @@ &uart3 {
 &usbotg1 {
 	vbus-supply = <&reg_usbotg1>;
 	disable-over-current;
-	dr_mode="otg";
+	dr_mode = "otg";
 	status = "okay";
 };
 
 &usbotg2 {
 	pinctrl-names = "default";
 	disable-over-current;
-	dr_mode="host";
+	dr_mode = "host";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
index b40148d728ea..9e6170d9394e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
@@ -84,42 +84,42 @@ reg_ldo4: ldo4 {
 			};
 
 			reg_buck1: buck1 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
 
 			reg_buck2: buck2 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
 
 			reg_buck3: buck3 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
 
 			reg_buck4: buck4 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
 
 			reg_buck5: buck5 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
 
 			reg_buck6: buck6 {
-				regulator-min-microvolt =  <400000>;
+				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-always-on;
 				regulator-boot-on;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
index 92eaf4ef4563..c97f4e06ae5f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
@@ -20,13 +20,13 @@ leds {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_led>;
 
-		user1 {
+		led-1 {
 			label = "TestLed601";
 			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 
-		user2 {
+		led-2 {
 			label = "TestLed602";
 			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
index ac1fe1530ac7..d643381417f1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
@@ -36,19 +36,19 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		back {
+		key-back {
 			label = "Back";
 			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
 		};
 
-		home {
+		key-home {
 			label = "Home";
 			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
 		};
 
-		menu {
+		key-menu {
 			label = "Menu";
 			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
index 00f86cada30d..66a0d103c90f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
@@ -16,13 +16,13 @@ memory@40000000 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pb {
+		key-user-pb {
 			label = "user_pb";
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_0>;
 		};
 
-		user-pb1x {
+		key-user-pb1x {
 			label = "user_pb1x";
 			linux,code = <BTN_1>;
 			interrupt-parent = <&gsc>;
@@ -36,14 +36,14 @@ key-erased {
 			interrupts = <1>;
 		};
 
-		eeprom-wp {
+		key-eeprom-wp {
 			label = "eeprom_wp";
 			linux,code = <BTN_3>;
 			interrupt-parent = <&gsc>;
 			interrupts = <2>;
 		};
 
-		tamper {
+		key-tamper {
 			label = "tamper";
 			linux,code = <BTN_4>;
 			interrupt-parent = <&gsc>;
@@ -286,8 +286,8 @@ buck1 {
 				regulator-name = "buck1";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1000000>;
-				regulator-min-microamp  = <3800000>;
-				regulator-max-microamp  = <6800000>;
+				regulator-min-microamp = <3800000>;
+				regulator-max-microamp = <6800000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
@@ -297,8 +297,8 @@ buck2 {
 				regulator-name = "buck2";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <900000>;
-				regulator-min-microamp  = <2200000>;
-				regulator-max-microamp  = <5200000>;
+				regulator-min-microamp = <2200000>;
+				regulator-max-microamp = <5200000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
@@ -308,8 +308,8 @@ buck3_reg: buck3 {
 				regulator-name = "buck3";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1000000>;
-				regulator-min-microamp  = <3800000>;
-				regulator-max-microamp  = <6800000>;
+				regulator-min-microamp = <3800000>;
+				regulator-max-microamp = <6800000>;
 				regulator-always-on;
 			};
 
@@ -318,8 +318,8 @@ buck4 {
 				regulator-name = "buck4";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-min-microamp  = <2200000>;
-				regulator-max-microamp  = <5200000>;
+				regulator-min-microamp = <2200000>;
+				regulator-max-microamp = <5200000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 24737e89038a..35fb929e7bcc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -38,13 +38,13 @@ memory@40000000 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pb {
+		key-user-pb {
 			label = "user_pb";
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_0>;
 		};
 
-		user-pb1x {
+		key-user-pb1x {
 			label = "user_pb1x";
 			linux,code = <BTN_1>;
 			interrupt-parent = <&gsc>;
@@ -58,14 +58,14 @@ key-erased {
 			interrupts = <1>;
 		};
 
-		eeprom-wp {
+		key-eeprom-wp {
 			label = "eeprom_wp";
 			linux,code = <BTN_3>;
 			interrupt-parent = <&gsc>;
 			interrupts = <2>;
 		};
 
-		tamper {
+		key-tamper {
 			label = "tamper";
 			linux,code = <BTN_4>;
 			interrupt-parent = <&gsc>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index 407ab4592b4c..6dc5eda2d256 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -42,13 +42,13 @@ can20m: can20m {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pb {
+		key-user-pb {
 			label = "user_pb";
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_0>;
 		};
 
-		user-pb1x {
+		key-user-pb1x {
 			label = "user_pb1x";
 			linux,code = <BTN_1>;
 			interrupt-parent = <&gsc>;
@@ -62,14 +62,14 @@ key-erased {
 			interrupts = <1>;
 		};
 
-		eeprom-wp {
+		key-eeprom-wp {
 			label = "eeprom_wp";
 			linux,code = <BTN_3>;
 			interrupt-parent = <&gsc>;
 			interrupts = <2>;
 		};
 
-		tamper {
+		key-tamper {
 			label = "tamper";
 			linux,code = <BTN_4>;
 			interrupt-parent = <&gsc>;
@@ -651,7 +651,7 @@ &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
 	rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
-	cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+	cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 	uart-has-rtscts;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index a7dae9bd4c11..a65761a53f23 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -33,13 +33,13 @@ memory@40000000 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pb {
+		key-user-pb {
 			label = "user_pb";
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_0>;
 		};
 
-		user-pb1x {
+		key-user-pb1x {
 			label = "user_pb1x";
 			linux,code = <BTN_1>;
 			interrupt-parent = <&gsc>;
@@ -53,7 +53,7 @@ key-erased {
 			interrupts = <1>;
 		};
 
-		eeprom-wp {
+		key-eeprom-wp {
 			label = "eeprom_wp";
 			linux,code = <BTN_3>;
 			interrupt-parent = <&gsc>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index eafa88d980b3..a8c329cb4c28 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -43,7 +43,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		wakeup {
+		key-wakeup {
 			debounce-interval = <10>;
 			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
 			gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1bf070473829..afb90f59c83c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -212,7 +212,7 @@ clk_ext3: clock-ext3 {
 	clk_ext4: clock-ext4 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency= <133000000>;
+		clock-frequency = <133000000>;
 		clock-output-names = "clk_ext4";
 	};
 
@@ -287,7 +287,7 @@ usbphynop2: usbphynop2 {
 		clock-names = "main_clk";
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "fsl,imx8mm-soc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -602,6 +602,11 @@ snvs_pwrkey: snvs-powerkey {
 					wakeup-source;
 					status = "disabled";
 				};
+
+				snvs_lpgpr: snvs-lpgpr {
+					compatible = "fsl,imx8mm-snvs-lpgpr",
+						     "fsl,imx7d-snvs-lpgpr";
+				};
 			};
 
 			clk: clock-controller@30380000 {
@@ -911,6 +916,7 @@ sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -995,7 +1001,7 @@ usdhc1: mmc@30b40000 {
 					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -1009,7 +1015,7 @@ usdhc2: mmc@30b50000 {
 					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -1023,7 +1029,7 @@ usdhc3: mmc@30b60000 {
 					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
index 02f37dcda7ed..9e82069c941f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
@@ -146,7 +146,7 @@ wm8962: audio-codec@1a {
 };
 
 &easrc {
-	fsl,asrc-rate  = <48000>;
+	fsl,asrc-rate = <48000>;
 	status = "okay";
 };
 
@@ -182,7 +182,7 @@ &uart3 {
 &usbotg1 {
 	vbus-supply = <&reg_usb_otg_vbus>;
 	disable-over-current;
-	dr_mode="otg";
+	dr_mode = "otg";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index d1f6cccfa00d..8db9d1122ca0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -78,7 +78,7 @@ sound-spdif {
 };
 
 &easrc {
-	fsl,asrc-rate  = <48000>;
+	fsl,asrc-rate = <48000>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
index f61c48776cf3..3ed7021a487c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
@@ -26,19 +26,19 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		back {
+		key-back {
 			label = "Back";
 			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
 		};
 
-		home {
+		key-home {
 			label = "Home";
 			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
 		};
 
-		menu {
+		key-menu {
 			label = "Menu";
 			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
index 367a232675aa..636f8602b979 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
@@ -39,13 +39,13 @@ can20m: can20m {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		user-pb {
+		key-user-pb {
 			label = "user_pb";
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_0>;
 		};
 
-		user-pb1x {
+		key-user-pb1x {
 			label = "user_pb1x";
 			linux,code = <BTN_1>;
 			interrupt-parent = <&gsc>;
@@ -59,14 +59,14 @@ key-erased {
 			interrupts = <1>;
 		};
 
-		eeprom-wp {
+		key-eeprom-wp {
 			label = "eeprom_wp";
 			linux,code = <BTN_3>;
 			interrupt-parent = <&gsc>;
 			interrupts = <2>;
 		};
 
-		tamper {
+		key-tamper {
 			label = "tamper";
 			linux,code = <BTN_4>;
 			interrupt-parent = <&gsc>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index e41e1d56f980..0c71b740a316 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -212,7 +212,7 @@ clk_ext3: clock-ext3 {
 	clk_ext4: clock-ext4 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency= <133000000>;
+		clock-frequency = <133000000>;
 		clock-output-names = "clk_ext4";
 	};
 
@@ -269,7 +269,7 @@ timer {
 		arm,no-tick-in-suspend;
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "fsl,imx8mn-soc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -422,7 +422,7 @@ easrc: easrc@300c0000 {
 						    "ctx2_rx", "ctx2_tx",
 						    "ctx3_rx", "ctx3_tx";
 					firmware-name = "imx/easrc/easrc-imx8mn.bin";
-					fsl,asrc-rate  = <8000>;
+					fsl,asrc-rate = <8000>;
 					fsl,asrc-format = <2>;
 					status = "disabled";
 				};
@@ -857,6 +857,7 @@ sec_jr0: jr@1000 {
 					 compatible = "fsl,sec-v4.0-job-ring";
 					 reg = <0x1000 0x1000>;
 					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					 status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -941,7 +942,7 @@ usdhc1: mmc@30b40000 {
 					 <&clk IMX8MN_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -955,7 +956,7 @@ usdhc2: mmc@30b50000 {
 					 <&clk IMX8MN_CLK_USDHC2_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -969,7 +970,7 @@ usdhc3: mmc@30b60000 {
 					 <&clk IMX8MN_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
new file mode 100644
index 000000000000..2ca2ede2e94e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/qca-ar803x.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp-dhcom-som.dtsi"
+
+/ {
+	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
+	compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-0 {
+			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
+			label = "TA1-GPIO-A";
+			linux,code = <KEY_A>;
+			pinctrl-0 = <&pinctrl_dhcom_a>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-1 {
+			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
+			label = "TA2-GPIO-B";
+			linux,code = <KEY_B>;
+			pinctrl-0 = <&pinctrl_dhcom_b>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-2 {
+			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
+			label = "TA3-GPIO-C";
+			linux,code = <KEY_C>;
+			pinctrl-0 = <&pinctrl_dhcom_c>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-3 {
+			gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
+			label = "TA4-GPIO-D";
+			linux,code = <KEY_D>;
+			pinctrl-0 = <&pinctrl_dhcom_d>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
+			pinctrl-0 = <&pinctrl_dhcom_e>;
+			pinctrl-names = "default";
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
+			pinctrl-0 = <&pinctrl_dhcom_f>;
+			pinctrl-names = "default";
+		};
+
+		led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
+			pinctrl-0 = <&pinctrl_dhcom_h>;
+			pinctrl-names = "default";
+		};
+
+		led-3 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+/*
+ * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
+ * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
+ */
+/delete-node/ &ethphy0f;
+
+/*
+ * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
+ * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
+ */
+/delete-node/ &ethphy1f;
+
+&fec {	/* Second ethernet */
+	phy-handle = <&ethphypdk>;
+
+	mdio {
+		ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			pinctrl-0 = <&pinctrl_ethphy1>;
+			pinctrl-names = "default";
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+			max-speed = <100>;
+			reg = <7>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			rxc-skew-ps = <3000>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txc-skew-ps = <3000>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
+&flexcan1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	fsl,over-current-active-low;
+};
+
+&iomuxc {
+	/*
+	 * GPIO_A,B,C,D are connected to buttons.
+	 * GPIO_E,F,H,I are connected to LEDs.
+	 * GPIO_M is connected to CLKOUT2.
+	 */
+	pinctrl-0 = <&pinctrl_hog_base
+		     &pinctrl_dhcom_g &pinctrl_dhcom_j
+		     &pinctrl_dhcom_k &pinctrl_dhcom_l
+		     &pinctrl_dhcom_int>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
new file mode 100644
index 000000000000..a616eb378002
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
@@ -0,0 +1,1030 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp.dtsi"
+
+/ {
+	model = "DH electronics i.MX8M Plus DHCOM SoM";
+	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+		rtc0 = &rv3032;
+		rtc1 = &snvs_rtc;
+		spi0 = &flexspi;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
+		reg = <0x0 0x40000000 0 0x08000000>;
+	};
+
+	reg_eth_vio: regulator-eth-vio {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&pinctrl_enet_vio>;
+		pinctrl-names = "default";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "eth_vio";
+		vin-supply = <&buck4>;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 19 0>; /* SD2_RESET */
+		off-on-delay-us = <12000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VDD_3V3_SD";
+		startup-delay-us = <100>;
+		vin-supply = <&buck4>;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	status = "disabled";
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "disabled";
+};
+
+&eqos {	/* First ethernet */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-handle = <&ethphy0g>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Up to one of these two PHYs may be populated. */
+		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+			compatible = "ethernet-phy-id0007.c110",
+				     "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio3>;
+			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy0>;
+			pinctrl-names = "default";
+			reg = <1>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+			/* Non-default PHY population option. */
+			status = "disabled";
+		};
+
+		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
+			compatible = "ethernet-phy-id0022.1642",
+				     "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio3>;
+			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+			micrel,led-mode = <0>;
+			pinctrl-0 = <&pinctrl_ethphy0>;
+			pinctrl-names = "default";
+			reg = <5>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+			/* Default PHY population option. */
+			status = "okay";
+		};
+	};
+};
+
+&fec {	/* Second ethernet */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	phy-handle = <&ethphy1f>;
+	phy-mode = "rgmii";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Up to one PHY may be populated. */
+		ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+			compatible = "ethernet-phy-id0007.c110",
+				     "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy1>;
+			pinctrl-names = "default";
+			reg = <1>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			/* Non-default PHY population option. */
+			status = "disabled";
+		};
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "disabled";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "disabled";
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi>;
+	status = "okay";
+
+	flash@0 {	/* W25Q128JWPIM */
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&gpio1 {
+	gpio-line-names =
+		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
+		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "DHCOM-K", "", "", "", "",
+		"", "", "", "", "DHCOM-INT", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "SOM-HW0", "",
+		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
+		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "SOM-HW1", "", "", "", "",
+		"", "", "", "DHCOM-D", "", "", "", "";
+};
+
+&gpio5 {
+	gpio-line-names =
+		"", "", "DHCOM-C", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
+		"", "", "", "", "", "", "", "";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pmic: pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+		/*
+		 * i.MX 8M Plus Data Sheet for Consumer Products
+		 * 3.1.4 Operating ranges
+		 * MIMX8ML8CVNKZAB
+		 */
+		regulators {
+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
+				regulator-compatible = "BUCK1";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck2: BUCK2 {	/* VDD_ARM */
+				regulator-compatible = "BUCK2";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck4: BUCK4 {	/* VDD_3V3 */
+				regulator-compatible = "BUCK4";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck5: BUCK5 {	/* VDD_1V8 */
+				regulator-compatible = "BUCK5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
+				regulator-compatible = "BUCK6";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
+				regulator-compatible = "LDO1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo3: LDO3 {	/* VDDA_1V8 */
+				regulator-compatible = "LDO3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo4: LDO4 {	/* PMIC_LDO4 */
+				regulator-compatible = "LDO4";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo5: LDO5 {	/* NVCC_SD2 */
+				regulator-compatible = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+
+	adc@48 {
+		compatible = "ti,tla2024";
+		reg = <0x48>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {	/* Voltage over AIN0 and AIN1. */
+			reg = <0>;
+		};
+
+		channel@1 {	/* Voltage over AIN0 and AIN3. */
+			reg = <1>;
+		};
+
+		channel@2 {	/* Voltage over AIN1 and AIN3. */
+			reg = <2>;
+		};
+
+		channel@3 {	/* Voltage over AIN2 and AIN3. */
+			reg = <3>;
+		};
+
+		channel@4 {	/* Voltage over AIN0 and GND. */
+			reg = <4>;
+		};
+
+		channel@5 {	/* Voltage over AIN1 and GND. */
+			reg = <5>;
+		};
+
+		channel@6 {	/* Voltage over AIN2 and GND. */
+			reg = <6>;
+		};
+
+		channel@7 {	/* Voltage over AIN3 and GND. */
+			reg = <7>;
+		};
+	};
+
+	touchscreen@49 {
+		compatible = "ti,tsc2004";
+		reg = <0x49>;
+		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_touch>;
+		vio-supply = <&buck4>;
+	};
+
+	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
+		compatible = "atmel,24c02";
+		pagesize = <16>;
+		reg = <0x50>;
+	};
+
+	rv3032: rtc@51 {
+		compatible = "microcrystal,rv3032";
+		reg = <0x51>;
+		interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+	};
+
+	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
+		compatible = "atmel,24c02";
+		pagesize = <16>;
+		reg = <0x53>;
+	};
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&i2c5 {	/* HDMI EDID bus */
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c5>;
+	pinctrl-1 = <&pinctrl_i2c5_gpio>;
+	scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pinctrl_pwm1>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&uart1 {
+	/* CA53 console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	/* Bluetooth */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_vbus>;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb1_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	vmmc-supply = <&buck4>;
+	bus-width = <4>;
+	non-removable;
+	cap-power-off-card;
+	keep-power-in-suspend;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	brcmf: bcrmf@1 {	/* muRata 2AE */
+		reg = <1>;
+		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
+		/*
+		 * The "host-wake" interrupt output is by default not
+		 * connected to the SoC, but can be connected on to
+		 * SoC pin on the carrier board.
+		 */
+		reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+	};
+};
+
+/* SD slot */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	vmmc-supply = <&buck4>;
+	vqmmc-supply = <&buck5>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_hog_base
+		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+		     /* GPIO_M is connected to CLKOUT2 */
+		     &pinctrl_dhcom_int>;
+	pinctrl-names = "default";
+
+	pinctrl_dhcom_a: dhcom-a-grp {
+		fsl,pins = <
+			/* ENET_QOS_EVENT0-OUT */
+			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
+		>;
+	};
+
+	pinctrl_dhcom_b: dhcom-b-grp {
+		fsl,pins = <
+			/* ENET_QOS_EVENT0-IN */
+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
+		>;
+	};
+
+	pinctrl_dhcom_c: dhcom-c-grp {
+		fsl,pins = <
+			/* GPIO_C */
+			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
+		>;
+	};
+
+	pinctrl_dhcom_d: dhcom-d-grp {
+		fsl,pins = <
+			/* GPIO_D */
+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
+		>;
+	};
+
+	pinctrl_dhcom_e: dhcom-e-grp {
+		fsl,pins = <
+			/* GPIO_E */
+			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
+		>;
+	};
+
+	pinctrl_dhcom_f: dhcom-f-grp {
+		fsl,pins = <
+			/* GPIO_F */
+			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
+		>;
+	};
+
+	pinctrl_dhcom_g: dhcom-g-grp {
+		fsl,pins = <
+			/* GPIO_G */
+			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
+		>;
+	};
+
+	pinctrl_dhcom_h: dhcom-h-grp {
+		fsl,pins = <
+			/* GPIO_H */
+			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
+		>;
+	};
+
+	pinctrl_dhcom_i: dhcom-i-grp {
+		fsl,pins = <
+			/* CSI1_SYNC */
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
+		>;
+	};
+
+	pinctrl_dhcom_j: dhcom-j-grp {
+		fsl,pins = <
+			/* CSIx_#RST */
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
+		>;
+	};
+
+	pinctrl_dhcom_k: dhcom-k-grp {
+		fsl,pins = <
+			/* CSIx_PWDN */
+			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
+		>;
+	};
+
+	pinctrl_dhcom_l: dhcom-l-grp {
+		fsl,pins = <
+			/* CSI2_SYNC */
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
+		>;
+	};
+
+	pinctrl_dhcom_int: dhcom-int-grp {
+		fsl,pins = <
+			/* INT_HIGHEST_PRIO */
+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
+		>;
+	};
+
+	pinctrl_hog_base: dhcom-hog-base-grp {
+		fsl,pins = <
+			/* GPIOs for memory coding */
+			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
+			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
+			/* GPIOs for hardware coding */
+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
+			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
+		>;
+	};
+
+	pinctrl_ecspi1: dhcom-ecspi1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44
+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44
+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40
+		>;
+	};
+
+	pinctrl_ecspi2: dhcom-ecspi2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
+		>;
+	};
+
+	pinctrl_eqos: dhcom-eqos-grp {	/* RGMII */
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
+		>;
+	};
+
+	pinctrl_enet_vio: dhcom-enet-vio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x22
+		>;
+	};
+
+	pinctrl_ethphy0: dhcom-ethphy0-grp {
+		fsl,pins = <
+			/* ENET1_#RST Reset */
+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
+			/* ENET1_#INT Interrupt */
+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
+		>;
+	};
+
+	pinctrl_ethphy1: dhcom-ethphy1-grp {
+		fsl,pins = <
+			/* ENET1_#RST Reset */
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
+			/* ENET1_#INT Interrupt */
+			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
+		>;
+	};
+
+	pinctrl_fec: dhcom-fec-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
+		>;
+	};
+
+	pinctrl_flexcan1: dhcom-flexcan1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
+		>;
+	};
+
+	pinctrl_flexcan2: dhcom-flexcan2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
+		>;
+	};
+
+	pinctrl_flexspi: dhcom-flexspi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
+		>;
+	};
+
+	pinctrl_hdmi: dhcom-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
+		>;
+	};
+
+	pinctrl_i2c3: dhcom-i2c3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
+		>;
+	};
+
+	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
+		>;
+	};
+
+	pinctrl_i2c4: dhcom-i2c4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
+		>;
+	};
+
+	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
+		>;
+	};
+
+	pinctrl_i2c5: dhcom-i2c5-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
+			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
+		>;
+	};
+
+	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
+			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
+		>;
+	};
+
+	pinctrl_pmic: dhcom-pmic-grp {
+		fsl,pins = <
+			/* PMIC_nINT */
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
+		>;
+	};
+
+	pinctrl_pwm1: dhcom-pwm1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
+		>;
+	};
+
+	pinctrl_rtc: dhcom-rtc-grp {
+		fsl,pins = <
+			/* RTC_#INT Interrupt */
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x40000080
+		>;
+	};
+
+	pinctrl_touch: dhcom-touch-grp {
+		fsl,pins = <
+			/* #TOUCH_INT */
+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
+		>;
+	};
+
+	pinctrl_uart1: dhcom-uart1-grp {
+		fsl,pins = <
+			/* Console UART */
+			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
+			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
+			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
+			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
+		>;
+	};
+
+	pinctrl_uart2: dhcom-uart2-grp {
+		fsl,pins = <
+			/* Bluetooth UART */
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
+			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
+		>;
+	};
+
+	pinctrl_uart3: dhcom-uart3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
+			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
+			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
+			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
+		>;
+	};
+
+	pinctrl_uart4: dhcom-uart4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usb0_vbus: dhcom-usb0-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID		0x0
+		>;
+	};
+
+	pinctrl_usb1_vbus: dhcom-usb1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
+			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
+		>;
+	};
+
+	pinctrl_usdhc1: dhcom-usdhc1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
+			/* BT_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
+			/* WL_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
+			/* BT_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
+			/* WL_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
+			/* BT_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
+			/* WL_REG_EN */
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
+		>;
+	};
+
+	pinctrl_usdhc2: dhcom-usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
+		>;
+	};
+
+	pinctrl_usdhc3: dhcom-usdhc3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
+			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
+		>;
+	};
+
+	pinctrl_wdog: dhcom-wdog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
+		>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4c3ac4214a2c..a449a511f932 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -67,18 +67,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 	};
 };
 
-&flexcan1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	xceiver-supply = <&reg_can1_stby>;
-	status = "okay";
+&A53_0 {
+	cpu-supply = <&reg_arm>;
 };
 
-&flexcan2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	xceiver-supply = <&reg_can2_stby>;
-	status = "disabled";/* can2 pin conflict with pdm */
+&A53_1 {
+	cpu-supply = <&reg_arm>;
+};
+
+&A53_2 {
+	cpu-supply = <&reg_arm>;
+};
+
+&A53_3 {
+	cpu-supply = <&reg_arm>;
 };
 
 &eqos {
@@ -197,6 +199,20 @@ ethphy1: ethernet-phy@1 {
 	};
 };
 
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_stby>;
+	status = "disabled";/* can2 pin conflict with pdm */
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -221,7 +237,7 @@ BUCK1 {
 				regulator-ramp-delay = <3125>;
 			};
 
-			BUCK2 {
+			reg_arm: BUCK2 {
 				regulator-name = "BUCK2";
 				regulator-min-microvolt = <720000>;
 				regulator-max-microvolt = <1025000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index fb17e329cd37..8c38f89df0ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -49,7 +49,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		wakeup {
+		button-wakeup {
 			debounce-interval = <10>;
 			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
 			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d9542dfff83f..cbfe841fa38b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -195,7 +195,7 @@ clk_ext3: clock-ext3 {
 	clk_ext4: clock-ext4 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency= <133000000>;
+		clock-frequency = <133000000>;
 		clock-output-names = "clk_ext4";
 	};
 
@@ -293,7 +293,7 @@ timer {
 		arm,no-tick-in-suspend;
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "fsl,imx8mp-soc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -791,6 +791,7 @@ sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -903,7 +904,7 @@ usdhc1: mmc@30b40000 {
 					 <&clk IMX8MP_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -917,7 +918,7 @@ usdhc2: mmc@30b50000 {
 					 <&clk IMX8MP_CLK_USDHC2_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -931,7 +932,7 @@ usdhc3: mmc@30b60000 {
 					 <&clk IMX8MP_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index b86f188a440d..6445c6b90b5b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -36,21 +36,21 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		btn1 {
+		button-1 {
 			label = "VOL_UP";
 			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
 			wakeup-source;
 			linux,code = <KEY_VOLUMEUP>;
 		};
 
-		btn2 {
+		button-2 {
 			label = "VOL_DOWN";
 			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 			wakeup-source;
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 
-		wwan-wake {
+		button-3 {
 			label = "WWAN_WAKE";
 			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
 			interrupt-parent = <&gpio3>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
index 587e55aaa57b..9eec8a7eecfc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
@@ -37,7 +37,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_keys>;
 
-		vol-down {
+		key-vol-down {
 			label = "VOL_DOWN";
 			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
@@ -45,7 +45,7 @@ vol-down {
 			wakeup-source;
 		};
 
-		vol-up {
+		key-vol-up {
 			label = "VOL_UP";
 			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
index f70fb32b96b0..9dda2a1554c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
@@ -26,7 +26,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
-		power {
+		button-power {
 			label = "Power Button";
 			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
@@ -152,7 +152,7 @@ reg_arm_dram: regulator@60 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_reg_arm_dram>;
 				reg = <0x60>;
-				regulator-min-microvolt =  <900000>;
+				regulator-min-microvolt = <900000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
 				vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
@@ -186,7 +186,7 @@ reg_soc_gpu_vpu: regulator@60 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
 				reg = <0x60>;
-				regulator-min-microvolt =  <900000>;
+				regulator-min-microvolt = <900000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
 				vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
index 2222ef7b3eab..4e05120c62d4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -443,7 +443,7 @@ &i2c3 {
 	status = "okay";
 
 	usbhub: usbhub@2c {
-		compatible ="microchip,usb2513b";
+		compatible = "microchip,usb2513b";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usbhub>;
 		reg = <0x2c>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 49eadb081b19..e9f0cdd10ab6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -94,7 +94,7 @@ clk_ext3: clock-ext3 {
 	clk_ext4: clock-ext4 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency= <133000000>;
+		clock-frequency = <133000000>;
 		clock-output-names = "clk_ext4";
 	};
 
@@ -320,7 +320,7 @@ timer {
 		arm,no-tick-in-suspend;
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "fsl,imx8mq-soc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -329,7 +329,7 @@ soc@0 {
 		nvmem-cells = <&imx8mq_uid>;
 		nvmem-cell-names = "soc_unique_id";
 
-		bus@30000000 { /* AIPS1 */
+		aips1: bus@30000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30000000 0x400000>;
 			#address-cells = <1>;
@@ -507,7 +507,7 @@ tmu: tmu@30260000 {
 						      <0x00030005 0x00000053>,
 						      <0x00030006 0x0000005f>,
 						      <0x00030007 0x00000071>;
-				#thermal-sensor-cells =  <1>;
+				#thermal-sensor-cells = <1>;
 			};
 
 			wdog1: watchdog@30280000 {
@@ -784,7 +784,7 @@ pgc_pcie2: power-domain@a {
 			};
 		};
 
-		bus@30400000 { /* AIPS2 */
+		aips2: bus@30400000 { /* AIPS2 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30400000 0x400000>;
 			#address-cells = <1>;
@@ -844,7 +844,7 @@ system_counter: timer@306a0000 {
 			};
 		};
 
-		bus@30800000 { /* AIPS3 */
+		aips3: bus@30800000 { /* AIPS3 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30800000 0x400000>;
 			#address-cells = <1>;
@@ -1018,6 +1018,7 @@ sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -1369,7 +1370,7 @@ opp-800M {
 			};
 		};
 
-		bus@32c00000 { /* AIPS4 */
+		aips4: bus@32c00000 { /* AIPS4 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x32c00000 0x400000>;
 			#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
index 144fc9e82da7..a08e70fb7c7a 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
@@ -16,7 +16,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpiokeys>;
 
-		wakeup {
+		key-wakeup {
 			label = "Wake-Up";
 			gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_WAKEUP>;
@@ -38,17 +38,17 @@ rtc_i2c: rtc@68 {
 
 /* Colibri UART_B */
 &lpuart0 {
-	status= "okay";
+	status = "okay";
 };
 
 /* Colibri UART_C */
 &lpuart2 {
-	status= "okay";
+	status = "okay";
 };
 
 /* Colibri UART_A */
 &lpuart3 {
-	status= "okay";
+	status = "okay";
 };
 
 /* Colibri FastEthernet */
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index a79ae33cbad2..483996a1f2d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -276,7 +276,7 @@ xtal24m: clock-xtal24m {
 	};
 
 	thermal_zones: thermal-zones {
-		cpu-thermal0 {
+		cpu0-thermal {
 			polling-delay-passive = <250>;
 			polling-delay = <2000>;
 			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 09f7364dd1d0..60c1b018bf03 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -137,7 +137,7 @@ scmi_sensor: protocol@15 {
 		};
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -331,7 +331,7 @@ usdhc0: mmc@298d0000 {
 				clock-names = "ipg", "ahb", "per";
 				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -346,7 +346,7 @@ usdhc1: mmc@298e0000 {
 				clock-names = "ipg", "ahb", "per";
 				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -361,13 +361,13 @@ usdhc2: mmc@298f0000 {
 				clock-names = "ipg", "ahb", "per";
 				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
 		};
 
-		gpioe: gpio@2d000000 {
+		gpioe: gpio@2d000080 {
 				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
 				gpio-controller;
@@ -381,7 +381,7 @@ gpioe: gpio@2d000000 {
 				gpio-ranges = <&iomuxc1 0 32 24>;
 		};
 
-		gpiof: gpio@2d010000 {
+		gpiof: gpio@2d010080 {
 				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
 				gpio-controller;
@@ -417,7 +417,7 @@ pcc5: clock-controller@2da70000 {
 			};
 		};
 
-		gpiod: gpio@2e200000 {
+		gpiod: gpio@2e200080 {
 			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
 			gpio-controller;
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
new file mode 100644
index 000000000000..69786c326db0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/ {
+	model = "NXP i.MX93 11X11 EVK board";
+	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&mu1 {
+	status = "okay";
+};
+
+&mu2 {
+	status = "okay";
+};
+
+&lpuart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+	no-sdio;
+	no-mmc;
+};
+
+&iomuxc {
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17fe
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x17fe
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17fe
+			MX93_PAD_SD2_CMD__USDHC2_CMD		0x13fe
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx93-pinfunc.h b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h
new file mode 100755
index 000000000000..4298a145f8a9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __DTS_IMX93_PINFUNC_H
+#define __DTS_IMX93_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI                            0x0000 0x01B0 0x03D8 0x0 0x0
+#define MX93_PAD_DAP_TDI__MQS2_LEFT                               0x0000 0x01B0 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDI__CAN2_TX                                 0x0000 0x01B0 0x0000 0x3 0x0
+#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30                        0x0000 0x01B0 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDI__GPIO3_IO28                              0x0000 0x01B0 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDI__LPUART5_RX                              0x0000 0x01B0 0x0430 0x6 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                      0x0004 0x01B4 0x03DC 0x0 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                  0x0004 0x01B4 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                        0x0004 0x01B4 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                     0x0004 0x01B4 0x0000 0x6 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                     0x0008 0x01B8 0x03D4 0x0 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                 0x0008 0x01B8 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                       0x0008 0x01B8 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                    0x0008 0x01B8 0x042C 0x6 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                   0x000C 0x01BC 0x0000 0x0 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                     0x000C 0x01BC 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX                        0x000C 0x01BC 0x0364 0x3 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31               0x000C 0x01BC 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                     0x000C 0x01BC 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                     0x000C 0x01BC 0x0434 0x6 0x0
+#define MX93_PAD_GPIO_IO00__GPIO2_IO00                            0x0010 0x01C0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA                            0x0010 0x01C0 0x03E4 0x11 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                      0x0010 0x01C0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                     0x0010 0x01C0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0                           0x0010 0x01C0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO00__LPUART5_TX                            0x0010 0x01C0 0x0434 0x5 0x1
+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA                            0x0010 0x01C0 0x03EC 0x16 0x0
+#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00                      0x0010 0x01C0 0x036C 0x7 0x0
+#define MX93_PAD_GPIO_IO01__GPIO2_IO01                            0x0014 0x01C4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL                            0x0014 0x01C4 0x03E0 0x11 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00                   0x0014 0x01C4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                      0x0014 0x01C4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO01__LPSPI6_SIN                            0x0014 0x01C4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO01__LPUART5_RX                            0x0014 0x01C4 0x0430 0x5 0x1
+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL                            0x0014 0x01C4 0x03E8 0x16 0x0
+#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01                      0x0014 0x01C4 0x0370 0x7 0x0
+#define MX93_PAD_GPIO_IO02__GPIO2_IO02                            0x0018 0x01C8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA                            0x0018 0x01C8 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                    0x0018 0x01C8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                   0x0018 0x01C8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT                           0x0018 0x01C8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B                         0x0018 0x01C8 0x042C 0x5 0x1
+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA                            0x0018 0x01C8 0x03F4 0x16 0x0
+#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02                      0x0018 0x01C8 0x0374 0x7 0x0
+#define MX93_PAD_GPIO_IO03__GPIO2_IO03                            0x001C 0x01CC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL                            0x001C 0x01CC 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                    0x001C 0x01CC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                   0x001C 0x01CC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO03__LPSPI6_SCK                            0x001C 0x01CC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B                         0x001C 0x01CC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL                            0x001C 0x01CC 0x03F0 0x16 0x0
+#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03                      0x001C 0x01CC 0x0378 0x7 0x0
+#define MX93_PAD_GPIO_IO04__GPIO2_IO04                            0x0020 0x01D0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO04__TPM3_CH0                              0x0020 0x01D0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO04__PDM_CLK                               0x0020 0x01D0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00                  0x0020 0x01D0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0                           0x0020 0x01D0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO04__LPUART6_TX                            0x0020 0x01D0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA                            0x0020 0x01D0 0x03F4 0x16 0x1
+#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04                      0x0020 0x01D0 0x037C 0x7 0x0
+#define MX93_PAD_GPIO_IO05__GPIO2_IO05                            0x0024 0x01D4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO05__TPM4_CH0                              0x0024 0x01D4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                      0x0024 0x01D4 0x0438 0x2 0x0
+#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01                  0x0024 0x01D4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO05__LPSPI7_SIN                            0x0024 0x01D4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO05__LPUART6_RX                            0x0024 0x01D4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL                            0x0024 0x01D4 0x03F0 0x16 0x1
+#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05                      0x0024 0x01D4 0x0380 0x7 0x0
+#define MX93_PAD_GPIO_IO06__GPIO2_IO06                            0x0028 0x01D8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO06__TPM5_CH0                              0x0028 0x01D8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                      0x0028 0x01D8 0x043C 0x2 0x0
+#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02                  0x0028 0x01D8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT                           0x0028 0x01D8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B                         0x0028 0x01D8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA                            0x0028 0x01D8 0x03FC 0x16 0x0
+#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06                      0x0028 0x01D8 0x0384 0x7 0x0
+#define MX93_PAD_GPIO_IO07__GPIO2_IO07                            0x002C 0x01DC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1                           0x002C 0x01DC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01                   0x002C 0x01DC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03                  0x002C 0x01DC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI7_SCK                            0x002C 0x01DC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B                         0x002C 0x01DC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL                            0x002C 0x01DC 0x03F8 0x16 0x0
+#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07                      0x002C 0x01DC 0x0388 0x7 0x0
+#define MX93_PAD_GPIO_IO08__GPIO2_IO08                            0x0030 0x01E0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0                           0x0030 0x01E0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02                   0x0030 0x01E0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04                  0x0030 0x01E0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO08__TPM6_CH0                              0x0030 0x01E0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO08__LPUART7_TX                            0x0030 0x01E0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA                            0x0030 0x01E0 0x03FC 0x16 0x1
+#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08                      0x0030 0x01E0 0x038C 0x7 0x0
+#define MX93_PAD_GPIO_IO09__GPIO2_IO09                            0x0034 0x01E4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO09__LPSPI3_SIN                            0x0034 0x01E4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03                   0x0034 0x01E4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05                  0x0034 0x01E4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK                           0x0034 0x01E4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO09__LPUART7_RX                            0x0034 0x01E4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL                            0x0034 0x01E4 0x03F8 0x16 0x1
+#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09                      0x0034 0x01E4 0x0390 0x7 0x0
+#define MX93_PAD_GPIO_IO10__GPIO2_IO10                            0x0038 0x01E8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT                           0x0038 0x01E8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04                   0x0038 0x01E8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06                  0x0038 0x01E8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK                           0x0038 0x01E8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B                         0x0038 0x01E8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA                            0x0038 0x01E8 0x0404 0x16 0x0
+#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                      0x0038 0x01E8 0x0394 0x7 0x0
+#define MX93_PAD_GPIO_IO11__GPIO2_IO11                            0x003C 0x01EC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO11__LPSPI3_SCK                            0x003C 0x01EC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05                   0x003C 0x01EC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07                  0x003C 0x01EC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK                           0x003C 0x01EC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B                         0x003C 0x01EC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL                            0x003C 0x01EC 0x0400 0x16 0x0
+#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                      0x003C 0x01EC 0x0398 0x7 0x0
+#define MX93_PAD_GPIO_IO12__GPIO2_IO12                            0x0040 0x01F0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO12__TPM3_CH2                              0x0040 0x01F0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                      0x0040 0x01F0 0x0440 0x2 0x0
+#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08                  0x0040 0x01F0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0                           0x0040 0x01F0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO12__LPUART8_TX                            0x0040 0x01F0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA                            0x0040 0x01F0 0x0404 0x16 0x1
+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                          0x0040 0x01F0 0x0450 0x7 0x0
+#define MX93_PAD_GPIO_IO13__GPIO2_IO13                            0x0044 0x01F4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO13__TPM4_CH2                              0x0044 0x01F4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                      0x0044 0x01F4 0x0444 0x2 0x0
+#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09                  0x0044 0x01F4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO13__LPSPI8_SIN                            0x0044 0x01F4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO13__LPUART8_RX                            0x0044 0x01F4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL                            0x0044 0x01F4 0x0400 0x16 0x1
+#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                      0x0044 0x01F4 0x039C 0x7 0x0
+#define MX93_PAD_GPIO_IO14__GPIO2_IO14                            0x0048 0x01F8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO14__LPUART3_TX                            0x0048 0x01F8 0x041C 0x1 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06                   0x0048 0x01F8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                  0x0048 0x01F8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT                           0x0048 0x01F8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B                         0x0048 0x01F8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO14__LPUART4_TX                            0x0048 0x01F8 0x0428 0x6 0x0
+#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                      0x0048 0x01F8 0x03A0 0x7 0x0
+#define MX93_PAD_GPIO_IO15__GPIO2_IO15                            0x004C 0x01FC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO15__LPUART3_RX                            0x004C 0x01FC 0x0418 0x1 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07                   0x004C 0x01FC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                  0x004C 0x01FC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO15__LPSPI8_SCK                            0x004C 0x01FC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B                         0x004C 0x01FC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO15__LPUART4_RX                            0x004C 0x01FC 0x0424 0x6 0x0
+#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                      0x004C 0x01FC 0x03A4 0x7 0x0
+#define MX93_PAD_GPIO_IO16__GPIO2_IO16                            0x0050 0x0200 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                          0x0050 0x0200 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                      0x0050 0x0200 0x0440 0x2 0x1
+#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                  0x0050 0x0200 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B                         0x0050 0x0200 0x0414 0x4 0x0
+#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2                           0x0050 0x0200 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B                         0x0050 0x0200 0x0420 0x6 0x0
+#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                      0x0050 0x0200 0x03A8 0x7 0x0
+#define MX93_PAD_GPIO_IO17__GPIO2_IO17                            0x0054 0x0204 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO17__SAI3_MCLK                             0x0054 0x0204 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08                   0x0054 0x0204 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                  0x0054 0x0204 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B                         0x0054 0x0204 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1                           0x0054 0x0204 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B                         0x0054 0x0204 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                      0x0054 0x0204 0x03AC 0x7 0x0
+#define MX93_PAD_GPIO_IO18__GPIO2_IO18                            0x0058 0x0208 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                          0x0058 0x0208 0x044C 0x1 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09                   0x0058 0x0208 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                  0x0058 0x0208 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0                           0x0058 0x0208 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0                           0x0058 0x0208 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO18__TPM5_CH2                              0x0058 0x0208 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                      0x0058 0x0208 0x03B0 0x7 0x0
+#define MX93_PAD_GPIO_IO19__GPIO2_IO19                            0x005C 0x020C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                          0x005C 0x020C 0x0450 0x1 0x1
+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                      0x005C 0x020C 0x0444 0x2 0x1
+#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                  0x005C 0x020C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI5_SIN                            0x005C 0x020C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI4_SIN                            0x005C 0x020C 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO19__TPM6_CH2                              0x005C 0x020C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00                        0x005C 0x020C 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO20__GPIO2_IO20                            0x0060 0x0210 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00                        0x0060 0x0210 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                      0x0060 0x0210 0x0438 0x2 0x1
+#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                  0x0060 0x0210 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT                           0x0060 0x0210 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT                           0x0060 0x0210 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO20__TPM3_CH1                              0x0060 0x0210 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                      0x0060 0x0210 0x03B4 0x7 0x0
+#define MX93_PAD_GPIO_IO21__GPIO2_IO21                            0x0064 0x0214 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00                        0x0064 0x0214 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO21__PDM_CLK                               0x0064 0x0214 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                  0x0064 0x0214 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI5_SCK                            0x0064 0x0214 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI4_SCK                            0x0064 0x0214 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO21__TPM4_CH1                              0x0064 0x0214 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                          0x0064 0x0214 0x044C 0x7 0x1
+#define MX93_PAD_GPIO_IO22__GPIO2_IO22                            0x0068 0x0218 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO22__USDHC3_CLK                            0x0068 0x0218 0x0458 0x1 0x0
+#define MX93_PAD_GPIO_IO22__SPDIF_IN                              0x0068 0x0218 0x0454 0x2 0x0
+#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                  0x0068 0x0218 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO22__TPM5_CH1                              0x0068 0x0218 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK                           0x0068 0x0218 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA                            0x0068 0x0218 0x03EC 0x16 0x1
+#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                      0x0068 0x0218 0x03B8 0x7 0x0
+#define MX93_PAD_GPIO_IO23__GPIO2_IO23                            0x006C 0x021C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO23__USDHC3_CMD                            0x006C 0x021C 0x045C 0x1 0x0
+#define MX93_PAD_GPIO_IO23__SPDIF_OUT                             0x006C 0x021C 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                  0x006C 0x021C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO23__TPM6_CH1                              0x006C 0x021C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL                            0x006C 0x021C 0x03E8 0x16 0x1
+#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                      0x006C 0x021C 0x03BC 0x7 0x0
+#define MX93_PAD_GPIO_IO24__GPIO2_IO24                            0x0070 0x0220 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0                          0x0070 0x0220 0x0460 0x1 0x0
+#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                  0x0070 0x0220 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO24__TPM3_CH3                              0x0070 0x0220 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO                          0x0070 0x0220 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1                           0x0070 0x0220 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                      0x0070 0x0220 0x03C0 0x7 0x0
+#define MX93_PAD_GPIO_IO25__GPIO2_IO25                            0x0074 0x0224 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x0464 0x1 0x0
+#define MX93_PAD_GPIO_IO25__CAN2_TX                               0x0074 0x0224 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                  0x0074 0x0224 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO25__TPM4_CH3                              0x0074 0x0224 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03D4 0x5 0x1
+#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1                           0x0074 0x0224 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                      0x0074 0x0224 0x03C4 0x7 0x0
+#define MX93_PAD_GPIO_IO26__GPIO2_IO26                            0x0078 0x0228 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2                          0x0078 0x0228 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                      0x0078 0x0228 0x043C 0x2 0x1
+#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                  0x0078 0x0228 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO26__TPM5_CH3                              0x0078 0x0228 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                          0x0078 0x0228 0x03D8 0x5 0x1
+#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1                           0x0078 0x0228 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                          0x0078 0x0228 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO27__GPIO2_IO27                            0x007C 0x022C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3                          0x007C 0x022C 0x046C 0x1 0x0
+#define MX93_PAD_GPIO_IO27__CAN2_RX                               0x007C 0x022C 0x0364 0x2 0x1
+#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                  0x007C 0x022C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO27__TPM6_CH3                              0x007C 0x022C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                          0x007C 0x022C 0x03DC 0x5 0x1
+#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1                           0x007C 0x022C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                      0x007C 0x022C 0x03C8 0x7 0x0
+#define MX93_PAD_GPIO_IO28__GPIO2_IO28                            0x0080 0x0230 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA                            0x0080 0x0230 0x03E4 0x11 0x1
+#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                      0x0080 0x0230 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO29__GPIO2_IO29                            0x0084 0x0234 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL                            0x0084 0x0234 0x03E0 0x11 0x1
+#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                      0x0084 0x0234 0x0000 0x7 0x0
+#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                    0x0088 0x0238 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                      0x0088 0x0238 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO1__GPIO3_IO26                            0x0088 0x0238 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__GPIO3_IO27                            0x008C 0x023C 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                    0x008C 0x023C 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                      0x008C 0x023C 0x03C8 0x4 0x1
+#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                    0x0090 0x0240 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                      0x0090 0x0240 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO3__GPIO4_IO28                            0x0090 0x0240 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                    0x0094 0x0244 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                      0x0094 0x0244 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO4__GPIO4_IO29                            0x0094 0x0244 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC                          0x0098 0x0248 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B                         0x0098 0x0248 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDC__I3C2_SCL                              0x0098 0x0248 0x03CC 0x2 0x0
+#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                       0x0098 0x0248 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00                      0x0098 0x0248 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDC__GPIO4_IO00                            0x0098 0x0248 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                        0x009C 0x024C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B                        0x009C 0x024C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDIO__I3C2_SDA                             0x009C 0x024C 0x03D0 0x2 0x0
+#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                     0x009C 0x024C 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01                     0x009C 0x024C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDIO__GPIO4_IO01                           0x009C 0x024C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                    0x00A0 0x0250 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD3__CAN2_TX                               0x00A0 0x0250 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                       0x00A0 0x0250 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02                      0x00A0 0x0250 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD3__GPIO4_IO02                            0x00A0 0x0250 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                    0x00A4 0x0254 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK   0x00A4 0x0254 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD2__CAN2_RX                               0x00A4 0x0254 0x0364 0x2 0x2
+#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                       0x00A4 0x0254 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03                      0x00A4 0x0254 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD2__GPIO4_IO03                            0x00A4 0x0254 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1                    0x00A8 0x0258 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B                         0x00A8 0x0258 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR                              0x00A8 0x0258 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                       0x00A8 0x0258 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04                      0x00A8 0x0258 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD1__GPIO4_IO04                            0x00A8 0x0258 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR_B                            0x00A8 0x0258 0x0000 0x6 0x0
+#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                    0x00AC 0x025C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD0__LPUART3_TX                            0x00AC 0x025C 0x041C 0x1 0x1
+#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05                      0x00AC 0x025C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD0__GPIO4_IO05                            0x00AC 0x025C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL              0x00B0 0x0260 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B                      0x00B0 0x0260 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06                   0x00B0 0x0260 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                         0x00B0 0x0260 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK    0x00B4 0x0264 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER                        0x00B4 0x0264 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07                      0x00B4 0x0264 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TXC__GPIO4_IO07                            0x00B4 0x0264 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL              0x00B8 0x0268 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B                      0x00B8 0x0268 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                   0x00B8 0x0268 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08                   0x00B8 0x0268 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08                         0x00B8 0x0268 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK    0x00BC 0x026C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER                        0x00BC 0x026C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09                      0x00BC 0x026C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RXC__GPIO4_IO09                            0x00BC 0x026C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                    0x00C0 0x0270 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD0__LPUART3_RX                            0x00C0 0x0270 0x0418 0x1 0x1
+#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                      0x00C0 0x0270 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD0__GPIO4_IO10                            0x00C0 0x0270 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                    0x00C4 0x0274 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B                         0x00C4 0x0274 0x0414 0x1 0x1
+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1                           0x00C4 0x0274 0x0408 0x3 0x0
+#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                      0x00C4 0x0274 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD1__GPIO4_IO11                            0x00C4 0x0274 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                    0x00C8 0x0278 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2                           0x00C8 0x0278 0x040C 0x3 0x0
+#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                      0x00C8 0x0278 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD2__GPIO4_IO12                            0x00C8 0x0278 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                    0x00CC 0x027C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER               0x00CC 0x027C 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3                           0x00CC 0x027C 0x0410 0x3 0x0
+#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                      0x00CC 0x027C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD3__GPIO4_IO13                            0x00CC 0x027C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDC__ENET1_MDC                             0x00D0 0x0280 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B                         0x00D0 0x0280 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC                          0x00D0 0x0280 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                      0x00D0 0x0280 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDC__GPIO4_IO14                            0x00D0 0x0280 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDIO__ENET1_MDIO                           0x00D4 0x0284 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B                        0x00D4 0x0284 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK                         0x00D4 0x0284 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                     0x00D4 0x0284 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDIO__GPIO4_IO15                           0x00D4 0x0284 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00                        0x00D8 0x0288 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                      0x00D8 0x0288 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD3__GPIO4_IO16                            0x00D8 0x0288 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3                       0x00D8 0x0288 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2                       0x00DC 0x028C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK                          0x00DC 0x028C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01                        0x00DC 0x028C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                      0x00DC 0x028C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD2__GPIO4_IO17                            0x00DC 0x028C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1                       0x00E0 0x0290 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B                         0x00E0 0x0290 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02                        0x00E0 0x0290 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                      0x00E0 0x0290 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD1__GPIO4_IO18                            0x00E0 0x0290 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0                       0x00E4 0x0294 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD0__LPUART4_TX                            0x00E4 0x0294 0x0428 0x1 0x1
+#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03                        0x00E4 0x0294 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                      0x00E4 0x0294 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD0__GPIO4_IO19                            0x00E4 0x0294 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL                 0x00E8 0x0298 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B                      0x00E8 0x0298 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                       0x00E8 0x0298 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                   0x00E8 0x0298 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20                         0x00E8 0x0298 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC                       0x00EC 0x029C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_TX_ER                           0x00EC 0x029C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK                          0x00EC 0x029C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                      0x00EC 0x029C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TXC__GPIO4_IO21                            0x00EC 0x029C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL                 0x00F0 0x02A0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B                      0x00F0 0x02A0 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00                     0x00F0 0x02A0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                   0x00F0 0x02A0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22                         0x00F0 0x02A0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC                       0x00F4 0x02A4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RX_ER                           0x00F4 0x02A4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01                        0x00F4 0x02A4 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                      0x00F4 0x02A4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RXC__GPIO4_IO23                            0x00F4 0x02A4 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0                       0x00F8 0x02A8 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD0__LPUART4_RX                            0x00F8 0x02A8 0x0424 0x1 0x1
+#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02                        0x00F8 0x02A8 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                      0x00F8 0x02A8 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD0__GPIO4_IO24                            0x00F8 0x02A8 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1                       0x00FC 0x02AC 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD1__SPDIF_IN                              0x00FC 0x02AC 0x0454 0x1 0x1
+#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03                        0x00FC 0x02AC 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                      0x00FC 0x02AC 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD1__GPIO4_IO25                            0x00FC 0x02AC 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2                       0x0100 0x02B0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B                         0x0100 0x02B0 0x0420 0x1 0x1
+#define MX93_PAD_ENET2_RD2__SAI2_MCLK                             0x0100 0x02B0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD2__MQS2_RIGHT                            0x0100 0x02B0 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                      0x0100 0x02B0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD2__GPIO4_IO26                            0x0100 0x02B0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3                       0x0104 0x02B4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_OUT                             0x0104 0x02B4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_IN                              0x0104 0x02B4 0x0454 0x2 0x2
+#define MX93_PAD_ENET2_RD3__MQS2_LEFT                             0x0104 0x02B4 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                      0x0104 0x02B4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD3__GPIO4_IO27                            0x0104 0x02B4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08                        0x0108 0x02B8 0x038C 0x4 0x1
+#define MX93_PAD_SD1_CLK__GPIO3_IO08                              0x0108 0x02B8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__USDHC1_CLK                              0x0108 0x02B8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__USDHC1_CMD                              0x010C 0x02BC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09                        0x010C 0x02BC 0x0390 0x4 0x1
+#define MX93_PAD_SD1_CMD__GPIO3_IO09                              0x010C 0x02BC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA0__USDHC1_DATA0                          0x0110 0x02C0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                      0x0110 0x02C0 0x0394 0x4 0x1
+#define MX93_PAD_SD1_DATA0__GPIO3_IO10                            0x0110 0x02C0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__USDHC1_DATA1                          0x0114 0x02C4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                      0x0114 0x02C4 0x0398 0x4 0x1
+#define MX93_PAD_SD1_DATA1__GPIO3_IO11                            0x0114 0x02C4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                 0x0114 0x02C4 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA2__USDHC1_DATA2                          0x0118 0x02C8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                      0x0118 0x02C8 0x0000 0x4 0x0
+#define MX93_PAD_SD1_DATA2__GPIO3_IO12                            0x0118 0x02C8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY               0x0118 0x02C8 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA3__USDHC1_DATA3                          0x011C 0x02CC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                      0x011C 0x02CC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                      0x011C 0x02CC 0x039C 0x4 0x1
+#define MX93_PAD_SD1_DATA3__GPIO3_IO13                            0x011C 0x02CC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA4__USDHC1_DATA4                          0x0120 0x02D0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04                     0x0120 0x02D0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                      0x0120 0x02D0 0x03A0 0x4 0x1
+#define MX93_PAD_SD1_DATA4__GPIO3_IO14                            0x0120 0x02D0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_DATA5                          0x0124 0x02D4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05                     0x0124 0x02D4 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B                        0x0124 0x02D4 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                      0x0124 0x02D4 0x03A4 0x4 0x1
+#define MX93_PAD_SD1_DATA5__GPIO3_IO15                            0x0124 0x02D4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_DATA6                          0x0128 0x02D8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06                     0x0128 0x02D8 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_CD_B                           0x0128 0x02D8 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                      0x0128 0x02D8 0x03A8 0x4 0x1
+#define MX93_PAD_SD1_DATA6__GPIO3_IO16                            0x0128 0x02D8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_DATA7                          0x012C 0x02DC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07                     0x012C 0x02DC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_WP                             0x012C 0x02DC 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                      0x012C 0x02DC 0x03AC 0x4 0x1
+#define MX93_PAD_SD1_DATA7__GPIO3_IO17                            0x012C 0x02DC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_STROBE__USDHC1_STROBE                        0x0130 0x02E0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS                       0x0130 0x02E0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                     0x0130 0x02E0 0x03B0 0x4 0x1
+#define MX93_PAD_SD1_STROBE__GPIO3_IO18                           0x0130 0x02E0 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT                      0x0134 0x02E4 0x0000 0x0 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_WP                           0x0134 0x02E4 0x0000 0x1 0x0
+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                         0x0134 0x02E4 0x0410 0x2 0x1
+#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                    0x0134 0x02E4 0x0000 0x4 0x0
+#define MX93_PAD_SD2_VSELECT__GPIO3_IO19                          0x0134 0x02E4 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1               0x0134 0x02E4 0x0368 0x6 0x0
+#define MX93_PAD_SD3_CLK__USDHC3_CLK                              0x0138 0x02E8 0x0458 0x0 0x1
+#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK                         0x0138 0x02E8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20                        0x0138 0x02E8 0x03B4 0x4 0x1
+#define MX93_PAD_SD3_CLK__GPIO3_IO20                              0x0138 0x02E8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_CMD__USDHC3_CMD                              0x013C 0x02EC 0x045C 0x0 0x1
+#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                        0x013C 0x02EC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21                        0x013C 0x02EC 0x0000 0x4 0x0
+#define MX93_PAD_SD3_CMD__GPIO3_IO21                              0x013C 0x02EC 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0                          0x0140 0x02F0 0x0460 0x0 0x1
+#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00                     0x0140 0x02F0 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                      0x0140 0x02F0 0x03B8 0x4 0x1
+#define MX93_PAD_SD3_DATA0__GPIO3_IO22                            0x0140 0x02F0 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1                          0x0144 0x02F4 0x0464 0x0 0x1
+#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01                     0x0144 0x02F4 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                      0x0144 0x02F4 0x03BC 0x4 0x1
+#define MX93_PAD_SD3_DATA1__GPIO3_IO23                            0x0144 0x02F4 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2                          0x0148 0x02F8 0x0468 0x0 0x1
+#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02                     0x0148 0x02F8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                      0x0148 0x02F8 0x03C0 0x4 0x1
+#define MX93_PAD_SD3_DATA2__GPIO3_IO24                            0x0148 0x02F8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3                          0x014C 0x02FC 0x046C 0x0 0x1
+#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03                     0x014C 0x02FC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                      0x014C 0x02FC 0x03C4 0x4 0x1
+#define MX93_PAD_SD3_DATA3__GPIO3_IO25                            0x014C 0x02FC 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CD_B__USDHC2_CD_B                            0x0150 0x0300 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                0x0150 0x0300 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CD_B__I3C2_SCL                               0x0150 0x0300 0x03CC 0x2 0x1
+#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00                       0x0150 0x0300 0x036C 0x4 0x1
+#define MX93_PAD_SD2_CD_B__GPIO3_IO00                             0x0150 0x0300 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__USDHC2_CLK                              0x0154 0x0304 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                0x0154 0x0304 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CLK__I3C2_SDA                                0x0154 0x0304 0x03D0 0x2 0x1
+#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01                        0x0154 0x0304 0x0370 0x4 0x1
+#define MX93_PAD_SD2_CLK__GPIO3_IO01                              0x0154 0x0304 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                   0x0154 0x0304 0x0000 0x6 0x0
+#define MX93_PAD_SD2_CMD__USDHC2_CMD                              0x0158 0x0308 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN                    0x0158 0x0308 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR                                0x0158 0x0308 0x0000 0x2 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR_B                              0x0158 0x0308 0x0000 0x3 0x0
+#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02                        0x0158 0x0308 0x0374 0x4 0x1
+#define MX93_PAD_SD2_CMD__GPIO3_IO02                              0x0158 0x0308 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                   0x0158 0x0308 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA0__USDHC2_DATA0                          0x015C 0x030C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT                 0x015C 0x030C 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA0__CAN2_TX                               0x015C 0x030C 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03                      0x015C 0x030C 0x0378 0x4 0x1
+#define MX93_PAD_SD2_DATA0__GPIO3_IO03                            0x015C 0x030C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                 0x015C 0x030C 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA1__USDHC2_DATA1                          0x0160 0x0310 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN                  0x0160 0x0310 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA1__CAN2_RX                               0x0160 0x0310 0x0364 0x2 0x3
+#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04                      0x0160 0x0310 0x037C 0x4 0x1
+#define MX93_PAD_SD2_DATA1__GPIO3_IO04                            0x0160 0x0310 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                     0x0160 0x0310 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA2__USDHC2_DATA2                          0x0164 0x0314 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT                 0x0164 0x0314 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA2__MQS2_RIGHT                            0x0164 0x0314 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05                      0x0164 0x0314 0x0380 0x4 0x1
+#define MX93_PAD_SD2_DATA2__GPIO3_IO05                            0x0164 0x0314 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                     0x0164 0x0314 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA3__USDHC2_DATA3                          0x0168 0x0318 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1                           0x0168 0x0318 0x0408 0x1 0x1
+#define MX93_PAD_SD2_DATA3__MQS2_LEFT                             0x0168 0x0318 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06                      0x0168 0x0318 0x0384 0x4 0x1
+#define MX93_PAD_SD2_DATA3__GPIO3_IO06                            0x0168 0x0318 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET              0x0168 0x0318 0x0000 0x6 0x0
+#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B                      0x016C 0x031C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                         0x016C 0x031C 0x040C 0x1 0x1
+#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07                    0x016C 0x031C 0x0388 0x4 0x1
+#define MX93_PAD_SD2_RESET_B__GPIO3_IO07                          0x016C 0x031C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET           0x016C 0x031C 0x0000 0x6 0x0
+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL                             0x0170 0x0320 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SCL__I3C1_SCL                               0x0170 0x0320 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B                          0x0170 0x0320 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SCL__TPM2_CH0                               0x0170 0x0320 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SCL__GPIO1_IO00                             0x0170 0x0320 0x0000 0x5 0x0
+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA                             0x0174 0x0324 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SDA__I3C1_SDA                               0x0174 0x0324 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B                          0x0174 0x0324 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SDA__TPM2_CH1                               0x0174 0x0324 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SDA__GPIO1_IO01                             0x0174 0x0324 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL                             0x0178 0x0328 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR                               0x0178 0x0328 0x0000 0x1 0x0
+#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B                          0x0178 0x0328 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SCL__TPM2_CH2                               0x0178 0x0328 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC                           0x0178 0x0328 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SCL__GPIO1_IO02                             0x0178 0x0328 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR_B                             0x0178 0x0328 0x0000 0x6 0x0
+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA                             0x017C 0x032C 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B                          0x017C 0x032C 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SDA__TPM2_CH3                               0x017C 0x032C 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK                           0x017C 0x032C 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SDA__GPIO1_IO03                             0x017C 0x032C 0x0000 0x5 0x0
+#define MX93_PAD_UART1_RXD__LPUART1_RX                            0x0180 0x0330 0x0000 0x0 0x0
+#define MX93_PAD_UART1_RXD__S400_UART_RX                          0x0180 0x0330 0x0000 0x1 0x0
+#define MX93_PAD_UART1_RXD__LPSPI2_SIN                            0x0180 0x0330 0x0000 0x2 0x0
+#define MX93_PAD_UART1_RXD__TPM1_CH0                              0x0180 0x0330 0x0000 0x3 0x0
+#define MX93_PAD_UART1_RXD__GPIO1_IO04                            0x0180 0x0330 0x0000 0x5 0x0
+#define MX93_PAD_UART1_TXD__LPUART1_TX                            0x0184 0x0334 0x0000 0x0 0x0
+#define MX93_PAD_UART1_TXD__S400_UART_TX                          0x0184 0x0334 0x0000 0x1 0x0
+#define MX93_PAD_UART1_TXD__LPSPI2_PCS0                           0x0184 0x0334 0x0000 0x2 0x0
+#define MX93_PAD_UART1_TXD__TPM1_CH1                              0x0184 0x0334 0x0000 0x3 0x0
+#define MX93_PAD_UART1_TXD__GPIO1_IO05                            0x0184 0x0334 0x0000 0x5 0x0
+#define MX93_PAD_UART2_RXD__LPUART2_RX                            0x0188 0x0338 0x0000 0x0 0x0
+#define MX93_PAD_UART2_RXD__LPUART1_CTS_B                         0x0188 0x0338 0x0000 0x1 0x0
+#define MX93_PAD_UART2_RXD__LPSPI2_SOUT                           0x0188 0x0338 0x0000 0x2 0x0
+#define MX93_PAD_UART2_RXD__TPM1_CH2                              0x0188 0x0338 0x0000 0x3 0x0
+#define MX93_PAD_UART2_RXD__SAI1_MCLK                             0x0188 0x0338 0x0448 0x4 0x0
+#define MX93_PAD_UART2_RXD__GPIO1_IO06                            0x0188 0x0338 0x0000 0x5 0x0
+#define MX93_PAD_UART2_TXD__LPUART2_TX                            0x018C 0x033C 0x0000 0x0 0x0
+#define MX93_PAD_UART2_TXD__LPUART1_RTS_B                         0x018C 0x033C 0x0000 0x1 0x0
+#define MX93_PAD_UART2_TXD__LPSPI2_SCK                            0x018C 0x033C 0x0000 0x2 0x0
+#define MX93_PAD_UART2_TXD__TPM1_CH3                              0x018C 0x033C 0x0000 0x3 0x0
+#define MX93_PAD_UART2_TXD__GPIO1_IO07                            0x018C 0x033C 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__PDM_CLK                                 0x0190 0x0340 0x0000 0x0 0x0
+#define MX93_PAD_PDM_CLK__MQS1_LEFT                               0x0190 0x0340 0x0000 0x1 0x0
+#define MX93_PAD_PDM_CLK__LPTMR1_ALT1                             0x0190 0x0340 0x0000 0x4 0x0
+#define MX93_PAD_PDM_CLK__GPIO1_IO08                              0x0190 0x0340 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__CAN1_TX                                 0x0190 0x0340 0x0000 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00                0x0194 0x0344 0x0438 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                      0x0194 0x0344 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                     0x0194 0x0344 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                     0x0194 0x0344 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                     0x0194 0x0344 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09                      0x0194 0x0344 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX                         0x0194 0x0344 0x0360 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01                0x0198 0x0348 0x043C 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                    0x0198 0x0348 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                     0x0198 0x0348 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                     0x0198 0x0348 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                     0x0198 0x0348 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10                      0x0198 0x0348 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1           0x0198 0x0348 0x0368 0x6 0x1
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC                          0x019C 0x034C 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01                        0x019C 0x034C 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0                           0x019C 0x034C 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B                         0x019C 0x034C 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXFS__MQS1_LEFT                             0x019C 0x034C 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXFS__GPIO1_IO11                            0x019C 0x034C 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK                           0x01A0 0x0350 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B                          0x01A0 0x0350 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXC__LPSPI1_SIN                             0x01A0 0x0350 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B                          0x01A0 0x0350 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXC__CAN1_RX                                0x01A0 0x0350 0x0360 0x4 0x1
+#define MX93_PAD_SAI1_TXC__GPIO1_IO12                             0x01A0 0x0350 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00                        0x01A4 0x0354 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B                         0x01A4 0x0354 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK                            0x01A4 0x0354 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B                         0x01A4 0x0354 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXD0__CAN1_TX                               0x01A4 0x0354 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXD0__GPIO1_IO13                            0x01A4 0x0354 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00                        0x01A8 0x0358 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK                             0x01A8 0x0358 0x0448 0x1 0x1
+#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT                           0x01A8 0x0358 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B                         0x01A8 0x0358 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT                            0x01A8 0x0358 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_RXD0__GPIO1_IO14                            0x01A8 0x0358 0x0000 0x5 0x0
+#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY                         0x01AC 0x035C 0x0000 0x0 0x0
+#define MX93_PAD_WDOG_ANY__GPIO1_IO15                             0x01AC 0x035C 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX93_PINFUNC_H */
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
new file mode 100644
index 000000000000..f83a07c7c9b1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx93-pinfunc.h"
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		serial0 = &lpuart1;
+		serial1 = &lpuart2;
+		serial2 = &lpuart3;
+		serial3 = &lpuart4;
+		serial4 = &lpuart5;
+		serial5 = &lpuart6;
+		serial6 = &lpuart7;
+		serial7 = &lpuart8;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A55_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+		};
+
+		A55_1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+		};
+
+	};
+
+	osc_32k: clock-osc-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "osc_32k";
+	};
+
+	osc_24m: clock-osc-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc_24m";
+	};
+
+	clk_ext1: clock-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		arm,no-tick-in-suspend;
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@48000000 {
+		compatible = "arm,gic-v3";
+		reg = <0 0x48000000 0 0x10000>,
+		      <0 0x48040000 0 0xc0000>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x80000000>,
+			 <0x28000000 0x0 0x28000000 0x10000000>;
+
+		aips1: bus@44000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x44000000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mu1: mailbox@44230000 {
+				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+				reg = <0x44230000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			system_counter: timer@44290000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x44290000 0x30000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_24m>;
+				clock-names = "per";
+			};
+
+			lpuart1: serial@44380000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x44380000 0x1000>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART1_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart2: serial@44390000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x44390000 0x1000>;
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART2_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			iomuxc: pinctrl@443c0000 {
+				compatible = "fsl,imx93-iomuxc";
+				reg = <0x443c0000 0x10000>;
+				status = "okay";
+			};
+
+			clk: clock-controller@44450000 {
+				compatible = "fsl,imx93-ccm";
+				reg = <0x44450000 0x10000>;
+				#clock-cells = <1>;
+				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
+				clock-names = "osc_32k", "osc_24m", "clk_ext1";
+				status = "okay";
+			};
+
+			anatop: anatop@44480000 {
+				compatible = "fsl,imx93-anatop", "syscon";
+				reg = <0x44480000 0x10000>;
+			};
+		};
+
+		aips2: bus@42000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x42000000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mu2: mailbox@42440000 {
+				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+				reg = <0x42440000 0x10000>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			lpuart3: serial@42570000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42570000 0x1000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart4: serial@42580000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42580000 0x1000>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart5: serial@42590000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42590000 0x1000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart6: serial@425a0000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x425a0000 0x1000>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart7: serial@42690000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42690000 0x1000>;
+				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART7_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart8: serial@426a0000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x426a0000 0x1000>;
+				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART8_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+		};
+
+		aips3: bus@42800000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x42800000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usdhc1: mmc@42850000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x42850000 0x10000>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC1_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <8>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+
+			usdhc2: mmc@42860000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x42860000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC2_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+
+			usdhc3: mmc@428b0000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x428b0000 0x10000>;
+				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC3_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+		};
+
+		gpio2: gpio@43810080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&iomuxc 0 32 32>;
+		};
+
+		gpio3: gpio@43820080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&iomuxc 0 64 32>;
+		};
+
+		gpio4: gpio@43830080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&iomuxc 0 96 32>;
+		};
+
+		gpio1: gpio@47400080 {
+			compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&iomuxc 0 0 32>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
index c2f0f1a1566c..104bdd4e437a 100644
--- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi
+++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
@@ -16,7 +16,6 @@ beeper {
 	};
 
 	chosen {
-		// bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200";
 		stdout-path = &uart3;
 	};
 
@@ -26,21 +25,21 @@ gpio-keys {
 		pinctrl-0 = <&pinctrl_gpiobutton>;
 		autorepeat;
 
-		switch1 {
+		switch-1 {
 			label = "switch1";
 			linux,code = <BTN_0>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 			wakeup-source;
 		};
 
-		btn2: switch2 {
+		btn2: switch-2 {
 			label = "switch2";
 			linux,code = <BTN_1>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 			wakeup-source;
 		};
 
-		switch3 {
+		switch-3 {
 			label = "switch3";
 			linux,code = <BTN_2>;
 			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
@@ -272,7 +271,6 @@ &uart3 {
 	status = "okay";
 };
 
-/* UART4 is assigned to Cortex-M4 */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 59ea8a25aa4c..824d401e7a2c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -79,7 +79,7 @@ psci {
 		};
 	};
 
-	soc {
+	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index f68580dc87d8..0192a01bf852 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -49,9 +49,9 @@ reserved-memory {
 		ramoops@32000000 {
 			compatible = "ramoops";
 			reg = <0x0 0x32000000 0x0 0x00100000>;
-			record-size	= <0x00020000>;
-			console-size	= <0x00020000>;
-			ftrace-size	= <0x00020000>;
+			record-size = <0x00020000>;
+			console-size = <0x00020000>;
+			ftrace-size = <0x00020000>;
 		};
 	};
 
@@ -63,9 +63,9 @@ reboot-mode {
 			compatible = "syscon-reboot-mode";
 			offset = <0x0>;
 
-			mode-normal	= <0x77665501>;
-			mode-bootloader	= <0x77665500>;
-			mode-recovery	= <0x77665502>;
+			mode-normal = <0x77665501>;
+			mode-bootloader = <0x77665500>;
+			mode-recovery = <0x77665502>;
 		};
 	};
 
@@ -74,7 +74,7 @@ keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 6b3057a09251..8343d0cedde3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -479,7 +479,7 @@ uart1: serial@fdf00000 {
 			reg = <0x0 0xfdf00000 0x0 0x1000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			dma-names = "rx", "tx";
-			dmas =  <&dma0 2 &dma0 3>;
+			dmas = <&dma0 2 &dma0 3>;
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
 				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
 			clock-names = "uartclk", "apb_pclk";
@@ -493,7 +493,7 @@ uart2: serial@fdf03000 {
 			reg = <0x0 0xfdf03000 0x0 0x1000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			dma-names = "rx", "tx";
-			dmas =  <&dma0 4 &dma0 5>;
+			dmas = <&dma0 4 &dma0 5>;
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
 				 <&crg_ctrl HI3660_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -519,7 +519,7 @@ uart4: serial@fdf01000 {
 			reg = <0x0 0xfdf01000 0x0 0x1000>;
 			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 			dma-names = "rx", "tx";
-			dmas =  <&dma0 6 &dma0 7>;
+			dmas = <&dma0 6 &dma0 7>;
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
 				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
 			clock-names = "uartclk", "apb_pclk";
@@ -533,7 +533,7 @@ uart5: serial@fdf05000 {
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			dma-names = "rx", "tx";
-			dmas =  <&dma0 8 &dma0 9>;
+			dmas = <&dma0 8 &dma0 9>;
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
 				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
 			clock-names = "uartclk", "apb_pclk";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 3125c3869c69..886b93c5893a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -324,7 +324,7 @@ gpio3: gpio@e8a0e000 {
 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges =  <&pmx0 0 13 4 &pmx0 7 17 1>;
+			gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 3df2afb2f637..629e604aa281 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -54,9 +54,9 @@ reserved-memory {
 		ramoops@21f00000 {
 			compatible = "ramoops";
 			reg = <0x0 0x21f00000 0x0 0x00100000>;
-			record-size	= <0x00020000>;
-			console-size	= <0x00020000>;
-			ftrace-size	= <0x00020000>;
+			record-size = <0x00020000>;
+			console-size = <0x00020000>;
+			ftrace-size = <0x00020000>;
 		};
 
 		/* global autoconfigured region for contiguous allocations */
@@ -76,9 +76,9 @@ reboot-mode {
 			compatible = "syscon-reboot-mode";
 			offset = <0x0>;
 
-			mode-normal	= <0x77665501>;
-			mode-bootloader	= <0x77665500>;
-			mode-recovery	= <0x77665502>;
+			mode-normal = <0x77665501>;
+			mode-bootloader = <0x77665500>;
+			mode-recovery = <0x77665502>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index 40f3e00ac832..c4eaebbb448f 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -27,12 +27,10 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		pwrbutton {
+		pwr-button {
 			label = "Power Button";
 			gpios = <&porta 8 GPIO_ACTIVE_LOW>;
 			linux,code = <116>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 70d7732dd348..2f8b03b0d365 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -537,7 +537,7 @@ port@0 {
 
 			port@1 {
 				reg = <1>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				port-rst-offset = <1>;
 				port-mode-offset = <1>;
 				media-type = "fiber";
@@ -546,7 +546,7 @@ port@1 {
 			port@4 {
 				reg = <4>;
 				phy-handle = <&phy0>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				port-rst-offset = <4>;
 				port-mode-offset = <2>;
 				media-type = "copper";
@@ -555,7 +555,7 @@ port@4 {
 			port@5 {
 				reg = <5>;
 				phy-handle = <&phy1>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				port-rst-offset = <5>;
 				port-mode-offset = <3>;
 				media-type = "copper";
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 6baf6a686450..1a16662f8867 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1422,7 +1422,7 @@ port@0 {
 
 			port@1 {
 				reg = <1>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				cpld-syscon = <&dsa_cpld 0x4>;
 				port-rst-offset = <1>;
 				port-mode-offset = <1>;
@@ -1433,7 +1433,7 @@ port@1 {
 			port@4 {
 				reg = <4>;
 				phy-handle = <&phy0>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				port-rst-offset = <4>;
 				port-mode-offset = <2>;
 				mc-mac-mask = [ff f0 00 00 00 00];
@@ -1443,7 +1443,7 @@ port@4 {
 			port@5 {
 				reg = <5>;
 				phy-handle = <&phy1>;
-				serdes-syscon= <&serdes_ctrl>;
+				serdes-syscon = <&serdes_ctrl>;
 				port-rst-offset = <5>;
 				port-mode-offset = <3>;
 				mc-mac-mask = [ff f0 00 00 00 00];
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index bec97480a960..78ae73d0cf36 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -52,7 +52,7 @@ L2_0: l2-cache0 {
 	};
 
 	psci {
-		compatible  = "arm,psci-0.2", "arm,psci";
+		compatible = "arm,psci-0.2", "arm,psci";
 		method = "smc";
 		cpu_suspend = <0x84000001>;
 		cpu_off = <0x84000002>;
@@ -150,7 +150,7 @@ uart0: serial@fe000000 {
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		uart1: serial@fe100000 {
 			compatible = "arm,pl011", "arm,primecell";
@@ -158,7 +158,7 @@ uart1: serial@fe100000 {
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		uart2: serial@fe200000 {
 			compatible = "arm,pl011", "arm,primecell";
@@ -166,7 +166,7 @@ uart2: serial@fe200000 {
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		spi0: spi@fe800000 {
 			compatible = "arm,pl022", "arm,primecell";
@@ -197,7 +197,7 @@ gpio0: gpio@fd400000 {
 			reg = <0x0 0xfd400000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio1: gpio@fd410000 {
 			#gpio-cells = <2>;
@@ -206,7 +206,7 @@ gpio1: gpio@fd410000 {
 			reg = <0x0 0xfd410000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio2: gpio@fd420000 {
 			#gpio-cells = <2>;
@@ -215,7 +215,7 @@ gpio2: gpio@fd420000 {
 			reg = <0x0 0xfd420000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio3: gpio@fd430000 {
 			#gpio-cells = <2>;
@@ -232,7 +232,7 @@ gpio4: gpio@fd440000 {
 			reg = <0x0 0xfd440000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio5: gpio@fd450000 {
 			#gpio-cells = <2>;
@@ -241,7 +241,7 @@ gpio5: gpio@fd450000 {
 			reg = <0x0 0xfd450000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio6: gpio@fd460000 {
 			#gpio-cells = <2>;
@@ -250,7 +250,7 @@ gpio6: gpio@fd460000 {
 			reg = <0x0 0xfd460000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio7: gpio@fd470000 {
 			#gpio-cells = <2>;
@@ -259,7 +259,7 @@ gpio7: gpio@fd470000 {
 			reg = <0x0 0xfd470000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio8: gpio@fd480000 {
 			#gpio-cells = <2>;
@@ -268,7 +268,7 @@ gpio8: gpio@fd480000 {
 			reg = <0x0 0xfd480000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio9: gpio@fd490000 {
 			#gpio-cells = <2>;
@@ -277,7 +277,7 @@ gpio9: gpio@fd490000 {
 			reg = <0x0 0xfd490000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio10: gpio@fd4a0000 {
 			#gpio-cells = <2>;
@@ -286,7 +286,7 @@ gpio10: gpio@fd4a0000 {
 			reg = <0x0 0xfd4a0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio11: gpio@fd4b0000 {
 			#gpio-cells = <2>;
@@ -303,7 +303,7 @@ gpio12: gpio@fd4c0000 {
 			reg = <0x0 0xfd4c0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio13: gpio@fd4d0000 {
 			#gpio-cells = <2>;
@@ -312,7 +312,7 @@ gpio13: gpio@fd4d0000 {
 			reg = <0x0 0xfd4d0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio14: gpio@fd4e0000 {
 			#gpio-cells = <2>;
@@ -321,7 +321,7 @@ gpio14: gpio@fd4e0000 {
 			reg = <0x0 0xfd4e0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio15: gpio@fd4f0000 {
 			#gpio-cells = <2>;
@@ -330,7 +330,7 @@ gpio15: gpio@fd4f0000 {
 			reg = <0x0 0xfd4f0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio16: gpio@fd500000 {
 			#gpio-cells = <2>;
@@ -339,7 +339,7 @@ gpio16: gpio@fd500000 {
 			reg = <0x0 0xfd500000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio17: gpio@fd510000 {
 			#gpio-cells = <2>;
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index ada3d4dc6305..2173316573be 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -52,7 +52,7 @@ L2_0: l2-cache0 {
 	};
 
 	psci {
-		compatible  = "arm,psci-0.2", "arm,psci";
+		compatible = "arm,psci-0.2", "arm,psci";
 		method = "smc";
 		cpu_suspend = <0x84000001>;
 		cpu_off = <0x84000002>;
@@ -150,7 +150,7 @@ uart0: serial@fe000000 {
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		uart1: serial@fe100000 {
 			compatible = "arm,pl011", "arm,primecell";
@@ -158,7 +158,7 @@ uart1: serial@fe100000 {
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		uart2: serial@fe200000 {
 			compatible = "arm,pl011", "arm,primecell";
@@ -166,7 +166,7 @@ uart2: serial@fe200000 {
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		spi0: spi@fe800000 {
 			compatible = "arm,pl022", "arm,primecell";
@@ -197,7 +197,7 @@ gpio0: gpio@fd400000 {
 			reg = <0x0 0xfd400000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio1: gpio@fd410000 {
 			#gpio-cells = <2>;
@@ -206,7 +206,7 @@ gpio1: gpio@fd410000 {
 			reg = <0x0 0xfd410000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio2: gpio@fd420000 {
 			#gpio-cells = <2>;
@@ -215,7 +215,7 @@ gpio2: gpio@fd420000 {
 			reg = <0x0 0xfd420000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio3: gpio@fd430000 {
 			#gpio-cells = <2>;
@@ -232,7 +232,7 @@ gpio4: gpio@fd440000 {
 			reg = <0x0 0xfd440000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio5: gpio@fd450000 {
 			#gpio-cells = <2>;
@@ -241,7 +241,7 @@ gpio5: gpio@fd450000 {
 			reg = <0x0 0xfd450000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio6: gpio@fd460000 {
 			#gpio-cells = <2>;
@@ -250,7 +250,7 @@ gpio6: gpio@fd460000 {
 			reg = <0x0 0xfd460000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio7: gpio@fd470000 {
 			#gpio-cells = <2>;
@@ -259,7 +259,7 @@ gpio7: gpio@fd470000 {
 			reg = <0x0 0xfd470000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio8: gpio@fd480000 {
 			#gpio-cells = <2>;
@@ -268,7 +268,7 @@ gpio8: gpio@fd480000 {
 			reg = <0x0 0xfd480000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio9: gpio@fd490000 {
 			#gpio-cells = <2>;
@@ -277,7 +277,7 @@ gpio9: gpio@fd490000 {
 			reg = <0x0 0xfd490000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio10: gpio@fd4a0000 {
 			#gpio-cells = <2>;
@@ -286,7 +286,7 @@ gpio10: gpio@fd4a0000 {
 			reg = <0x0 0xfd4a0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio11: gpio@fd4b0000 {
 			#gpio-cells = <2>;
@@ -303,7 +303,7 @@ gpio12: gpio@fd4c0000 {
 			reg = <0x0 0xfd4c0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio13: gpio@fd4d0000 {
 			#gpio-cells = <2>;
@@ -312,7 +312,7 @@ gpio13: gpio@fd4d0000 {
 			reg = <0x0 0xfd4d0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio14: gpio@fd4e0000 {
 			#gpio-cells = <2>;
@@ -321,7 +321,7 @@ gpio14: gpio@fd4e0000 {
 			reg = <0x0 0xfd4e0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio15: gpio@fd4f0000 {
 			#gpio-cells = <2>;
@@ -330,7 +330,7 @@ gpio15: gpio@fd4f0000 {
 			reg = <0x0 0xfd4f0000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio16: gpio@fd500000 {
 			#gpio-cells = <2>;
@@ -339,7 +339,7 @@ gpio16: gpio@fd500000 {
 			reg = <0x0 0xfd500000 0x1000>;
 			clocks = <&clk_bus>;
 			clock-names = "apb_pclk";
-			status="disabled";
+			status = "disabled";
 		};
 		gpio17: gpio@fd510000 {
 			#gpio-cells = <2>;
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
index 39a8e5e99d79..b9ba7c452a77 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
@@ -37,7 +37,7 @@ sfp_eth0: sfp-eth0 {
 		los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	/* SFP 1G */
@@ -47,7 +47,7 @@ sfp_eth2: sfp-eth2 {
 		los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 779cf167c33e..c0389dd17340 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -68,7 +68,7 @@ sfp_eth0: sfp-eth0 {
 		los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&cp1_sfpp0_pins>;
 		maximum-power-milliwatt = <2000>;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
index 74bed79e4f5e..cf868e0bbb9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
@@ -70,7 +70,7 @@ sfp_cp0_eth0: sfp-cp0-eth0 {
 		los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>;
 		maximum-power-milliwatt = <3000>;
 	};
 
@@ -80,7 +80,7 @@ sfp_cp1_eth0: sfp-cp1-eth0 {
 		los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>;
 		maximum-power-milliwatt = <3000>;
 	};
 
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index 7e20987253a3..f58402eb9536 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -404,7 +404,7 @@ &cp0_usb3_0 {
 &cp0_usb3_1 {
 	status = "okay";
 	usb-phy = <&cp0_usb3_0_phy1>;
-	phys =  <&cp0_utmi1>;
+	phys = <&cp0_utmi1>;
 	phy-names = "utmi";
 	dr_mode = "host";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 11aa135aa0f3..9b1af9c80130 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -106,7 +106,7 @@ &cpu2 {
 };
 
 &eth {
-	phy-mode ="rgmii-rxid";
+	phy-mode = "rgmii-rxid";
 	phy-handle = <&ethernet_phy0>;
 	mediatek,tx-delay-ps = <1530>;
 	snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 623eb3beabf2..4797537cb368 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -329,6 +329,7 @@ iommu0: iommu@10205000 {
 		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
+		mediatek,infracfg = <&infracfg>;
 		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
 				 <&larb3>, <&larb6>;
 		#iommu-cells = <1>;
@@ -346,6 +347,7 @@ iommu1: iommu@1020a000 {
 		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
+		mediatek,infracfg = <&infracfg>;
 		mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
 		#iommu-cells = <1>;
 	};
diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi
index 01ba77669717..b55d3fac9bd4 100644
--- a/arch/arm64/boot/dts/mediatek/mt6755.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi
@@ -1,14 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016 MediaTek Inc.
  * Author: Mars.C <mars.cheng@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index c85659d0ff5d..d4842b4a4eb7 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -1,18 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2015 MediaTek Inc.
  * Author: Mars.C <mars.cheng@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
 
 / {
 	compatible = "mediatek,mt6795";
@@ -34,6 +28,8 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			cci-control-port = <&cci_control2>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu1: cpu@1 {
@@ -41,6 +37,8 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			cci-control-port = <&cci_control2>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu2: cpu@2 {
@@ -48,6 +46,8 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			cci-control-port = <&cci_control2>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu3: cpu@3 {
@@ -55,6 +55,8 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			cci-control-port = <&cci_control2>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu4: cpu@100 {
@@ -62,6 +64,8 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			cci-control-port = <&cci_control1>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu5: cpu@101 {
@@ -69,6 +73,8 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			cci-control-port = <&cci_control1>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu6: cpu@102 {
@@ -76,6 +82,8 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			cci-control-port = <&cci_control1>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu7: cpu@103 {
@@ -83,27 +91,88 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			cci-control-port = <&cci_control1>;
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
-	system_clk: dummy13m {
+	clk26m: oscillator-26m {
 		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
 		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
 	};
 
-	rtc_clk: dummy32k {
+	clk32k: oscillator-32k {
 		compatible = "fixed-clock";
-		clock-frequency = <32000>;
 		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
 	};
 
-	uart_clk: dummy26m {
+	system_clk: dummy13m {
 		compatible = "fixed-clock";
-		clock-frequency = <26000000>;
+		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
@@ -117,59 +186,133 @@ timer {
 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	sysirq: intpol-controller@10200620 {
-		compatible = "mediatek,mt6795-sysirq",
-			     "mediatek,mt6577-sysirq";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		reg = <0 0x10200620 0 0x20>;
-	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
 
-	gic: interrupt-controller@10221000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x10221000 0 0x1000>,
-		      <0 0x10222000 0 0x2000>,
-		      <0 0x10224000 0 0x2000>,
-		      <0 0x10226000 0 0x2000>;
-	};
+		pio: pinctrl@10005000 {
+			compatible = "mediatek,mt6795-pinctrl";
+			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
+			reg-names = "base", "eint";
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 196>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		watchdog: watchdog@10007000 {
+			compatible = "mediatek,mt6795-wdt";
+			reg = <0 0x10007000 0 0x100>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+			#reset-cells = <1>;
+			timeout-sec = <20>;
+		};
 
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		timer: timer@10008000 {
+			compatible = "mediatek,mt6795-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&system_clk>, <&clk32k>;
+		};
 
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		sysirq: intpol-controller@10200620 {
+			compatible = "mediatek,mt6795-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10200620 0 0x20>;
+		};
+
+		gic: interrupt-controller@10221000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10221000 0 0x1000>,
+			      <0 0x10222000 0 0x2000>,
+			      <0 0x10224000 0 0x2000>,
+			      <0 0x10226000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		cci: cci@10390000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0 0x10390000 0 0x1000>;
+			ranges = <0 0 0x10390000 0x10000>;
 
-	uart3: serial@11005000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11005000 0 0x400>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
+			cci_control0: slave-if@1000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace-lite";
+				reg = <0x1000 0x1000>;
+			};
+
+			cci_control1: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control2: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&clk26m>;
+			status = "disabled";
+		};
+
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&clk26m>;
+			status = "disabled";
+		};
+
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&clk26m>;
+			status = "disabled";
+		};
+
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&clk26m>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 2b9bf8dd14ec..7b81eac934c5 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 
 #include "mt7622.dtsi"
 #include "mt6380.dtsi"
@@ -40,13 +41,13 @@ cpu@1 {
 	gpio-keys {
 		compatible = "gpio-keys";
 
-		factory {
+		factory-key {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
 		};
 
-		wps {
+		wps-key {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
@@ -56,14 +57,16 @@ wps {
 	leds {
 		compatible = "gpio-leds";
 
-		green {
+		led-0 {
 			label = "bpi-r64:pio:green";
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		red {
+		led-1 {
 			label = "bpi-r64:pio:red";
+			color = <LED_COLOR_ID_RED>;
 			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
@@ -336,14 +339,14 @@ mux {
 	i2c1_pins: i2c1-pins {
 		mux {
 			function = "i2c";
-			groups =  "i2c1_0";
+			groups = "i2c1_0";
 		};
 	};
 
 	i2c2_pins: i2c2-pins {
 		mux {
 			function = "i2c";
-			groups =  "i2c2_0";
+			groups = "i2c2_0";
 		};
 	};
 
@@ -366,14 +369,14 @@ conf {
 	irrx_pins: irrx-pins {
 		mux {
 			function = "ir";
-			groups =  "ir_1_rx";
+			groups = "ir_1_rx";
 		};
 	};
 
 	irtx_pins: irtx-pins {
 		mux {
 			function = "ir";
-			groups =  "ir_1_tx";
+			groups = "ir_1_tx";
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 596c073d8b05..36722cabe626 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -40,15 +40,14 @@ cpu@1 {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		poll-interval = <100>;
 
-		factory {
+		key-factory {
 			label = "factory";
 			linux,code = <BTN_0>;
 			gpios = <&pio 0 0>;
 		};
 
-		wps {
+		key-wps {
 			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&pio 102 0>;
@@ -298,14 +297,14 @@ mux {
 	i2c1_pins: i2c1-pins {
 		mux {
 			function = "i2c";
-			groups =  "i2c1_0";
+			groups = "i2c1_0";
 		};
 	};
 
 	i2c2_pins: i2c2-pins {
 		mux {
 			function = "i2c";
-			groups =  "i2c2_0";
+			groups = "i2c2_0";
 		};
 	};
 
@@ -328,14 +327,14 @@ conf {
 	irrx_pins: irrx-pins {
 		mux {
 			function = "ir";
-			groups =  "ir_1_rx";
+			groups = "ir_1_rx";
 		};
 	};
 
 	irtx_pins: irtx-pins {
 		mux {
 			function = "ir";
-			groups =  "ir_1_tx";
+			groups = "ir_1_tx";
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index dbcee8b4d8d8..146e18b5b1f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -118,8 +118,8 @@ clk25m: oscillator {
 	};
 
 	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	pmu {
@@ -616,9 +616,9 @@ audsys: clock-controller@11220000 {
 
 		afe: audio-controller {
 			compatible = "mediatek,mt7622-audio";
-			interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
-				      <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
-			interrupt-names	= "afe", "asys";
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names = "afe", "asys";
 
 			clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 				 <&topckgen CLK_TOP_AUD1_SEL>,
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index d2636a0ed152..e3a407d03551 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -57,8 +57,8 @@ cpu3: cpu@3 {
 	};
 
 	psci {
-		compatible  = "arm,psci-0.2";
-		method      = "smc";
+		compatible = "arm,psci-0.2";
+		method = "smc";
 	};
 
 	reserved-memory {
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
index 44f6149c1307..28433b94f7c7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
@@ -21,7 +21,7 @@ cpu_crit: cpu_crit0 {
 };
 
 &gpio_keys {
-	/delete-node/tablet_mode;
-	/delete-node/volume_down;
-	/delete-node/volume_up;
+	/delete-node/switch-tablet-mode;
+	/delete-node/switch-volume-down;
+	/delete-node/switch-volume-up;
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
index 9c75fbb31f98..e21feb85d822 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
@@ -53,7 +53,7 @@ gpio_keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&gpio_keys_pins>;
 
-		lid {
+		switch-lid {
 			label = "Lid";
 			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
 			linux,code = <SW_LID>;
@@ -61,7 +61,7 @@ lid {
 			gpio-key,wakeup;
 		};
 
-		power {
+		switch-power {
 			label = "Power";
 			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_POWER>;
@@ -69,7 +69,7 @@ power {
 			gpio-key,wakeup;
 		};
 
-		tablet_mode {
+		switch-tablet-mode {
 			label = "Tablet_mode";
 			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
 			linux,code = <SW_TABLET_MODE>;
@@ -77,13 +77,13 @@ tablet_mode {
 			gpio-key,wakeup;
 		};
 
-		volume_down {
+		switch-volume-down {
 			label = "Volume_down";
 			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 
-		volume_up {
+		switch-volume-up {
 			label = "Volume_up";
 			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_VOLUMEUP>;
@@ -300,8 +300,8 @@ da9211_vcpu_reg: BUCKA {
 				regulator-name = "VBUCKA";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1310000>;
-				regulator-min-microamp  = <2000000>;
-				regulator-max-microamp  = <4400000>;
+				regulator-min-microamp = <2000000>;
+				regulator-max-microamp = <4400000>;
 				regulator-ramp-delay = <10000>;
 				regulator-always-on;
 				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
@@ -312,8 +312,8 @@ da9211_vgpu_reg: BUCKB {
 				regulator-name = "VBUCKB";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1310000>;
-				regulator-min-microamp  = <2000000>;
-				regulator-max-microamp  = <3000000>;
+				regulator-min-microamp = <2000000>;
+				regulator-max-microamp = <3000000>;
 				regulator-ramp-delay = <10000>;
 			};
 		};
@@ -374,8 +374,8 @@ &mmc0 {
 	mmc-hs400-1_8v;
 	cap-mmc-hw-reset;
 	hs400-ds-delay = <0x14015>;
-	mediatek,hs200-cmd-int-delay=<30>;
-	mediatek,hs400-cmd-int-delay=<14>;
+	mediatek,hs200-cmd-int-delay = <30>;
+	mediatek,hs400-cmd-int-delay = <14>;
 	mediatek,hs400-cmd-resp-sel-rising;
 	vmmc-supply = <&mt6397_vemc_3v3_reg>;
 	vqmmc-supply = <&mt6397_vio18_reg>;
@@ -410,7 +410,7 @@ &mmc3 {
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	cap-sdio-irq;
 	vmmc-supply = <&sdio_fixed_3v3>;
 	vqmmc-supply = <&mt6397_vgp3_reg>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 4fa1e93302c7..0b5f154007be 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -122,8 +122,8 @@ da9211_vcpu_reg: BUCKA {
 				regulator-name = "VBUCKA";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1310000>;
-				regulator-min-microamp	= <2000000>;
-				regulator-max-microamp	= <4400000>;
+				regulator-min-microamp = <2000000>;
+				regulator-max-microamp = <4400000>;
 				regulator-ramp-delay = <10000>;
 				regulator-always-on;
 			};
@@ -132,8 +132,8 @@ da9211_vgpu_reg: BUCKB {
 				regulator-name = "VBUCKB";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1310000>;
-				regulator-min-microamp	= <2000000>;
-				regulator-max-microamp	= <3000000>;
+				regulator-min-microamp = <2000000>;
+				regulator-max-microamp = <3000000>;
 				regulator-ramp-delay = <10000>;
 			};
 		};
@@ -148,8 +148,8 @@ &mmc0 {
 	bus-width = <8>;
 	max-frequency = <50000000>;
 	cap-mmc-highspeed;
-	mediatek,hs200-cmd-int-delay=<26>;
-	mediatek,hs400-cmd-int-delay=<14>;
+	mediatek,hs200-cmd-int-delay = <26>;
+	mediatek,hs400-cmd-int-delay = <14>;
 	mediatek,hs400-cmd-resp-sel-rising;
 	vmmc-supply = <&mt6397_vemc_3v3_reg>;
 	vqmmc-supply = <&mt6397_vio18_reg>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40d7b47fc52e..384356dc26ce 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1,14 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2014 MediaTek Inc.
  * Author: Eddie Huang <eddie.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <dt-bindings/clock/mt8173-clk.h>
@@ -246,9 +239,9 @@ pmu_a72 {
 	psci {
 		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 		method = "smc";
-		cpu_suspend   = <0x84000001>;
-		cpu_off	      = <0x84000002>;
-		cpu_on	      = <0x84000003>;
+		cpu_suspend = <0x84000001>;
+		cpu_off	 = <0x84000002>;
+		cpu_on	 = <0x84000003>;
 	};
 
 	clk26m: oscillator0 {
@@ -588,6 +581,7 @@ iommu: iommu@10205000 {
 			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 			clocks = <&infracfg CLK_INFRA_M4U>;
 			clock-names = "bclk";
+			mediatek,infracfg = <&infracfg>;
 			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
 					 <&larb3>, <&larb4>, <&larb5>;
 			#iommu-cells = <1>;
@@ -1505,7 +1499,7 @@ larb5: larb@19001000 {
 
 		vcodec_enc_vp8: vcodec@19002000 {
 			compatible = "mediatek,mt8173-vcodec-enc-vp8";
-			reg =  <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+			reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
 			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
 			iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
 				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index f3fd3cca23e9..52dc4a50e34d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -134,7 +134,7 @@ &mmc1 {
 	vmmc-supply = <&mt6358_vmch_reg>;
 	vqmmc-supply = <&mt6358_vmc_reg>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	non-removable;
 };
 
@@ -412,6 +412,42 @@ &spi5 {
 
 };
 
+&cci {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu0 {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+	proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+	proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+	proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+	proc-supply = <&mt6358_vproc11_reg>;
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
index 2d7a193272ae..3ac83be53627 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -73,7 +73,7 @@ volume_buttons: volume-buttons {
 		pinctrl-names = "default";
 		pinctrl-0 = <&volume_button_pins>;
 
-		volume_down {
+		button-volume-down {
 			label = "Volume Down";
 			linux,code = <KEY_VOLUMEDOWN>;
 			debounce-interval = <100>;
@@ -81,7 +81,7 @@ volume_down {
 			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 		};
 
-		volume_up {
+		button-volume-up {
 			label = "Volume Up";
 			linux,code = <KEY_VOLUMEUP>;
 			debounce-interval = <100>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
index 28966a65391b..50a0dd36b5fb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
@@ -45,7 +45,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pen_eject>;
 
-		pen-insert {
+		switch-pen-insert {
 			label = "Pen Insert";
 			/* Insert = low, eject = high */
 			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index 8d5bf73a9099..89e4358f140a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -144,7 +144,7 @@ wifi_wakeup: wifi-wakeup {
 		pinctrl-names = "default";
 		pinctrl-0 = <&wifi_pins_wakeup>;
 
-		wowlan {
+		button-wowlan {
 			label = "Wake on WiFi";
 			gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_WAKEUP>;
@@ -230,6 +230,10 @@ &auxadc {
 	status = "okay";
 };
 
+&cci {
+	proc-supply = <&mt6358_vproc12_reg>;
+};
+
 &cpu0 {
 	proc-supply = <&mt6358_vproc12_reg>;
 };
@@ -378,7 +382,7 @@ &mmc1 {
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	cap-sdio-irq;
 	non-removable;
 	no-mmc;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index afeb5cd37826..530e0c9ce0c9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -159,7 +159,7 @@ &mmc1 {
 	vmmc-supply = <&mt6358_vmch_reg>;
 	vqmmc-supply = <&mt6358_vmc_reg>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	non-removable;
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 01e650251928..9485c1efc87c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -42,6 +42,252 @@ aliases {
 		rdma1 = &rdma1;
 	};
 
+	cluster0_opp: opp-table-cluster0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp0-793000000 {
+			opp-hz = /bits/ 64 <793000000>;
+			opp-microvolt = <650000>;
+			required-opps = <&opp2_00>;
+		};
+		opp0-910000000 {
+			opp-hz = /bits/ 64 <910000000>;
+			opp-microvolt = <687500>;
+			required-opps = <&opp2_01>;
+		};
+		opp0-1014000000 {
+			opp-hz = /bits/ 64 <1014000000>;
+			opp-microvolt = <718750>;
+			required-opps = <&opp2_02>;
+		};
+		opp0-1131000000 {
+			opp-hz = /bits/ 64 <1131000000>;
+			opp-microvolt = <756250>;
+			required-opps = <&opp2_03>;
+		};
+		opp0-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			opp-microvolt = <800000>;
+			required-opps = <&opp2_04>;
+		};
+		opp0-1326000000 {
+			opp-hz = /bits/ 64 <1326000000>;
+			opp-microvolt = <818750>;
+			required-opps = <&opp2_05>;
+		};
+		opp0-1417000000 {
+			opp-hz = /bits/ 64 <1417000000>;
+			opp-microvolt = <850000>;
+			required-opps = <&opp2_06>;
+		};
+		opp0-1508000000 {
+			opp-hz = /bits/ 64 <1508000000>;
+			opp-microvolt = <868750>;
+			required-opps = <&opp2_07>;
+		};
+		opp0-1586000000 {
+			opp-hz = /bits/ 64 <1586000000>;
+			opp-microvolt = <893750>;
+			required-opps = <&opp2_08>;
+		};
+		opp0-1625000000 {
+			opp-hz = /bits/ 64 <1625000000>;
+			opp-microvolt = <906250>;
+			required-opps = <&opp2_09>;
+		};
+		opp0-1677000000 {
+			opp-hz = /bits/ 64 <1677000000>;
+			opp-microvolt = <931250>;
+			required-opps = <&opp2_10>;
+		};
+		opp0-1716000000 {
+			opp-hz = /bits/ 64 <1716000000>;
+			opp-microvolt = <943750>;
+			required-opps = <&opp2_11>;
+		};
+		opp0-1781000000 {
+			opp-hz = /bits/ 64 <1781000000>;
+			opp-microvolt = <975000>;
+			required-opps = <&opp2_12>;
+		};
+		opp0-1846000000 {
+			opp-hz = /bits/ 64 <1846000000>;
+			opp-microvolt = <1000000>;
+			required-opps = <&opp2_13>;
+		};
+		opp0-1924000000 {
+			opp-hz = /bits/ 64 <1924000000>;
+			opp-microvolt = <1025000>;
+			required-opps = <&opp2_14>;
+		};
+		opp0-1989000000 {
+			opp-hz = /bits/ 64 <1989000000>;
+			opp-microvolt = <1050000>;
+			required-opps = <&opp2_15>;
+		};	};
+
+	cluster1_opp: opp-table-cluster1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp1-793000000 {
+			opp-hz = /bits/ 64 <793000000>;
+			opp-microvolt = <700000>;
+			required-opps = <&opp2_00>;
+		};
+		opp1-910000000 {
+			opp-hz = /bits/ 64 <910000000>;
+			opp-microvolt = <725000>;
+			required-opps = <&opp2_01>;
+		};
+		opp1-1014000000 {
+			opp-hz = /bits/ 64 <1014000000>;
+			opp-microvolt = <750000>;
+			required-opps = <&opp2_02>;
+		};
+		opp1-1131000000 {
+			opp-hz = /bits/ 64 <1131000000>;
+			opp-microvolt = <775000>;
+			required-opps = <&opp2_03>;
+		};
+		opp1-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			opp-microvolt = <800000>;
+			required-opps = <&opp2_04>;
+		};
+		opp1-1326000000 {
+			opp-hz = /bits/ 64 <1326000000>;
+			opp-microvolt = <825000>;
+			required-opps = <&opp2_05>;
+		};
+		opp1-1417000000 {
+			opp-hz = /bits/ 64 <1417000000>;
+			opp-microvolt = <850000>;
+			required-opps = <&opp2_06>;
+		};
+		opp1-1508000000 {
+			opp-hz = /bits/ 64 <1508000000>;
+			opp-microvolt = <875000>;
+			required-opps = <&opp2_07>;
+		};
+		opp1-1586000000 {
+			opp-hz = /bits/ 64 <1586000000>;
+			opp-microvolt = <900000>;
+			required-opps = <&opp2_08>;
+		};
+		opp1-1625000000 {
+			opp-hz = /bits/ 64 <1625000000>;
+			opp-microvolt = <912500>;
+			required-opps = <&opp2_09>;
+		};
+		opp1-1677000000 {
+			opp-hz = /bits/ 64 <1677000000>;
+			opp-microvolt = <931250>;
+			required-opps = <&opp2_10>;
+		};
+		opp1-1716000000 {
+			opp-hz = /bits/ 64 <1716000000>;
+			opp-microvolt = <950000>;
+			required-opps = <&opp2_11>;
+		};
+		opp1-1781000000 {
+			opp-hz = /bits/ 64 <1781000000>;
+			opp-microvolt = <975000>;
+			required-opps = <&opp2_12>;
+		};
+		opp1-1846000000 {
+			opp-hz = /bits/ 64 <1846000000>;
+			opp-microvolt = <1000000>;
+			required-opps = <&opp2_13>;
+		};
+		opp1-1924000000 {
+			opp-hz = /bits/ 64 <1924000000>;
+			opp-microvolt = <1025000>;
+			required-opps = <&opp2_14>;
+		};
+		opp1-1989000000 {
+			opp-hz = /bits/ 64 <1989000000>;
+			opp-microvolt = <1050000>;
+			required-opps = <&opp2_15>;
+		};
+	};
+
+	cci_opp: opp-table-cci {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp2_00: opp-273000000 {
+			opp-hz = /bits/ 64 <273000000>;
+			opp-microvolt = <650000>;
+		};
+		opp2_01: opp-338000000 {
+			opp-hz = /bits/ 64 <338000000>;
+			opp-microvolt = <687500>;
+		};
+		opp2_02: opp-403000000 {
+			opp-hz = /bits/ 64 <403000000>;
+			opp-microvolt = <718750>;
+		};
+		opp2_03: opp-463000000 {
+			opp-hz = /bits/ 64 <463000000>;
+			opp-microvolt = <756250>;
+		};
+		opp2_04: opp-546000000 {
+			opp-hz = /bits/ 64 <546000000>;
+			opp-microvolt = <800000>;
+		};
+		opp2_05: opp-624000000 {
+			opp-hz = /bits/ 64 <624000000>;
+			opp-microvolt = <818750>;
+		};
+		opp2_06: opp-689000000 {
+			opp-hz = /bits/ 64 <689000000>;
+			opp-microvolt = <850000>;
+		};
+		opp2_07: opp-767000000 {
+			opp-hz = /bits/ 64 <767000000>;
+			opp-microvolt = <868750>;
+		};
+		opp2_08: opp-845000000 {
+			opp-hz = /bits/ 64 <845000000>;
+			opp-microvolt = <893750>;
+		};
+		opp2_09: opp-871000000 {
+			opp-hz = /bits/ 64 <871000000>;
+			opp-microvolt = <906250>;
+		};
+		opp2_10: opp-923000000 {
+			opp-hz = /bits/ 64 <923000000>;
+			opp-microvolt = <931250>;
+		};
+		opp2_11: opp-962000000 {
+			opp-hz = /bits/ 64 <962000000>;
+			opp-microvolt = <943750>;
+		};
+		opp2_12: opp-1027000000 {
+			opp-hz = /bits/ 64 <1027000000>;
+			opp-microvolt = <975000>;
+		};
+		opp2_13: opp-1092000000 {
+			opp-hz = /bits/ 64 <1092000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp2_14: opp-1144000000 {
+			opp-hz = /bits/ 64 <1144000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp2_15: opp-1196000000 {
+			opp-hz = /bits/ 64 <1196000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	cci: cci {
+		compatible = "mediatek,mt8183-cci";
+		clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+			 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+		clock-names = "cci", "intermediate";
+		operating-points-v2 = <&cci_opp>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -85,8 +331,13 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <741>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 			dynamic-power-coefficient = <84>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu1: cpu@1 {
@@ -96,8 +347,13 @@ cpu1: cpu@1 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <741>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 			dynamic-power-coefficient = <84>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu2: cpu@2 {
@@ -107,8 +363,13 @@ cpu2: cpu@2 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <741>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 			dynamic-power-coefficient = <84>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu3: cpu@3 {
@@ -118,8 +379,13 @@ cpu3: cpu@3 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <741>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 			dynamic-power-coefficient = <84>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu4: cpu@100 {
@@ -129,8 +395,13 @@ cpu4: cpu@100 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 			dynamic-power-coefficient = <211>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu5: cpu@101 {
@@ -140,8 +411,13 @@ cpu5: cpu@101 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 			dynamic-power-coefficient = <211>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu6: cpu@102 {
@@ -151,8 +427,13 @@ cpu6: cpu@102 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 			dynamic-power-coefficient = <211>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		cpu7: cpu@103 {
@@ -162,8 +443,13 @@ cpu7: cpu@103 {
 			enable-method = "psci";
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 			dynamic-power-coefficient = <211>;
 			#cooling-cells = <2>;
+			mediatek,cci = <&cci>;
 		};
 
 		idle-states {
@@ -295,8 +581,8 @@ pmu-a73 {
 	};
 
 	psci {
-		compatible      = "arm,psci-1.0";
-		method          = "smc";
+		compatible = "arm,psci-1.0";
+		method = "smc";
 	};
 
 	clk26m: oscillator {
@@ -321,7 +607,7 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 
-		soc_data: soc_data@8000000 {
+		soc_data: efuse@8000000 {
 			compatible = "mediatek,mt8183-efuse",
 				     "mediatek,efuse";
 			reg = <0 0x08000000 0 0x0010>;
@@ -504,7 +790,7 @@ power-domain@MT8183_POWER_DOMAIN_CONN {
 
 				power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
 					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
-					clocks =  <&topckgen CLK_TOP_MUX_MFG>;
+					clocks = <&topckgen CLK_TOP_MUX_MFG>;
 					clock-names = "mfg";
 					#address-cells = <1>;
 					#size-cells = <0>;
@@ -807,6 +1093,18 @@ spi0: spi@1100a000 {
 			status = "disabled";
 		};
 
+		svs: svs@1100b000 {
+			compatible = "mediatek,mt8183-svs";
+			reg = <0 0x1100b000 0 0x1000>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&infracfg CLK_INFRA_THERM>;
+			clock-names = "main";
+			nvmem-cells = <&svs_calibration>,
+				      <&thermal_calibration>;
+			nvmem-cell-names = "svs-calibration-data",
+					   "t-calibration-data";
+		};
+
 		thermal: thermal@1100b000 {
 			#thermal-sensor-cells = <1>;
 			compatible = "mediatek,mt8183-thermal";
@@ -1150,7 +1448,7 @@ i2c8: i2c@1101b000 {
 		};
 
 		ssusb: usb@11201000 {
-			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
+			compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
 			reg = <0 0x11201000 0 0x2e00>,
 			      <0 0x11203e00 0 0x0100>;
 			reg-names = "mac", "ippc";
@@ -1325,6 +1623,10 @@ thermal_calibration: calib@180 {
 			mipi_tx_calibration: calib@190 {
 				reg = <0x190 0xc>;
 			};
+
+			svs_calibration: calib@580 {
+				reg = <0x580 0x64>;
+			};
 		};
 
 		u3phy: t-phy@11f40000 {
@@ -1508,6 +1810,7 @@ mutex: mutex@14016000 {
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
 					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
 		};
 
 		larb0: larb@14017000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 733aec2e7f77..cbae5a5ee4a0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -43,7 +43,7 @@ cpu0: cpu@0 {
 			reg = <0x000>;
 			enable-method = "psci";
 			clock-frequency = <1701000000>;
-			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
 		};
@@ -54,7 +54,7 @@ cpu1: cpu@100 {
 			reg = <0x100>;
 			enable-method = "psci";
 			clock-frequency = <1701000000>;
-			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
 		};
@@ -65,7 +65,7 @@ cpu2: cpu@200 {
 			reg = <0x200>;
 			enable-method = "psci";
 			clock-frequency = <1701000000>;
-			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
 		};
@@ -76,7 +76,7 @@ cpu3: cpu@300 {
 			reg = <0x300>;
 			enable-method = "psci";
 			clock-frequency = <1701000000>;
-			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+			cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <530>;
 		};
@@ -87,7 +87,7 @@ cpu4: cpu@400 {
 			reg = <0x400>;
 			enable-method = "psci";
 			clock-frequency = <2171000000>;
-			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 		};
@@ -98,7 +98,7 @@ cpu5: cpu@500 {
 			reg = <0x500>;
 			enable-method = "psci";
 			clock-frequency = <2171000000>;
-			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 		};
@@ -109,7 +109,7 @@ cpu6: cpu@600 {
 			reg = <0x600>;
 			enable-method = "psci";
 			clock-frequency = <2171000000>;
-			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 		};
@@ -120,7 +120,7 @@ cpu7: cpu@700 {
 			reg = <0x700>;
 			enable-method = "psci";
 			clock-frequency = <2171000000>;
-			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+			cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
 		};
@@ -172,8 +172,8 @@ l3_0: l3-cache {
 		};
 
 		idle-states {
-			entry-method = "arm,psci";
-			cpuoff_l: cpuoff_l {
+			entry-method = "psci";
+			cpu_sleep_l: cpu-sleep-l {
 				compatible = "arm,idle-state";
 				arm,psci-suspend-param = <0x00010001>;
 				local-timer-stop;
@@ -181,7 +181,7 @@ cpuoff_l: cpuoff_l {
 				exit-latency-us = <140>;
 				min-residency-us = <780>;
 			};
-			cpuoff_b: cpuoff_b {
+			cpu_sleep_b: cpu-sleep-b {
 				compatible = "arm,idle-state";
 				arm,psci-suspend-param = <0x00010001>;
 				local-timer-stop;
@@ -189,7 +189,7 @@ cpuoff_b: cpuoff_b {
 				exit-latency-us = <145>;
 				min-residency-us = <720>;
 			};
-			clusteroff_l: clusteroff_l {
+			cluster_sleep_l: cluster-sleep-l {
 				compatible = "arm,idle-state";
 				arm,psci-suspend-param = <0x01010002>;
 				local-timer-stop;
@@ -197,7 +197,7 @@ clusteroff_l: clusteroff_l {
 				exit-latency-us = <155>;
 				min-residency-us = <860>;
 			};
-			clusteroff_b: clusteroff_b {
+			cluster_sleep_b: cluster-sleep-b {
 				compatible = "arm,idle-state";
 				arm,psci-suspend-param = <0x01010002>;
 				local-timer-stop;
@@ -271,6 +271,7 @@ infracfg: syscon@10001000 {
 			compatible = "mediatek,mt8192-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		pericfg: syscon@10003000 {
@@ -911,7 +912,7 @@ nor_flash: spi@11234000 {
 		};
 
 		efuse: efuse@11c10000 {
-			compatible = "mediatek,efuse";
+			compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
 			reg = <0 0x11c10000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index db25a515e420..690dc7717f2c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -139,19 +139,19 @@ pins {
 };
 
 &u3phy0 {
-	status="okay";
+	status = "okay";
 };
 
 &u3phy1 {
-	status="okay";
+	status = "okay";
 };
 
 &u3phy2 {
-	status="okay";
+	status = "okay";
 };
 
 &u3phy3 {
-	status="okay";
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index b57e620c2c72..066c14989708 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,7 +10,6 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
-#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8195";
@@ -295,17 +294,7 @@ infracfg_ao: syscon@10001000 {
 			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
-
-			infracfg_rst: reset-controller {
-				compatible = "ti,syscon-reset";
-				#reset-cells = <1>;
-				ti,reset-bits = <
-					0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
-					0x120 0  0x124 0  0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
-					0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
-					0x150 5  0x154 5  0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
-				>;
-			};
+			#reset-cells = <1>;
 		};
 
 		pericfg: syscon@10003000 {
@@ -573,6 +562,8 @@ xhci0: usb@11200000 {
 				 <&apmixedsys CLK_APMIXED_USB1PLL>,
 				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
+			wakeup-source;
 			status = "disabled";
 		};
 
@@ -636,6 +627,8 @@ xhci1: usb@11290000 {
 				 <&apmixedsys CLK_APMIXED_USB1PLL>,
 				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
+			wakeup-source;
 			status = "disabled";
 		};
 
@@ -655,6 +648,8 @@ xhci2: usb@112a0000 {
 				 <&topckgen CLK_TOP_SSUSB_P2_REF>,
 				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "xhci_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
+			wakeup-source;
 			status = "disabled";
 		};
 
@@ -674,6 +669,8 @@ xhci3: usb@112b0000 {
 				 <&topckgen CLK_TOP_SSUSB_P3_REF>,
 				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "xhci_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
+			wakeup-source;
 			status = "disabled";
 		};
 
@@ -691,6 +688,53 @@ nor_flash: spi@1132c000 {
 			status = "disabled";
 		};
 
+		efuse: efuse@11c10000 {
+			compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
+			reg = <0 0x11c10000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			u3_tx_imp_p0: usb3-tx-imp@184,1 {
+				reg = <0x184 0x1>;
+				bits = <0 5>;
+			};
+			u3_rx_imp_p0: usb3-rx-imp@184,2 {
+				reg = <0x184 0x2>;
+				bits = <5 5>;
+			};
+			u3_intr_p0: usb3-intr@185 {
+				reg = <0x185 0x1>;
+				bits = <2 6>;
+			};
+			comb_tx_imp_p1: usb3-tx-imp@186,1 {
+				reg = <0x186 0x1>;
+				bits = <0 5>;
+			};
+			comb_rx_imp_p1: usb3-rx-imp@186,2 {
+				reg = <0x186 0x2>;
+				bits = <5 5>;
+			};
+			comb_intr_p1: usb3-intr@187 {
+				reg = <0x187 0x1>;
+				bits = <2 6>;
+			};
+			u2_intr_p0: usb2-intr-p0@188,1 {
+				reg = <0x188 0x1>;
+				bits = <0 5>;
+			};
+			u2_intr_p1: usb2-intr-p1@188,2 {
+				reg = <0x188 0x2>;
+				bits = <5 5>;
+			};
+			u2_intr_p2: usb2-intr-p2@189,1 {
+				reg = <0x189 0x1>;
+				bits = <2 5>;
+			};
+			u2_intr_p3: usb2-intr-p3@189,2 {
+				reg = <0x189 0x2>;
+				bits = <7 5>;
+			};
+		};
+
 		u3phy2: t-phy@11c40000 {
 			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
 			#address-cells = <1>;
@@ -873,6 +917,10 @@ u3port1: usb-phy@700 {
 				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
 					 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
 				clock-names = "ref", "da_ref";
+				nvmem-cells = <&comb_intr_p1>,
+					      <&comb_rx_imp_p1>,
+					      <&comb_tx_imp_p1>;
+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 				#phy-cells = <1>;
 			};
 		};
@@ -897,6 +945,10 @@ u3port0: usb-phy@700 {
 				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
 					 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
 				clock-names = "ref", "da_ref";
+				nvmem-cells = <&u3_intr_p0>,
+					      <&u3_rx_imp_p0>,
+					      <&u3_tx_imp_p0>;
+				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 				#phy-cells = <1>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index 7a717f926929..8ee1529683a3 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -28,7 +28,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&gpio_keys_default>;
 
-		volume-up {
+		key-volume-up {
 			gpios = <&pio 42 GPIO_ACTIVE_LOW>;
 			label = "volume_up";
 			linux,code = <115>;
@@ -36,7 +36,7 @@ volume-up {
 			debounce-interval = <15>;
 		};
 
-		volume-down {
+		key-volume-down {
 			gpios = <&pio 43 GPIO_ACTIVE_LOW>;
 			label = "volume_down";
 			linux,code = <114>;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 699256f1b9d8..bf12be5e8d84 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -546,164 +546,164 @@ phy64: ethernet-phy@64 {
 
 &axi {
 	sfp_eth12: sfp-eth12 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp1>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
 		tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth13: sfp-eth13 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp2>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
 		tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth14: sfp-eth14 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp3>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp3>;
 		tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth15: sfp-eth15 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp4>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp4>;
 		tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth48: sfp-eth48 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp5>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp5>;
 		tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth49: sfp-eth49 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp6>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp6>;
 		tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth50: sfp-eth50 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp7>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp7>;
 		tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth51: sfp-eth51 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp8>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp8>;
 		tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth52: sfp-eth52 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp9>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp9>;
 		tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth53: sfp-eth53 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp10>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp10>;
 		tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth54: sfp-eth54 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp11>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp11>;
 		tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth55: sfp-eth55 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp12>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp12>;
 		tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth56: sfp-eth56 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp13>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp13>;
 		tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth57: sfp-eth57 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp14>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp14>;
 		tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth58: sfp-eth58 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp15>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp15>;
 		tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth59: sfp-eth59 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp16>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp16>;
 		tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth60: sfp-eth60 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp17>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp17>;
 		tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth61: sfp-eth61 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp18>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp18>;
 		tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth62: sfp-eth62 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp19>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp19>;
 		tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth63: sfp-eth63 {
-		compatible       = "sff,sfp";
-		i2c-bus          = <&i2c_sfp20>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp20>;
 		tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
-		los-gpios        = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios   = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios   = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index d10a9172b529..ec90bda7ed6a 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -170,40 +170,40 @@ i2c_sfp4: i2c_sfp4 {
 
 &axi {
 	sfp_eth60: sfp-eth60 {
-		compatible	   = "sff,sfp";
-		i2c-bus            = <&i2c_sfp1>;
-		tx-disable-gpios   = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
+		compatible	 = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
 		rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
-		los-gpios          = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios     = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios     = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth61: sfp-eth61 {
-		compatible         = "sff,sfp";
-		i2c-bus            = <&i2c_sfp2>;
-		tx-disable-gpios   = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp2>;
+		tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
 		rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
-		los-gpios          = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios     = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios     = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth62: sfp-eth62 {
-		compatible         = "sff,sfp";
-		i2c-bus            = <&i2c_sfp3>;
-		tx-disable-gpios   = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp3>;
+		tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
 		rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
-		los-gpios          = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios     = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios     = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
 	};
 	sfp_eth63: sfp-eth63 {
-		compatible         = "sff,sfp";
-		i2c-bus            = <&i2c_sfp4>;
-		tx-disable-gpios   = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp4>;
+		tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
 		rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
-		los-gpios          = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios     = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
-		tx-fault-gpios     = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
+		los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
+		tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 70737a09a9b8..bd1897707fcc 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -915,6 +915,22 @@ xbar_asrc_in7_ep: endpoint {
 						remote-endpoint = <&asrc_in7_ep>;
 					};
 				};
+
+				xbar_ope1_in_port: port@70 {
+					reg = <0x70>;
+
+					xbar_ope1_in_ep: endpoint {
+						remote-endpoint = <&ope1_cif_in_ep>;
+					};
+				};
+
+				port@71 {
+					reg = <0x71>;
+
+					xbar_ope1_out_ep: endpoint {
+						remote-endpoint = <&ope1_cif_out_ep>;
+					};
+				};
 			};
 
 			admaif@290f000 {
@@ -1911,6 +1927,31 @@ adx4_out4_ep: endpoint {
 				};
 			};
 
+			processing-engine@2908000 {
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0x0>;
+
+						ope1_cif_in_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_in_ep>;
+						};
+					};
+
+					ope1_out_port: port@1 {
+						reg = <0x1>;
+
+						ope1_cif_out_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_out_ep>;
+						};
+					};
+				};
+			};
+
 			amixer@290bb00 {
 				status = "okay";
 
@@ -2552,6 +2593,7 @@ sound {
 		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
 		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
 		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -2571,6 +2613,7 @@ sound {
 		       <&mixer_out5_port>,
 		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
 		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
 		       /* I/O */
 		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
 		       <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0e9afc3e2f26..cd8c4f392f0b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -509,6 +509,29 @@ tegra_adx4: adx@2903b00 {
 				status = "disabled";
 			};
 
+			tegra_ope1: processing-engine@2908000 {
+				compatible = "nvidia,tegra186-ope",
+					     "nvidia,tegra210-ope";
+				reg = <0x2908000 0x100>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				sound-name-prefix = "OPE1";
+				status = "disabled";
+
+				equalizer@2908100 {
+					compatible = "nvidia,tegra186-peq",
+						     "nvidia,tegra210-peq";
+					reg = <0x2908100 0x100>;
+				};
+
+				dynamic-range-compressor@2908200 {
+					compatible = "nvidia,tegra186-mbdrc",
+						     "nvidia,tegra210-mbdrc";
+					reg = <0x2908200 0x200>;
+				};
+			};
+
 			tegra_amixer: amixer@290bb00 {
 				compatible = "nvidia,tegra186-amixer",
 					     "nvidia,tegra210-amixer";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index bce518ace6a0..fafd7073d18c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -868,6 +868,22 @@ xbar_asrc_in7_ep: endpoint {
 							remote-endpoint = <&asrc_in7_ep>;
 						};
 					};
+
+					xbar_ope1_in_port: port@70 {
+						reg = <0x70>;
+
+						xbar_ope1_in_ep: endpoint {
+							remote-endpoint = <&ope1_cif_in_ep>;
+						};
+					};
+
+					port@71 {
+						reg = <0x71>;
+
+						xbar_ope1_out_ep: endpoint {
+							remote-endpoint = <&ope1_cif_out_ep>;
+						};
+					};
 				};
 
 				admaif@290f000 {
@@ -1710,6 +1726,31 @@ adx4_out4_ep: endpoint {
 					};
 				};
 
+				processing-engine@2908000 {
+					status = "okay";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0x0>;
+
+							ope1_cif_in_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_in_ep>;
+							};
+						};
+
+						ope1_out_port: port@1 {
+							reg = <0x1>;
+
+							ope1_cif_out_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_out_ep>;
+							};
+						};
+					};
+				};
+
 				amixer@290bb00 {
 					status = "okay";
 
@@ -2273,6 +2314,7 @@ sound {
 		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
 		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
 		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -2291,6 +2333,7 @@ sound {
 		       <&mixer_out4_port>, <&mixer_out5_port>,
 		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
 		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
 		       /* BE I/O Ports */
 		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
 		       <&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index 7acc32dd290a..4cee935e44a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -878,6 +878,22 @@ xbar_asrc_in7_ep: endpoint {
 							remote-endpoint = <&asrc_in7_ep>;
 						};
 					};
+
+					xbar_ope1_in_port: port@70 {
+						reg = <0x70>;
+
+						xbar_ope1_in_ep: endpoint {
+							remote-endpoint = <&ope1_cif_in_ep>;
+						};
+					};
+
+					port@71 {
+						reg = <0x71>;
+
+						xbar_ope1_out_ep: endpoint {
+							remote-endpoint = <&ope1_cif_out_ep>;
+						};
+					};
 				};
 
 				admaif@290f000 {
@@ -1770,6 +1786,31 @@ adx4_out4_ep: endpoint {
 					};
 				};
 
+				processing-engine@2908000 {
+					status = "okay";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0x0>;
+
+							ope1_cif_in_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_in_ep>;
+							};
+						};
+
+						ope1_out_port: port@1 {
+							reg = <0x1>;
+
+							ope1_cif_out_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_out_ep>;
+							};
+						};
+					};
+				};
+
 				amixer@290bb00 {
 					status = "okay";
 
@@ -2323,6 +2364,7 @@ sound {
 		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
 		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
 		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -2342,6 +2384,7 @@ sound {
 		       <&mixer_out5_port>,
 		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
 		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
 		       /* BE I/O Ports */
 		       <&i2s3_port>, <&i2s5_port>,
 		       <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d1f8248c00f4..e65d1b0be5a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -562,6 +562,29 @@ tegra_adx4: adx@2903b00 {
 					status = "disabled";
 				};
 
+				tegra_ope1: processing-engine@2908000 {
+					compatible = "nvidia,tegra194-ope",
+						     "nvidia,tegra210-ope";
+					reg = <0x2908000 0x100>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges;
+					sound-name-prefix = "OPE1";
+					status = "disabled";
+
+					equalizer@2908100 {
+						compatible = "nvidia,tegra194-peq",
+							     "nvidia,tegra210-peq";
+						reg = <0x2908100 0x100>;
+					};
+
+					dynamic-range-compressor@2908200 {
+						compatible = "nvidia,tegra194-mbdrc",
+							     "nvidia,tegra210-mbdrc";
+						reg = <0x2908200 0x200>;
+					};
+				};
+
 				tegra_amixer: amixer@290bb00 {
 					compatible = "nvidia,tegra194-amixer",
 						     "nvidia,tegra210-amixer";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 328fbfec4ee8..1e26ca91a944 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -682,6 +682,56 @@ adx2_out4_ep: endpoint {
 				};
 			};
 
+			processing-engine@702d8000 {
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0x0>;
+
+						ope1_cif_in_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_in_ep>;
+						};
+					};
+
+					ope1_out_port: port@1 {
+						reg = <0x1>;
+
+						ope1_cif_out_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_out_ep>;
+						};
+					};
+				};
+			};
+
+			processing-engine@702d8400 {
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0x0>;
+
+						ope2_cif_in_ep: endpoint {
+							remote-endpoint = <&xbar_ope2_in_ep>;
+						};
+					};
+
+					ope2_out_port: port@1 {
+						reg = <0x1>;
+
+						ope2_cif_out_ep: endpoint {
+							remote-endpoint = <&xbar_ope2_out_ep>;
+						};
+					};
+				};
+			};
+
 			amixer@702dbb00 {
 				status = "okay";
 
@@ -1251,6 +1301,38 @@ xbar_mixer_out5_ep: endpoint {
 						remote-endpoint = <&mixer_out5_ep>;
 					};
 				};
+
+				xbar_ope1_in_port: port@41 {
+					reg = <0x41>;
+
+					xbar_ope1_in_ep: endpoint {
+						remote-endpoint = <&ope1_cif_in_ep>;
+					};
+				};
+
+				port@42 {
+					reg = <0x42>;
+
+					xbar_ope1_out_ep: endpoint {
+						remote-endpoint = <&ope1_cif_out_ep>;
+					};
+				};
+
+				xbar_ope2_in_port: port@43 {
+					reg = <0x43>;
+
+					xbar_ope2_in_ep: endpoint {
+						remote-endpoint = <&ope2_cif_in_ep>;
+					};
+				};
+
+				port@44 {
+					reg = <0x44>;
+
+					xbar_ope2_out_ep: endpoint {
+						remote-endpoint = <&ope2_cif_out_ep>;
+					};
+				};
 			};
 		};
 	};
@@ -1281,6 +1363,7 @@ sound {
 		       <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
 		       <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
 		       <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+		       <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -1293,6 +1376,7 @@ sound {
 		       <&mixer_out1_port>, <&mixer_out2_port>,
 		       <&mixer_out3_port>, <&mixer_out4_port>,
 		       <&mixer_out5_port>,
+		       <&ope1_out_port>, <&ope2_out_port>,
 		       /* I/O DAP Ports */
 		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
 		       <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 746bd52ea3f7..749b44cf3ffa 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -1074,6 +1074,56 @@ adx2_out4_ep: endpoint {
 				};
 			};
 
+			processing-engine@702d8000 {
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0x0>;
+
+						ope1_cif_in_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_in_ep>;
+						};
+					};
+
+					ope1_out_port: port@1 {
+						reg = <0x1>;
+
+						ope1_cif_out_ep: endpoint {
+							remote-endpoint = <&xbar_ope1_out_ep>;
+						};
+					};
+				};
+			};
+
+			processing-engine@702d8400 {
+				status = "okay";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0x0>;
+
+						ope2_cif_in_ep: endpoint {
+							remote-endpoint = <&xbar_ope2_in_ep>;
+						};
+					};
+
+					ope2_out_port: port@1 {
+						reg = <0x1>;
+
+						ope2_cif_out_ep: endpoint {
+							remote-endpoint = <&xbar_ope2_out_ep>;
+						};
+					};
+				};
+			};
+
 			amixer@702dbb00 {
 				status = "okay";
 
@@ -1611,6 +1661,38 @@ xbar_mixer_out5_ep: endpoint {
 						remote-endpoint = <&mixer_out5_ep>;
 					};
 				};
+
+				xbar_ope1_in_port: port@41 {
+					reg = <0x41>;
+
+					xbar_ope1_in_ep: endpoint {
+						remote-endpoint = <&ope1_cif_in_ep>;
+					};
+				};
+
+				port@42 {
+					reg = <0x42>;
+
+					xbar_ope1_out_ep: endpoint {
+						remote-endpoint = <&ope1_cif_out_ep>;
+					};
+				};
+
+				xbar_ope2_in_port: port@43 {
+					reg = <0x43>;
+
+					xbar_ope2_in_ep: endpoint {
+						remote-endpoint = <&ope2_cif_in_ep>;
+					};
+				};
+
+				port@44 {
+					reg = <0x44>;
+
+					xbar_ope2_out_ep: endpoint {
+						remote-endpoint = <&ope2_cif_out_ep>;
+					};
+				};
 			};
 		};
 	};
@@ -1884,6 +1966,7 @@ sound {
 		       <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
 		       <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
 		       <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+		       <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -1896,6 +1979,7 @@ sound {
 		       <&mixer_out1_port>, <&mixer_out2_port>,
 		       <&mixer_out3_port>, <&mixer_out4_port>,
 		       <&mixer_out5_port>,
+		       <&ope1_out_port>, <&ope2_out_port>,
 		       /* I/O DAP Ports */
 		       <&i2s3_port>, <&i2s4_port>,
 		       <&dmic1_port>, <&dmic2_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 4f0e51f1a343..724e87450605 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1055,7 +1055,7 @@ padctl: padctl@7009f000 {
 		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 		resets = <&tegra_car 142>;
 		reset-names = "padctl";
-		nvidia,pmc =  <&tegra_pmc>;
+		nvidia,pmc = <&tegra_pmc>;
 
 		status = "disabled";
 
@@ -1723,6 +1723,46 @@ tegra_adx2: adx@702d3900 {
 				status = "disabled";
 			};
 
+			tegra_ope1: processing-engine@702d8000 {
+				compatible = "nvidia,tegra210-ope";
+				reg = <0x702d8000 0x100>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				sound-name-prefix = "OPE1";
+				status = "disabled";
+
+				equalizer@702d8100 {
+					compatible = "nvidia,tegra210-peq";
+					reg = <0x702d8100 0x100>;
+				};
+
+				dynamic-range-compressor@702d8200 {
+					compatible = "nvidia,tegra210-mbdrc";
+					reg = <0x702d8200 0x200>;
+				};
+			};
+
+			tegra_ope2: processing-engine@702d8400 {
+				compatible = "nvidia,tegra210-ope";
+				reg = <0x702d8400 0x100>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				sound-name-prefix = "OPE2";
+				status = "disabled";
+
+				equalizer@702d8500 {
+					compatible = "nvidia,tegra210-peq";
+					reg = <0x702d8500 0x100>;
+				};
+
+				dynamic-range-compressor@702d8600 {
+					compatible = "nvidia,tegra210-mbdrc";
+					reg = <0x702d8600 0x200>;
+				};
+			};
+
 			tegra_amixer: amixer@702dbb00 {
 				compatible = "nvidia,tegra210-amixer";
 				reg = <0x702dbb00 0x800>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index eaf1994abb04..3f6c399e3371 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -867,6 +867,22 @@ xbar_asrc_in7_ep: endpoint {
 							remote-endpoint = <&asrc_in7_ep>;
 						};
 					};
+
+					xbar_ope1_in_port: port@70 {
+						reg = <0x70>;
+
+						xbar_ope1_in_ep: endpoint {
+							remote-endpoint = <&ope1_cif_in_ep>;
+						};
+					};
+
+					port@71 {
+						reg = <0x71>;
+
+						xbar_ope1_out_ep: endpoint {
+							remote-endpoint = <&ope1_cif_out_ep>;
+						};
+					};
 				};
 
 				i2s@2901000 {
@@ -1490,6 +1506,31 @@ dmic3_dap: endpoint {
 					};
 				};
 
+				processing-engine@2908000 {
+					status = "okay";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0x0>;
+
+							ope1_cif_in_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_in_ep>;
+							};
+						};
+
+						ope1_out_port: port@1 {
+							reg = <0x1>;
+
+							ope1_cif_out_ep: endpoint {
+								remote-endpoint = <&xbar_ope1_out_ep>;
+							};
+						};
+					};
+				};
+
 				mvc@290a000 {
 					status = "okay";
 
@@ -2044,6 +2085,7 @@ sound {
 		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
 		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
 		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
 		       /* HW accelerators */
 		       <&sfc1_out_port>, <&sfc2_out_port>,
 		       <&sfc3_out_port>, <&sfc4_out_port>,
@@ -2062,6 +2104,7 @@ sound {
 		       <&mix_out4_port>, <&mix_out5_port>,
 		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
 		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
 		       /* BE I/O Ports */
 		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
 		       <&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cb3af539e477..2ae2f11f289c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -21,6 +21,48 @@ bus@0 {
 
 		ranges = <0x0 0x0 0x0 0x40000000>;
 
+		gpcdma: dma-controller@2600000 {
+			compatible = "nvidia,tegra194-gpcdma",
+				      "nvidia,tegra186-gpcdma";
+			reg = <0x2600000 0x210000>;
+			resets = <&bpmp TEGRA234_RESET_GPCDMA>;
+			reset-names = "gpcdma";
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
 		aconnect@2900000 {
 			compatible = "nvidia,tegra234-aconnect",
 				     "nvidia,tegra210-aconnect";
@@ -304,6 +346,29 @@ tegra_dspk2: dspk@2905100 {
 					status = "disabled";
 				};
 
+				tegra_ope1: processing-engine@2908000 {
+					compatible = "nvidia,tegra234-ope",
+						     "nvidia,tegra210-ope";
+					reg = <0x2908000 0x100>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges;
+					sound-name-prefix = "OPE1";
+					status = "disabled";
+
+					equalizer@2908100 {
+						compatible = "nvidia,tegra234-peq",
+							     "nvidia,tegra210-peq";
+						reg = <0x2908100 0x100>;
+					};
+
+					dynamic-range-compressor@2908200 {
+						compatible = "nvidia,tegra234-mbdrc",
+							     "nvidia,tegra210-mbdrc";
+						reg = <0x2908200 0x200>;
+					};
+				};
+
 				tegra_mvc1: mvc@290a000 {
 					compatible = "nvidia,tegra234-mvc",
 						     "nvidia,tegra210-mvc";
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index 821cb7c0c183..d9a8c2e68ae1 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -43,7 +43,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0>;
-		compatible = "n25q128a11";
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
 		spi-max-frequency = <50000000>;
 	};
 };
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 05472510e29d..d2468081c4d2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -436,7 +436,7 @@ restart@4ab000 {
 		};
 
 		qfprom: qfprom@5c000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
 			reg = <0x0005c000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 9932186f7ceb..ab95ec4a7491 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -650,7 +650,7 @@ rpm_msg_ram: sram@68000 {
 		};
 
 		qfprom@74000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
 			reg = <0x00074000 0x8ff>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
index 66540d2ca13b..db240a3207dc 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
@@ -7,7 +7,7 @@
 
 / {
 	model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP";
-	compatible = "qcom,msm8998-mtp";
+	compatible = "qcom,msm8998-mtp", "qcom,msm8998";
 
 	qcom,board-id = <8 0>;
 };
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 758c45bbbe78..9b8e5767fdb6 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -838,7 +838,7 @@ rpm_msg_ram: sram@778000 {
 		};
 
 		qfprom: qfprom@784000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
 			reg = <0x00784000 0x621c>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi
index cfef42353611..cf26432bb7ce 100644
--- a/arch/arm64/boot/dts/qcom/pm660l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi
@@ -67,7 +67,7 @@ pmic@3 {
 
 		pm660l_wled: leds@d800 {
 			compatible = "qcom,pm660l-wled";
-			reg = <0xd800 0xd900>;
+			reg = <0xd800>, <0xd900>;
 			interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "ovp";
 			label = "backlight";
diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
index 6e7c252568e6..81899fe17f2b 100644
--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -35,7 +35,7 @@ pmi8994_spmi_regulators: regulators {
 
 		pmi8994_wled: wled@d800 {
 			compatible = "qcom,pmi8994-wled";
-			reg = <0xd800 0xd900>;
+			reg = <0xd800>, <0xd900>;
 			interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "short";
 			qcom,cabc;
diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
index 0fef5f113f05..ef29e80c442c 100644
--- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -44,7 +44,7 @@ lab: lab {
 
 		pmi8998_wled: leds@d800 {
 			compatible = "qcom,pmi8998-wled";
-			reg = <0xd800 0xd900>;
+			reg = <0xd800>, <0xd900>;
 			interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
 				     <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "ovp", "short";
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index d912166b7552..1cdbe6645f2a 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -366,7 +366,7 @@ usb2_phy_sec: phy@7c000 {
 		};
 
 		qfprom: qfprom@a4000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
 			reg = <0x000a4000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 5dcaac23a138..705dc60f2151 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3215,7 +3215,7 @@ aoss_reset: reset-controller@c2a0000 {
 		};
 
 		aoss_qmp: power-controller@c300000 {
-			compatible = "qcom,sc7180-aoss-qmp";
+			compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
 			reg = <0 0x0c300000 0 0x400>;
 			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 			mboxes = <&apss_shared 0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..3eafc50b6abd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3843,7 +3843,7 @@ aoss_reset: reset-controller@c2a0000 {
 		};
 
 		aoss_qmp: power-controller@c300000 {
-			compatible = "qcom,sc7280-aoss-qmp";
+			compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
 			reg = <0 0x0c300000 0 0x400>;
 			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 						     IPCC_MPROC_SIGNAL_GLINK_QMP
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index b72e8e6c52f3..c713aa6e7044 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -552,19 +552,19 @@ rpm_msg_ram: sram@778000 {
 		};
 
 		qfprom: qfprom@780000 {
-			compatible = "qcom,qfprom";
+			compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
 			reg = <0x00780000 0x621c>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			qusb2_hstx_trim: hstx-trim@240 {
-				reg = <0x240 0x1>;
-				bits = <25 3>;
+				reg = <0x243 0x1>;
+				bits = <1 3>;
 			};
 
 			gpu_speed_bin: gpu-speed-bin@41a0 {
-				reg = <0x41a0 0x1>;
-				bits = <21 7>;
+				reg = <0x41a2 0x1>;
+				bits = <5 7>;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8ea44c4b56b4..5725fe47009d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3718,7 +3718,7 @@ pdc: interrupt-controller@b220000 {
 		};
 
 		aoss_qmp: power-controller@c300000 {
-			compatible = "qcom,sm8150-aoss-qmp";
+			compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
 			reg = <0x0 0x0c300000 0x0 0x400>;
 			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 			mboxes = <&apss_shared 0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index cf0c97bd5ad3..c8962acfddbe 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3734,7 +3734,7 @@ tsens1: thermal-sensor@c265000 {
 		};
 
 		aoss_qmp: power-controller@c300000 {
-			compatible = "qcom,sm8250-aoss-qmp";
+			compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
 			reg = <0 0x0c300000 0 0x400>;
 			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 						     IPCC_MPROC_SIGNAL_GLINK_QMP
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 743cba9b683c..dd32b227df49 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1718,7 +1718,7 @@ tsens1: thermal-sensor@c265000 {
 		};
 
 		aoss_qmp: power-controller@c300000 {
-			compatible = "qcom,sm8350-aoss-qmp";
+			compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
 			reg = <0 0x0c300000 0 0x400>;
 			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
 						     IRQ_TYPE_EDGE_RISING>;
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index 142e7ffbd2bd..63e7a39e100e 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
@@ -146,7 +146,7 @@ rgb_panel: endpoint {
 		};
 	};
 
-	reg_audio: regulator_audio {
+	reg_audio: regulator-audio {
 		compatible = "regulator-fixed";
 		regulator-name = "audio-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -174,7 +174,7 @@ reg_lcd_reset: regulator-lcd-reset {
 		vin-supply = <&reg_lcd>;
 	};
 
-	reg_cam0: regulator_camera {
+	reg_cam0: regulator-cam0 {
 		compatible = "regulator-fixed";
 		regulator-name = "reg_cam0";
 		regulator-min-microvolt = <1800000>;
@@ -183,7 +183,7 @@ reg_cam0: regulator_camera {
 		enable-active-high;
 	};
 
-	reg_cam1: regulator_camera {
+	reg_cam1: regulator-cam1 {
 		compatible = "regulator-fixed";
 		regulator-name = "reg_cam1";
 		regulator-min-microvolt = <1800000>;
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index 877d076ffcc9..f5c1d74b738b 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
@@ -20,7 +20,7 @@ osc_32k: osc_32k {
 		clock-output-names = "osc_32k";
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -29,7 +29,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi
index 7231f820d601..ef3bb835d5c0 100644
--- a/arch/arm64/boot/dts/renesas/draak.dtsi
+++ b/arch/arm64/boot/dts/renesas/draak.dtsi
@@ -630,7 +630,7 @@ rsnd_for_ak4613: endpoint {
 				bitclock-master = <&rsnd_for_ak4613>;
 				frame-master = <&rsnd_for_ak4613>;
 				playback = <&ssi3>, <&src5>, <&dvc0>;
-				capture  = <&ssi4>, <&src6>, <&dvc1>;
+				capture = <&ssi4>, <&src6>, <&dvc1>;
 			};
 		};
 	};
diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi
index 72f359efa23e..8fc03491a11c 100644
--- a/arch/arm64/boot/dts/renesas/ebisu.dtsi
+++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi
@@ -145,7 +145,7 @@ memory@48000000 {
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -154,7 +154,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
@@ -163,7 +163,7 @@ reg_3p3v: regulator1 {
 		regulator-always-on;
 	};
 
-	reg_12p0v: regulator2 {
+	reg_12p0v: regulator-12p0v {
 		compatible = "regulator-fixed";
 		regulator-name = "D12.0V";
 		regulator-min-microvolt = <12000000>;
@@ -711,7 +711,7 @@ &rcar_sound {
 	rcar_sound,dai {
 		dai0 {
 			playback = <&ssi0>, <&src0>, <&dvc0>;
-			capture  = <&ssi1>, <&src1>, <&dvc1>;
+			capture = <&ssi1>, <&src1>, <&dvc1>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 935d06515aa6..b062f41ee270 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -53,7 +53,7 @@ led4 {
 		};
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -62,7 +62,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index b6aeb22e8836..c563d26a7a71 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1281,7 +1281,7 @@ port@1 {
 
 					vin4csi40: endpoint@2 {
 						reg = <2>;
-						remote-endpoint= <&csi40vin4>;
+						remote-endpoint = <&csi40vin4>;
 					};
 				};
 			};
@@ -1309,7 +1309,7 @@ port@1 {
 
 					vin5csi40: endpoint@2 {
 						reg = <2>;
-						remote-endpoint= <&csi40vin5>;
+						remote-endpoint = <&csi40vin5>;
 					};
 				};
 			};
@@ -1952,7 +1952,7 @@ thermal-zones {
 		cpu-thermal {
 			polling-delay-passive = <250>;
 			polling-delay = <0>;
-			thermal-sensors = <&thermal 0>;
+			thermal-sensors = <&thermal>;
 			sustainable-power = <717>;
 
 			cooling-maps {
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index d33021202637..565e9d85946e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1324,7 +1324,7 @@ port@1 {
 
 					vin4csi40: endpoint@2 {
 						reg = <2>;
-						remote-endpoint= <&csi40vin4>;
+						remote-endpoint = <&csi40vin4>;
 					};
 				};
 			};
@@ -1352,7 +1352,7 @@ port@1 {
 
 					vin5csi40: endpoint@2 {
 						reg = <2>;
-						remote-endpoint= <&csi40vin5>;
+						remote-endpoint = <&csi40vin5>;
 					};
 				};
 			};
@@ -2129,7 +2129,7 @@ thermal-zones {
 		cpu-thermal {
 			polling-delay-passive = <250>;
 			polling-delay = <0>;
-			thermal-sensors = <&thermal 0>;
+			thermal-sensors = <&thermal>;
 			sustainable-power = <717>;
 
 			cooling-maps {
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index b9731504b7cd..3d668709d8a8 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -41,6 +41,7 @@ a76_0: cpu@0 {
 			device_type = "cpu";
 			power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76_0>;
+			clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>;
 		};
 
 		L3_CA76_0: cache-controller-0 {
@@ -105,7 +106,8 @@ pfc: pinctrl@e6050000 {
 		};
 
 		gpio0: gpio@e6058180 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6058180 0 0x54>;
 			interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 916>;
@@ -119,7 +121,8 @@ gpio0: gpio@e6058180 {
 		};
 
 		gpio1: gpio@e6050180 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6050180 0 0x54>;
 			interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 915>;
@@ -133,7 +136,8 @@ gpio1: gpio@e6050180 {
 		};
 
 		gpio2: gpio@e6050980 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6050980 0 0x54>;
 			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 915>;
@@ -147,7 +151,8 @@ gpio2: gpio@e6050980 {
 		};
 
 		gpio3: gpio@e6058980 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6058980 0 0x54>;
 			interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 916>;
@@ -161,7 +166,8 @@ gpio3: gpio@e6058980 {
 		};
 
 		gpio4: gpio@e6060180 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6060180 0 0x54>;
 			interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 917>;
@@ -175,7 +181,8 @@ gpio4: gpio@e6060180 {
 		};
 
 		gpio5: gpio@e6060980 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6060980 0 0x54>;
 			interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 917>;
@@ -189,7 +196,8 @@ gpio5: gpio@e6060980 {
 		};
 
 		gpio6: gpio@e6068180 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6068180 0 0x54>;
 			interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
@@ -203,7 +211,8 @@ gpio6: gpio@e6068180 {
 		};
 
 		gpio7: gpio@e6068980 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6068980 0 0x54>;
 			interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
@@ -217,7 +226,8 @@ gpio7: gpio@e6068980 {
 		};
 
 		gpio8: gpio@e6069180 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6069180 0 0x54>;
 			interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
@@ -231,7 +241,8 @@ gpio8: gpio@e6069180 {
 		};
 
 		gpio9: gpio@e6069980 {
-			compatible = "renesas,gpio-r8a779a0";
+			compatible = "renesas,gpio-r8a779a0",
+				     "renesas,rcar-gen4-gpio";
 			reg = <0 0xe6069980 0 0x54>;
 			interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD 918>;
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 41aa8591b3b1..81d178e69527 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -60,6 +60,11 @@ scif3_pins: scif3 {
 		function = "scif3";
 	};
 
+	scif0_pins: scif0 {
+		groups = "scif0_data", "scif0_ctrl";
+		function = "scif0";
+	};
+
 	scif_clk_pins: scif_clk {
 		groups = "scif_clk";
 		function = "scif_clk";
@@ -79,6 +84,14 @@ &scif3 {
 	status = "okay";
 };
 
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	status = "okay";
+};
+
 &scif_clk {
 	clock-frequency = <24000000>;
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
index 2e3b719cc749..7a7c8ffba711 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
@@ -15,6 +15,7 @@ / {
 
 	aliases {
 		serial0 = &scif3;
+		serial1 = &scif0;
 	};
 
 	chosen {
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index df46fb87cffc..384817ffa4de 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -18,11 +18,171 @@ cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a55_0>;
+				};
+				core1 {
+					cpu = <&a55_1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a55_2>;
+				};
+				core1 {
+					cpu = <&a55_3>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&a55_4>;
+				};
+				core1 {
+					cpu = <&a55_5>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&a55_6>;
+				};
+				core1 {
+					cpu = <&a55_7>;
+				};
+			};
+		};
+
 		a55_0: cpu@0 {
 			compatible = "arm,cortex-a55";
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA55_0>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+		};
+
+		a55_1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
+			next-level-cache = <&L3_CA55_0>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+		};
+
+		a55_2: cpu@10000 {
+			compatible = "arm,cortex-a55";
+			reg = <0x10000>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
+			next-level-cache = <&L3_CA55_1>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+		};
+
+		a55_3: cpu@10100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x10100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
+			next-level-cache = <&L3_CA55_1>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
+		};
+
+		a55_4: cpu@20000 {
+			compatible = "arm,cortex-a55";
+			reg = <0x20000>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
+			next-level-cache = <&L3_CA55_2>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+		};
+
+		a55_5: cpu@20100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x20100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
+			next-level-cache = <&L3_CA55_2>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+		};
+
+		a55_6: cpu@30000 {
+			compatible = "arm,cortex-a55";
+			reg = <0x30000>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
+			next-level-cache = <&L3_CA55_3>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+		};
+
+		a55_7: cpu@30100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x30100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
+			next-level-cache = <&L3_CA55_3>;
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
+		};
+
+		L3_CA55_0: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779F0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA55_1: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779F0_PD_A2E0D1>;
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA55_2: cache-controller-2 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779F0_PD_A2E1D0>;
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA55_3: cache-controller-3 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779F0_PD_A2E1D1>;
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
 		};
 	};
 
@@ -45,6 +205,11 @@ pmu_a55 {
 		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
 	/* External SCIF clock - to be overridden by boards that provide it */
 	scif_clk: scif {
 		compatible = "fixed-clock";
@@ -157,6 +322,18 @@ sysc: system-controller@e6180000 {
 			#power-domain-cells = <1>;
 		};
 
+		tsc: thermal@e6198000 {
+			compatible = "renesas,r8a779f0-thermal";
+			/* The 4th sensor is in control domain and not for Linux */
+			reg = <0 0xe6198000 0 0x200>,
+			      <0 0xe61a0000 0 0x200>,
+			      <0 0xe61a8000 0 0x200>;
+			clocks = <&cpg CPG_MOD 919>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 919>;
+			#thermal-sensor-cells = <1>;
+		};
+
 		i2c0: i2c@e6500000 {
 			compatible = "renesas,i2c-r8a779f0",
 				     "renesas,rcar-gen4-i2c";
@@ -259,6 +436,120 @@ i2c5: i2c@e66e0000 {
 			status = "disabled";
 		};
 
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a779f0",
+				     "renesas,rcar-gen4-hscif", "renesas,hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 514>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x31>, <&dmac0 0x30>,
+			       <&dmac1 0x31>, <&dmac1 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 514>;
+			status = "disabled";
+		};
+
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a779f0",
+				     "renesas,rcar-gen4-hscif", "renesas,hscif";
+			reg = <0 0xe6550000 0 0x60>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 515>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x33>, <&dmac0 0x32>,
+			       <&dmac1 0x33>, <&dmac1 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 515>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a779f0",
+				     "renesas,rcar-gen4-hscif", "renesas,hscif";
+			reg = <0 0xe6560000 0 0x60>;
+			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x35>, <&dmac0 0x34>,
+			       <&dmac1 0x35>, <&dmac1 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 516>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a779f0",
+				     "renesas,rcar-gen4-hscif", "renesas,hscif";
+			reg = <0 0xe66a0000 0 0x60>;
+			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x37>, <&dmac0 0x36>,
+			       <&dmac1 0x37>, <&dmac1 0x36>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		ufs: ufs@e6860000 {
+			compatible = "renesas,r8a779f0-ufs";
+			reg = <0 0xe6860000 0 0x100>;
+			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+			clock-names = "fck", "ref_clk";
+			freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 1514>;
+			status = "disabled";
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a779f0",
+				     "renesas,rcar-gen4-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 64>;
+			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x51>, <&dmac0 0x50>,
+			       <&dmac1 0x51>, <&dmac1 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 702>;
+			status = "disabled";
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a779f0",
+				     "renesas,rcar-gen4-scif", "renesas,scif";
+			reg = <0 0xe6e68000 0 64>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x53>, <&dmac0 0x52>,
+			       <&dmac1 0x53>, <&dmac1 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
 		scif3: serial@e6c50000 {
 			compatible = "renesas,scif-r8a779f0",
 				     "renesas,rcar-gen4-scif", "renesas,scif";
@@ -268,11 +559,31 @@ scif3: serial@e6c50000 {
 				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
 				 <&scif_clk>;
 			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x57>, <&dmac0 0x56>,
+			       <&dmac1 0x57>, <&dmac1 0x56>;
+			dma-names = "tx", "rx", "tx", "rx";
 			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 			resets = <&cpg 704>;
 			status = "disabled";
 		};
 
+		scif4: serial@e6c40000 {
+			compatible = "renesas,scif-r8a779f0",
+				     "renesas,rcar-gen4-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 64>;
+			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 705>,
+				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac0 0x59>, <&dmac0 0x58>,
+			       <&dmac1 0x59>, <&dmac1 0x58>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 705>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller@e7350000 {
 			compatible = "renesas,dmac-r8a779f0",
 				     "renesas,rcar-gen4-dmac";
@@ -306,6 +617,14 @@ dmac0: dma-controller@e7350000 {
 			resets = <&cpg 709>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+				 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+				 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+				 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+				 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+				 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+				 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+				 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
 		};
 
 		dmac1: dma-controller@e7351000 {
@@ -341,6 +660,60 @@ dmac1: dma-controller@e7351000 {
 			resets = <&cpg 710>;
 			#dma-cells = <1>;
 			dma-channels = <16>;
+			iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
+				 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
+				 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
+				 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
+				 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
+				 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
+				 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
+				 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
+		};
+
+		ipmmu_rt0: iommu@ee480000 {
+			compatible = "renesas,ipmmu-r8a779f0",
+				     "renesas,rcar-gen4-ipmmu-vmsa";
+			reg = <0 0xee480000 0 0x20000>;
+			renesas,ipmmu-main = <&ipmmu_mm 10>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_rt1: iommu@ee4c0000 {
+			compatible = "renesas,ipmmu-r8a779f0",
+				     "renesas,rcar-gen4-ipmmu-vmsa";
+			reg = <0 0xee4c0000 0 0x20000>;
+			renesas,ipmmu-main = <&ipmmu_mm 19>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_ds0: iommu@eed00000 {
+			compatible = "renesas,ipmmu-r8a779f0",
+				     "renesas,rcar-gen4-ipmmu-vmsa";
+			reg = <0 0xeed00000 0 0x20000>;
+			renesas,ipmmu-main = <&ipmmu_mm 0>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_hc: iommu@eed40000 {
+			compatible = "renesas,ipmmu-r8a779f0",
+				     "renesas,rcar-gen4-ipmmu-vmsa";
+			reg = <0 0xeed40000 0 0x20000>;
+			renesas,ipmmu-main = <&ipmmu_mm 2>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
+		};
+
+		ipmmu_mm: iommu@eefc0000 {
+			compatible = "renesas,ipmmu-r8a779f0",
+				     "renesas,rcar-gen4-ipmmu-vmsa";
+			reg = <0 0xeefc0000 0 0x20000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			#iommu-cells = <1>;
 		};
 
 		gic: interrupt-controller@f1000000 {
@@ -351,7 +724,7 @@ gic: interrupt-controller@f1000000 {
 			reg = <0x0 0xf1000000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x110000>;
 			interrupts = <GIC_PPI 9
-				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+				      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
 		prr: chipid@fff00044 {
@@ -360,11 +733,62 @@ prr: chipid@fff00044 {
 		};
 	};
 
+	thermal-zones {
+		sensor_thermal1: sensor1-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 0>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal2: sensor2-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 1>;
+
+			trips {
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor_thermal3: sensor3-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&tsc 2>;
+
+			trips {
+				sensor3_crit: sensor3-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	ufs30_clk: ufs30-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
 	};
 };
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index b31fb713ae4d..40201a16d653 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -483,8 +483,27 @@ i2c3: i2c@10058c00 {
 		};
 
 		adc: adc@10059000 {
+			compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
 			reg = <0 0x10059000 0 0x400>;
-			/* place holder */
+			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
+				 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A07G043_ADC_PRESETN>,
+				 <&cpg R9A07G043_ADC_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			channel@0 {
+				reg = <0>;
+			};
+			channel@1 {
+				reg = <1>;
+			};
 		};
 
 		tsu: thermal@10059400 {
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 2d740bd420ca..121e55282d18 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -13,9 +13,3 @@ / {
 	model = "Renesas SMARC EVK based on r9a07g043u11";
 	compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
 };
-
-&spi1 {
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index c207d8ce5523..c3a52fa0b16e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -14,6 +14,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &avb;
 	};
 
 	chosen {
@@ -35,6 +36,19 @@ memory@180000000 {
 	};
 };
 
+&avb {
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	phy-mode = "gmii";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id001c.c916",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
 &extal_clk {
 	clock-frequency = <48000000>;
 };
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 27810f4ad4cb..d4cc5459fbb7 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -62,6 +62,57 @@ gic: interrupt-controller@82000000 {
 			clock-names = "clk";
 		};
 
+		avb: ethernet@a3300000 {
+			compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+			reg = <0 0xa3300000 0 0x800>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
+				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "dia", "dib",
+					  "err_a", "err_b", "mgmt_a", "mgmt_b",
+					  "line3";
+			clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
+			clock-names = "axi", "chi", "gptp";
+			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disable";
+		};
+
 		cpg: clock-controller@a3500000 {
 			compatible = "renesas,r9a09g011-cpg";
 			reg = <0 0xa3500000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index aeacd22e9eb0..9410796c8ad6 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -34,7 +34,7 @@ memory@48000000 {
 		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -43,7 +43,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 959a0ad1d367..78e6e2376b01 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -23,7 +23,7 @@ memory@48000000 {
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -32,7 +32,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index aa170492dd2b..6be25a8a28db 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -29,7 +29,7 @@
 #define SW_RSPI_CAN	1
 #endif
 
-#if (SW_SCIF_CAN & SW_RSPI_CAN)
+#if (SW_SCIF_CAN && SW_RSPI_CAN)
 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
 #endif
 
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index a663115f5aae..cf3b3d118ef1 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -24,7 +24,7 @@ memory@48000000 {
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -33,7 +33,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
@@ -57,6 +57,14 @@ vccq_sdhi0: regulator-vccq-sdhi0 {
 #endif
 };
 
+#if (SW_SW0_DEV_SEL)
+&adc {
+	pinctrl-0 = <&adc_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+#endif
+
 #if (!SW_ET0_EN_N)
 &eth0 {
 	pinctrl-0 = <&eth0_pins>;
@@ -124,6 +132,10 @@ &ostm2 {
 };
 
 &pinctrl {
+	adc_pins: adc {
+		pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
+	};
+
 	eth0_pins: eth0 {
 		pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
 			 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
@@ -209,6 +221,13 @@ sd0_mux_uhs {
 			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
 		};
 	};
+
+	spi1_pins: rspi1 {
+		pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
+			 <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
+			 <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
+			 <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
+	};
 };
 
 #if (SW_SW0_DEV_SEL)
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
index 0051634d7b1c..f9835c12023e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
@@ -51,6 +51,12 @@ &snd_rzg2l {
 	status = "disabled";
 };
 
+&spi1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-names;
+	status = "disabled";
+};
+
 &ssi1 {
 	/delete-property/ pinctrl-0;
 	/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 31837fcd7bf0..b7c7911858b2 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -170,7 +170,7 @@ key-c {
 		};
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -179,7 +179,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
@@ -188,7 +188,7 @@ reg_3p3v: regulator1 {
 		regulator-always-on;
 	};
 
-	reg_12v: regulator2 {
+	reg_12v: regulator-12v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-12V";
 		regulator-min-microvolt = <12000000>;
@@ -832,7 +832,7 @@ rsnd_endpoint0: endpoint {
 				frame-master = <&rsnd_endpoint0>;
 
 				playback = <&ssi0>, <&src0>, <&dvc0>;
-				capture  = <&ssi1>, <&src1>, <&dvc1>;
+				capture = <&ssi1>, <&src1>, <&dvc1>;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 5bcb84403ef6..408871c2859d 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -206,12 +206,12 @@ pcm3168a: audio-codec@44 {
 				clocks = <&clksndsel>;
 				clock-names = "scki";
 
-				VDD1-supply	= <&snd_3p3v>;
-				VDD2-supply	= <&snd_3p3v>;
-				VCCAD1-supply	= <&snd_vcc5v>;
-				VCCAD2-supply	= <&snd_vcc5v>;
-				VCCDA1-supply	= <&snd_vcc5v>;
-				VCCDA2-supply	= <&snd_vcc5v>;
+				VDD1-supply = <&snd_3p3v>;
+				VDD2-supply = <&snd_3p3v>;
+				VCCAD1-supply = <&snd_vcc5v>;
+				VCCAD2-supply = <&snd_vcc5v>;
+				VCCDA1-supply = <&snd_vcc5v>;
+				VCCDA2-supply = <&snd_vcc5v>;
 
 				ports {
 					#address-cells = <1>;
@@ -438,7 +438,7 @@ rsnd_for_pcm3168a_capture: endpoint {
 				bitclock-master;
 				frame-master;
 				dai-tdm-slot-num = <6>;
-				capture  = <&ssi4>;
+				capture = <&ssi4>;
 			};
 		};
 	};
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 90a4c0629d24..0772dfe4adff 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -76,7 +76,7 @@ led6 {
 		};
 	};
 
-	reg_1p8v: regulator0 {
+	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -85,7 +85,7 @@ reg_1p8v: regulator0 {
 		regulator-always-on;
 	};
 
-	reg_3p3v: regulator1 {
+	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
@@ -411,7 +411,7 @@ rsnd_for_ak4613: endpoint {
 				bitclock-master;
 				frame-master;
 				playback = <&ssi0>, <&src0>, <&dvc0>;
-				capture  = <&ssi1>, <&src1>, <&dvc1>;
+				capture = <&ssi1>, <&src1>, <&dvc1>;
 			};
 		};
 		rsnd_port1: port@1 {
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 18d00eae3072..ef79a672804a 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 56dfbb2e2fa6..214f94fea3dc 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -528,7 +528,7 @@ uart5: serial@ff178000 {
 	i2c0: i2c@ff180000 {
 		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 		reg = <0x0 0xff180000 0x0 0x1000>;
-		clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
+		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 		clock-names = "i2c", "pclk";
 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
index 9b4f855ea5d4..9fe9b0d11003 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
@@ -75,7 +75,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
new file mode 100644
index 000000000000..a71f249ed384
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
+ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+	model = "Radxa ROCK Pi S";
+	compatible = "radxa,rockpis", "rockchip,rk3308";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
+
+		green-led {
+			default-state = "on";
+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+			label = "rockpis:green:power";
+			linux,default-trigger = "default-on";
+		};
+
+		blue-led {
+			default-state = "on";
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+			label = "rockpis:blue:user";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-0 = <&wifi_enable_h>;
+		pinctrl-names = "default";
+		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_io: vcc-io {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_io";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_ddr: vcc-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_ddr";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "vcc5v0_otg";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdd_core: vdd-core {
+		compatible = "pwm-regulator";
+		pwms = <&pwm0 0 5000 1>;
+		pwm-supply = <&vcc5v0_sys>;
+		regulator-name = "vdd_core";
+		regulator-min-microvolt = <827000>;
+		regulator-max-microvolt = <1340000>;
+		regulator-init-microvolt = <1015000>;
+		regulator-settling-time-up-us = <250>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_io>;
+	status = "okay";
+};
+
+&gmac {
+	clock_in_out = "output";
+	phy-supply = <&vcc_io>;
+	snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 50000>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rtc_32k>;
+
+	leds {
+		green_led_gio: green-led-gpio {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		heartbeat_led_gpio: heartbeat-led-gpio {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake: wifi-host-wake {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_pin_pull_down>;
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdio {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	max-frequency = <1000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	cap-sd-highspeed;
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+
+	u2phy_host: host-port {
+		phy-supply = <&vcc5v0_otg>;
+		status = "okay";
+	};
+
+	u2phy_otg: otg-port {
+		phy-supply = <&vcc5v0_otg>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "realtek,rtl8723bs-bt";
+		device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&usb_host_ehci {
+	status = "okay";
+};
+
+&usb_host_ohci {
+	status = "okay";
+};
+
+&usb20_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index ea0695b51ecd..415aa9ff8bd4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -71,82 +71,82 @@ gpio-keys {
 		 * |------------------------------------------------|
 		 */
 
-		sw1 {
+		button-sw1 {
 			gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
 			label = "DPAD-UP";
 			linux,code = <BTN_DPAD_UP>;
 		};
-		sw2 {
+		button-sw2 {
 			gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
 			label = "DPAD-DOWN";
 			linux,code = <BTN_DPAD_DOWN>;
 		};
-		sw3 {
+		button-sw3 {
 			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
 			label = "DPAD-LEFT";
 			linux,code = <BTN_DPAD_LEFT>;
 		};
-		sw4 {
+		button-sw4 {
 			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
 			label = "DPAD-RIGHT";
 			linux,code = <BTN_DPAD_RIGHT>;
 		};
-		sw5 {
+		button-sw5 {
 			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "BTN-A";
 			linux,code = <BTN_EAST>;
 		};
-		sw6 {
+		button-sw6 {
 			gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "BTN-B";
 			linux,code = <BTN_SOUTH>;
 		};
-		sw7 {
+		button-sw7 {
 			gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
 			label = "BTN-Y";
 			linux,code = <BTN_WEST>;
 		};
-		sw8 {
+		button-sw8 {
 			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
 			label = "BTN-X";
 			linux,code = <BTN_NORTH>;
 		};
-		sw9 {
+		button-sw9 {
 			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
 			label = "F1";
 			linux,code = <BTN_TRIGGER_HAPPY1>;
 		};
-		sw10 {
+		button-sw10 {
 			gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
 			label = "F2";
 			linux,code = <BTN_TRIGGER_HAPPY2>;
 		};
-		sw11 {
+		button-sw11 {
 			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "F3";
 			linux,code = <BTN_TRIGGER_HAPPY3>;
 		};
-		sw12 {
+		button-sw12 {
 			gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
 			label = "F4";
 			linux,code = <BTN_TRIGGER_HAPPY4>;
 		};
-		sw13 {
+		button-sw13 {
 			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
 			label = "F5";
 			linux,code = <BTN_TRIGGER_HAPPY5>;
 		};
-		sw14 {
+		button-sw14 {
 			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "F6";
 			linux,code = <BTN_TRIGGER_HAPPY6>;
 		};
-		sw15 {
+		button-sw15 {
 			gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
 			label = "TOP-LEFT";
 			linux,code = <BTN_TL>;
 		};
-		sw16 {
+		button-sw16 {
 			gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
 			label = "TOP-RIGHT";
 			linux,code = <BTN_TR>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
index 3857d487ab84..1445b879ac7a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -34,7 +34,7 @@ keys {
 		pinctrl-0 = <&reset_button_pin>;
 		pinctrl-names = "default";
 
-		reset {
+		key-reset {
 			label = "reset";
 			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_RESTART>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index 15d1fc541c38..083452c67711 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -76,7 +76,7 @@ keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
index 62aa97a0b8c9..be06e6e64d18 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
@@ -43,7 +43,7 @@ keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index 3ebe15e03cf4..7f5bba0c6001 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -44,7 +44,7 @@ keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
 			label = "GPIO Power";
@@ -134,7 +134,7 @@ vcc_sys: vcc-sys-regulator {
 
 	vccio_sd: vcc-io-sd-regulator {
 		compatible = "regulator-fixed";
-		regulator-name= "vccio_sd";
+		regulator-name = "vccio_sd";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 5ccaa5f7a370..29df84b81552 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -30,7 +30,7 @@ keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index 959d3cc801f2..38d757c00548 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -37,7 +37,7 @@ keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key>;
 
-		power {
+		key-power {
 			wakeup-source;
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 4f0b5feaa5e6..a4c5aaf1f457 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -1084,7 +1084,7 @@ emmc_bus8: emmc-bus8 {
 
 		gmac {
 			rgmii_pins: rgmii-pins {
-				rockchip,pins =	<3 RK_PC6 1 &pcfg_pull_none>,
+				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
 						<3 RK_PD0 1 &pcfg_pull_none>,
 						<3 RK_PC3 1 &pcfg_pull_none>,
 						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
@@ -1102,7 +1102,7 @@ rgmii_pins: rgmii-pins {
 			};
 
 			rmii_pins: rmii-pins {
-				rockchip,pins =	<3 RK_PC6 1 &pcfg_pull_none>,
+				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
 						<3 RK_PD0 1 &pcfg_pull_none>,
 						<3 RK_PC3 1 &pcfg_pull_none>,
 						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
@@ -1257,7 +1257,7 @@ sdmmc_bus4: sdmmc-bus4 {
 
 		spdif {
 			spdif_tx: spdif-tx {
-				rockchip,pins =	<2 RK_PC7 1 &pcfg_pull_none>;
+				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 7b717ebec8ff..3d1e126b553f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -55,7 +55,7 @@ backlight: backlight {
 	};
 
 	edp_panel: edp-panel {
-		compatible ="lg,lp079qx1-sp0v";
+		compatible = "lg,lp079qx1-sp0v";
 		backlight = <&backlight>;
 		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
 		power-supply = <&vcc3v3_s0>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index b340c9e246c4..c5db64f3e124 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -87,7 +87,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Key Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 50d459ee4831..cd074641884b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -206,7 +206,7 @@ gpio_keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&bt_host_wake_l>;
 
-		wake_on_bt: wake-on-bt {
+		wake_on_bt: key-wake-on-bt {
 			label = "Wake-on-Bluetooth";
 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
index 6863689df06f..2cc9b3386c16 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@@ -92,7 +92,7 @@ &gpio_keys {
 	pinctrl-names = "default";
 	pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
 
-	pen-insert {
+	switch-pen-insert {
 		label = "Pen Insert";
 		/* Insert = low, eject = high */
 		gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index 913d845eb51a..40d4053fba80 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -183,7 +183,7 @@ gpio_keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pen_eject_odl>;
 
-		pen-insert {
+		switch-pen-insert {
 			label = "Pen Insert";
 			/* Insert = low, eject = high */
 			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -376,7 +376,8 @@ &cru {
 		<&cru ACLK_VIO>,
 		<&cru ACLK_GIC_PRE>,
 		<&cru PCLK_DDR>,
-		<&cru ACLK_HDCP>;
+		<&cru ACLK_HDCP>,
+		<&cru ACLK_VDU>;
 	assigned-clock-rates =
 		<600000000>, <1600000000>,
 		<1000000000>,
@@ -388,6 +389,7 @@ &cru {
 		<400000000>,
 		<200000000>,
 		<200000000>,
+		<400000000>,
 		<400000000>;
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
index 46c4581deb8d..2a332763c35c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
@@ -136,7 +136,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Key Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index cef4d18b599d..fe5b52610010 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -46,9 +46,9 @@ wan_led: led-wan {
 	gpio-keys {
 		pinctrl-0 = <&reset_button_pin>;
 
-		/delete-node/ power;
+		/delete-node/ key-power;
 
-		reset {
+		key-reset {
 			debounce-interval = <50>;
 			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
 			label = "reset";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 248ad41a976b..278123b4f911 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -111,7 +111,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&power_key>;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Key Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
index ed856bfcfc33..9e2e246e0bab 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
@@ -78,7 +78,7 @@ keys: gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
index d6b68d77d63a..194e48c755f6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -76,7 +76,7 @@ gpio-key-lid {
 		pinctrl-names = "default";
 		pinctrl-0 = <&lidbtn_pin>;
 
-		lid {
+		switch-lid {
 			debounce-interval = <20>;
 			gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
 			label = "Lid";
@@ -92,7 +92,7 @@ gpio-key-power {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn_pin>;
 
-		power {
+		key-power {
 			debounce-interval = <20>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index 3ae5d727e367..04c752f49be9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -49,7 +49,7 @@ simple-audio-card,cpu {
 	sgtl5000_clk: sgtl5000-oscillator  {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency  = <24576000>;
+			clock-frequency = <24576000>;
 	};
 
 	dc_12v: dc-12v {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index 0e45cc2d195b..acb174d3a8c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -54,7 +54,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwr_key_l>;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Key Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 45e77f86d329..78157521e944 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -20,6 +20,15 @@ chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	/* enable for panel backlight support */
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <5>;
+		pwms = <&pwm0 0 1000000 0>;
+		status = "disabled";
+	};
+
 	clkin_gmac: external-gmac-clock {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
@@ -33,7 +42,7 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Key Power";
@@ -107,6 +116,14 @@ dit_p0_0: endpoint {
 		};
 	};
 
+	avdd: avdd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd";
+		regulator-min-microvolt = <11000000>;
+		regulator-max-microvolt = <11000000>;
+		vin-supply = <&vcc3v3_s0>;
+	};
+
 	vcc12v_dcin: vcc12v-dcin {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";
@@ -400,8 +417,6 @@ regulator-state-mem {
 
 			vcc3v0_touch: LDO_REG2 {
 				regulator-name = "vcc3v0_touch";
-				regulator-always-on;
-				regulator-boot-on;
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3000000>;
 				regulator-state-mem {
@@ -490,8 +505,6 @@ regulator-state-mem {
 
 			vcc3v3_s0: SWITCH_REG2 {
 				regulator-name = "vcc3v3_s0";
-				regulator-always-on;
-				regulator-boot-on;
 				regulator-state-mem {
 					regulator-off-in-suspend;
 				};
@@ -565,6 +578,19 @@ fusb0: typec-portc@22 {
 		vbus-supply = <&vcc5v0_typec>;
 		status = "okay";
 	};
+
+	/* enable for pine64 touch screen support */
+	touch: touchscreen@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;
+		AVDD28-supply = <&vcc3v0_touch>;
+		VDDIO-supply = <&vcc3v0_touch>;
+		irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
 };
 
 &i2s0 {
@@ -600,6 +626,42 @@ &io_domains {
 	gpio1830-supply = <&vcc_3v0>;
 };
 
+/* enable for pine64 panel display support */
+&mipi_dsi {
+	clock-master;
+	status = "disabled";
+
+	ports {
+		mipi_out: port@1 {
+			reg = <1>;
+
+			mipi_out_panel: endpoint {
+				remote-endpoint = <&mipi_in_panel>;
+			};
+		};
+	};
+
+	mipi_panel: panel@0 {
+		compatible = "feiyang,fy07024di26a30d";
+		reg = <0>;
+		avdd-supply = <&avdd>;
+		backlight = <&backlight>;
+		dvdd-supply = <&vcc3v3_s0>;
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				mipi_in_panel: endpoint {
+					remote-endpoint = <&mipi_out_panel>;
+				};
+			};
+		};
+	};
+};
+
 &pcie0 {
 	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
index f6b2199a42bd..13927e7d0724 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
@@ -88,7 +88,7 @@ backlight: backlight {
 	};
 
 	edp_panel: edp-panel {
-		compatible ="lg,lp079qx1-sp0v";
+		compatible = "lg,lp079qx1-sp0v";
 		backlight = <&backlight>;
 		enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 2aa0fad8f893..e6ac292ce645 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -53,7 +53,7 @@ keys: gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
 
-		power {
+		key-power {
 			debounce-interval = <100>;
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index fbd0346624e6..9d5b0e8c9cca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1462,7 +1462,8 @@ cru: clock-controller@ff760000 {
 			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 			<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
 			<&cru ACLK_GIC_PRE>,
-			<&cru PCLK_DDR>;
+			<&cru PCLK_DDR>,
+			<&cru ACLK_VDU>;
 		assigned-clock-rates =
 			 <594000000>,  <800000000>,
 			<1000000000>,
@@ -1473,7 +1474,8 @@ cru: clock-controller@ff760000 {
 			 <100000000>,   <50000000>,
 			 <400000000>, <400000000>,
 			 <200000000>,
-			 <200000000>;
+			 <200000000>,
+			 <400000000>;
 	};
 
 	grf: syscon@ff770000 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index 01d1a75c8b4d..935b8c68a71d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -347,7 +347,7 @@ hym8563_int: hym8563-int {
 
 	pcie {
 		pcie_pwr: pcie-pwr {
-			rockchip,pins =	<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
index e01668e6e5f9..0d45868132b9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
@@ -49,7 +49,7 @@ gpio-keys {
 		pinctrl-0 = <&hall_int_l>;
 		pinctrl-names = "default";
 
-		cover {
+		switch-cover {
 			label = "cover";
 			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
 			linux,input-type = <EV_SW>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 1534e11a9ad1..d943559b157c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3566.dtsi"
 
 / {
@@ -32,9 +33,22 @@ fan: gpio_fan {
 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
 		gpio-fan,speed-map = <0    0
 				      4500 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fan_en_h>;
 		#cooling-cells = <2>;
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -125,6 +139,18 @@ vbus: vbus {
 		vin-supply = <&vcc12v_dcin>;
 	};
 
+	vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_enable_h>;
+		regulator-name = "vcc3v3_pcie_p";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
 	vcc5v0_usb: vcc5v0_usb {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_usb";
@@ -201,6 +227,10 @@ &combphy1 {
 	status = "okay";
 };
 
+&combphy2 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -262,6 +292,28 @@ &gpu {
 	status = "okay";
 };
 
+&hdmi {
+	avdd-0v9-supply = <&vdda_0v9>;
+	avdd-1v8-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -492,6 +544,10 @@ &i2c3 {
 	status = "okay";
 };
 
+&i2s0_8ch {
+	status = "okay";
+};
+
 &i2s1_8ch {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2s1m0_sclktx
@@ -509,6 +565,14 @@ rgmii_phy1: ethernet-phy@0 {
 	};
 };
 
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_p>;
+	status = "okay";
+};
+
 &pinctrl {
 	bt {
 		bt_enable_h: bt-enable-h {
@@ -524,6 +588,12 @@ bt_wake_l: bt-wake-l {
 		};
 	};
 
+	fan {
+		fan_en_h: fan-en-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	leds {
 		work_led_enable_h: work-led-enable-h {
 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -534,6 +604,16 @@ diy_led_enable_h: diy-led-enable-h {
 		};
 	};
 
+	pcie {
+		pcie_enable_h: pcie-enable-h {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		pmic_int_l: pmic-int-l {
 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -588,6 +668,7 @@ &sdmmc0 {
 	disable-wp;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
 	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
@@ -608,6 +689,22 @@ &sdmmc1 {
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 /* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";
@@ -687,6 +784,7 @@ &usb_host1_ohci {
 };
 
 &usb_host0_xhci {
+	dr_mode = "host";
 	status = "okay";
 };
 
@@ -722,3 +820,20 @@ &usb2phy1_otg {
 	phy-supply = <&vcc5v0_usb20_host>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
index 7bdcecc0dfe4..02d5f5a8ca03 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
@@ -133,7 +133,7 @@ &gmac1 {
 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
 	clock_in_out = "input";
-	phy-mode = "rgmii-id";
+	phy-mode = "rgmii";
 	phy-supply = <&vcc_3v3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&gmac1m1_miim
diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 0b957068ff89..6c4b17d27bdc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -29,3 +29,7 @@ &usb_host0_xhci {
 	extcon = <&usb2phy0>;
 	maximum-speed = "high-speed";
 };
+
+&vop {
+	compatible = "rockchip,rk3566-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
index 40cf2236c0b6..5e34bd0b214d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
@@ -54,6 +55,17 @@ dc_12v: dc-12v {
 		regulator-max-microvolt = <12000000>;
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	vcc3v3_sys: vcc3v3-sys {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_sys";
@@ -174,6 +186,33 @@ &gmac1m1_rgmii_clk
 	status = "okay";
 };
 
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -215,6 +254,7 @@ regulator-state-mem {
 
 			vdd_gpu: DCDC_REG2 {
 				regulator-name = "vdd_gpu";
+				regulator-always-on;
 				regulator-init-microvolt = <900000>;
 				regulator-initial-mode = <0x2>;
 				regulator-min-microvolt = <500000>;
@@ -264,6 +304,7 @@ regulator-state-mem {
 
 			vdda0v9_image: LDO_REG1 {
 				regulator-name = "vdda0v9_image";
+				regulator-always-on;
 				regulator-min-microvolt = <900000>;
 				regulator-max-microvolt = <900000>;
 
@@ -359,6 +400,7 @@ regulator-state-mem {
 
 			vcca1v8_image: LDO_REG9 {
 				regulator-name = "vcca1v8_image";
+				regulator-always-on;
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
 
@@ -389,11 +431,81 @@ regulator-state-mem {
 	};
 };
 
+&i2c3 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "rtcic_32kout";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
 &i2c5 {
 	/* pin 3 (SDA) + 4 (SCL) of header con2 */
 	status = "disabled";
 };
 
+&i2s0_8ch {
+	/* hdmi sound */
+	status = "okay";
+};
+
+&mdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	switch@0 {
+		compatible = "mediatek,mt7531";
+		reg = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				label = "lan0";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan1";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan3";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "cpu";
+				ethernet = <&gmac0>;
+				phy-mode = "rgmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					pause;
+				};
+			};
+		};
+	};
+};
+
 &mdio1 {
 	rgmii_phy1: ethernet-phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c22";
@@ -411,6 +523,12 @@ green_led_pin: green-led-pin {
 		};
 	};
 
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		pmic_int: pmic_int {
 			rockchip,pins =
@@ -523,6 +641,8 @@ &spi3 {
 };
 
 &tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
 	status = "okay";
 };
 
@@ -587,3 +707,20 @@ &usb2phy0_otg {
 	phy-supply = <&vcc5v0_usb_otg>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index 622be8be9813..777b1615bd08 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
@@ -34,6 +35,17 @@ dc_12v: dc-12v {
 		regulator-max-microvolt = <12000000>;
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -209,6 +221,24 @@ &gpu {
 	status = "okay";
 };
 
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -635,3 +665,20 @@ &usb2phy1_otg {
 	phy-supply = <&vcc5v0_usb_host>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 0813c0c5abde..da2ef705ce29 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -4,6 +4,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
@@ -20,6 +21,17 @@ chosen: chosen {
 		stdout-path = "serial2:1500000n8";
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -166,6 +178,24 @@ &gpu {
 	status = "okay";
 };
 
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -560,3 +590,20 @@ &usb2phy1_otg {
 	phy-supply = <&vcc5v0_usb_host>;
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 5eafddf62edc..2bdf8c7e9765 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -137,3 +137,7 @@ &usb_host0_xhci {
 	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
 	phy-names = "usb2-phy", "usb3-phy";
 };
+
+&vop {
+	compatible = "rockchip,rk3568-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 914f13c0d399..319981c3e9f7 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -129,6 +129,11 @@ opp-1800000000 {
 		};
 	};
 
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
 	firmware {
 		scmi: scmi {
 			compatible = "arm,scmi-smc";
@@ -178,6 +183,22 @@ opp-800000000 {
 		};
 	};
 
+	hdmi_sound: hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "HDMI";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		status = "disabled";
+
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a55-pmu";
 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
@@ -632,6 +653,84 @@ gmac1_mtl_tx_setup: tx-queues-config {
 		};
 	};
 
+	vop: vop@fe040000 {
+		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+		reg-names = "vop", "gamma-lut";
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
+			 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
+		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
+		iommus = <&vop_mmu>;
+		power-domains = <&power RK3568_PD_VO>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		vop_out: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vp0: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			vp1: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			vp2: port@2 {
+				reg = <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	vop_mmu: iommu@fe043e00 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
+	hdmi: hdmi@fe0a0000 {
+		compatible = "rockchip,rk3568-dw-hdmi";
+		reg = <0x0 0xfe0a0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_HDMI_HOST>,
+			 <&cru CLK_HDMI_SFR>,
+			 <&cru CLK_HDMI_CEC>,
+			 <&pmucru CLK_HDMI_REF>,
+			 <&cru HCLK_VO>;
+		clock-names = "iahb", "isfr", "cec", "ref";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
+		power-domains = <&power RK3568_PD_VO>;
+		reg-io-width = <4>;
+		rockchip,grf = <&grf>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_in: port@0 {
+				reg = <0>;
+			};
+
+			hdmi_out: port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	qos_gpu: qos@fe128000 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe128000 0x0 0x20>;
@@ -752,6 +851,56 @@ qos_vop_m1: qos@fe1a8100 {
 		reg = <0x0 0xfe1a8100 0x0 0x20>;
 	};
 
+	pcie2x1: pcie@fe260000 {
+		compatible = "rockchip,rk3568-pcie";
+		reg = <0x3 0xc0000000 0x0 0x00400000>,
+		      <0x0 0xfe260000 0x0 0x00010000>,
+		      <0x3 0x3f000000 0x0 0x01000000>;
+		reg-names = "dbi", "apb", "config";
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "sys", "pmc", "msi", "legacy", "err";
+		bus-range = <0x0 0xf>;
+		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
+			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
+			 <&cru CLK_PCIE20_AUX_NDFT>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk", "aux";
+		device_type = "pci";
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc 0>,
+				<0 0 0 2 &pcie_intc 1>,
+				<0 0 0 3 &pcie_intc 2>,
+				<0 0 0 4 &pcie_intc 3>;
+		linux,pci-domain = <0>;
+		num-ib-windows = <6>;
+		num-ob-windows = <2>;
+		max-link-speed = <2>;
+		msi-map = <0x0 &gic 0x0 0x1000>;
+		num-lanes = <1>;
+		phys = <&combphy2 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3568_PD_PIPE>;
+		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
+			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
+		resets = <&cru SRST_PCIE20_POWERUP>;
+		reset-names = "pipe";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		status = "disabled";
+
+		pcie_intc: legacy-interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+
 	sdmmc0: mmc@fe2b0000 {
 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe2b0000 0x0 0x4000>;
@@ -818,6 +967,23 @@ spdif: spdif@fe460000 {
 		status = "disabled";
 	};
 
+	i2s0_8ch: i2s@fe400000 {
+		compatible = "rockchip,rk3568-i2s-tdm";
+		reg = <0x0 0xfe400000 0x0 0x1000>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
+		assigned-clock-rates = <1188000000>, <1188000000>;
+		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac1 0>;
+		dma-names = "tx";
+		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,grf = <&grf>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
 	i2s1_8ch: i2s@fe410000 {
 		compatible = "rockchip,rk3568-i2s-tdm";
 		reg = <0x0 0xfe410000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi
index 231436be0e3f..8bb8a70966d2 100644
--- a/arch/arm64/boot/dts/sprd/sc9836.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi
@@ -207,11 +207,11 @@ gic: interrupt-controller@12001000 {
 	};
 
 	psci {
-		compatible	= "arm,psci";
-		method		= "smc";
-		cpu_on		= <0xc4000003>;
-		cpu_off		= <0x84000002>;
-		cpu_suspend	= <0xc4000001>;
+		compatible = "arm,psci";
+		method = "smc";
+		cpu_on = <0xc4000003>;
+		cpu_off = <0x84000002>;
+		cpu_suspend = <0xc4000001>;
 	};
 
 	timer {
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
index 8cf4a6575980..22d81ace740a 100644
--- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
@@ -552,7 +552,7 @@ ap-ahb {
 			ranges;
 
 			sdio0: sdio@20300000 {
-				compatible  = "sprd,sdhci-r11";
+				compatible = "sprd,sdhci-r11";
 				reg = <0 0x20300000 0 0x1000>;
 				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -568,7 +568,7 @@ sdio0: sdio@20300000 {
 			};
 
 			sdio3: sdio@20600000 {
-				compatible  = "sprd,sdhci-r11";
+				compatible = "sprd,sdhci-r11";
 				reg = <0 0x20600000 0 0x1000>;
 				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index 89d91abbd5d1..fece49704b5c 100644
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -134,7 +134,7 @@ ap_dma: dma-controller@20100000 {
 			};
 
 			sdio3: sdio@50430000 {
-				compatible  = "sprd,sdhci-r11";
+				compatible = "sprd,sdhci-r11";
 				reg = <0 0x50430000 0 0x1000>;
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 
diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 5af560c1b5e6..1db6ddf03f01 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -37,3 +37,7 @@ &fin_pll {
 &serial_0 {
 	status = "okay";
 };
+
+&ufs {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d4d0cb005712..d0abb9aa0e9e 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -8,7 +8,7 @@
  *		https://www.tesla.com
  */
 
-#include <dt-bindings/pinctrl/samsung.h>
+#include "fsd-pinctrl.h"
 
 &pinctrl_fsys0 {
 	gpf0: gpf0-gpio-bank {
@@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank {
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	ufs_rst_n: ufs-rst-n-pins {
+		samsung,pins = "gpf5-0";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+	};
+
+	ufs_refclk_out: ufs-refclk-out-pins {
+		samsung,pins = "gpf5-1";
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+	};
 };
 
 &pinctrl_peric {
@@ -223,107 +237,107 @@ gpg7: gpg7-gpio-bank {
 
 	pwm0_out: pwm0-out-pins {
 		samsung,pins = "gpb6-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV2>;
 	};
 
 	pwm1_out: pwm1-out-pins {
 		samsung,pins = "gpb6-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV2>;
 	};
 
 	hs_i2c0_bus: hs-i2c0-bus-pins {
 		samsung,pins = "gpb0-0", "gpb0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c1_bus: hs-i2c1-bus-pins {
 		samsung,pins = "gpb0-2", "gpb0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c2_bus: hs-i2c2-bus-pins {
 		samsung,pins = "gpb0-4", "gpb0-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c3_bus: hs-i2c3-bus-pins {
 		samsung,pins = "gpb0-6", "gpb0-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c4_bus: hs-i2c4-bus-pins {
 		samsung,pins = "gpb1-0", "gpb1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c5_bus: hs-i2c5-bus-pins {
 		samsung,pins = "gpb1-2", "gpb1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c6_bus: hs-i2c6-bus-pins {
 		samsung,pins = "gpb1-4", "gpb1-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	hs_i2c7_bus: hs-i2c7-bus-pins {
 		samsung,pins = "gpb1-6", "gpb1-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	uart0_data: uart0-data-pins {
 		samsung,pins = "gpb7-0", "gpb7-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	uart1_data: uart1-data-pins {
 		samsung,pins = "gpb7-4", "gpb7-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	spi0_bus: spi0-bus-pins {
 		samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	spi1_bus: spi1-bus-pins {
 		samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 
 	spi2_bus: spi2-bus-pins {
 		samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+		samsung,pin-function = <FSD_PIN_FUNC_2>;
+		samsung,pin-pud = <FSD_PIN_PULL_UP>;
+		samsung,pin-drv = <FSD_PIN_DRV_LV1>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h
new file mode 100644
index 000000000000..6ffbda362493
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Tesla FSD DTS pinctrl constants
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2022 Linaro Ltd
+ * Author: Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifndef __DTS_ARM64_TESLA_FSD_PINCTRL_H__
+#define __DTS_ARM64_TESLA_FSD_PINCTRL_H__
+
+#define FSD_PIN_PULL_NONE		0
+#define FSD_PIN_PULL_DOWN		1
+#define FSD_PIN_PULL_UP			3
+
+#define FSD_PIN_DRV_LV1			0
+#define FSD_PIN_DRV_LV2			2
+#define FSD_PIN_DRV_LV3			1
+#define FSD_PIN_DRV_LV4			3
+
+#define FSD_PIN_FUNC_INPUT		0
+#define FSD_PIN_FUNC_OUTPUT		1
+#define FSD_PIN_FUNC_2			2
+#define FSD_PIN_FUNC_3			3
+#define FSD_PIN_FUNC_4			4
+#define FSD_PIN_FUNC_5			5
+#define FSD_PIN_FUNC_6			6
+#define FSD_PIN_FUNC_EINT		0xf
+#define FSD_PIN_FUNC_F			FSD_PIN_FUNC_EINT
+
+#endif /* __DTS_ARM64_TESLA_FSD_PINCTRL_H__ */
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index af39655331de..f35bc5a288c2 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -93,6 +93,13 @@ cpucl0_0: cpu@0 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl0_1: cpu@1 {
@@ -102,6 +109,13 @@ cpucl0_1: cpu@1 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl0_2: cpu@2 {
@@ -111,6 +125,13 @@ cpucl0_2: cpu@2 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl0_3: cpu@3 {
@@ -119,6 +140,13 @@ cpucl0_3: cpu@3 {
 				reg = <0x0 0x003>;
 				enable-method = "psci";
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		/* Cluster 1 */
@@ -129,6 +157,13 @@ cpucl1_0: cpu@100 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl1_1: cpu@101 {
@@ -138,6 +173,13 @@ cpucl1_1: cpu@101 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl1_2: cpu@102 {
@@ -147,6 +189,13 @@ cpucl1_2: cpu@102 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl1_3: cpu@103 {
@@ -156,6 +205,13 @@ cpucl1_3: cpu@103 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		/* Cluster 2 */
@@ -166,6 +222,13 @@ cpucl2_0: cpu@200 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl2_1: cpu@201 {
@@ -175,6 +238,13 @@ cpucl2_1: cpu@201 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl2_2: cpu@202 {
@@ -184,6 +254,13 @@ cpucl2_2: cpu@202 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
 		};
 
 		cpucl2_3: cpu@203 {
@@ -193,6 +270,20 @@ cpucl2_3: cpu@203 {
 				enable-method = "psci";
 				clock-frequency = <2400000000>;
 				cpu-idle-states = <&CPU_SLEEP>;
+				i-cache-size = <0xc000>;
+				i-cache-line-size = <64>;
+				i-cache-sets = <256>;
+				d-cache-size = <0x8000>;
+				d-cache-line-size = <64>;
+				d-cache-sets = <256>;
+				next-level-cache = <&cpucl_l2>;
+		};
+
+		cpucl_l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x400000>;
+			cache-line-size = <64>;
+			cache-sets = <4096>;
 		};
 
 		idle-states {
@@ -740,6 +831,35 @@ timer@10040000 {
 			clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
 			clock-names = "fin_pll", "mct";
 		};
+
+		ufs: ufs@15120000 {
+			compatible = "tesla,fsd-ufs";
+			reg = <0x0 0x15120000 0x0 0x200>,  /* 0: HCI standard */
+			      <0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
+			      <0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
+			      <0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
+				 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+			phys = <&ufs_phy>;
+			phy-names = "ufs-phy";
+			status = "disabled";
+		};
+
+		ufs_phy: ufs-phy@15124000 {
+			compatible = "tesla,fsd-ufs-phy";
+			reg = <0x0 0x15124000 0x0 0x800>;
+			reg-names = "phy-pma";
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			#phy-cells = <0>;
+			clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
+			clock-names = "ref_clk";
+		};
 	};
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index d08abad0bcf4..df3b9883e887 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -144,8 +144,8 @@ dmsc: system-controller@44043000 {
 		compatible = "ti,k2g-sci";
 		ti,host-id = <12>;
 		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 12>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 12>,
+			 <&secure_proxy_main 13>;
 		reg-names = "debug_messages";
 		reg = <0x00 0x44043000 0x00 0xfe0>;
 
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 39fb1d763037..d0c3128fa036 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -13,7 +13,7 @@
 #include "k3-am625.dtsi"
 
 / {
-	compatible =  "ti,am625-sk", "ti,am625";
+	compatible = "ti,am625-sk", "ti,am625";
 	model = "Texas Instruments AM625 SK";
 
 	aliases {
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index f64b368c6c37..ada00575f0f2 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -174,7 +174,7 @@ dmsc: system-controller@44043000 {
 		compatible = "ti,k2g-sci";
 		ti,host-id = <12>;
 		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 12>,
+		mboxes = <&secure_proxy_main 12>,
 			<&secure_proxy_main 13>;
 		reg-names = "debug_messages";
 		reg = <0x00 0x44043000 0x00 0xfe0>;
@@ -456,13 +456,11 @@ sdhci0: mmc@fa10000 {
 		clock-names = "clk_ahb", "clk_xin";
 		mmc-ddr-1_8v;
 		mmc-hs200-1_8v;
-		mmc-hs400-1_8v;
 		ti,trm-icp = <0x2>;
 		ti,otap-del-sel-legacy = <0x0>;
 		ti,otap-del-sel-mmc-hs = <0x0>;
 		ti,otap-del-sel-ddr52 = <0x6>;
 		ti,otap-del-sel-hs200 = <0x7>;
-		ti,otap-del-sel-hs400 = <0x4>;
 	};
 
 	sdhci1: mmc@fa00000 {
@@ -1303,7 +1301,7 @@ main_mcan1: can@20711000 {
 		      <0x00 0x20718000 0x00 0x8000>;
 		reg-names = "m_can", "message_ram";
 		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
-		clocks =  <&k3_clks 99 5>, <&k3_clks 99 0>;
+		clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
 		clock-names = "hclk", "cclk";
 		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 8e7893e58b03..ad150c704623 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -13,7 +13,7 @@
 #include "k3-am642.dtsi"
 
 / {
-	compatible =  "ti,am642-evm", "ti,am642";
+	compatible = "ti,am642-evm", "ti,am642";
 	model = "Texas Instruments AM642 EVM";
 
 	chosen {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 59f506cbd275..64eed5456721 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -12,7 +12,7 @@
 #include "k3-am642.dtsi"
 
 / {
-	compatible =  "ti,am642-sk", "ti,am642";
+	compatible = "ti,am642-sk", "ti,am642";
 	model = "Texas Instruments AM642 SK";
 
 	chosen {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 6e41f2fa044a..32b797237581 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -425,7 +425,7 @@ &mcu_i2c0 {
 
 	psu: regulator@60 {
 		compatible = "ti,tps62363";
-		reg =  <0x60>;
+		reg = <0x60>;
 		regulator-name = "tps62363-vout";
 		regulator-min-microvolt = <500000>;
 		regulator-max-microvolt = <1500000>;
@@ -574,7 +574,7 @@ &mcu_spi0 {
 	pinctrl-0 = <&mcu_spi0_pins_default>;
 
 	#address-cells = <1>;
-	#size-cells= <0>;
+	#size-cells = <0>;
 	ti,pindir-d0-out-d1-in;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..8919fede3cd7 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -690,7 +690,7 @@ main_gpio1: gpio@601000 {
 
 	pcie0_rc: pcie@5500000 {
 		compatible = "ti,am654-pcie-rc";
-		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+		reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 		reg-names = "app", "dbics", "config", "atu";
 		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 		#address-cells = <3>;
@@ -710,7 +710,7 @@ pcie0_rc: pcie@5500000 {
 
 	pcie0_ep: pcie-ep@5500000 {
 		compatible = "ti,am654-pcie-ep";
-		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
+		reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 		reg-names = "app", "dbics", "addr_space", "atu";
 		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 		ti,syscon-pcie-mode = <&pcie0_mode>;
@@ -723,7 +723,7 @@ pcie0_ep: pcie-ep@5500000 {
 
 	pcie1_rc: pcie@5600000 {
 		compatible = "ti,am654-pcie-rc";
-		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+		reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 		reg-names = "app", "dbics", "config", "atu";
 		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 		#address-cells = <3>;
@@ -743,7 +743,7 @@ pcie1_rc: pcie@5600000 {
 
 	pcie1_ep: pcie-ep@5600000 {
 		compatible = "ti,am654-pcie-ep";
-		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
+		reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 		reg-names = "app", "dbics", "addr_space", "atu";
 		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 		ti,syscon-pcie-mode = <&pcie1_mode>;
@@ -843,9 +843,9 @@ dss: dss@4a00000 {
 
 		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 
-		clocks =	<&k3_clks 67 1>,
-				<&k3_clks 216 1>,
-				<&k3_clks 67 2>;
+		clocks = <&k3_clks 67 1>,
+			 <&k3_clks 216 1>,
+			 <&k3_clks 67 2>;
 		clock-names = "fck", "vp1", "vp2";
 
 		/*
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index 9c69d0917f69..fa11d7142006 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -12,8 +12,8 @@ dmsc: system-controller@44083000 {
 
 		mbox-names = "rx", "tx";
 
-		mboxes= <&secure_proxy_main 11>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 11>,
+			 <&secure_proxy_main 13>;
 
 		reg-names = "debug_messages";
 		reg = <0x44083000 0x1000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 57497cb1ed68..5850582dd4ed 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -10,7 +10,7 @@
 #include <dt-bindings/net/ti-dp83867.h>
 
 / {
-	compatible =  "ti,am654-evm", "ti,am654";
+	compatible = "ti,am654-evm", "ti,am654";
 	model = "Texas Instruments AM654 Base Board";
 
 	chosen {
@@ -73,13 +73,13 @@ gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&push_button_pins_default>;
 
-		sw5 {
+		switch-5 {
 			label = "GPIO Key USER1";
 			linux,code = <BTN_0>;
 			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
 		};
 
-		sw6 {
+		switch-6 {
 			label = "GPIO Key USER2";
 			linux,code = <BTN_1>;
 			gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
@@ -330,7 +330,7 @@ &main_spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_spi0_pins_default>;
 	#address-cells = <1>;
-	#size-cells= <0>;
+	#size-cells = <0>;
 	ti,pindir-d0-out-d1-in;
 
 	flash@0 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 1044ec6c4b0d..ff13bbeed30c 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@ dmsc: system-controller@44083000 {
 
 		mbox-names = "rx", "tx";
 
-		mboxes= <&secure_proxy_main 11>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 11>,
+			 <&secure_proxy_main 13>;
 
 		reg-names = "debug_messages";
 		reg = <0x00 0x44083000 0x00 0x1000>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 2bc26a296496..b1691ac3442d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -26,13 +26,13 @@ gpio_keys: gpio-keys {
 		pinctrl-names = "default";
 		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
 
-		sw10: sw10 {
+		sw10: switch-10 {
 			label = "GPIO Key USER1";
 			linux,code = <BTN_0>;
 			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
-		sw11: sw11 {
+		sw11: switch-11 {
 			label = "GPIO Key USER2";
 			linux,code = <BTN_1>;
 			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index b4972dfb7da8..df08724bbf1c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@ dmsc: system-controller@44083000 {
 
 		mbox-names = "rx", "tx";
 
-		mboxes= <&secure_proxy_main 11>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 11>,
+			 <&secure_proxy_main 13>;
 
 		reg-names = "debug_messages";
 		reg = <0x00 0x44083000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index be7f39299894..34e7d577ae13 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -33,7 +33,7 @@ gic500: interrupt-controller@1800000 {
 		ranges;
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
+		reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
 		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
 		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
 		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
@@ -320,7 +320,7 @@ main_sdhci0: mmc@4f80000 {
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
-		clock-names =  "clk_ahb", "clk_xin";
+		clock-names = "clk_ahb", "clk_xin";
 		assigned-clocks = <&k3_clks 98 1>;
 		assigned-clock-parents = <&k3_clks 98 2>;
 		bus-width = <8>;
@@ -347,7 +347,7 @@ main_sdhci1: mmc@4fb0000 {
 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
-		clock-names =  "clk_ahb", "clk_xin";
+		clock-names = "clk_ahb", "clk_xin";
 		assigned-clocks = <&k3_clks 99 1>;
 		assigned-clock-parents = <&k3_clks 99 2>;
 		bus-width = <4>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 6c5c02edb375..4d1bfabd1313 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -12,8 +12,8 @@ sms: system-controller@44083000 {
 
 		mbox-names = "rx", "tx";
 
-		mboxes= <&secure_proxy_main 11>,
-			<&secure_proxy_main 13>;
+		mboxes = <&secure_proxy_main 11>,
+			 <&secure_proxy_main 13>;
 
 		reg-names = "debug_messages";
 		reg = <0x00 0x44083000 0x00 0x1000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 8493dd7d5f1f..e172fa05c9a0 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -239,6 +239,10 @@ &lpd_watchdog {
 	clocks = <&zynqmp_clk LPD_WDT>;
 };
 
+&xilinx_ams {
+	clocks = <&zynqmp_clk AMS_REF>;
+};
+
 &zynqmp_dpdma {
 	clocks = <&zynqmp_clk DPDMA_REF>;
 };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
index 550b389153e6..bb2602dd2805 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
@@ -285,5 +285,5 @@ &gpio {
 			  "", "", "", "", "", /* 155 - 159 */
 			  "", "", "", "", "", /* 160 - 164 */
 			  "", "", "", "", "", /* 165 - 169 */
-			  "", "", "", ""; /* 170 - 174 */
+			  "", "", "", ""; /* 170 - 173 */
 };
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index c715a18368c2..a549265e55f6 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -874,6 +874,32 @@ lpd_watchdog: watchdog@ff150000 {
 			timeout-sec = <10>;
 		};
 
+		xilinx_ams: ams@ffa50000 {
+			compatible = "xlnx,zynqmp-ams";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 56 4>;
+			reg = <0x0 0xffa50000 0x0 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#io-channel-cells = <1>;
+			ranges = <0 0 0xffa50800 0x800>;
+
+			ams_ps: ams_ps@0 {
+				compatible = "xlnx,zynqmp-ams-ps";
+				status = "disabled";
+				reg = <0x0 0x400>;
+			};
+
+			ams_pl: ams_pl@400 {
+				compatible = "xlnx,zynqmp-ams-pl";
+				status = "disabled";
+				reg = <0x400 0x400>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		zynqmp_dpdma: dma-controller@fd4c0000 {
 			compatible = "xlnx,zynqmp-dpdma";
 			status = "disabled";
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d1105343bc2..55811436adb8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -36,6 +36,7 @@ CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM4908=y
+CONFIG_ARCH_BCMBCA=y
 CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_BRCMSTB=y
@@ -527,6 +528,7 @@ CONFIG_PINCTRL_IMX8QM=y
 CONFIG_PINCTRL_IMX8QXP=y
 CONFIG_PINCTRL_IMX8DXL=y
 CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_PINCTRL_IMX93=y
 CONFIG_PINCTRL_MSM=y
 CONFIG_PINCTRL_IPQ8074=y
 CONFIG_PINCTRL_IPQ6018=y
@@ -754,6 +756,7 @@ CONFIG_DRM_CDNS_MHDP8546=m
 CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
 CONFIG_DRM_DW_HDMI_CEC=m
 CONFIG_DRM_IMX_DCSS=m
+CONFIG_DRM_V3D=m
 CONFIG_DRM_VC4=m
 CONFIG_DRM_ETNAVIV=m
 CONFIG_DRM_HISI_HIBMC=m
@@ -808,6 +811,7 @@ CONFIG_SND_SOC_TEGRA=m
 CONFIG_SND_SOC_TEGRA210_AHUB=m
 CONFIG_SND_SOC_TEGRA210_DMIC=m
 CONFIG_SND_SOC_TEGRA210_I2S=m
+CONFIG_SND_SOC_TEGRA210_OPE=m
 CONFIG_SND_SOC_TEGRA186_ASRC=m
 CONFIG_SND_SOC_TEGRA186_DSPK=m
 CONFIG_SND_SOC_TEGRA210_ADMAIF=m
@@ -1029,6 +1033,7 @@ CONFIG_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MQ=y
 CONFIG_CLK_IMX8QXP=y
 CONFIG_CLK_IMX8ULP=y
+CONFIG_CLK_IMX93=y
 CONFIG_TI_SCI_CLK=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_QCOM_A53PLL=y
@@ -1119,6 +1124,7 @@ CONFIG_ARCH_R8A779F0=y
 CONFIG_ARCH_R8A77980=y
 CONFIG_ARCH_R8A77970=y
 CONFIG_ARCH_R8A779A0=y
+CONFIG_ARCH_R8A779G0=y
 CONFIG_ARCH_R8A774C0=y
 CONFIG_ARCH_R8A774E1=y
 CONFIG_ARCH_R8A774A1=y
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index ac85682c013c..4391a463abd7 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -72,6 +72,11 @@ config CRYPTO_GHASH_ARM64_CE
 	select CRYPTO_GF128MUL
 	select CRYPTO_LIB_AES
 
+config CRYPTO_POLYVAL_ARM64_CE
+	tristate "POLYVAL using ARMv8 Crypto Extensions (for HCTR2)"
+	depends on KERNEL_MODE_NEON
+	select CRYPTO_POLYVAL
+
 config CRYPTO_CRCT10DIF_ARM64_CE
 	tristate "CRCT10DIF digest algorithm using PMULL instructions"
 	depends on KERNEL_MODE_NEON && CRC_T10DIF
@@ -96,13 +101,13 @@ config CRYPTO_AES_ARM64_CE_CCM
 	select CRYPTO_LIB_AES
 
 config CRYPTO_AES_ARM64_CE_BLK
-	tristate "AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions"
+	tristate "AES in ECB/CBC/CTR/XTS/XCTR modes using ARMv8 Crypto Extensions"
 	depends on KERNEL_MODE_NEON
 	select CRYPTO_SKCIPHER
 	select CRYPTO_AES_ARM64_CE
 
 config CRYPTO_AES_ARM64_NEON_BLK
-	tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
+	tristate "AES in ECB/CBC/CTR/XTS/XCTR modes using NEON instructions"
 	depends on KERNEL_MODE_NEON
 	select CRYPTO_SKCIPHER
 	select CRYPTO_LIB_AES
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index bea8995133b1..24bb0c4610de 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -32,6 +32,9 @@ sm4-neon-y := sm4-neon-glue.o sm4-neon-core.o
 obj-$(CONFIG_CRYPTO_GHASH_ARM64_CE) += ghash-ce.o
 ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o
 
+obj-$(CONFIG_CRYPTO_POLYVAL_ARM64_CE) += polyval-ce.o
+polyval-ce-y := polyval-ce-glue.o polyval-ce-core.o
+
 obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM64_CE) += crct10dif-ce.o
 crct10dif-ce-y := crct10dif-ce-core.o crct10dif-ce-glue.o
 
diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c
index 561dd2332571..162787c7aa86 100644
--- a/arch/arm64/crypto/aes-glue.c
+++ b/arch/arm64/crypto/aes-glue.c
@@ -34,10 +34,11 @@
 #define aes_essiv_cbc_encrypt	ce_aes_essiv_cbc_encrypt
 #define aes_essiv_cbc_decrypt	ce_aes_essiv_cbc_decrypt
 #define aes_ctr_encrypt		ce_aes_ctr_encrypt
+#define aes_xctr_encrypt	ce_aes_xctr_encrypt
 #define aes_xts_encrypt		ce_aes_xts_encrypt
 #define aes_xts_decrypt		ce_aes_xts_decrypt
 #define aes_mac_update		ce_aes_mac_update
-MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions");
+MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS/XCTR using ARMv8 Crypto Extensions");
 #else
 #define MODE			"neon"
 #define PRIO			200
@@ -50,16 +51,18 @@ MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions");
 #define aes_essiv_cbc_encrypt	neon_aes_essiv_cbc_encrypt
 #define aes_essiv_cbc_decrypt	neon_aes_essiv_cbc_decrypt
 #define aes_ctr_encrypt		neon_aes_ctr_encrypt
+#define aes_xctr_encrypt	neon_aes_xctr_encrypt
 #define aes_xts_encrypt		neon_aes_xts_encrypt
 #define aes_xts_decrypt		neon_aes_xts_decrypt
 #define aes_mac_update		neon_aes_mac_update
-MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 NEON");
+MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS/XCTR using ARMv8 NEON");
 #endif
 #if defined(USE_V8_CRYPTO_EXTENSIONS) || !IS_ENABLED(CONFIG_CRYPTO_AES_ARM64_BS)
 MODULE_ALIAS_CRYPTO("ecb(aes)");
 MODULE_ALIAS_CRYPTO("cbc(aes)");
 MODULE_ALIAS_CRYPTO("ctr(aes)");
 MODULE_ALIAS_CRYPTO("xts(aes)");
+MODULE_ALIAS_CRYPTO("xctr(aes)");
 #endif
 MODULE_ALIAS_CRYPTO("cts(cbc(aes))");
 MODULE_ALIAS_CRYPTO("essiv(cbc(aes),sha256)");
@@ -89,6 +92,9 @@ asmlinkage void aes_cbc_cts_decrypt(u8 out[], u8 const in[], u32 const rk[],
 asmlinkage void aes_ctr_encrypt(u8 out[], u8 const in[], u32 const rk[],
 				int rounds, int bytes, u8 ctr[]);
 
+asmlinkage void aes_xctr_encrypt(u8 out[], u8 const in[], u32 const rk[],
+				 int rounds, int bytes, u8 ctr[], int byte_ctr);
+
 asmlinkage void aes_xts_encrypt(u8 out[], u8 const in[], u32 const rk1[],
 				int rounds, int bytes, u32 const rk2[], u8 iv[],
 				int first);
@@ -442,6 +448,52 @@ static int __maybe_unused essiv_cbc_decrypt(struct skcipher_request *req)
 	return err ?: cbc_decrypt_walk(req, &walk);
 }
 
+static int __maybe_unused xctr_encrypt(struct skcipher_request *req)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
+	int err, rounds = 6 + ctx->key_length / 4;
+	struct skcipher_walk walk;
+	unsigned int byte_ctr = 0;
+
+	err = skcipher_walk_virt(&walk, req, false);
+
+	while (walk.nbytes > 0) {
+		const u8 *src = walk.src.virt.addr;
+		unsigned int nbytes = walk.nbytes;
+		u8 *dst = walk.dst.virt.addr;
+		u8 buf[AES_BLOCK_SIZE];
+
+		/*
+		 * If given less than 16 bytes, we must copy the partial block
+		 * into a temporary buffer of 16 bytes to avoid out of bounds
+		 * reads and writes.  Furthermore, this code is somewhat unusual
+		 * in that it expects the end of the data to be at the end of
+		 * the temporary buffer, rather than the start of the data at
+		 * the start of the temporary buffer.
+		 */
+		if (unlikely(nbytes < AES_BLOCK_SIZE))
+			src = dst = memcpy(buf + sizeof(buf) - nbytes,
+					   src, nbytes);
+		else if (nbytes < walk.total)
+			nbytes &= ~(AES_BLOCK_SIZE - 1);
+
+		kernel_neon_begin();
+		aes_xctr_encrypt(dst, src, ctx->key_enc, rounds, nbytes,
+						 walk.iv, byte_ctr);
+		kernel_neon_end();
+
+		if (unlikely(nbytes < AES_BLOCK_SIZE))
+			memcpy(walk.dst.virt.addr,
+			       buf + sizeof(buf) - nbytes, nbytes);
+		byte_ctr += nbytes;
+
+		err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
+	}
+
+	return err;
+}
+
 static int __maybe_unused ctr_encrypt(struct skcipher_request *req)
 {
 	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
@@ -457,6 +509,14 @@ static int __maybe_unused ctr_encrypt(struct skcipher_request *req)
 		u8 *dst = walk.dst.virt.addr;
 		u8 buf[AES_BLOCK_SIZE];
 
+		/*
+		 * If given less than 16 bytes, we must copy the partial block
+		 * into a temporary buffer of 16 bytes to avoid out of bounds
+		 * reads and writes.  Furthermore, this code is somewhat unusual
+		 * in that it expects the end of the data to be at the end of
+		 * the temporary buffer, rather than the start of the data at
+		 * the start of the temporary buffer.
+		 */
 		if (unlikely(nbytes < AES_BLOCK_SIZE))
 			src = dst = memcpy(buf + sizeof(buf) - nbytes,
 					   src, nbytes);
@@ -669,6 +729,22 @@ static struct skcipher_alg aes_algs[] = { {
 	.setkey		= skcipher_aes_setkey,
 	.encrypt	= ctr_encrypt,
 	.decrypt	= ctr_encrypt,
+}, {
+	.base = {
+		.cra_name		= "xctr(aes)",
+		.cra_driver_name	= "xctr-aes-" MODE,
+		.cra_priority		= PRIO,
+		.cra_blocksize		= 1,
+		.cra_ctxsize		= sizeof(struct crypto_aes_ctx),
+		.cra_module		= THIS_MODULE,
+	},
+	.min_keysize	= AES_MIN_KEY_SIZE,
+	.max_keysize	= AES_MAX_KEY_SIZE,
+	.ivsize		= AES_BLOCK_SIZE,
+	.chunksize	= AES_BLOCK_SIZE,
+	.setkey		= skcipher_aes_setkey,
+	.encrypt	= xctr_encrypt,
+	.decrypt	= xctr_encrypt,
 }, {
 	.base = {
 		.cra_name		= "xts(aes)",
diff --git a/arch/arm64/crypto/aes-modes.S b/arch/arm64/crypto/aes-modes.S
index dc35eb0245c5..5abc834271f4 100644
--- a/arch/arm64/crypto/aes-modes.S
+++ b/arch/arm64/crypto/aes-modes.S
@@ -318,127 +318,211 @@ AES_FUNC_END(aes_cbc_cts_decrypt)
 	.byte		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 	.previous
 
-
 	/*
-	 * aes_ctr_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
-	 *		   int bytes, u8 ctr[])
+	 * This macro generates the code for CTR and XCTR mode.
 	 */
+.macro ctr_encrypt xctr
+	// Arguments
+	OUT		.req x0
+	IN		.req x1
+	KEY		.req x2
+	ROUNDS_W	.req w3
+	BYTES_W		.req w4
+	IV		.req x5
+	BYTE_CTR_W 	.req w6		// XCTR only
+	// Intermediate values
+	CTR_W		.req w11	// XCTR only
+	CTR		.req x11	// XCTR only
+	IV_PART		.req x12
+	BLOCKS		.req x13
+	BLOCKS_W	.req w13
 
-AES_FUNC_START(aes_ctr_encrypt)
 	stp		x29, x30, [sp, #-16]!
 	mov		x29, sp
 
-	enc_prepare	w3, x2, x12
-	ld1		{vctr.16b}, [x5]
+	enc_prepare	ROUNDS_W, KEY, IV_PART
+	ld1		{vctr.16b}, [IV]
 
-	umov		x12, vctr.d[1]		/* keep swabbed ctr in reg */
-	rev		x12, x12
-
-.LctrloopNx:
-	add		w7, w4, #15
-	sub		w4, w4, #MAX_STRIDE << 4
-	lsr		w7, w7, #4
+	/*
+	 * Keep 64 bits of the IV in a register.  For CTR mode this lets us
+	 * easily increment the IV.  For XCTR mode this lets us efficiently XOR
+	 * the 64-bit counter with the IV.
+	 */
+	.if \xctr
+		umov		IV_PART, vctr.d[0]
+		lsr		CTR_W, BYTE_CTR_W, #4
+	.else
+		umov		IV_PART, vctr.d[1]
+		rev		IV_PART, IV_PART
+	.endif
+
+.LctrloopNx\xctr:
+	add		BLOCKS_W, BYTES_W, #15
+	sub		BYTES_W, BYTES_W, #MAX_STRIDE << 4
+	lsr		BLOCKS_W, BLOCKS_W, #4
 	mov		w8, #MAX_STRIDE
-	cmp		w7, w8
-	csel		w7, w7, w8, lt
-	adds		x12, x12, x7
+	cmp		BLOCKS_W, w8
+	csel		BLOCKS_W, BLOCKS_W, w8, lt
 
+	/*
+	 * Set up the counter values in v0-v{MAX_STRIDE-1}.
+	 *
+	 * If we are encrypting less than MAX_STRIDE blocks, the tail block
+	 * handling code expects the last keystream block to be in
+	 * v{MAX_STRIDE-1}.  For example: if encrypting two blocks with
+	 * MAX_STRIDE=5, then v3 and v4 should have the next two counter blocks.
+	 */
+	.if \xctr
+		add		CTR, CTR, BLOCKS
+	.else
+		adds		IV_PART, IV_PART, BLOCKS
+	.endif
 	mov		v0.16b, vctr.16b
 	mov		v1.16b, vctr.16b
 	mov		v2.16b, vctr.16b
 	mov		v3.16b, vctr.16b
 ST5(	mov		v4.16b, vctr.16b		)
-	bcs		0f
-
-	.subsection	1
-	/* apply carry to outgoing counter */
-0:	umov		x8, vctr.d[0]
-	rev		x8, x8
-	add		x8, x8, #1
-	rev		x8, x8
-	ins		vctr.d[0], x8
-
-	/* apply carry to N counter blocks for N := x12 */
-	cbz		x12, 2f
-	adr		x16, 1f
-	sub		x16, x16, x12, lsl #3
-	br		x16
-	bti		c
-	mov		v0.d[0], vctr.d[0]
-	bti		c
-	mov		v1.d[0], vctr.d[0]
-	bti		c
-	mov		v2.d[0], vctr.d[0]
-	bti		c
-	mov		v3.d[0], vctr.d[0]
-ST5(	bti		c				)
-ST5(	mov		v4.d[0], vctr.d[0]		)
-1:	b		2f
-	.previous
+	.if \xctr
+		sub		x6, CTR, #MAX_STRIDE - 1
+		sub		x7, CTR, #MAX_STRIDE - 2
+		sub		x8, CTR, #MAX_STRIDE - 3
+		sub		x9, CTR, #MAX_STRIDE - 4
+ST5(		sub		x10, CTR, #MAX_STRIDE - 5	)
+		eor		x6, x6, IV_PART
+		eor		x7, x7, IV_PART
+		eor		x8, x8, IV_PART
+		eor		x9, x9, IV_PART
+ST5(		eor		x10, x10, IV_PART		)
+		mov		v0.d[0], x6
+		mov		v1.d[0], x7
+		mov		v2.d[0], x8
+		mov		v3.d[0], x9
+ST5(		mov		v4.d[0], x10			)
+	.else
+		bcs		0f
+		.subsection	1
+		/*
+		 * This subsection handles carries.
+		 *
+		 * Conditional branching here is allowed with respect to time
+		 * invariance since the branches are dependent on the IV instead
+		 * of the plaintext or key.  This code is rarely executed in
+		 * practice anyway.
+		 */
+
+		/* Apply carry to outgoing counter. */
+0:		umov		x8, vctr.d[0]
+		rev		x8, x8
+		add		x8, x8, #1
+		rev		x8, x8
+		ins		vctr.d[0], x8
+
+		/*
+		 * Apply carry to counter blocks if needed.
+		 *
+		 * Since the carry flag was set, we know 0 <= IV_PART <
+		 * MAX_STRIDE.  Using the value of IV_PART we can determine how
+		 * many counter blocks need to be updated.
+		 */
+		cbz		IV_PART, 2f
+		adr		x16, 1f
+		sub		x16, x16, IV_PART, lsl #3
+		br		x16
+		bti		c
+		mov		v0.d[0], vctr.d[0]
+		bti		c
+		mov		v1.d[0], vctr.d[0]
+		bti		c
+		mov		v2.d[0], vctr.d[0]
+		bti		c
+		mov		v3.d[0], vctr.d[0]
+ST5(		bti		c				)
+ST5(		mov		v4.d[0], vctr.d[0]		)
+1:		b		2f
+		.previous
+
+2:		rev		x7, IV_PART
+		ins		vctr.d[1], x7
+		sub		x7, IV_PART, #MAX_STRIDE - 1
+		sub		x8, IV_PART, #MAX_STRIDE - 2
+		sub		x9, IV_PART, #MAX_STRIDE - 3
+		rev		x7, x7
+		rev		x8, x8
+		mov		v1.d[1], x7
+		rev		x9, x9
+ST5(		sub		x10, IV_PART, #MAX_STRIDE - 4	)
+		mov		v2.d[1], x8
+ST5(		rev		x10, x10			)
+		mov		v3.d[1], x9
+ST5(		mov		v4.d[1], x10			)
+	.endif
 
-2:	rev		x7, x12
-	ins		vctr.d[1], x7
-	sub		x7, x12, #MAX_STRIDE - 1
-	sub		x8, x12, #MAX_STRIDE - 2
-	sub		x9, x12, #MAX_STRIDE - 3
-	rev		x7, x7
-	rev		x8, x8
-	mov		v1.d[1], x7
-	rev		x9, x9
-ST5(	sub		x10, x12, #MAX_STRIDE - 4	)
-	mov		v2.d[1], x8
-ST5(	rev		x10, x10			)
-	mov		v3.d[1], x9
-ST5(	mov		v4.d[1], x10			)
-	tbnz		w4, #31, .Lctrtail
-	ld1		{v5.16b-v7.16b}, [x1], #48
+	/*
+	 * If there are at least MAX_STRIDE blocks left, XOR the data with
+	 * keystream and store.  Otherwise jump to tail handling.
+	 */
+	tbnz		BYTES_W, #31, .Lctrtail\xctr
+	ld1		{v5.16b-v7.16b}, [IN], #48
 ST4(	bl		aes_encrypt_block4x		)
 ST5(	bl		aes_encrypt_block5x		)
 	eor		v0.16b, v5.16b, v0.16b
-ST4(	ld1		{v5.16b}, [x1], #16		)
+ST4(	ld1		{v5.16b}, [IN], #16		)
 	eor		v1.16b, v6.16b, v1.16b
-ST5(	ld1		{v5.16b-v6.16b}, [x1], #32	)
+ST5(	ld1		{v5.16b-v6.16b}, [IN], #32	)
 	eor		v2.16b, v7.16b, v2.16b
 	eor		v3.16b, v5.16b, v3.16b
 ST5(	eor		v4.16b, v6.16b, v4.16b		)
-	st1		{v0.16b-v3.16b}, [x0], #64
-ST5(	st1		{v4.16b}, [x0], #16		)
-	cbz		w4, .Lctrout
-	b		.LctrloopNx
-
-.Lctrout:
-	st1		{vctr.16b}, [x5]	/* return next CTR value */
+	st1		{v0.16b-v3.16b}, [OUT], #64
+ST5(	st1		{v4.16b}, [OUT], #16		)
+	cbz		BYTES_W, .Lctrout\xctr
+	b		.LctrloopNx\xctr
+
+.Lctrout\xctr:
+	.if !\xctr
+		st1		{vctr.16b}, [IV] /* return next CTR value */
+	.endif
 	ldp		x29, x30, [sp], #16
 	ret
 
-.Lctrtail:
-	/* XOR up to MAX_STRIDE * 16 - 1 bytes of in/output with v0 ... v3/v4 */
+.Lctrtail\xctr:
+	/*
+	 * Handle up to MAX_STRIDE * 16 - 1 bytes of plaintext
+	 *
+	 * This code expects the last keystream block to be in v{MAX_STRIDE-1}.
+	 * For example: if encrypting two blocks with MAX_STRIDE=5, then v3 and
+	 * v4 should have the next two counter blocks.
+	 *
+	 * This allows us to store the ciphertext by writing to overlapping
+	 * regions of memory.  Any invalid ciphertext blocks get overwritten by
+	 * correctly computed blocks.  This approach greatly simplifies the
+	 * logic for storing the ciphertext.
+	 */
 	mov		x16, #16
-	ands		x6, x4, #0xf
-	csel		x13, x6, x16, ne
+	ands		w7, BYTES_W, #0xf
+	csel		x13, x7, x16, ne
 
-ST5(	cmp		w4, #64 - (MAX_STRIDE << 4)	)
+ST5(	cmp		BYTES_W, #64 - (MAX_STRIDE << 4))
 ST5(	csel		x14, x16, xzr, gt		)
-	cmp		w4, #48 - (MAX_STRIDE << 4)
+	cmp		BYTES_W, #48 - (MAX_STRIDE << 4)
 	csel		x15, x16, xzr, gt
-	cmp		w4, #32 - (MAX_STRIDE << 4)
+	cmp		BYTES_W, #32 - (MAX_STRIDE << 4)
 	csel		x16, x16, xzr, gt
-	cmp		w4, #16 - (MAX_STRIDE << 4)
+	cmp		BYTES_W, #16 - (MAX_STRIDE << 4)
 
-	adr_l		x12, .Lcts_permute_table
-	add		x12, x12, x13
-	ble		.Lctrtail1x
+	adr_l		x9, .Lcts_permute_table
+	add		x9, x9, x13
+	ble		.Lctrtail1x\xctr
 
-ST5(	ld1		{v5.16b}, [x1], x14		)
-	ld1		{v6.16b}, [x1], x15
-	ld1		{v7.16b}, [x1], x16
+ST5(	ld1		{v5.16b}, [IN], x14		)
+	ld1		{v6.16b}, [IN], x15
+	ld1		{v7.16b}, [IN], x16
 
 ST4(	bl		aes_encrypt_block4x		)
 ST5(	bl		aes_encrypt_block5x		)
 
-	ld1		{v8.16b}, [x1], x13
-	ld1		{v9.16b}, [x1]
-	ld1		{v10.16b}, [x12]
+	ld1		{v8.16b}, [IN], x13
+	ld1		{v9.16b}, [IN]
+	ld1		{v10.16b}, [x9]
 
 ST4(	eor		v6.16b, v6.16b, v0.16b		)
 ST4(	eor		v7.16b, v7.16b, v1.16b		)
@@ -453,32 +537,91 @@ ST5(	eor		v7.16b, v7.16b, v2.16b		)
 ST5(	eor		v8.16b, v8.16b, v3.16b		)
 ST5(	eor		v9.16b, v9.16b, v4.16b		)
 
-ST5(	st1		{v5.16b}, [x0], x14		)
-	st1		{v6.16b}, [x0], x15
-	st1		{v7.16b}, [x0], x16
-	add		x13, x13, x0
+ST5(	st1		{v5.16b}, [OUT], x14		)
+	st1		{v6.16b}, [OUT], x15
+	st1		{v7.16b}, [OUT], x16
+	add		x13, x13, OUT
 	st1		{v9.16b}, [x13]		// overlapping stores
-	st1		{v8.16b}, [x0]
-	b		.Lctrout
-
-.Lctrtail1x:
-	sub		x7, x6, #16
-	csel		x6, x6, x7, eq
-	add		x1, x1, x6
-	add		x0, x0, x6
-	ld1		{v5.16b}, [x1]
-	ld1		{v6.16b}, [x0]
+	st1		{v8.16b}, [OUT]
+	b		.Lctrout\xctr
+
+.Lctrtail1x\xctr:
+	/*
+	 * Handle <= 16 bytes of plaintext
+	 *
+	 * This code always reads and writes 16 bytes.  To avoid out of bounds
+	 * accesses, XCTR and CTR modes must use a temporary buffer when
+	 * encrypting/decrypting less than 16 bytes.
+	 *
+	 * This code is unusual in that it loads the input and stores the output
+	 * relative to the end of the buffers rather than relative to the start.
+	 * This causes unusual behaviour when encrypting/decrypting less than 16
+	 * bytes; the end of the data is expected to be at the end of the
+	 * temporary buffer rather than the start of the data being at the start
+	 * of the temporary buffer.
+	 */
+	sub		x8, x7, #16
+	csel		x7, x7, x8, eq
+	add		IN, IN, x7
+	add		OUT, OUT, x7
+	ld1		{v5.16b}, [IN]
+	ld1		{v6.16b}, [OUT]
 ST5(	mov		v3.16b, v4.16b			)
-	encrypt_block	v3, w3, x2, x8, w7
-	ld1		{v10.16b-v11.16b}, [x12]
+	encrypt_block	v3, ROUNDS_W, KEY, x8, w7
+	ld1		{v10.16b-v11.16b}, [x9]
 	tbl		v3.16b, {v3.16b}, v10.16b
 	sshr		v11.16b, v11.16b, #7
 	eor		v5.16b, v5.16b, v3.16b
 	bif		v5.16b, v6.16b, v11.16b
-	st1		{v5.16b}, [x0]
-	b		.Lctrout
+	st1		{v5.16b}, [OUT]
+	b		.Lctrout\xctr
+
+	// Arguments
+	.unreq OUT
+	.unreq IN
+	.unreq KEY
+	.unreq ROUNDS_W
+	.unreq BYTES_W
+	.unreq IV
+	.unreq BYTE_CTR_W	// XCTR only
+	// Intermediate values
+	.unreq CTR_W		// XCTR only
+	.unreq CTR		// XCTR only
+	.unreq IV_PART
+	.unreq BLOCKS
+	.unreq BLOCKS_W
+.endm
+
+	/*
+	 * aes_ctr_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
+	 *		   int bytes, u8 ctr[])
+	 *
+	 * The input and output buffers must always be at least 16 bytes even if
+	 * encrypting/decrypting less than 16 bytes.  Otherwise out of bounds
+	 * accesses will occur.  The data to be encrypted/decrypted is expected
+	 * to be at the end of this 16-byte temporary buffer rather than the
+	 * start.
+	 */
+
+AES_FUNC_START(aes_ctr_encrypt)
+	ctr_encrypt 0
 AES_FUNC_END(aes_ctr_encrypt)
 
+	/*
+	 * aes_xctr_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
+	 *		   int bytes, u8 const iv[], int byte_ctr)
+	 *
+	 * The input and output buffers must always be at least 16 bytes even if
+	 * encrypting/decrypting less than 16 bytes.  Otherwise out of bounds
+	 * accesses will occur.  The data to be encrypted/decrypted is expected
+	 * to be at the end of this 16-byte temporary buffer rather than the
+	 * start.
+	 */
+
+AES_FUNC_START(aes_xctr_encrypt)
+	ctr_encrypt 1
+AES_FUNC_END(aes_xctr_encrypt)
+
 
 	/*
 	 * aes_xts_encrypt(u8 out[], u8 const in[], u8 const rk1[], int rounds,
diff --git a/arch/arm64/crypto/polyval-ce-core.S b/arch/arm64/crypto/polyval-ce-core.S
new file mode 100644
index 000000000000..b5326540d2e3
--- /dev/null
+++ b/arch/arm64/crypto/polyval-ce-core.S
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Implementation of POLYVAL using ARMv8 Crypto Extensions.
+ *
+ * Copyright 2021 Google LLC
+ */
+/*
+ * This is an efficient implementation of POLYVAL using ARMv8 Crypto Extensions
+ * It works on 8 blocks at a time, by precomputing the first 8 keys powers h^8,
+ * ..., h^1 in the POLYVAL finite field. This precomputation allows us to split
+ * finite field multiplication into two steps.
+ *
+ * In the first step, we consider h^i, m_i as normal polynomials of degree less
+ * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
+ * is simply polynomial multiplication.
+ *
+ * In the second step, we compute the reduction of p(x) modulo the finite field
+ * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
+ *
+ * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
+ * multiplication is finite field multiplication. The advantage is that the
+ * two-step process  only requires 1 finite field reduction for every 8
+ * polynomial multiplications. Further parallelism is gained by interleaving the
+ * multiplications and polynomial reductions.
+ */
+
+#include <linux/linkage.h>
+#define STRIDE_BLOCKS 8
+
+KEY_POWERS	.req	x0
+MSG		.req	x1
+BLOCKS_LEFT	.req	x2
+ACCUMULATOR	.req	x3
+KEY_START	.req	x10
+EXTRA_BYTES	.req	x11
+TMP	.req	x13
+
+M0	.req	v0
+M1	.req	v1
+M2	.req	v2
+M3	.req	v3
+M4	.req	v4
+M5	.req	v5
+M6	.req	v6
+M7	.req	v7
+KEY8	.req	v8
+KEY7	.req	v9
+KEY6	.req	v10
+KEY5	.req	v11
+KEY4	.req	v12
+KEY3	.req	v13
+KEY2	.req	v14
+KEY1	.req	v15
+PL	.req	v16
+PH	.req	v17
+TMP_V	.req	v18
+LO	.req	v20
+MI	.req	v21
+HI	.req	v22
+SUM	.req	v23
+GSTAR	.req	v24
+
+	.text
+
+	.arch	armv8-a+crypto
+	.align	4
+
+.Lgstar:
+	.quad	0xc200000000000000, 0xc200000000000000
+
+/*
+ * Computes the product of two 128-bit polynomials in X and Y and XORs the
+ * components of the 256-bit product into LO, MI, HI.
+ *
+ * Given:
+ *  X = [X_1 : X_0]
+ *  Y = [Y_1 : Y_0]
+ *
+ * We compute:
+ *  LO += X_0 * Y_0
+ *  MI += (X_0 + X_1) * (Y_0 + Y_1)
+ *  HI += X_1 * Y_1
+ *
+ * Later, the 256-bit result can be extracted as:
+ *   [HI_1 : HI_0 + HI_1 + MI_1 + LO_1 : LO_1 + HI_0 + MI_0 + LO_0 : LO_0]
+ * This step is done when computing the polynomial reduction for efficiency
+ * reasons.
+ *
+ * Karatsuba multiplication is used instead of Schoolbook multiplication because
+ * it was found to be slightly faster on ARM64 CPUs.
+ *
+ */
+.macro karatsuba1 X Y
+	X .req \X
+	Y .req \Y
+	ext	v25.16b, X.16b, X.16b, #8
+	ext	v26.16b, Y.16b, Y.16b, #8
+	eor	v25.16b, v25.16b, X.16b
+	eor	v26.16b, v26.16b, Y.16b
+	pmull2	v28.1q, X.2d, Y.2d
+	pmull	v29.1q, X.1d, Y.1d
+	pmull	v27.1q, v25.1d, v26.1d
+	eor	HI.16b, HI.16b, v28.16b
+	eor	LO.16b, LO.16b, v29.16b
+	eor	MI.16b, MI.16b, v27.16b
+	.unreq X
+	.unreq Y
+.endm
+
+/*
+ * Same as karatsuba1, except overwrites HI, LO, MI rather than XORing into
+ * them.
+ */
+.macro karatsuba1_store X Y
+	X .req \X
+	Y .req \Y
+	ext	v25.16b, X.16b, X.16b, #8
+	ext	v26.16b, Y.16b, Y.16b, #8
+	eor	v25.16b, v25.16b, X.16b
+	eor	v26.16b, v26.16b, Y.16b
+	pmull2	HI.1q, X.2d, Y.2d
+	pmull	LO.1q, X.1d, Y.1d
+	pmull	MI.1q, v25.1d, v26.1d
+	.unreq X
+	.unreq Y
+.endm
+
+/*
+ * Computes the 256-bit polynomial represented by LO, HI, MI. Stores
+ * the result in PL, PH.
+ * [PH : PL] =
+ *   [HI_1 : HI_1 + HI_0 + MI_1 + LO_1 : HI_0 + MI_0 + LO_1 + LO_0 : LO_0]
+ */
+.macro karatsuba2
+	// v4 = [HI_1 + MI_1 : HI_0 + MI_0]
+	eor	v4.16b, HI.16b, MI.16b
+	// v4 = [HI_1 + MI_1 + LO_1 : HI_0 + MI_0 + LO_0]
+	eor	v4.16b, v4.16b, LO.16b
+	// v5 = [HI_0 : LO_1]
+	ext	v5.16b, LO.16b, HI.16b, #8
+	// v4 = [HI_1 + HI_0 + MI_1 + LO_1 : HI_0 + MI_0 + LO_1 + LO_0]
+	eor	v4.16b, v4.16b, v5.16b
+	// HI = [HI_0 : HI_1]
+	ext	HI.16b, HI.16b, HI.16b, #8
+	// LO = [LO_0 : LO_1]
+	ext	LO.16b, LO.16b, LO.16b, #8
+	// PH = [HI_1 : HI_1 + HI_0 + MI_1 + LO_1]
+	ext	PH.16b, v4.16b, HI.16b, #8
+	// PL = [HI_0 + MI_0 + LO_1 + LO_0 : LO_0]
+	ext	PL.16b, LO.16b, v4.16b, #8
+.endm
+
+/*
+ * Computes the 128-bit reduction of PH : PL. Stores the result in dest.
+ *
+ * This macro computes p(x) mod g(x) where p(x) is in montgomery form and g(x) =
+ * x^128 + x^127 + x^126 + x^121 + 1.
+ *
+ * We have a 256-bit polynomial PH : PL = P_3 : P_2 : P_1 : P_0 that is the
+ * product of two 128-bit polynomials in Montgomery form.  We need to reduce it
+ * mod g(x).  Also, since polynomials in Montgomery form have an "extra" factor
+ * of x^128, this product has two extra factors of x^128.  To get it back into
+ * Montgomery form, we need to remove one of these factors by dividing by x^128.
+ *
+ * To accomplish both of these goals, we add multiples of g(x) that cancel out
+ * the low 128 bits P_1 : P_0, leaving just the high 128 bits. Since the low
+ * bits are zero, the polynomial division by x^128 can be done by right
+ * shifting.
+ *
+ * Since the only nonzero term in the low 64 bits of g(x) is the constant term,
+ * the multiple of g(x) needed to cancel out P_0 is P_0 * g(x).  The CPU can
+ * only do 64x64 bit multiplications, so split P_0 * g(x) into x^128 * P_0 +
+ * x^64 * g*(x) * P_0 + P_0, where g*(x) is bits 64-127 of g(x).  Adding this to
+ * the original polynomial gives P_3 : P_2 + P_0 + T_1 : P_1 + T_0 : 0, where T
+ * = T_1 : T_0 = g*(x) * P_0.  Thus, bits 0-63 got "folded" into bits 64-191.
+ *
+ * Repeating this same process on the next 64 bits "folds" bits 64-127 into bits
+ * 128-255, giving the answer in bits 128-255. This time, we need to cancel P_1
+ * + T_0 in bits 64-127. The multiple of g(x) required is (P_1 + T_0) * g(x) *
+ * x^64. Adding this to our previous computation gives P_3 + P_1 + T_0 + V_1 :
+ * P_2 + P_0 + T_1 + V_0 : 0 : 0, where V = V_1 : V_0 = g*(x) * (P_1 + T_0).
+ *
+ * So our final computation is:
+ *   T = T_1 : T_0 = g*(x) * P_0
+ *   V = V_1 : V_0 = g*(x) * (P_1 + T_0)
+ *   p(x) / x^{128} mod g(x) = P_3 + P_1 + T_0 + V_1 : P_2 + P_0 + T_1 + V_0
+ *
+ * The implementation below saves a XOR instruction by computing P_1 + T_0 : P_0
+ * + T_1 and XORing into dest, rather than separately XORing P_1 : P_0 and T_0 :
+ * T_1 into dest.  This allows us to reuse P_1 + T_0 when computing V.
+ */
+.macro montgomery_reduction dest
+	DEST .req \dest
+	// TMP_V = T_1 : T_0 = P_0 * g*(x)
+	pmull	TMP_V.1q, PL.1d, GSTAR.1d
+	// TMP_V = T_0 : T_1
+	ext	TMP_V.16b, TMP_V.16b, TMP_V.16b, #8
+	// TMP_V = P_1 + T_0 : P_0 + T_1
+	eor	TMP_V.16b, PL.16b, TMP_V.16b
+	// PH = P_3 + P_1 + T_0 : P_2 + P_0 + T_1
+	eor	PH.16b, PH.16b, TMP_V.16b
+	// TMP_V = V_1 : V_0 = (P_1 + T_0) * g*(x)
+	pmull2	TMP_V.1q, TMP_V.2d, GSTAR.2d
+	eor	DEST.16b, PH.16b, TMP_V.16b
+	.unreq DEST
+.endm
+
+/*
+ * Compute Polyval on 8 blocks.
+ *
+ * If reduce is set, also computes the montgomery reduction of the
+ * previous full_stride call and XORs with the first message block.
+ * (m_0 + REDUCE(PL, PH))h^8 + ... + m_7h^1.
+ * I.e., the first multiplication uses m_0 + REDUCE(PL, PH) instead of m_0.
+ *
+ * Sets PL, PH.
+ */
+.macro full_stride reduce
+	eor		LO.16b, LO.16b, LO.16b
+	eor		MI.16b, MI.16b, MI.16b
+	eor		HI.16b, HI.16b, HI.16b
+
+	ld1		{M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
+	ld1		{M4.16b, M5.16b, M6.16b, M7.16b}, [MSG], #64
+
+	karatsuba1 M7 KEY1
+	.if \reduce
+	pmull	TMP_V.1q, PL.1d, GSTAR.1d
+	.endif
+
+	karatsuba1 M6 KEY2
+	.if \reduce
+	ext	TMP_V.16b, TMP_V.16b, TMP_V.16b, #8
+	.endif
+
+	karatsuba1 M5 KEY3
+	.if \reduce
+	eor	TMP_V.16b, PL.16b, TMP_V.16b
+	.endif
+
+	karatsuba1 M4 KEY4
+	.if \reduce
+	eor	PH.16b, PH.16b, TMP_V.16b
+	.endif
+
+	karatsuba1 M3 KEY5
+	.if \reduce
+	pmull2	TMP_V.1q, TMP_V.2d, GSTAR.2d
+	.endif
+
+	karatsuba1 M2 KEY6
+	.if \reduce
+	eor	SUM.16b, PH.16b, TMP_V.16b
+	.endif
+
+	karatsuba1 M1 KEY7
+	eor	M0.16b, M0.16b, SUM.16b
+
+	karatsuba1 M0 KEY8
+	karatsuba2
+.endm
+
+/*
+ * Handle any extra blocks after full_stride loop.
+ */
+.macro partial_stride
+	add	KEY_POWERS, KEY_START, #(STRIDE_BLOCKS << 4)
+	sub	KEY_POWERS, KEY_POWERS, BLOCKS_LEFT, lsl #4
+	ld1	{KEY1.16b}, [KEY_POWERS], #16
+
+	ld1	{TMP_V.16b}, [MSG], #16
+	eor	SUM.16b, SUM.16b, TMP_V.16b
+	karatsuba1_store KEY1 SUM
+	sub	BLOCKS_LEFT, BLOCKS_LEFT, #1
+
+	tst	BLOCKS_LEFT, #4
+	beq	.Lpartial4BlocksDone
+	ld1	{M0.16b, M1.16b,  M2.16b, M3.16b}, [MSG], #64
+	ld1	{KEY8.16b, KEY7.16b, KEY6.16b,	KEY5.16b}, [KEY_POWERS], #64
+	karatsuba1 M0 KEY8
+	karatsuba1 M1 KEY7
+	karatsuba1 M2 KEY6
+	karatsuba1 M3 KEY5
+.Lpartial4BlocksDone:
+	tst	BLOCKS_LEFT, #2
+	beq	.Lpartial2BlocksDone
+	ld1	{M0.16b, M1.16b}, [MSG], #32
+	ld1	{KEY8.16b, KEY7.16b}, [KEY_POWERS], #32
+	karatsuba1 M0 KEY8
+	karatsuba1 M1 KEY7
+.Lpartial2BlocksDone:
+	tst	BLOCKS_LEFT, #1
+	beq	.LpartialDone
+	ld1	{M0.16b}, [MSG], #16
+	ld1	{KEY8.16b}, [KEY_POWERS], #16
+	karatsuba1 M0 KEY8
+.LpartialDone:
+	karatsuba2
+	montgomery_reduction SUM
+.endm
+
+/*
+ * Perform montgomery multiplication in GF(2^128) and store result in op1.
+ *
+ * Computes op1*op2*x^{-128} mod x^128 + x^127 + x^126 + x^121 + 1
+ * If op1, op2 are in montgomery form, this computes the montgomery
+ * form of op1*op2.
+ *
+ * void pmull_polyval_mul(u8 *op1, const u8 *op2);
+ */
+SYM_FUNC_START(pmull_polyval_mul)
+	adr	TMP, .Lgstar
+	ld1	{GSTAR.2d}, [TMP]
+	ld1	{v0.16b}, [x0]
+	ld1	{v1.16b}, [x1]
+	karatsuba1_store v0 v1
+	karatsuba2
+	montgomery_reduction SUM
+	st1	{SUM.16b}, [x0]
+	ret
+SYM_FUNC_END(pmull_polyval_mul)
+
+/*
+ * Perform polynomial evaluation as specified by POLYVAL.  This computes:
+ *	h^n * accumulator + h^n * m_0 + ... + h^1 * m_{n-1}
+ * where n=nblocks, h is the hash key, and m_i are the message blocks.
+ *
+ * x0 - pointer to precomputed key powers h^8 ... h^1
+ * x1 - pointer to message blocks
+ * x2 - number of blocks to hash
+ * x3 - pointer to accumulator
+ *
+ * void pmull_polyval_update(const struct polyval_ctx *ctx, const u8 *in,
+ *			     size_t nblocks, u8 *accumulator);
+ */
+SYM_FUNC_START(pmull_polyval_update)
+	adr	TMP, .Lgstar
+	mov	KEY_START, KEY_POWERS
+	ld1	{GSTAR.2d}, [TMP]
+	ld1	{SUM.16b}, [ACCUMULATOR]
+	subs	BLOCKS_LEFT, BLOCKS_LEFT, #STRIDE_BLOCKS
+	blt .LstrideLoopExit
+	ld1	{KEY8.16b, KEY7.16b, KEY6.16b, KEY5.16b}, [KEY_POWERS], #64
+	ld1	{KEY4.16b, KEY3.16b, KEY2.16b, KEY1.16b}, [KEY_POWERS], #64
+	full_stride 0
+	subs	BLOCKS_LEFT, BLOCKS_LEFT, #STRIDE_BLOCKS
+	blt .LstrideLoopExitReduce
+.LstrideLoop:
+	full_stride 1
+	subs	BLOCKS_LEFT, BLOCKS_LEFT, #STRIDE_BLOCKS
+	bge	.LstrideLoop
+.LstrideLoopExitReduce:
+	montgomery_reduction SUM
+.LstrideLoopExit:
+	adds	BLOCKS_LEFT, BLOCKS_LEFT, #STRIDE_BLOCKS
+	beq	.LskipPartial
+	partial_stride
+.LskipPartial:
+	st1	{SUM.16b}, [ACCUMULATOR]
+	ret
+SYM_FUNC_END(pmull_polyval_update)
diff --git a/arch/arm64/crypto/polyval-ce-glue.c b/arch/arm64/crypto/polyval-ce-glue.c
new file mode 100644
index 000000000000..0a3b5718df85
--- /dev/null
+++ b/arch/arm64/crypto/polyval-ce-glue.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Glue code for POLYVAL using ARMv8 Crypto Extensions
+ *
+ * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
+ * Copyright (c) 2009 Intel Corp.
+ *   Author: Huang Ying <ying.huang@intel.com>
+ * Copyright 2021 Google LLC
+ */
+
+/*
+ * Glue code based on ghash-clmulni-intel_glue.c.
+ *
+ * This implementation of POLYVAL uses montgomery multiplication accelerated by
+ * ARMv8 Crypto Extensions instructions to implement the finite field operations.
+ */
+
+#include <crypto/algapi.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/simd.h>
+#include <crypto/polyval.h>
+#include <linux/crypto.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpufeature.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+
+#define NUM_KEY_POWERS	8
+
+struct polyval_tfm_ctx {
+	/*
+	 * These powers must be in the order h^8, ..., h^1.
+	 */
+	u8 key_powers[NUM_KEY_POWERS][POLYVAL_BLOCK_SIZE];
+};
+
+struct polyval_desc_ctx {
+	u8 buffer[POLYVAL_BLOCK_SIZE];
+	u32 bytes;
+};
+
+asmlinkage void pmull_polyval_update(const struct polyval_tfm_ctx *keys,
+	const u8 *in, size_t nblocks, u8 *accumulator);
+asmlinkage void pmull_polyval_mul(u8 *op1, const u8 *op2);
+
+static void internal_polyval_update(const struct polyval_tfm_ctx *keys,
+	const u8 *in, size_t nblocks, u8 *accumulator)
+{
+	if (likely(crypto_simd_usable())) {
+		kernel_neon_begin();
+		pmull_polyval_update(keys, in, nblocks, accumulator);
+		kernel_neon_end();
+	} else {
+		polyval_update_non4k(keys->key_powers[NUM_KEY_POWERS-1], in,
+			nblocks, accumulator);
+	}
+}
+
+static void internal_polyval_mul(u8 *op1, const u8 *op2)
+{
+	if (likely(crypto_simd_usable())) {
+		kernel_neon_begin();
+		pmull_polyval_mul(op1, op2);
+		kernel_neon_end();
+	} else {
+		polyval_mul_non4k(op1, op2);
+	}
+}
+
+static int polyval_arm64_setkey(struct crypto_shash *tfm,
+			const u8 *key, unsigned int keylen)
+{
+	struct polyval_tfm_ctx *tctx = crypto_shash_ctx(tfm);
+	int i;
+
+	if (keylen != POLYVAL_BLOCK_SIZE)
+		return -EINVAL;
+
+	memcpy(tctx->key_powers[NUM_KEY_POWERS-1], key, POLYVAL_BLOCK_SIZE);
+
+	for (i = NUM_KEY_POWERS-2; i >= 0; i--) {
+		memcpy(tctx->key_powers[i], key, POLYVAL_BLOCK_SIZE);
+		internal_polyval_mul(tctx->key_powers[i],
+				     tctx->key_powers[i+1]);
+	}
+
+	return 0;
+}
+
+static int polyval_arm64_init(struct shash_desc *desc)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	memset(dctx, 0, sizeof(*dctx));
+
+	return 0;
+}
+
+static int polyval_arm64_update(struct shash_desc *desc,
+			 const u8 *src, unsigned int srclen)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+	u8 *pos;
+	unsigned int nblocks;
+	unsigned int n;
+
+	if (dctx->bytes) {
+		n = min(srclen, dctx->bytes);
+		pos = dctx->buffer + POLYVAL_BLOCK_SIZE - dctx->bytes;
+
+		dctx->bytes -= n;
+		srclen -= n;
+
+		while (n--)
+			*pos++ ^= *src++;
+
+		if (!dctx->bytes)
+			internal_polyval_mul(dctx->buffer,
+					    tctx->key_powers[NUM_KEY_POWERS-1]);
+	}
+
+	while (srclen >= POLYVAL_BLOCK_SIZE) {
+		/* allow rescheduling every 4K bytes */
+		nblocks = min(srclen, 4096U) / POLYVAL_BLOCK_SIZE;
+		internal_polyval_update(tctx, src, nblocks, dctx->buffer);
+		srclen -= nblocks * POLYVAL_BLOCK_SIZE;
+		src += nblocks * POLYVAL_BLOCK_SIZE;
+	}
+
+	if (srclen) {
+		dctx->bytes = POLYVAL_BLOCK_SIZE - srclen;
+		pos = dctx->buffer;
+		while (srclen--)
+			*pos++ ^= *src++;
+	}
+
+	return 0;
+}
+
+static int polyval_arm64_final(struct shash_desc *desc, u8 *dst)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+	if (dctx->bytes) {
+		internal_polyval_mul(dctx->buffer,
+				     tctx->key_powers[NUM_KEY_POWERS-1]);
+	}
+
+	memcpy(dst, dctx->buffer, POLYVAL_BLOCK_SIZE);
+
+	return 0;
+}
+
+static struct shash_alg polyval_alg = {
+	.digestsize	= POLYVAL_DIGEST_SIZE,
+	.init		= polyval_arm64_init,
+	.update		= polyval_arm64_update,
+	.final		= polyval_arm64_final,
+	.setkey		= polyval_arm64_setkey,
+	.descsize	= sizeof(struct polyval_desc_ctx),
+	.base		= {
+		.cra_name		= "polyval",
+		.cra_driver_name	= "polyval-ce",
+		.cra_priority		= 200,
+		.cra_blocksize		= POLYVAL_BLOCK_SIZE,
+		.cra_ctxsize		= sizeof(struct polyval_tfm_ctx),
+		.cra_module		= THIS_MODULE,
+	},
+};
+
+static int __init polyval_ce_mod_init(void)
+{
+	return crypto_register_shash(&polyval_alg);
+}
+
+static void __exit polyval_ce_mod_exit(void)
+{
+	crypto_unregister_shash(&polyval_alg);
+}
+
+module_cpu_feature_match(PMULL, polyval_ce_mod_init)
+module_exit(polyval_ce_mod_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("POLYVAL hash function accelerated by ARMv8 Crypto Extensions");
+MODULE_ALIAS_CRYPTO("polyval");
+MODULE_ALIAS_CRYPTO("polyval-ce");
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 3995652daf81..f7cd0e01bfdd 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -91,7 +91,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 }
 
 /* IO barriers */
-#define __iormb(v)							\
+#define __io_ar(v)							\
 ({									\
 	unsigned long tmp;						\
 									\
@@ -108,39 +108,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 		     : "memory");					\
 })
 
-#define __io_par(v)		__iormb(v)
-#define __iowmb()		dma_wmb()
-#define __iomb()		dma_mb()
-
-/*
- * Relaxed I/O memory access primitives. These follow the Device memory
- * ordering rules but do not guarantee any ordering relative to Normal memory
- * accesses.
- */
-#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
-#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
-#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
-#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
+#define __io_bw()		dma_wmb()
+#define __io_br(v)
+#define __io_aw(v)
 
-#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
-#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
-#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
-#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
-
-/*
- * I/O memory access primitives. Reads are ordered relative to any
- * following Normal memory access. Writes are ordered relative to any prior
- * Normal memory access.
- */
-#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })
-#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
-#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
-#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
-
-#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
-#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
-#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
-#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })
+/* arm64-specific, don't use in portable drivers */
+#define __iormb(v)		__io_ar(v)
+#define __iowmb()		__io_bw()
+#define __iomb()		dma_mb()
 
 /*
  *  I/O port access primitives.
diff --git a/arch/arm64/kernel/elfcore.c b/arch/arm64/kernel/elfcore.c
index 98d67444a5b6..27ef7ad3ffd2 100644
--- a/arch/arm64/kernel/elfcore.c
+++ b/arch/arm64/kernel/elfcore.c
@@ -8,9 +8,9 @@
 #include <asm/cpufeature.h>
 #include <asm/mte.h>
 
-#define for_each_mte_vma(tsk, vma)					\
+#define for_each_mte_vma(vmi, vma)					\
 	if (system_supports_mte())					\
-		for (vma = tsk->mm->mmap; vma; vma = vma->vm_next)	\
+		for_each_vma(vmi, vma)					\
 			if (vma->vm_flags & VM_MTE)
 
 static unsigned long mte_vma_tag_dump_size(struct vm_area_struct *vma)
@@ -81,8 +81,9 @@ Elf_Half elf_core_extra_phdrs(void)
 {
 	struct vm_area_struct *vma;
 	int vma_count = 0;
+	VMA_ITERATOR(vmi, current->mm, 0);
 
-	for_each_mte_vma(current, vma)
+	for_each_mte_vma(vmi, vma)
 		vma_count++;
 
 	return vma_count;
@@ -91,8 +92,9 @@ Elf_Half elf_core_extra_phdrs(void)
 int elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset)
 {
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, current->mm, 0);
 
-	for_each_mte_vma(current, vma) {
+	for_each_mte_vma(vmi, vma) {
 		struct elf_phdr phdr;
 
 		phdr.p_type = PT_AARCH64_MEMTAG_MTE;
@@ -116,8 +118,9 @@ size_t elf_core_extra_data_size(void)
 {
 	struct vm_area_struct *vma;
 	size_t data_size = 0;
+	VMA_ITERATOR(vmi, current->mm, 0);
 
-	for_each_mte_vma(current, vma)
+	for_each_mte_vma(vmi, vma)
 		data_size += mte_vma_tag_dump_size(vma);
 
 	return data_size;
@@ -126,8 +129,9 @@ size_t elf_core_extra_data_size(void)
 int elf_core_write_extra_data(struct coredump_params *cprm)
 {
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, current->mm, 0);
 
-	for_each_mte_vma(current, vma) {
+	for_each_mte_vma(vmi, vma) {
 		if (vma->vm_flags & VM_DONTDUMP)
 			continue;
 
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 56cefd33eb8e..c75ca36b4a49 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -41,7 +41,7 @@ static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs)
 
 	if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
 		lockdep_hardirqs_off(CALLER_ADDR0);
-		rcu_irq_enter();
+		ct_irq_enter();
 		trace_hardirqs_off_finish();
 
 		regs->exit_rcu = true;
@@ -76,7 +76,7 @@ static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
 		if (regs->exit_rcu) {
 			trace_hardirqs_on_prepare();
 			lockdep_hardirqs_on_prepare();
-			rcu_irq_exit();
+			ct_irq_exit();
 			lockdep_hardirqs_on(CALLER_ADDR0);
 			return;
 		}
@@ -84,7 +84,7 @@ static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
 		trace_hardirqs_on();
 	} else {
 		if (regs->exit_rcu)
-			rcu_irq_exit();
+			ct_irq_exit();
 	}
 }
 
@@ -161,7 +161,7 @@ static void noinstr arm64_enter_nmi(struct pt_regs *regs)
 	__nmi_enter();
 	lockdep_hardirqs_off(CALLER_ADDR0);
 	lockdep_hardirq_enter();
-	rcu_nmi_enter();
+	ct_nmi_enter();
 
 	trace_hardirqs_off_finish();
 	ftrace_nmi_enter();
@@ -182,7 +182,7 @@ static void noinstr arm64_exit_nmi(struct pt_regs *regs)
 		lockdep_hardirqs_on_prepare();
 	}
 
-	rcu_nmi_exit();
+	ct_nmi_exit();
 	lockdep_hardirq_exit();
 	if (restore)
 		lockdep_hardirqs_on(CALLER_ADDR0);
@@ -199,7 +199,7 @@ static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
 	regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
 
 	lockdep_hardirqs_off(CALLER_ADDR0);
-	rcu_nmi_enter();
+	ct_nmi_enter();
 
 	trace_hardirqs_off_finish();
 }
@@ -218,7 +218,7 @@ static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
 		lockdep_hardirqs_on_prepare();
 	}
 
-	rcu_nmi_exit();
+	ct_nmi_exit();
 	if (restore)
 		lockdep_hardirqs_on(CALLER_ADDR0);
 }
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
index a61fc4f989b3..a8388af62b99 100644
--- a/arch/arm64/kernel/vdso.c
+++ b/arch/arm64/kernel/vdso.c
@@ -136,10 +136,11 @@ int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
 {
 	struct mm_struct *mm = task->mm;
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
 	mmap_read_lock(mm);
 
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		unsigned long size = vma->vm_end - vma->vm_start;
 
 		if (vma_is_special_mapping(vma, vdso_info[VDSO_ABI_AA64].dm))
diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile
index f9fe4dc21b1f..87d22a18b7a5 100644
--- a/arch/arm64/kvm/hyp/nvhe/Makefile
+++ b/arch/arm64/kvm/hyp/nvhe/Makefile
@@ -4,7 +4,12 @@
 #
 
 asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS
-ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS
+
+# Tracepoint and MMIO logging symbols should not be visible at nVHE KVM as
+# there is no way to execute them and any such MMIO access from nVHE KVM
+# will explode instantly (Words of Marc Zyngier). So introduce a generic flag
+# __DISABLE_TRACE_MMIO__ to disable MMIO tracing for nVHE KVM.
+ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__
 
 hostprogs := gen-hyprel
 HOST_EXTRACFLAGS += -I$(objtree)/include
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index c5e11768e5c1..de166cdeb89a 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -608,6 +608,10 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr,
 		return 0;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return 0;
+
 	if (fault & VM_FAULT_RETRY) {
 		mm_flags |= FAULT_FLAG_TRIED;
 		goto retry;
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index e2a5ec9fdc0d..c9e076683e5d 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -368,6 +368,26 @@ pte_t *huge_pte_offset(struct mm_struct *mm,
 	return NULL;
 }
 
+unsigned long hugetlb_mask_last_page(struct hstate *h)
+{
+	unsigned long hp_size = huge_page_size(h);
+
+	switch (hp_size) {
+	case PUD_SIZE:
+		return PGDIR_SIZE - PUD_SIZE;
+	case CONT_PMD_SIZE:
+		return PUD_SIZE - CONT_PMD_SIZE;
+	case PMD_SIZE:
+		return PUD_SIZE - PMD_SIZE;
+	case CONT_PTE_SIZE:
+		return PMD_SIZE - CONT_PTE_SIZE;
+	default:
+		break;
+	}
+
+	return 0UL;
+}
+
 pte_t arch_make_huge_pte(pte_t entry, unsigned int shift, vm_flags_t flags)
 {
 	size_t pagesize = 1UL << shift;
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 339ee84e5a61..8456dbae9441 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -350,8 +350,8 @@ void __init arm64_memblock_init(void)
 			"initrd not fully accessible via the linear mapping -- please check your bootloader ...\n")) {
 			phys_initrd_size = 0;
 		} else {
-			memblock_remove(base, size); /* clear MEMBLOCK_ flags */
 			memblock_add(base, size);
+			memblock_clear_nomap(base, size);
 			memblock_reserve(base, size);
 		}
 	}
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 42f2e9a8616c..f08a4447d363 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -246,6 +246,7 @@ static bool is_lsi_offset(int offset, int scale)
 static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf)
 {
 	const struct bpf_prog *prog = ctx->prog;
+	const bool is_main_prog = prog->aux->func_idx == 0;
 	const u8 r6 = bpf2a64[BPF_REG_6];
 	const u8 r7 = bpf2a64[BPF_REG_7];
 	const u8 r8 = bpf2a64[BPF_REG_8];
@@ -299,7 +300,7 @@ static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf)
 	/* Set up BPF prog stack base register */
 	emit(A64_MOV(1, fp, A64_SP), ctx);
 
-	if (!ebpf_from_cbpf) {
+	if (!ebpf_from_cbpf && is_main_prog) {
 		/* Initialize tail_call_cnt */
 		emit(A64_MOVZ(1, tcc, 0, 0), ctx);
 
@@ -1530,3 +1531,9 @@ void bpf_jit_free_exec(void *addr)
 {
 	return vfree(addr);
 }
+
+/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
+bool bpf_jit_supports_subprog_tailcalls(void)
+{
+	return true;
+}
diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig
index 21d72b078eef..f55ba1745f7b 100644
--- a/arch/csky/Kconfig
+++ b/arch/csky/Kconfig
@@ -42,7 +42,7 @@ config CSKY
 	select HAVE_ARCH_AUDITSYSCALL
 	select HAVE_ARCH_MMAP_RND_BITS
 	select HAVE_ARCH_SECCOMP_FILTER
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
 	select HAVE_DEBUG_BUGVERBOSE
 	select HAVE_DEBUG_KMEMLEAK
diff --git a/arch/csky/kernel/entry.S b/arch/csky/kernel/entry.S
index a4ababf25e24..547b4cd1b24b 100644
--- a/arch/csky/kernel/entry.S
+++ b/arch/csky/kernel/entry.S
@@ -19,11 +19,11 @@
 .endm
 
 .macro	context_tracking
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
 	mfcr	a0, epsr
 	btsti	a0, 31
 	bt	1f
-	jbsr	context_tracking_user_exit
+	jbsr	user_exit_callable
 	ldw	a0, (sp, LSAVE_A0)
 	ldw	a1, (sp, LSAVE_A1)
 	ldw	a2, (sp, LSAVE_A2)
@@ -159,8 +159,8 @@ ret_from_exception:
 	and	r10, r9
 	cmpnei	r10, 0
 	bt	exit_work
-#ifdef CONFIG_CONTEXT_TRACKING
-	jbsr	context_tracking_user_enter
+#ifdef CONFIG_CONTEXT_TRACKING_USER
+	jbsr	user_enter_callable
 #endif
 1:
 #ifdef CONFIG_PREEMPTION
diff --git a/arch/csky/mm/fault.c b/arch/csky/mm/fault.c
index 7215a46b6b8e..e15f736cca4b 100644
--- a/arch/csky/mm/fault.c
+++ b/arch/csky/mm/fault.c
@@ -285,6 +285,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
 		return;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely((fault & VM_FAULT_RETRY) && (flags & FAULT_FLAG_ALLOW_RETRY))) {
 		flags |= FAULT_FLAG_TRIED;
 
diff --git a/arch/hexagon/mm/vm_fault.c b/arch/hexagon/mm/vm_fault.c
index 4fac4b9eb316..f73c7cbfe326 100644
--- a/arch/hexagon/mm/vm_fault.c
+++ b/arch/hexagon/mm/vm_fault.c
@@ -96,6 +96,10 @@ void do_page_fault(unsigned long address, long cause, struct pt_regs *regs)
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	/* The most common case -- we are done. */
 	if (likely(!(fault & VM_FAULT_ERROR))) {
 		if (fault & VM_FAULT_RETRY) {
diff --git a/arch/ia64/include/uapi/asm/cmpxchg.h b/arch/ia64/include/uapi/asm/cmpxchg.h
index 2c2f3cfeaa77..ca2e02685343 100644
--- a/arch/ia64/include/uapi/asm/cmpxchg.h
+++ b/arch/ia64/include/uapi/asm/cmpxchg.h
@@ -33,24 +33,24 @@ extern void ia64_xchg_called_with_bad_pointer(void);
 									\
 	switch (size) {							\
 	case 1:								\
-		__xchg_result = ia64_xchg1((__u8 *)ptr, x);		\
+		__xchg_result = ia64_xchg1((__u8 __force *)ptr, x);	\
 		break;							\
 									\
 	case 2:								\
-		__xchg_result = ia64_xchg2((__u16 *)ptr, x);		\
+		__xchg_result = ia64_xchg2((__u16 __force *)ptr, x);	\
 		break;							\
 									\
 	case 4:								\
-		__xchg_result = ia64_xchg4((__u32 *)ptr, x);		\
+		__xchg_result = ia64_xchg4((__u32 __force *)ptr, x);	\
 		break;							\
 									\
 	case 8:								\
-		__xchg_result = ia64_xchg8((__u64 *)ptr, x);		\
+		__xchg_result = ia64_xchg8((__u64 __force *)ptr, x);	\
 		break;							\
 	default:							\
 		ia64_xchg_called_with_bad_pointer();			\
 	}								\
-	__xchg_result;							\
+	(__typeof__ (*(ptr)) __force) __xchg_result;			\
 })
 
 #ifndef __KERNEL__
@@ -76,42 +76,42 @@ extern long ia64_cmpxchg_called_with_bad_pointer(void);
 									\
 	switch (size) {							\
 	case 1:								\
-		_o_ = (__u8) (long) (old);				\
+		_o_ = (__u8) (long __force) (old);			\
 		break;							\
 	case 2:								\
-		_o_ = (__u16) (long) (old);				\
+		_o_ = (__u16) (long __force) (old);			\
 		break;							\
 	case 4:								\
-		_o_ = (__u32) (long) (old);				\
+		_o_ = (__u32) (long __force) (old);			\
 		break;							\
 	case 8:								\
-		_o_ = (__u64) (long) (old);				\
+		_o_ = (__u64) (long __force) (old);			\
 		break;							\
 	default:							\
 		break;							\
 	}								\
 	switch (size) {							\
 	case 1:								\
-		_r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_);	\
+		_r_ = ia64_cmpxchg1_##sem((__u8 __force *) ptr, new, _o_);	\
 		break;							\
 									\
 	case 2:								\
-		_r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_);	\
+		_r_ = ia64_cmpxchg2_##sem((__u16 __force *) ptr, new, _o_);	\
 		break;							\
 									\
 	case 4:								\
-		_r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_);	\
+		_r_ = ia64_cmpxchg4_##sem((__u32 __force *) ptr, new, _o_);	\
 		break;							\
 									\
 	case 8:								\
-		_r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_);	\
+		_r_ = ia64_cmpxchg8_##sem((__u64 __force *) ptr, new, _o_);	\
 		break;							\
 									\
 	default:							\
 		_r_ = ia64_cmpxchg_called_with_bad_pointer();		\
 		break;							\
 	}								\
-	(__typeof__(old)) _r_;						\
+	(__typeof__(old) __force) _r_;					\
 })
 
 #define cmpxchg_acq(ptr, o, n)	\
diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c
index 07379d1a227f..ef78c2d66cdd 100644
--- a/arch/ia64/mm/fault.c
+++ b/arch/ia64/mm/fault.c
@@ -139,6 +139,10 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		/*
 		 * We ran out of memory, or some other thing happened
diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine
index a1042568b9ad..4fbe57de1851 100644
--- a/arch/m68k/Kconfig.machine
+++ b/arch/m68k/Kconfig.machine
@@ -161,10 +161,11 @@ config VIRT
 	select RTC_CLASS
 	select RTC_DRV_GOLDFISH
 	select TTY
+	select VIRTIO_MENU
 	select VIRTIO_MMIO
 	help
 	  This options enable a pure virtual machine based on m68k,
-	  VIRTIO MMIO devices and GOLDFISH interfaces (TTY, RTC, PIC)
+	  VIRTIO MMIO devices and GOLDFISH interfaces (TTY, RTC, PIC).
 
 config PILOT
 	bool
diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
index 4218750414bb..7dab46728aed 100644
--- a/arch/m68k/coldfire/device.c
+++ b/arch/m68k/coldfire/device.c
@@ -581,7 +581,7 @@ static struct platform_device mcf_esdhc = {
 };
 #endif /* MCFSDHC_BASE */
 
-#if IS_ENABLED(CONFIG_CAN_FLEXCAN)
+#ifdef MCFFLEXCAN_SIZE
 
 #include <linux/can/platform/flexcan.h>
 
@@ -620,7 +620,7 @@ static struct platform_device mcf_flexcan0 = {
 	.resource = mcf5441x_flexcan0_resource,
 	.dev.platform_data = &mcf5441x_flexcan_info,
 };
-#endif /* IS_ENABLED(CONFIG_CAN_FLEXCAN) */
+#endif /* MCFFLEXCAN_SIZE */
 
 static struct platform_device *mcf_devices[] __initdata = {
 	&mcf_uart,
@@ -657,7 +657,7 @@ static struct platform_device *mcf_devices[] __initdata = {
 #ifdef MCFSDHC_BASE
 	&mcf_esdhc,
 #endif
-#if IS_ENABLED(CONFIG_CAN_FLEXCAN)
+#ifdef MCFFLEXCAN_SIZE
 	&mcf_flexcan0,
 #endif
 };
diff --git a/arch/m68k/coldfire/intc-2.c b/arch/m68k/coldfire/intc-2.c
index 995093357c59..f74f0e473119 100644
--- a/arch/m68k/coldfire/intc-2.c
+++ b/arch/m68k/coldfire/intc-2.c
@@ -7,7 +7,7 @@
  * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
  * controllers, and the 547x and 548x families which have only one of them.
  *
- * The external 7 fixed interrupts are part the the Edge Port unit of these
+ * The external 7 fixed interrupts are part of the Edge Port unit of these
  * ColdFire parts. They can be configured as level or edge triggered.
  *
  * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
diff --git a/arch/m68k/coldfire/m523x.c b/arch/m68k/coldfire/m523x.c
index 193c178162c1..83a997313393 100644
--- a/arch/m68k/coldfire/m523x.c
+++ b/arch/m68k/coldfire/m523x.c
@@ -28,7 +28,7 @@
 DEFINE_CLK(pll, "pll.0", MCF_CLK);
 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
 
-struct clk_lookup m523x_clk_lookup[] = {
+static struct clk_lookup m523x_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
 	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
 	CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
diff --git a/arch/m68k/mac/iop.c b/arch/m68k/mac/iop.c
index de156a027f5b..010b3b5ae8e8 100644
--- a/arch/m68k/mac/iop.c
+++ b/arch/m68k/mac/iop.c
@@ -25,7 +25,7 @@
  *		  check this.)
  * 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is
  *		  gone, IOP base addresses are now in an array and the
- *		  globally-visible functions take an IOP number instead of an
+ *		  globally-visible functions take an IOP number instead of
  *		  an actual base address.
  * 990610 (jmt) - Finished the message passing framework and it seems to work.
  *		  Sending _definitely_ works; my adb-bus.c mods can send
@@ -66,7 +66,7 @@
  * a shared memory area in the IOP RAM. Each IOP has seven "channels"; each
  * channel is connected to a specific software driver on the IOP. For example
  * on the SCC IOP there is one channel for each serial port. Each channel has
- * an incoming and and outgoing message queue with a depth of one.
+ * an incoming and an outgoing message queue with a depth of one.
  *
  * A message is 32 bytes plus a state byte for the channel (MSG_IDLE, MSG_NEW,
  * MSG_RCVD, MSG_COMPLETE). To send a message you copy the message into the
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index 71aa9f6315dc..4d2837eb3e2a 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -141,6 +141,10 @@ int do_page_fault(struct pt_regs *regs, unsigned long address,
 	if (fault_signal_pending(fault, regs))
 		return 0;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return 0;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/m68k/sun3/mmu_emu.c b/arch/m68k/sun3/mmu_emu.c
index 7ec20817c0c9..7321b3b76283 100644
--- a/arch/m68k/sun3/mmu_emu.c
+++ b/arch/m68k/sun3/mmu_emu.c
@@ -211,7 +211,7 @@ void clear_context(unsigned long context)
 
      if(context) {
 	     if(!ctx_alloc[context])
-		     panic("clear_context: context not allocated\n");
+		     panic("%s: context not allocated\n", __func__);
 
 	     ctx_alloc[context]->context = SUN3_INVALID_CONTEXT;
 	     ctx_alloc[context] = (struct mm_struct *)0;
@@ -261,7 +261,7 @@ unsigned long get_free_context(struct mm_struct *mm)
 		}
 		// check to make sure one was really free...
 		if(new == CONTEXTS_NUM)
-			panic("get_free_context: failed to find free context");
+			panic("%s: failed to find free context", __func__);
 	}
 
 	ctx_alloc[new] = mm;
@@ -369,16 +369,15 @@ int mmu_emu_handle_fault (unsigned long vaddr, int read_flag, int kernel_fault)
 	}
 
 #ifdef DEBUG_MMU_EMU
-	pr_info("mmu_emu_handle_fault: vaddr=%lx type=%s crp=%p\n",
-		vaddr, read_flag ? "read" : "write", crp);
+	pr_info("%s: vaddr=%lx type=%s crp=%p\n", __func__, vaddr,
+		read_flag ? "read" : "write", crp);
 #endif
 
 	segment = (vaddr >> SUN3_PMEG_SIZE_BITS) & 0x7FF;
 	offset  = (vaddr >> SUN3_PTE_SIZE_BITS) & 0xF;
 
 #ifdef DEBUG_MMU_EMU
-	pr_info("mmu_emu_handle_fault: segment=%lx offset=%lx\n", segment,
-		offset);
+	pr_info("%s: segment=%lx offset=%lx\n", __func__, segment, offset);
 #endif
 
 	pte = (pte_t *) pgd_val (*(crp + segment));
diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c
index a9626e6a68af..5c40c3ebe52f 100644
--- a/arch/microblaze/mm/fault.c
+++ b/arch/microblaze/mm/fault.c
@@ -222,6 +222,10 @@ void do_page_fault(struct pt_regs *regs, unsigned long address,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index db09d45d59ec..9457894db237 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -56,7 +56,7 @@ config MIPS
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
 	select HAVE_ASM_MODVERSIONS
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_TIF_NOHZ
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_DEBUG_KMEMLEAK
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index b0a034b468bb..42e69664efd9 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -111,8 +111,9 @@ tcu: timer@10002000 {
 
 		clocks = <&cgu X1000_CLK_RTCLK>,
 			 <&cgu X1000_CLK_EXCLK>,
-			 <&cgu X1000_CLK_PCLK>;
-		clock-names = "rtc", "ext", "pclk";
+			 <&cgu X1000_CLK_PCLK>,
+			 <&cgu X1000_CLK_TCU>;
+		clock-names = "rtc", "ext", "pclk", "tcu";
 
 		interrupt-controller;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index dbf21afaccb1..65a5da71c199 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -104,8 +104,9 @@ tcu: timer@10002000 {
 
 		clocks = <&cgu X1830_CLK_RTCLK>,
 			 <&cgu X1830_CLK_EXCLK>,
-			 <&cgu X1830_CLK_PCLK>;
-		clock-names = "rtc", "ext", "pclk";
+			 <&cgu X1830_CLK_PCLK>,
+			 <&cgu X1830_CLK_TCU>;
+		clock-names = "rtc", "ext", "pclk", "tcu";
 
 		interrupt-controller;
 		#interrupt-cells = <1>;
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index b6695367aa33..97ceaf080c0c 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -134,7 +134,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_STAGING=y
 CONFIG_OCTEON_ETHERNET=y
-CONFIG_OCTEON_USB=y
+CONFIG_USB_OCTEON_HCD=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_RAS=y
 CONFIG_EXT4_FS=y
diff --git a/arch/mips/generic/board-ranchu.c b/arch/mips/generic/board-ranchu.c
index a89aaad59cb1..930c45041882 100644
--- a/arch/mips/generic/board-ranchu.c
+++ b/arch/mips/generic/board-ranchu.c
@@ -44,6 +44,7 @@ static __init unsigned int ranchu_measure_hpt_freq(void)
 		      __func__);
 
 	rtc_base = of_iomap(np, 0);
+	of_node_put(np);
 	if (!rtc_base)
 		panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
 
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index d5f7362e8c24..dc023a979803 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -230,7 +230,7 @@ void mips_mt_set_cpuoptions(void)
 
 struct class *mt_class;
 
-static int __init mt_init(void)
+static int __init mips_mt_init(void)
 {
 	struct class *mtc;
 
@@ -243,4 +243,4 @@ static int __init mt_init(void)
 	return 0;
 }
 
-subsys_initcall(mt_init);
+subsys_initcall(mips_mt_init);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 5204fc6d6d50..1187729d8cbb 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -208,6 +208,12 @@ void __init ltq_soc_init(void)
 			of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
 		panic("Failed to get core resources");
 
+	of_node_put(np_status);
+	of_node_put(np_ebu);
+	of_node_put(np_sys1);
+	of_node_put(np_syseth);
+	of_node_put(np_sysgpe);
+
 	if ((request_mem_region(res_status.start, resource_size(&res_status),
 				res_status.name) < 0) ||
 		(request_mem_region(res_ebu.start, resource_size(&res_ebu),
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index b732495f138a..20622bf0a9b3 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -408,6 +408,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 		if (!ltq_eiu_membase)
 			panic("Failed to remap eiu memory");
 	}
+	of_node_put(eiu_node);
 
 	return 0;
 }
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 084f6caba5f2..d444a1b98a72 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -441,6 +441,10 @@ void __init ltq_soc_init(void)
 			of_address_to_resource(np_ebu, 0, &res_ebu))
 		panic("Failed to get core resources");
 
+	of_node_put(np_pmu);
+	of_node_put(np_cgu);
+	of_node_put(np_ebu);
+
 	if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
 				res_pmu.name) ||
 		!request_mem_region(res_cgu.start, resource_size(&res_cgu),
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index b08bc556d30d..a27045f5a556 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -162,6 +162,10 @@ static void __do_page_fault(struct pt_regs *regs, unsigned long write,
 		return;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index bbf1e38e1431..2cb708cdf01a 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -214,6 +214,8 @@ static void update_gic_frequency_dt(void)
 
 	if (of_update_property(node, &gic_frequency_prop) < 0)
 		pr_err("error updating gic frequency property\n");
+
+	of_node_put(node);
 }
 
 #endif
diff --git a/arch/mips/pic32/pic32mzda/init.c b/arch/mips/pic32/pic32mzda/init.c
index 129915616763..d9c8c4e46aff 100644
--- a/arch/mips/pic32/pic32mzda/init.c
+++ b/arch/mips/pic32/pic32mzda/init.c
@@ -98,13 +98,18 @@ static int __init pic32_of_prepare_platform_data(struct of_dev_auxdata *lookup)
 		np = of_find_compatible_node(NULL, NULL, lookup->compatible);
 		if (np) {
 			lookup->name = (char *)np->name;
-			if (lookup->phys_addr)
+			if (lookup->phys_addr) {
+				of_node_put(np);
 				continue;
+			}
 			if (!of_address_to_resource(np, 0, &res))
 				lookup->phys_addr = res.start;
+			of_node_put(np);
 		}
 	}
 
+	of_node_put(root);
+
 	return 0;
 }
 
diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index 7174e9abbb1b..777b515c52c8 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -32,6 +32,9 @@ static unsigned int pic32_xlate_core_timer_irq(void)
 		goto default_map;
 
 	irq = irq_of_parse_and_map(node, 0);
+
+	of_node_put(node);
+
 	if (!irq)
 		goto default_map;
 
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 587c7b998769..ea8072acf8d9 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -40,6 +40,8 @@ __iomem void *plat_of_remap_node(const char *node)
 	if (of_address_to_resource(np, 0, &res))
 		panic("Failed to get resource for %s", node);
 
+	of_node_put(np);
+
 	if (!request_mem_region(res.start,
 				resource_size(&res),
 				res.name))
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 7b7f25b4b057..9240bcdbe74e 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -640,8 +640,6 @@ static int icu_get_irq(unsigned int irq)
 
 	printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
 
-	atomic_inc(&irq_err_count);
-
 	return -1;
 }
 
diff --git a/arch/nios2/mm/fault.c b/arch/nios2/mm/fault.c
index a32f14cd72f2..edaca0a6c1c1 100644
--- a/arch/nios2/mm/fault.c
+++ b/arch/nios2/mm/fault.c
@@ -139,6 +139,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long cause,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/openrisc/mm/fault.c b/arch/openrisc/mm/fault.c
index 53b760af3bb7..b4762d66e9ef 100644
--- a/arch/openrisc/mm/fault.c
+++ b/arch/openrisc/mm/fault.c
@@ -165,6 +165,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 8d03b3b26229..0bdee6724132 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -22,7 +22,7 @@ void flush_kernel_icache_range_asm(unsigned long, unsigned long);
 void flush_user_dcache_range_asm(unsigned long, unsigned long);
 void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
 void purge_kernel_dcache_range_asm(unsigned long, unsigned long);
-void flush_kernel_dcache_page_asm(void *);
+void flush_kernel_dcache_page_asm(const void *addr);
 void flush_kernel_icache_page(void *);
 
 /* Cache flush operations */
@@ -31,7 +31,7 @@ void flush_cache_all_local(void);
 void flush_cache_all(void);
 void flush_cache_mm(struct mm_struct *mm);
 
-void flush_kernel_dcache_page_addr(void *addr);
+void flush_kernel_dcache_page_addr(const void *addr);
 
 #define flush_kernel_dcache_range(start,size) \
 	flush_kernel_dcache_range_asm((start), (start)+(size));
@@ -75,7 +75,7 @@ void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
 void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr);
 
 #define ARCH_HAS_FLUSH_ON_KUNMAP
-static inline void kunmap_flush_on_unmap(void *addr)
+static inline void kunmap_flush_on_unmap(const void *addr)
 {
 	flush_kernel_dcache_page_addr(addr);
 }
diff --git a/arch/parisc/include/asm/fb.h b/arch/parisc/include/asm/fb.h
index d63a2acb91f2..55d29c4f716e 100644
--- a/arch/parisc/include/asm/fb.h
+++ b/arch/parisc/include/asm/fb.h
@@ -12,7 +12,7 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
 	pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
 }
 
-#if defined(CONFIG_STI_CONSOLE) || defined(CONFIG_FB_STI)
+#if defined(CONFIG_FB_STI)
 int fb_is_primary_device(struct fb_info *info);
 #else
 static inline int fb_is_primary_device(struct fb_info *info)
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index c8a11fcecf4c..c61bced69f63 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -549,7 +549,7 @@ extern void purge_kernel_dcache_page_asm(unsigned long);
 extern void clear_user_page_asm(void *, unsigned long);
 extern void copy_user_page_asm(void *, void *, unsigned long);
 
-void flush_kernel_dcache_page_addr(void *addr)
+void flush_kernel_dcache_page_addr(const void *addr)
 {
 	unsigned long flags;
 
@@ -660,15 +660,20 @@ static inline unsigned long mm_total_size(struct mm_struct *mm)
 {
 	struct vm_area_struct *vma;
 	unsigned long usize = 0;
+	VMA_ITERATOR(vmi, mm, 0);
 
-	for (vma = mm->mmap; vma && usize < parisc_cache_flush_threshold; vma = vma->vm_next)
+	for_each_vma(vmi, vma) {
+		if (usize >= parisc_cache_flush_threshold)
+			break;
 		usize += vma->vm_end - vma->vm_start;
+	}
 	return usize;
 }
 
 void flush_cache_mm(struct mm_struct *mm)
 {
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
 	/*
 	 * Flushing the whole cache on each cpu takes forever on
@@ -688,7 +693,7 @@ void flush_cache_mm(struct mm_struct *mm)
 	}
 
 	/* Flush mm */
-	for (vma = mm->mmap; vma; vma = vma->vm_next)
+	for_each_vma(vmi, vma)
 		flush_cache_pages(vma, vma->vm_start, vma->vm_end);
 }
 
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 0fe2d79fb123..eba193bcdab1 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -480,10 +480,12 @@ static void execute_on_irq_stack(void *func, unsigned long param1)
 	*irq_stack_in_use = 1;
 }
 
+#ifndef CONFIG_PREEMPT_RT
 void do_softirq_own_stack(void)
 {
 	execute_on_irq_stack(__do_softirq, 0);
 }
+#endif
 #endif /* CONFIG_IRQSTACKS */
 
 /* ONLY called from entry.S:intr_extint() */
diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index 84bc437be5cd..9ad80d4d3389 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
@@ -311,6 +311,10 @@ void do_page_fault(struct pt_regs *regs, unsigned long code,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		/*
 		 * We hit a shared mapping outside of the file, or some
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c2ce2e60c8f0..8f76499919fe 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -202,7 +202,7 @@ config PPC
 	select HAVE_ARCH_SECCOMP_FILTER
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ASM_MODVERSIONS
-	select HAVE_CONTEXT_TRACKING		if PPC64
+	select HAVE_CONTEXT_TRACKING_USER		if PPC64
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DEBUG_STACKOVERFLOW
@@ -243,6 +243,7 @@ config PPC
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_RELIABLE_STACKTRACE
 	select HAVE_RSEQ
+	select HAVE_RUST			if PPC64 && CPU_LITTLE_ENDIAN
 	select HAVE_SETUP_PER_CPU_AREA		if PPC64
 	select HAVE_SOFTIRQ_ON_OWN_STACK
 	select HAVE_STACKPROTECTOR		if PPC32 && $(cc-option,-mstack-protector-guard=tls -mstack-protector-guard-reg=r2)
diff --git a/arch/powerpc/include/asm/context_tracking.h b/arch/powerpc/include/asm/context_tracking.h
index f2682b28b050..4b63931c49e0 100644
--- a/arch/powerpc/include/asm/context_tracking.h
+++ b/arch/powerpc/include/asm/context_tracking.h
@@ -2,7 +2,7 @@
 #ifndef _ASM_POWERPC_CONTEXT_TRACKING_H
 #define _ASM_POWERPC_CONTEXT_TRACKING_H
 
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
 #define SCHEDULE_USER bl	schedule_user
 #else
 #define SCHEDULE_USER bl	schedule
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index dd09919c3c66..0822a274a549 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -611,6 +611,7 @@ static inline void check_stack_overflow(void)
 	}
 }
 
+#ifndef CONFIG_PREEMPT_RT
 static __always_inline void call_do_softirq(const void *sp)
 {
 	/* Temporarily switch r1 to sp, call __do_softirq() then restore r1. */
@@ -629,6 +630,7 @@ static __always_inline void call_do_softirq(const void *sp)
 		   "r11", "r12"
 	);
 }
+#endif
 
 static __always_inline void call_do_irq(struct pt_regs *regs, void *sp)
 {
@@ -747,10 +749,12 @@ void *mcheckirq_ctx[NR_CPUS] __read_mostly;
 void *softirq_ctx[NR_CPUS] __read_mostly;
 void *hardirq_ctx[NR_CPUS] __read_mostly;
 
+#ifndef CONFIG_PREEMPT_RT
 void do_softirq_own_stack(void)
 {
 	call_do_softirq(softirq_ctx[smp_processor_id()]);
 }
+#endif
 
 irq_hw_number_t virq_to_hw(unsigned int virq)
 {
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 9f8d0fa7b718..a20deebf233f 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * PowerPC backend to the KGDB stub.
  *
@@ -8,10 +9,6 @@
  * PPC32 support restored by Vitaly Wool <vwool@ru.mvista.com> and
  * Sergei Shtylyov <sshtylyov@ru.mvista.com>
  * Copyright (C) 2007-2008 Wind River Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program as licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index ee0433809621..0fbda89cd1bb 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1855,7 +1855,7 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
 		tm_reclaim_current(0);
 #endif
 
-	memset(regs->gpr, 0, sizeof(regs->gpr));
+	memset(&regs->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
 	regs->ctr = 0;
 	regs->link = 0;
 	regs->xer = 0;
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 04694ec423f6..13d6cb188835 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2302,7 +2302,7 @@ static void __init prom_init_stdout(void)
 
 static int __init prom_find_machine_type(void)
 {
-	char compat[256];
+	static char compat[256] __prombss;
 	int len, i = 0;
 #ifdef CONFIG_PPC64
 	phandle rtas;
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index a6fce3106e02..693133972294 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -1071,7 +1071,7 @@ static struct rtas_filter rtas_filters[] __ro_after_init = {
 	{ "get-time-of-day", -1, -1, -1, -1, -1 },
 	{ "ibm,get-vpd", -1, 0, -1, 1, 2 },
 	{ "ibm,lpar-perftools", -1, 2, 3, -1, -1 },
-	{ "ibm,platform-dump", -1, 4, 5, -1, -1 },
+	{ "ibm,platform-dump", -1, 4, 5, -1, -1 },		/* Special cased */
 	{ "ibm,read-slot-reset-state", -1, -1, -1, -1, -1 },
 	{ "ibm,scan-log-dump", -1, 0, 1, -1, -1 },
 	{ "ibm,set-dynamic-indicator", -1, 2, -1, -1, -1 },
@@ -1120,6 +1120,15 @@ static bool block_rtas_call(int token, int nargs,
 				size = 1;
 
 			end = base + size - 1;
+
+			/*
+			 * Special case for ibm,platform-dump - NULL buffer
+			 * address is used to indicate end of dump processing
+			 */
+			if (!strcmp(f->name, "ibm,platform-dump") &&
+			    base == 0)
+				return false;
+
 			if (!in_rmo_buf(base, end))
 				goto err;
 		}
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index eb0077b302e2..1a02629ec70b 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -935,12 +935,6 @@ void __init setup_arch(char **cmdline_p)
 	/* Print various info about the machine that has been gathered so far. */
 	print_system_info();
 
-	/* Reserve large chunks of memory for use by CMA for KVM. */
-	kvm_cma_reserve();
-
-	/*  Reserve large chunks of memory for us by CMA for hugetlb */
-	gigantic_hugetlb_cma_reserve();
-
 	klp_init_thread_info(&init_task);
 
 	setup_initial_init_mm(_stext, _etext, _edata, _end);
@@ -955,6 +949,13 @@ void __init setup_arch(char **cmdline_p)
 
 	initmem_init();
 
+	/*
+	 * Reserve large chunks of memory for use by CMA for KVM and hugetlb. These must
+	 * be called after initmem_init(), so that pageblock_order is initialised.
+	 */
+	kvm_cma_reserve();
+	gigantic_hugetlb_cma_reserve();
+
 	early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT);
 
 	if (ppc_md.setup_arch)
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 0da287544054..94a8fa5017c3 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -113,18 +113,18 @@ struct vdso_data *arch_get_vdso_data(void *vvar_page)
 int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
 {
 	struct mm_struct *mm = task->mm;
+	VMA_ITERATOR(vmi, mm, 0);
 	struct vm_area_struct *vma;
 
 	mmap_read_lock(mm);
-
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		unsigned long size = vma->vm_end - vma->vm_start;
 
 		if (vma_is_special_mapping(vma, &vvar_spec))
 			zap_page_range(vma, vma->vm_start, size);
 	}
-
 	mmap_read_unlock(mm);
+
 	return 0;
 }
 
diff --git a/arch/powerpc/mm/book3s32/tlb.c b/arch/powerpc/mm/book3s32/tlb.c
index 19f0ef950d77..9ad6b56bfec9 100644
--- a/arch/powerpc/mm/book3s32/tlb.c
+++ b/arch/powerpc/mm/book3s32/tlb.c
@@ -81,14 +81,15 @@ EXPORT_SYMBOL(hash__flush_range);
 void hash__flush_tlb_mm(struct mm_struct *mm)
 {
 	struct vm_area_struct *mp;
+	VMA_ITERATOR(vmi, mm, 0);
 
 	/*
-	 * It is safe to go down the mm's list of vmas when called
-	 * from dup_mmap, holding mmap_lock.  It would also be safe from
-	 * unmap_region or exit_mmap, but not from vmtruncate on SMP -
-	 * but it seems dup_mmap is the only SMP case which gets here.
+	 * It is safe to iterate the vmas when called from dup_mmap,
+	 * holding mmap_lock.  It would also be safe from unmap_region
+	 * or exit_mmap, but not from vmtruncate on SMP - but it seems
+	 * dup_mmap is the only SMP case which gets here.
 	 */
-	for (mp = mm->mmap; mp != NULL; mp = mp->vm_next)
+	for_each_vma(vmi, mp)
 		hash__flush_range(mp->vm_mm, mp->vm_start, mp->vm_end);
 }
 EXPORT_SYMBOL(hash__flush_tlb_mm);
diff --git a/arch/powerpc/mm/book3s64/subpage_prot.c b/arch/powerpc/mm/book3s64/subpage_prot.c
index 60c6ea16a972..d73b3b4176e8 100644
--- a/arch/powerpc/mm/book3s64/subpage_prot.c
+++ b/arch/powerpc/mm/book3s64/subpage_prot.c
@@ -149,24 +149,15 @@ static void subpage_mark_vma_nohuge(struct mm_struct *mm, unsigned long addr,
 				    unsigned long len)
 {
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, addr);
 
 	/*
 	 * We don't try too hard, we just mark all the vma in that range
 	 * VM_NOHUGEPAGE and split them.
 	 */
-	vma = find_vma(mm, addr);
-	/*
-	 * If the range is in unmapped range, just return
-	 */
-	if (vma && ((addr + len) <= vma->vm_start))
-		return;
-
-	while (vma) {
-		if (vma->vm_start >= (addr + len))
-			break;
+	for_each_vma_range(vmi, vma, addr + len) {
 		vma->vm_flags |= VM_NOHUGEPAGE;
 		walk_page_vma(vma, &subpage_walk_ops, NULL);
-		vma = vma->vm_next;
 	}
 }
 #else
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index c1cb21a00884..7c507fb48182 100644
--- a/arch/powerpc/mm/copro_fault.c
+++ b/arch/powerpc/mm/copro_fault.c
@@ -65,6 +65,11 @@ int copro_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
 
 	ret = 0;
 	*flt = handle_mm_fault(vma, ea, is_write ? FAULT_FLAG_WRITE : 0, NULL);
+
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (*flt & VM_FAULT_COMPLETED)
+		return 0;
+
 	if (unlikely(*flt & VM_FAULT_ERROR)) {
 		if (*flt & VM_FAULT_OOM) {
 			ret = -ENOMEM;
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index d53fed4eccbd..014005428687 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -511,6 +511,10 @@ static int ___do_page_fault(struct pt_regs *regs, unsigned long address,
 	if (fault_signal_pending(fault, regs))
 		return user_mode(regs) ? 0 : SIGBUS;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		goto out;
+
 	/*
 	 * Handle the retry right now, the mmap_lock has been released in that
 	 * case.
@@ -525,6 +529,7 @@ static int ___do_page_fault(struct pt_regs *regs, unsigned long address,
 	if (unlikely(fault & VM_FAULT_ERROR))
 		return mm_fault_error(regs, address, fault);
 
+out:
 	/*
 	 * Major/minor page fault accounting.
 	 */
diff --git a/arch/powerpc/platforms/microwatt/microwatt.h b/arch/powerpc/platforms/microwatt/microwatt.h
new file mode 100644
index 000000000000..335417e95e66
--- /dev/null
+++ b/arch/powerpc/platforms/microwatt/microwatt.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MICROWATT_H
+#define _MICROWATT_H
+
+void microwatt_rng_init(void);
+
+#endif /* _MICROWATT_H */
diff --git a/arch/powerpc/platforms/microwatt/rng.c b/arch/powerpc/platforms/microwatt/rng.c
index 7bc4d1cbfaf0..8ece87d005c8 100644
--- a/arch/powerpc/platforms/microwatt/rng.c
+++ b/arch/powerpc/platforms/microwatt/rng.c
@@ -11,6 +11,7 @@
 #include <asm/archrandom.h>
 #include <asm/cputable.h>
 #include <asm/machdep.h>
+#include "microwatt.h"
 
 #define DARN_ERR 0xFFFFFFFFFFFFFFFFul
 
@@ -29,7 +30,7 @@ static int microwatt_get_random_darn(unsigned long *v)
 	return 1;
 }
 
-static __init int rng_init(void)
+void __init microwatt_rng_init(void)
 {
 	unsigned long val;
 	int i;
@@ -37,12 +38,7 @@ static __init int rng_init(void)
 	for (i = 0; i < 10; i++) {
 		if (microwatt_get_random_darn(&val)) {
 			ppc_md.get_random_seed = microwatt_get_random_darn;
-			return 0;
+			return;
 		}
 	}
-
-	pr_warn("Unable to use DARN for get_random_seed()\n");
-
-	return -EIO;
 }
-machine_subsys_initcall(, rng_init);
diff --git a/arch/powerpc/platforms/microwatt/setup.c b/arch/powerpc/platforms/microwatt/setup.c
index 0b02603bdb74..6b32539395a4 100644
--- a/arch/powerpc/platforms/microwatt/setup.c
+++ b/arch/powerpc/platforms/microwatt/setup.c
@@ -16,6 +16,8 @@
 #include <asm/xics.h>
 #include <asm/udbg.h>
 
+#include "microwatt.h"
+
 static void __init microwatt_init_IRQ(void)
 {
 	xics_init();
@@ -32,10 +34,16 @@ static int __init microwatt_populate(void)
 }
 machine_arch_initcall(microwatt, microwatt_populate);
 
+static void __init microwatt_setup_arch(void)
+{
+	microwatt_rng_init();
+}
+
 define_machine(microwatt) {
 	.name			= "microwatt",
 	.probe			= microwatt_probe,
 	.init_IRQ		= microwatt_init_IRQ,
+	.setup_arch		= microwatt_setup_arch,
 	.progress		= udbg_progress,
 	.calibrate_decr		= generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index e297bf4abfcb..866efdc103fd 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -42,4 +42,6 @@ ssize_t memcons_copy(struct memcons *mc, char *to, loff_t pos, size_t count);
 u32 __init memcons_get_size(struct memcons *mc);
 struct memcons *__init memcons_init(struct device_node *node, const char *mc_prop_name);
 
+void pnv_rng_init(void);
+
 #endif /* _POWERNV_H */
diff --git a/arch/powerpc/platforms/powernv/rng.c b/arch/powerpc/platforms/powernv/rng.c
index e3d44b36ae98..463c78c52cc5 100644
--- a/arch/powerpc/platforms/powernv/rng.c
+++ b/arch/powerpc/platforms/powernv/rng.c
@@ -17,6 +17,7 @@
 #include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/smp.h>
+#include "powernv.h"
 
 #define DARN_ERR 0xFFFFFFFFFFFFFFFFul
 
@@ -28,7 +29,6 @@ struct powernv_rng {
 
 static DEFINE_PER_CPU(struct powernv_rng *, powernv_rng);
 
-
 int powernv_hwrng_present(void)
 {
 	struct powernv_rng *rng;
@@ -98,9 +98,6 @@ static int __init initialise_darn(void)
 			return 0;
 		}
 	}
-
-	pr_warn("Unable to use DARN for get_random_seed()\n");
-
 	return -EIO;
 }
 
@@ -163,32 +160,55 @@ static __init int rng_create(struct device_node *dn)
 
 	rng_init_per_cpu(rng, dn);
 
-	pr_info_once("Registering arch random hook.\n");
-
 	ppc_md.get_random_seed = powernv_get_random_long;
 
 	return 0;
 }
 
-static __init int rng_init(void)
+static int __init pnv_get_random_long_early(unsigned long *v)
 {
 	struct device_node *dn;
-	int rc;
+
+	if (!slab_is_available())
+		return 0;
+
+	if (cmpxchg(&ppc_md.get_random_seed, pnv_get_random_long_early,
+		    NULL) != pnv_get_random_long_early)
+		return 0;
 
 	for_each_compatible_node(dn, NULL, "ibm,power-rng") {
-		rc = rng_create(dn);
-		if (rc) {
-			pr_err("Failed creating rng for %pOF (%d).\n",
-				dn, rc);
+		if (rng_create(dn))
 			continue;
-		}
-
 		/* Create devices for hwrng driver */
 		of_platform_device_create(dn, NULL, NULL);
 	}
 
-	initialise_darn();
+	if (!ppc_md.get_random_seed)
+		return 0;
+	return ppc_md.get_random_seed(v);
+}
+
+void __init pnv_rng_init(void)
+{
+	struct device_node *dn;
 
+	/* Prefer darn over the rest. */
+	if (!initialise_darn())
+		return;
+
+	dn = of_find_compatible_node(NULL, NULL, "ibm,power-rng");
+	if (dn)
+		ppc_md.get_random_seed = pnv_get_random_long_early;
+
+	of_node_put(dn);
+}
+
+static int __init pnv_rng_late_init(void)
+{
+	unsigned long v;
+	/* In case it wasn't called during init for some other reason. */
+	if (ppc_md.get_random_seed == pnv_get_random_long_early)
+		pnv_get_random_long_early(&v);
 	return 0;
 }
-machine_subsys_initcall(powernv, rng_init);
+machine_subsys_initcall(powernv, pnv_rng_late_init);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 824c3ad7a0fa..dac545aa0308 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -203,6 +203,8 @@ static void __init pnv_setup_arch(void)
 	pnv_check_guarded_cores();
 
 	/* XXX PMCS */
+
+	pnv_rng_init();
 }
 
 static void __init pnv_init(void)
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c
index 15ed8206c463..5f4037c1d7fe 100644
--- a/arch/powerpc/platforms/pseries/cmm.c
+++ b/arch/powerpc/platforms/pseries/cmm.c
@@ -19,9 +19,6 @@
 #include <linux/stringify.h>
 #include <linux/swap.h>
 #include <linux/device.h>
-#include <linux/mount.h>
-#include <linux/pseudo_fs.h>
-#include <linux/magic.h>
 #include <linux/balloon_compaction.h>
 #include <asm/firmware.h>
 #include <asm/hvcall.h>
@@ -500,19 +497,6 @@ static struct notifier_block cmm_mem_nb = {
 };
 
 #ifdef CONFIG_BALLOON_COMPACTION
-static struct vfsmount *balloon_mnt;
-
-static int cmm_init_fs_context(struct fs_context *fc)
-{
-	return init_pseudo(fc, PPC_CMM_MAGIC) ? 0 : -ENOMEM;
-}
-
-static struct file_system_type balloon_fs = {
-	.name = "ppc-cmm",
-	.init_fs_context = cmm_init_fs_context,
-	.kill_sb = kill_anon_super,
-};
-
 static int cmm_migratepage(struct balloon_dev_info *b_dev_info,
 			   struct page *newpage, struct page *page,
 			   enum migrate_mode mode)
@@ -564,47 +548,13 @@ static int cmm_migratepage(struct balloon_dev_info *b_dev_info,
 	return MIGRATEPAGE_SUCCESS;
 }
 
-static int cmm_balloon_compaction_init(void)
+static void cmm_balloon_compaction_init(void)
 {
-	int rc;
-
 	balloon_devinfo_init(&b_dev_info);
 	b_dev_info.migratepage = cmm_migratepage;
-
-	balloon_mnt = kern_mount(&balloon_fs);
-	if (IS_ERR(balloon_mnt)) {
-		rc = PTR_ERR(balloon_mnt);
-		balloon_mnt = NULL;
-		return rc;
-	}
-
-	b_dev_info.inode = alloc_anon_inode(balloon_mnt->mnt_sb);
-	if (IS_ERR(b_dev_info.inode)) {
-		rc = PTR_ERR(b_dev_info.inode);
-		b_dev_info.inode = NULL;
-		kern_unmount(balloon_mnt);
-		balloon_mnt = NULL;
-		return rc;
-	}
-
-	b_dev_info.inode->i_mapping->a_ops = &balloon_aops;
-	return 0;
-}
-static void cmm_balloon_compaction_deinit(void)
-{
-	if (b_dev_info.inode)
-		iput(b_dev_info.inode);
-	b_dev_info.inode = NULL;
-	kern_unmount(balloon_mnt);
-	balloon_mnt = NULL;
 }
 #else /* CONFIG_BALLOON_COMPACTION */
-static int cmm_balloon_compaction_init(void)
-{
-	return 0;
-}
-
-static void cmm_balloon_compaction_deinit(void)
+static void cmm_balloon_compaction_init(void)
 {
 }
 #endif /* CONFIG_BALLOON_COMPACTION */
@@ -622,9 +572,7 @@ static int cmm_init(void)
 	if (!firmware_has_feature(FW_FEATURE_CMO) && !simulate)
 		return -EOPNOTSUPP;
 
-	rc = cmm_balloon_compaction_init();
-	if (rc)
-		return rc;
+	cmm_balloon_compaction_init();
 
 	rc = register_oom_notifier(&cmm_oom_nb);
 	if (rc < 0)
@@ -658,7 +606,6 @@ static int cmm_init(void)
 out_oom_notifier:
 	unregister_oom_notifier(&cmm_oom_nb);
 out_balloon_compaction:
-	cmm_balloon_compaction_deinit();
 	return rc;
 }
 
@@ -677,7 +624,6 @@ static void cmm_exit(void)
 	unregister_memory_notifier(&cmm_mem_nb);
 	cmm_free_pages(atomic_long_read(&loaned_pages));
 	cmm_unregister_sysfs(&cmm_dev);
-	cmm_balloon_compaction_deinit();
 }
 
 /**
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index f5c916c839c9..1d75b7742ef0 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -122,4 +122,6 @@ void pseries_lpar_read_hblkrm_characteristics(void);
 static inline void pseries_lpar_read_hblkrm_characteristics(void) { }
 #endif
 
+void pseries_rng_init(void);
+
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/rng.c b/arch/powerpc/platforms/pseries/rng.c
index 6268545947b8..6ddfdeaace9e 100644
--- a/arch/powerpc/platforms/pseries/rng.c
+++ b/arch/powerpc/platforms/pseries/rng.c
@@ -10,6 +10,7 @@
 #include <asm/archrandom.h>
 #include <asm/machdep.h>
 #include <asm/plpar_wrappers.h>
+#include "pseries.h"
 
 
 static int pseries_get_random_long(unsigned long *v)
@@ -24,19 +25,13 @@ static int pseries_get_random_long(unsigned long *v)
 	return 0;
 }
 
-static __init int rng_init(void)
+void __init pseries_rng_init(void)
 {
 	struct device_node *dn;
 
 	dn = of_find_compatible_node(NULL, NULL, "ibm,random");
 	if (!dn)
-		return -ENODEV;
-
-	pr_info("Registering arch random hook.\n");
-
+		return;
 	ppc_md.get_random_seed = pseries_get_random_long;
-
 	of_node_put(dn);
-	return 0;
 }
-machine_subsys_initcall(pseries, rng_init);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index afb074269b42..ee4f1db49515 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -839,6 +839,7 @@ static void __init pSeries_setup_arch(void)
 	}
 
 	ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
+	pseries_rng_init();
 }
 
 static void pseries_panic(char *str)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 32ffef9f6e5b..850f6fbb0b5f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -86,7 +86,7 @@ config RISCV
 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 	select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
 	select HAVE_ASM_MODVERSIONS
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
@@ -104,6 +104,7 @@ config RISCV
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_REGS_AND_STACK_ACCESS_API
+	select HAVE_RUST if 64BIT
 	select HAVE_FUNCTION_ARG_ACCESS_API
 	select HAVE_STACKPROTECTOR
 	select HAVE_SYSCALL_TRACEPOINTS
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 34cf8a598617..48b850b7568e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -26,6 +26,8 @@ ifeq ($(CONFIG_ARCH_RV64I),y)
 	KBUILD_CFLAGS += -mabi=lp64
 	KBUILD_AFLAGS += -mabi=lp64
 
+	KBUILD_RUSTFLAGS += -Ctarget-cpu=generic-rv64
+
 	KBUILD_LDFLAGS += -melf64lriscv
 else
 	BITS := 32
@@ -33,6 +35,9 @@ else
 
 	KBUILD_CFLAGS += -mabi=ilp32
 	KBUILD_AFLAGS += -mabi=ilp32
+
+	KBUILD_RUSTFLAGS += -Ctarget-cpu=generic-rv32
+
 	KBUILD_LDFLAGS += -melf32lriscv
 endif
 
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 3095d08453a1..c490d6e4bf1a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -287,7 +287,6 @@ spi0: spi@20108000 {
 			interrupt-parent = <&plic>;
 			interrupts = <54>;
 			clocks = <&clkcfg CLK_SPI0>;
-			spi-max-frequency = <25000000>;
 			status = "disabled";
 		};
 
@@ -299,7 +298,6 @@ spi1: spi@20109000 {
 			interrupt-parent = <&plic>;
 			interrupts = <55>;
 			clocks = <&clkcfg CLK_SPI1>;
-			spi-max-frequency = <25000000>;
 			status = "disabled";
 		};
 
@@ -311,7 +309,6 @@ qspi: spi@21000000 {
 			interrupt-parent = <&plic>;
 			interrupts = <85>;
 			clocks = <&clkcfg CLK_QSPI>;
-			spi-max-frequency = <25000000>;
 			status = "disabled";
 		};
 
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index e5d75270b99c..b37b6fedd53b 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -14,40 +14,26 @@
 #include <asm/patch.h>
 #include <asm/vendorid_list.h>
 
-struct errata_info {
-	char name[ERRATA_STRING_LENGTH_MAX];
-	bool (*check_func)(unsigned long arch_id, unsigned long impid);
-	unsigned int stage;
-};
-
-static bool errata_mt_check_func(unsigned long  arch_id, unsigned long impid)
+static bool errata_probe_pbmt(unsigned int stage,
+			      unsigned long arch_id, unsigned long impid)
 {
 	if (arch_id != 0 || impid != 0)
 		return false;
-	return true;
-}
 
-static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = {
-	{
-		.name = "memory-types",
-		.stage = RISCV_ALTERNATIVES_EARLY_BOOT,
-		.check_func = errata_mt_check_func
-	},
-};
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT ||
+	    stage == RISCV_ALTERNATIVES_MODULE)
+		return true;
+
+	return false;
+}
 
-static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid)
+static u32 thead_errata_probe(unsigned int stage,
+			      unsigned long archid, unsigned long impid)
 {
-	const struct errata_info *info;
 	u32 cpu_req_errata = 0;
-	int idx;
-
-	for (idx = 0; idx < ERRATA_THEAD_NUMBER; idx++) {
-		info = &errata_list[idx];
 
-		if ((stage == RISCV_ALTERNATIVES_MODULE ||
-		     info->stage == stage) && info->check_func(archid, impid))
-			cpu_req_errata |= (1U << idx);
-	}
+	if (errata_probe_pbmt(stage, archid, impid))
+		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);
 
 	return cpu_req_errata;
 }
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 9e2888dbb5b1..416ead0f9a65 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -75,20 +75,20 @@ asm volatile(ALTERNATIVE(						\
 	"nop\n\t"							\
 	"nop\n\t"							\
 	"nop",								\
-	"li      t3, %2\n\t"						\
-	"slli    t3, t3, %4\n\t"					\
+	"li      t3, %1\n\t"						\
+	"slli    t3, t3, %3\n\t"					\
 	"and     t3, %0, t3\n\t"					\
 	"bne     t3, zero, 2f\n\t"					\
-	"li      t3, %3\n\t"						\
-	"slli    t3, t3, %4\n\t"					\
+	"li      t3, %2\n\t"						\
+	"slli    t3, t3, %3\n\t"					\
 	"or      %0, %0, t3\n\t"					\
 	"2:",  THEAD_VENDOR_ID,						\
 		ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
 	: "+r"(_val)							\
-	: "0"(_val),							\
-	  "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
 	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),			\
-	  "I"(ALT_THEAD_PBMT_SHIFT))
+	  "I"(ALT_THEAD_PBMT_SHIFT)					\
+	: "t3")
 #else
 #define ALT_THEAD_PMA(_val)
 #endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4e2486881840..e48eebdd2631 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -12,6 +12,7 @@
 #include <uapi/asm/hwcap.h>
 
 #ifndef __ASSEMBLY__
+#include <linux/jump_label.h>
 /*
  * This yields a mask that user programs can use to figure out what
  * instruction set this cpu supports.
@@ -56,6 +57,16 @@ enum riscv_isa_ext_id {
 	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
 };
 
+/*
+ * This enum represents the logical ID for each RISC-V ISA extension static
+ * keys. We can use static key to optimize code path if some ISA extensions
+ * are available.
+ */
+enum riscv_isa_ext_key {
+	RISCV_ISA_EXT_KEY_FPU,		/* For 'F' and 'D' */
+	RISCV_ISA_EXT_KEY_MAX,
+};
+
 struct riscv_isa_ext_data {
 	/* Name of the extension displayed to userspace via /proc/cpuinfo */
 	char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
@@ -63,6 +74,20 @@ struct riscv_isa_ext_data {
 	unsigned int isa_ext_id;
 };
 
+extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
+
+static __always_inline int riscv_isa_ext2key(int num)
+{
+	switch (num) {
+	case RISCV_ISA_EXT_f:
+		return RISCV_ISA_EXT_KEY_FPU;
+	case RISCV_ISA_EXT_d:
+		return RISCV_ISA_EXT_KEY_FPU;
+	default:
+		return -EINVAL;
+	}
+}
+
 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
 
 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h
index 7fd52a30e605..830ac621dbbc 100644
--- a/arch/riscv/include/asm/pci.h
+++ b/arch/riscv/include/asm/pci.h
@@ -12,8 +12,8 @@
 
 #include <asm/io.h>
 
-#define PCIBIOS_MIN_IO		0
-#define PCIBIOS_MIN_MEM		0
+#define PCIBIOS_MIN_IO		4
+#define PCIBIOS_MIN_MEM		16
 
 /* RISC-V shim does not initialize PCI bus */
 #define pcibios_assign_all_busses() 1
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 0a3f4f95c555..11463489fec6 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -8,6 +8,7 @@
 
 #include <linux/jump_label.h>
 #include <linux/sched/task_stack.h>
+#include <asm/hwcap.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/csr.h>
@@ -56,10 +57,9 @@ static inline void __switch_to_aux(struct task_struct *prev,
 	fstate_restore(next, task_pt_regs(next));
 }
 
-extern struct static_key_false cpu_hwcap_fpu;
 static __always_inline bool has_fpu(void)
 {
-	return static_branch_likely(&cpu_hwcap_fpu);
+	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
 }
 #else
 static __always_inline bool has_fpu(void) { return false; }
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index c9d0d3c53223..a7d26a00beea 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -20,7 +20,7 @@ struct cpu_manufacturer_info_t {
 	unsigned long vendor_id;
 	unsigned long arch_id;
 	unsigned long imp_id;
-	void (*vendor_patch_func)(struct alt_entry *begin, struct alt_entry *end,
+	void (*patch_func)(struct alt_entry *begin, struct alt_entry *end,
 				  unsigned long archid, unsigned long impid,
 				  unsigned int stage);
 };
@@ -40,16 +40,16 @@ static void __init_or_module riscv_fill_cpu_mfr_info(struct cpu_manufacturer_inf
 	switch (cpu_mfr_info->vendor_id) {
 #ifdef CONFIG_ERRATA_SIFIVE
 	case SIFIVE_VENDOR_ID:
-		cpu_mfr_info->vendor_patch_func = sifive_errata_patch_func;
+		cpu_mfr_info->patch_func = sifive_errata_patch_func;
 		break;
 #endif
 #ifdef CONFIG_ERRATA_THEAD
 	case THEAD_VENDOR_ID:
-		cpu_mfr_info->vendor_patch_func = thead_errata_patch_func;
+		cpu_mfr_info->patch_func = thead_errata_patch_func;
 		break;
 #endif
 	default:
-		cpu_mfr_info->vendor_patch_func = NULL;
+		cpu_mfr_info->patch_func = NULL;
 	}
 }
 
@@ -68,13 +68,13 @@ static void __init_or_module _apply_alternatives(struct alt_entry *begin,
 
 	riscv_cpufeature_patch_func(begin, end, stage);
 
-	if (!cpu_mfr_info.vendor_patch_func)
+	if (!cpu_mfr_info.patch_func)
 		return;
 
-	cpu_mfr_info.vendor_patch_func(begin, end,
-				   cpu_mfr_info.arch_id,
-				   cpu_mfr_info.imp_id,
-				   stage);
+	cpu_mfr_info.patch_func(begin, end,
+				cpu_mfr_info.arch_id,
+				cpu_mfr_info.imp_id,
+				stage);
 }
 
 void __init apply_boot_alternatives(void)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 12b05ce164bb..1b3ec44e25f5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -27,9 +27,8 @@ unsigned long elf_hwcap __read_mostly;
 /* Host ISA bitmap */
 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 
-#ifdef CONFIG_FPU
-__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
-#endif
+__ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
+EXPORT_SYMBOL(riscv_isa_ext_keys);
 
 /**
  * riscv_isa_extension_base() - Get base extension word
@@ -238,19 +237,15 @@ void __init riscv_fill_hwcap(void)
 			print_str[j++] = (char)('a' + i);
 	pr_info("riscv: ELF capabilities %s\n", print_str);
 
-#ifdef CONFIG_FPU
-	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
-		static_branch_enable(&cpu_hwcap_fpu);
-#endif
+	for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
+		j = riscv_isa_ext2key(i);
+		if (j >= 0)
+			static_branch_enable(&riscv_isa_ext_keys[j]);
+	}
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE
-struct cpufeature_info {
-	char name[ERRATA_STRING_LENGTH_MAX];
-	bool (*check_func)(unsigned int stage);
-};
-
-static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
+static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
 {
 #ifdef CONFIG_RISCV_ISA_SVPBMT
 	switch (stage) {
@@ -264,26 +259,19 @@ static bool __init_or_module cpufeature_svpbmt_check_func(unsigned int stage)
 	return false;
 }
 
-static const struct cpufeature_info __initdata_or_module
-cpufeature_list[CPUFEATURE_NUMBER] = {
-	{
-		.name = "svpbmt",
-		.check_func = cpufeature_svpbmt_check_func
-	},
-};
-
+/*
+ * Probe presence of individual extensions.
+ *
+ * This code may also be executed before kernel relocation, so we cannot use
+ * addresses generated by the address-of operator as they won't be valid in
+ * this context.
+ */
 static u32 __init_or_module cpufeature_probe(unsigned int stage)
 {
-	const struct cpufeature_info *info;
 	u32 cpu_req_feature = 0;
-	int idx;
 
-	for (idx = 0; idx < CPUFEATURE_NUMBER; idx++) {
-		info = &cpufeature_list[idx];
-
-		if (info->check_func(stage))
-			cpu_req_feature |= (1U << idx);
-	}
+	if (cpufeature_probe_svpbmt(stage))
+		cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
 
 	return cpu_req_feature;
 }
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 2e5b88ca11ce..b9eda3fcbd6d 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -111,12 +111,12 @@ _save_context:
 	call __trace_hardirqs_off
 #endif
 
-#ifdef CONFIG_CONTEXT_TRACKING
-	/* If previous state is in user mode, call context_tracking_user_exit. */
+#ifdef CONFIG_CONTEXT_TRACKING_USER
+	/* If previous state is in user mode, call user_exit_callable(). */
 	li   a0, SR_PP
 	and a0, s1, a0
 	bnez a0, skip_context_tracking
-	call context_tracking_user_exit
+	call user_exit_callable
 skip_context_tracking:
 #endif
 
@@ -176,7 +176,7 @@ handle_syscall:
 	 */
 	csrs CSR_STATUS, SR_IE
 #endif
-#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
+#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING_USER)
 	/* Recover a0 - a7 for system calls */
 	REG_L a0, PT_A0(sp)
 	REG_L a1, PT_A1(sp)
@@ -269,8 +269,8 @@ resume_userspace:
 	andi s1, s0, _TIF_WORK_MASK
 	bnez s1, work_pending
 
-#ifdef CONFIG_CONTEXT_TRACKING
-	call context_tracking_user_enter
+#ifdef CONFIG_CONTEXT_TRACKING_USER
+	call user_enter_callable
 #endif
 
 	/* Save unwound kernel stack pointer in thread_info */
diff --git a/arch/riscv/kernel/vdso.c b/arch/riscv/kernel/vdso.c
index 69b05b6c181b..692e7ae3dcb8 100644
--- a/arch/riscv/kernel/vdso.c
+++ b/arch/riscv/kernel/vdso.c
@@ -114,11 +114,12 @@ int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
 {
 	struct mm_struct *mm = task->mm;
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 	struct __vdso_info *vdso_info = mm->context.vdso_info;
 
 	mmap_read_lock(mm);
 
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		unsigned long size = vma->vm_end - vma->vm_start;
 
 		if (vma_is_special_mapping(vma, vdso_info->dm))
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index 40694f0cab9e..f2fbd1400b7c 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -326,6 +326,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_RETRY)) {
 		flags |= FAULT_FLAG_TRIED;
 
diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index 2a3715bf29fe..d926e0f7ef57 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -69,6 +69,7 @@ struct rv_jit_context {
 	struct bpf_prog *prog;
 	u16 *insns;		/* RV insns */
 	int ninsns;
+	int body_len;
 	int epilogue_offset;
 	int *offset;		/* BPF to RV */
 	int nexentries;
diff --git a/arch/riscv/net/bpf_jit_core.c b/arch/riscv/net/bpf_jit_core.c
index be743d700aa7..737baf8715da 100644
--- a/arch/riscv/net/bpf_jit_core.c
+++ b/arch/riscv/net/bpf_jit_core.c
@@ -44,7 +44,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
 	unsigned int prog_size = 0, extable_size = 0;
 	bool tmp_blinded = false, extra_pass = false;
 	struct bpf_prog *tmp, *orig_prog = prog;
-	int pass = 0, prev_ninsns = 0, i;
+	int pass = 0, prev_ninsns = 0, prologue_len, i;
 	struct rv_jit_data *jit_data;
 	struct rv_jit_context *ctx;
 
@@ -95,6 +95,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
 			prog = orig_prog;
 			goto out_offset;
 		}
+		ctx->body_len = ctx->ninsns;
 		bpf_jit_build_prologue(ctx);
 		ctx->epilogue_offset = ctx->ninsns;
 		bpf_jit_build_epilogue(ctx);
@@ -161,6 +162,11 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
 
 	if (!prog->is_func || extra_pass) {
 		bpf_jit_binary_lock_ro(jit_data->header);
+		prologue_len = ctx->epilogue_offset - ctx->body_len;
+		for (i = 0; i < prog->len; i++)
+			ctx->offset[i] = ninsns_rvoff(prologue_len +
+						      ctx->offset[i]);
+		bpf_prog_fill_jited_linfo(prog, ctx->offset);
 out_offset:
 		kfree(ctx->offset);
 		kfree(jit_data);
diff --git a/arch/s390/boot/uv.c b/arch/s390/boot/uv.c
index e6be155ab2e5..67c737c1e580 100644
--- a/arch/s390/boot/uv.c
+++ b/arch/s390/boot/uv.c
@@ -41,6 +41,10 @@ void uv_query_info(void)
 		uv_info.max_num_sec_conf = uvcb.max_num_sec_conf;
 		uv_info.max_guest_cpu_id = uvcb.max_guest_cpu_id;
 		uv_info.uv_feature_indications = uvcb.uv_feature_indications;
+		uv_info.supp_se_hdr_ver = uvcb.supp_se_hdr_versions;
+		uv_info.supp_se_hdr_pcf = uvcb.supp_se_hdr_pcf;
+		uv_info.conf_dump_storage_state_len = uvcb.conf_dump_storage_state_len;
+		uv_info.conf_dump_finalize_len = uvcb.conf_dump_finalize_len;
 	}
 
 #ifdef CONFIG_PROTECTED_VIRTUALIZATION_GUEST
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 766028d54a3e..a0fbe4820e0a 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -923,6 +923,7 @@ struct kvm_s390_pv {
 	u64 guest_len;
 	unsigned long stor_base;
 	void *stor_var;
+	bool dumping;
 };
 
 struct kvm_arch{
diff --git a/arch/s390/include/asm/softirq_stack.h b/arch/s390/include/asm/softirq_stack.h
index fd17f25704bd..af68d6c1d584 100644
--- a/arch/s390/include/asm/softirq_stack.h
+++ b/arch/s390/include/asm/softirq_stack.h
@@ -5,9 +5,10 @@
 #include <asm/lowcore.h>
 #include <asm/stacktrace.h>
 
+#ifndef CONFIG_PREEMPT_RT
 static inline void do_softirq_own_stack(void)
 {
 	call_on_stack(0, S390_lowcore.async_stack, void, __do_softirq);
 }
-
+#endif
 #endif /* __ASM_S390_SOFTIRQ_STACK_H */
diff --git a/arch/s390/include/asm/uv.h b/arch/s390/include/asm/uv.h
index cfea7b77a5b8..3e597bb634bd 100644
--- a/arch/s390/include/asm/uv.h
+++ b/arch/s390/include/asm/uv.h
@@ -50,6 +50,10 @@
 #define UVC_CMD_SET_UNSHARE_ALL		0x0340
 #define UVC_CMD_PIN_PAGE_SHARED		0x0341
 #define UVC_CMD_UNPIN_PAGE_SHARED	0x0342
+#define UVC_CMD_DUMP_INIT		0x0400
+#define UVC_CMD_DUMP_CONF_STOR_STATE	0x0401
+#define UVC_CMD_DUMP_CPU		0x0402
+#define UVC_CMD_DUMP_COMPLETE		0x0403
 #define UVC_CMD_SET_SHARED_ACCESS	0x1000
 #define UVC_CMD_REMOVE_SHARED_ACCESS	0x1001
 #define UVC_CMD_RETR_ATTEST		0x1020
@@ -77,6 +81,10 @@ enum uv_cmds_inst {
 	BIT_UVC_CMD_UNSHARE_ALL = 20,
 	BIT_UVC_CMD_PIN_PAGE_SHARED = 21,
 	BIT_UVC_CMD_UNPIN_PAGE_SHARED = 22,
+	BIT_UVC_CMD_DUMP_INIT = 24,
+	BIT_UVC_CMD_DUMP_CONFIG_STOR_STATE = 25,
+	BIT_UVC_CMD_DUMP_CPU = 26,
+	BIT_UVC_CMD_DUMP_COMPLETE = 27,
 	BIT_UVC_CMD_RETR_ATTEST = 28,
 };
 
@@ -110,7 +118,13 @@ struct uv_cb_qui {
 	u8  reserved88[158 - 136];		/* 0x0088 */
 	u16 max_guest_cpu_id;			/* 0x009e */
 	u64 uv_feature_indications;		/* 0x00a0 */
-	u8  reserveda8[200 - 168];		/* 0x00a8 */
+	u64 reserveda8;				/* 0x00a8 */
+	u64 supp_se_hdr_versions;		/* 0x00b0 */
+	u64 supp_se_hdr_pcf;			/* 0x00b8 */
+	u64 reservedc0;				/* 0x00c0 */
+	u64 conf_dump_storage_state_len;	/* 0x00c8 */
+	u64 conf_dump_finalize_len;		/* 0x00d0 */
+	u8  reservedd8[256 - 216];		/* 0x00d8 */
 } __packed __aligned(8);
 
 /* Initialize Ultravisor */
@@ -240,6 +254,31 @@ struct uv_cb_attest {
 	u64 reserved168[4];		/* 0x0168 */
 } __packed __aligned(8);
 
+struct uv_cb_dump_cpu {
+	struct uv_cb_header header;
+	u64 reserved08[2];
+	u64 cpu_handle;
+	u64 dump_area_origin;
+	u64 reserved28[5];
+} __packed __aligned(8);
+
+struct uv_cb_dump_stor_state {
+	struct uv_cb_header header;
+	u64 reserved08[2];
+	u64 config_handle;
+	u64 dump_area_origin;
+	u64 gaddr;
+	u64 reserved28[4];
+} __packed __aligned(8);
+
+struct uv_cb_dump_complete {
+	struct uv_cb_header header;
+	u64 reserved08[2];
+	u64 config_handle;
+	u64 dump_area_origin;
+	u64 reserved30[5];
+} __packed __aligned(8);
+
 static inline int __uv_call(unsigned long r1, unsigned long r2)
 {
 	int cc;
@@ -307,6 +346,10 @@ struct uv_info {
 	unsigned int max_num_sec_conf;
 	unsigned short max_guest_cpu_id;
 	unsigned long uv_feature_indications;
+	unsigned long supp_se_hdr_ver;
+	unsigned long supp_se_hdr_pcf;
+	unsigned long conf_dump_storage_state_len;
+	unsigned long conf_dump_finalize_len;
 };
 
 extern struct uv_info uv_info;
diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c
index a5425075dd25..84fe33b6af4d 100644
--- a/arch/s390/kernel/uv.c
+++ b/arch/s390/kernel/uv.c
@@ -392,6 +392,54 @@ static ssize_t uv_query_facilities(struct kobject *kobj,
 static struct kobj_attribute uv_query_facilities_attr =
 	__ATTR(facilities, 0444, uv_query_facilities, NULL);
 
+static ssize_t uv_query_supp_se_hdr_ver(struct kobject *kobj,
+					struct kobj_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%lx\n", uv_info.supp_se_hdr_ver);
+}
+
+static struct kobj_attribute uv_query_supp_se_hdr_ver_attr =
+	__ATTR(supp_se_hdr_ver, 0444, uv_query_supp_se_hdr_ver, NULL);
+
+static ssize_t uv_query_supp_se_hdr_pcf(struct kobject *kobj,
+					struct kobj_attribute *attr, char *buf)
+{
+	return sysfs_emit(buf, "%lx\n", uv_info.supp_se_hdr_pcf);
+}
+
+static struct kobj_attribute uv_query_supp_se_hdr_pcf_attr =
+	__ATTR(supp_se_hdr_pcf, 0444, uv_query_supp_se_hdr_pcf, NULL);
+
+static ssize_t uv_query_dump_cpu_len(struct kobject *kobj,
+				     struct kobj_attribute *attr, char *page)
+{
+	return scnprintf(page, PAGE_SIZE, "%lx\n",
+			uv_info.guest_cpu_stor_len);
+}
+
+static struct kobj_attribute uv_query_dump_cpu_len_attr =
+	__ATTR(uv_query_dump_cpu_len, 0444, uv_query_dump_cpu_len, NULL);
+
+static ssize_t uv_query_dump_storage_state_len(struct kobject *kobj,
+					       struct kobj_attribute *attr, char *page)
+{
+	return scnprintf(page, PAGE_SIZE, "%lx\n",
+			uv_info.conf_dump_storage_state_len);
+}
+
+static struct kobj_attribute uv_query_dump_storage_state_len_attr =
+	__ATTR(dump_storage_state_len, 0444, uv_query_dump_storage_state_len, NULL);
+
+static ssize_t uv_query_dump_finalize_len(struct kobject *kobj,
+					  struct kobj_attribute *attr, char *page)
+{
+	return scnprintf(page, PAGE_SIZE, "%lx\n",
+			uv_info.conf_dump_finalize_len);
+}
+
+static struct kobj_attribute uv_query_dump_finalize_len_attr =
+	__ATTR(dump_finalize_len, 0444, uv_query_dump_finalize_len, NULL);
+
 static ssize_t uv_query_feature_indications(struct kobject *kobj,
 					    struct kobj_attribute *attr, char *buf)
 {
@@ -437,6 +485,11 @@ static struct attribute *uv_query_attrs[] = {
 	&uv_query_max_guest_cpus_attr.attr,
 	&uv_query_max_guest_vms_attr.attr,
 	&uv_query_max_guest_addr_attr.attr,
+	&uv_query_supp_se_hdr_ver_attr.attr,
+	&uv_query_supp_se_hdr_pcf_attr.attr,
+	&uv_query_dump_storage_state_len_attr.attr,
+	&uv_query_dump_finalize_len_attr.attr,
+	&uv_query_dump_cpu_len_attr.attr,
 	NULL,
 };
 
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index 5075cde77b29..535099f2736d 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -69,10 +69,11 @@ static struct page *find_timens_vvar_page(struct vm_area_struct *vma)
 int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
 {
 	struct mm_struct *mm = task->mm;
+	VMA_ITERATOR(vmi, mm, 0);
 	struct vm_area_struct *vma;
 
 	mmap_read_lock(mm);
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		unsigned long size = vma->vm_end - vma->vm_start;
 
 		if (!vma_is_special_mapping(vma, &vvar_mapping))
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 8fcb56141689..72bd5c9b9617 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -606,6 +606,26 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 	case KVM_CAP_S390_PROTECTED:
 		r = is_prot_virt_host();
 		break;
+	case KVM_CAP_S390_PROTECTED_DUMP: {
+		u64 pv_cmds_dump[] = {
+			BIT_UVC_CMD_DUMP_INIT,
+			BIT_UVC_CMD_DUMP_CONFIG_STOR_STATE,
+			BIT_UVC_CMD_DUMP_CPU,
+			BIT_UVC_CMD_DUMP_COMPLETE,
+		};
+		int i;
+
+		r = is_prot_virt_host();
+
+		for (i = 0; i < ARRAY_SIZE(pv_cmds_dump); i++) {
+			if (!test_bit_inv(pv_cmds_dump[i],
+					  (unsigned long *)&uv_info.inst_calls_list)) {
+				r = 0;
+				break;
+			}
+		}
+		break;
+	}
 	default:
 		r = 0;
 	}
@@ -2220,6 +2240,115 @@ static int kvm_s390_cpus_to_pv(struct kvm *kvm, u16 *rc, u16 *rrc)
 	return r;
 }
 
+/*
+ * Here we provide user space with a direct interface to query UV
+ * related data like UV maxima and available features as well as
+ * feature specific data.
+ *
+ * To facilitate future extension of the data structures we'll try to
+ * write data up to the maximum requested length.
+ */
+static ssize_t kvm_s390_handle_pv_info(struct kvm_s390_pv_info *info)
+{
+	ssize_t len_min;
+
+	switch (info->header.id) {
+	case KVM_PV_INFO_VM: {
+		len_min =  sizeof(info->header) + sizeof(info->vm);
+
+		if (info->header.len_max < len_min)
+			return -EINVAL;
+
+		memcpy(info->vm.inst_calls_list,
+		       uv_info.inst_calls_list,
+		       sizeof(uv_info.inst_calls_list));
+
+		/* It's max cpuid not max cpus, so it's off by one */
+		info->vm.max_cpus = uv_info.max_guest_cpu_id + 1;
+		info->vm.max_guests = uv_info.max_num_sec_conf;
+		info->vm.max_guest_addr = uv_info.max_sec_stor_addr;
+		info->vm.feature_indication = uv_info.uv_feature_indications;
+
+		return len_min;
+	}
+	case KVM_PV_INFO_DUMP: {
+		len_min =  sizeof(info->header) + sizeof(info->dump);
+
+		if (info->header.len_max < len_min)
+			return -EINVAL;
+
+		info->dump.dump_cpu_buffer_len = uv_info.guest_cpu_stor_len;
+		info->dump.dump_config_mem_buffer_per_1m = uv_info.conf_dump_storage_state_len;
+		info->dump.dump_config_finalize_len = uv_info.conf_dump_finalize_len;
+		return len_min;
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
+static int kvm_s390_pv_dmp(struct kvm *kvm, struct kvm_pv_cmd *cmd,
+			   struct kvm_s390_pv_dmp dmp)
+{
+	int r = -EINVAL;
+	void __user *result_buff = (void __user *)dmp.buff_addr;
+
+	switch (dmp.subcmd) {
+	case KVM_PV_DUMP_INIT: {
+		if (kvm->arch.pv.dumping)
+			break;
+
+		/*
+		 * Block SIE entry as concurrent dump UVCs could lead
+		 * to validities.
+		 */
+		kvm_s390_vcpu_block_all(kvm);
+
+		r = uv_cmd_nodata(kvm_s390_pv_get_handle(kvm),
+				  UVC_CMD_DUMP_INIT, &cmd->rc, &cmd->rrc);
+		KVM_UV_EVENT(kvm, 3, "PROTVIRT DUMP INIT: rc %x rrc %x",
+			     cmd->rc, cmd->rrc);
+		if (!r) {
+			kvm->arch.pv.dumping = true;
+		} else {
+			kvm_s390_vcpu_unblock_all(kvm);
+			r = -EINVAL;
+		}
+		break;
+	}
+	case KVM_PV_DUMP_CONFIG_STOR_STATE: {
+		if (!kvm->arch.pv.dumping)
+			break;
+
+		/*
+		 * gaddr is an output parameter since we might stop
+		 * early. As dmp will be copied back in our caller, we
+		 * don't need to do it ourselves.
+		 */
+		r = kvm_s390_pv_dump_stor_state(kvm, result_buff, &dmp.gaddr, dmp.buff_len,
+						&cmd->rc, &cmd->rrc);
+		break;
+	}
+	case KVM_PV_DUMP_COMPLETE: {
+		if (!kvm->arch.pv.dumping)
+			break;
+
+		r = -EINVAL;
+		if (dmp.buff_len < uv_info.conf_dump_finalize_len)
+			break;
+
+		r = kvm_s390_pv_dump_complete(kvm, result_buff,
+					      &cmd->rc, &cmd->rrc);
+		break;
+	}
+	default:
+		r = -ENOTTY;
+		break;
+	}
+
+	return r;
+}
+
 static int kvm_s390_handle_pv(struct kvm *kvm, struct kvm_pv_cmd *cmd)
 {
 	int r = 0;
@@ -2356,6 +2485,68 @@ static int kvm_s390_handle_pv(struct kvm *kvm, struct kvm_pv_cmd *cmd)
 			     cmd->rc, cmd->rrc);
 		break;
 	}
+	case KVM_PV_INFO: {
+		struct kvm_s390_pv_info info = {};
+		ssize_t data_len;
+
+		/*
+		 * No need to check the VM protection here.
+		 *
+		 * Maybe user space wants to query some of the data
+		 * when the VM is still unprotected. If we see the
+		 * need to fence a new data command we can still
+		 * return an error in the info handler.
+		 */
+
+		r = -EFAULT;
+		if (copy_from_user(&info, argp, sizeof(info.header)))
+			break;
+
+		r = -EINVAL;
+		if (info.header.len_max < sizeof(info.header))
+			break;
+
+		data_len = kvm_s390_handle_pv_info(&info);
+		if (data_len < 0) {
+			r = data_len;
+			break;
+		}
+		/*
+		 * If a data command struct is extended (multiple
+		 * times) this can be used to determine how much of it
+		 * is valid.
+		 */
+		info.header.len_written = data_len;
+
+		r = -EFAULT;
+		if (copy_to_user(argp, &info, data_len))
+			break;
+
+		r = 0;
+		break;
+	}
+	case KVM_PV_DUMP: {
+		struct kvm_s390_pv_dmp dmp;
+
+		r = -EINVAL;
+		if (!kvm_s390_pv_is_protected(kvm))
+			break;
+
+		r = -EFAULT;
+		if (copy_from_user(&dmp, argp, sizeof(dmp)))
+			break;
+
+		r = kvm_s390_pv_dmp(kvm, cmd, dmp);
+		if (r)
+			break;
+
+		if (copy_to_user(argp, &dmp, sizeof(dmp))) {
+			r = -EFAULT;
+			break;
+		}
+
+		break;
+	}
 	default:
 		r = -ENOTTY;
 	}
@@ -3047,9 +3238,7 @@ static int sca_can_add_vcpu(struct kvm *kvm, unsigned int id)
 	if (!sclp.has_esca || !sclp.has_64bscao)
 		return false;
 
-	mutex_lock(&kvm->lock);
 	rc = kvm->arch.use_esca ? 0 : sca_switch_to_extended(kvm);
-	mutex_unlock(&kvm->lock);
 
 	return rc == 0 && id < KVM_S390_ESCA_CPU_SLOTS;
 }
@@ -4473,6 +4662,15 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
 	struct kvm_run *kvm_run = vcpu->run;
 	int rc;
 
+	/*
+	 * Running a VM while dumping always has the potential to
+	 * produce inconsistent dump data. But for PV vcpus a SIE
+	 * entry while dumping could also lead to a fatal validity
+	 * intercept which we absolutely want to avoid.
+	 */
+	if (vcpu->kvm->arch.pv.dumping)
+		return -EINVAL;
+
 	if (kvm_run->immediate_exit)
 		return -EINTR;
 
@@ -4912,6 +5110,48 @@ long kvm_arch_vcpu_async_ioctl(struct file *filp,
 	return -ENOIOCTLCMD;
 }
 
+static int kvm_s390_handle_pv_vcpu_dump(struct kvm_vcpu *vcpu,
+					struct kvm_pv_cmd *cmd)
+{
+	struct kvm_s390_pv_dmp dmp;
+	void *data;
+	int ret;
+
+	/* Dump initialization is a prerequisite */
+	if (!vcpu->kvm->arch.pv.dumping)
+		return -EINVAL;
+
+	if (copy_from_user(&dmp, (__u8 __user *)cmd->data, sizeof(dmp)))
+		return -EFAULT;
+
+	/* We only handle this subcmd right now */
+	if (dmp.subcmd != KVM_PV_DUMP_CPU)
+		return -EINVAL;
+
+	/* CPU dump length is the same as create cpu storage donation. */
+	if (dmp.buff_len != uv_info.guest_cpu_stor_len)
+		return -EINVAL;
+
+	data = kvzalloc(uv_info.guest_cpu_stor_len, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = kvm_s390_pv_dump_cpu(vcpu, data, &cmd->rc, &cmd->rrc);
+
+	VCPU_EVENT(vcpu, 3, "PROTVIRT DUMP CPU %d rc %x rrc %x",
+		   vcpu->vcpu_id, cmd->rc, cmd->rrc);
+
+	if (ret)
+		ret = -EINVAL;
+
+	/* On success copy over the dump data */
+	if (!ret && copy_to_user((__u8 __user *)dmp.buff_addr, data, uv_info.guest_cpu_stor_len))
+		ret = -EFAULT;
+
+	kvfree(data);
+	return ret;
+}
+
 long kvm_arch_vcpu_ioctl(struct file *filp,
 			 unsigned int ioctl, unsigned long arg)
 {
@@ -5076,6 +5316,33 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 					   irq_state.len);
 		break;
 	}
+	case KVM_S390_PV_CPU_COMMAND: {
+		struct kvm_pv_cmd cmd;
+
+		r = -EINVAL;
+		if (!is_prot_virt_host())
+			break;
+
+		r = -EFAULT;
+		if (copy_from_user(&cmd, argp, sizeof(cmd)))
+			break;
+
+		r = -EINVAL;
+		if (cmd.flags)
+			break;
+
+		/* We only handle this cmd right now */
+		if (cmd.cmd != KVM_PV_DUMP)
+			break;
+
+		r = kvm_s390_handle_pv_vcpu_dump(vcpu, &cmd);
+
+		/* Always copy over UV rc / rrc data */
+		if (copy_to_user((__u8 __user *)argp, &cmd.rc,
+				 sizeof(cmd.rc) + sizeof(cmd.rrc)))
+			r = -EFAULT;
+		break;
+	}
 	default:
 		r = -ENOTTY;
 	}
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 497d52a83c78..dd01d989816f 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -250,6 +250,11 @@ int kvm_s390_pv_set_sec_parms(struct kvm *kvm, void *hdr, u64 length, u16 *rc,
 int kvm_s390_pv_unpack(struct kvm *kvm, unsigned long addr, unsigned long size,
 		       unsigned long tweak, u16 *rc, u16 *rrc);
 int kvm_s390_pv_set_cpu_state(struct kvm_vcpu *vcpu, u8 state);
+int kvm_s390_pv_dump_cpu(struct kvm_vcpu *vcpu, void *buff, u16 *rc, u16 *rrc);
+int kvm_s390_pv_dump_stor_state(struct kvm *kvm, void __user *buff_user,
+				u64 *gaddr, u64 buff_user_len, u16 *rc, u16 *rrc);
+int kvm_s390_pv_dump_complete(struct kvm *kvm, void __user *buff_user,
+			      u16 *rc, u16 *rrc);
 
 static inline u64 kvm_s390_pv_get_handle(struct kvm *kvm)
 {
diff --git a/arch/s390/kvm/pv.c b/arch/s390/kvm/pv.c
index cc7c9599f43e..b4a499b10b67 100644
--- a/arch/s390/kvm/pv.c
+++ b/arch/s390/kvm/pv.c
@@ -7,6 +7,7 @@
  */
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
+#include <linux/minmax.h>
 #include <linux/pagemap.h>
 #include <linux/sched/signal.h>
 #include <asm/gmap.h>
@@ -298,3 +299,200 @@ int kvm_s390_pv_set_cpu_state(struct kvm_vcpu *vcpu, u8 state)
 		return -EINVAL;
 	return 0;
 }
+
+int kvm_s390_pv_dump_cpu(struct kvm_vcpu *vcpu, void *buff, u16 *rc, u16 *rrc)
+{
+	struct uv_cb_dump_cpu uvcb = {
+		.header.cmd = UVC_CMD_DUMP_CPU,
+		.header.len = sizeof(uvcb),
+		.cpu_handle = vcpu->arch.pv.handle,
+		.dump_area_origin = (u64)buff,
+	};
+	int cc;
+
+	cc = uv_call_sched(0, (u64)&uvcb);
+	*rc = uvcb.header.rc;
+	*rrc = uvcb.header.rrc;
+	return cc;
+}
+
+/* Size of the cache for the storage state dump data. 1MB for now */
+#define DUMP_BUFF_LEN HPAGE_SIZE
+
+/**
+ * kvm_s390_pv_dump_stor_state
+ *
+ * @kvm: pointer to the guest's KVM struct
+ * @buff_user: Userspace pointer where we will write the results to
+ * @gaddr: Starting absolute guest address for which the storage state
+ *	   is requested.
+ * @buff_user_len: Length of the buff_user buffer
+ * @rc: Pointer to where the uvcb return code is stored
+ * @rrc: Pointer to where the uvcb return reason code is stored
+ *
+ * Stores buff_len bytes of tweak component values to buff_user
+ * starting with the 1MB block specified by the absolute guest address
+ * (gaddr). The gaddr pointer will be updated with the last address
+ * for which data was written when returning to userspace. buff_user
+ * might be written to even if an error rc is returned. For instance
+ * if we encounter a fault after writing the first page of data.
+ *
+ * Context: kvm->lock needs to be held
+ *
+ * Return:
+ *  0 on success
+ *  -ENOMEM if allocating the cache fails
+ *  -EINVAL if gaddr is not aligned to 1MB
+ *  -EINVAL if buff_user_len is not aligned to uv_info.conf_dump_storage_state_len
+ *  -EINVAL if the UV call fails, rc and rrc will be set in this case
+ *  -EFAULT if copying the result to buff_user failed
+ */
+int kvm_s390_pv_dump_stor_state(struct kvm *kvm, void __user *buff_user,
+				u64 *gaddr, u64 buff_user_len, u16 *rc, u16 *rrc)
+{
+	struct uv_cb_dump_stor_state uvcb = {
+		.header.cmd = UVC_CMD_DUMP_CONF_STOR_STATE,
+		.header.len = sizeof(uvcb),
+		.config_handle = kvm->arch.pv.handle,
+		.gaddr = *gaddr,
+		.dump_area_origin = 0,
+	};
+	const u64 increment_len = uv_info.conf_dump_storage_state_len;
+	size_t buff_kvm_size;
+	size_t size_done = 0;
+	u8 *buff_kvm = NULL;
+	int cc, ret;
+
+	ret = -EINVAL;
+	/* UV call processes 1MB guest storage chunks at a time */
+	if (!IS_ALIGNED(*gaddr, HPAGE_SIZE))
+		goto out;
+
+	/*
+	 * We provide the storage state for 1MB chunks of guest
+	 * storage. The buffer will need to be aligned to
+	 * conf_dump_storage_state_len so we don't end on a partial
+	 * chunk.
+	 */
+	if (!buff_user_len ||
+	    !IS_ALIGNED(buff_user_len, increment_len))
+		goto out;
+
+	/*
+	 * Allocate a buffer from which we will later copy to the user
+	 * process. We don't want userspace to dictate our buffer size
+	 * so we limit it to DUMP_BUFF_LEN.
+	 */
+	ret = -ENOMEM;
+	buff_kvm_size = min_t(u64, buff_user_len, DUMP_BUFF_LEN);
+	buff_kvm = vzalloc(buff_kvm_size);
+	if (!buff_kvm)
+		goto out;
+
+	ret = 0;
+	uvcb.dump_area_origin = (u64)buff_kvm;
+	/* We will loop until the user buffer is filled or an error occurs */
+	do {
+		/* Get 1MB worth of guest storage state data */
+		cc = uv_call_sched(0, (u64)&uvcb);
+
+		/* All or nothing */
+		if (cc) {
+			ret = -EINVAL;
+			break;
+		}
+
+		size_done += increment_len;
+		uvcb.dump_area_origin += increment_len;
+		buff_user_len -= increment_len;
+		uvcb.gaddr += HPAGE_SIZE;
+
+		/* KVM Buffer full, time to copy to the process */
+		if (!buff_user_len || size_done == DUMP_BUFF_LEN) {
+			if (copy_to_user(buff_user, buff_kvm, size_done)) {
+				ret = -EFAULT;
+				break;
+			}
+
+			buff_user += size_done;
+			size_done = 0;
+			uvcb.dump_area_origin = (u64)buff_kvm;
+		}
+	} while (buff_user_len);
+
+	/* Report back where we ended dumping */
+	*gaddr = uvcb.gaddr;
+
+	/* Lets only log errors, we don't want to spam */
+out:
+	if (ret)
+		KVM_UV_EVENT(kvm, 3,
+			     "PROTVIRT DUMP STORAGE STATE: addr %llx ret %d, uvcb rc %x rrc %x",
+			     uvcb.gaddr, ret, uvcb.header.rc, uvcb.header.rrc);
+	*rc = uvcb.header.rc;
+	*rrc = uvcb.header.rrc;
+	vfree(buff_kvm);
+
+	return ret;
+}
+
+/**
+ * kvm_s390_pv_dump_complete
+ *
+ * @kvm: pointer to the guest's KVM struct
+ * @buff_user: Userspace pointer where we will write the results to
+ * @rc: Pointer to where the uvcb return code is stored
+ * @rrc: Pointer to where the uvcb return reason code is stored
+ *
+ * Completes the dumping operation and writes the completion data to
+ * user space.
+ *
+ * Context: kvm->lock needs to be held
+ *
+ * Return:
+ *  0 on success
+ *  -ENOMEM if allocating the completion buffer fails
+ *  -EINVAL if the UV call fails, rc and rrc will be set in this case
+ *  -EFAULT if copying the result to buff_user failed
+ */
+int kvm_s390_pv_dump_complete(struct kvm *kvm, void __user *buff_user,
+			      u16 *rc, u16 *rrc)
+{
+	struct uv_cb_dump_complete complete = {
+		.header.len = sizeof(complete),
+		.header.cmd = UVC_CMD_DUMP_COMPLETE,
+		.config_handle = kvm_s390_pv_get_handle(kvm),
+	};
+	u64 *compl_data;
+	int ret;
+
+	/* Allocate dump area */
+	compl_data = vzalloc(uv_info.conf_dump_finalize_len);
+	if (!compl_data)
+		return -ENOMEM;
+	complete.dump_area_origin = (u64)compl_data;
+
+	ret = uv_call_sched(0, (u64)&complete);
+	*rc = complete.header.rc;
+	*rrc = complete.header.rrc;
+	KVM_UV_EVENT(kvm, 3, "PROTVIRT DUMP COMPLETE: rc %x rrc %x",
+		     complete.header.rc, complete.header.rrc);
+
+	if (!ret) {
+		/*
+		 * kvm_s390_pv_dealloc_vm() will also (mem)set
+		 * this to false on a reboot or other destroy
+		 * operation for this vm.
+		 */
+		kvm->arch.pv.dumping = false;
+		kvm_s390_vcpu_unblock_all(kvm);
+		ret = copy_to_user(buff_user, compl_data, uv_info.conf_dump_finalize_len);
+		if (ret)
+			ret = -EFAULT;
+	}
+	vfree(compl_data);
+	/* If the UVC returned an error, translate it to -EINVAL */
+	if (ret > 0)
+		ret = -EINVAL;
+	return ret;
+}
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index e173b6187ad5..973dcd05c293 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -433,6 +433,17 @@ static inline vm_fault_t do_exception(struct pt_regs *regs, int access)
 			goto out_up;
 		goto out;
 	}
+
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED) {
+		if (gmap) {
+			mmap_read_lock(mm);
+			goto out_gmap;
+		}
+		fault = 0;
+		goto out;
+	}
+
 	if (unlikely(fault & VM_FAULT_ERROR))
 		goto out_up;
 
@@ -452,6 +463,7 @@ static inline vm_fault_t do_exception(struct pt_regs *regs, int access)
 		mmap_read_lock(mm);
 		goto retry;
 	}
+out_gmap:
 	if (IS_ENABLED(CONFIG_PGSTE) && gmap) {
 		address =  __gmap_link(gmap, current->thread.gmap_addr,
 				       address);
diff --git a/arch/s390/mm/gmap.c b/arch/s390/mm/gmap.c
index b8ae4a4aa2ba..6e24f337eac0 100644
--- a/arch/s390/mm/gmap.c
+++ b/arch/s390/mm/gmap.c
@@ -2515,8 +2515,9 @@ static const struct mm_walk_ops thp_split_walk_ops = {
 static inline void thp_split_mm(struct mm_struct *mm)
 {
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
-	for (vma = mm->mmap; vma != NULL; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		vma->vm_flags &= ~VM_HUGEPAGE;
 		vma->vm_flags |= VM_NOHUGEPAGE;
 		walk_page_vma(vma, &thp_split_walk_ops, NULL);
@@ -2584,8 +2585,9 @@ int gmap_mark_unmergeable(void)
 	struct mm_struct *mm = current->mm;
 	struct vm_area_struct *vma;
 	int ret;
+	VMA_ITERATOR(vmi, mm, 0);
 
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		ret = ksm_madvise(vma, vma->vm_start, vma->vm_end,
 				  MADV_UNMERGEABLE, &vma->vm_flags);
 		if (ret)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index cf9a3ec32406..fba90e670ed4 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -271,8 +271,12 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
 #endif /* CONFIG_HAVE_IOREMAP_PROT */
 
 #else /* CONFIG_MMU */
-#define iounmap(addr)		do { } while (0)
-#define ioremap(offset, size)	((void __iomem *)(unsigned long)(offset))
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
+{
+	return (void __iomem *)(unsigned long)offset;
+}
+
+static inline void iounmap(volatile void __iomem *addr) { }
 #endif /* CONFIG_MMU */
 
 #define ioremap_uc	ioremap
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index ef0f0827cf57..2d3eca8fee01 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -149,6 +149,7 @@ void irq_ctx_exit(int cpu)
 	hardirq_ctx[cpu] = NULL;
 }
 
+#ifndef CONFIG_PREEMPT_RT
 void do_softirq_own_stack(void)
 {
 	struct thread_info *curctx;
@@ -176,6 +177,7 @@ void do_softirq_own_stack(void)
 		  "r5", "r6", "r7", "r8", "r9", "r15", "t", "pr"
 	);
 }
+#endif
 #else
 static inline void handle_one_irq(unsigned int irq)
 {
diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c
index e175667b1363..acd2f5e50bfc 100644
--- a/arch/sh/mm/fault.c
+++ b/arch/sh/mm/fault.c
@@ -485,6 +485,10 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
 		if (mm_fault_error(regs, error_code, address, fault))
 			return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (fault & VM_FAULT_RETRY) {
 		flags |= FAULT_FLAG_TRIED;
 
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index ba449c47effd..9232411a8821 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -71,7 +71,7 @@ config SPARC64
 	select HAVE_DYNAMIC_FTRACE
 	select HAVE_FTRACE_MCOUNT_RECORD
 	select HAVE_SYSCALL_TRACEPOINTS
-	select HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER
 	select HAVE_TIF_NOHZ
 	select HAVE_DEBUG_KMEMLEAK
 	select IOMMU_HELPER
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index c8848bb681a1..41fa1be980a3 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -855,6 +855,7 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs)
 	set_irq_regs(old_regs);
 }
 
+#ifndef CONFIG_PREEMPT_RT
 void do_softirq_own_stack(void)
 {
 	void *orig_sp, *sp = softirq_stack[smp_processor_id()];
@@ -869,6 +870,7 @@ void do_softirq_own_stack(void)
 	__asm__ __volatile__("mov %0, %%sp"
 			     : : "r" (orig_sp));
 }
+#endif
 
 #ifdef CONFIG_HOTPLUG_CPU
 void fixup_irqs(void)
diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S
index c5fd4b450d9b..eef102765a7e 100644
--- a/arch/sparc/kernel/rtrap_64.S
+++ b/arch/sparc/kernel/rtrap_64.S
@@ -15,7 +15,7 @@
 #include <asm/visasm.h>
 #include <asm/processor.h>
 
-#ifdef CONFIG_CONTEXT_TRACKING
+#ifdef CONFIG_CONTEXT_TRACKING_USER
 # define SCHEDULE_USER schedule_user
 #else
 # define SCHEDULE_USER schedule
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index ad569d9bd124..91259f291c54 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -190,6 +190,10 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
 	if (fault_signal_pending(fault, regs))
 		return;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index 253e07043298..4acc12eafbf5 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -427,6 +427,10 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
 	if (fault_signal_pending(fault, regs))
 		goto exit_exception;
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		goto lock_released;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
@@ -449,6 +453,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
 	}
 	mmap_read_unlock(mm);
 
+lock_released:
 	mm_rss = get_mm_rss(mm);
 #if defined(CONFIG_TRANSPARENT_HUGEPAGE)
 	mm_rss -= (mm->context.thp_pte_count * (HPAGE_SIZE / PAGE_SIZE));
diff --git a/arch/sparc/vdso/vdso2c.c b/arch/sparc/vdso/vdso2c.c
index ab7504176a7f..dc81240aab6f 100644
--- a/arch/sparc/vdso/vdso2c.c
+++ b/arch/sparc/vdso/vdso2c.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * vdso2c - A vdso image preparation tool
  * Copyright (c) 2014 Andy Lutomirski and others
- * Licensed under the GPL v2
  *
  * vdso2c requires stripped and unstripped input.  It would be trivial
  * to fully strip the input in here, but, for reasons described below,
diff --git a/arch/um/Kconfig b/arch/um/Kconfig
index 4ec22e156a2e..6dc06a7bf8b7 100644
--- a/arch/um/Kconfig
+++ b/arch/um/Kconfig
@@ -25,6 +25,7 @@ config UML
 	select TRACE_IRQFLAGS_SUPPORT
 	select TTY # Needed for line.c
 	select HAVE_ARCH_VMAP_STACK
+	select HAVE_RUST			if X86_64
 
 config MMU
 	bool
diff --git a/arch/um/kernel/tlb.c b/arch/um/kernel/tlb.c
index bc38f79ca3a3..ad449173a1a1 100644
--- a/arch/um/kernel/tlb.c
+++ b/arch/um/kernel/tlb.c
@@ -584,21 +584,19 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
 
 void flush_tlb_mm(struct mm_struct *mm)
 {
-	struct vm_area_struct *vma = mm->mmap;
+	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
-	while (vma != NULL) {
+	for_each_vma(vmi, vma)
 		fix_range(mm, vma->vm_start, vma->vm_end, 0);
-		vma = vma->vm_next;
-	}
 }
 
 void force_flush_all(void)
 {
 	struct mm_struct *mm = current->mm;
-	struct vm_area_struct *vma = mm->mmap;
+	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
-	while (vma != NULL) {
+	for_each_vma(vmi, vma)
 		fix_range(mm, vma->vm_start, vma->vm_end, 1);
-		vma = vma->vm_next;
-	}
 }
diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c
index d1d5d0be0308..d3ce21c4ca32 100644
--- a/arch/um/kernel/trap.c
+++ b/arch/um/kernel/trap.c
@@ -76,6 +76,10 @@ int handle_page_fault(unsigned long address, unsigned long ip,
 		if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
 			goto out_nosemaphore;
 
+		/* The fault is fully completed (including releasing mmap lock) */
+		if (fault & VM_FAULT_COMPLETED)
+			return 0;
+
 		if (unlikely(fault & VM_FAULT_ERROR)) {
 			if (fault & VM_FAULT_OOM) {
 				goto out_of_memory;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index be0b95e51df6..abe751626a35 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -186,8 +186,8 @@ config X86
 	select HAVE_ASM_MODVERSIONS
 	select HAVE_CMPXCHG_DOUBLE
 	select HAVE_CMPXCHG_LOCAL
-	select HAVE_CONTEXT_TRACKING		if X86_64
-	select HAVE_CONTEXT_TRACKING_OFFSTACK	if HAVE_CONTEXT_TRACKING
+	select HAVE_CONTEXT_TRACKING_USER		if X86_64
+	select HAVE_CONTEXT_TRACKING_USER_OFFSTACK	if HAVE_CONTEXT_TRACKING_USER
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_OBJTOOL_MCOUNT		if HAVE_OBJTOOL
 	select HAVE_BUILDTIME_MCOUNT_SORT
@@ -257,6 +257,7 @@ config X86
 	select HAVE_STATIC_CALL_INLINE		if HAVE_OBJTOOL
 	select HAVE_PREEMPT_DYNAMIC_CALL
 	select HAVE_RSEQ
+	select HAVE_RUST			if X86_64
 	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_UACCESS_VALIDATION		if HAVE_OBJTOOL
 	select HAVE_UNSTABLE_SCHED_CLOCK
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index a74886aed349..23f44a0db356 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -21,6 +21,8 @@ ifdef CONFIG_CC_IS_CLANG
 RETPOLINE_CFLAGS	:= -mretpoline-external-thunk
 RETPOLINE_VDSO_CFLAGS	:= -mretpoline
 endif
+RETPOLINE_RUSTFLAGS	:= -Ctarget-feature=+retpoline-external-thunk
+
 export RETPOLINE_CFLAGS
 export RETPOLINE_VDSO_CFLAGS
 
@@ -61,6 +63,8 @@ export BITS
 #    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383
 #
 KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
+KBUILD_RUSTFLAGS += -Ctarget-feature=-mmx,-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2
+KBUILD_RUSTFLAGS += -Ctarget-feature=-3dnow,-3dnowa,-avx,-avx2,+soft-float
 
 ifeq ($(CONFIG_X86_KERNEL_IBT),y)
 #
@@ -148,8 +152,17 @@ else
         cflags-$(CONFIG_GENERIC_CPU)	+= -mtune=generic
         KBUILD_CFLAGS += $(cflags-y)
 
+        rustflags-$(CONFIG_MK8)		+= -Ctarget-cpu=k8
+        rustflags-$(CONFIG_MPSC)	+= -Ctarget-cpu=nocona
+        rustflags-$(CONFIG_MCORE2)	+= -Ctarget-cpu=core2
+        rustflags-$(CONFIG_MATOM)	+= -Ctarget-cpu=atom
+        rustflags-$(CONFIG_GENERIC_CPU)	+= -Ztune-cpu=generic
+        KBUILD_RUSTFLAGS += $(rustflags-y)
+
         KBUILD_CFLAGS += -mno-red-zone
         KBUILD_CFLAGS += -mcmodel=kernel
+        KBUILD_RUSTFLAGS += -Cno-redzone=y
+        KBUILD_RUSTFLAGS += -Ccode-model=kernel
 endif
 
 #
@@ -185,6 +198,7 @@ ifdef CONFIG_RETPOLINE
   ifndef CONFIG_CC_IS_CLANG
     KBUILD_CFLAGS += -fno-jump-tables
   endif
+  KBUILD_RUSTFLAGS += $(RETPOLINE_RUSTFLAGS)
 endif
 
 ifdef CONFIG_SLS
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 2831685adf6f..04d07ab744b2 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -61,14 +61,15 @@ sha256-ssse3-$(CONFIG_AS_SHA256_NI) += sha256_ni_asm.o
 obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o
 sha512-ssse3-y := sha512-ssse3-asm.o sha512-avx-asm.o sha512-avx2-asm.o sha512_ssse3_glue.o
 
-obj-$(CONFIG_CRYPTO_BLAKE2S_X86) += blake2s-x86_64.o
-blake2s-x86_64-y := blake2s-shash.o
-obj-$(if $(CONFIG_CRYPTO_BLAKE2S_X86),y) += libblake2s-x86_64.o
+obj-$(CONFIG_CRYPTO_BLAKE2S_X86) += libblake2s-x86_64.o
 libblake2s-x86_64-y := blake2s-core.o blake2s-glue.o
 
 obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
 
+obj-$(CONFIG_CRYPTO_POLYVAL_CLMUL_NI) += polyval-clmulni.o
+polyval-clmulni-y := polyval-clmulni_asm.o polyval-clmulni_glue.o
+
 obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
 crc32c-intel-y := crc32c-intel_glue.o
 crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
diff --git a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
index 43852ba6e19c..2402b9418cd7 100644
--- a/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
+++ b/arch/x86/crypto/aes_ctrby8_avx-x86_64.S
@@ -23,6 +23,11 @@
 
 #define VMOVDQ		vmovdqu
 
+/*
+ * Note: the "x" prefix in these aliases means "this is an xmm register".  The
+ * alias prefixes have no relation to XCTR where the "X" prefix means "XOR
+ * counter".
+ */
 #define xdata0		%xmm0
 #define xdata1		%xmm1
 #define xdata2		%xmm2
@@ -31,8 +36,10 @@
 #define xdata5		%xmm5
 #define xdata6		%xmm6
 #define xdata7		%xmm7
-#define xcounter	%xmm8
-#define xbyteswap	%xmm9
+#define xcounter	%xmm8	// CTR mode only
+#define xiv		%xmm8	// XCTR mode only
+#define xbyteswap	%xmm9	// CTR mode only
+#define xtmp		%xmm9	// XCTR mode only
 #define xkey0		%xmm10
 #define xkey4		%xmm11
 #define xkey8		%xmm12
@@ -45,7 +52,7 @@
 #define p_keys		%rdx
 #define p_out		%rcx
 #define num_bytes	%r8
-
+#define counter		%r9	// XCTR mode only
 #define tmp		%r10
 #define	DDQ_DATA	0
 #define	XDATA		1
@@ -102,7 +109,7 @@ ddq_add_8:
  * do_aes num_in_par load_keys key_len
  * This increments p_in, but not p_out
  */
-.macro do_aes b, k, key_len
+.macro do_aes b, k, key_len, xctr
 	.set by, \b
 	.set load_keys, \k
 	.set klen, \key_len
@@ -111,29 +118,48 @@ ddq_add_8:
 		vmovdqa	0*16(p_keys), xkey0
 	.endif
 
-	vpshufb	xbyteswap, xcounter, xdata0
-
-	.set i, 1
-	.rept (by - 1)
-		club XDATA, i
-		vpaddq	(ddq_add_1 + 16 * (i - 1))(%rip), xcounter, var_xdata
-		vptest	ddq_low_msk(%rip), var_xdata
-		jnz 1f
-		vpaddq	ddq_high_add_1(%rip), var_xdata, var_xdata
-		vpaddq	ddq_high_add_1(%rip), xcounter, xcounter
-		1:
-		vpshufb	xbyteswap, var_xdata, var_xdata
-		.set i, (i +1)
-	.endr
+	.if \xctr
+		movq counter, xtmp
+		.set i, 0
+		.rept (by)
+			club XDATA, i
+			vpaddq	(ddq_add_1 + 16 * i)(%rip), xtmp, var_xdata
+			.set i, (i +1)
+		.endr
+		.set i, 0
+		.rept (by)
+			club	XDATA, i
+			vpxor	xiv, var_xdata, var_xdata
+			.set i, (i +1)
+		.endr
+	.else
+		vpshufb	xbyteswap, xcounter, xdata0
+		.set i, 1
+		.rept (by - 1)
+			club XDATA, i
+			vpaddq	(ddq_add_1 + 16 * (i - 1))(%rip), xcounter, var_xdata
+			vptest	ddq_low_msk(%rip), var_xdata
+			jnz 1f
+			vpaddq	ddq_high_add_1(%rip), var_xdata, var_xdata
+			vpaddq	ddq_high_add_1(%rip), xcounter, xcounter
+			1:
+			vpshufb	xbyteswap, var_xdata, var_xdata
+			.set i, (i +1)
+		.endr
+	.endif
 
 	vmovdqa	1*16(p_keys), xkeyA
 
 	vpxor	xkey0, xdata0, xdata0
-	vpaddq	(ddq_add_1 + 16 * (by - 1))(%rip), xcounter, xcounter
-	vptest	ddq_low_msk(%rip), xcounter
-	jnz	1f
-	vpaddq	ddq_high_add_1(%rip), xcounter, xcounter
-	1:
+	.if \xctr
+		add $by, counter
+	.else
+		vpaddq	(ddq_add_1 + 16 * (by - 1))(%rip), xcounter, xcounter
+		vptest	ddq_low_msk(%rip), xcounter
+		jnz	1f
+		vpaddq	ddq_high_add_1(%rip), xcounter, xcounter
+		1:
+	.endif
 
 	.set i, 1
 	.rept (by - 1)
@@ -371,94 +397,99 @@ ddq_add_8:
 	.endr
 .endm
 
-.macro do_aes_load val, key_len
-	do_aes \val, 1, \key_len
+.macro do_aes_load val, key_len, xctr
+	do_aes \val, 1, \key_len, \xctr
 .endm
 
-.macro do_aes_noload val, key_len
-	do_aes \val, 0, \key_len
+.macro do_aes_noload val, key_len, xctr
+	do_aes \val, 0, \key_len, \xctr
 .endm
 
 /* main body of aes ctr load */
 
-.macro do_aes_ctrmain key_len
+.macro do_aes_ctrmain key_len, xctr
 	cmp	$16, num_bytes
-	jb	.Ldo_return2\key_len
+	jb	.Ldo_return2\xctr\key_len
 
-	vmovdqa	byteswap_const(%rip), xbyteswap
-	vmovdqu	(p_iv), xcounter
-	vpshufb	xbyteswap, xcounter, xcounter
+	.if \xctr
+		shr	$4, counter
+		vmovdqu	(p_iv), xiv
+	.else
+		vmovdqa	byteswap_const(%rip), xbyteswap
+		vmovdqu	(p_iv), xcounter
+		vpshufb	xbyteswap, xcounter, xcounter
+	.endif
 
 	mov	num_bytes, tmp
 	and	$(7*16), tmp
-	jz	.Lmult_of_8_blks\key_len
+	jz	.Lmult_of_8_blks\xctr\key_len
 
 	/* 1 <= tmp <= 7 */
 	cmp	$(4*16), tmp
-	jg	.Lgt4\key_len
-	je	.Leq4\key_len
+	jg	.Lgt4\xctr\key_len
+	je	.Leq4\xctr\key_len
 
-.Llt4\key_len:
+.Llt4\xctr\key_len:
 	cmp	$(2*16), tmp
-	jg	.Leq3\key_len
-	je	.Leq2\key_len
+	jg	.Leq3\xctr\key_len
+	je	.Leq2\xctr\key_len
 
-.Leq1\key_len:
-	do_aes_load	1, \key_len
+.Leq1\xctr\key_len:
+	do_aes_load	1, \key_len, \xctr
 	add	$(1*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Leq2\key_len:
-	do_aes_load	2, \key_len
+.Leq2\xctr\key_len:
+	do_aes_load	2, \key_len, \xctr
 	add	$(2*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
 
-.Leq3\key_len:
-	do_aes_load	3, \key_len
+.Leq3\xctr\key_len:
+	do_aes_load	3, \key_len, \xctr
 	add	$(3*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Leq4\key_len:
-	do_aes_load	4, \key_len
+.Leq4\xctr\key_len:
+	do_aes_load	4, \key_len, \xctr
 	add	$(4*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Lgt4\key_len:
+.Lgt4\xctr\key_len:
 	cmp	$(6*16), tmp
-	jg	.Leq7\key_len
-	je	.Leq6\key_len
+	jg	.Leq7\xctr\key_len
+	je	.Leq6\xctr\key_len
 
-.Leq5\key_len:
-	do_aes_load	5, \key_len
+.Leq5\xctr\key_len:
+	do_aes_load	5, \key_len, \xctr
 	add	$(5*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Leq6\key_len:
-	do_aes_load	6, \key_len
+.Leq6\xctr\key_len:
+	do_aes_load	6, \key_len, \xctr
 	add	$(6*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Leq7\key_len:
-	do_aes_load	7, \key_len
+.Leq7\xctr\key_len:
+	do_aes_load	7, \key_len, \xctr
 	add	$(7*16), p_out
 	and	$(~7*16), num_bytes
-	jz	.Ldo_return2\key_len
-	jmp	.Lmain_loop2\key_len
+	jz	.Ldo_return2\xctr\key_len
+	jmp	.Lmain_loop2\xctr\key_len
 
-.Lmult_of_8_blks\key_len:
+.Lmult_of_8_blks\xctr\key_len:
 	.if (\key_len != KEY_128)
 		vmovdqa	0*16(p_keys), xkey0
 		vmovdqa	4*16(p_keys), xkey4
@@ -471,17 +502,19 @@ ddq_add_8:
 		vmovdqa	9*16(p_keys), xkey12
 	.endif
 .align 16
-.Lmain_loop2\key_len:
+.Lmain_loop2\xctr\key_len:
 	/* num_bytes is a multiple of 8 and >0 */
-	do_aes_noload	8, \key_len
+	do_aes_noload	8, \key_len, \xctr
 	add	$(8*16), p_out
 	sub	$(8*16), num_bytes
-	jne	.Lmain_loop2\key_len
+	jne	.Lmain_loop2\xctr\key_len
 
-.Ldo_return2\key_len:
-	/* return updated IV */
-	vpshufb	xbyteswap, xcounter, xcounter
-	vmovdqu	xcounter, (p_iv)
+.Ldo_return2\xctr\key_len:
+	.if !\xctr
+		/* return updated IV */
+		vpshufb	xbyteswap, xcounter, xcounter
+		vmovdqu	xcounter, (p_iv)
+	.endif
 	RET
 .endm
 
@@ -494,7 +527,7 @@ ddq_add_8:
  */
 SYM_FUNC_START(aes_ctr_enc_128_avx_by8)
 	/* call the aes main loop */
-	do_aes_ctrmain KEY_128
+	do_aes_ctrmain KEY_128 0
 
 SYM_FUNC_END(aes_ctr_enc_128_avx_by8)
 
@@ -507,7 +540,7 @@ SYM_FUNC_END(aes_ctr_enc_128_avx_by8)
  */
 SYM_FUNC_START(aes_ctr_enc_192_avx_by8)
 	/* call the aes main loop */
-	do_aes_ctrmain KEY_192
+	do_aes_ctrmain KEY_192 0
 
 SYM_FUNC_END(aes_ctr_enc_192_avx_by8)
 
@@ -520,6 +553,45 @@ SYM_FUNC_END(aes_ctr_enc_192_avx_by8)
  */
 SYM_FUNC_START(aes_ctr_enc_256_avx_by8)
 	/* call the aes main loop */
-	do_aes_ctrmain KEY_256
+	do_aes_ctrmain KEY_256 0
 
 SYM_FUNC_END(aes_ctr_enc_256_avx_by8)
+
+/*
+ * routine to do AES128 XCTR enc/decrypt "by8"
+ * XMM registers are clobbered.
+ * Saving/restoring must be done at a higher level
+ * aes_xctr_enc_128_avx_by8(const u8 *in, const u8 *iv, const void *keys,
+ * 	u8* out, unsigned int num_bytes, unsigned int byte_ctr)
+ */
+SYM_FUNC_START(aes_xctr_enc_128_avx_by8)
+	/* call the aes main loop */
+	do_aes_ctrmain KEY_128 1
+
+SYM_FUNC_END(aes_xctr_enc_128_avx_by8)
+
+/*
+ * routine to do AES192 XCTR enc/decrypt "by8"
+ * XMM registers are clobbered.
+ * Saving/restoring must be done at a higher level
+ * aes_xctr_enc_192_avx_by8(const u8 *in, const u8 *iv, const void *keys,
+ * 	u8* out, unsigned int num_bytes, unsigned int byte_ctr)
+ */
+SYM_FUNC_START(aes_xctr_enc_192_avx_by8)
+	/* call the aes main loop */
+	do_aes_ctrmain KEY_192 1
+
+SYM_FUNC_END(aes_xctr_enc_192_avx_by8)
+
+/*
+ * routine to do AES256 XCTR enc/decrypt "by8"
+ * XMM registers are clobbered.
+ * Saving/restoring must be done at a higher level
+ * aes_xctr_enc_256_avx_by8(const u8 *in, const u8 *iv, const void *keys,
+ * 	u8* out, unsigned int num_bytes, unsigned int byte_ctr)
+ */
+SYM_FUNC_START(aes_xctr_enc_256_avx_by8)
+	/* call the aes main loop */
+	do_aes_ctrmain KEY_256 1
+
+SYM_FUNC_END(aes_xctr_enc_256_avx_by8)
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index 41901ba9d3a2..a5b0cb3efeba 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -135,6 +135,20 @@ asmlinkage void aes_ctr_enc_192_avx_by8(const u8 *in, u8 *iv,
 		void *keys, u8 *out, unsigned int num_bytes);
 asmlinkage void aes_ctr_enc_256_avx_by8(const u8 *in, u8 *iv,
 		void *keys, u8 *out, unsigned int num_bytes);
+
+
+asmlinkage void aes_xctr_enc_128_avx_by8(const u8 *in, const u8 *iv,
+	const void *keys, u8 *out, unsigned int num_bytes,
+	unsigned int byte_ctr);
+
+asmlinkage void aes_xctr_enc_192_avx_by8(const u8 *in, const u8 *iv,
+	const void *keys, u8 *out, unsigned int num_bytes,
+	unsigned int byte_ctr);
+
+asmlinkage void aes_xctr_enc_256_avx_by8(const u8 *in, const u8 *iv,
+	const void *keys, u8 *out, unsigned int num_bytes,
+	unsigned int byte_ctr);
+
 /*
  * asmlinkage void aesni_gcm_init_avx_gen2()
  * gcm_data *my_ctx_data, context data
@@ -527,6 +541,59 @@ static int ctr_crypt(struct skcipher_request *req)
 	return err;
 }
 
+static void aesni_xctr_enc_avx_tfm(struct crypto_aes_ctx *ctx, u8 *out,
+				   const u8 *in, unsigned int len, u8 *iv,
+				   unsigned int byte_ctr)
+{
+	if (ctx->key_length == AES_KEYSIZE_128)
+		aes_xctr_enc_128_avx_by8(in, iv, (void *)ctx, out, len,
+					 byte_ctr);
+	else if (ctx->key_length == AES_KEYSIZE_192)
+		aes_xctr_enc_192_avx_by8(in, iv, (void *)ctx, out, len,
+					 byte_ctr);
+	else
+		aes_xctr_enc_256_avx_by8(in, iv, (void *)ctx, out, len,
+					 byte_ctr);
+}
+
+static int xctr_crypt(struct skcipher_request *req)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	struct crypto_aes_ctx *ctx = aes_ctx(crypto_skcipher_ctx(tfm));
+	u8 keystream[AES_BLOCK_SIZE];
+	struct skcipher_walk walk;
+	unsigned int nbytes;
+	unsigned int byte_ctr = 0;
+	int err;
+	__le32 block[AES_BLOCK_SIZE / sizeof(__le32)];
+
+	err = skcipher_walk_virt(&walk, req, false);
+
+	while ((nbytes = walk.nbytes) > 0) {
+		kernel_fpu_begin();
+		if (nbytes & AES_BLOCK_MASK)
+			aesni_xctr_enc_avx_tfm(ctx, walk.dst.virt.addr,
+				walk.src.virt.addr, nbytes & AES_BLOCK_MASK,
+				walk.iv, byte_ctr);
+		nbytes &= ~AES_BLOCK_MASK;
+		byte_ctr += walk.nbytes - nbytes;
+
+		if (walk.nbytes == walk.total && nbytes > 0) {
+			memcpy(block, walk.iv, AES_BLOCK_SIZE);
+			block[0] ^= cpu_to_le32(1 + byte_ctr / AES_BLOCK_SIZE);
+			aesni_enc(ctx, keystream, (u8 *)block);
+			crypto_xor_cpy(walk.dst.virt.addr + walk.nbytes -
+				       nbytes, walk.src.virt.addr + walk.nbytes
+				       - nbytes, keystream, nbytes);
+			byte_ctr += nbytes;
+			nbytes = 0;
+		}
+		kernel_fpu_end();
+		err = skcipher_walk_done(&walk, nbytes);
+	}
+	return err;
+}
+
 static int
 rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
 {
@@ -1050,6 +1117,33 @@ static struct skcipher_alg aesni_skciphers[] = {
 static
 struct simd_skcipher_alg *aesni_simd_skciphers[ARRAY_SIZE(aesni_skciphers)];
 
+#ifdef CONFIG_X86_64
+/*
+ * XCTR does not have a non-AVX implementation, so it must be enabled
+ * conditionally.
+ */
+static struct skcipher_alg aesni_xctr = {
+	.base = {
+		.cra_name		= "__xctr(aes)",
+		.cra_driver_name	= "__xctr-aes-aesni",
+		.cra_priority		= 400,
+		.cra_flags		= CRYPTO_ALG_INTERNAL,
+		.cra_blocksize		= 1,
+		.cra_ctxsize		= CRYPTO_AES_CTX_SIZE,
+		.cra_module		= THIS_MODULE,
+	},
+	.min_keysize	= AES_MIN_KEY_SIZE,
+	.max_keysize	= AES_MAX_KEY_SIZE,
+	.ivsize		= AES_BLOCK_SIZE,
+	.chunksize	= AES_BLOCK_SIZE,
+	.setkey		= aesni_skcipher_setkey,
+	.encrypt	= xctr_crypt,
+	.decrypt	= xctr_crypt,
+};
+
+static struct simd_skcipher_alg *aesni_simd_xctr;
+#endif /* CONFIG_X86_64 */
+
 #ifdef CONFIG_X86_64
 static int generic_gcmaes_set_key(struct crypto_aead *aead, const u8 *key,
 				  unsigned int key_len)
@@ -1163,7 +1257,7 @@ static int __init aesni_init(void)
 		static_call_update(aesni_ctr_enc_tfm, aesni_ctr_enc_avx_tfm);
 		pr_info("AES CTR mode by8 optimization enabled\n");
 	}
-#endif
+#endif /* CONFIG_X86_64 */
 
 	err = crypto_register_alg(&aesni_cipher_alg);
 	if (err)
@@ -1180,8 +1274,22 @@ static int __init aesni_init(void)
 	if (err)
 		goto unregister_skciphers;
 
+#ifdef CONFIG_X86_64
+	if (boot_cpu_has(X86_FEATURE_AVX))
+		err = simd_register_skciphers_compat(&aesni_xctr, 1,
+						     &aesni_simd_xctr);
+	if (err)
+		goto unregister_aeads;
+#endif /* CONFIG_X86_64 */
+
 	return 0;
 
+#ifdef CONFIG_X86_64
+unregister_aeads:
+	simd_unregister_aeads(aesni_aeads, ARRAY_SIZE(aesni_aeads),
+				aesni_simd_aeads);
+#endif /* CONFIG_X86_64 */
+
 unregister_skciphers:
 	simd_unregister_skciphers(aesni_skciphers, ARRAY_SIZE(aesni_skciphers),
 				  aesni_simd_skciphers);
@@ -1197,6 +1305,10 @@ static void __exit aesni_exit(void)
 	simd_unregister_skciphers(aesni_skciphers, ARRAY_SIZE(aesni_skciphers),
 				  aesni_simd_skciphers);
 	crypto_unregister_alg(&aesni_cipher_alg);
+#ifdef CONFIG_X86_64
+	if (boot_cpu_has(X86_FEATURE_AVX))
+		simd_unregister_skciphers(&aesni_xctr, 1, &aesni_simd_xctr);
+#endif /* CONFIG_X86_64 */
 }
 
 late_initcall(aesni_init);
diff --git a/arch/x86/crypto/blake2s-glue.c b/arch/x86/crypto/blake2s-glue.c
index 69853c13e8fb..aaba21230528 100644
--- a/arch/x86/crypto/blake2s-glue.c
+++ b/arch/x86/crypto/blake2s-glue.c
@@ -4,7 +4,6 @@
  */
 
 #include <crypto/internal/blake2s.h>
-#include <crypto/internal/simd.h>
 
 #include <linux/types.h>
 #include <linux/jump_label.h>
@@ -33,7 +32,7 @@ void blake2s_compress(struct blake2s_state *state, const u8 *block,
 	/* SIMD disables preemption, so relax after processing each page. */
 	BUILD_BUG_ON(SZ_4K / BLAKE2S_BLOCK_SIZE < 8);
 
-	if (!static_branch_likely(&blake2s_use_ssse3) || !crypto_simd_usable()) {
+	if (!static_branch_likely(&blake2s_use_ssse3) || !may_use_simd()) {
 		blake2s_compress_generic(state, block, nblocks, inc);
 		return;
 	}
diff --git a/arch/x86/crypto/blake2s-shash.c b/arch/x86/crypto/blake2s-shash.c
deleted file mode 100644
index 59ae28abe35c..000000000000
--- a/arch/x86/crypto/blake2s-shash.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
- */
-
-#include <crypto/internal/blake2s.h>
-#include <crypto/internal/simd.h>
-#include <crypto/internal/hash.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/sizes.h>
-
-#include <asm/cpufeature.h>
-#include <asm/processor.h>
-
-static int crypto_blake2s_update_x86(struct shash_desc *desc,
-				     const u8 *in, unsigned int inlen)
-{
-	return crypto_blake2s_update(desc, in, inlen, false);
-}
-
-static int crypto_blake2s_final_x86(struct shash_desc *desc, u8 *out)
-{
-	return crypto_blake2s_final(desc, out, false);
-}
-
-#define BLAKE2S_ALG(name, driver_name, digest_size)			\
-	{								\
-		.base.cra_name		= name,				\
-		.base.cra_driver_name	= driver_name,			\
-		.base.cra_priority	= 200,				\
-		.base.cra_flags		= CRYPTO_ALG_OPTIONAL_KEY,	\
-		.base.cra_blocksize	= BLAKE2S_BLOCK_SIZE,		\
-		.base.cra_ctxsize	= sizeof(struct blake2s_tfm_ctx), \
-		.base.cra_module	= THIS_MODULE,			\
-		.digestsize		= digest_size,			\
-		.setkey			= crypto_blake2s_setkey,	\
-		.init			= crypto_blake2s_init,		\
-		.update			= crypto_blake2s_update_x86,	\
-		.final			= crypto_blake2s_final_x86,	\
-		.descsize		= sizeof(struct blake2s_state),	\
-	}
-
-static struct shash_alg blake2s_algs[] = {
-	BLAKE2S_ALG("blake2s-128", "blake2s-128-x86", BLAKE2S_128_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-160", "blake2s-160-x86", BLAKE2S_160_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-224", "blake2s-224-x86", BLAKE2S_224_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-256", "blake2s-256-x86", BLAKE2S_256_HASH_SIZE),
-};
-
-static int __init blake2s_mod_init(void)
-{
-	if (IS_REACHABLE(CONFIG_CRYPTO_HASH) && boot_cpu_has(X86_FEATURE_SSSE3))
-		return crypto_register_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs));
-	return 0;
-}
-
-static void __exit blake2s_mod_exit(void)
-{
-	if (IS_REACHABLE(CONFIG_CRYPTO_HASH) && boot_cpu_has(X86_FEATURE_SSSE3))
-		crypto_unregister_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs));
-}
-
-module_init(blake2s_mod_init);
-module_exit(blake2s_mod_exit);
-
-MODULE_ALIAS_CRYPTO("blake2s-128");
-MODULE_ALIAS_CRYPTO("blake2s-128-x86");
-MODULE_ALIAS_CRYPTO("blake2s-160");
-MODULE_ALIAS_CRYPTO("blake2s-160-x86");
-MODULE_ALIAS_CRYPTO("blake2s-224");
-MODULE_ALIAS_CRYPTO("blake2s-224-x86");
-MODULE_ALIAS_CRYPTO("blake2s-256");
-MODULE_ALIAS_CRYPTO("blake2s-256-x86");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/x86/crypto/crc32-pclmul_asm.S b/arch/x86/crypto/crc32-pclmul_asm.S
index c392a6edbfff..ca53e96996ac 100644
--- a/arch/x86/crypto/crc32-pclmul_asm.S
+++ b/arch/x86/crypto/crc32-pclmul_asm.S
@@ -1,26 +1,4 @@
-/* GPL HEADER START
- *
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 only,
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License version 2 for more details (a copy is included
- * in the LICENSE file that accompanied this code).
- *
- * You should have received a copy of the GNU General Public License
- * version 2 along with this program; If not, see http://www.gnu.org/licenses
- *
- * Please  visit http://www.xyratex.com/contact if you need additional
- * information or have any questions.
- *
- * GPL HEADER END
- */
-
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright 2012 Xyratex Technology Limited
  *
diff --git a/arch/x86/crypto/polyval-clmulni_asm.S b/arch/x86/crypto/polyval-clmulni_asm.S
new file mode 100644
index 000000000000..a6ebe4e7dd2b
--- /dev/null
+++ b/arch/x86/crypto/polyval-clmulni_asm.S
@@ -0,0 +1,321 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 Google LLC
+ */
+/*
+ * This is an efficient implementation of POLYVAL using intel PCLMULQDQ-NI
+ * instructions. It works on 8 blocks at a time, by precomputing the first 8
+ * keys powers h^8, ..., h^1 in the POLYVAL finite field. This precomputation
+ * allows us to split finite field multiplication into two steps.
+ *
+ * In the first step, we consider h^i, m_i as normal polynomials of degree less
+ * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
+ * is simply polynomial multiplication.
+ *
+ * In the second step, we compute the reduction of p(x) modulo the finite field
+ * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
+ *
+ * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
+ * multiplication is finite field multiplication. The advantage is that the
+ * two-step process  only requires 1 finite field reduction for every 8
+ * polynomial multiplications. Further parallelism is gained by interleaving the
+ * multiplications and polynomial reductions.
+ */
+
+#include <linux/linkage.h>
+#include <asm/frame.h>
+
+#define STRIDE_BLOCKS 8
+
+#define GSTAR %xmm7
+#define PL %xmm8
+#define PH %xmm9
+#define TMP_XMM %xmm11
+#define LO %xmm12
+#define HI %xmm13
+#define MI %xmm14
+#define SUM %xmm15
+
+#define KEY_POWERS %rdi
+#define MSG %rsi
+#define BLOCKS_LEFT %rdx
+#define ACCUMULATOR %rcx
+#define TMP %rax
+
+.section    .rodata.cst16.gstar, "aM", @progbits, 16
+.align 16
+
+.Lgstar:
+	.quad 0xc200000000000000, 0xc200000000000000
+
+.text
+
+/*
+ * Performs schoolbook1_iteration on two lists of 128-bit polynomials of length
+ * count pointed to by MSG and KEY_POWERS.
+ */
+.macro schoolbook1 count
+	.set i, 0
+	.rept (\count)
+		schoolbook1_iteration i 0
+		.set i, (i +1)
+	.endr
+.endm
+
+/*
+ * Computes the product of two 128-bit polynomials at the memory locations
+ * specified by (MSG + 16*i) and (KEY_POWERS + 16*i) and XORs the components of
+ * the 256-bit product into LO, MI, HI.
+ *
+ * Given:
+ *   X = [X_1 : X_0]
+ *   Y = [Y_1 : Y_0]
+ *
+ * We compute:
+ *   LO += X_0 * Y_0
+ *   MI += X_0 * Y_1 + X_1 * Y_0
+ *   HI += X_1 * Y_1
+ *
+ * Later, the 256-bit result can be extracted as:
+ *   [HI_1 : HI_0 + MI_1 : LO_1 + MI_0 : LO_0]
+ * This step is done when computing the polynomial reduction for efficiency
+ * reasons.
+ *
+ * If xor_sum == 1, then also XOR the value of SUM into m_0.  This avoids an
+ * extra multiplication of SUM and h^8.
+ */
+.macro schoolbook1_iteration i xor_sum
+	movups (16*\i)(MSG), %xmm0
+	.if (\i == 0 && \xor_sum == 1)
+		pxor SUM, %xmm0
+	.endif
+	vpclmulqdq $0x01, (16*\i)(KEY_POWERS), %xmm0, %xmm2
+	vpclmulqdq $0x00, (16*\i)(KEY_POWERS), %xmm0, %xmm1
+	vpclmulqdq $0x10, (16*\i)(KEY_POWERS), %xmm0, %xmm3
+	vpclmulqdq $0x11, (16*\i)(KEY_POWERS), %xmm0, %xmm4
+	vpxor %xmm2, MI, MI
+	vpxor %xmm1, LO, LO
+	vpxor %xmm4, HI, HI
+	vpxor %xmm3, MI, MI
+.endm
+
+/*
+ * Performs the same computation as schoolbook1_iteration, except we expect the
+ * arguments to already be loaded into xmm0 and xmm1 and we set the result
+ * registers LO, MI, and HI directly rather than XOR'ing into them.
+ */
+.macro schoolbook1_noload
+	vpclmulqdq $0x01, %xmm0, %xmm1, MI
+	vpclmulqdq $0x10, %xmm0, %xmm1, %xmm2
+	vpclmulqdq $0x00, %xmm0, %xmm1, LO
+	vpclmulqdq $0x11, %xmm0, %xmm1, HI
+	vpxor %xmm2, MI, MI
+.endm
+
+/*
+ * Computes the 256-bit polynomial represented by LO, HI, MI. Stores
+ * the result in PL, PH.
+ *   [PH : PL] = [HI_1 : HI_0 + MI_1 : LO_1 + MI_0 : LO_0]
+ */
+.macro schoolbook2
+	vpslldq $8, MI, PL
+	vpsrldq $8, MI, PH
+	pxor LO, PL
+	pxor HI, PH
+.endm
+
+/*
+ * Computes the 128-bit reduction of PH : PL. Stores the result in dest.
+ *
+ * This macro computes p(x) mod g(x) where p(x) is in montgomery form and g(x) =
+ * x^128 + x^127 + x^126 + x^121 + 1.
+ *
+ * We have a 256-bit polynomial PH : PL = P_3 : P_2 : P_1 : P_0 that is the
+ * product of two 128-bit polynomials in Montgomery form.  We need to reduce it
+ * mod g(x).  Also, since polynomials in Montgomery form have an "extra" factor
+ * of x^128, this product has two extra factors of x^128.  To get it back into
+ * Montgomery form, we need to remove one of these factors by dividing by x^128.
+ *
+ * To accomplish both of these goals, we add multiples of g(x) that cancel out
+ * the low 128 bits P_1 : P_0, leaving just the high 128 bits. Since the low
+ * bits are zero, the polynomial division by x^128 can be done by right shifting.
+ *
+ * Since the only nonzero term in the low 64 bits of g(x) is the constant term,
+ * the multiple of g(x) needed to cancel out P_0 is P_0 * g(x).  The CPU can
+ * only do 64x64 bit multiplications, so split P_0 * g(x) into x^128 * P_0 +
+ * x^64 * g*(x) * P_0 + P_0, where g*(x) is bits 64-127 of g(x).  Adding this to
+ * the original polynomial gives P_3 : P_2 + P_0 + T_1 : P_1 + T_0 : 0, where T
+ * = T_1 : T_0 = g*(x) * P_0.  Thus, bits 0-63 got "folded" into bits 64-191.
+ *
+ * Repeating this same process on the next 64 bits "folds" bits 64-127 into bits
+ * 128-255, giving the answer in bits 128-255. This time, we need to cancel P_1
+ * + T_0 in bits 64-127. The multiple of g(x) required is (P_1 + T_0) * g(x) *
+ * x^64. Adding this to our previous computation gives P_3 + P_1 + T_0 + V_1 :
+ * P_2 + P_0 + T_1 + V_0 : 0 : 0, where V = V_1 : V_0 = g*(x) * (P_1 + T_0).
+ *
+ * So our final computation is:
+ *   T = T_1 : T_0 = g*(x) * P_0
+ *   V = V_1 : V_0 = g*(x) * (P_1 + T_0)
+ *   p(x) / x^{128} mod g(x) = P_3 + P_1 + T_0 + V_1 : P_2 + P_0 + T_1 + V_0
+ *
+ * The implementation below saves a XOR instruction by computing P_1 + T_0 : P_0
+ * + T_1 and XORing into dest, rather than separately XORing P_1 : P_0 and T_0 :
+ * T_1 into dest.  This allows us to reuse P_1 + T_0 when computing V.
+ */
+.macro montgomery_reduction dest
+	vpclmulqdq $0x00, PL, GSTAR, TMP_XMM	# TMP_XMM = T_1 : T_0 = P_0 * g*(x)
+	pshufd $0b01001110, TMP_XMM, TMP_XMM	# TMP_XMM = T_0 : T_1
+	pxor PL, TMP_XMM			# TMP_XMM = P_1 + T_0 : P_0 + T_1
+	pxor TMP_XMM, PH			# PH = P_3 + P_1 + T_0 : P_2 + P_0 + T_1
+	pclmulqdq $0x11, GSTAR, TMP_XMM		# TMP_XMM = V_1 : V_0 = V = [(P_1 + T_0) * g*(x)]
+	vpxor TMP_XMM, PH, \dest
+.endm
+
+/*
+ * Compute schoolbook multiplication for 8 blocks
+ * m_0h^8 + ... + m_7h^1
+ *
+ * If reduce is set, also computes the montgomery reduction of the
+ * previous full_stride call and XORs with the first message block.
+ * (m_0 + REDUCE(PL, PH))h^8 + ... + m_7h^1.
+ * I.e., the first multiplication uses m_0 + REDUCE(PL, PH) instead of m_0.
+ */
+.macro full_stride reduce
+	pxor LO, LO
+	pxor HI, HI
+	pxor MI, MI
+
+	schoolbook1_iteration 7 0
+	.if \reduce
+		vpclmulqdq $0x00, PL, GSTAR, TMP_XMM
+	.endif
+
+	schoolbook1_iteration 6 0
+	.if \reduce
+		pshufd $0b01001110, TMP_XMM, TMP_XMM
+	.endif
+
+	schoolbook1_iteration 5 0
+	.if \reduce
+		pxor PL, TMP_XMM
+	.endif
+
+	schoolbook1_iteration 4 0
+	.if \reduce
+		pxor TMP_XMM, PH
+	.endif
+
+	schoolbook1_iteration 3 0
+	.if \reduce
+		pclmulqdq $0x11, GSTAR, TMP_XMM
+	.endif
+
+	schoolbook1_iteration 2 0
+	.if \reduce
+		vpxor TMP_XMM, PH, SUM
+	.endif
+
+	schoolbook1_iteration 1 0
+
+	schoolbook1_iteration 0 1
+
+	addq $(8*16), MSG
+	schoolbook2
+.endm
+
+/*
+ * Process BLOCKS_LEFT blocks, where 0 < BLOCKS_LEFT < STRIDE_BLOCKS
+ */
+.macro partial_stride
+	mov BLOCKS_LEFT, TMP
+	shlq $4, TMP
+	addq $(16*STRIDE_BLOCKS), KEY_POWERS
+	subq TMP, KEY_POWERS
+
+	movups (MSG), %xmm0
+	pxor SUM, %xmm0
+	movaps (KEY_POWERS), %xmm1
+	schoolbook1_noload
+	dec BLOCKS_LEFT
+	addq $16, MSG
+	addq $16, KEY_POWERS
+
+	test $4, BLOCKS_LEFT
+	jz .Lpartial4BlocksDone
+	schoolbook1 4
+	addq $(4*16), MSG
+	addq $(4*16), KEY_POWERS
+.Lpartial4BlocksDone:
+	test $2, BLOCKS_LEFT
+	jz .Lpartial2BlocksDone
+	schoolbook1 2
+	addq $(2*16), MSG
+	addq $(2*16), KEY_POWERS
+.Lpartial2BlocksDone:
+	test $1, BLOCKS_LEFT
+	jz .LpartialDone
+	schoolbook1 1
+.LpartialDone:
+	schoolbook2
+	montgomery_reduction SUM
+.endm
+
+/*
+ * Perform montgomery multiplication in GF(2^128) and store result in op1.
+ *
+ * Computes op1*op2*x^{-128} mod x^128 + x^127 + x^126 + x^121 + 1
+ * If op1, op2 are in montgomery form, this computes the montgomery
+ * form of op1*op2.
+ *
+ * void clmul_polyval_mul(u8 *op1, const u8 *op2);
+ */
+SYM_FUNC_START(clmul_polyval_mul)
+	FRAME_BEGIN
+	vmovdqa .Lgstar(%rip), GSTAR
+	movups (%rdi), %xmm0
+	movups (%rsi), %xmm1
+	schoolbook1_noload
+	schoolbook2
+	montgomery_reduction SUM
+	movups SUM, (%rdi)
+	FRAME_END
+	RET
+SYM_FUNC_END(clmul_polyval_mul)
+
+/*
+ * Perform polynomial evaluation as specified by POLYVAL.  This computes:
+ *	h^n * accumulator + h^n * m_0 + ... + h^1 * m_{n-1}
+ * where n=nblocks, h is the hash key, and m_i are the message blocks.
+ *
+ * rdi - pointer to precomputed key powers h^8 ... h^1
+ * rsi - pointer to message blocks
+ * rdx - number of blocks to hash
+ * rcx - pointer to the accumulator
+ *
+ * void clmul_polyval_update(const struct polyval_tfm_ctx *keys,
+ *	const u8 *in, size_t nblocks, u8 *accumulator);
+ */
+SYM_FUNC_START(clmul_polyval_update)
+	FRAME_BEGIN
+	vmovdqa .Lgstar(%rip), GSTAR
+	movups (ACCUMULATOR), SUM
+	subq $STRIDE_BLOCKS, BLOCKS_LEFT
+	js .LstrideLoopExit
+	full_stride 0
+	subq $STRIDE_BLOCKS, BLOCKS_LEFT
+	js .LstrideLoopExitReduce
+.LstrideLoop:
+	full_stride 1
+	subq $STRIDE_BLOCKS, BLOCKS_LEFT
+	jns .LstrideLoop
+.LstrideLoopExitReduce:
+	montgomery_reduction SUM
+.LstrideLoopExit:
+	add $STRIDE_BLOCKS, BLOCKS_LEFT
+	jz .LskipPartial
+	partial_stride
+.LskipPartial:
+	movups SUM, (ACCUMULATOR)
+	FRAME_END
+	RET
+SYM_FUNC_END(clmul_polyval_update)
diff --git a/arch/x86/crypto/polyval-clmulni_glue.c b/arch/x86/crypto/polyval-clmulni_glue.c
new file mode 100644
index 000000000000..b7664d018851
--- /dev/null
+++ b/arch/x86/crypto/polyval-clmulni_glue.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Glue code for POLYVAL using PCMULQDQ-NI
+ *
+ * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
+ * Copyright (c) 2009 Intel Corp.
+ *   Author: Huang Ying <ying.huang@intel.com>
+ * Copyright 2021 Google LLC
+ */
+
+/*
+ * Glue code based on ghash-clmulni-intel_glue.c.
+ *
+ * This implementation of POLYVAL uses montgomery multiplication
+ * accelerated by PCLMULQDQ-NI to implement the finite field
+ * operations.
+ */
+
+#include <crypto/algapi.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/simd.h>
+#include <crypto/polyval.h>
+#include <linux/crypto.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/cpu_device_id.h>
+#include <asm/simd.h>
+
+#define NUM_KEY_POWERS	8
+
+struct polyval_tfm_ctx {
+	/*
+	 * These powers must be in the order h^8, ..., h^1.
+	 */
+	u8 key_powers[NUM_KEY_POWERS][POLYVAL_BLOCK_SIZE];
+};
+
+struct polyval_desc_ctx {
+	u8 buffer[POLYVAL_BLOCK_SIZE];
+	u32 bytes;
+};
+
+asmlinkage void clmul_polyval_update(const struct polyval_tfm_ctx *keys,
+	const u8 *in, size_t nblocks, u8 *accumulator);
+asmlinkage void clmul_polyval_mul(u8 *op1, const u8 *op2);
+
+static void internal_polyval_update(const struct polyval_tfm_ctx *keys,
+	const u8 *in, size_t nblocks, u8 *accumulator)
+{
+	if (likely(crypto_simd_usable())) {
+		kernel_fpu_begin();
+		clmul_polyval_update(keys, in, nblocks, accumulator);
+		kernel_fpu_end();
+	} else {
+		polyval_update_non4k(keys->key_powers[NUM_KEY_POWERS-1], in,
+			nblocks, accumulator);
+	}
+}
+
+static void internal_polyval_mul(u8 *op1, const u8 *op2)
+{
+	if (likely(crypto_simd_usable())) {
+		kernel_fpu_begin();
+		clmul_polyval_mul(op1, op2);
+		kernel_fpu_end();
+	} else {
+		polyval_mul_non4k(op1, op2);
+	}
+}
+
+static int polyval_x86_setkey(struct crypto_shash *tfm,
+			const u8 *key, unsigned int keylen)
+{
+	struct polyval_tfm_ctx *tctx = crypto_shash_ctx(tfm);
+	int i;
+
+	if (keylen != POLYVAL_BLOCK_SIZE)
+		return -EINVAL;
+
+	memcpy(tctx->key_powers[NUM_KEY_POWERS-1], key, POLYVAL_BLOCK_SIZE);
+
+	for (i = NUM_KEY_POWERS-2; i >= 0; i--) {
+		memcpy(tctx->key_powers[i], key, POLYVAL_BLOCK_SIZE);
+		internal_polyval_mul(tctx->key_powers[i],
+				     tctx->key_powers[i+1]);
+	}
+
+	return 0;
+}
+
+static int polyval_x86_init(struct shash_desc *desc)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	memset(dctx, 0, sizeof(*dctx));
+
+	return 0;
+}
+
+static int polyval_x86_update(struct shash_desc *desc,
+			 const u8 *src, unsigned int srclen)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+	u8 *pos;
+	unsigned int nblocks;
+	unsigned int n;
+
+	if (dctx->bytes) {
+		n = min(srclen, dctx->bytes);
+		pos = dctx->buffer + POLYVAL_BLOCK_SIZE - dctx->bytes;
+
+		dctx->bytes -= n;
+		srclen -= n;
+
+		while (n--)
+			*pos++ ^= *src++;
+
+		if (!dctx->bytes)
+			internal_polyval_mul(dctx->buffer,
+					    tctx->key_powers[NUM_KEY_POWERS-1]);
+	}
+
+	while (srclen >= POLYVAL_BLOCK_SIZE) {
+		/* Allow rescheduling every 4K bytes. */
+		nblocks = min(srclen, 4096U) / POLYVAL_BLOCK_SIZE;
+		internal_polyval_update(tctx, src, nblocks, dctx->buffer);
+		srclen -= nblocks * POLYVAL_BLOCK_SIZE;
+		src += nblocks * POLYVAL_BLOCK_SIZE;
+	}
+
+	if (srclen) {
+		dctx->bytes = POLYVAL_BLOCK_SIZE - srclen;
+		pos = dctx->buffer;
+		while (srclen--)
+			*pos++ ^= *src++;
+	}
+
+	return 0;
+}
+
+static int polyval_x86_final(struct shash_desc *desc, u8 *dst)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+	if (dctx->bytes) {
+		internal_polyval_mul(dctx->buffer,
+				     tctx->key_powers[NUM_KEY_POWERS-1]);
+	}
+
+	memcpy(dst, dctx->buffer, POLYVAL_BLOCK_SIZE);
+
+	return 0;
+}
+
+static struct shash_alg polyval_alg = {
+	.digestsize	= POLYVAL_DIGEST_SIZE,
+	.init		= polyval_x86_init,
+	.update		= polyval_x86_update,
+	.final		= polyval_x86_final,
+	.setkey		= polyval_x86_setkey,
+	.descsize	= sizeof(struct polyval_desc_ctx),
+	.base		= {
+		.cra_name		= "polyval",
+		.cra_driver_name	= "polyval-clmulni",
+		.cra_priority		= 200,
+		.cra_blocksize		= POLYVAL_BLOCK_SIZE,
+		.cra_ctxsize		= sizeof(struct polyval_tfm_ctx),
+		.cra_module		= THIS_MODULE,
+	},
+};
+
+__maybe_unused static const struct x86_cpu_id pcmul_cpu_id[] = {
+	X86_MATCH_FEATURE(X86_FEATURE_PCLMULQDQ, NULL),
+	{}
+};
+MODULE_DEVICE_TABLE(x86cpu, pcmul_cpu_id);
+
+static int __init polyval_clmulni_mod_init(void)
+{
+	if (!x86_match_cpu(pcmul_cpu_id))
+		return -ENODEV;
+
+	if (!boot_cpu_has(X86_FEATURE_AVX))
+		return -ENODEV;
+
+	return crypto_register_shash(&polyval_alg);
+}
+
+static void __exit polyval_clmulni_mod_exit(void)
+{
+	crypto_unregister_shash(&polyval_alg);
+}
+
+module_init(polyval_clmulni_mod_init);
+module_exit(polyval_clmulni_mod_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("POLYVAL hash function accelerated by PCLMULQDQ-NI");
+MODULE_ALIAS_CRYPTO("polyval");
+MODULE_ALIAS_CRYPTO("polyval-clmulni");
diff --git a/arch/x86/entry/vdso/vdso2c.c b/arch/x86/entry/vdso/vdso2c.c
index edfe9780f6d1..90d15f2a7205 100644
--- a/arch/x86/entry/vdso/vdso2c.c
+++ b/arch/x86/entry/vdso/vdso2c.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * vdso2c - A vdso image preparation tool
  * Copyright (c) 2014 Andy Lutomirski and others
- * Licensed under the GPL v2
  *
  * vdso2c requires stripped and unstripped input.  It would be trivial
  * to fully strip the input in here, but, for reasons described below,
diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c
index 1000d457c332..6292b960037b 100644
--- a/arch/x86/entry/vdso/vma.c
+++ b/arch/x86/entry/vdso/vma.c
@@ -127,17 +127,17 @@ int vdso_join_timens(struct task_struct *task, struct time_namespace *ns)
 {
 	struct mm_struct *mm = task->mm;
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
 	mmap_read_lock(mm);
-
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		unsigned long size = vma->vm_end - vma->vm_start;
 
 		if (vma_is_special_mapping(vma, &vvar_mapping))
 			zap_page_range(vma, vma->vm_start, size);
 	}
-
 	mmap_read_unlock(mm);
+
 	return 0;
 }
 #else
@@ -354,6 +354,7 @@ int map_vdso_once(const struct vdso_image *image, unsigned long addr)
 {
 	struct mm_struct *mm = current->mm;
 	struct vm_area_struct *vma;
+	VMA_ITERATOR(vmi, mm, 0);
 
 	mmap_write_lock(mm);
 	/*
@@ -363,7 +364,7 @@ int map_vdso_once(const struct vdso_image *image, unsigned long addr)
 	 * We could search vma near context.vdso, but it's a slowpath,
 	 * so let's explicitly check all VMAs to be completely sure.
 	 */
-	for (vma = mm->mmap; vma; vma = vma->vm_next) {
+	for_each_vma(vmi, vma) {
 		if (vma_is_special_mapping(vma, &vdso_mapping) ||
 				vma_is_special_mapping(vma, &vvar_mapping)) {
 			mmap_write_unlock(mm);
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 0d04414b97d2..d568afc705d2 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -21,7 +21,6 @@
 #define NUM_COUNTERS_NB		4
 #define NUM_COUNTERS_L2		4
 #define NUM_COUNTERS_L3		6
-#define MAX_COUNTERS		6
 
 #define RDPMC_BASE_NB		6
 #define RDPMC_BASE_LLC		10
@@ -31,6 +30,7 @@
 #undef pr_fmt
 #define pr_fmt(fmt)	"amd_uncore: " fmt
 
+static int pmu_version;
 static int num_counters_llc;
 static int num_counters_nb;
 static bool l3_mask;
@@ -46,7 +46,7 @@ struct amd_uncore {
 	u32 msr_base;
 	cpumask_t *active_mask;
 	struct pmu *pmu;
-	struct perf_event *events[MAX_COUNTERS];
+	struct perf_event **events;
 	struct hlist_node node;
 };
 
@@ -158,6 +158,16 @@ static int amd_uncore_add(struct perf_event *event, int flags)
 	hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;
 	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 
+	/*
+	 * The first four DF counters are accessible via RDPMC index 6 to 9
+	 * followed by the L3 counters from index 10 to 15. For processors
+	 * with more than four DF counters, the DF RDPMC assignments become
+	 * discontiguous as the additional counters are accessible starting
+	 * from index 16.
+	 */
+	if (is_nb_event(event) && hwc->idx >= NUM_COUNTERS_NB)
+		hwc->event_base_rdpmc += NUM_COUNTERS_L3;
+
 	if (flags & PERF_EF_START)
 		amd_uncore_start(event, PERF_EF_RELOAD);
 
@@ -209,10 +219,14 @@ static int amd_uncore_event_init(struct perf_event *event)
 {
 	struct amd_uncore *uncore;
 	struct hw_perf_event *hwc = &event->hw;
+	u64 event_mask = AMD64_RAW_EVENT_MASK_NB;
 
 	if (event->attr.type != event->pmu->type)
 		return -ENOENT;
 
+	if (pmu_version >= 2 && is_nb_event(event))
+		event_mask = AMD64_PERFMON_V2_RAW_EVENT_MASK_NB;
+
 	/*
 	 * NB and Last level cache counters (MSRs) are shared across all cores
 	 * that share the same NB / Last level cache.  On family 16h and below,
@@ -221,7 +235,7 @@ static int amd_uncore_event_init(struct perf_event *event)
 	 * out. So we do not support sampling and per-thread events via
 	 * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
 	 */
-	hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
+	hwc->config = event->attr.config & event_mask;
 	hwc->idx = -1;
 
 	if (event->cpu < 0)
@@ -247,6 +261,19 @@ static int amd_uncore_event_init(struct perf_event *event)
 	return 0;
 }
 
+static umode_t
+amd_f17h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)
+{
+	return boot_cpu_data.x86 >= 0x17 && boot_cpu_data.x86 < 0x19 ?
+	       attr->mode : 0;
+}
+
+static umode_t
+amd_f19h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)
+{
+	return boot_cpu_data.x86 >= 0x19 ? attr->mode : 0;
+}
+
 static ssize_t amd_uncore_attr_show_cpumask(struct device *dev,
 					    struct device_attribute *attr,
 					    char *buf)
@@ -287,8 +314,10 @@ static struct device_attribute format_attr_##_var =			\
 
 DEFINE_UNCORE_FORMAT_ATTR(event12,	event,		"config:0-7,32-35");
 DEFINE_UNCORE_FORMAT_ATTR(event14,	event,		"config:0-7,32-35,59-60"); /* F17h+ DF */
+DEFINE_UNCORE_FORMAT_ATTR(event14v2,	event,		"config:0-7,32-37");	   /* PerfMonV2 DF */
 DEFINE_UNCORE_FORMAT_ATTR(event8,	event,		"config:0-7");		   /* F17h+ L3 */
-DEFINE_UNCORE_FORMAT_ATTR(umask,	umask,		"config:8-15");
+DEFINE_UNCORE_FORMAT_ATTR(umask8,	umask,		"config:8-15");
+DEFINE_UNCORE_FORMAT_ATTR(umask12,	umask,		"config:8-15,24-27");	   /* PerfMonV2 DF */
 DEFINE_UNCORE_FORMAT_ATTR(coreid,	coreid,		"config:42-44");	   /* F19h L3 */
 DEFINE_UNCORE_FORMAT_ATTR(slicemask,	slicemask,	"config:48-51");	   /* F17h L3 */
 DEFINE_UNCORE_FORMAT_ATTR(threadmask8,	threadmask,	"config:56-63");	   /* F17h L3 */
@@ -297,20 +326,33 @@ DEFINE_UNCORE_FORMAT_ATTR(enallslices,	enallslices,	"config:46");		   /* F19h L3
 DEFINE_UNCORE_FORMAT_ATTR(enallcores,	enallcores,	"config:47");		   /* F19h L3 */
 DEFINE_UNCORE_FORMAT_ATTR(sliceid,	sliceid,	"config:48-50");	   /* F19h L3 */
 
+/* Common DF and NB attributes */
 static struct attribute *amd_uncore_df_format_attr[] = {
-	&format_attr_event12.attr, /* event14 if F17h+ */
-	&format_attr_umask.attr,
+	&format_attr_event12.attr,	/* event */
+	&format_attr_umask8.attr,	/* umask */
 	NULL,
 };
 
+/* Common L2 and L3 attributes */
 static struct attribute *amd_uncore_l3_format_attr[] = {
-	&format_attr_event12.attr, /* event8 if F17h+ */
-	&format_attr_umask.attr,
-	NULL, /* slicemask if F17h,	coreid if F19h */
-	NULL, /* threadmask8 if F17h,	enallslices if F19h */
-	NULL, /*			enallcores if F19h */
-	NULL, /*			sliceid if F19h */
-	NULL, /*			threadmask2 if F19h */
+	&format_attr_event12.attr,	/* event */
+	&format_attr_umask8.attr,	/* umask */
+	NULL,				/* threadmask */
+	NULL,
+};
+
+/* F17h unique L3 attributes */
+static struct attribute *amd_f17h_uncore_l3_format_attr[] = {
+	&format_attr_slicemask.attr,	/* slicemask */
+	NULL,
+};
+
+/* F19h unique L3 attributes */
+static struct attribute *amd_f19h_uncore_l3_format_attr[] = {
+	&format_attr_coreid.attr,	/* coreid */
+	&format_attr_enallslices.attr,	/* enallslices */
+	&format_attr_enallcores.attr,	/* enallcores */
+	&format_attr_sliceid.attr,	/* sliceid */
 	NULL,
 };
 
@@ -324,6 +366,18 @@ static struct attribute_group amd_uncore_l3_format_group = {
 	.attrs = amd_uncore_l3_format_attr,
 };
 
+static struct attribute_group amd_f17h_uncore_l3_format_group = {
+	.name = "format",
+	.attrs = amd_f17h_uncore_l3_format_attr,
+	.is_visible = amd_f17h_uncore_is_visible,
+};
+
+static struct attribute_group amd_f19h_uncore_l3_format_group = {
+	.name = "format",
+	.attrs = amd_f19h_uncore_l3_format_attr,
+	.is_visible = amd_f19h_uncore_is_visible,
+};
+
 static const struct attribute_group *amd_uncore_df_attr_groups[] = {
 	&amd_uncore_attr_group,
 	&amd_uncore_df_format_group,
@@ -336,6 +390,12 @@ static const struct attribute_group *amd_uncore_l3_attr_groups[] = {
 	NULL,
 };
 
+static const struct attribute_group *amd_uncore_l3_attr_update[] = {
+	&amd_f17h_uncore_l3_format_group,
+	&amd_f19h_uncore_l3_format_group,
+	NULL,
+};
+
 static struct pmu amd_nb_pmu = {
 	.task_ctx_nr	= perf_invalid_context,
 	.attr_groups	= amd_uncore_df_attr_groups,
@@ -353,6 +413,7 @@ static struct pmu amd_nb_pmu = {
 static struct pmu amd_llc_pmu = {
 	.task_ctx_nr	= perf_invalid_context,
 	.attr_groups	= amd_uncore_l3_attr_groups,
+	.attr_update	= amd_uncore_l3_attr_update,
 	.name		= "amd_l2",
 	.event_init	= amd_uncore_event_init,
 	.add		= amd_uncore_add,
@@ -370,11 +431,19 @@ static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
 			cpu_to_node(cpu));
 }
 
+static inline struct perf_event **
+amd_uncore_events_alloc(unsigned int num, unsigned int cpu)
+{
+	return kzalloc_node(sizeof(struct perf_event *) * num, GFP_KERNEL,
+			    cpu_to_node(cpu));
+}
+
 static int amd_uncore_cpu_up_prepare(unsigned int cpu)
 {
-	struct amd_uncore *uncore_nb = NULL, *uncore_llc;
+	struct amd_uncore *uncore_nb = NULL, *uncore_llc = NULL;
 
 	if (amd_uncore_nb) {
+		*per_cpu_ptr(amd_uncore_nb, cpu) = NULL;
 		uncore_nb = amd_uncore_alloc(cpu);
 		if (!uncore_nb)
 			goto fail;
@@ -384,11 +453,15 @@ static int amd_uncore_cpu_up_prepare(unsigned int cpu)
 		uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL;
 		uncore_nb->active_mask = &amd_nb_active_mask;
 		uncore_nb->pmu = &amd_nb_pmu;
+		uncore_nb->events = amd_uncore_events_alloc(num_counters_nb, cpu);
+		if (!uncore_nb->events)
+			goto fail;
 		uncore_nb->id = -1;
 		*per_cpu_ptr(amd_uncore_nb, cpu) = uncore_nb;
 	}
 
 	if (amd_uncore_llc) {
+		*per_cpu_ptr(amd_uncore_llc, cpu) = NULL;
 		uncore_llc = amd_uncore_alloc(cpu);
 		if (!uncore_llc)
 			goto fail;
@@ -398,6 +471,9 @@ static int amd_uncore_cpu_up_prepare(unsigned int cpu)
 		uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL;
 		uncore_llc->active_mask = &amd_llc_active_mask;
 		uncore_llc->pmu = &amd_llc_pmu;
+		uncore_llc->events = amd_uncore_events_alloc(num_counters_llc, cpu);
+		if (!uncore_llc->events)
+			goto fail;
 		uncore_llc->id = -1;
 		*per_cpu_ptr(amd_uncore_llc, cpu) = uncore_llc;
 	}
@@ -405,9 +481,16 @@ static int amd_uncore_cpu_up_prepare(unsigned int cpu)
 	return 0;
 
 fail:
-	if (amd_uncore_nb)
-		*per_cpu_ptr(amd_uncore_nb, cpu) = NULL;
-	kfree(uncore_nb);
+	if (uncore_nb) {
+		kfree(uncore_nb->events);
+		kfree(uncore_nb);
+	}
+
+	if (uncore_llc) {
+		kfree(uncore_llc->events);
+		kfree(uncore_llc);
+	}
+
 	return -ENOMEM;
 }
 
@@ -540,8 +623,11 @@ static void uncore_dead(unsigned int cpu, struct amd_uncore * __percpu *uncores)
 	if (cpu == uncore->cpu)
 		cpumask_clear_cpu(cpu, uncore->active_mask);
 
-	if (!--uncore->refcnt)
+	if (!--uncore->refcnt) {
+		kfree(uncore->events);
 		kfree(uncore);
+	}
+
 	*per_cpu_ptr(uncores, cpu) = NULL;
 }
 
@@ -560,6 +646,7 @@ static int __init amd_uncore_init(void)
 {
 	struct attribute **df_attr = amd_uncore_df_format_attr;
 	struct attribute **l3_attr = amd_uncore_l3_format_attr;
+	union cpuid_0x80000022_ebx ebx;
 	int ret = -ENODEV;
 
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
@@ -569,6 +656,9 @@ static int __init amd_uncore_init(void)
 	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 		return -ENODEV;
 
+	if (boot_cpu_has(X86_FEATURE_PERFMON_V2))
+		pmu_version = 2;
+
 	num_counters_nb	= NUM_COUNTERS_NB;
 	num_counters_llc = NUM_COUNTERS_L2;
 	if (boot_cpu_data.x86 >= 0x17) {
@@ -585,8 +675,12 @@ static int __init amd_uncore_init(void)
 	}
 
 	if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {
-		if (boot_cpu_data.x86 >= 0x17)
+		if (pmu_version >= 2) {
+			*df_attr++ = &format_attr_event14v2.attr;
+			*df_attr++ = &format_attr_umask12.attr;
+		} else if (boot_cpu_data.x86 >= 0x17) {
 			*df_attr = &format_attr_event14.attr;
+		}
 
 		amd_uncore_nb = alloc_percpu(struct amd_uncore *);
 		if (!amd_uncore_nb) {
@@ -597,6 +691,11 @@ static int __init amd_uncore_init(void)
 		if (ret)
 			goto fail_nb;
 
+		if (pmu_version >= 2) {
+			ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
+			num_counters_nb = ebx.split.num_df_pmc;
+		}
+
 		pr_info("%d %s %s counters detected\n", num_counters_nb,
 			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?  "HYGON" : "",
 			amd_nb_pmu.name);
@@ -607,16 +706,11 @@ static int __init amd_uncore_init(void)
 	if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) {
 		if (boot_cpu_data.x86 >= 0x19) {
 			*l3_attr++ = &format_attr_event8.attr;
-			*l3_attr++ = &format_attr_umask.attr;
-			*l3_attr++ = &format_attr_coreid.attr;
-			*l3_attr++ = &format_attr_enallslices.attr;
-			*l3_attr++ = &format_attr_enallcores.attr;
-			*l3_attr++ = &format_attr_sliceid.attr;
+			*l3_attr++ = &format_attr_umask8.attr;
 			*l3_attr++ = &format_attr_threadmask2.attr;
 		} else if (boot_cpu_data.x86 >= 0x17) {
 			*l3_attr++ = &format_attr_event8.attr;
-			*l3_attr++ = &format_attr_umask.attr;
-			*l3_attr++ = &format_attr_slicemask.attr;
+			*l3_attr++ = &format_attr_umask8.attr;
 			*l3_attr++ = &format_attr_threadmask8.attr;
 		}
 
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 30788894124f..f969410d0c90 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -693,9 +693,9 @@ void x86_pmu_disable_all(void)
 	}
 }
 
-struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
+struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
 {
-	return static_call(x86_pmu_guest_get_msrs)(nr);
+	return static_call(x86_pmu_guest_get_msrs)(nr, data);
 }
 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
 
@@ -2103,14 +2103,15 @@ static int __init init_hw_perf_events(void)
 	}
 	if (err != 0) {
 		pr_cont("no PMU driver, software events only.\n");
-		return 0;
+		err = 0;
+		goto out_bad_pmu;
 	}
 
 	pmu_check_apic();
 
 	/* sanity check that the hardware exists or is emulated */
 	if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
-		return 0;
+		goto out_bad_pmu;
 
 	pr_cont("%s PMU driver.\n", x86_pmu.name);
 
@@ -2219,6 +2220,8 @@ static int __init init_hw_perf_events(void)
 	cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
 out:
 	cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
+out_bad_pmu:
+	memset(&x86_pmu, 0, sizeof(x86_pmu));
 	return err;
 }
 early_initcall(init_hw_perf_events);
@@ -2990,6 +2993,11 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
 
 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 {
+	if (!x86_pmu_initialized()) {
+		memset(cap, 0, sizeof(*cap));
+		return;
+	}
+
 	cap->version		= x86_pmu.version;
 	/*
 	 * KVM doesn't support the hybrid PMU yet.
@@ -3002,5 +3010,17 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 	cap->bit_width_fixed	= x86_pmu.cntval_bits;
 	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
 	cap->events_mask_len	= x86_pmu.events_mask_len;
+	cap->pebs_ept		= x86_pmu.pebs_ept;
 }
 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
+
+u64 perf_get_hw_event_config(int hw_event)
+{
+	int max = x86_pmu.max_events;
+
+	if (hw_event < max)
+		return x86_pmu.event_map(array_index_nospec(hw_event, max));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(perf_get_hw_event_config);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 45024abd929f..4e9b7af9cc45 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -14,6 +14,7 @@
 #include <linux/slab.h>
 #include <linux/export.h>
 #include <linux/nmi.h>
+#include <linux/kvm_host.h>
 
 #include <asm/cpufeature.h>
 #include <asm/hardirq.h>
@@ -2852,6 +2853,47 @@ static void intel_pmu_reset(void)
 	local_irq_restore(flags);
 }
 
+/*
+ * We may be running with guest PEBS events created by KVM, and the
+ * PEBS records are logged into the guest's DS and invisible to host.
+ *
+ * In the case of guest PEBS overflow, we only trigger a fake event
+ * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
+ * The guest will then vm-entry and check the guest DS area to read
+ * the guest PEBS records.
+ *
+ * The contents and other behavior of the guest event do not matter.
+ */
+static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
+				      struct perf_sample_data *data)
+{
+	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+	u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
+	struct perf_event *event = NULL;
+	int bit;
+
+	if (!unlikely(perf_guest_state()))
+		return;
+
+	if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
+	    !guest_pebs_idxs)
+		return;
+
+	for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs,
+			 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) {
+		event = cpuc->events[bit];
+		if (!event->attr.precise_ip)
+			continue;
+
+		perf_sample_data_init(data, 0, event->hw.last_period);
+		if (perf_event_overflow(event, data, regs))
+			x86_pmu_stop(event, 0);
+
+		/* Inject one fake event is enough. */
+		break;
+	}
+}
+
 static int handle_pmi_common(struct pt_regs *regs, u64 status)
 {
 	struct perf_sample_data data;
@@ -2891,10 +2933,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
 	 * counters from the GLOBAL_STATUS mask and we always process PEBS
 	 * events via drain_pebs().
 	 */
-	if (x86_pmu.flags & PMU_FL_PEBS_ALL)
-		status &= ~cpuc->pebs_enabled;
-	else
-		status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
+	status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
 
 	/*
 	 * PEBS overflow sets bit 62 in the global status register
@@ -2903,6 +2942,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
 		u64 pebs_enabled = cpuc->pebs_enabled;
 
 		handled++;
+		x86_pmu_handle_guest_pebs(regs, &data);
 		x86_pmu.drain_pebs(regs, &data);
 		status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
 
@@ -3930,40 +3970,98 @@ static int intel_pmu_hw_config(struct perf_event *event)
 	return 0;
 }
 
-static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
+/*
+ * Currently, the only caller of this function is the atomic_switch_perf_msrs().
+ * The host perf conext helps to prepare the values of the real hardware for
+ * a set of msrs that need to be switched atomically in a vmx transaction.
+ *
+ * For example, the pseudocode needed to add a new msr should look like:
+ *
+ * arr[(*nr)++] = (struct perf_guest_switch_msr){
+ *	.msr = the hardware msr address,
+ *	.host = the value the hardware has when it doesn't run a guest,
+ *	.guest = the value the hardware has when it runs a guest,
+ * };
+ *
+ * These values have nothing to do with the emulated values the guest sees
+ * when it uses {RD,WR}MSR, which should be handled by the KVM context,
+ * specifically in the intel_pmu_{get,set}_msr().
+ */
+static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
 {
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 	struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
+	struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
 	u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
+	u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
+	int global_ctrl, pebs_enable;
+
+	*nr = 0;
+	global_ctrl = (*nr)++;
+	arr[global_ctrl] = (struct perf_guest_switch_msr){
+		.msr = MSR_CORE_PERF_GLOBAL_CTRL,
+		.host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
+		.guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),
+	};
 
-	arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
-	arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
-	arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
-	if (x86_pmu.flags & PMU_FL_PEBS_ALL)
-		arr[0].guest &= ~cpuc->pebs_enabled;
-	else
-		arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
-	*nr = 1;
+	if (!x86_pmu.pebs)
+		return arr;
 
-	if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
-		/*
-		 * If PMU counter has PEBS enabled it is not enough to
-		 * disable counter on a guest entry since PEBS memory
-		 * write can overshoot guest entry and corrupt guest
-		 * memory. Disabling PEBS solves the problem.
-		 *
-		 * Don't do this if the CPU already enforces it.
-		 */
-		arr[1].msr = MSR_IA32_PEBS_ENABLE;
-		arr[1].host = cpuc->pebs_enabled;
-		arr[1].guest = 0;
-		*nr = 2;
+	/*
+	 * If PMU counter has PEBS enabled it is not enough to
+	 * disable counter on a guest entry since PEBS memory
+	 * write can overshoot guest entry and corrupt guest
+	 * memory. Disabling PEBS solves the problem.
+	 *
+	 * Don't do this if the CPU already enforces it.
+	 */
+	if (x86_pmu.pebs_no_isolation) {
+		arr[(*nr)++] = (struct perf_guest_switch_msr){
+			.msr = MSR_IA32_PEBS_ENABLE,
+			.host = cpuc->pebs_enabled,
+			.guest = 0,
+		};
+		return arr;
+	}
+
+	if (!kvm_pmu || !x86_pmu.pebs_ept)
+		return arr;
+
+	arr[(*nr)++] = (struct perf_guest_switch_msr){
+		.msr = MSR_IA32_DS_AREA,
+		.host = (unsigned long)cpuc->ds,
+		.guest = kvm_pmu->ds_area,
+	};
+
+	if (x86_pmu.intel_cap.pebs_baseline) {
+		arr[(*nr)++] = (struct perf_guest_switch_msr){
+			.msr = MSR_PEBS_DATA_CFG,
+			.host = cpuc->pebs_data_cfg,
+			.guest = kvm_pmu->pebs_data_cfg,
+		};
+	}
+
+	pebs_enable = (*nr)++;
+	arr[pebs_enable] = (struct perf_guest_switch_msr){
+		.msr = MSR_IA32_PEBS_ENABLE,
+		.host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
+		.guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
+	};
+
+	if (arr[pebs_enable].host) {
+		/* Disable guest PEBS if host PEBS is enabled. */
+		arr[pebs_enable].guest = 0;
+	} else {
+		/* Disable guest PEBS for cross-mapped PEBS counters. */
+		arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
+		/* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
+		arr[global_ctrl].guest |= arr[pebs_enable].guest;
 	}
 
 	return arr;
 }
 
-static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
+static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
 {
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 	struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
@@ -5650,6 +5748,7 @@ __init int intel_pmu_init(void)
 	x86_pmu.events_mask_len		= eax.split.mask_length;
 
 	x86_pmu.max_pebs_events		= min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
+	x86_pmu.pebs_capable		= PEBS_COUNTER_MASK;
 
 	/*
 	 * Quirk: v2 perfmon does not report fixed-purpose events, so
@@ -5834,6 +5933,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_aliases = NULL;
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.lbr_pt_coexist = true;
+		x86_pmu.pebs_capable = ~0ULL;
 		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
 		x86_pmu.flags |= PMU_FL_PEBS_ALL;
 		x86_pmu.get_event_constraints = glp_get_event_constraints;
@@ -6138,6 +6238,7 @@ __init int intel_pmu_init(void)
 
 	case INTEL_FAM6_ICELAKE_X:
 	case INTEL_FAM6_ICELAKE_D:
+		x86_pmu.pebs_ept = 1;
 		pmem = true;
 		fallthrough;
 	case INTEL_FAM6_ICELAKE_L:
@@ -6190,6 +6291,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_aliases = NULL;
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.pebs_block = true;
+		x86_pmu.pebs_capable = ~0ULL;
 		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
 		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
 		x86_pmu.flags |= PMU_FL_PEBS_ALL;
@@ -6235,6 +6337,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_aliases = NULL;
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.pebs_block = true;
+		x86_pmu.pebs_capable = ~0ULL;
 		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
 		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
 		x86_pmu.flags |= PMU_FL_PEBS_ALL;
@@ -6398,8 +6501,7 @@ __init int intel_pmu_init(void)
 					  x86_pmu.intel_ctrl);
 	/*
 	 * Access LBR MSR may cause #GP under certain circumstances.
-	 * E.g. KVM doesn't support LBR MSR
-	 * Check all LBT MSR here.
+	 * Check all LBR MSR here.
 	 * Disable LBR access if any LBR MSRs can not be accessed.
 	 */
 	if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 21a5482bcf84..b432fbba5833 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -136,7 +136,8 @@ struct amd_nb {
 	PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
 	PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
 	PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
-	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
+	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
+	PERF_SAMPLE_WEIGHT_TYPE)
 
 #define PEBS_GP_REGS			\
 	((1ULL << PERF_REG_X86_AX)    | \
@@ -818,7 +819,8 @@ struct x86_pmu {
 			pebs_prec_dist		:1,
 			pebs_no_tlb		:1,
 			pebs_no_isolation	:1,
-			pebs_block		:1;
+			pebs_block		:1,
+			pebs_ept		:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	int		max_pebs_events;
@@ -827,6 +829,7 @@ struct x86_pmu {
 	void		(*pebs_aliases)(struct perf_event *event);
 	unsigned long	large_pebs_flags;
 	u64		rtm_abort_event;
+	u64		pebs_capable;
 
 	/*
 	 * Intel LBR
@@ -902,7 +905,7 @@ struct x86_pmu {
 	/*
 	 * Intel host/guest support (KVM)
 	 */
-	struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
+	struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data);
 
 	/*
 	 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 03acc823838a..e314732c4777 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -219,7 +219,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
+#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 71943dce691e..fdc6216cb953 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -323,7 +323,7 @@ static inline u32 efi64_convert_status(efi_status_t status)
 #define __efi64_argmap_get_memory_space_descriptor(phys, desc) \
 	(__efi64_split(phys), (desc))
 
-#define __efi64_argmap_set_memory_space_descriptor(phys, size, flags) \
+#define __efi64_argmap_set_memory_space_attributes(phys, size, flags) \
 	(__efi64_split(phys), __efi64_split(size), __efi64_split(flags))
 
 /*
@@ -383,7 +383,6 @@ static inline bool efi_is_64bit(void)
 extern bool efi_reboot_required(void);
 extern bool efi_is_table_address(unsigned long phys_addr);
 
-extern void efi_find_mirror(void);
 extern void efi_reserve_boot_services(void);
 #else
 static inline void parse_efi_setup(u64 phys_addr, u32 data_len) {}
@@ -395,9 +394,6 @@ static inline  bool efi_is_table_address(unsigned long phys_addr)
 {
 	return false;
 }
-static inline void efi_find_mirror(void)
-{
-}
 static inline void efi_reserve_boot_services(void)
 {
 }
diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h
index 6b0f31fb53f7..503a577814b2 100644
--- a/arch/x86/include/asm/fpu/api.h
+++ b/arch/x86/include/asm/fpu/api.h
@@ -164,4 +164,6 @@ static inline bool fpstate_is_confidential(struct fpu_guest *gfpu)
 /* prctl */
 extern long fpu_xstate_prctl(int option, unsigned long arg2);
 
+extern void fpu_idle_fpregs(void);
+
 #endif /* _ASM_X86_FPU_API_H */
diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-x86-ops.h
index da47f60a4650..6f2f1affbb78 100644
--- a/arch/x86/include/asm/kvm-x86-ops.h
+++ b/arch/x86/include/asm/kvm-x86-ops.h
@@ -21,6 +21,7 @@ KVM_X86_OP(has_emulated_msr)
 KVM_X86_OP(vcpu_after_set_cpuid)
 KVM_X86_OP(vm_init)
 KVM_X86_OP_OPTIONAL(vm_destroy)
+KVM_X86_OP_OPTIONAL_RET0(vcpu_precreate)
 KVM_X86_OP(vcpu_create)
 KVM_X86_OP(vcpu_free)
 KVM_X86_OP(vcpu_reset)
diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h
index fdfd8e06fee6..c17e3e96fc1d 100644
--- a/arch/x86/include/asm/kvm-x86-pmu-ops.h
+++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h
@@ -12,7 +12,7 @@ BUILD_BUG_ON(1)
  * a NULL definition, for example if "static_call_cond()" will be used
  * at the call sites.
  */
-KVM_X86_PMU_OP(pmc_perf_hw_id)
+KVM_X86_PMU_OP(hw_event_available)
 KVM_X86_PMU_OP(pmc_is_enabled)
 KVM_X86_PMU_OP(pmc_idx_to_pmc)
 KVM_X86_PMU_OP(rdpmc_ecx_to_pmc)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 9217bd6cf0d1..1038ccb7056a 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -65,6 +65,9 @@
 #define KVM_BUS_LOCK_DETECTION_VALID_MODE	(KVM_BUS_LOCK_DETECTION_OFF | \
 						 KVM_BUS_LOCK_DETECTION_EXIT)
 
+#define KVM_X86_NOTIFY_VMEXIT_VALID_BITS	(KVM_X86_NOTIFY_VMEXIT_ENABLED | \
+						 KVM_X86_NOTIFY_VMEXIT_USER)
+
 /* x86-specific vcpu->requests bit members */
 #define KVM_REQ_MIGRATE_TIMER		KVM_ARCH_REQ(0)
 #define KVM_REQ_REPORT_TPR_ACCESS	KVM_ARCH_REQ(1)
@@ -505,6 +508,7 @@ struct kvm_pmu {
 	unsigned nr_arch_fixed_counters;
 	unsigned available_event_types;
 	u64 fixed_ctr_ctrl;
+	u64 fixed_ctr_ctrl_mask;
 	u64 global_ctrl;
 	u64 global_status;
 	u64 counter_bitmask[2];
@@ -520,6 +524,21 @@ struct kvm_pmu {
 	DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
 	DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
 
+	u64 ds_area;
+	u64 pebs_enable;
+	u64 pebs_enable_mask;
+	u64 pebs_data_cfg;
+	u64 pebs_data_cfg_mask;
+
+	/*
+	 * If a guest counter is cross-mapped to host counter with different
+	 * index, its PEBS capability will be temporarily disabled.
+	 *
+	 * The user should make sure that this mask is updated
+	 * after disabling interrupts and before perf_guest_get_msrs();
+	 */
+	u64 host_cross_mapped_mask;
+
 	/*
 	 * The gate to release perf_events not marked in
 	 * pmc_in_use only once in a vcpu time slice.
@@ -644,7 +663,6 @@ struct kvm_vcpu_arch {
 	u64 efer;
 	u64 apic_base;
 	struct kvm_lapic *apic;    /* kernel irqchip context */
-	bool apicv_active;
 	bool load_eoi_exitmap_pending;
 	DECLARE_BITMAP(ioapic_handled_vectors, 256);
 	unsigned long apic_attention;
@@ -1222,8 +1240,13 @@ struct kvm_arch {
 	bool guest_can_read_msr_platform_info;
 	bool exception_payload_enabled;
 
+	bool triple_fault_event;
+
 	bool bus_lock_detection_enabled;
 	bool enable_pmu;
+
+	u32 notify_window;
+	u32 notify_vmexit_flags;
 	/*
 	 * If exit_on_emulation_error is set, and the in-kernel instruction
 	 * emulator fails to emulate an instruction, allow userspace
@@ -1307,6 +1330,12 @@ struct kvm_arch {
 	hpa_t	hv_root_tdp;
 	spinlock_t hv_root_tdp_lock;
 #endif
+	/*
+	 * VM-scope maximum vCPU ID. Used to determine the size of structures
+	 * that increase along with the maximum vCPU ID, in which case, using
+	 * the global KVM_MAX_VCPU_IDS may lead to significant memory waste.
+	 */
+	u32 max_vcpu_ids;
 };
 
 struct kvm_vm_stat {
@@ -1367,6 +1396,7 @@ struct kvm_vcpu_stat {
 	u64 preemption_reported;
 	u64 preemption_other;
 	u64 guest_mode;
+	u64 notify_window_exits;
 };
 
 struct x86_instruction_info;
@@ -1407,6 +1437,7 @@ struct kvm_x86_ops {
 	void (*vm_destroy)(struct kvm *kvm);
 
 	/* Create, but do not attach this VCPU */
+	int (*vcpu_precreate)(struct kvm *kvm);
 	int (*vcpu_create)(struct kvm_vcpu *vcpu);
 	void (*vcpu_free)(struct kvm_vcpu *vcpu);
 	void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
@@ -1471,7 +1502,7 @@ struct kvm_x86_ops {
 	u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
 	void (*patch_hypercall)(struct kvm_vcpu *vcpu,
 				unsigned char *hypercall_addr);
-	void (*inject_irq)(struct kvm_vcpu *vcpu);
+	void (*inject_irq)(struct kvm_vcpu *vcpu, bool reinjected);
 	void (*inject_nmi)(struct kvm_vcpu *vcpu);
 	void (*queue_exception)(struct kvm_vcpu *vcpu);
 	void (*cancel_injection)(struct kvm_vcpu *vcpu);
@@ -1485,7 +1516,7 @@ struct kvm_x86_ops {
 	bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason);
 	void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
 	void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
-	void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
+	void (*hwapic_isr_update)(int isr);
 	bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
 	void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 	void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
@@ -1705,21 +1736,6 @@ extern bool tdp_enabled;
 
 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
 
-/* control of guest tsc rate supported? */
-extern bool kvm_has_tsc_control;
-/* maximum supported tsc_khz for guests */
-extern u32  kvm_max_guest_tsc_khz;
-/* number of bits of the fractional part of the TSC scaling ratio */
-extern u8   kvm_tsc_scaling_ratio_frac_bits;
-/* maximum allowed value of TSC scaling ratio */
-extern u64  kvm_max_tsc_scaling_ratio;
-/* 1ull << kvm_tsc_scaling_ratio_frac_bits */
-extern u64  kvm_default_tsc_scaling_ratio;
-/* bus lock detection supported? */
-extern bool kvm_has_bus_lock_exit;
-
-extern u64 kvm_mce_cap_supported;
-
 /*
  * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
  *			userspace I/O) to indicate that the emulation context
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d27e0581b777..0296f8599fd9 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -221,6 +221,12 @@
 #define PERF_CAP_PT_IDX			16
 
 #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
+#define PERF_CAP_PEBS_TRAP             BIT_ULL(6)
+#define PERF_CAP_ARCH_REG              BIT_ULL(7)
+#define PERF_CAP_PEBS_FORMAT           0xf00
+#define PERF_CAP_PEBS_BASELINE         BIT_ULL(14)
+#define PERF_CAP_PEBS_MASK	(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
+				 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
 
 #define MSR_IA32_RTIT_CTL		0x00000570
 #define RTIT_CTL_TRACEEN		BIT(0)
@@ -1005,6 +1011,7 @@
 #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
 #define MSR_IA32_VMX_VMFUNC             0x00000491
+#define MSR_IA32_VMX_PROCBASED_CTLS3	0x00000492
 
 /* VMX_BASIC bits and bitmasks */
 #define VMX_BASIC_VMCS_SIZE_SHIFT	32
diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h
index 29dd27b5a339..3a8fdf881313 100644
--- a/arch/x86/include/asm/mwait.h
+++ b/arch/x86/include/asm/mwait.h
@@ -13,6 +13,7 @@
 #define MWAIT_SUBSTATE_SIZE		4
 #define MWAIT_HINT2CSTATE(hint)		(((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
 #define MWAIT_HINT2SUBSTATE(hint)	((hint) & MWAIT_CSTATE_MASK)
+#define MWAIT_C1_SUBSTATE_MASK  0xf0
 
 #define CPUID_MWAIT_LEAF		5
 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 409725e86f42..f6fc8dd51ef4 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -89,6 +89,19 @@
 #define AMD64_RAW_EVENT_MASK_NB		\
 	(AMD64_EVENTSEL_EVENT        |  \
 	 ARCH_PERFMON_EVENTSEL_UMASK)
+
+#define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB	\
+	(AMD64_EVENTSEL_EVENT	|		\
+	 GENMASK_ULL(37, 36))
+
+#define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB	\
+	(ARCH_PERFMON_EVENTSEL_UMASK	|	\
+	 GENMASK_ULL(27, 24))
+
+#define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB		\
+	(AMD64_PERFMON_V2_EVENTSEL_EVENT_NB	|	\
+	 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
+
 #define AMD64_NUM_COUNTERS				4
 #define AMD64_NUM_COUNTERS_CORE				6
 #define AMD64_NUM_COUNTERS_NB				4
@@ -194,6 +207,9 @@ union cpuid_0x80000022_ebx {
 	struct {
 		/* Number of Core Performance Counters */
 		unsigned int	num_core_pmc:4;
+		unsigned int	reserved:6;
+		/* Number of Data Fabric Counters */
+		unsigned int	num_df_pmc:6;
 	} split;
 	unsigned int		full;
 };
@@ -206,6 +222,7 @@ struct x86_pmu_capability {
 	int		bit_width_fixed;
 	unsigned int	events_mask;
 	int		events_mask_len;
+	unsigned int	pebs_ept	:1;
 };
 
 /*
@@ -504,6 +521,7 @@ struct x86_pmu_lbr {
 };
 
 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
+extern u64 perf_get_hw_event_config(int hw_event);
 extern void perf_check_microcode(void);
 extern void perf_clear_dirty_counters(void);
 extern int x86_perf_rdpmc_index(struct perf_event *event);
@@ -513,15 +531,20 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 	memset(cap, 0, sizeof(*cap));
 }
 
+static inline u64 perf_get_hw_event_config(int hw_event)
+{
+	return 0;
+}
+
 static inline void perf_events_lapic_init(void)	{ }
 static inline void perf_check_microcode(void) { }
 #endif
 
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
-extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
+extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
 extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
 #else
-struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
+struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
 static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
 {
 	return -1;
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 45b18eb94fa1..35f709f619fb 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -295,6 +295,15 @@ static inline int enqcmds(void __iomem *dst, const void *src)
 	return 0;
 }
 
+static inline void tile_release(void)
+{
+	/*
+	 * Instruction opcode for TILERELEASE; supported in binutils
+	 * version >= 2.36.
+	 */
+	asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0");
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_X86_SPECIAL_INSNS_H */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 6c343c6a1855..c371ef695fcc 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -31,6 +31,7 @@
 #define CPU_BASED_RDTSC_EXITING                 VMCS_CONTROL_BIT(RDTSC_EXITING)
 #define CPU_BASED_CR3_LOAD_EXITING		VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
 #define CPU_BASED_CR3_STORE_EXITING		VMCS_CONTROL_BIT(CR3_STORE_EXITING)
+#define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS	VMCS_CONTROL_BIT(TERTIARY_CONTROLS)
 #define CPU_BASED_CR8_LOAD_EXITING              VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
 #define CPU_BASED_CR8_STORE_EXITING             VMCS_CONTROL_BIT(CR8_STORE_EXITING)
 #define CPU_BASED_TPR_SHADOW                    VMCS_CONTROL_BIT(VIRTUAL_TPR)
@@ -74,6 +75,12 @@
 #define SECONDARY_EXEC_TSC_SCALING              VMCS_CONTROL_BIT(TSC_SCALING)
 #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE	VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
 #define SECONDARY_EXEC_BUS_LOCK_DETECTION	VMCS_CONTROL_BIT(BUS_LOCK_DETECTION)
+#define SECONDARY_EXEC_NOTIFY_VM_EXITING	VMCS_CONTROL_BIT(NOTIFY_VM_EXITING)
+
+/*
+ * Definitions of Tertiary Processor-Based VM-Execution Controls.
+ */
+#define TERTIARY_EXEC_IPI_VIRT			VMCS_CONTROL_BIT(IPI_VIRT)
 
 #define PIN_BASED_EXT_INTR_MASK                 VMCS_CONTROL_BIT(INTR_EXITING)
 #define PIN_BASED_NMI_EXITING                   VMCS_CONTROL_BIT(NMI_EXITING)
@@ -158,6 +165,7 @@ static inline int vmx_misc_mseg_revid(u64 vmx_misc)
 enum vmcs_field {
 	VIRTUAL_PROCESSOR_ID            = 0x00000000,
 	POSTED_INTR_NV                  = 0x00000002,
+	LAST_PID_POINTER_INDEX		= 0x00000008,
 	GUEST_ES_SELECTOR               = 0x00000800,
 	GUEST_CS_SELECTOR               = 0x00000802,
 	GUEST_SS_SELECTOR               = 0x00000804,
@@ -221,6 +229,10 @@ enum vmcs_field {
 	ENCLS_EXITING_BITMAP_HIGH	= 0x0000202F,
 	TSC_MULTIPLIER                  = 0x00002032,
 	TSC_MULTIPLIER_HIGH             = 0x00002033,
+	TERTIARY_VM_EXEC_CONTROL	= 0x00002034,
+	TERTIARY_VM_EXEC_CONTROL_HIGH	= 0x00002035,
+	PID_POINTER_TABLE		= 0x00002042,
+	PID_POINTER_TABLE_HIGH		= 0x00002043,
 	GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 	GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 	VMCS_LINK_POINTER               = 0x00002800,
@@ -269,6 +281,7 @@ enum vmcs_field {
 	SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 	PLE_GAP                         = 0x00004020,
 	PLE_WINDOW                      = 0x00004022,
+	NOTIFY_WINDOW                   = 0x00004024,
 	VM_INSTRUCTION_ERROR            = 0x00004400,
 	VM_EXIT_REASON                  = 0x00004402,
 	VM_EXIT_INTR_INFO               = 0x00004404,
@@ -553,6 +566,11 @@ enum vm_entry_failure_code {
 #define EPT_VIOLATION_GVA_IS_VALID	(1 << EPT_VIOLATION_GVA_IS_VALID_BIT)
 #define EPT_VIOLATION_GVA_TRANSLATED	(1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
 
+/*
+ * Exit Qualifications for NOTIFY VM EXIT
+ */
+#define NOTIFY_VM_CONTEXT_INVALID     BIT(0)
+
 /*
  * VM-instruction error numbers
  */
diff --git a/arch/x86/include/asm/vmxfeatures.h b/arch/x86/include/asm/vmxfeatures.h
index d9a74681a77d..c6a7eed03914 100644
--- a/arch/x86/include/asm/vmxfeatures.h
+++ b/arch/x86/include/asm/vmxfeatures.h
@@ -5,7 +5,7 @@
 /*
  * Defines VMX CPU feature bits
  */
-#define NVMXINTS			3 /* N 32-bit words worth of info */
+#define NVMXINTS			5 /* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -43,6 +43,7 @@
 #define VMX_FEATURE_RDTSC_EXITING	( 1*32+ 12) /* "" VM-Exit on RDTSC */
 #define VMX_FEATURE_CR3_LOAD_EXITING	( 1*32+ 15) /* "" VM-Exit on writes to CR3 */
 #define VMX_FEATURE_CR3_STORE_EXITING	( 1*32+ 16) /* "" VM-Exit on reads from CR3 */
+#define VMX_FEATURE_TERTIARY_CONTROLS	( 1*32+ 17) /* "" Enable Tertiary VM-Execution Controls */
 #define VMX_FEATURE_CR8_LOAD_EXITING	( 1*32+ 19) /* "" VM-Exit on writes to CR8 */
 #define VMX_FEATURE_CR8_STORE_EXITING	( 1*32+ 20) /* "" VM-Exit on reads from CR8 */
 #define VMX_FEATURE_VIRTUAL_TPR		( 1*32+ 21) /* "vtpr" TPR virtualization, a.k.a. TPR shadow */
@@ -84,5 +85,8 @@
 #define VMX_FEATURE_USR_WAIT_PAUSE	( 2*32+ 26) /* Enable TPAUSE, UMONITOR, UMWAIT in guest */
 #define VMX_FEATURE_ENCLV_EXITING	( 2*32+ 28) /* "" VM-Exit on ENCLV (leaf dependent) */
 #define VMX_FEATURE_BUS_LOCK_DETECTION	( 2*32+ 30) /* "" VM-Exit when bus lock caused */
+#define VMX_FEATURE_NOTIFY_VM_EXITING	( 2*32+ 31) /* VM-Exit when no event windows after notify window */
 
+/* Tertiary Processor-Based VM-Execution Controls, word 3 */
+#define VMX_FEATURE_IPI_VIRT		( 3*32+  4) /* Enable IPI virtualization */
 #endif /* _ASM_X86_VMXFEATURES_H */
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
index 21614807a2cb..50a4e787d5e6 100644
--- a/arch/x86/include/uapi/asm/kvm.h
+++ b/arch/x86/include/uapi/asm/kvm.h
@@ -306,7 +306,8 @@ struct kvm_pit_state {
 	struct kvm_pit_channel_state channels[3];
 };
 
-#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
+#define KVM_PIT_FLAGS_HPET_LEGACY     0x00000001
+#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002
 
 struct kvm_pit_state2 {
 	struct kvm_pit_channel_state channels[3];
@@ -325,6 +326,7 @@ struct kvm_reinject_control {
 #define KVM_VCPUEVENT_VALID_SHADOW	0x00000004
 #define KVM_VCPUEVENT_VALID_SMM		0x00000008
 #define KVM_VCPUEVENT_VALID_PAYLOAD	0x00000010
+#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT	0x00000020
 
 /* Interrupt shadow states */
 #define KVM_X86_SHADOW_INT_MOV_SS	0x01
@@ -359,7 +361,10 @@ struct kvm_vcpu_events {
 		__u8 smm_inside_nmi;
 		__u8 latched_init;
 	} smi;
-	__u8 reserved[27];
+	struct {
+		__u8 pending;
+	} triple_fault;
+	__u8 reserved[26];
 	__u8 exception_has_payload;
 	__u64 exception_payload;
 };
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
index 946d761adbd3..a5faf6d88f1b 100644
--- a/arch/x86/include/uapi/asm/vmx.h
+++ b/arch/x86/include/uapi/asm/vmx.h
@@ -91,6 +91,7 @@
 #define EXIT_REASON_UMWAIT              67
 #define EXIT_REASON_TPAUSE              68
 #define EXIT_REASON_BUS_LOCK            74
+#define EXIT_REASON_NOTIFY              75
 
 #define VMX_EXIT_REASONS \
 	{ EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
@@ -153,7 +154,8 @@
 	{ EXIT_REASON_XRSTORS,               "XRSTORS" }, \
 	{ EXIT_REASON_UMWAIT,                "UMWAIT" }, \
 	{ EXIT_REASON_TPAUSE,                "TPAUSE" }, \
-	{ EXIT_REASON_BUS_LOCK,              "BUS_LOCK" }
+	{ EXIT_REASON_BUS_LOCK,              "BUS_LOCK" }, \
+	{ EXIT_REASON_NOTIFY,                "NOTIFY" }
 
 #define VMX_EXIT_REASON_FLAGS \
 	{ VMX_EXIT_REASONS_FAILED_VMENTRY,	"FAILED_VMENTRY" }
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c
index da696eb4821a..993697e71854 100644
--- a/arch/x86/kernel/cpu/feat_ctl.c
+++ b/arch/x86/kernel/cpu/feat_ctl.c
@@ -15,6 +15,8 @@ enum vmx_feature_leafs {
 	MISC_FEATURES = 0,
 	PRIMARY_CTLS,
 	SECONDARY_CTLS,
+	TERTIARY_CTLS_LOW,
+	TERTIARY_CTLS_HIGH,
 	NR_VMX_FEATURE_WORDS,
 };
 
@@ -22,7 +24,7 @@ enum vmx_feature_leafs {
 
 static void init_vmx_capabilities(struct cpuinfo_x86 *c)
 {
-	u32 supported, funcs, ept, vpid, ign;
+	u32 supported, funcs, ept, vpid, ign, low, high;
 
 	BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
 
@@ -42,6 +44,11 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
 	rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
 	c->vmx_capability[SECONDARY_CTLS] = supported;
 
+	/* All 64 bits of tertiary controls MSR are allowed-1 settings. */
+	rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);
+	c->vmx_capability[TERTIARY_CTLS_LOW] = low;
+	c->vmx_capability[TERTIARY_CTLS_HIGH] = high;
+
 	rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);
 	rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);
 
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index 0531d6a06df5..3b28c5b25e12 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -851,3 +851,17 @@ int fpu__exception_code(struct fpu *fpu, int trap_nr)
 	 */
 	return 0;
 }
+
+/*
+ * Initialize register state that may prevent from entering low-power idle.
+ * This function will be invoked from the cpuidle driver only when needed.
+ */
+void fpu_idle_fpregs(void)
+{
+	/* Note: AMX_TILE being enabled implies XGETBV1 support */
+	if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) &&
+	    (xfeatures_in_use() & XFEATURE_MASK_XTILE)) {
+		tile_release();
+		fpregs_deactivate(&current->thread.fpu);
+	}
+}
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 1a3658f7e6d9..d4e48b4a438b 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -236,8 +236,7 @@ void kvm_async_pf_task_wake(u32 token)
 	raw_spin_unlock(&b->lock);
 
 	/* A dummy token might be allocated and ultimately not used.  */
-	if (dummy)
-		kfree(dummy);
+	kfree(dummy);
 }
 EXPORT_SYMBOL_GPL(kvm_async_pf_task_wake);
 
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 9b2772b7e1f3..5d627f8e5e79 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -810,24 +810,43 @@ static void amd_e400_idle(void)
 }
 
 /*
- * Intel Core2 and older machines prefer MWAIT over HALT for C1.
- * We can't rely on cpuidle installing MWAIT, because it will not load
- * on systems that support only C1 -- so the boot default must be MWAIT.
+ * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
+ * exists and whenever MONITOR/MWAIT extensions are present there is at
+ * least one C1 substate.
  *
- * Some AMD machines are the opposite, they depend on using HALT.
- *
- * So for default C1, which is used during boot until cpuidle loads,
- * use MWAIT-C1 on Intel HW that has it, else use HALT.
+ * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
+ * is passed to kernel commandline parameter.
  */
 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 {
-	if (c->x86_vendor != X86_VENDOR_INTEL)
+	u32 eax, ebx, ecx, edx;
+
+	/* User has disallowed the use of MWAIT. Fallback to HALT */
+	if (boot_option_idle_override == IDLE_NOMWAIT)
 		return 0;
 
-	if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
+	/* MWAIT is not supported on this platform. Fallback to HALT */
+	if (!cpu_has(c, X86_FEATURE_MWAIT))
 		return 0;
 
-	return 1;
+	/* Monitor has a bug. Fallback to HALT */
+	if (boot_cpu_has_bug(X86_BUG_MONITOR))
+		return 0;
+
+	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
+
+	/*
+	 * If MWAIT extensions are not available, it is safe to use MWAIT
+	 * with EAX=0, ECX=0.
+	 */
+	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
+		return 1;
+
+	/*
+	 * If MWAIT extensions are available, there should be at least one
+	 * MWAIT C1 substate present.
+	 */
+	return (edx & MWAIT_C1_SUBSTATE_MASK);
 }
 
 /*
@@ -932,9 +951,8 @@ static int __init idle_setup(char *str)
 	} else if (!strcmp(str, "nomwait")) {
 		/*
 		 * If the boot option of "idle=nomwait" is added,
-		 * it means that mwait will be disabled for CPU C2/C3
-		 * states. In such case it won't touch the variable
-		 * of boot_option_idle_override.
+		 * it means that mwait will be disabled for CPU C1/C2/C3
+		 * states.
 		 */
 		boot_option_idle_override = IDLE_NOMWAIT;
 	} else
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index 0c1154a1c403..3b388330a106 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -96,7 +96,7 @@ void __init tboot_probe(void)
 
 static pgd_t *tboot_pg_dir;
 static struct mm_struct tboot_mm = {
-	.mm_rb          = RB_ROOT,
+	.mm_mt          = MTREE_INIT_EXT(mm_mt, MM_MT_FLAGS, tboot_mm.mmap_lock),
 	.pgd            = swapper_pg_dir,
 	.mm_users       = ATOMIC_INIT(2),
 	.mm_count       = ATOMIC_INIT(1),
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index de6d44e07e34..d47222ab8e6e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -200,7 +200,7 @@ void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
 
 /*
  * Calculate guest's supported XCR0 taking into account guest CPUID data and
- * supported_xcr0 (comprised of host configuration and KVM_SUPPORTED_XCR0).
+ * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
  */
 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
 {
@@ -210,7 +210,7 @@ static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
 	if (!best)
 		return 0;
 
-	return (best->eax | ((u64)best->edx << 32)) & supported_xcr0;
+	return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
 }
 
 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
@@ -868,7 +868,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 	case 9:
 		break;
 	case 0xa: { /* Architectural Performance Monitoring */
-		struct x86_pmu_capability cap;
 		union cpuid10_eax eax;
 		union cpuid10_edx edx;
 
@@ -877,30 +876,20 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 			break;
 		}
 
-		perf_get_x86_pmu_capability(&cap);
+		eax.split.version_id = kvm_pmu_cap.version;
+		eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
+		eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
+		eax.split.mask_length = kvm_pmu_cap.events_mask_len;
+		edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
+		edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
 
-		/*
-		 * The guest architecture pmu is only supported if the architecture
-		 * pmu exists on the host and the module parameters allow it.
-		 */
-		if (!cap.version || !enable_pmu)
-			memset(&cap, 0, sizeof(cap));
-
-		eax.split.version_id = min(cap.version, 2);
-		eax.split.num_counters = cap.num_counters_gp;
-		eax.split.bit_width = cap.bit_width_gp;
-		eax.split.mask_length = cap.events_mask_len;
-
-		edx.split.num_counters_fixed =
-			min(cap.num_counters_fixed, KVM_PMC_MAX_FIXED);
-		edx.split.bit_width_fixed = cap.bit_width_fixed;
-		if (cap.version)
+		if (kvm_pmu_cap.version)
 			edx.split.anythread_deprecated = 1;
 		edx.split.reserved1 = 0;
 		edx.split.reserved2 = 0;
 
 		entry->eax = eax.full;
-		entry->ebx = cap.events_mask;
+		entry->ebx = kvm_pmu_cap.events_mask;
 		entry->ecx = 0;
 		entry->edx = edx.full;
 		break;
@@ -923,8 +912,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 		}
 		break;
 	case 0xd: {
-		u64 permitted_xcr0 = supported_xcr0 & xstate_get_guest_group_perm();
-		u64 permitted_xss = supported_xss;
+		u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
+		u64 permitted_xss = kvm_caps.supported_xss;
 
 		entry->eax &= permitted_xcr0;
 		entry->ebx = xstate_required_size(permitted_xcr0, false);
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 8a770b481d9d..ac72aabba981 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -145,6 +145,11 @@ static inline int guest_cpuid_model(struct kvm_vcpu *vcpu)
 	return x86_model(best->eax);
 }
 
+static inline bool cpuid_model_is_consistent(struct kvm_vcpu *vcpu)
+{
+	return boot_cpu_data.x86_model == guest_cpuid_model(vcpu);
+}
+
 static inline int guest_cpuid_stepping(struct kvm_vcpu *vcpu)
 {
 	struct kvm_cpuid_entry2 *best;
diff --git a/arch/x86/kvm/debugfs.c b/arch/x86/kvm/debugfs.c
index 9240b3b7f8dd..cfed36aba2f7 100644
--- a/arch/x86/kvm/debugfs.c
+++ b/arch/x86/kvm/debugfs.c
@@ -48,7 +48,7 @@ DEFINE_SIMPLE_ATTRIBUTE(vcpu_tsc_scaling_fops, vcpu_get_tsc_scaling_ratio, NULL,
 
 static int vcpu_get_tsc_scaling_frac_bits(void *data, u64 *val)
 {
-	*val = kvm_tsc_scaling_ratio_frac_bits;
+	*val = kvm_caps.tsc_scaling_ratio_frac_bits;
 	return 0;
 }
 
@@ -66,7 +66,7 @@ void kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu, struct dentry *debugfs_
 				    debugfs_dentry, vcpu,
 				    &vcpu_timer_advance_ns_fops);
 
-	if (kvm_has_tsc_control) {
+	if (kvm_caps.has_tsc_control) {
 		debugfs_create_file("tsc-scaling-ratio", 0444,
 				    debugfs_dentry, vcpu,
 				    &vcpu_tsc_scaling_fops);
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 89b11e7dca8a..39ea9138224c 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -247,6 +247,9 @@ enum x86_transfer_type {
 
 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
 {
+	if (KVM_EMULATOR_BUG_ON(nr >= NR_EMULATOR_GPRS, ctxt))
+		nr &= NR_EMULATOR_GPRS - 1;
+
 	if (!(ctxt->regs_valid & (1 << nr))) {
 		ctxt->regs_valid |= 1 << nr;
 		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
@@ -256,6 +259,12 @@ static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
 
 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
 {
+	if (KVM_EMULATOR_BUG_ON(nr >= NR_EMULATOR_GPRS, ctxt))
+		nr &= NR_EMULATOR_GPRS - 1;
+
+	BUILD_BUG_ON(sizeof(ctxt->regs_dirty) * BITS_PER_BYTE < NR_EMULATOR_GPRS);
+	BUILD_BUG_ON(sizeof(ctxt->regs_valid) * BITS_PER_BYTE < NR_EMULATOR_GPRS);
+
 	ctxt->regs_valid |= 1 << nr;
 	ctxt->regs_dirty |= 1 << nr;
 	return &ctxt->_regs[nr];
@@ -269,9 +278,10 @@ static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
 
 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
 {
+	unsigned long dirty = ctxt->regs_dirty;
 	unsigned reg;
 
-	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
+	for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS)
 		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
 }
 
@@ -614,7 +624,9 @@ static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
 			     u32 error, bool valid)
 {
-	WARN_ON(vec > 0x1f);
+	if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt))
+		return X86EMUL_UNHANDLEABLE;
+
 	ctxt->exception.vector = vec;
 	ctxt->exception.error_code = error;
 	ctxt->exception.error_code_valid = valid;
@@ -1361,7 +1373,8 @@ static int read_emulated(struct x86_emulate_ctxt *ctxt,
 	if (mc->pos < mc->end)
 		goto read_cached;
 
-	WARN_ON((mc->end + size) >= sizeof(mc->data));
+	if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt))
+		return X86EMUL_UNHANDLEABLE;
 
 	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
 				      &ctxt->exception);
@@ -2431,7 +2444,7 @@ static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt,
 	ctxt->eflags =             GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED;
 	ctxt->_eip =               GET_SMSTATE(u32, smstate, 0x7ff0);
 
-	for (i = 0; i < 8; i++)
+	for (i = 0; i < NR_EMULATOR_GPRS; i++)
 		*reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4);
 
 	val = GET_SMSTATE(u32, smstate, 0x7fcc);
@@ -2488,7 +2501,7 @@ static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt,
 	u16 selector;
 	int i, r;
 
-	for (i = 0; i < 16; i++)
+	for (i = 0; i < NR_EMULATOR_GPRS; i++)
 		*reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8);
 
 	ctxt->_eip   = GET_SMSTATE(u64, smstate, 0x7f78);
@@ -5718,7 +5731,8 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
 
 done:
 	if (rc == X86EMUL_PROPAGATE_FAULT) {
-		WARN_ON(ctxt->exception.vector > 0x1f);
+		if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt))
+			return EMULATION_FAILED;
 		ctxt->have_exception = true;
 	}
 	if (rc == X86EMUL_INTERCEPTED)
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 1c83076091af..e0a7a0e7a73c 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -591,7 +591,10 @@ static int speaker_ioport_write(struct kvm_vcpu *vcpu,
 		return -EOPNOTSUPP;
 
 	mutex_lock(&pit_state->lock);
-	pit_state->speaker_data_on = (val >> 1) & 1;
+	if (val & (1 << 1))
+		pit_state->flags |= KVM_PIT_FLAGS_SPEAKER_DATA_ON;
+	else
+		pit_state->flags &= ~KVM_PIT_FLAGS_SPEAKER_DATA_ON;
 	pit_set_gate(pit, 2, val & 1);
 	mutex_unlock(&pit_state->lock);
 	return 0;
@@ -612,8 +615,9 @@ static int speaker_ioport_read(struct kvm_vcpu *vcpu,
 	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
 
 	mutex_lock(&pit_state->lock);
-	ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(pit, 2) |
-		(pit_get_out(pit, 2) << 5) | (refresh_clock << 4));
+	ret = (!!(pit_state->flags & KVM_PIT_FLAGS_SPEAKER_DATA_ON) << 1) |
+		pit_get_gate(pit, 2) | (pit_get_out(pit, 2) << 5) |
+		(refresh_clock << 4);
 	if (len > sizeof(ret))
 		len = sizeof(ret);
 	memcpy(data, (char *)&ret, len);
diff --git a/arch/x86/kvm/i8254.h b/arch/x86/kvm/i8254.h
index 394d9527da7e..a768212ba821 100644
--- a/arch/x86/kvm/i8254.h
+++ b/arch/x86/kvm/i8254.h
@@ -29,7 +29,6 @@ struct kvm_kpit_state {
 	bool is_periodic;
 	s64 period; 				/* unit: ns */
 	struct hrtimer timer;
-	u32    speaker_data_on;
 
 	struct mutex lock;
 	atomic_t reinject;
diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h
index 8dff25d267b7..89246446d6aa 100644
--- a/arch/x86/kvm/kvm_emulate.h
+++ b/arch/x86/kvm/kvm_emulate.h
@@ -89,6 +89,7 @@ struct x86_instruction_info {
 #define X86EMUL_INTERCEPTED     6 /* Intercepted by nested VMCB/VMCS */
 
 struct x86_emulate_ops {
+	void (*vm_bugged)(struct x86_emulate_ctxt *ctxt);
 	/*
 	 * read_gpr: read a general purpose register (rax - r15)
 	 *
@@ -301,6 +302,18 @@ struct fastop;
 
 typedef void (*fastop_t)(struct fastop *);
 
+/*
+ * The emulator's _regs array tracks only the GPRs, i.e. excludes RIP.  RIP is
+ * tracked/accessed via _eip, and except for RIP relative addressing, which
+ * also uses _eip, RIP cannot be a register operand nor can it be an operand in
+ * a ModRM or SIB byte.
+ */
+#ifdef CONFIG_X86_64
+#define NR_EMULATOR_GPRS	16
+#else
+#define NR_EMULATOR_GPRS	8
+#endif
+
 struct x86_emulate_ctxt {
 	void *vcpu;
 	const struct x86_emulate_ops *ops;
@@ -345,9 +358,9 @@ struct x86_emulate_ctxt {
 	u8 lock_prefix;
 	u8 rep_prefix;
 	/* bitmaps of registers in _regs[] that can be read */
-	u32 regs_valid;
+	u16 regs_valid;
 	/* bitmaps of registers in _regs[] that have been written */
-	u32 regs_dirty;
+	u16 regs_dirty;
 	/* modrm */
 	u8 modrm;
 	u8 modrm_mod;
@@ -363,7 +376,7 @@ struct x86_emulate_ctxt {
 	struct operand src2;
 	struct operand dst;
 	struct operand memop;
-	unsigned long _regs[NR_VCPU_REGS];
+	unsigned long _regs[NR_EMULATOR_GPRS];
 	struct operand *memopp;
 	struct fetch_cache fetch;
 	struct read_cache io_read;
@@ -371,6 +384,15 @@ struct x86_emulate_ctxt {
 	bool is_branch;
 };
 
+#define KVM_EMULATOR_BUG_ON(cond, ctxt)		\
+({						\
+	int __ret = (cond);			\
+						\
+	if (WARN_ON_ONCE(__ret))		\
+		ctxt->ops->vm_bugged(ctxt);	\
+	unlikely(__ret);			\
+})
+
 /* Repeat String Operation Prefix */
 #define REPE_PREFIX	0xf3
 #define REPNE_PREFIX	0xf2
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0e68b4c937fc..43c42a580295 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -67,6 +67,7 @@ static bool lapic_timer_advance_dynamic __read_mostly;
 #define LAPIC_TIMER_ADVANCE_NS_MAX     5000
 /* step-by-step approximation to mitigate fluctuation */
 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
+static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
 
 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
 {
@@ -518,14 +519,11 @@ static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 
 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 {
-	struct kvm_vcpu *vcpu;
-
-	vcpu = apic->vcpu;
-
-	if (unlikely(vcpu->arch.apicv_active)) {
+	if (unlikely(apic->apicv_active)) {
 		/* need to update RVI */
 		kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
-		static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));
+		static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu,
+							    apic_find_highest_irr(apic));
 	} else {
 		apic->irr_pending = false;
 		kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
@@ -542,20 +540,16 @@ EXPORT_SYMBOL_GPL(kvm_apic_clear_irr);
 
 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 {
-	struct kvm_vcpu *vcpu;
-
 	if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 		return;
 
-	vcpu = apic->vcpu;
-
 	/*
 	 * With APIC virtualization enabled, all caching is disabled
 	 * because the processor can modify ISR under the hood.  Instead
 	 * just set SVI.
 	 */
-	if (unlikely(vcpu->arch.apicv_active))
-		static_call_cond(kvm_x86_hwapic_isr_update)(vcpu, vec);
+	if (unlikely(apic->apicv_active))
+		static_call_cond(kvm_x86_hwapic_isr_update)(vec);
 	else {
 		++apic->isr_count;
 		BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
@@ -589,12 +583,9 @@ static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 
 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 {
-	struct kvm_vcpu *vcpu;
 	if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 		return;
 
-	vcpu = apic->vcpu;
-
 	/*
 	 * We do get here for APIC virtualization enabled if the guest
 	 * uses the Hyper-V APIC enlightenment.  In this case we may need
@@ -602,8 +593,8 @@ static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 	 * on the other hand isr_count and highest_isr_cache are unused
 	 * and must be left alone.
 	 */
-	if (unlikely(vcpu->arch.apicv_active))
-		static_call_cond(kvm_x86_hwapic_isr_update)(vcpu, apic_find_highest_isr(apic));
+	if (unlikely(apic->apicv_active))
+		static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic));
 	else {
 		--apic->isr_count;
 		BUG_ON(apic->isr_count < 0);
@@ -1583,7 +1574,7 @@ static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
 		int vec = reg & APIC_VECTOR_MASK;
 		void *bitmap = apic->regs + APIC_ISR;
 
-		if (vcpu->arch.apicv_active)
+		if (apic->apicv_active)
 			bitmap = apic->regs + APIC_IRR;
 
 		if (apic_test_vector(vec, bitmap))
@@ -1602,7 +1593,7 @@ static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
 	 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
 	 * always for VMX enabled hardware.
 	 */
-	if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
+	if (vcpu->arch.tsc_scaling_ratio == kvm_caps.default_tsc_scaling_ratio) {
 		__delay(min(guest_cycles,
 			nsec_to_cycles(vcpu, timer_advance_ns)));
 	} else {
@@ -1700,7 +1691,7 @@ static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
 	if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
 		ktimer->expired_tscdeadline = ktimer->tscdeadline;
 
-	if (!from_timer_fn && vcpu->arch.apicv_active) {
+	if (!from_timer_fn && apic->apicv_active) {
 		WARN_ON(kvm_get_running_vcpu() != vcpu);
 		kvm_apic_inject_pending_timer_irqs(apic);
 		return;
@@ -2246,10 +2237,27 @@ EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
 /* emulate APIC access in a trap manner */
 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
 {
-	u32 val = kvm_lapic_get_reg(vcpu->arch.apic, offset);
+	struct kvm_lapic *apic = vcpu->arch.apic;
+	u64 val;
+
+	if (apic_x2apic_mode(apic)) {
+		/*
+		 * When guest APIC is in x2APIC mode and IPI virtualization
+		 * is enabled, accessing APIC_ICR may cause trap-like VM-exit
+		 * on Intel hardware. Other offsets are not possible.
+		 */
+		if (WARN_ON_ONCE(offset != APIC_ICR))
+			return;
 
-	/* TODO: optimize to just emulate side effect w/o one more write */
-	kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
+		kvm_lapic_msr_read(apic, offset, &val);
+		kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));
+		trace_kvm_apic_write(APIC_ICR, val);
+	} else {
+		val = kvm_lapic_get_reg(apic, offset);
+
+		/* TODO: optimize to just emulate side effect w/o one more write */
+		kvm_lapic_reg_write(apic, offset, (u32)val);
+	}
 }
 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
 
@@ -2361,7 +2369,7 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
 {
 	struct kvm_lapic *apic = vcpu->arch.apic;
 
-	if (vcpu->arch.apicv_active) {
+	if (apic->apicv_active) {
 		/* irr_pending is always true when apicv is activated. */
 		apic->irr_pending = true;
 		apic->isr_count = 1;
@@ -2436,10 +2444,10 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
 
 	vcpu->arch.pv_eoi.msr_val = 0;
 	apic_update_ppr(apic);
-	if (vcpu->arch.apicv_active) {
+	if (apic->apicv_active) {
 		static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu);
 		static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, -1);
-		static_call_cond(kvm_x86_hwapic_isr_update)(vcpu, -1);
+		static_call_cond(kvm_x86_hwapic_isr_update)(-1);
 	}
 
 	vcpu->arch.apic_arb_prio = 0;
@@ -2716,10 +2724,10 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
 	kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
 	kvm_apic_update_apicv(vcpu);
 	apic->highest_isr_cache = -1;
-	if (vcpu->arch.apicv_active) {
+	if (apic->apicv_active) {
 		static_call_cond(kvm_x86_apicv_post_state_restore)(vcpu);
 		static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));
-		static_call_cond(kvm_x86_hwapic_isr_update)(vcpu, apic_find_highest_isr(apic));
+		static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic));
 	}
 	kvm_make_request(KVM_REQ_EVENT, vcpu);
 	if (ioapic_in_kernel(vcpu->kvm))
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 65bb2a8cf145..6207b64b1281 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -48,6 +48,7 @@ struct kvm_lapic {
 	struct kvm_timer lapic_timer;
 	u32 divide_count;
 	struct kvm_vcpu *vcpu;
+	bool apicv_active;
 	bool sw_enabled;
 	bool irr_pending;
 	bool lvt0_in_nmi_mode;
@@ -204,7 +205,7 @@ static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 
 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
 {
-	return vcpu->arch.apic && vcpu->arch.apicv_active;
+	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
 }
 
 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index f8192864b496..a99acec925eb 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -6,11 +6,6 @@
 #include "kvm_cache_regs.h"
 #include "cpuid.h"
 
-#define PT64_PT_BITS 9
-#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
-#define PT32_PT_BITS 10
-#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
-
 #define PT_WRITABLE_SHIFT 1
 #define PT_USER_SHIFT 2
 
@@ -34,11 +29,6 @@
 #define PT_DIR_PAT_SHIFT 12
 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
 
-#define PT32_DIR_PSE36_SIZE 4
-#define PT32_DIR_PSE36_SHIFT 13
-#define PT32_DIR_PSE36_MASK \
-	(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
-
 #define PT64_ROOT_5LEVEL 5
 #define PT64_ROOT_4LEVEL 4
 #define PT32_ROOT_LEVEL 2
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 17252f39bd7c..651ea363b02d 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -53,8 +53,6 @@
 #include <asm/kvm_page_track.h>
 #include "trace.h"
 
-#include "paging.h"
-
 extern bool itlb_multihit_kvm_mitigation;
 
 int __read_mostly nx_huge_pages = -1;
@@ -111,26 +109,6 @@ module_param(dbg, bool, 0644);
 
 #define PTE_PREFETCH_NUM		8
 
-#define PT32_LEVEL_BITS 10
-
-#define PT32_LEVEL_SHIFT(level) \
-		(PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
-
-#define PT32_LVL_OFFSET_MASK(level) \
-	(PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
-						* PT32_LEVEL_BITS))) - 1))
-
-#define PT32_INDEX(address, level)\
-	(((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
-
-
-#define PT32_BASE_ADDR_MASK PAGE_MASK
-#define PT32_DIR_BASE_ADDR_MASK \
-	(PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
-#define PT32_LVL_ADDR_MASK(level) \
-	(PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
-					    * PT32_LEVEL_BITS))) - 1))
-
 #include <trace/events/kvm.h>
 
 /* make pte_list_desc fit well in cache lines */
@@ -326,13 +304,6 @@ static int is_cpuid_PSE36(void)
 	return 1;
 }
 
-static gfn_t pse36_gfn_delta(u32 gpte)
-{
-	int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
-
-	return (gpte & PT32_DIR_PSE36_MASK) << shift;
-}
-
 #ifdef CONFIG_X86_64
 static void __set_spte(u64 *sptep, u64 spte)
 {
@@ -563,6 +534,7 @@ static int mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
 	kvm_pfn_t pfn;
 	u64 old_spte = *sptep;
 	int level = sptep_to_sp(sptep)->role.level;
+	struct page *page;
 
 	if (!is_shadow_present_pte(old_spte) ||
 	    !spte_has_volatile_bits(old_spte))
@@ -578,11 +550,13 @@ static int mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
 	pfn = spte_to_pfn(old_spte);
 
 	/*
-	 * KVM does not hold the refcount of the page used by
-	 * kvm mmu, before reclaiming the page, we should
-	 * unmap it from mmu first.
+	 * KVM doesn't hold a reference to any pages mapped into the guest, and
+	 * instead uses the mmu_notifier to ensure that KVM unmaps any pages
+	 * before they are reclaimed.  Sanity check that, if the pfn is backed
+	 * by a refcounted page, the refcount is elevated.
 	 */
-	WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
+	page = kvm_pfn_to_refcounted_page(pfn);
+	WARN_ON(page && !page_count(page));
 
 	if (is_accessed_spte(old_spte))
 		kvm_set_pfn_accessed(pfn);
@@ -717,7 +691,7 @@ static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
 	if (!sp->role.direct)
 		return sp->gfns[index];
 
-	return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
+	return sp->gfn + (index << ((sp->role.level - 1) * SPTE_LEVEL_BITS));
 }
 
 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
@@ -1789,7 +1763,7 @@ static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
 			continue;
 		}
 
-		child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
+		child = to_shadow_page(ent & SPTE_BASE_ADDR_MASK);
 
 		if (child->unsync_children) {
 			if (mmu_pages_add(pvec, child, i))
@@ -2040,8 +2014,24 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
 	role.direct = direct;
 	role.access = access;
 	if (role.has_4_byte_gpte) {
-		quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
-		quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
+		/*
+		 * If the guest has 4-byte PTEs then that means it's using 32-bit,
+		 * 2-level, non-PAE paging. KVM shadows such guests with PAE paging
+		 * (i.e. 8-byte PTEs). The difference in PTE size means that KVM must
+		 * shadow each guest page table with multiple shadow page tables, which
+		 * requires extra bookkeeping in the role.
+		 *
+		 * Specifically, to shadow the guest's page directory (which covers a
+		 * 4GiB address space), KVM uses 4 PAE page directories, each mapping
+		 * 1GiB of the address space. @role.quadrant encodes which quarter of
+		 * the address space each maps.
+		 *
+		 * To shadow the guest's page tables (which each map a 4MiB region), KVM
+		 * uses 2 PAE page tables, each mapping a 2MiB region. For these,
+		 * @role.quadrant encodes which half of the region they map.
+		 */
+		quadrant = gaddr >> (PAGE_SHIFT + (SPTE_LEVEL_BITS * level));
+		quadrant &= (1 << level) - 1;
 		role.quadrant = quadrant;
 	}
 	if (level <= vcpu->arch.mmu->cpu_role.base.level)
@@ -2145,7 +2135,7 @@ static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterato
 
 		iterator->shadow_addr
 			= vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
-		iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
+		iterator->shadow_addr &= SPTE_BASE_ADDR_MASK;
 		--iterator->level;
 		if (!iterator->shadow_addr)
 			iterator->level = 0;
@@ -2164,7 +2154,7 @@ static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
 	if (iterator->level < PG_LEVEL_4K)
 		return false;
 
-	iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
+	iterator->index = SPTE_INDEX(iterator->addr, iterator->level);
 	iterator->sptep	= ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
 	return true;
 }
@@ -2177,7 +2167,7 @@ static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
 		return;
 	}
 
-	iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
+	iterator->shadow_addr = spte & SPTE_BASE_ADDR_MASK;
 	--iterator->level;
 }
 
@@ -2216,7 +2206,7 @@ static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
 		 * so we should update the spte at this point to get
 		 * a new sp with the correct access.
 		 */
-		child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
+		child = to_shadow_page(*sptep & SPTE_BASE_ADDR_MASK);
 		if (child->role.access == direct_access)
 			return;
 
@@ -2237,7 +2227,7 @@ static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
 		if (is_last_spte(pte, sp->role.level)) {
 			drop_spte(kvm, spte);
 		} else {
-			child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
+			child = to_shadow_page(pte & SPTE_BASE_ADDR_MASK);
 			drop_parent_pte(child, spte);
 
 			/*
@@ -2263,7 +2253,7 @@ static int kvm_mmu_page_unlink_children(struct kvm *kvm,
 	int zapped = 0;
 	unsigned i;
 
-	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
+	for (i = 0; i < SPTE_ENT_PER_PAGE; ++i)
 		zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
 
 	return zapped;
@@ -2676,7 +2666,7 @@ static int mmu_set_spte(struct kvm_vcpu *vcpu, struct kvm_memory_slot *slot,
 			struct kvm_mmu_page *child;
 			u64 pte = *sptep;
 
-			child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
+			child = to_shadow_page(pte & SPTE_BASE_ADDR_MASK);
 			drop_parent_pte(child, sptep);
 			flush = true;
 		} else if (pfn != spte_to_pfn(*sptep)) {
@@ -2801,15 +2791,24 @@ static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
 				  const struct kvm_memory_slot *slot)
 {
+	int level = PG_LEVEL_4K;
+	struct page *page;
 	unsigned long hva;
 	unsigned long flags;
-	int level = PG_LEVEL_4K;
 	pgd_t pgd;
 	p4d_t p4d;
 	pud_t pud;
 	pmd_t pmd;
 
-	if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
+	/*
+	 * Note, @slot must be non-NULL, i.e. the caller is responsible for
+	 * ensuring @pfn isn't garbage and is backed by a memslot.
+	 */
+	page = kvm_pfn_to_refcounted_page(pfn);
+	if (!page)
+		return PG_LEVEL_4K;
+
+	if (!PageCompound(page) && !kvm_is_zone_device_page(page))
 		return PG_LEVEL_4K;
 
 	/*
@@ -2893,7 +2892,7 @@ void kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault
 	if (unlikely(fault->max_level == PG_LEVEL_4K))
 		return;
 
-	if (is_error_noslot_pfn(fault->pfn) || kvm_is_reserved_pfn(fault->pfn))
+	if (is_error_noslot_pfn(fault->pfn))
 		return;
 
 	if (kvm_slot_dirty_track_enabled(slot))
@@ -3095,7 +3094,7 @@ fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
 	 *
 	 * Compare with set_spte where instead shadow_dirty_mask is set.
 	 */
-	if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
+	if (!try_cmpxchg64(sptep, &old_spte, new_spte))
 		return false;
 
 	if (is_writable_pte(new_spte) && !is_writable_pte(old_spte))
@@ -3265,7 +3264,7 @@ static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
 	if (!VALID_PAGE(*root_hpa))
 		return;
 
-	sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
+	sp = to_shadow_page(*root_hpa & SPTE_BASE_ADDR_MASK);
 	if (WARN_ON(!sp))
 		return;
 
@@ -3737,7 +3736,7 @@ void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
 		hpa_t root = vcpu->arch.mmu->pae_root[i];
 
 		if (IS_VALID_PAE_ROOT(root)) {
-			root &= PT64_BASE_ADDR_MASK;
+			root &= SPTE_BASE_ADDR_MASK;
 			sp = to_shadow_page(root);
 			mmu_sync_children(vcpu, sp, true);
 		}
@@ -5199,11 +5198,11 @@ static bool need_remote_flush(u64 old, u64 new)
 		return false;
 	if (!is_shadow_present_pte(new))
 		return true;
-	if ((old ^ new) & PT64_BASE_ADDR_MASK)
+	if ((old ^ new) & SPTE_BASE_ADDR_MASK)
 		return true;
 	old ^= shadow_nx_mask;
 	new ^= shadow_nx_mask;
-	return (old & ~new & PT64_PERM_MASK) != 0;
+	return (old & ~new & SPTE_PERM_MASK) != 0;
 }
 
 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
@@ -5328,13 +5327,6 @@ static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
 
 	pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
 
-	/*
-	 * No need to care whether allocation memory is successful
-	 * or not since pte prefetch is skipped if it does not have
-	 * enough objects in the cache.
-	 */
-	mmu_topup_memory_caches(vcpu, true);
-
 	write_lock(&vcpu->kvm->mmu_lock);
 
 	gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
@@ -6012,7 +6004,7 @@ static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
 		 * the guest, and the guest page table is using 4K page size
 		 * mapping if the indirect sp has level = 1.
 		 */
-		if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
+		if (sp->role.direct &&
 		    sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
 							       pfn, PG_LEVEL_NUM)) {
 			pte_list_remove(kvm, rmap_head, sptep);
@@ -6317,7 +6309,7 @@ int kvm_mmu_vendor_module_init(void)
 	if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
 		goto out;
 
-	ret = register_shrinker(&mmu_shrinker);
+	ret = register_shrinker(&mmu_shrinker, "x86-mmu");
 	if (ret)
 		goto out;
 
diff --git a/arch/x86/kvm/mmu/mmu_internal.h b/arch/x86/kvm/mmu/mmu_internal.h
index bd2a26897b97..5e1e3c8f8aaa 100644
--- a/arch/x86/kvm/mmu/mmu_internal.h
+++ b/arch/x86/kvm/mmu/mmu_internal.h
@@ -20,6 +20,20 @@ extern bool dbg;
 #define MMU_WARN_ON(x) do { } while (0)
 #endif
 
+/* Page table builder macros common to shadow (host) PTEs and guest PTEs. */
+#define __PT_LEVEL_SHIFT(level, bits_per_level)	\
+	(PAGE_SHIFT + ((level) - 1) * (bits_per_level))
+#define __PT_INDEX(address, level, bits_per_level) \
+	(((address) >> __PT_LEVEL_SHIFT(level, bits_per_level)) & ((1 << (bits_per_level)) - 1))
+
+#define __PT_LVL_ADDR_MASK(base_addr_mask, level, bits_per_level) \
+	((base_addr_mask) & ~((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))
+
+#define __PT_LVL_OFFSET_MASK(base_addr_mask, level, bits_per_level) \
+	((base_addr_mask) & ((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))
+
+#define __PT_ENT_PER_PAGE(bits_per_level)  (1 << (bits_per_level))
+
 /*
  * Unlike regular MMU roots, PAE "roots", a.k.a. PDPTEs/PDPTRs, have a PRESENT
  * bit, and thus are guaranteed to be non-zero when valid.  And, when a guest
diff --git a/arch/x86/kvm/mmu/paging.h b/arch/x86/kvm/mmu/paging.h
deleted file mode 100644
index de8ab323bb70..000000000000
--- a/arch/x86/kvm/mmu/paging.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Shadow paging constants/helpers that don't need to be #undef'd. */
-#ifndef __KVM_X86_PAGING_H
-#define __KVM_X86_PAGING_H
-
-#define GUEST_PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
-#define PT64_LVL_ADDR_MASK(level) \
-	(GUEST_PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
-						* PT64_LEVEL_BITS))) - 1))
-#define PT64_LVL_OFFSET_MASK(level) \
-	(GUEST_PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
-						* PT64_LEVEL_BITS))) - 1))
-#endif /* __KVM_X86_PAGING_H */
-
diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h
index db80f7ccaa4e..e4655056e651 100644
--- a/arch/x86/kvm/mmu/paging_tmpl.h
+++ b/arch/x86/kvm/mmu/paging_tmpl.h
@@ -16,25 +16,21 @@
  */
 
 /*
- * We need the mmu code to access both 32-bit and 64-bit guest ptes,
- * so the code in this file is compiled twice, once per pte size.
+ * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
+ * as well as guest EPT tables, so the code in this file is compiled thrice,
+ * once per guest PTE type.  The per-type defines are #undef'd at the end.
  */
 
 #if PTTYPE == 64
 	#define pt_element_t u64
 	#define guest_walker guest_walker64
 	#define FNAME(name) paging##64_##name
-	#define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
-	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
-	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
-	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
-	#define PT_LEVEL_BITS PT64_LEVEL_BITS
+	#define PT_LEVEL_BITS 9
 	#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
 	#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
 	#define PT_HAVE_ACCESSED_DIRTY(mmu) true
 	#ifdef CONFIG_X86_64
 	#define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
-	#define CMPXCHG "cmpxchgq"
 	#else
 	#define PT_MAX_FULL_LEVELS 2
 	#endif
@@ -42,36 +38,35 @@
 	#define pt_element_t u32
 	#define guest_walker guest_walker32
 	#define FNAME(name) paging##32_##name
-	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
-	#define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
-	#define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
-	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
-	#define PT_LEVEL_BITS PT32_LEVEL_BITS
+	#define PT_LEVEL_BITS 10
 	#define PT_MAX_FULL_LEVELS 2
 	#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
 	#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
 	#define PT_HAVE_ACCESSED_DIRTY(mmu) true
-	#define CMPXCHG "cmpxchgl"
+
+	#define PT32_DIR_PSE36_SIZE 4
+	#define PT32_DIR_PSE36_SHIFT 13
+	#define PT32_DIR_PSE36_MASK \
+		(((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
 #elif PTTYPE == PTTYPE_EPT
 	#define pt_element_t u64
 	#define guest_walker guest_walkerEPT
 	#define FNAME(name) ept_##name
-	#define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
-	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
-	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
-	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
-	#define PT_LEVEL_BITS PT64_LEVEL_BITS
+	#define PT_LEVEL_BITS 9
 	#define PT_GUEST_DIRTY_SHIFT 9
 	#define PT_GUEST_ACCESSED_SHIFT 8
 	#define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled)
-	#ifdef CONFIG_X86_64
-	#define CMPXCHG "cmpxchgq"
-	#endif
 	#define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
 #else
 	#error Invalid PTTYPE value
 #endif
 
+/* Common logic, but per-type values.  These also need to be undefined. */
+#define PT_BASE_ADDR_MASK	((pt_element_t)(((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
+#define PT_LVL_ADDR_MASK(lvl)	__PT_LVL_ADDR_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
+#define PT_LVL_OFFSET_MASK(lvl)	__PT_LVL_OFFSET_MASK(PT_BASE_ADDR_MASK, lvl, PT_LEVEL_BITS)
+#define PT_INDEX(addr, lvl)	__PT_INDEX(addr, lvl, PT_LEVEL_BITS)
+
 #define PT_GUEST_DIRTY_MASK    (1 << PT_GUEST_DIRTY_SHIFT)
 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
 
@@ -97,6 +92,15 @@ struct guest_walker {
 	struct x86_exception fault;
 };
 
+#if PTTYPE == 32
+static inline gfn_t pse36_gfn_delta(u32 gpte)
+{
+	int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
+
+	return (gpte & PT32_DIR_PSE36_MASK) << shift;
+}
+#endif
+
 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
 {
 	return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
@@ -421,8 +425,10 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
 	gfn = gpte_to_gfn_lvl(pte, walker->level);
 	gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
 
-	if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
+#if PTTYPE == 32
+	if (walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
 		gfn += pse36_gfn_delta(pte);
+#endif
 
 	real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(gfn), access, &walker->fault);
 	if (real_gpa == UNMAPPED_GVA)
@@ -888,7 +894,7 @@ static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
 	WARN_ON(sp->role.level != PG_LEVEL_4K);
 
 	if (PTTYPE == 32)
-		offset = sp->role.quadrant << PT64_LEVEL_BITS;
+		offset = sp->role.quadrant << SPTE_LEVEL_BITS;
 
 	return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
 }
@@ -1023,7 +1029,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 
 	first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
 
-	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
+	for (i = 0; i < SPTE_ENT_PER_PAGE; i++) {
 		u64 *sptep, spte;
 		struct kvm_memory_slot *slot;
 		unsigned pte_access;
@@ -1053,7 +1059,14 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 		if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access))
 			continue;
 
-		if (gfn != sp->gfns[i]) {
+		/*
+		 * Drop the SPTE if the new protections would result in a RWX=0
+		 * SPTE or if the gfn is changing.  The RWX=0 case only affects
+		 * EPT with execute-only support, i.e. EPT without an effective
+		 * "present" bit, as all other paging modes will create a
+		 * read-only SPTE if pte_access is zero.
+		 */
+		if ((!pte_access && !shadow_present_mask) || gfn != sp->gfns[i]) {
 			drop_spte(vcpu->kvm, &sp->spt[i]);
 			flush = true;
 			continue;
@@ -1070,6 +1083,15 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 		flush |= mmu_spte_update(sptep, spte);
 	}
 
+	/*
+	 * Note, any flush is purely for KVM's correctness, e.g. when dropping
+	 * an existing SPTE or clearing W/A/D bits to ensure an mmu_notifier
+	 * unmap or dirty logging event doesn't fail to flush.  The guest is
+	 * responsible for flushing the TLB to ensure any changes in protection
+	 * bits are recognized, i.e. until the guest flushes or page faults on
+	 * a relevant address, KVM is architecturally allowed to let vCPUs use
+	 * cached translations with the old protection bits.
+	 */
 	return flush;
 }
 
@@ -1084,7 +1106,6 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 #undef PT_MAX_FULL_LEVELS
 #undef gpte_to_gfn
 #undef gpte_to_gfn_lvl
-#undef CMPXCHG
 #undef PT_GUEST_ACCESSED_MASK
 #undef PT_GUEST_DIRTY_MASK
 #undef PT_GUEST_DIRTY_SHIFT
diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
index b5960bbde7f7..242e4828d7df 100644
--- a/arch/x86/kvm/mmu/spte.c
+++ b/arch/x86/kvm/mmu/spte.c
@@ -129,6 +129,8 @@ bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 	u64 spte = SPTE_MMU_PRESENT_MASK;
 	bool wrprot = false;
 
+	WARN_ON_ONCE(!pte_access && !shadow_present_mask);
+
 	if (sp->role.ad_disabled)
 		spte |= SPTE_TDP_AD_DISABLED_MASK;
 	else if (kvm_mmu_page_ad_need_write_protect(sp))
@@ -299,7 +301,7 @@ u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn)
 {
 	u64 new_spte;
 
-	new_spte = old_spte & ~PT64_BASE_ADDR_MASK;
+	new_spte = old_spte & ~SPTE_BASE_ADDR_MASK;
 	new_spte |= (u64)new_pfn << PAGE_SHIFT;
 
 	new_spte &= ~PT_WRITABLE_MASK;
diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h
index 0127bb6e3c7d..121c5eaaec77 100644
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -36,12 +36,12 @@ extern bool __read_mostly enable_mmio_caching;
 static_assert(SPTE_TDP_AD_ENABLED_MASK == 0);
 
 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
-#define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
+#define SPTE_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
 #else
-#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
+#define SPTE_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
 #endif
 
-#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
+#define SPTE_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
 			| shadow_x_mask | shadow_nx_mask | shadow_me_mask)
 
 #define ACC_EXEC_MASK    1
@@ -50,17 +50,13 @@ static_assert(SPTE_TDP_AD_ENABLED_MASK == 0);
 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
 
 /* The mask for the R/X bits in EPT PTEs */
-#define PT64_EPT_READABLE_MASK			0x1ull
-#define PT64_EPT_EXECUTABLE_MASK		0x4ull
+#define SPTE_EPT_READABLE_MASK			0x1ull
+#define SPTE_EPT_EXECUTABLE_MASK		0x4ull
 
-#define PT64_LEVEL_BITS 9
-
-#define PT64_LEVEL_SHIFT(level) \
-		(PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
-
-#define PT64_INDEX(address, level)\
-	(((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
-#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
+#define SPTE_LEVEL_BITS			9
+#define SPTE_LEVEL_SHIFT(level)		__PT_LEVEL_SHIFT(level, SPTE_LEVEL_BITS)
+#define SPTE_INDEX(address, level)	__PT_INDEX(address, level, SPTE_LEVEL_BITS)
+#define SPTE_ENT_PER_PAGE		__PT_ENT_PER_PAGE(SPTE_LEVEL_BITS)
 
 /*
  * The mask/shift to use for saving the original R/X bits when marking the PTE
@@ -69,8 +65,8 @@ static_assert(SPTE_TDP_AD_ENABLED_MASK == 0);
  * restored only when a write is attempted to the page.  This mask obviously
  * must not overlap the A/D type mask.
  */
-#define SHADOW_ACC_TRACK_SAVED_BITS_MASK (PT64_EPT_READABLE_MASK | \
-					  PT64_EPT_EXECUTABLE_MASK)
+#define SHADOW_ACC_TRACK_SAVED_BITS_MASK (SPTE_EPT_READABLE_MASK | \
+					  SPTE_EPT_EXECUTABLE_MASK)
 #define SHADOW_ACC_TRACK_SAVED_BITS_SHIFT 54
 #define SHADOW_ACC_TRACK_SAVED_MASK	(SHADOW_ACC_TRACK_SAVED_BITS_MASK << \
 					 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
@@ -282,7 +278,7 @@ static inline bool is_executable_pte(u64 spte)
 
 static inline kvm_pfn_t spte_to_pfn(u64 pte)
 {
-	return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
+	return (pte & SPTE_BASE_ADDR_MASK) >> PAGE_SHIFT;
 }
 
 static inline bool is_accessed_spte(u64 spte)
diff --git a/arch/x86/kvm/mmu/tdp_iter.c b/arch/x86/kvm/mmu/tdp_iter.c
index ee4802d7b36c..9c65a64a56d9 100644
--- a/arch/x86/kvm/mmu/tdp_iter.c
+++ b/arch/x86/kvm/mmu/tdp_iter.c
@@ -11,7 +11,7 @@
 static void tdp_iter_refresh_sptep(struct tdp_iter *iter)
 {
 	iter->sptep = iter->pt_path[iter->level - 1] +
-		SHADOW_PT_INDEX(iter->gfn << PAGE_SHIFT, iter->level);
+		SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level);
 	iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep);
 }
 
@@ -116,8 +116,8 @@ static bool try_step_side(struct tdp_iter *iter)
 	 * Check if the iterator is already at the end of the current page
 	 * table.
 	 */
-	if (SHADOW_PT_INDEX(iter->gfn << PAGE_SHIFT, iter->level) ==
-            (PT64_ENT_PER_PAGE - 1))
+	if (SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level) ==
+	    (SPTE_ENT_PER_PAGE - 1))
 		return false;
 
 	iter->gfn += KVM_PAGES_PER_HPAGE(iter->level);
diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index 7b9265d67131..1ea40809ef1f 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -425,7 +425,7 @@ static void handle_removed_pt(struct kvm *kvm, tdp_ptep_t pt, bool shared)
 
 	tdp_mmu_unlink_sp(kvm, sp, shared);
 
-	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
+	for (i = 0; i < SPTE_ENT_PER_PAGE; i++) {
 		tdp_ptep_t sptep = pt + i;
 		gfn_t gfn = base_gfn + i * KVM_PAGES_PER_HPAGE(level);
 		u64 old_spte;
@@ -633,7 +633,6 @@ static inline int tdp_mmu_set_spte_atomic(struct kvm *kvm,
 					  u64 new_spte)
 {
 	u64 *sptep = rcu_dereference(iter->sptep);
-	u64 old_spte;
 
 	/*
 	 * The caller is responsible for ensuring the old SPTE is not a REMOVED
@@ -649,17 +648,8 @@ static inline int tdp_mmu_set_spte_atomic(struct kvm *kvm,
 	 * Note, fast_pf_fix_direct_spte() can also modify TDP MMU SPTEs and
 	 * does not hold the mmu_lock.
 	 */
-	old_spte = cmpxchg64(sptep, iter->old_spte, new_spte);
-	if (old_spte != iter->old_spte) {
-		/*
-		 * The page table entry was modified by a different logical
-		 * CPU. Refresh iter->old_spte with the current value so the
-		 * caller operates on fresh data, e.g. if it retries
-		 * tdp_mmu_set_spte_atomic().
-		 */
-		iter->old_spte = old_spte;
+	if (!try_cmpxchg64(sptep, &iter->old_spte, new_spte))
 		return -EBUSY;
-	}
 
 	__handle_changed_spte(kvm, iter->as_id, iter->gfn, iter->old_spte,
 			      new_spte, iter->level, true);
@@ -1487,7 +1477,7 @@ static int tdp_mmu_split_huge_page(struct kvm *kvm, struct tdp_iter *iter,
 	 * No need for atomics when writing to sp->spt since the page table has
 	 * not been linked in yet and thus is not reachable from any other CPU.
 	 */
-	for (i = 0; i < PT64_ENT_PER_PAGE; i++)
+	for (i = 0; i < SPTE_ENT_PER_PAGE; i++)
 		sp->spt[i] = make_huge_page_split_spte(huge_spte, level, i);
 
 	/*
@@ -1507,7 +1497,7 @@ static int tdp_mmu_split_huge_page(struct kvm *kvm, struct tdp_iter *iter,
 	 * are overwriting from the page stats. But we have to manually update
 	 * the page stats with the new present child pages.
 	 */
-	kvm_update_page_stats(kvm, level - 1, PT64_ENT_PER_PAGE);
+	kvm_update_page_stats(kvm, level - 1, SPTE_ENT_PER_PAGE);
 
 out:
 	trace_kvm_mmu_split_huge_page(iter->gfn, huge_spte, level, ret);
@@ -1760,10 +1750,6 @@ static void zap_collapsible_spte_range(struct kvm *kvm,
 		 * be mapped at a higher level.
 		 */
 		pfn = spte_to_pfn(iter.old_spte);
-
-		if (kvm_is_reserved_pfn(pfn))
-			continue;
-
 		max_mapping_level = kvm_mmu_max_mapping_level(kvm, slot,
 				iter.gfn, pfn, PG_LEVEL_NUM);
 
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 3f868fed9114..6a32092460d3 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -16,6 +16,7 @@
 #include <linux/bsearch.h>
 #include <linux/sort.h>
 #include <asm/perf_event.h>
+#include <asm/cpu_device_id.h>
 #include "x86.h"
 #include "cpuid.h"
 #include "lapic.h"
@@ -24,6 +25,15 @@
 /* This is enough to filter the vast majority of currently defined events. */
 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
 
+struct x86_pmu_capability __read_mostly kvm_pmu_cap;
+EXPORT_SYMBOL_GPL(kvm_pmu_cap);
+
+static const struct x86_cpu_id vmx_icl_pebs_cpu[] = {
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL),
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL),
+	{}
+};
+
 /* NOTE:
  * - Each perf counter is defined as "struct kvm_pmc";
  * - There are two types of perf counters: general purpose (gp) and fixed.
@@ -34,7 +44,9 @@
  *   However AMD doesn't support fixed-counters;
  * - There are three types of index to access perf counters (PMC):
  *     1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
- *        has MSR_K7_PERFCTRn.
+ *        has MSR_K7_PERFCTRn and, for families 15H and later,
+ *        MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are
+ *        aliased to MSR_K7_PERFCTRn.
  *     2. MSR Index (named idx): This normally is used by RDPMC instruction.
  *        For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
  *        C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
@@ -46,7 +58,8 @@
  *        between pmc and perf counters is as the following:
  *        * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
  *                 [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
- *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
+ *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H
+ *          and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters
  */
 
 static struct kvm_pmu_ops kvm_pmu_ops __read_mostly;
@@ -86,15 +99,22 @@ static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
 static inline void __kvm_perf_overflow(struct kvm_pmc *pmc, bool in_pmi)
 {
 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
+	bool skip_pmi = false;
 
 	/* Ignore counters that have been reprogrammed already. */
 	if (test_and_set_bit(pmc->idx, pmu->reprogram_pmi))
 		return;
 
-	__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
+	if (pmc->perf_event && pmc->perf_event->attr.precise_ip) {
+		/* Indicate PEBS overflow PMI to guest. */
+		skip_pmi = __test_and_set_bit(GLOBAL_STATUS_BUFFER_OVF_BIT,
+					      (unsigned long *)&pmu->global_status);
+	} else {
+		__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
+	}
 	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
 
-	if (!pmc->intr)
+	if (!pmc->intr || skip_pmi)
 		return;
 
 	/*
@@ -124,6 +144,7 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 				  u64 config, bool exclude_user,
 				  bool exclude_kernel, bool intr)
 {
+	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 	struct perf_event *event;
 	struct perf_event_attr attr = {
 		.type = type,
@@ -135,9 +156,7 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		.exclude_kernel = exclude_kernel,
 		.config = config,
 	};
-
-	if (type == PERF_TYPE_HARDWARE && config >= PERF_COUNT_HW_MAX)
-		return;
+	bool pebs = test_bit(pmc->idx, (unsigned long *)&pmu->pebs_enable);
 
 	attr.sample_period = get_sample_period(pmc, pmc->counter);
 
@@ -150,6 +169,25 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 		 */
 		attr.sample_period = 0;
 	}
+	if (pebs) {
+		/*
+		 * The non-zero precision level of guest event makes the ordinary
+		 * guest event becomes a guest PEBS event and triggers the host
+		 * PEBS PMI handler to determine whether the PEBS overflow PMI
+		 * comes from the host counters or the guest.
+		 *
+		 * For most PEBS hardware events, the difference in the software
+		 * precision levels of guest and host PEBS events will not affect
+		 * the accuracy of the PEBS profiling result, because the "event IP"
+		 * in the PEBS record is calibrated on the guest side.
+		 *
+		 * On Icelake everything is fine. Other hardware (GLC+, TNT+) that
+		 * could possibly care here is unsupported and needs changes.
+		 */
+		attr.precise_ip = 1;
+		if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32)
+			attr.precise_ip = 3;
+	}
 
 	event = perf_event_create_kernel_counter(&attr, -1, current,
 						 kvm_perf_overflow, pmc);
@@ -163,7 +201,7 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
 	pmc_to_pmu(pmc)->event_count++;
 	clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
 	pmc->is_paused = false;
-	pmc->intr = intr;
+	pmc->intr = intr || pebs;
 }
 
 static void pmc_pause_counter(struct kvm_pmc *pmc)
@@ -189,6 +227,10 @@ static bool pmc_resume_counter(struct kvm_pmc *pmc)
 			      get_sample_period(pmc, pmc->counter)))
 		return false;
 
+	if (!test_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->pebs_enable) &&
+	    pmc->perf_event->attr.precise_ip)
+		return false;
+
 	/* reuse perf_event to serve as pmc_reprogram_counter() does*/
 	perf_event_enable(pmc->perf_event);
 	pmc->is_paused = false;
@@ -205,115 +247,83 @@ static int cmp_u64(const void *pa, const void *pb)
 	return (a > b) - (a < b);
 }
 
-void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
+static bool check_pmu_event_filter(struct kvm_pmc *pmc)
 {
-	u64 config;
-	u32 type = PERF_TYPE_RAW;
-	struct kvm *kvm = pmc->vcpu->kvm;
 	struct kvm_pmu_event_filter *filter;
-	struct kvm_pmu *pmu = vcpu_to_pmu(pmc->vcpu);
+	struct kvm *kvm = pmc->vcpu->kvm;
 	bool allow_event = true;
+	__u64 key;
+	int idx;
 
-	if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
-		printk_once("kvm pmu: pin control bit is ignored\n");
-
-	pmc->eventsel = eventsel;
-
-	pmc_pause_counter(pmc);
-
-	if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
-		return;
+	if (!static_call(kvm_x86_pmu_hw_event_available)(pmc))
+		return false;
 
 	filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
-	if (filter) {
-		__u64 key = eventsel & AMD64_RAW_EVENT_MASK_NB;
+	if (!filter)
+		goto out;
 
+	if (pmc_is_gp(pmc)) {
+		key = pmc->eventsel & AMD64_RAW_EVENT_MASK_NB;
 		if (bsearch(&key, filter->events, filter->nevents,
 			    sizeof(__u64), cmp_u64))
 			allow_event = filter->action == KVM_PMU_EVENT_ALLOW;
 		else
 			allow_event = filter->action == KVM_PMU_EVENT_DENY;
-	}
-	if (!allow_event)
-		return;
-
-	if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
-			  ARCH_PERFMON_EVENTSEL_INV |
-			  ARCH_PERFMON_EVENTSEL_CMASK |
-			  HSW_IN_TX |
-			  HSW_IN_TX_CHECKPOINTED))) {
-		config = static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc);
-		if (config != PERF_COUNT_HW_MAX)
-			type = PERF_TYPE_HARDWARE;
+	} else {
+		idx = pmc->idx - INTEL_PMC_IDX_FIXED;
+		if (filter->action == KVM_PMU_EVENT_DENY &&
+		    test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
+			allow_event = false;
+		if (filter->action == KVM_PMU_EVENT_ALLOW &&
+		    !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
+			allow_event = false;
 	}
 
-	if (type == PERF_TYPE_RAW)
-		config = eventsel & pmu->raw_event_mask;
-
-	if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
-		return;
-
-	pmc_release_perf_event(pmc);
-
-	pmc->current_config = eventsel;
-	pmc_reprogram_counter(pmc, type, config,
-			      !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
-			      !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
-			      eventsel & ARCH_PERFMON_EVENTSEL_INT);
+out:
+	return allow_event;
 }
-EXPORT_SYMBOL_GPL(reprogram_gp_counter);
 
-void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
+void reprogram_counter(struct kvm_pmc *pmc)
 {
-	unsigned en_field = ctrl & 0x3;
-	bool pmi = ctrl & 0x8;
-	struct kvm_pmu_event_filter *filter;
-	struct kvm *kvm = pmc->vcpu->kvm;
+	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
+	u64 eventsel = pmc->eventsel;
+	u64 new_config = eventsel;
+	u8 fixed_ctr_ctrl;
 
 	pmc_pause_counter(pmc);
 
-	if (!en_field || !pmc_is_enabled(pmc))
+	if (!pmc_speculative_in_use(pmc) || !pmc_is_enabled(pmc))
 		return;
 
-	filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
-	if (filter) {
-		if (filter->action == KVM_PMU_EVENT_DENY &&
-		    test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
-			return;
-		if (filter->action == KVM_PMU_EVENT_ALLOW &&
-		    !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
-			return;
-	}
-
-	if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
+	if (!check_pmu_event_filter(pmc))
 		return;
 
-	pmc_release_perf_event(pmc);
-
-	pmc->current_config = (u64)ctrl;
-	pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
-			      static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc),
-			      !(en_field & 0x2), /* exclude user */
-			      !(en_field & 0x1), /* exclude kernel */
-			      pmi);
-}
-EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
+	if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
+		printk_once("kvm pmu: pin control bit is ignored\n");
 
-void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
-{
-	struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, pmc_idx);
+	if (pmc_is_fixed(pmc)) {
+		fixed_ctr_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl,
+						  pmc->idx - INTEL_PMC_IDX_FIXED);
+		if (fixed_ctr_ctrl & 0x1)
+			eventsel |= ARCH_PERFMON_EVENTSEL_OS;
+		if (fixed_ctr_ctrl & 0x2)
+			eventsel |= ARCH_PERFMON_EVENTSEL_USR;
+		if (fixed_ctr_ctrl & 0x8)
+			eventsel |= ARCH_PERFMON_EVENTSEL_INT;
+		new_config = (u64)fixed_ctr_ctrl;
+	}
 
-	if (!pmc)
+	if (pmc->current_config == new_config && pmc_resume_counter(pmc))
 		return;
 
-	if (pmc_is_gp(pmc))
-		reprogram_gp_counter(pmc, pmc->eventsel);
-	else {
-		int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
-		u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
+	pmc_release_perf_event(pmc);
 
-		reprogram_fixed_counter(pmc, ctrl, idx);
-	}
+	pmc->current_config = new_config;
+	pmc_reprogram_counter(pmc, PERF_TYPE_RAW,
+			      (eventsel & pmu->raw_event_mask),
+			      !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
+			      !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
+			      eventsel & ARCH_PERFMON_EVENTSEL_INT);
 }
 EXPORT_SYMBOL_GPL(reprogram_counter);
 
@@ -329,8 +339,7 @@ void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
 			clear_bit(bit, pmu->reprogram_pmi);
 			continue;
 		}
-
-		reprogram_counter(pmu, bit);
+		reprogram_counter(pmc);
 	}
 
 	/*
@@ -416,10 +425,10 @@ void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
 	}
 }
 
-bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
+bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated)
 {
 	return static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr) ||
-		static_call(kvm_x86_pmu_is_valid_msr)(vcpu, msr);
+		static_call(kvm_x86_pmu_is_valid_msr)(vcpu, msr, host_initiated);
 }
 
 static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
@@ -433,11 +442,19 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
 
 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
+	if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu) {
+		msr_info->data = 0;
+		return 0;
+	}
+
 	return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info);
 }
 
 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
+	if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu)
+		return !!msr_info->data;
+
 	kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
 	return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info);
 }
@@ -471,17 +488,6 @@ void kvm_pmu_init(struct kvm_vcpu *vcpu)
 	kvm_pmu_refresh(vcpu);
 }
 
-static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
-{
-	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
-
-	if (pmc_is_fixed(pmc))
-		return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
-			pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
-
-	return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
-}
-
 /* Release perf_events for vPMCs that have been unused for a full time slice.  */
 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
 {
@@ -514,13 +520,12 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
 
 static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
 {
-	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 	u64 prev_count;
 
 	prev_count = pmc->counter;
 	pmc->counter = (pmc->counter + 1) & pmc_bitmask(pmc);
 
-	reprogram_counter(pmu, pmc->idx);
+	reprogram_counter(pmc);
 	if (pmc->counter < prev_count)
 		__kvm_perf_overflow(pmc, false);
 }
@@ -528,13 +533,8 @@ static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
 static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc,
 	unsigned int perf_hw_id)
 {
-	u64 old_eventsel = pmc->eventsel;
-	unsigned int config;
-
-	pmc->eventsel &= (ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_UMASK);
-	config = static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc);
-	pmc->eventsel = old_eventsel;
-	return config == perf_hw_id;
+	return !((pmc->eventsel ^ perf_get_hw_event_config(perf_hw_id)) &
+		AMD64_RAW_EVENT_MASK_NB);
 }
 
 static inline bool cpl_is_matched(struct kvm_pmc *pmc)
diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index e745f443b6a8..c1b61671ba1e 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -8,6 +8,9 @@
 #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
 #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
 
+#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |	\
+					  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
+
 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
 
@@ -22,14 +25,14 @@ struct kvm_event_hw_type_mapping {
 };
 
 struct kvm_pmu_ops {
-	unsigned int (*pmc_perf_hw_id)(struct kvm_pmc *pmc);
+	bool (*hw_event_available)(struct kvm_pmc *pmc);
 	bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
 	struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
 	struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu,
 		unsigned int idx, u64 *mask);
 	struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr);
 	bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx);
-	bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
+	bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated);
 	int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 	int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 	void (*refresh)(struct kvm_vcpu *vcpu);
@@ -144,15 +147,49 @@ static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
 			  get_sample_period(pmc, pmc->counter));
 }
 
-void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel);
-void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx);
-void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx);
+static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
+{
+	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
+
+	if (pmc_is_fixed(pmc))
+		return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
+					pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
+
+	return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
+}
+
+extern struct x86_pmu_capability kvm_pmu_cap;
+
+static inline void kvm_init_pmu_capability(void)
+{
+	bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
+
+	perf_get_x86_pmu_capability(&kvm_pmu_cap);
+
+	 /*
+	  * For Intel, only support guest architectural pmu
+	  * on a host with architectural pmu.
+	  */
+	if ((is_intel && !kvm_pmu_cap.version) || !kvm_pmu_cap.num_counters_gp)
+		enable_pmu = false;
+
+	if (!enable_pmu) {
+		memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
+		return;
+	}
+
+	kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2);
+	kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
+					     KVM_PMC_MAX_FIXED);
+}
+
+void reprogram_counter(struct kvm_pmc *pmc);
 
 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx);
-bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
+bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated);
 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index ba7cd26f438f..83bae1f2eeb8 100644
--- a/arch/x86/kvm/svm/nested.c
+++ b/arch/x86/kvm/svm/nested.c
@@ -371,6 +371,7 @@ void __nested_copy_vmcb_control_to_cache(struct kvm_vcpu *vcpu,
 	to->nested_ctl          = from->nested_ctl;
 	to->event_inj           = from->event_inj;
 	to->event_inj_err       = from->event_inj_err;
+	to->next_rip            = from->next_rip;
 	to->nested_cr3          = from->nested_cr3;
 	to->virt_ext            = from->virt_ext;
 	to->pause_filter_count  = from->pause_filter_count;
@@ -608,7 +609,32 @@ static void nested_vmcb02_prepare_save(struct vcpu_svm *svm, struct vmcb *vmcb12
 	}
 }
 
-static void nested_vmcb02_prepare_control(struct vcpu_svm *svm)
+static inline bool is_evtinj_soft(u32 evtinj)
+{
+	u32 type = evtinj & SVM_EVTINJ_TYPE_MASK;
+	u8 vector = evtinj & SVM_EVTINJ_VEC_MASK;
+
+	if (!(evtinj & SVM_EVTINJ_VALID))
+		return false;
+
+	if (type == SVM_EVTINJ_TYPE_SOFT)
+		return true;
+
+	return type == SVM_EVTINJ_TYPE_EXEPT && kvm_exception_is_soft(vector);
+}
+
+static bool is_evtinj_nmi(u32 evtinj)
+{
+	u32 type = evtinj & SVM_EVTINJ_TYPE_MASK;
+
+	if (!(evtinj & SVM_EVTINJ_VALID))
+		return false;
+
+	return type == SVM_EVTINJ_TYPE_NMI;
+}
+
+static void nested_vmcb02_prepare_control(struct vcpu_svm *svm,
+					  unsigned long vmcb12_rip)
 {
 	u32 int_ctl_vmcb01_bits = V_INTR_MASKING_MASK;
 	u32 int_ctl_vmcb12_bits = V_TPR_MASK | V_IRQ_INJECTION_BITS_MASK;
@@ -650,7 +676,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm)
 
 	vmcb02->control.tsc_offset = vcpu->arch.tsc_offset;
 
-	if (svm->tsc_ratio_msr != kvm_default_tsc_scaling_ratio) {
+	if (svm->tsc_ratio_msr != kvm_caps.default_tsc_scaling_ratio) {
 		WARN_ON(!svm->tsc_scaling_enabled);
 		nested_svm_update_tsc_ratio_msr(vcpu);
 	}
@@ -664,6 +690,30 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm)
 	vmcb02->control.event_inj           = svm->nested.ctl.event_inj;
 	vmcb02->control.event_inj_err       = svm->nested.ctl.event_inj_err;
 
+	/*
+	 * next_rip is consumed on VMRUN as the return address pushed on the
+	 * stack for injected soft exceptions/interrupts.  If nrips is exposed
+	 * to L1, take it verbatim from vmcb12.  If nrips is supported in
+	 * hardware but not exposed to L1, stuff the actual L2 RIP to emulate
+	 * what a nrips=0 CPU would do (L1 is responsible for advancing RIP
+	 * prior to injecting the event).
+	 */
+	if (svm->nrips_enabled)
+		vmcb02->control.next_rip    = svm->nested.ctl.next_rip;
+	else if (boot_cpu_has(X86_FEATURE_NRIPS))
+		vmcb02->control.next_rip    = vmcb12_rip;
+
+	svm->nmi_l1_to_l2 = is_evtinj_nmi(vmcb02->control.event_inj);
+	if (is_evtinj_soft(vmcb02->control.event_inj)) {
+		svm->soft_int_injected = true;
+		svm->soft_int_csbase = svm->vmcb->save.cs.base;
+		svm->soft_int_old_rip = vmcb12_rip;
+		if (svm->nrips_enabled)
+			svm->soft_int_next_rip = svm->nested.ctl.next_rip;
+		else
+			svm->soft_int_next_rip = vmcb12_rip;
+	}
+
 	vmcb02->control.virt_ext            = vmcb01->control.virt_ext &
 					      LBR_CTL_ENABLE_MASK;
 	if (svm->lbrv_enabled)
@@ -745,7 +795,7 @@ int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb12_gpa,
 	nested_svm_copy_common_state(svm->vmcb01.ptr, svm->nested.vmcb02.ptr);
 
 	svm_switch_vmcb(svm, &svm->nested.vmcb02);
-	nested_vmcb02_prepare_control(svm);
+	nested_vmcb02_prepare_control(svm, vmcb12->save.rip);
 	nested_vmcb02_prepare_save(svm, vmcb12);
 
 	ret = nested_svm_load_cr3(&svm->vcpu, svm->nested.save.cr3,
@@ -834,6 +884,8 @@ int nested_svm_vmrun(struct kvm_vcpu *vcpu)
 
 out_exit_err:
 	svm->nested.nested_run_pending = 0;
+	svm->nmi_l1_to_l2 = false;
+	svm->soft_int_injected = false;
 
 	svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
 	svm->vmcb->control.exit_code_hi = 0;
@@ -982,7 +1034,7 @@ int nested_svm_vmexit(struct vcpu_svm *svm)
 		vmcb_mark_dirty(vmcb01, VMCB_INTERCEPTS);
 	}
 
-	if (svm->tsc_ratio_msr != kvm_default_tsc_scaling_ratio) {
+	if (svm->tsc_ratio_msr != kvm_caps.default_tsc_scaling_ratio) {
 		WARN_ON(!svm->tsc_scaling_enabled);
 		vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio;
 		__svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
@@ -1421,6 +1473,7 @@ static void nested_copy_vmcb_cache_to_control(struct vmcb_control_area *dst,
 	dst->nested_ctl           = from->nested_ctl;
 	dst->event_inj            = from->event_inj;
 	dst->event_inj_err        = from->event_inj_err;
+	dst->next_rip             = from->next_rip;
 	dst->nested_cr3           = from->nested_cr3;
 	dst->virt_ext              = from->virt_ext;
 	dst->pause_filter_count   = from->pause_filter_count;
@@ -1605,7 +1658,7 @@ static int svm_set_nested_state(struct kvm_vcpu *vcpu,
 	nested_copy_vmcb_control_to_cache(svm, ctl);
 
 	svm_switch_vmcb(svm, &svm->nested.vmcb02);
-	nested_vmcb02_prepare_control(svm);
+	nested_vmcb02_prepare_control(svm, svm->vmcb->save.rip);
 
 	/*
 	 * While the nested guest CR3 is already checked and set by
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index 136039fc6d01..fe520b2649b5 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -33,34 +33,6 @@ enum index {
 	INDEX_ERROR,
 };
 
-/* duplicated from amd_perfmon_event_map, K7 and above should work. */
-static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
-	[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
-	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
-	[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
-	[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
-	[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
-	[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
-	[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
-	[7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
-};
-
-/* duplicated from amd_f17h_perfmon_event_map. */
-static struct kvm_event_hw_type_mapping amd_f17h_event_mapping[] = {
-	[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
-	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
-	[2] = { 0x60, 0xff, PERF_COUNT_HW_CACHE_REFERENCES },
-	[3] = { 0x64, 0x09, PERF_COUNT_HW_CACHE_MISSES },
-	[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
-	[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
-	[6] = { 0x87, 0x02, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
-	[7] = { 0x87, 0x01, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
-};
-
-/* amd_pmc_perf_hw_id depends on these being the same size */
-static_assert(ARRAY_SIZE(amd_event_mapping) ==
-	     ARRAY_SIZE(amd_f17h_event_mapping));
-
 static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
 {
 	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
@@ -154,31 +126,9 @@ static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,
 	return &pmu->gp_counters[msr_to_index(msr)];
 }
 
-static unsigned int amd_pmc_perf_hw_id(struct kvm_pmc *pmc)
+static bool amd_hw_event_available(struct kvm_pmc *pmc)
 {
-	struct kvm_event_hw_type_mapping *event_mapping;
-	u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
-	u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
-	int i;
-
-	/* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */
-	if (WARN_ON(pmc_is_fixed(pmc)))
-		return PERF_COUNT_HW_MAX;
-
-	if (guest_cpuid_family(pmc->vcpu) >= 0x17)
-		event_mapping = amd_f17h_event_mapping;
-	else
-		event_mapping = amd_event_mapping;
-
-	for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
-		if (event_mapping[i].eventsel == event_select
-		    && event_mapping[i].unit_mask == unit_mask)
-			break;
-
-	if (i == ARRAY_SIZE(amd_event_mapping))
-		return PERF_COUNT_HW_MAX;
-
-	return event_mapping[i].event_type;
+	return true;
 }
 
 /* check if a PMC is enabled by comparing it against global_ctrl bits. Because
@@ -229,10 +179,19 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
 	return &counters[idx];
 }
 
-static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
+static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated)
 {
 	/* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough.  */
-	return false;
+	if (!host_initiated)
+		return false;
+
+	switch (msr) {
+	case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
+	case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
+		return true;
+	default:
+		return false;
+	}
 }
 
 static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
@@ -286,8 +245,10 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
 	if (pmc) {
 		data &= ~pmu->reserved_bits;
-		if (data != pmc->eventsel)
-			reprogram_gp_counter(pmc, data);
+		if (data != pmc->eventsel) {
+			pmc->eventsel = data;
+			reprogram_counter(pmc);
+		}
 		return 0;
 	}
 
@@ -343,7 +304,7 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu)
 }
 
 struct kvm_pmu_ops amd_pmu_ops __initdata = {
-	.pmc_perf_hw_id = amd_pmc_perf_hw_id,
+	.hw_event_available = amd_hw_event_available,
 	.pmc_is_enabled = amd_pmc_is_enabled,
 	.pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
 	.rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc,
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 51fd985cf21d..309bcdb2f929 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -1606,38 +1606,35 @@ static int sev_lock_vcpus_for_migration(struct kvm *kvm,
 {
 	struct kvm_vcpu *vcpu;
 	unsigned long i, j;
-	bool first = true;
 
 	kvm_for_each_vcpu(i, vcpu, kvm) {
 		if (mutex_lock_killable_nested(&vcpu->mutex, role))
 			goto out_unlock;
 
-		if (first) {
+#ifdef CONFIG_PROVE_LOCKING
+		if (!i)
 			/*
 			 * Reset the role to one that avoids colliding with
 			 * the role used for the first vcpu mutex.
 			 */
 			role = SEV_NR_MIGRATION_ROLES;
-			first = false;
-		} else {
+		else
 			mutex_release(&vcpu->mutex.dep_map, _THIS_IP_);
-		}
+#endif
 	}
 
 	return 0;
 
 out_unlock:
 
-	first = true;
 	kvm_for_each_vcpu(j, vcpu, kvm) {
 		if (i == j)
 			break;
 
-		if (first)
-			first = false;
-		else
+#ifdef CONFIG_PROVE_LOCKING
+		if (j)
 			mutex_acquire(&vcpu->mutex.dep_map, role, 0, _THIS_IP_);
-
+#endif
 
 		mutex_unlock(&vcpu->mutex);
 	}
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 87da90360bc7..136298cfb3fb 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -342,9 +342,11 @@ static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 
 }
 
-static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
+static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
+					   bool commit_side_effects)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
+	unsigned long old_rflags;
 
 	/*
 	 * SEV-ES does not expose the next RIP. The RIP update is controlled by
@@ -359,18 +361,75 @@ static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
 	}
 
 	if (!svm->next_rip) {
+		if (unlikely(!commit_side_effects))
+			old_rflags = svm->vmcb->save.rflags;
+
 		if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 			return 0;
+
+		if (unlikely(!commit_side_effects))
+			svm->vmcb->save.rflags = old_rflags;
 	} else {
 		kvm_rip_write(vcpu, svm->next_rip);
 	}
 
 done:
-	svm_set_interrupt_shadow(vcpu, 0);
+	if (likely(commit_side_effects))
+		svm_set_interrupt_shadow(vcpu, 0);
 
 	return 1;
 }
 
+static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
+{
+	return __svm_skip_emulated_instruction(vcpu, true);
+}
+
+static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu)
+{
+	unsigned long rip, old_rip = kvm_rip_read(vcpu);
+	struct vcpu_svm *svm = to_svm(vcpu);
+
+	/*
+	 * Due to architectural shortcomings, the CPU doesn't always provide
+	 * NextRIP, e.g. if KVM intercepted an exception that occurred while
+	 * the CPU was vectoring an INTO/INT3 in the guest.  Temporarily skip
+	 * the instruction even if NextRIP is supported to acquire the next
+	 * RIP so that it can be shoved into the NextRIP field, otherwise
+	 * hardware will fail to advance guest RIP during event injection.
+	 * Drop the exception/interrupt if emulation fails and effectively
+	 * retry the instruction, it's the least awful option.  If NRIPS is
+	 * in use, the skip must not commit any side effects such as clearing
+	 * the interrupt shadow or RFLAGS.RF.
+	 */
+	if (!__svm_skip_emulated_instruction(vcpu, !nrips))
+		return -EIO;
+
+	rip = kvm_rip_read(vcpu);
+
+	/*
+	 * Save the injection information, even when using next_rip, as the
+	 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection
+	 * doesn't complete due to a VM-Exit occurring while the CPU is
+	 * vectoring the event.   Decoding the instruction isn't guaranteed to
+	 * work as there may be no backing instruction, e.g. if the event is
+	 * being injected by L1 for L2, or if the guest is patching INT3 into
+	 * a different instruction.
+	 */
+	svm->soft_int_injected = true;
+	svm->soft_int_csbase = svm->vmcb->save.cs.base;
+	svm->soft_int_old_rip = old_rip;
+	svm->soft_int_next_rip = rip;
+
+	if (nrips)
+		kvm_rip_write(vcpu, old_rip);
+
+	if (static_cpu_has(X86_FEATURE_NRIPS))
+		svm->vmcb->control.next_rip = rip;
+
+	return 0;
+}
+
 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
@@ -380,21 +439,9 @@ static void svm_queue_exception(struct kvm_vcpu *vcpu)
 
 	kvm_deliver_exception_payload(vcpu);
 
-	if (nr == BP_VECTOR && !nrips) {
-		unsigned long rip, old_rip = kvm_rip_read(vcpu);
-
-		/*
-		 * For guest debugging where we have to reinject #BP if some
-		 * INT3 is guest-owned:
-		 * Emulate nRIP by moving RIP forward. Will fail if injection
-		 * raises a fault that is not intercepted. Still better than
-		 * failing in all cases.
-		 */
-		(void)svm_skip_emulated_instruction(vcpu);
-		rip = kvm_rip_read(vcpu);
-		svm->int3_rip = rip + svm->vmcb->save.cs.base;
-		svm->int3_injected = rip - old_rip;
-	}
+	if (kvm_exception_is_soft(nr) &&
+	    svm_update_soft_interrupt_rip(vcpu))
+		return;
 
 	svm->vmcb->control.event_inj = nr
 		| SVM_EVTINJ_VALID
@@ -1238,7 +1285,7 @@ static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
 
 	svm_init_osvw(vcpu);
 	vcpu->arch.microcode_version = 0x01000065;
-	svm->tsc_ratio_msr = kvm_default_tsc_scaling_ratio;
+	svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio;
 
 	if (sev_es_guest(vcpu->kvm))
 		sev_es_vcpu_reset(svm);
@@ -3382,35 +3429,49 @@ static void svm_inject_nmi(struct kvm_vcpu *vcpu)
 	struct vcpu_svm *svm = to_svm(vcpu);
 
 	svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
+
+	if (svm->nmi_l1_to_l2)
+		return;
+
 	vcpu->arch.hflags |= HF_NMI_MASK;
 	if (!sev_es_guest(vcpu->kvm))
 		svm_set_intercept(svm, INTERCEPT_IRET);
 	++vcpu->stat.nmi_injections;
 }
 
-static void svm_inject_irq(struct kvm_vcpu *vcpu)
+static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
+	u32 type;
 
-	BUG_ON(!(gif_set(svm)));
+	if (vcpu->arch.interrupt.soft) {
+		if (svm_update_soft_interrupt_rip(vcpu))
+			return;
 
-	trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
+		type = SVM_EVTINJ_TYPE_SOFT;
+	} else {
+		type = SVM_EVTINJ_TYPE_INTR;
+	}
+
+	trace_kvm_inj_virq(vcpu->arch.interrupt.nr,
+			   vcpu->arch.interrupt.soft, reinjected);
 	++vcpu->stat.irq_injections;
 
 	svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
-		SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
+				       SVM_EVTINJ_VALID | type;
 }
 
 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
 				     int trig_mode, int vector)
 {
 	/*
-	 * vcpu->arch.apicv_active must be read after vcpu->mode.
+	 * apic->apicv_active must be read after vcpu->mode.
 	 * Pairs with smp_store_release in vcpu_enter_guest.
 	 */
 	bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
 
-	if (!READ_ONCE(vcpu->arch.apicv_active)) {
+	/* Note, this is called iff the local APIC is in-kernel. */
+	if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {
 		/* Process the interrupt via inject_pending_event */
 		kvm_make_request(KVM_REQ_EVENT, vcpu);
 		kvm_vcpu_kick(vcpu);
@@ -3675,15 +3736,49 @@ static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
 	svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
 }
 
+static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector,
+					int type)
+{
+	bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT);
+	bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT);
+	struct vcpu_svm *svm = to_svm(vcpu);
+
+	/*
+	 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's
+	 * associated with the original soft exception/interrupt.  next_rip is
+	 * cleared on all exits that can occur while vectoring an event, so KVM
+	 * needs to manually set next_rip for re-injection.  Unlike the !nrips
+	 * case below, this needs to be done if and only if KVM is re-injecting
+	 * the same event, i.e. if the event is a soft exception/interrupt,
+	 * otherwise next_rip is unused on VMRUN.
+	 */
+	if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) &&
+	    kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase))
+		svm->vmcb->control.next_rip = svm->soft_int_next_rip;
+	/*
+	 * If NRIPS isn't enabled, KVM must manually advance RIP prior to
+	 * injecting the soft exception/interrupt.  That advancement needs to
+	 * be unwound if vectoring didn't complete.  Note, the new event may
+	 * not be the injected event, e.g. if KVM injected an INTn, the INTn
+	 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will
+	 * be the reported vectored event, but RIP still needs to be unwound.
+	 */
+	else if (!nrips && (is_soft || is_exception) &&
+		 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase))
+		kvm_rip_write(vcpu, svm->soft_int_old_rip);
+}
+
 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 	u8 vector;
 	int type;
 	u32 exitintinfo = svm->vmcb->control.exit_int_info;
-	unsigned int3_injected = svm->int3_injected;
+	bool nmi_l1_to_l2 = svm->nmi_l1_to_l2;
+	bool soft_int_injected = svm->soft_int_injected;
 
-	svm->int3_injected = 0;
+	svm->nmi_l1_to_l2 = false;
+	svm->soft_int_injected = false;
 
 	/*
 	 * If we've made progress since setting HF_IRET_MASK, we've
@@ -3708,9 +3803,13 @@ static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
 	vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
 	type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
 
+	if (soft_int_injected)
+		svm_complete_soft_interrupt(vcpu, vector, type);
+
 	switch (type) {
 	case SVM_EXITINTINFO_TYPE_NMI:
 		vcpu->arch.nmi_injected = true;
+		svm->nmi_l1_to_l2 = nmi_l1_to_l2;
 		break;
 	case SVM_EXITINTINFO_TYPE_EXEPT:
 		/*
@@ -3719,18 +3818,6 @@ static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
 		if (vector == X86_TRAP_VC)
 			break;
 
-		/*
-		 * In case of software exceptions, do not reinject the vector,
-		 * but re-execute the instruction instead. Rewind RIP first
-		 * if we emulated INT3 before.
-		 */
-		if (kvm_exception_is_soft(vector)) {
-			if (vector == BP_VECTOR && int3_injected &&
-			    kvm_is_linear_rip(vcpu, svm->int3_rip))
-				kvm_rip_write(vcpu,
-					      kvm_rip_read(vcpu) - int3_injected);
-			break;
-		}
 		if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
 			u32 err = svm->vmcb->control.exit_int_info_err;
 			kvm_requeue_exception_e(vcpu, vector, err);
@@ -3741,9 +3828,13 @@ static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
 	case SVM_EXITINTINFO_TYPE_INTR:
 		kvm_queue_interrupt(vcpu, vector, false);
 		break;
+	case SVM_EXITINTINFO_TYPE_SOFT:
+		kvm_queue_interrupt(vcpu, vector, true);
+		break;
 	default:
 		break;
 	}
+
 }
 
 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
@@ -3959,7 +4050,7 @@ static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
 		hv_track_root_tdp(vcpu, root_hpa);
 
 		cr3 = vcpu->arch.cr3;
-	} else if (vcpu->arch.mmu->root_role.level >= PT64_ROOT_4LEVEL) {
+	} else if (root_level >= PT64_ROOT_4LEVEL) {
 		cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
 	} else {
 		/* PCID in the guest should be impossible with a 32-bit MMU. */
@@ -4780,7 +4871,7 @@ static __init void svm_set_cpu_caps(void)
 {
 	kvm_set_cpu_caps();
 
-	supported_xss = 0;
+	kvm_caps.supported_xss = 0;
 
 	/* CPUID 0x80000001 and 0x8000000A (SVM features) */
 	if (nested) {
@@ -4856,7 +4947,8 @@ static __init int svm_hardware_setup(void)
 
 	init_msrpm_offsets();
 
-	supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
+	kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
+				     XFEATURE_MASK_BNDCSR);
 
 	if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 		kvm_enable_efer_bits(EFER_FFXSR);
@@ -4866,11 +4958,11 @@ static __init int svm_hardware_setup(void)
 			tsc_scaling = false;
 		} else {
 			pr_info("TSC scaling supported\n");
-			kvm_has_tsc_control = true;
+			kvm_caps.has_tsc_control = true;
 		}
 	}
-	kvm_max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
-	kvm_tsc_scaling_ratio_frac_bits = 32;
+	kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
+	kvm_caps.tsc_scaling_ratio_frac_bits = 32;
 
 	tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 
diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
index 1bddd336a27e..d51de3c9264a 100644
--- a/arch/x86/kvm/svm/svm.h
+++ b/arch/x86/kvm/svm/svm.h
@@ -139,6 +139,7 @@ struct vmcb_ctrl_area_cached {
 	u64 nested_ctl;
 	u32 event_inj;
 	u32 event_inj_err;
+	u64 next_rip;
 	u64 nested_cr3;
 	u64 virt_ext;
 	u32 clean;
@@ -228,9 +229,12 @@ struct vcpu_svm {
 
 	bool nmi_singlestep;
 	u64 nmi_singlestep_guest_rflags;
+	bool nmi_l1_to_l2;
 
-	unsigned int3_injected;
-	unsigned long int3_rip;
+	unsigned long soft_int_csbase;
+	unsigned long soft_int_old_rip;
+	unsigned long soft_int_next_rip;
+	bool soft_int_injected;
 
 	/* optional nested SVM features that are enabled for this guest  */
 	bool nrips_enabled                : 1;
@@ -613,12 +617,8 @@ int avic_init_vcpu(struct vcpu_svm *svm);
 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 void avic_vcpu_put(struct kvm_vcpu *vcpu);
 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu);
-void avic_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 bool avic_check_apicv_inhibit_reasons(enum kvm_apicv_inhibit reason);
-void avic_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
-void avic_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
-bool avic_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq,
 			uint32_t guest_irq, bool set);
 void avic_vcpu_blocking(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h
index de4762517569..fd28dd40b813 100644
--- a/arch/x86/kvm/trace.h
+++ b/arch/x86/kvm/trace.h
@@ -333,18 +333,24 @@ TRACE_EVENT_KVM_EXIT(kvm_exit);
  * Tracepoint for kvm interrupt injection:
  */
 TRACE_EVENT(kvm_inj_virq,
-	TP_PROTO(unsigned int irq),
-	TP_ARGS(irq),
+	TP_PROTO(unsigned int vector, bool soft, bool reinjected),
+	TP_ARGS(vector, soft, reinjected),
 
 	TP_STRUCT__entry(
-		__field(	unsigned int,	irq		)
+		__field(	unsigned int,	vector		)
+		__field(	bool,		soft		)
+		__field(	bool,		reinjected	)
 	),
 
 	TP_fast_assign(
-		__entry->irq		= irq;
+		__entry->vector		= vector;
+		__entry->soft		= soft;
+		__entry->reinjected	= reinjected;
 	),
 
-	TP_printk("irq %u", __entry->irq)
+	TP_printk("%s 0x%x%s",
+		  __entry->soft ? "Soft/INTn" : "IRQ", __entry->vector,
+		  __entry->reinjected ? " [reinjected]" : "")
 );
 
 #define EXS(x) { x##_VECTOR, "#" #x }
@@ -358,25 +364,30 @@ TRACE_EVENT(kvm_inj_virq,
  * Tracepoint for kvm interrupt injection:
  */
 TRACE_EVENT(kvm_inj_exception,
-	TP_PROTO(unsigned exception, bool has_error, unsigned error_code),
-	TP_ARGS(exception, has_error, error_code),
+	TP_PROTO(unsigned exception, bool has_error, unsigned error_code,
+		 bool reinjected),
+	TP_ARGS(exception, has_error, error_code, reinjected),
 
 	TP_STRUCT__entry(
 		__field(	u8,	exception	)
 		__field(	u8,	has_error	)
 		__field(	u32,	error_code	)
+		__field(	bool,	reinjected	)
 	),
 
 	TP_fast_assign(
 		__entry->exception	= exception;
 		__entry->has_error	= has_error;
 		__entry->error_code	= error_code;
+		__entry->reinjected	= reinjected;
 	),
 
-	TP_printk("%s (0x%x)",
+	TP_printk("%s%s%s%s%s",
 		  __print_symbolic(__entry->exception, kvm_trace_sym_exc),
-		  /* FIXME: don't print error_code if not present */
-		  __entry->has_error ? __entry->error_code : 0)
+		  !__entry->has_error ? "" : " (",
+		  !__entry->has_error ? "" : __print_symbolic(__entry->error_code, { }),
+		  !__entry->has_error ? "" : ")",
+		  __entry->reinjected ? " [reinjected]" : "")
 );
 
 /*
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 3f430e218375..069d8d298e1d 100644
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -6,6 +6,8 @@
 
 #include "lapic.h"
 #include "x86.h"
+#include "pmu.h"
+#include "cpuid.h"
 
 extern bool __read_mostly enable_vpid;
 extern bool __read_mostly flexpriority_enabled;
@@ -13,6 +15,7 @@ extern bool __read_mostly enable_ept;
 extern bool __read_mostly enable_unrestricted_guest;
 extern bool __read_mostly enable_ept_ad_bits;
 extern bool __read_mostly enable_pml;
+extern bool __read_mostly enable_ipiv;
 extern int __read_mostly pt_mode;
 
 #define PT_MODE_SYSTEM		0
@@ -59,6 +62,7 @@ struct vmcs_config {
 	u32 pin_based_exec_ctrl;
 	u32 cpu_based_exec_ctrl;
 	u32 cpu_based_2nd_exec_ctrl;
+	u64 cpu_based_3rd_exec_ctrl;
 	u32 vmexit_ctrl;
 	u32 vmentry_ctrl;
 	struct nested_vmx_msrs nested;
@@ -94,20 +98,17 @@ static inline bool cpu_has_vmx_posted_intr(void)
 
 static inline bool cpu_has_load_ia32_efer(void)
 {
-	return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) &&
-	       (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER);
+	return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER;
 }
 
 static inline bool cpu_has_load_perf_global_ctrl(void)
 {
-	return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
-	       (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
+	return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
 }
 
 static inline bool cpu_has_vmx_mpx(void)
 {
-	return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
-		(vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
+	return vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS;
 }
 
 static inline bool cpu_has_vmx_tpr_shadow(void)
@@ -131,6 +132,12 @@ static inline bool cpu_has_secondary_exec_ctrls(void)
 		CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 }
 
+static inline bool cpu_has_tertiary_exec_ctrls(void)
+{
+	return vmcs_config.cpu_based_exec_ctrl &
+		CPU_BASED_ACTIVATE_TERTIARY_CONTROLS;
+}
+
 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 {
 	return vmcs_config.cpu_based_2nd_exec_ctrl &
@@ -276,6 +283,11 @@ static inline bool cpu_has_vmx_apicv(void)
 		cpu_has_vmx_posted_intr();
 }
 
+static inline bool cpu_has_vmx_ipiv(void)
+{
+	return vmcs_config.cpu_based_3rd_exec_ctrl & TERTIARY_EXEC_IPI_VIRT;
+}
+
 static inline bool cpu_has_vmx_flexpriority(void)
 {
 	return cpu_has_vmx_tpr_shadow() &&
@@ -363,7 +375,6 @@ static inline bool cpu_has_vmx_intel_pt(void)
 	rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
 	return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) &&
 		(vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) &&
-		(vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_RTIT_CTL) &&
 		(vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL);
 }
 
@@ -385,23 +396,31 @@ static inline bool vmx_pt_mode_is_host_guest(void)
 	return pt_mode == PT_MODE_HOST_GUEST;
 }
 
+static inline bool vmx_pebs_supported(void)
+{
+	return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept;
+}
+
 static inline u64 vmx_get_perf_capabilities(void)
 {
-	u64 perf_cap = 0;
+	u64 perf_cap = PMU_CAP_FW_WRITES;
+	u64 host_perf_cap = 0;
 
 	if (!enable_pmu)
-		return perf_cap;
+		return 0;
 
 	if (boot_cpu_has(X86_FEATURE_PDCM))
-		rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap);
+		rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
 
-	perf_cap &= PMU_CAP_LBR_FMT;
+	perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT;
 
-	/*
-	 * Since counters are virtualized, KVM would support full
-	 * width counting unconditionally, even if the host lacks it.
-	 */
-	return PMU_CAP_FW_WRITES | perf_cap;
+	if (vmx_pebs_supported()) {
+		perf_cap |= host_perf_cap & PERF_CAP_PEBS_MASK;
+		if ((perf_cap & PERF_CAP_PEBS_FORMAT) < 4)
+			perf_cap &= ~PERF_CAP_PEBS_BASELINE;
+	}
+
+	return perf_cap;
 }
 
 static inline u64 vmx_supported_debugctl(void)
@@ -417,4 +436,10 @@ static inline u64 vmx_supported_debugctl(void)
 	return debugctl;
 }
 
+static inline bool cpu_has_notify_vmexit(void)
+{
+	return vmcs_config.cpu_based_2nd_exec_ctrl &
+		SECONDARY_EXEC_NOTIFY_VM_EXITING;
+}
+
 #endif /* __KVM_X86_VMX_CAPS_H */
diff --git a/arch/x86/kvm/vmx/evmcs.c b/arch/x86/kvm/vmx/evmcs.c
index 87e3dc10edf4..6a61b1ae7942 100644
--- a/arch/x86/kvm/vmx/evmcs.c
+++ b/arch/x86/kvm/vmx/evmcs.c
@@ -297,8 +297,10 @@ const unsigned int nr_evmcs_1_fields = ARRAY_SIZE(vmcs_field_to_evmcs_1);
 #if IS_ENABLED(CONFIG_HYPERV)
 __init void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf)
 {
+	vmcs_conf->cpu_based_exec_ctrl &= ~EVMCS1_UNSUPPORTED_EXEC_CTRL;
 	vmcs_conf->pin_based_exec_ctrl &= ~EVMCS1_UNSUPPORTED_PINCTRL;
 	vmcs_conf->cpu_based_2nd_exec_ctrl &= ~EVMCS1_UNSUPPORTED_2NDEXEC;
+	vmcs_conf->cpu_based_3rd_exec_ctrl = 0;
 
 	vmcs_conf->vmexit_ctrl &= ~EVMCS1_UNSUPPORTED_VMEXIT_CTRL;
 	vmcs_conf->vmentry_ctrl &= ~EVMCS1_UNSUPPORTED_VMENTRY_CTRL;
diff --git a/arch/x86/kvm/vmx/evmcs.h b/arch/x86/kvm/vmx/evmcs.h
index 8d70f9aea94b..f886a8ff0342 100644
--- a/arch/x86/kvm/vmx/evmcs.h
+++ b/arch/x86/kvm/vmx/evmcs.h
@@ -50,6 +50,7 @@ DECLARE_STATIC_KEY_FALSE(enable_evmcs);
  */
 #define EVMCS1_UNSUPPORTED_PINCTRL (PIN_BASED_POSTED_INTR | \
 				    PIN_BASED_VMX_PREEMPTION_TIMER)
+#define EVMCS1_UNSUPPORTED_EXEC_CTRL (CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
 #define EVMCS1_UNSUPPORTED_2NDEXEC					\
 	(SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |				\
 	 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |			\
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index f5cb18e00e78..778f82015f03 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -311,11 +311,12 @@ static void free_nested(struct kvm_vcpu *vcpu)
 	vmx->nested.cached_vmcs12 = NULL;
 	kfree(vmx->nested.cached_shadow_vmcs12);
 	vmx->nested.cached_shadow_vmcs12 = NULL;
-	/* Unpin physical memory we referred to in the vmcs02 */
-	if (vmx->nested.apic_access_page) {
-		kvm_release_page_clean(vmx->nested.apic_access_page);
-		vmx->nested.apic_access_page = NULL;
-	}
+	/*
+	 * Unpin physical memory we referred to in the vmcs02.  The APIC access
+	 * page's backing page (yeah, confusing) shouldn't actually be accessed,
+	 * and if it is written, the contents are irrelevant.
+	 */
+	kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
 	kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
 	kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
 	vmx->nested.pi_desc = NULL;
@@ -2133,6 +2134,8 @@ static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
 
 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
 {
+	struct kvm *kvm = vmx->vcpu.kvm;
+
 	/*
 	 * If vmcs02 hasn't been initialized, set the constant vmcs02 state
 	 * according to L0's settings (vmcs12 is irrelevant here).  Host
@@ -2175,6 +2178,9 @@ static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx)
 	if (cpu_has_vmx_encls_vmexit())
 		vmcs_write64(ENCLS_EXITING_BITMAP, INVALID_GPA);
 
+	if (kvm_notify_vmexit_enabled(kvm))
+		vmcs_write32(NOTIFY_WINDOW, kvm->arch.notify_window);
+
 	/*
 	 * Set the MSR load/store lists to match L0's settings.  Only the
 	 * addresses are constant (for vmcs02), the counts can change based
@@ -2515,11 +2521,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
 		vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
 	} else {
 		kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
-		vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
+		vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.pre_vmenter_debugctl);
 	}
 	if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending ||
 	    !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
-		vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
+		vmcs_write64(GUEST_BNDCFGS, vmx->nested.pre_vmenter_bndcfgs);
 	vmx_set_rflags(vcpu, vmcs12->guest_rflags);
 
 	/* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
@@ -2548,7 +2554,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
 			vmx_get_l2_tsc_multiplier(vcpu));
 
 	vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
-	if (kvm_has_tsc_control)
+	if (kvm_caps.has_tsc_control)
 		vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
 
 	nested_vmx_transition_tlb_flush(vcpu, vmcs12, true);
@@ -3159,8 +3165,6 @@ static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 	struct kvm_host_map *map;
-	struct page *page;
-	u64 hpa;
 
 	if (!vcpu->arch.pdptrs_from_userspace &&
 	    !nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) {
@@ -3175,23 +3179,12 @@ static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu)
 
 
 	if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
-		/*
-		 * Translate L1 physical address to host physical
-		 * address for vmcs02. Keep the page pinned, so this
-		 * physical address remains valid. We keep a reference
-		 * to it so we can release it later.
-		 */
-		if (vmx->nested.apic_access_page) { /* shouldn't happen */
-			kvm_release_page_clean(vmx->nested.apic_access_page);
-			vmx->nested.apic_access_page = NULL;
-		}
-		page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
-		if (!is_error_page(page)) {
-			vmx->nested.apic_access_page = page;
-			hpa = page_to_phys(vmx->nested.apic_access_page);
-			vmcs_write64(APIC_ACCESS_ADDR, hpa);
+		map = &vmx->nested.apic_access_page_map;
+
+		if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->apic_access_addr), map)) {
+			vmcs_write64(APIC_ACCESS_ADDR, pfn_to_hpa(map->pfn));
 		} else {
-			pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n",
+			pr_debug_ratelimited("%s: no backing for APIC-access address in vmcs12\n",
 					     __func__);
 			vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
 			vcpu->run->internal.suberror =
@@ -3374,11 +3367,13 @@ enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
 	if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
 		evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
 
-	if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
-		vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
+	if (!vmx->nested.nested_run_pending ||
+	    !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
+		vmx->nested.pre_vmenter_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
 	if (kvm_mpx_supported() &&
-		!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
-		vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
+	    (!vmx->nested.nested_run_pending ||
+	     !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)))
+		vmx->nested.pre_vmenter_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
 
 	/*
 	 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and*
@@ -4097,8 +4092,6 @@ static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
 	vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
 	vmcs12->guest_pending_dbg_exceptions =
 		vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
-	if (kvm_mpx_supported())
-		vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
 
 	vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
 }
@@ -4610,7 +4603,7 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
 	vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
 	vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
 	vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
-	if (kvm_has_tsc_control)
+	if (kvm_caps.has_tsc_control)
 		vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
 
 	if (vmx->nested.l1_tpr_threshold != -1)
@@ -4627,10 +4620,7 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
 	}
 
 	/* Unpin physical memory we referred to in vmcs02 */
-	if (vmx->nested.apic_access_page) {
-		kvm_release_page_clean(vmx->nested.apic_access_page);
-		vmx->nested.apic_access_page = NULL;
-	}
+	kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false);
 	kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true);
 	kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true);
 	vmx->nested.pi_desc = NULL;
@@ -6112,6 +6102,9 @@ static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu,
 			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE);
 	case EXIT_REASON_ENCLS:
 		return nested_vmx_exit_handled_encls(vcpu, vmcs12);
+	case EXIT_REASON_NOTIFY:
+		/* Notify VM exit is not exposed to L1 */
+		return false;
 	default:
 		return true;
 	}
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 37e9eb32e3d9..422f0a6562ac 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -37,23 +37,35 @@ static int fixed_pmc_events[] = {1, 0, 7};
 
 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
 {
+	struct kvm_pmc *pmc;
+	u8 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl;
 	int i;
 
+	pmu->fixed_ctr_ctrl = data;
 	for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
 		u8 new_ctrl = fixed_ctrl_field(data, i);
-		u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
-		struct kvm_pmc *pmc;
-
-		pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
+		u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i);
 
 		if (old_ctrl == new_ctrl)
 			continue;
 
+		pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
+
 		__set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use);
-		reprogram_fixed_counter(pmc, new_ctrl, i);
+		reprogram_counter(pmc);
 	}
+}
 
-	pmu->fixed_ctr_ctrl = data;
+static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
+{
+	if (pmc_idx < INTEL_PMC_IDX_FIXED) {
+		return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
+				  MSR_P6_EVNTSEL0);
+	} else {
+		u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
+
+		return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
+	}
 }
 
 /* function is called when global control register has been updated. */
@@ -61,14 +73,18 @@ static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
 {
 	int bit;
 	u64 diff = pmu->global_ctrl ^ data;
+	struct kvm_pmc *pmc;
 
 	pmu->global_ctrl = data;
 
-	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
-		reprogram_counter(pmu, bit);
+	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) {
+		pmc = intel_pmc_idx_to_pmc(pmu, bit);
+		if (pmc)
+			reprogram_counter(pmc);
+	}
 }
 
-static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc)
+static bool intel_hw_event_available(struct kvm_pmc *pmc)
 {
 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 	u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
@@ -82,15 +98,12 @@ static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc)
 
 		/* disable event that reported as not present by cpuid */
 		if ((i < 7) && !(pmu->available_event_types & (1 << i)))
-			return PERF_COUNT_HW_MAX + 1;
+			return false;
 
 		break;
 	}
 
-	if (i == ARRAY_SIZE(intel_arch_events))
-		return PERF_COUNT_HW_MAX;
-
-	return intel_arch_events[i].event_type;
+	return true;
 }
 
 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
@@ -98,19 +111,10 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
 {
 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
 
-	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
-}
-
-static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
-{
-	if (pmc_idx < INTEL_PMC_IDX_FIXED)
-		return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
-				  MSR_P6_EVNTSEL0);
-	else {
-		u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
+	if (pmu->version < 2)
+		return true;
 
-		return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
-	}
+	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
 }
 
 static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
@@ -167,16 +171,6 @@ static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
 	return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);
 }
 
-bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu)
-{
-	/*
-	 * As a first step, a guest could only enable LBR feature if its
-	 * cpu model is the same as the host because the LBR registers
-	 * would be pass-through to the guest and they're model specific.
-	 */
-	return boot_cpu_data.x86_model == guest_cpuid_model(vcpu);
-}
-
 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu)
 {
 	struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu);
@@ -202,27 +196,45 @@ static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
 	return ret;
 }
 
-static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
+static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated)
 {
 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
-	int ret;
+	u64 perf_capabilities = vcpu->arch.perf_capabilities;
 
 	switch (msr) {
 	case MSR_CORE_PERF_FIXED_CTR_CTRL:
 	case MSR_CORE_PERF_GLOBAL_STATUS:
 	case MSR_CORE_PERF_GLOBAL_CTRL:
 	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
-		ret = pmu->version > 1;
+		if (host_initiated)
+			return true;
+		return pmu->version > 1;
+		break;
+	case MSR_IA32_PEBS_ENABLE:
+		if (host_initiated)
+			return true;
+		return perf_capabilities & PERF_CAP_PEBS_FORMAT;
+		break;
+	case MSR_IA32_DS_AREA:
+		if (host_initiated)
+			return true;
+		return guest_cpuid_has(vcpu, X86_FEATURE_DS);
+		break;
+	case MSR_PEBS_DATA_CFG:
+		if (host_initiated)
+			return true;
+		return (perf_capabilities & PERF_CAP_PEBS_BASELINE) &&
+			((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3);
 		break;
 	default:
-		ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
+		if (host_initiated)
+			return true;
+		return get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
 			get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
 			get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) ||
 			intel_pmu_is_valid_lbr_msr(vcpu, msr);
 		break;
 	}
-
-	return ret;
 }
 
 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
@@ -361,6 +373,15 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 		msr_info->data = 0;
 		return 0;
+	case MSR_IA32_PEBS_ENABLE:
+		msr_info->data = pmu->pebs_enable;
+		return 0;
+	case MSR_IA32_DS_AREA:
+		msr_info->data = pmu->ds_area;
+		return 0;
+	case MSR_PEBS_DATA_CFG:
+		msr_info->data = pmu->pebs_data_cfg;
+		return 0;
 	default:
 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
@@ -395,7 +416,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_CORE_PERF_FIXED_CTR_CTRL:
 		if (pmu->fixed_ctr_ctrl == data)
 			return 0;
-		if (!(data & 0xfffffffffffff444ull)) {
+		if (!(data & pmu->fixed_ctr_ctrl_mask)) {
 			reprogram_fixed_counters(pmu, data);
 			return 0;
 		}
@@ -421,6 +442,29 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			return 0;
 		}
 		break;
+	case MSR_IA32_PEBS_ENABLE:
+		if (pmu->pebs_enable == data)
+			return 0;
+		if (!(data & pmu->pebs_enable_mask)) {
+			pmu->pebs_enable = data;
+			return 0;
+		}
+		break;
+	case MSR_IA32_DS_AREA:
+		if (msr_info->host_initiated && data && !guest_cpuid_has(vcpu, X86_FEATURE_DS))
+			return 1;
+		if (is_noncanonical_address(data, vcpu))
+			return 1;
+		pmu->ds_area = data;
+		return 0;
+	case MSR_PEBS_DATA_CFG:
+		if (pmu->pebs_data_cfg == data)
+			return 0;
+		if (!(data & pmu->pebs_data_cfg_mask)) {
+			pmu->pebs_data_cfg = data;
+			return 0;
+		}
+		break;
 	default:
 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
@@ -445,7 +489,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			    (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED))
 				reserved_bits ^= HSW_IN_TX_CHECKPOINTED;
 			if (!(data & reserved_bits)) {
-				reprogram_gp_counter(pmc, data);
+				pmc->eventsel = data;
+				reprogram_counter(pmc);
 				return 0;
 			}
 		} else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false))
@@ -474,11 +519,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 {
 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 	struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
-
-	struct x86_pmu_capability x86_pmu;
 	struct kvm_cpuid_entry2 *entry;
 	union cpuid10_eax eax;
 	union cpuid10_edx edx;
+	u64 counter_mask;
+	int i;
 
 	pmu->nr_arch_gp_counters = 0;
 	pmu->nr_arch_fixed_counters = 0;
@@ -487,6 +532,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 	pmu->version = 0;
 	pmu->reserved_bits = 0xffffffff00200000ull;
 	pmu->raw_event_mask = X86_RAW_EVENT_MASK;
+	pmu->fixed_ctr_ctrl_mask = ~0ull;
+	pmu->pebs_enable_mask = ~0ull;
+	pmu->pebs_data_cfg_mask = ~0ull;
+
+	vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PMU_RO_MASK;
 
 	entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
 	if (!entry || !vcpu->kvm->arch.enable_pmu)
@@ -498,13 +548,15 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 	if (!pmu->version)
 		return;
 
-	perf_get_x86_pmu_capability(&x86_pmu);
+	vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_EMON;
 
 	pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
-					 x86_pmu.num_counters_gp);
-	eax.split.bit_width = min_t(int, eax.split.bit_width, x86_pmu.bit_width_gp);
+					 kvm_pmu_cap.num_counters_gp);
+	eax.split.bit_width = min_t(int, eax.split.bit_width,
+				    kvm_pmu_cap.bit_width_gp);
 	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
-	eax.split.mask_length = min_t(int, eax.split.mask_length, x86_pmu.events_mask_len);
+	eax.split.mask_length = min_t(int, eax.split.mask_length,
+				      kvm_pmu_cap.events_mask_len);
 	pmu->available_event_types = ~entry->ebx &
 					((1ull << eax.split.mask_length) - 1);
 
@@ -514,17 +566,19 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 		pmu->nr_arch_fixed_counters =
 			min3(ARRAY_SIZE(fixed_pmc_events),
 			     (size_t) edx.split.num_counters_fixed,
-			     (size_t) x86_pmu.num_counters_fixed);
-		edx.split.bit_width_fixed = min_t(int,
-			edx.split.bit_width_fixed, x86_pmu.bit_width_fixed);
+			     (size_t)kvm_pmu_cap.num_counters_fixed);
+		edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed,
+						  kvm_pmu_cap.bit_width_fixed);
 		pmu->counter_bitmask[KVM_PMC_FIXED] =
 			((u64)1 << edx.split.bit_width_fixed) - 1;
 		setup_fixed_pmc_eventsel(pmu);
 	}
 
-	pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
-		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
-	pmu->global_ctrl_mask = ~pmu->global_ctrl;
+	for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
+		pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4));
+	counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
+		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED));
+	pmu->global_ctrl_mask = counter_mask;
 	pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
 			& ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
 			    MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
@@ -546,15 +600,33 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 		INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
 
 	nested_vmx_pmu_refresh(vcpu,
-			       intel_is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL));
+			       intel_is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, false));
 
-	if (intel_pmu_lbr_is_compatible(vcpu))
+	if (cpuid_model_is_consistent(vcpu))
 		x86_perf_get_lbr(&lbr_desc->records);
 	else
 		lbr_desc->records.nr = 0;
 
 	if (lbr_desc->records.nr)
 		bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
+
+	if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) {
+		vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
+		if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) {
+			pmu->pebs_enable_mask = counter_mask;
+			pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
+			for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
+				pmu->fixed_ctr_ctrl_mask &=
+					~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4));
+			}
+			pmu->pebs_data_cfg_mask = ~0xff00000full;
+		} else {
+			pmu->pebs_enable_mask =
+				~((1ull << pmu->nr_arch_gp_counters) - 1);
+		}
+	} else {
+		vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK;
+	}
 }
 
 static void intel_pmu_init(struct kvm_vcpu *vcpu)
@@ -719,8 +791,28 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
 		intel_pmu_release_guest_lbr_event(vcpu);
 }
 
+void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
+{
+	struct kvm_pmc *pmc = NULL;
+	int bit;
+
+	for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
+			 X86_PMC_IDX_MAX) {
+		pmc = intel_pmc_idx_to_pmc(pmu, bit);
+
+		if (!pmc || !pmc_speculative_in_use(pmc) ||
+		    !intel_pmc_is_enabled(pmc))
+			continue;
+
+		if (pmc->perf_event && pmc->idx != pmc->perf_event->hw.idx) {
+			pmu->host_cross_mapped_mask |=
+				BIT_ULL(pmc->perf_event->hw.idx);
+		}
+	}
+}
+
 struct kvm_pmu_ops intel_pmu_ops __initdata = {
-	.pmc_perf_hw_id = intel_pmc_perf_hw_id,
+	.hw_event_available = intel_hw_event_available,
 	.pmc_is_enabled = intel_pmc_is_enabled,
 	.pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
 	.rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c
index 07e5fcf5a5aa..73f60aa480fe 100644
--- a/arch/x86/kvm/vmx/posted_intr.c
+++ b/arch/x86/kvm/vmx/posted_intr.c
@@ -42,7 +42,7 @@ static int pi_try_set_control(struct pi_desc *pi_desc, u64 old, u64 new)
 	 * update must be retried with a fresh snapshot an ON change causes
 	 * the cmpxchg to fail.
 	 */
-	if (cmpxchg64(&pi_desc->control, old, new) != old)
+	if (!try_cmpxchg64(&pi_desc->control, &old, new))
 		return -EBUSY;
 
 	return 0;
@@ -177,11 +177,24 @@ static void pi_enable_wakeup_handler(struct kvm_vcpu *vcpu)
 	local_irq_restore(flags);
 }
 
+static bool vmx_needs_pi_wakeup(struct kvm_vcpu *vcpu)
+{
+	/*
+	 * The default posted interrupt vector does nothing when
+	 * invoked outside guest mode.   Return whether a blocked vCPU
+	 * can be the target of posted interrupts, as is the case when
+	 * using either IPI virtualization or VT-d PI, so that the
+	 * notification vector is switched to the one that calls
+	 * back to the pi_wakeup_handler() function.
+	 */
+	return vmx_can_use_ipiv(vcpu) || vmx_can_use_vtd_pi(vcpu->kvm);
+}
+
 void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
 {
 	struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
 
-	if (!vmx_can_use_vtd_pi(vcpu->kvm))
+	if (!vmx_needs_pi_wakeup(vcpu))
 		return;
 
 	if (kvm_vcpu_is_blocking(vcpu) && !vmx_interrupt_blocked(vcpu))
diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h
index 9a45d5c9f116..26992076552e 100644
--- a/arch/x86/kvm/vmx/posted_intr.h
+++ b/arch/x86/kvm/vmx/posted_intr.h
@@ -5,6 +5,8 @@
 #define POSTED_INTR_ON  0
 #define POSTED_INTR_SN  1
 
+#define PID_TABLE_ENTRY_VALID 1
+
 /* Posted-Interrupt Descriptor */
 struct pi_desc {
 	u32 pir[8];     /* Posted interrupt requested */
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index 2b9d7a7e83f7..ac290a44a693 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -50,6 +50,7 @@ struct vmcs_controls_shadow {
 	u32 pin;
 	u32 exec;
 	u32 secondary_exec;
+	u64 tertiary_exec;
 };
 
 /*
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 3a919e49129b..aad89d05cf36 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -105,6 +105,9 @@ module_param(fasteoi, bool, S_IRUGO);
 
 module_param(enable_apicv, bool, S_IRUGO);
 
+bool __read_mostly enable_ipiv = true;
+module_param(enable_ipiv, bool, 0444);
+
 /*
  * If nested=1, nested virtualization is supported, i.e., guests may use
  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
@@ -116,6 +119,9 @@ module_param(nested, bool, S_IRUGO);
 bool __read_mostly enable_pml = 1;
 module_param_named(pml, enable_pml, bool, S_IRUGO);
 
+static bool __read_mostly error_on_inconsistent_vmcs_config = true;
+module_param(error_on_inconsistent_vmcs_config, bool, 0444);
+
 static bool __read_mostly dump_invalid_vmcs = 0;
 module_param(dump_invalid_vmcs, bool, 0644);
 
@@ -443,18 +449,20 @@ asmlinkage void vmread_error(unsigned long field, bool fault)
 
 noinline void vmwrite_error(unsigned long field, unsigned long value)
 {
-	vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
+	vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%u\n",
 			field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 }
 
 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
 {
-	vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
+	vmx_insn_failed("kvm: vmclear failed: %p/%llx err=%u\n",
+			vmcs, phys_addr, vmcs_read32(VM_INSTRUCTION_ERROR));
 }
 
 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
 {
-	vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
+	vmx_insn_failed("kvm: vmptrld failed: %p/%llx err=%u\n",
+			vmcs, phys_addr, vmcs_read32(VM_INSTRUCTION_ERROR));
 }
 
 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
@@ -1769,7 +1777,7 @@ u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
 	    nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
 		return vmcs12->tsc_multiplier;
 
-	return kvm_default_tsc_scaling_ratio;
+	return kvm_caps.default_tsc_scaling_ratio;
 }
 
 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
@@ -2093,6 +2101,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
 		    (data & MSR_IA32_BNDCFGS_RSVD))
 			return 1;
+
+		if (is_guest_mode(vcpu) &&
+		    ((vmx->nested.msrs.entry_ctls_high & VM_ENTRY_LOAD_BNDCFGS) ||
+		     (vmx->nested.msrs.exit_ctls_high & VM_EXIT_CLEAR_BNDCFGS)))
+			get_vmcs12(vcpu)->guest_bndcfgs = data;
+
 		vmcs_write64(GUEST_BNDCFGS, data);
 		break;
 	case MSR_IA32_UMWAIT_CONTROL:
@@ -2294,7 +2308,18 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			if ((data & PMU_CAP_LBR_FMT) !=
 			    (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT))
 				return 1;
-			if (!intel_pmu_lbr_is_compatible(vcpu))
+			if (!cpuid_model_is_consistent(vcpu))
+				return 1;
+		}
+		if (data & PERF_CAP_PEBS_FORMAT) {
+			if ((data & PERF_CAP_PEBS_MASK) !=
+			    (vmx_get_perf_capabilities() & PERF_CAP_PEBS_MASK))
+				return 1;
+			if (!guest_cpuid_has(vcpu, X86_FEATURE_DS))
+				return 1;
+			if (!guest_cpuid_has(vcpu, X86_FEATURE_DTES64))
+				return 1;
+			if (!cpuid_model_is_consistent(vcpu))
 				return 1;
 		}
 		ret = kvm_set_msr_common(vcpu, msr_info);
@@ -2471,6 +2496,15 @@ static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 	return 0;
 }
 
+static __init u64 adjust_vmx_controls64(u64 ctl_opt, u32 msr)
+{
+	u64 allowed;
+
+	rdmsrl(msr, allowed);
+
+	return  ctl_opt & allowed;
+}
+
 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 				    struct vmx_capability *vmx_cap)
 {
@@ -2479,8 +2513,26 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 	u32 _pin_based_exec_control = 0;
 	u32 _cpu_based_exec_control = 0;
 	u32 _cpu_based_2nd_exec_control = 0;
+	u64 _cpu_based_3rd_exec_control = 0;
 	u32 _vmexit_control = 0;
 	u32 _vmentry_control = 0;
+	int i;
+
+	/*
+	 * LOAD/SAVE_DEBUG_CONTROLS are absent because both are mandatory.
+	 * SAVE_IA32_PAT and SAVE_IA32_EFER are absent because KVM always
+	 * intercepts writes to PAT and EFER, i.e. never enables those controls.
+	 */
+	struct {
+		u32 entry_control;
+		u32 exit_control;
+	} const vmcs_entry_exit_pairs[] = {
+		{ VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,	VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL },
+		{ VM_ENTRY_LOAD_IA32_PAT,		VM_EXIT_LOAD_IA32_PAT },
+		{ VM_ENTRY_LOAD_IA32_EFER,		VM_EXIT_LOAD_IA32_EFER },
+		{ VM_ENTRY_LOAD_BNDCFGS,		VM_EXIT_CLEAR_BNDCFGS },
+		{ VM_ENTRY_LOAD_IA32_RTIT_CTL,		VM_EXIT_CLEAR_IA32_RTIT_CTL },
+	};
 
 	memset(vmcs_conf, 0, sizeof(*vmcs_conf));
 	min = CPU_BASED_HLT_EXITING |
@@ -2500,7 +2552,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 
 	opt = CPU_BASED_TPR_SHADOW |
 	      CPU_BASED_USE_MSR_BITMAPS |
-	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
+	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS |
+	      CPU_BASED_ACTIVATE_TERTIARY_CONTROLS;
 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 				&_cpu_based_exec_control) < 0)
 		return -EIO;
@@ -2533,7 +2586,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 			SECONDARY_EXEC_PT_USE_GPA |
 			SECONDARY_EXEC_PT_CONCEAL_VMX |
 			SECONDARY_EXEC_ENABLE_VMFUNC |
-			SECONDARY_EXEC_BUS_LOCK_DETECTION;
+			SECONDARY_EXEC_BUS_LOCK_DETECTION |
+			SECONDARY_EXEC_NOTIFY_VM_EXITING;
 		if (cpu_has_sgx())
 			opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
 		if (adjust_vmx_controls(min2, opt2,
@@ -2563,15 +2617,30 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 					     CPU_BASED_CR3_STORE_EXITING |
 					     CPU_BASED_INVLPG_EXITING);
 	} else if (vmx_cap->ept) {
-		vmx_cap->ept = 0;
 		pr_warn_once("EPT CAP should not exist if not support "
 				"1-setting enable EPT VM-execution control\n");
+
+		if (error_on_inconsistent_vmcs_config)
+			return -EIO;
+
+		vmx_cap->ept = 0;
 	}
 	if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
-		vmx_cap->vpid) {
-		vmx_cap->vpid = 0;
+	    vmx_cap->vpid) {
 		pr_warn_once("VPID CAP should not exist if not support "
 				"1-setting enable VPID VM-execution control\n");
+
+		if (error_on_inconsistent_vmcs_config)
+			return -EIO;
+
+		vmx_cap->vpid = 0;
+	}
+
+	if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) {
+		u64 opt3 = TERTIARY_EXEC_IPI_VIRT;
+
+		_cpu_based_3rd_exec_control = adjust_vmx_controls64(opt3,
+					      MSR_IA32_VMX_PROCBASED_CTLS3);
 	}
 
 	min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
@@ -2612,6 +2681,23 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 				&_vmentry_control) < 0)
 		return -EIO;
 
+	for (i = 0; i < ARRAY_SIZE(vmcs_entry_exit_pairs); i++) {
+		u32 n_ctrl = vmcs_entry_exit_pairs[i].entry_control;
+		u32 x_ctrl = vmcs_entry_exit_pairs[i].exit_control;
+
+		if (!(_vmentry_control & n_ctrl) == !(_vmexit_control & x_ctrl))
+			continue;
+
+		pr_warn_once("Inconsistent VM-Entry/VM-Exit pair, entry = %x, exit = %x\n",
+			     _vmentry_control & n_ctrl, _vmexit_control & x_ctrl);
+
+		if (error_on_inconsistent_vmcs_config)
+			return -EIO;
+
+		_vmentry_control &= ~n_ctrl;
+		_vmexit_control &= ~x_ctrl;
+	}
+
 	/*
 	 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
 	 * can't be used due to an errata where VM Exit may incorrectly clear
@@ -2660,6 +2746,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 	vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
 	vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
 	vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
+	vmcs_conf->cpu_based_3rd_exec_ctrl = _cpu_based_3rd_exec_control;
 	vmcs_conf->vmexit_ctrl         = _vmexit_control;
 	vmcs_conf->vmentry_ctrl        = _vmentry_control;
 
@@ -3684,7 +3771,7 @@ static int init_rmode_identity_map(struct kvm *kvm)
 	}
 
 	/* Set up identity-mapping pagetable for EPT in real mode */
-	for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
+	for (i = 0; i < (PAGE_SIZE / sizeof(tmp)); i++) {
 		tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
 			_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
 		if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
@@ -3914,6 +4001,8 @@ static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
 		vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
 		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
 		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
+		if (enable_ipiv)
+			vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW);
 	}
 }
 
@@ -3959,17 +4048,21 @@ static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
 	u32 i;
 
 	/*
-	 * Set intercept permissions for all potentially passed through MSRs
-	 * again. They will automatically get filtered through the MSR filter,
-	 * so we are back in sync after this.
+	 * Redo intercept permissions for MSRs that KVM is passing through to
+	 * the guest.  Disabling interception will check the new MSR filter and
+	 * ensure that KVM enables interception if usersepace wants to filter
+	 * the MSR.  MSRs that KVM is already intercepting don't need to be
+	 * refreshed since KVM is going to intercept them regardless of what
+	 * userspace wants.
 	 */
 	for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
 		u32 msr = vmx_possible_passthrough_msrs[i];
-		bool read = test_bit(i, vmx->shadow_msr_intercept.read);
-		bool write = test_bit(i, vmx->shadow_msr_intercept.write);
 
-		vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
-		vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
+		if (!test_bit(i, vmx->shadow_msr_intercept.read))
+			vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_R);
+
+		if (!test_bit(i, vmx->shadow_msr_intercept.write))
+			vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_W);
 	}
 
 	pt_update_intercept_for_msr(vcpu);
@@ -4067,7 +4160,8 @@ static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
 	if (!r)
 		return 0;
 
-	if (!vcpu->arch.apicv_active)
+	/* Note, this is called iff the local APIC is in-kernel. */
+	if (!vcpu->arch.apic->apicv_active)
 		return -1;
 
 	if (pi_test_and_set_pir(vector, &vmx->pi_desc))
@@ -4241,15 +4335,19 @@ static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
 	}
 
 	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
-	if (cpu_has_secondary_exec_ctrls()) {
-		if (kvm_vcpu_apicv_active(vcpu))
-			secondary_exec_controls_setbit(vmx,
-				      SECONDARY_EXEC_APIC_REGISTER_VIRT |
-				      SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
-		else
-			secondary_exec_controls_clearbit(vmx,
-					SECONDARY_EXEC_APIC_REGISTER_VIRT |
-					SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
+
+	if (kvm_vcpu_apicv_active(vcpu)) {
+		secondary_exec_controls_setbit(vmx,
+					       SECONDARY_EXEC_APIC_REGISTER_VIRT |
+					       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
+		if (enable_ipiv)
+			tertiary_exec_controls_setbit(vmx, TERTIARY_EXEC_IPI_VIRT);
+	} else {
+		secondary_exec_controls_clearbit(vmx,
+						 SECONDARY_EXEC_APIC_REGISTER_VIRT |
+						 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
+		if (enable_ipiv)
+			tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT);
 	}
 
 	vmx_update_msr_bitmap_x2apic(vcpu);
@@ -4281,6 +4379,20 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx)
 	return exec_control;
 }
 
+static u64 vmx_tertiary_exec_control(struct vcpu_vmx *vmx)
+{
+	u64 exec_control = vmcs_config.cpu_based_3rd_exec_ctrl;
+
+	/*
+	 * IPI virtualization relies on APICv. Disable IPI virtualization if
+	 * APICv is inhibited.
+	 */
+	if (!enable_ipiv || !kvm_vcpu_apicv_active(&vmx->vcpu))
+		exec_control &= ~TERTIARY_EXEC_IPI_VIRT;
+
+	return exec_control;
+}
+
 /*
  * Adjust a single secondary execution control bit to intercept/allow an
  * instruction in the guest.  This is usually done based on whether or not a
@@ -4423,13 +4535,48 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
 	if (!vcpu->kvm->arch.bus_lock_detection_enabled)
 		exec_control &= ~SECONDARY_EXEC_BUS_LOCK_DETECTION;
 
+	if (!kvm_notify_vmexit_enabled(vcpu->kvm))
+		exec_control &= ~SECONDARY_EXEC_NOTIFY_VM_EXITING;
+
 	return exec_control;
 }
 
+static inline int vmx_get_pid_table_order(struct kvm *kvm)
+{
+	return get_order(kvm->arch.max_vcpu_ids * sizeof(*to_kvm_vmx(kvm)->pid_table));
+}
+
+static int vmx_alloc_ipiv_pid_table(struct kvm *kvm)
+{
+	struct page *pages;
+	struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
+
+	if (!irqchip_in_kernel(kvm) || !enable_ipiv)
+		return 0;
+
+	if (kvm_vmx->pid_table)
+		return 0;
+
+	pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, vmx_get_pid_table_order(kvm));
+	if (!pages)
+		return -ENOMEM;
+
+	kvm_vmx->pid_table = (void *)page_address(pages);
+	return 0;
+}
+
+static int vmx_vcpu_precreate(struct kvm *kvm)
+{
+	return vmx_alloc_ipiv_pid_table(kvm);
+}
+
 #define VMX_XSS_EXIT_BITMAP 0
 
 static void init_vmcs(struct vcpu_vmx *vmx)
 {
+	struct kvm *kvm = vmx->vcpu.kvm;
+	struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
+
 	if (nested)
 		nested_vmx_set_vmcs_shadowing_bitmap();
 
@@ -4446,6 +4593,9 @@ static void init_vmcs(struct vcpu_vmx *vmx)
 	if (cpu_has_secondary_exec_ctrls())
 		secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
 
+	if (cpu_has_tertiary_exec_ctrls())
+		tertiary_exec_controls_set(vmx, vmx_tertiary_exec_control(vmx));
+
 	if (enable_apicv && lapic_in_kernel(&vmx->vcpu)) {
 		vmcs_write64(EOI_EXIT_BITMAP0, 0);
 		vmcs_write64(EOI_EXIT_BITMAP1, 0);
@@ -4458,12 +4608,20 @@ static void init_vmcs(struct vcpu_vmx *vmx)
 		vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
 	}
 
-	if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
+	if (vmx_can_use_ipiv(&vmx->vcpu)) {
+		vmcs_write64(PID_POINTER_TABLE, __pa(kvm_vmx->pid_table));
+		vmcs_write16(LAST_PID_POINTER_INDEX, kvm->arch.max_vcpu_ids - 1);
+	}
+
+	if (!kvm_pause_in_guest(kvm)) {
 		vmcs_write32(PLE_GAP, ple_gap);
 		vmx->ple_window = ple_window;
 		vmx->ple_window_dirty = true;
 	}
 
+	if (kvm_notify_vmexit_enabled(kvm))
+		vmcs_write32(NOTIFY_WINDOW, kvm->arch.notify_window);
+
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
 	vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
@@ -4634,13 +4792,13 @@ static void vmx_enable_nmi_window(struct kvm_vcpu *vcpu)
 	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
 }
 
-static void vmx_inject_irq(struct kvm_vcpu *vcpu)
+static void vmx_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
 {
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 	uint32_t intr;
 	int irq = vcpu->arch.interrupt.nr;
 
-	trace_kvm_inj_virq(irq);
+	trace_kvm_inj_virq(irq, vcpu->arch.interrupt.soft, reinjected);
 
 	++vcpu->stat.irq_injections;
 	if (vmx->rmode.vm86_active) {
@@ -5752,6 +5910,32 @@ static int handle_bus_lock_vmexit(struct kvm_vcpu *vcpu)
 	return 1;
 }
 
+static int handle_notify(struct kvm_vcpu *vcpu)
+{
+	unsigned long exit_qual = vmx_get_exit_qual(vcpu);
+	bool context_invalid = exit_qual & NOTIFY_VM_CONTEXT_INVALID;
+
+	++vcpu->stat.notify_window_exits;
+
+	/*
+	 * Notify VM exit happened while executing iret from NMI,
+	 * "blocked by NMI" bit has to be set before next VM entry.
+	 */
+	if (enable_vnmi && (exit_qual & INTR_INFO_UNBLOCK_NMI))
+		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
+			      GUEST_INTR_STATE_NMI);
+
+	if (vcpu->kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_USER ||
+	    context_invalid) {
+		vcpu->run->exit_reason = KVM_EXIT_NOTIFY;
+		vcpu->run->notify.flags = context_invalid ?
+					  KVM_NOTIFY_CONTEXT_INVALID : 0;
+		return 0;
+	}
+
+	return 1;
+}
+
 /*
  * The exit handlers return 1 if the exit was handled fully and guest execution
  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
@@ -5809,6 +5993,7 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
 	[EXIT_REASON_PREEMPTION_TIMER]	      = handle_preemption_timer,
 	[EXIT_REASON_ENCLS]		      = handle_encls,
 	[EXIT_REASON_BUS_LOCK]                = handle_bus_lock_vmexit,
+	[EXIT_REASON_NOTIFY]		      = handle_notify,
 };
 
 static const int kvm_vmx_max_exit_handlers =
@@ -5906,6 +6091,7 @@ void dump_vmcs(struct kvm_vcpu *vcpu)
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 	u32 vmentry_ctl, vmexit_ctl;
 	u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
+	u64 tertiary_exec_control;
 	unsigned long cr4;
 	int efer_slot;
 
@@ -5919,9 +6105,16 @@ void dump_vmcs(struct kvm_vcpu *vcpu)
 	cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
 	pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
 	cr4 = vmcs_readl(GUEST_CR4);
-	secondary_exec_control = 0;
+
 	if (cpu_has_secondary_exec_ctrls())
 		secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+	else
+		secondary_exec_control = 0;
+
+	if (cpu_has_tertiary_exec_ctrls())
+		tertiary_exec_control = vmcs_read64(TERTIARY_VM_EXEC_CONTROL);
+	else
+		tertiary_exec_control = 0;
 
 	pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
 	       vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
@@ -6021,9 +6214,10 @@ void dump_vmcs(struct kvm_vcpu *vcpu)
 		vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
 
 	pr_err("*** Control State ***\n");
-	pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
-	       pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
-	pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
+	pr_err("CPUBased=0x%08x SecondaryExec=0x%08x TertiaryExec=0x%016llx\n",
+	       cpu_based_exec_ctrl, secondary_exec_control, tertiary_exec_control);
+	pr_err("PinBased=0x%08x EntryControls=%08x ExitControls=%08x\n",
+	       pin_based_exec_ctrl, vmentry_ctl, vmexit_ctl);
 	pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
 	       vmcs_read32(EXCEPTION_BITMAP),
 	       vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
@@ -6173,7 +6367,8 @@ static int __vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
 	     exit_reason.basic != EXIT_REASON_EPT_VIOLATION &&
 	     exit_reason.basic != EXIT_REASON_PML_FULL &&
 	     exit_reason.basic != EXIT_REASON_APIC_ACCESS &&
-	     exit_reason.basic != EXIT_REASON_TASK_SWITCH)) {
+	     exit_reason.basic != EXIT_REASON_TASK_SWITCH &&
+	     exit_reason.basic != EXIT_REASON_NOTIFY)) {
 		int ndata = 3;
 
 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
@@ -6435,7 +6630,7 @@ static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
 	put_page(page);
 }
 
-static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
+static void vmx_hwapic_isr_update(int max_isr)
 {
 	u16 status;
 	u8 old;
@@ -6765,9 +6960,14 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
 {
 	int i, nr_msrs;
 	struct perf_guest_switch_msr *msrs;
+	struct kvm_pmu *pmu = vcpu_to_pmu(&vmx->vcpu);
+
+	pmu->host_cross_mapped_mask = 0;
+	if (pmu->pebs_enable & pmu->global_ctrl)
+		intel_pmu_cross_mapped_check(pmu);
 
 	/* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
-	msrs = perf_guest_get_msrs(&nr_msrs);
+	msrs = perf_guest_get_msrs(&nr_msrs, (void *)pmu);
 	if (!msrs)
 		return;
 
@@ -7150,6 +7350,10 @@ static int vmx_vcpu_create(struct kvm_vcpu *vcpu)
 			goto free_vmcs;
 	}
 
+	if (vmx_can_use_ipiv(vcpu))
+		WRITE_ONCE(to_kvm_vmx(vcpu->kvm)->pid_table[vcpu->vcpu_id],
+			   __pa(&vmx->pi_desc) | PID_TABLE_ENTRY_VALID);
+
 	return 0;
 
 free_vmcs:
@@ -7486,6 +7690,13 @@ static __init void vmx_set_cpu_caps(void)
 		kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
 	if (vmx_pt_mode_is_host_guest())
 		kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
+	if (vmx_pebs_supported()) {
+		kvm_cpu_cap_check_and_set(X86_FEATURE_DS);
+		kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64);
+	}
+
+	if (!enable_pmu)
+		kvm_cpu_cap_clear(X86_FEATURE_PDCM);
 
 	if (!enable_sgx) {
 		kvm_cpu_cap_clear(X86_FEATURE_SGX);
@@ -7498,7 +7709,7 @@ static __init void vmx_set_cpu_caps(void)
 		kvm_cpu_cap_set(X86_FEATURE_UMIP);
 
 	/* CPUID 0xD.1 */
-	supported_xss = 0;
+	kvm_caps.supported_xss = 0;
 	if (!cpu_has_vmx_xsaves())
 		kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
 
@@ -7639,9 +7850,9 @@ static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
 		delta_tsc = 0;
 
 	/* Convert to host delta tsc if tsc scaling is enabled */
-	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
+	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio &&
 	    delta_tsc && u64_shl_div_u64(delta_tsc,
-				kvm_tsc_scaling_ratio_frac_bits,
+				kvm_caps.tsc_scaling_ratio_frac_bits,
 				vcpu->arch.l1_tsc_scaling_ratio, &delta_tsc))
 		return -ERANGE;
 
@@ -7713,6 +7924,13 @@ static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
 {
 	struct vcpu_vmx *vmx = to_vmx(vcpu);
 
+	/*
+	 * TODO: Implement custom flows for forcing the vCPU out/in of L2 on
+	 * SMI and RSM.  Using the common VM-Exit + VM-Enter routines is wrong
+	 * SMI and RSM only modify state that is saved and restored via SMRAM.
+	 * E.g. most MSRs are left untouched, but many are modified by VM-Exit
+	 * and VM-Enter, and thus L2's values may be corrupted on SMI+RSM.
+	 */
 	vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
 	if (vmx->nested.smm.guest_mode)
 		nested_vmx_vmexit(vcpu, -1, 0, 0);
@@ -7786,6 +8004,13 @@ static bool vmx_check_apicv_inhibit_reasons(enum kvm_apicv_inhibit reason)
 	return supported & BIT(reason);
 }
 
+static void vmx_vm_destroy(struct kvm *kvm)
+{
+	struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
+
+	free_pages((unsigned long)kvm_vmx->pid_table, vmx_get_pid_table_order(kvm));
+}
+
 static struct kvm_x86_ops vmx_x86_ops __initdata = {
 	.name = "kvm_intel",
 
@@ -7797,7 +8022,9 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = {
 
 	.vm_size = sizeof(struct kvm_vmx),
 	.vm_init = vmx_vm_init,
+	.vm_destroy = vmx_vm_destroy,
 
+	.vcpu_precreate = vmx_vcpu_precreate,
 	.vcpu_create = vmx_vcpu_create,
 	.vcpu_free = vmx_vcpu_free,
 	.vcpu_reset = vmx_vcpu_reset,
@@ -8011,8 +8238,8 @@ static __init int hardware_setup(void)
 	}
 
 	if (!cpu_has_vmx_mpx())
-		supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
-				    XFEATURE_MASK_BNDCSR);
+		kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
+					     XFEATURE_MASK_BNDCSR);
 
 	if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
 	    !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
@@ -8075,12 +8302,16 @@ static __init int hardware_setup(void)
 	if (!enable_apicv)
 		vmx_x86_ops.sync_pir_to_irr = NULL;
 
+	if (!enable_apicv || !cpu_has_vmx_ipiv())
+		enable_ipiv = false;
+
 	if (cpu_has_vmx_tsc_scaling())
-		kvm_has_tsc_control = true;
+		kvm_caps.has_tsc_control = true;
 
-	kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
-	kvm_tsc_scaling_ratio_frac_bits = 48;
-	kvm_has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
+	kvm_caps.max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
+	kvm_caps.tsc_scaling_ratio_frac_bits = 48;
+	kvm_caps.has_bus_lock_exit = cpu_has_vmx_bus_lock_detection();
+	kvm_caps.has_notify_vmexit = cpu_has_notify_vmexit();
 
 	set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
 
@@ -8137,11 +8368,11 @@ static __init int hardware_setup(void)
 		vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
 	}
 
-	kvm_mce_cap_supported |= MCG_LMCE_P;
+	kvm_caps.supported_mce_cap |= MCG_LMCE_P;
 
 	if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
 		return -EINVAL;
-	if (!enable_ept || !cpu_has_vmx_intel_pt())
+	if (!enable_ept || !enable_pmu || !cpu_has_vmx_intel_pt())
 		pt_mode = PT_MODE_SYSTEM;
 	if (pt_mode == PT_MODE_HOST_GUEST)
 		vmx_init_ops.handle_intel_pt_intr = vmx_handle_intel_pt_intr;
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 8d2342ede0c5..2f32828a395c 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -94,7 +94,7 @@ union vmx_exit_reason {
 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
 
-bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
+void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
 
 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
@@ -204,7 +204,7 @@ struct nested_vmx {
 	 * Guest pages referred to in the vmcs02 with host-physical
 	 * pointers, so we must keep them pinned while L2 runs.
 	 */
-	struct page *apic_access_page;
+	struct kvm_host_map apic_access_page_map;
 	struct kvm_host_map virtual_apic_map;
 	struct kvm_host_map pi_desc_map;
 
@@ -219,9 +219,18 @@ struct nested_vmx {
 	bool has_preemption_timer_deadline;
 	bool preemption_timer_expired;
 
-	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
-	u64 vmcs01_debugctl;
-	u64 vmcs01_guest_bndcfgs;
+	/*
+	 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
+	 * order to propagate the guest's pre-VM-Enter value into vmcs02.  For
+	 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
+	 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
+	 * userspace restores MSRs before nested state.  If userspace restores
+	 * MSRs after nested state, the snapshot holds garbage, but KVM can't
+	 * detect that, and the garbage value in vmcs02 will be overwritten by
+	 * MSR restoration in any case.
+	 */
+	u64 pre_vmenter_debugctl;
+	u64 pre_vmenter_bndcfgs;
 
 	/* to migrate it to L1 if L2 writes to L1's CR8 directly */
 	int l1_tpr_threshold;
@@ -368,6 +377,8 @@ struct kvm_vmx {
 	unsigned int tss_addr;
 	bool ept_identity_pagetable_done;
 	gpa_t ept_identity_map_addr;
+	/* Posted Interrupt Descriptor (PID) table for IPI virtualization */
+	u64 *pid_table;
 };
 
 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
@@ -458,35 +469,36 @@ static inline u8 vmx_get_rvi(void)
 	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 }
 
-#define BUILD_CONTROLS_SHADOW(lname, uname)				    \
-static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)	    \
-{									    \
-	if (vmx->loaded_vmcs->controls_shadow.lname != val) {		    \
-		vmcs_write32(uname, val);				    \
-		vmx->loaded_vmcs->controls_shadow.lname = val;		    \
-	}								    \
-}									    \
-static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs)	    \
-{									    \
-	return vmcs->controls_shadow.lname;				    \
-}									    \
-static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)		    \
-{									    \
-	return __##lname##_controls_get(vmx->loaded_vmcs);		    \
-}									    \
-static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
-{									    \
-	lname##_controls_set(vmx, lname##_controls_get(vmx) | val);	    \
-}									    \
-static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
-{									    \
-	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);	    \
+#define BUILD_CONTROLS_SHADOW(lname, uname, bits)				\
+static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val)	\
+{										\
+	if (vmx->loaded_vmcs->controls_shadow.lname != val) {			\
+		vmcs_write##bits(uname, val);					\
+		vmx->loaded_vmcs->controls_shadow.lname = val;			\
+	}									\
+}										\
+static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs)	\
+{										\
+	return vmcs->controls_shadow.lname;					\
+}										\
+static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx)		\
+{										\
+	return __##lname##_controls_get(vmx->loaded_vmcs);			\
+}										\
+static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val)	\
+{										\
+	lname##_controls_set(vmx, lname##_controls_get(vmx) | val);		\
+}										\
+static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val)	\
+{										\
+	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);		\
 }
-BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
-BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
-BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
-BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
-BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
+BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
+BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
+BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
+BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
+BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
+BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
 
 /*
  * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
@@ -582,4 +594,9 @@ static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
 	return (vmx_instr_info >> 28) & 0xf;
 }
 
+static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
+{
+	return  lapic_in_kernel(vcpu) && enable_ipiv;
+}
+
 #endif /* __KVM_X86_VMX_H */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 1910e1e78b15..9721b2d5e515 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -87,8 +87,11 @@
 
 #define MAX_IO_MSRS 256
 #define KVM_MAX_MCE_BANKS 32
-u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
-EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
+
+struct kvm_caps kvm_caps __read_mostly = {
+	.supported_mce_cap = MCG_CTL_P | MCG_SER_P,
+};
+EXPORT_SYMBOL_GPL(kvm_caps);
 
 #define  ERR_PTR_USR(e)  ((void __user *)ERR_PTR(e))
 
@@ -151,19 +154,6 @@ module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 static bool __read_mostly kvmclock_periodic_sync = true;
 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 
-bool __read_mostly kvm_has_tsc_control;
-EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
-u32  __read_mostly kvm_max_guest_tsc_khz;
-EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
-u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
-EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
-u64  __read_mostly kvm_max_tsc_scaling_ratio;
-EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
-u64 __read_mostly kvm_default_tsc_scaling_ratio;
-EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
-bool __read_mostly kvm_has_bus_lock_exit;
-EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
-
 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 static u32 __read_mostly tsc_tolerance_ppm = 250;
 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
@@ -235,8 +225,6 @@ EXPORT_SYMBOL_GPL(enable_apicv);
 
 u64 __read_mostly host_xss;
 EXPORT_SYMBOL_GPL(host_xss);
-u64 __read_mostly supported_xss;
-EXPORT_SYMBOL_GPL(supported_xss);
 
 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
 	KVM_GENERIC_VM_STATS(),
@@ -298,7 +286,8 @@ const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
 	STATS_DESC_COUNTER(VCPU, directed_yield_successful),
 	STATS_DESC_COUNTER(VCPU, preemption_reported),
 	STATS_DESC_COUNTER(VCPU, preemption_other),
-	STATS_DESC_ICOUNTER(VCPU, guest_mode)
+	STATS_DESC_ICOUNTER(VCPU, guest_mode),
+	STATS_DESC_COUNTER(VCPU, notify_window_exits),
 };
 
 const struct kvm_stats_header kvm_vcpu_stats_header = {
@@ -311,8 +300,6 @@ const struct kvm_stats_header kvm_vcpu_stats_header = {
 };
 
 u64 __read_mostly host_xcr0;
-u64 __read_mostly supported_xcr0;
-EXPORT_SYMBOL_GPL(supported_xcr0);
 
 static struct kmem_cache *x86_emulator_cache;
 
@@ -1450,6 +1437,7 @@ static const u32 msrs_to_save_all[] = {
 	MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
 	MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
 	MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
+	MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
 
 	MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
 	MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
@@ -2349,12 +2337,12 @@ static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 
 	/* Guest TSC same frequency as host TSC? */
 	if (!scale) {
-		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
+		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
 		return 0;
 	}
 
 	/* TSC scaling supported? */
-	if (!kvm_has_tsc_control) {
+	if (!kvm_caps.has_tsc_control) {
 		if (user_tsc_khz > tsc_khz) {
 			vcpu->arch.tsc_catchup = 1;
 			vcpu->arch.tsc_always_catchup = 1;
@@ -2366,10 +2354,10 @@ static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 	}
 
 	/* TSC scaling required  - calculate ratio */
-	ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
+	ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
 				user_tsc_khz, tsc_khz);
 
-	if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
+	if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
 		pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
 			            user_tsc_khz);
 		return -1;
@@ -2387,7 +2375,7 @@ static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
 	/* tsc_khz can be zero if TSC calibration fails */
 	if (user_tsc_khz == 0) {
 		/* set tsc_scaling_ratio to a safe value */
-		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
+		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
 		return -1;
 	}
 
@@ -2464,18 +2452,18 @@ static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
  * (frac) represent the fractional part, ie. ratio represents a fixed
  * point number (mult + frac * 2^(-N)).
  *
- * N equals to kvm_tsc_scaling_ratio_frac_bits.
+ * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
  */
 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
 {
-	return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
+	return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
 }
 
 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
 {
 	u64 _tsc = tsc;
 
-	if (ratio != kvm_default_tsc_scaling_ratio)
+	if (ratio != kvm_caps.default_tsc_scaling_ratio)
 		_tsc = __scale_tsc(ratio, tsc);
 
 	return _tsc;
@@ -2502,11 +2490,11 @@ u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
 {
 	u64 nested_offset;
 
-	if (l2_multiplier == kvm_default_tsc_scaling_ratio)
+	if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
 		nested_offset = l1_offset;
 	else
 		nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
-						kvm_tsc_scaling_ratio_frac_bits);
+						kvm_caps.tsc_scaling_ratio_frac_bits);
 
 	nested_offset += l2_offset;
 	return nested_offset;
@@ -2515,9 +2503,9 @@ EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
 
 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
 {
-	if (l2_multiplier != kvm_default_tsc_scaling_ratio)
+	if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
 		return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
-				       kvm_tsc_scaling_ratio_frac_bits);
+				       kvm_caps.tsc_scaling_ratio_frac_bits);
 
 	return l1_multiplier;
 }
@@ -2559,7 +2547,7 @@ static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multipli
 	else
 		vcpu->arch.tsc_scaling_ratio = l1_multiplier;
 
-	if (kvm_has_tsc_control)
+	if (kvm_caps.has_tsc_control)
 		static_call(kvm_x86_write_tsc_multiplier)(
 			vcpu, vcpu->arch.tsc_scaling_ratio);
 }
@@ -2695,7 +2683,7 @@ static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
 
 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
 {
-	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
+	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
 		WARN_ON(adjustment < 0);
 	adjustment = kvm_scale_tsc((u64) adjustment,
 				   vcpu->arch.l1_tsc_scaling_ratio);
@@ -3108,7 +3096,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
 
 	/* With all the info we got, fill in the values */
 
-	if (kvm_has_tsc_control)
+	if (kvm_caps.has_tsc_control)
 		tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
 					    v->arch.l1_tsc_scaling_ratio);
 
@@ -3239,10 +3227,13 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			/* only 0 or all 1s can be written to IA32_MCi_CTL
 			 * some Linux kernels though clear bit 10 in bank 4 to
 			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
-			 * this to avoid an uncatched #GP in the guest
+			 * this to avoid an uncatched #GP in the guest.
+			 *
+			 * UNIXWARE clears bit 0 of MC1_CTL to ignore
+			 * correctable, single-bit ECC data errors.
 			 */
 			if ((offset & 0x3) == 0 &&
-			    data != 0 && (data | (1 << 10)) != ~(u64)0)
+			    data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
 				return -1;
 
 			/* MCi_STATUS */
@@ -3560,9 +3551,25 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			vcpu->arch.ia32_tsc_adjust_msr = data;
 		}
 		break;
-	case MSR_IA32_MISC_ENABLE:
+	case MSR_IA32_MISC_ENABLE: {
+		u64 old_val = vcpu->arch.ia32_misc_enable_msr;
+		u64 pmu_mask = MSR_IA32_MISC_ENABLE_PMU_RO_MASK |
+			MSR_IA32_MISC_ENABLE_EMON;
+
+		/* RO bits */
+		if (!msr_info->host_initiated &&
+		    ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK))
+			return 1;
+
+		/*
+		 * For a dummy user space, the order of setting vPMU capabilities and
+		 * initialising MSR_IA32_MISC_ENABLE is not strictly guaranteed, so to
+		 * avoid inconsistent functionality we keep the vPMU bits unchanged here.
+		 */
+		data &= ~pmu_mask;
+		data |= old_val & pmu_mask;
 		if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
-		    ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
+		    ((old_val ^ data)  & MSR_IA32_MISC_ENABLE_MWAIT)) {
 			if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
 				return 1;
 			vcpu->arch.ia32_misc_enable_msr = data;
@@ -3571,6 +3578,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			vcpu->arch.ia32_misc_enable_msr = data;
 		}
 		break;
+	}
 	case MSR_IA32_SMBASE:
 		if (!msr_info->host_initiated)
 			return 1;
@@ -3597,7 +3605,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
 		 * XSAVES/XRSTORS to save/restore PT MSRs.
 		 */
-		if (data & ~supported_xss)
+		if (data & ~kvm_caps.supported_xss)
 			return 1;
 		vcpu->arch.ia32_xss = data;
 		kvm_update_cpuid_runtime(vcpu);
@@ -3703,7 +3711,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		fallthrough;
 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
-		if (kvm_pmu_is_valid_msr(vcpu, msr))
+		if (kvm_pmu_is_valid_msr(vcpu, msr, msr_info->host_initiated))
 			return kvm_pmu_set_msr(vcpu, msr_info);
 
 		if (pr || data != 0)
@@ -3786,7 +3794,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		break;
 #endif
 	default:
-		if (kvm_pmu_is_valid_msr(vcpu, msr))
+		if (kvm_pmu_is_valid_msr(vcpu, msr, msr_info->host_initiated))
 			return kvm_pmu_set_msr(vcpu, msr_info);
 		return KVM_MSR_RET_INVALID;
 	}
@@ -3866,7 +3874,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		msr_info->data = 0;
 		break;
 	case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
-		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
+		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index, msr_info->host_initiated))
 			return kvm_pmu_get_msr(vcpu, msr_info);
 		if (!msr_info->host_initiated)
 			return 1;
@@ -3876,7 +3884,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
-		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
+		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index, msr_info->host_initiated))
 			return kvm_pmu_get_msr(vcpu, msr_info);
 		msr_info->data = 0;
 		break;
@@ -4122,7 +4130,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		break;
 #endif
 	default:
-		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
+		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index, msr_info->host_initiated))
 			return kvm_pmu_get_msr(vcpu, msr_info);
 		return KVM_MSR_RET_INVALID;
 	}
@@ -4280,6 +4288,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 	case KVM_CAP_GET_MSR_FEATURES:
 	case KVM_CAP_MSR_PLATFORM_INFO:
 	case KVM_CAP_EXCEPTION_PAYLOAD:
+	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
 	case KVM_CAP_SET_GUEST_DEBUG:
 	case KVM_CAP_LAST_CPU:
 	case KVM_CAP_X86_USER_SPACE_MSR:
@@ -4357,7 +4366,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		break;
 	case KVM_CAP_TSC_CONTROL:
 	case KVM_CAP_VM_TSC_CONTROL:
-		r = kvm_has_tsc_control;
+		r = kvm_caps.has_tsc_control;
 		break;
 	case KVM_CAP_X2APIC_API:
 		r = KVM_X2APIC_API_VALID_FLAGS;
@@ -4379,7 +4388,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		r = sched_info_on();
 		break;
 	case KVM_CAP_X86_BUS_LOCK_EXIT:
-		if (kvm_has_bus_lock_exit)
+		if (kvm_caps.has_bus_lock_exit)
 			r = KVM_BUS_LOCK_DETECTION_OFF |
 			    KVM_BUS_LOCK_DETECTION_EXIT;
 		else
@@ -4388,7 +4397,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 	case KVM_CAP_XSAVE2: {
 		u64 guest_perm = xstate_get_guest_group_perm();
 
-		r = xstate_required_size(supported_xcr0 & guest_perm, false);
+		r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
 		if (r < sizeof(struct kvm_xsave))
 			r = sizeof(struct kvm_xsave);
 		break;
@@ -4399,6 +4408,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 	case KVM_CAP_DISABLE_QUIRKS2:
 		r = KVM_X86_VALID_QUIRKS;
 		break;
+	case KVM_CAP_X86_NOTIFY_VMEXIT:
+		r = kvm_caps.has_notify_vmexit;
+		break;
 	default:
 		break;
 	}
@@ -4426,7 +4438,7 @@ static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
 
 	switch (attr->attr) {
 	case KVM_X86_XCOMP_GUEST_SUPP:
-		if (put_user(supported_xcr0, uaddr))
+		if (put_user(kvm_caps.supported_xcr0, uaddr))
 			return -EFAULT;
 		return 0;
 	default:
@@ -4503,8 +4515,8 @@ long kvm_arch_dev_ioctl(struct file *filp,
 	}
 	case KVM_X86_GET_MCE_CAP_SUPPORTED:
 		r = -EFAULT;
-		if (copy_to_user(argp, &kvm_mce_cap_supported,
-				 sizeof(kvm_mce_cap_supported)))
+		if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
+				 sizeof(kvm_caps.supported_mce_cap)))
 			goto out;
 		r = 0;
 		break;
@@ -4803,7 +4815,7 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
 	r = -EINVAL;
 	if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
 		goto out;
-	if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
+	if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
 		goto out;
 	r = 0;
 	vcpu->arch.mcg_cap = mcg_cap;
@@ -4941,6 +4953,10 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
 			 | KVM_VCPUEVENT_VALID_SMM);
 	if (vcpu->kvm->arch.exception_payload_enabled)
 		events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
+	if (vcpu->kvm->arch.triple_fault_event) {
+		events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
+		events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
+	}
 
 	memset(&events->reserved, 0, sizeof(events->reserved));
 }
@@ -4954,7 +4970,8 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
 			      | KVM_VCPUEVENT_VALID_SIPI_VECTOR
 			      | KVM_VCPUEVENT_VALID_SHADOW
 			      | KVM_VCPUEVENT_VALID_SMM
-			      | KVM_VCPUEVENT_VALID_PAYLOAD))
+			      | KVM_VCPUEVENT_VALID_PAYLOAD
+			      | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
 		return -EINVAL;
 
 	if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
@@ -5027,6 +5044,15 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
 		}
 	}
 
+	if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
+		if (!vcpu->kvm->arch.triple_fault_event)
+			return -EINVAL;
+		if (events->triple_fault.pending)
+			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
+		else
+			kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
+	}
+
 	kvm_make_request(KVM_REQ_EVENT, vcpu);
 
 	return 0;
@@ -5095,7 +5121,8 @@ static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
 
 	return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
 					      guest_xsave->region,
-					      supported_xcr0, &vcpu->arch.pkru);
+					      kvm_caps.supported_xcr0,
+					      &vcpu->arch.pkru);
 }
 
 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
@@ -5600,8 +5627,8 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
 		r = -EINVAL;
 		user_tsc_khz = (u32)arg;
 
-		if (kvm_has_tsc_control &&
-		    user_tsc_khz >= kvm_max_guest_tsc_khz)
+		if (kvm_caps.has_tsc_control &&
+		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
 			goto out;
 
 		if (user_tsc_khz == 0)
@@ -6028,6 +6055,10 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 		kvm->arch.exception_payload_enabled = cap->args[0];
 		r = 0;
 		break;
+	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
+		kvm->arch.triple_fault_event = cap->args[0];
+		r = 0;
+		break;
 	case KVM_CAP_X86_USER_SPACE_MSR:
 		kvm->arch.user_space_msr_mask = cap->args[0];
 		r = 0;
@@ -6041,7 +6072,7 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 		    (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
 			break;
 
-		if (kvm_has_bus_lock_exit &&
+		if (kvm_caps.has_bus_lock_exit &&
 		    cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
 			kvm->arch.bus_lock_detection_enabled = true;
 		r = 0;
@@ -6104,6 +6135,36 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
 		}
 		mutex_unlock(&kvm->lock);
 		break;
+	case KVM_CAP_MAX_VCPU_ID:
+		r = -EINVAL;
+		if (cap->args[0] > KVM_MAX_VCPU_IDS)
+			break;
+
+		mutex_lock(&kvm->lock);
+		if (kvm->arch.max_vcpu_ids == cap->args[0]) {
+			r = 0;
+		} else if (!kvm->arch.max_vcpu_ids) {
+			kvm->arch.max_vcpu_ids = cap->args[0];
+			r = 0;
+		}
+		mutex_unlock(&kvm->lock);
+		break;
+	case KVM_CAP_X86_NOTIFY_VMEXIT:
+		r = -EINVAL;
+		if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
+			break;
+		if (!kvm_caps.has_notify_vmexit)
+			break;
+		if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
+			break;
+		mutex_lock(&kvm->lock);
+		if (!kvm->created_vcpus) {
+			kvm->arch.notify_window = cap->args[0] >> 32;
+			kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
+			r = 0;
+		}
+		mutex_unlock(&kvm->lock);
+		break;
 	default:
 		r = -EINVAL;
 		break;
@@ -6576,8 +6637,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 		r = -EINVAL;
 		user_tsc_khz = (u32)arg;
 
-		if (kvm_has_tsc_control &&
-		    user_tsc_khz >= kvm_max_guest_tsc_khz)
+		if (kvm_caps.has_tsc_control &&
+		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
 			goto out;
 
 		if (user_tsc_khz == 0)
@@ -6652,15 +6713,12 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 static void kvm_init_msr_list(void)
 {
-	struct x86_pmu_capability x86_pmu;
 	u32 dummy[2];
 	unsigned i;
 
 	BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
 			 "Please update the fixed PMCs in msrs_to_saved_all[]");
 
-	perf_get_x86_pmu_capability(&x86_pmu);
-
 	num_msrs_to_save = 0;
 	num_emulated_msrs = 0;
 	num_msr_based_features = 0;
@@ -6712,12 +6770,12 @@ static void kvm_init_msr_list(void)
 			break;
 		case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
 			if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
-			    min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
+			    min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
 				continue;
 			break;
 		case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
 			if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
-			    min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
+			    min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
 				continue;
 			break;
 		case MSR_IA32_XFD:
@@ -7860,7 +7918,16 @@ static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
 	return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
 }
 
+static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
+{
+	struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
+
+	if (!kvm->vm_bugged)
+		kvm_vm_bugged(kvm);
+}
+
 static const struct x86_emulate_ops emulate_ops = {
+	.vm_bugged           = emulator_vm_bugged,
 	.read_gpr            = emulator_read_gpr,
 	.write_gpr           = emulator_write_gpr,
 	.read_std            = emulator_read_std,
@@ -8743,7 +8810,7 @@ static void kvm_hyperv_tsc_notifier(void)
 	/* TSC frequency always matches when on Hyper-V */
 	for_each_present_cpu(cpu)
 		per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
-	kvm_max_guest_tsc_khz = tsc_khz;
+	kvm_caps.max_guest_tsc_khz = tsc_khz;
 
 	list_for_each_entry(kvm, &vm_list, vm_list) {
 		__kvm_start_pvclock_update(kvm);
@@ -9005,7 +9072,7 @@ int kvm_arch_init(void *opaque)
 
 	if (boot_cpu_has(X86_FEATURE_XSAVE)) {
 		host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
-		supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
+		kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
 	}
 
 	if (pi_inject_timer == -1)
@@ -9396,7 +9463,7 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
 	if (!lapic_in_kernel(vcpu))
 		return;
 
-	if (vcpu->arch.apicv_active)
+	if (vcpu->arch.apic->apicv_active)
 		return;
 
 	if (!vcpu->arch.apic->vapic_addr)
@@ -9425,6 +9492,11 @@ int kvm_check_nested_events(struct kvm_vcpu *vcpu)
 
 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
 {
+	trace_kvm_inj_exception(vcpu->arch.exception.nr,
+				vcpu->arch.exception.has_error_code,
+				vcpu->arch.exception.error_code,
+				vcpu->arch.exception.injected);
+
 	if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
 		vcpu->arch.exception.error_code = false;
 	static_call(kvm_x86_queue_exception)(vcpu);
@@ -9460,7 +9532,7 @@ static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
 			static_call(kvm_x86_inject_nmi)(vcpu);
 			can_inject = false;
 		} else if (vcpu->arch.interrupt.injected) {
-			static_call(kvm_x86_inject_irq)(vcpu);
+			static_call(kvm_x86_inject_irq)(vcpu, true);
 			can_inject = false;
 		}
 	}
@@ -9482,13 +9554,6 @@ static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
 
 	/* try to inject new event if pending */
 	if (vcpu->arch.exception.pending) {
-		trace_kvm_inj_exception(vcpu->arch.exception.nr,
-					vcpu->arch.exception.has_error_code,
-					vcpu->arch.exception.error_code);
-
-		vcpu->arch.exception.pending = false;
-		vcpu->arch.exception.injected = true;
-
 		if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
 			__kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
 					     X86_EFLAGS_RF);
@@ -9502,6 +9567,10 @@ static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
 		}
 
 		kvm_inject_exception(vcpu);
+
+		vcpu->arch.exception.pending = false;
+		vcpu->arch.exception.injected = true;
+
 		can_inject = false;
 	}
 
@@ -9554,7 +9623,7 @@ static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
 			goto out;
 		if (r) {
 			kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
-			static_call(kvm_x86_inject_irq)(vcpu);
+			static_call(kvm_x86_inject_irq)(vcpu, false);
 			WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
 		}
 		if (kvm_cpu_has_injectable_intr(vcpu))
@@ -9847,6 +9916,7 @@ void kvm_make_scan_ioapic_request(struct kvm *kvm)
 
 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
 {
+	struct kvm_lapic *apic = vcpu->arch.apic;
 	bool activate;
 
 	if (!lapic_in_kernel(vcpu))
@@ -9857,10 +9927,10 @@ void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
 
 	activate = kvm_vcpu_apicv_activated(vcpu);
 
-	if (vcpu->arch.apicv_active == activate)
+	if (apic->apicv_active == activate)
 		goto out;
 
-	vcpu->arch.apicv_active = activate;
+	apic->apicv_active = activate;
 	kvm_apic_update_apicv(vcpu);
 	static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
 
@@ -9870,7 +9940,7 @@ void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
 	 * still active when the interrupt got accepted. Make sure
 	 * inject_pending_event() is called to check for that.
 	 */
-	if (!vcpu->arch.apicv_active)
+	if (!apic->apicv_active)
 		kvm_make_request(KVM_REQ_EVENT, vcpu);
 
 out:
@@ -11266,11 +11336,17 @@ static int sync_regs(struct kvm_vcpu *vcpu)
 
 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 {
-	if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
+	if (kvm_check_tsc_unstable() && kvm->created_vcpus)
 		pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
 			     "guest TSC will not be reliable\n");
 
-	return 0;
+	if (!kvm->arch.max_vcpu_ids)
+		kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
+
+	if (id >= kvm->arch.max_vcpu_ids)
+		return -EINVAL;
+
+	return static_call(kvm_x86_vcpu_precreate)(kvm);
 }
 
 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
@@ -11307,7 +11383,7 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 		 * will ensure the vCPU gets the correct state before VM-Entry.
 		 */
 		if (enable_apicv) {
-			vcpu->arch.apicv_active = true;
+			vcpu->arch.apic->apicv_active = true;
 			kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
 		}
 	} else
@@ -11707,6 +11783,8 @@ int kvm_arch_hardware_setup(void *opaque)
 	if (boot_cpu_has(X86_FEATURE_XSAVES))
 		rdmsrl(MSR_IA32_XSS, host_xss);
 
+	kvm_init_pmu_capability();
+
 	r = ops->hardware_setup();
 	if (r != 0)
 		return r;
@@ -11716,13 +11794,13 @@ int kvm_arch_hardware_setup(void *opaque)
 	kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
 
 	if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
-		supported_xss = 0;
+		kvm_caps.supported_xss = 0;
 
 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
 	cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
 #undef __kvm_cpu_cap_has
 
-	if (kvm_has_tsc_control) {
+	if (kvm_caps.has_tsc_control) {
 		/*
 		 * Make sure the user can only configure tsc_khz values that
 		 * fit into a signed integer.
@@ -11730,10 +11808,10 @@ int kvm_arch_hardware_setup(void *opaque)
 		 * be 1 on all machines.
 		 */
 		u64 max = min(0x7fffffffULL,
-			      __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
-		kvm_max_guest_tsc_khz = max;
+			      __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
+		kvm_caps.max_guest_tsc_khz = max;
 	}
-	kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
+	kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
 	kvm_init_msr_list();
 	return 0;
 }
@@ -12321,7 +12399,8 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 
 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
 {
-	if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
+	if (kvm_vcpu_apicv_active(vcpu) &&
+	    static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
 		return true;
 
 	return false;
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 588792f00334..501b884b8cc4 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -8,6 +8,27 @@
 #include "kvm_cache_regs.h"
 #include "kvm_emulate.h"
 
+struct kvm_caps {
+	/* control of guest tsc rate supported? */
+	bool has_tsc_control;
+	/* maximum supported tsc_khz for guests */
+	u32  max_guest_tsc_khz;
+	/* number of bits of the fractional part of the TSC scaling ratio */
+	u8   tsc_scaling_ratio_frac_bits;
+	/* maximum allowed value of TSC scaling ratio */
+	u64  max_tsc_scaling_ratio;
+	/* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */
+	u64  default_tsc_scaling_ratio;
+	/* bus lock detection supported? */
+	bool has_bus_lock_exit;
+	/* notify VM exit supported? */
+	bool has_notify_vmexit;
+
+	u64 supported_mce_cap;
+	u64 supported_xcr0;
+	u64 supported_xss;
+};
+
 void kvm_spurious_fault(void);
 
 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check)		\
@@ -283,14 +304,15 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
 
 extern u64 host_xcr0;
-extern u64 supported_xcr0;
 extern u64 host_xss;
-extern u64 supported_xss;
+
+extern struct kvm_caps kvm_caps;
+
 extern bool enable_pmu;
 
 static inline bool kvm_mpx_supported(void)
 {
-	return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
+	return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
 		== (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 }
 
@@ -344,6 +366,11 @@ static inline bool kvm_cstate_in_guest(struct kvm *kvm)
 	return kvm->arch.cstate_in_guest;
 }
 
+static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
+{
+	return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
+}
+
 enum kvm_intr_type {
 	/* Values are arbitrary, but must be non-zero. */
 	KVM_HANDLING_IRQ = 1,
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index fad8faa29d04..fa71a5d12e87 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -1408,6 +1408,10 @@ void do_user_addr_fault(struct pt_regs *regs,
 		return;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	/*
 	 * If we need to retry the mmap_lock has already been released,
 	 * and if there is a fatal signal pending there is no guarantee
@@ -1526,7 +1530,7 @@ DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault)
 
 	/*
 	 * Entry handling for valid #PF from kernel mode is slightly
-	 * different: RCU is already watching and rcu_irq_enter() must not
+	 * different: RCU is already watching and ct_irq_enter() must not
 	 * be invoked because a kernel fault on a user space address might
 	 * sleep.
 	 *
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index a0d023cb4292..509408da0da1 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -19,44 +19,6 @@
 #include <asm/tlbflush.h>
 #include <asm/elf.h>
 
-#if 0	/* This is just for testing */
-struct page *
-follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
-{
-	unsigned long start = address;
-	int length = 1;
-	int nr;
-	struct page *page;
-	struct vm_area_struct *vma;
-
-	vma = find_vma(mm, addr);
-	if (!vma || !is_vm_hugetlb_page(vma))
-		return ERR_PTR(-EINVAL);
-
-	pte = huge_pte_offset(mm, address, vma_mmu_pagesize(vma));
-
-	/* hugetlb should be locked, and hence, prefaulted */
-	WARN_ON(!pte || pte_none(*pte));
-
-	page = &pte_page(*pte)[vpfn % (HPAGE_SIZE/PAGE_SIZE)];
-
-	WARN_ON(!PageHead(page));
-
-	return page;
-}
-
-int pmd_huge(pmd_t pmd)
-{
-	return 0;
-}
-
-int pud_huge(pud_t pud)
-{
-	return 0;
-}
-
-#else
-
 /*
  * pmd_huge() returns 1 if @pmd is hugetlb related entry, that is normal
  * hugetlb entry or non-present (migration or hwpoisoned) hugetlb entry.
@@ -72,7 +34,6 @@ int pud_huge(pud_t pud)
 {
 	return !!(pud_val(pud) & _PAGE_PSE);
 }
-#endif
 
 #ifdef CONFIG_HUGETLB_PAGE
 static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *file,
diff --git a/arch/x86/mm/pkeys.c b/arch/x86/mm/pkeys.c
index e44e938885b7..7418c367e328 100644
--- a/arch/x86/mm/pkeys.c
+++ b/arch/x86/mm/pkeys.c
@@ -110,7 +110,7 @@ int __arch_override_mprotect_pkey(struct vm_area_struct *vma, int prot, int pkey
 	return vma_pkey(vma);
 }
 
-#define PKRU_AD_KEY(pkey)	(PKRU_AD_BIT << ((pkey) * PKRU_BITS_PER_PKEY))
+#define PKRU_AD_MASK(pkey)	(PKRU_AD_BIT << ((pkey) * PKRU_BITS_PER_PKEY))
 
 /*
  * Make the default PKRU value (at execve() time) as restrictive
@@ -118,11 +118,14 @@ int __arch_override_mprotect_pkey(struct vm_area_struct *vma, int prot, int pkey
  * in the process's lifetime will not accidentally get access
  * to data which is pkey-protected later on.
  */
-u32 init_pkru_value = PKRU_AD_KEY( 1) | PKRU_AD_KEY( 2) | PKRU_AD_KEY( 3) |
-		      PKRU_AD_KEY( 4) | PKRU_AD_KEY( 5) | PKRU_AD_KEY( 6) |
-		      PKRU_AD_KEY( 7) | PKRU_AD_KEY( 8) | PKRU_AD_KEY( 9) |
-		      PKRU_AD_KEY(10) | PKRU_AD_KEY(11) | PKRU_AD_KEY(12) |
-		      PKRU_AD_KEY(13) | PKRU_AD_KEY(14) | PKRU_AD_KEY(15);
+u32 init_pkru_value = PKRU_AD_MASK( 1) | PKRU_AD_MASK( 2) |
+		      PKRU_AD_MASK( 3) | PKRU_AD_MASK( 4) |
+		      PKRU_AD_MASK( 5) | PKRU_AD_MASK( 6) |
+		      PKRU_AD_MASK( 7) | PKRU_AD_MASK( 8) |
+		      PKRU_AD_MASK( 9) | PKRU_AD_MASK(10) |
+		      PKRU_AD_MASK(11) | PKRU_AD_MASK(12) |
+		      PKRU_AD_MASK(13) | PKRU_AD_MASK(14) |
+		      PKRU_AD_MASK(15);
 
 static ssize_t init_pkru_read_file(struct file *file, char __user *user_buf,
 			     size_t count, loff_t *ppos)
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index d400b6d9d246..d9314cc8b81f 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -734,10 +734,10 @@ static void flush_tlb_func(void *info)
 	const struct flush_tlb_info *f = info;
 	struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
 	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
-	u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
 	u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
 	bool local = smp_processor_id() == f->initiating_cpu;
 	unsigned long nr_invalidate = 0;
+	u64 mm_tlb_gen;
 
 	/* This code cannot presently handle being reentered. */
 	VM_WARN_ON(!irqs_disabled());
@@ -771,6 +771,22 @@ static void flush_tlb_func(void *info)
 		return;
 	}
 
+	if (f->new_tlb_gen <= local_tlb_gen) {
+		/*
+		 * The TLB is already up to date in respect to f->new_tlb_gen.
+		 * While the core might be still behind mm_tlb_gen, checking
+		 * mm_tlb_gen unnecessarily would have negative caching effects
+		 * so avoid it.
+		 */
+		return;
+	}
+
+	/*
+	 * Defer mm_tlb_gen reading as long as possible to avoid cache
+	 * contention.
+	 */
+	mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
+
 	if (unlikely(local_tlb_gen == mm_tlb_gen)) {
 		/*
 		 * There's nothing to do: we're already up to date.  This can
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index f298b18a9a3d..95b36ab2883f 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -1420,8 +1420,9 @@ st:			if (is_imm8(insn->off))
 		case BPF_JMP | BPF_CALL:
 			func = (u8 *) __bpf_call_base + imm32;
 			if (tail_call_reachable) {
+				/* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
 				EMIT3_off32(0x48, 0x8B, 0x85,
-					    -(bpf_prog->aux->stack_depth + 8));
+					    -round_up(bpf_prog->aux->stack_depth, 8) - 8);
 				if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
 					return -EINVAL;
 			} else {
@@ -2491,3 +2492,9 @@ void *bpf_arch_text_copy(void *dst, void *src, size_t len)
 		return ERR_PTR(-EINVAL);
 	return dst;
 }
+
+/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
+bool bpf_jit_supports_subprog_tailcalls(void)
+{
+	return true;
+}
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 1591d67e0bcd..6e598bd78eef 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -108,29 +108,6 @@ static int __init setup_add_efi_memmap(char *arg)
 }
 early_param("add_efi_memmap", setup_add_efi_memmap);
 
-void __init efi_find_mirror(void)
-{
-	efi_memory_desc_t *md;
-	u64 mirror_size = 0, total_size = 0;
-
-	if (!efi_enabled(EFI_MEMMAP))
-		return;
-
-	for_each_efi_memory_desc(md) {
-		unsigned long long start = md->phys_addr;
-		unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
-
-		total_size += size;
-		if (md->attribute & EFI_MEMORY_MORE_RELIABLE) {
-			memblock_mark_mirror(start, size);
-			mirror_size += size;
-		}
-	}
-	if (mirror_size)
-		pr_info("Memory: %lldM/%lldM mirrored memory\n",
-			mirror_size>>20, total_size>>20);
-}
-
 /*
  * Tell the kernel about the EFI memory map.  This might include
  * more than the max 128 entries that can fit in the passed in e820
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index e3eae648ba2e..ab30bcb46290 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -2173,7 +2173,7 @@ ENDPROC(ret_from_kernel_thread)
 
 #ifdef CONFIG_HIBERNATION
 
-	.bss
+	.section	.bss, "aw"
 	.align	4
 .Lsaved_regs:
 #if defined(__XTENSA_WINDOWED_ABI__)
diff --git a/arch/xtensa/kernel/syscall.c b/arch/xtensa/kernel/syscall.c
index 201356faa7e6..b3c2450d6f23 100644
--- a/arch/xtensa/kernel/syscall.c
+++ b/arch/xtensa/kernel/syscall.c
@@ -58,6 +58,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
 		unsigned long len, unsigned long pgoff, unsigned long flags)
 {
 	struct vm_area_struct *vmm;
+	struct vma_iterator vmi;
 
 	if (flags & MAP_FIXED) {
 		/* We do not accept a shared mapping if it would violate
@@ -79,15 +80,20 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
 	else
 		addr = PAGE_ALIGN(addr);
 
-	for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
-		/* At this point:  (!vmm || addr < vmm->vm_end). */
-		if (TASK_SIZE - len < addr)
-			return -ENOMEM;
-		if (!vmm || addr + len <= vm_start_gap(vmm))
-			return addr;
+	vma_iter_init(&vmi, current->mm, addr);
+	for_each_vma(vmi, vmm) {
+		/* At this point:  (addr < vmm->vm_end). */
+		if (addr + len <= vm_start_gap(vmm))
+			break;
+
 		addr = vmm->vm_end;
 		if (flags & MAP_SHARED)
 			addr = COLOUR_ALIGN(addr, pgoff);
 	}
+
+	if (TASK_SIZE - len < addr)
+		return -ENOMEM;
+
+	return addr;
 }
 #endif
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index e8ceb1528608..16b8a6273772 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -154,6 +154,7 @@ static void __init calibrate_ccount(void)
 	cpu = of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu");
 	if (cpu) {
 		clk = of_clk_get(cpu, 0);
+		of_node_put(cpu);
 		if (!IS_ERR(clk)) {
 			ccount_freq = clk_get_rate(clk);
 			return;
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index 16f0a5ff5799..8c781b05c0bd 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -172,6 +172,10 @@ void do_page_fault(struct pt_regs *regs)
 		return;
 	}
 
+	/* The fault is fully completed (including releasing mmap lock) */
+	if (fault & VM_FAULT_COMPLETED)
+		return;
+
 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index 538e6748e85a..c79c1d09ea86 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -133,6 +133,7 @@ static int __init machine_setup(void)
 
 	if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
 		update_local_mac(eth);
+	of_node_put(eth);
 	return 0;
 }
 arch_initcall(machine_setup);
diff --git a/block/bfq-cgroup.c b/block/bfq-cgroup.c
index 09574af83566..9fc605791b1e 100644
--- a/block/bfq-cgroup.c
+++ b/block/bfq-cgroup.c
@@ -706,10 +706,10 @@ void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
 }
 
 /**
- * __bfq_bic_change_cgroup - move @bic to @cgroup.
+ * __bfq_bic_change_cgroup - move @bic to @bfqg.
  * @bfqd: the queue descriptor.
  * @bic: the bic to move.
- * @blkcg: the blk-cgroup to move to.
+ * @bfqg: the group to move to.
  *
  * Move bic to blkcg, assuming that bfqd->lock is held; which makes
  * sure that the reference to cgroup is valid across the call (see
@@ -863,6 +863,7 @@ static void bfq_flush_idle_tree(struct bfq_service_tree *st)
  * @bfqd: the device data structure with the root group.
  * @entity: the entity to move, if entity is a leaf; or the parent entity
  *	    of an active leaf entity to move, if entity is not a leaf.
+ * @ioprio_class: I/O priority class to reparent.
  */
 static void bfq_reparent_leaf_entity(struct bfq_data *bfqd,
 				     struct bfq_entity *entity,
@@ -892,6 +893,7 @@ static void bfq_reparent_leaf_entity(struct bfq_data *bfqd,
  * @bfqd: the device data structure with the root group.
  * @bfqg: the group to move from.
  * @st: the service tree to start the search from.
+ * @ioprio_class: I/O priority class to reparent.
  */
 static void bfq_reparent_active_queues(struct bfq_data *bfqd,
 				       struct bfq_group *bfqg,
@@ -1471,8 +1473,6 @@ struct bfq_group *bfqq_group(struct bfq_queue *bfqq)
 	return bfqq->bfqd->root_group;
 }
 
-void bfqg_and_blkg_get(struct bfq_group *bfqg) {}
-
 void bfqg_and_blkg_put(struct bfq_group *bfqg) {}
 
 struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node)
diff --git a/block/bfq-wf2q.c b/block/bfq-wf2q.c
index f8eb340381cf..983413cdefad 100644
--- a/block/bfq-wf2q.c
+++ b/block/bfq-wf2q.c
@@ -1360,6 +1360,8 @@ static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st,
 /**
  * __bfq_lookup_next_entity - return the first eligible entity in @st.
  * @st: the service tree.
+ * @in_service: whether or not there is an in-service entity for the sched_data
+ *	this active tree belongs to.
  *
  * If there is no in-service entity for the sched_data st belongs to,
  * then return the entity that will be set in service if:
@@ -1472,9 +1474,6 @@ static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
 			break;
 	}
 
-	if (!entity)
-		return NULL;
-
 	return entity;
 }
 
diff --git a/block/bio.c b/block/bio.c
index 51c99f2c5c90..933ea3210954 100644
--- a/block/bio.c
+++ b/block/bio.c
@@ -1159,6 +1159,37 @@ static void bio_put_pages(struct page **pages, size_t size, size_t off)
 		put_page(pages[i]);
 }
 
+static int bio_iov_add_page(struct bio *bio, struct page *page,
+		unsigned int len, unsigned int offset)
+{
+	bool same_page = false;
+
+	if (!__bio_try_merge_page(bio, page, len, offset, &same_page)) {
+		if (WARN_ON_ONCE(bio_full(bio, len)))
+			return -EINVAL;
+		__bio_add_page(bio, page, len, offset);
+		return 0;
+	}
+
+	if (same_page)
+		put_page(page);
+	return 0;
+}
+
+static int bio_iov_add_zone_append_page(struct bio *bio, struct page *page,
+		unsigned int len, unsigned int offset)
+{
+	struct request_queue *q = bdev_get_queue(bio->bi_bdev);
+	bool same_page = false;
+
+	if (bio_add_hw_page(q, bio, page, len, offset,
+			queue_max_zone_append_sectors(q), &same_page) != len)
+		return -EINVAL;
+	if (same_page)
+		put_page(page);
+	return 0;
+}
+
 #define PAGE_PTRS_PER_BVEC     (sizeof(struct bio_vec) / sizeof(struct page *))
 
 /**
@@ -1177,7 +1208,6 @@ static int __bio_iov_iter_get_pages(struct bio *bio, struct iov_iter *iter)
 	unsigned short entries_left = bio->bi_max_vecs - bio->bi_vcnt;
 	struct bio_vec *bv = bio->bi_io_vec + bio->bi_vcnt;
 	struct page **pages = (struct page **)bv;
-	bool same_page = false;
 	ssize_t size, left;
 	unsigned len, i;
 	size_t offset;
@@ -1186,82 +1216,43 @@ static int __bio_iov_iter_get_pages(struct bio *bio, struct iov_iter *iter)
 	 * Move page array up in the allocated memory for the bio vecs as far as
 	 * possible so that we can start filling biovecs from the beginning
 	 * without overwriting the temporary page array.
-	*/
+	 */
 	BUILD_BUG_ON(PAGE_PTRS_PER_BVEC < 2);
 	pages += entries_left * (PAGE_PTRS_PER_BVEC - 1);
 
-	size = iov_iter_get_pages(iter, pages, LONG_MAX, nr_pages, &offset);
-	if (unlikely(size <= 0))
-		return size ? size : -EFAULT;
-
-	for (left = size, i = 0; left > 0; left -= len, i++) {
-		struct page *page = pages[i];
-
-		len = min_t(size_t, PAGE_SIZE - offset, left);
-
-		if (__bio_try_merge_page(bio, page, len, offset, &same_page)) {
-			if (same_page)
-				put_page(page);
-		} else {
-			if (WARN_ON_ONCE(bio_full(bio, len))) {
-				bio_put_pages(pages + i, left, offset);
-				return -EINVAL;
-			}
-			__bio_add_page(bio, page, len, offset);
-		}
-		offset = 0;
-	}
-
-	iov_iter_advance(iter, size);
-	return 0;
-}
-
-static int __bio_iov_append_get_pages(struct bio *bio, struct iov_iter *iter)
-{
-	unsigned short nr_pages = bio->bi_max_vecs - bio->bi_vcnt;
-	unsigned short entries_left = bio->bi_max_vecs - bio->bi_vcnt;
-	struct request_queue *q = bdev_get_queue(bio->bi_bdev);
-	unsigned int max_append_sectors = queue_max_zone_append_sectors(q);
-	struct bio_vec *bv = bio->bi_io_vec + bio->bi_vcnt;
-	struct page **pages = (struct page **)bv;
-	ssize_t size, left;
-	unsigned len, i;
-	size_t offset;
-	int ret = 0;
-
-	if (WARN_ON_ONCE(!max_append_sectors))
-		return 0;
-
 	/*
-	 * Move page array up in the allocated memory for the bio vecs as far as
-	 * possible so that we can start filling biovecs from the beginning
-	 * without overwriting the temporary page array.
+	 * Each segment in the iov is required to be a block size multiple.
+	 * However, we may not be able to get the entire segment if it spans
+	 * more pages than bi_max_vecs allows, so we have to ALIGN_DOWN the
+	 * result to ensure the bio's total size is correct. The remainder of
+	 * the iov data will be picked up in the next bio iteration.
 	 */
-	BUILD_BUG_ON(PAGE_PTRS_PER_BVEC < 2);
-	pages += entries_left * (PAGE_PTRS_PER_BVEC - 1);
-
 	size = iov_iter_get_pages(iter, pages, LONG_MAX, nr_pages, &offset);
+	if (size > 0)
+		size = ALIGN_DOWN(size, bdev_logical_block_size(bio->bi_bdev));
 	if (unlikely(size <= 0))
 		return size ? size : -EFAULT;
 
 	for (left = size, i = 0; left > 0; left -= len, i++) {
 		struct page *page = pages[i];
-		bool same_page = false;
+		int ret;
 
 		len = min_t(size_t, PAGE_SIZE - offset, left);
-		if (bio_add_hw_page(q, bio, page, len, offset,
-				max_append_sectors, &same_page) != len) {
+		if (bio_op(bio) == REQ_OP_ZONE_APPEND)
+			ret = bio_iov_add_zone_append_page(bio, page, len,
+					offset);
+		else
+			ret = bio_iov_add_page(bio, page, len, offset);
+
+		if (ret) {
 			bio_put_pages(pages + i, left, offset);
-			ret = -EINVAL;
-			break;
+			return ret;
 		}
-		if (same_page)
-			put_page(page);
 		offset = 0;
 	}
 
-	iov_iter_advance(iter, size - left);
-	return ret;
+	iov_iter_advance(iter, size);
+	return 0;
 }
 
 /**
@@ -1298,10 +1289,7 @@ int bio_iov_iter_get_pages(struct bio *bio, struct iov_iter *iter)
 	}
 
 	do {
-		if (bio_op(bio) == REQ_OP_ZONE_APPEND)
-			ret = __bio_iov_append_get_pages(bio, iter);
-		else
-			ret = __bio_iov_iter_get_pages(bio, iter);
+		ret = __bio_iov_iter_get_pages(bio, iter);
 	} while (!ret && iov_iter_count(iter) && !bio_full(bio, 0));
 
 	/* don't account direct I/O as memory stall */
diff --git a/block/blk-core.c b/block/blk-core.c
index 06ff5bbfe8f6..eb86c756a7fd 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -448,7 +448,7 @@ struct request_queue *blk_alloc_queue(int node_id, bool alloc_srcu)
 
 	q->last_merge = NULL;
 
-	q->id = ida_simple_get(&blk_queue_ida, 0, 0, GFP_KERNEL);
+	q->id = ida_alloc(&blk_queue_ida, GFP_KERNEL);
 	if (q->id < 0)
 		goto fail_srcu;
 
@@ -498,7 +498,7 @@ struct request_queue *blk_alloc_queue(int node_id, bool alloc_srcu)
 fail_split:
 	bioset_exit(&q->bio_split);
 fail_id:
-	ida_simple_remove(&blk_queue_ida, q->id);
+	ida_free(&blk_queue_ida, q->id);
 fail_srcu:
 	if (alloc_srcu)
 		cleanup_srcu_struct(q->srcu);
diff --git a/block/blk-iocost.c b/block/blk-iocost.c
index 33a11ba971ea..b7082f2aed9c 100644
--- a/block/blk-iocost.c
+++ b/block/blk-iocost.c
@@ -2769,7 +2769,7 @@ static void ioc_rqos_done(struct rq_qos *rqos, struct request *rq)
 	if (!ioc->enabled || !rq->alloc_time_ns || !rq->start_time_ns)
 		return;
 
-	switch (req_op(rq) & REQ_OP_MASK) {
+	switch (req_op(rq)) {
 	case REQ_OP_READ:
 		pidx = QOS_RLAT;
 		rw = READ;
diff --git a/block/blk-merge.c b/block/blk-merge.c
index 7771dacc99cb..0f5f42ebd0bb 100644
--- a/block/blk-merge.c
+++ b/block/blk-merge.c
@@ -164,18 +164,21 @@ static struct bio *blk_bio_write_zeroes_split(struct request_queue *q,
 static inline unsigned get_max_io_size(struct request_queue *q,
 				       struct bio *bio)
 {
-	unsigned sectors = blk_max_size_offset(q, bio->bi_iter.bi_sector, 0);
-	unsigned max_sectors = sectors;
 	unsigned pbs = queue_physical_block_size(q) >> SECTOR_SHIFT;
 	unsigned lbs = queue_logical_block_size(q) >> SECTOR_SHIFT;
-	unsigned start_offset = bio->bi_iter.bi_sector & (pbs - 1);
+	unsigned max_sectors = queue_max_sectors(q), start, end;
 
-	max_sectors += start_offset;
-	max_sectors &= ~(pbs - 1);
-	if (max_sectors > start_offset)
-		return max_sectors - start_offset;
+	if (q->limits.chunk_sectors) {
+		max_sectors = min(max_sectors,
+			blk_chunk_sectors_left(bio->bi_iter.bi_sector,
+					       q->limits.chunk_sectors));
+	}
 
-	return sectors & ~(lbs - 1);
+	start = bio->bi_iter.bi_sector & (pbs - 1);
+	end = (start + max_sectors) & ~(pbs - 1);
+	if (end > start)
+		return end - start;
+	return max_sectors & ~(lbs - 1);
 }
 
 static inline unsigned get_max_segment_size(const struct request_queue *q,
@@ -201,11 +204,11 @@ static inline unsigned get_max_segment_size(const struct request_queue *q,
  * @nsegs:    [in,out] Number of segments in the bio being built. Incremented
  *            by the number of segments from @bv that may be appended to that
  *            bio without exceeding @max_segs
- * @sectors:  [in,out] Number of sectors in the bio being built. Incremented
- *            by the number of sectors from @bv that may be appended to that
- *            bio without exceeding @max_sectors
+ * @bytes:    [in,out] Number of bytes in the bio being built. Incremented
+ *            by the number of bytes from @bv that may be appended to that
+ *            bio without exceeding @max_bytes
  * @max_segs: [in] upper bound for *@nsegs
- * @max_sectors: [in] upper bound for *@sectors
+ * @max_bytes: [in] upper bound for *@bytes
  *
  * When splitting a bio, it can happen that a bvec is encountered that is too
  * big to fit in a single segment and hence that it has to be split in the
@@ -216,10 +219,10 @@ static inline unsigned get_max_segment_size(const struct request_queue *q,
  */
 static bool bvec_split_segs(const struct request_queue *q,
 			    const struct bio_vec *bv, unsigned *nsegs,
-			    unsigned *sectors, unsigned max_segs,
-			    unsigned max_sectors)
+			    unsigned *bytes, unsigned max_segs,
+			    unsigned max_bytes)
 {
-	unsigned max_len = (min(max_sectors, UINT_MAX >> 9) - *sectors) << 9;
+	unsigned max_len = min(max_bytes, UINT_MAX) - *bytes;
 	unsigned len = min(bv->bv_len, max_len);
 	unsigned total_len = 0;
 	unsigned seg_size = 0;
@@ -237,7 +240,7 @@ static bool bvec_split_segs(const struct request_queue *q,
 			break;
 	}
 
-	*sectors += total_len >> 9;
+	*bytes += total_len;
 
 	/* tell the caller to split the bvec if it is too big to fit */
 	return len > 0 || bv->bv_len > max_len;
@@ -269,8 +272,8 @@ static struct bio *blk_bio_segment_split(struct request_queue *q,
 {
 	struct bio_vec bv, bvprv, *bvprvp = NULL;
 	struct bvec_iter iter;
-	unsigned nsegs = 0, sectors = 0;
-	const unsigned max_sectors = get_max_io_size(q, bio);
+	unsigned nsegs = 0, bytes = 0;
+	const unsigned max_bytes = get_max_io_size(q, bio) << 9;
 	const unsigned max_segs = queue_max_segments(q);
 
 	bio_for_each_bvec(bv, bio, iter) {
@@ -282,12 +285,12 @@ static struct bio *blk_bio_segment_split(struct request_queue *q,
 			goto split;
 
 		if (nsegs < max_segs &&
-		    sectors + (bv.bv_len >> 9) <= max_sectors &&
+		    bytes + bv.bv_len <= max_bytes &&
 		    bv.bv_offset + bv.bv_len <= PAGE_SIZE) {
 			nsegs++;
-			sectors += bv.bv_len >> 9;
-		} else if (bvec_split_segs(q, &bv, &nsegs, &sectors, max_segs,
-					 max_sectors)) {
+			bytes += bv.bv_len;
+		} else if (bvec_split_segs(q, &bv, &nsegs, &bytes, max_segs,
+					   max_bytes)) {
 			goto split;
 		}
 
@@ -300,13 +303,20 @@ static struct bio *blk_bio_segment_split(struct request_queue *q,
 split:
 	*segs = nsegs;
 
+	/*
+	 * Individual bvecs might not be logical block aligned. Round down the
+	 * split size so that each bio is properly block size aligned, even if
+	 * we do not use the full hardware limits.
+	 */
+	bytes = ALIGN_DOWN(bytes, queue_logical_block_size(q));
+
 	/*
 	 * Bio splitting may cause subtle trouble such as hang when doing sync
 	 * iopoll in direct IO routine. Given performance gain of iopoll for
 	 * big IO can be trival, disable iopoll when split needed.
 	 */
 	bio_clear_polled(bio);
-	return bio_split(bio, sectors, GFP_NOIO, bs);
+	return bio_split(bio, bytes >> SECTOR_SHIFT, GFP_NOIO, bs);
 }
 
 /**
@@ -375,7 +385,7 @@ EXPORT_SYMBOL(blk_queue_split);
 unsigned int blk_recalc_rq_segments(struct request *rq)
 {
 	unsigned int nr_phys_segs = 0;
-	unsigned int nr_sectors = 0;
+	unsigned int bytes = 0;
 	struct req_iterator iter;
 	struct bio_vec bv;
 
@@ -398,7 +408,7 @@ unsigned int blk_recalc_rq_segments(struct request *rq)
 	}
 
 	rq_for_each_bvec(bv, rq, iter)
-		bvec_split_segs(rq->q, &bv, &nr_phys_segs, &nr_sectors,
+		bvec_split_segs(rq->q, &bv, &nr_phys_segs, &bytes,
 				UINT_MAX, UINT_MAX);
 	return nr_phys_segs;
 }
@@ -559,17 +569,18 @@ static inline unsigned int blk_rq_get_max_sectors(struct request *rq,
 						  sector_t offset)
 {
 	struct request_queue *q = rq->q;
+	unsigned int max_sectors;
 
 	if (blk_rq_is_passthrough(rq))
 		return q->limits.max_hw_sectors;
 
+	max_sectors = blk_queue_get_max_sectors(q, req_op(rq));
 	if (!q->limits.chunk_sectors ||
 	    req_op(rq) == REQ_OP_DISCARD ||
 	    req_op(rq) == REQ_OP_SECURE_ERASE)
-		return blk_queue_get_max_sectors(q, req_op(rq));
-
-	return min(blk_max_size_offset(q, offset, 0),
-			blk_queue_get_max_sectors(q, req_op(rq)));
+		return max_sectors;
+	return min(max_sectors,
+		   blk_chunk_sectors_left(offset, q->limits.chunk_sectors));
 }
 
 static inline int ll_new_hw_segment(struct request *req, struct bio *bio,
diff --git a/block/blk-mq.c b/block/blk-mq.c
index 33145ba52c96..d52c36b03857 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -2085,14 +2085,10 @@ static void __blk_mq_delay_run_hw_queue(struct blk_mq_hw_ctx *hctx, bool async,
 		return;
 
 	if (!async && !(hctx->flags & BLK_MQ_F_BLOCKING)) {
-		int cpu = get_cpu();
-		if (cpumask_test_cpu(cpu, hctx->cpumask)) {
+		if (cpumask_test_cpu(raw_smp_processor_id(), hctx->cpumask)) {
 			__blk_mq_run_hw_queue(hctx);
-			put_cpu();
 			return;
 		}
-
-		put_cpu();
 	}
 
 	kblockd_mod_delayed_work_on(blk_mq_hctx_next_cpu(hctx), &hctx->run_work,
@@ -2156,7 +2152,7 @@ static struct blk_mq_hw_ctx *blk_mq_get_sq_hctx(struct request_queue *q)
 	 * just causes lock contention inside the scheduler and pointless cache
 	 * bouncing.
 	 */
-	struct blk_mq_hw_ctx *hctx = blk_mq_map_queue(q, 0, ctx);
+	struct blk_mq_hw_ctx *hctx = ctx->hctxs[HCTX_TYPE_DEFAULT];
 
 	if (!blk_mq_hctx_stopped(hctx))
 		return hctx;
diff --git a/block/blk-mq.h b/block/blk-mq.h
index 2615bd58bad3..e4c6fe2c8ac8 100644
--- a/block/blk-mq.h
+++ b/block/blk-mq.h
@@ -86,16 +86,16 @@ static inline struct blk_mq_hw_ctx *blk_mq_map_queue_type(struct request_queue *
 	return xa_load(&q->hctx_table, q->tag_set->map[type].mq_map[cpu]);
 }
 
-static inline enum hctx_type blk_mq_get_hctx_type(unsigned int flags)
+static inline enum hctx_type blk_mq_get_hctx_type(unsigned int opf)
 {
 	enum hctx_type type = HCTX_TYPE_DEFAULT;
 
 	/*
 	 * The caller ensure that if REQ_POLLED, poll must be enabled.
 	 */
-	if (flags & REQ_POLLED)
+	if (opf & REQ_POLLED)
 		type = HCTX_TYPE_POLL;
-	else if ((flags & REQ_OP_MASK) == REQ_OP_READ)
+	else if ((opf & REQ_OP_MASK) == REQ_OP_READ)
 		type = HCTX_TYPE_READ;
 	return type;
 }
@@ -103,14 +103,14 @@ static inline enum hctx_type blk_mq_get_hctx_type(unsigned int flags)
 /*
  * blk_mq_map_queue() - map (cmd_flags,type) to hardware queue
  * @q: request queue
- * @flags: request command flags
+ * @opf: operation type (REQ_OP_*) and flags (e.g. REQ_POLLED).
  * @ctx: software queue cpu ctx
  */
 static inline struct blk_mq_hw_ctx *blk_mq_map_queue(struct request_queue *q,
-						     unsigned int flags,
+						     unsigned int opf,
 						     struct blk_mq_ctx *ctx)
 {
-	return ctx->hctxs[blk_mq_get_hctx_type(flags)];
+	return ctx->hctxs[blk_mq_get_hctx_type(opf)];
 }
 
 /*
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index 88bd41d4cb59..2ed9e7d52b47 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -274,6 +274,11 @@ static ssize_t queue_virt_boundary_mask_show(struct request_queue *q, char *page
 	return queue_var_show(q->limits.virt_boundary_mask, page);
 }
 
+static ssize_t queue_dma_alignment_show(struct request_queue *q, char *page)
+{
+	return queue_var_show(queue_dma_alignment(q), page);
+}
+
 #define QUEUE_SYSFS_BIT_FNS(name, flag, neg)				\
 static ssize_t								\
 queue_##name##_show(struct request_queue *q, char *page)		\
@@ -606,6 +611,7 @@ QUEUE_RO_ENTRY(queue_dax, "dax");
 QUEUE_RW_ENTRY(queue_io_timeout, "io_timeout");
 QUEUE_RW_ENTRY(queue_wb_lat, "wbt_lat_usec");
 QUEUE_RO_ENTRY(queue_virt_boundary_mask, "virt_boundary_mask");
+QUEUE_RO_ENTRY(queue_dma_alignment, "dma_alignment");
 
 #ifdef CONFIG_BLK_DEV_THROTTLING_LOW
 QUEUE_RW_ENTRY(blk_throtl_sample_time, "throttle_sample_time");
@@ -667,6 +673,7 @@ static struct attribute *queue_attrs[] = {
 	&blk_throtl_sample_time_entry.attr,
 #endif
 	&queue_virt_boundary_mask_entry.attr,
+	&queue_dma_alignment_entry.attr,
 	NULL,
 };
 
@@ -792,7 +799,7 @@ static void blk_release_queue(struct kobject *kobj)
 	if (blk_queue_has_srcu(q))
 		cleanup_srcu_struct(q->srcu);
 
-	ida_simple_remove(&blk_queue_ida, q->id);
+	ida_free(&blk_queue_ida, q->id);
 	call_rcu(&q->rcu_head, blk_free_queue_rcu);
 }
 
diff --git a/block/blk.h b/block/blk.h
index 434017701403..8e79296ee97a 100644
--- a/block/blk.h
+++ b/block/blk.h
@@ -159,6 +159,19 @@ static inline bool blk_discard_mergable(struct request *req)
 	return false;
 }
 
+static inline unsigned int blk_queue_get_max_sectors(struct request_queue *q,
+						     int op)
+{
+	if (unlikely(op == REQ_OP_DISCARD || op == REQ_OP_SECURE_ERASE))
+		return min(q->limits.max_discard_sectors,
+			   UINT_MAX >> SECTOR_SHIFT);
+
+	if (unlikely(op == REQ_OP_WRITE_ZEROES))
+		return q->limits.max_write_zeroes_sectors;
+
+	return q->limits.max_sectors;
+}
+
 #ifdef CONFIG_BLK_DEV_INTEGRITY
 void blk_flush_integrity(void);
 bool __bio_integrity_endio(struct bio *);
diff --git a/block/bounce.c b/block/bounce.c
index 8f7b6fe3b4db..c8f487af7be3 100644
--- a/block/bounce.c
+++ b/block/bounce.c
@@ -205,19 +205,26 @@ void __blk_queue_bounce(struct request_queue *q, struct bio **bio_orig)
 	int rw = bio_data_dir(*bio_orig);
 	struct bio_vec *to, from;
 	struct bvec_iter iter;
-	unsigned i = 0;
+	unsigned i = 0, bytes = 0;
 	bool bounce = false;
-	int sectors = 0;
+	int sectors;
 
 	bio_for_each_segment(from, *bio_orig, iter) {
 		if (i++ < BIO_MAX_VECS)
-			sectors += from.bv_len >> 9;
+			bytes += from.bv_len;
 		if (PageHighMem(from.bv_page))
 			bounce = true;
 	}
 	if (!bounce)
 		return;
 
+	/*
+	 * Individual bvecs might not be logical block aligned. Round down
+	 * the split size so that each bio is properly block size aligned,
+	 * even if we do not use the full hardware limits.
+	 */
+	sectors = ALIGN_DOWN(bytes, queue_logical_block_size(q)) >>
+			SECTOR_SHIFT;
 	if (sectors < bio_sectors(*bio_orig)) {
 		bio = bio_split(*bio_orig, sectors, GFP_NOIO, &bounce_bio_split);
 		bio_chain(bio, *bio_orig);
diff --git a/block/bsg.c b/block/bsg.c
index 882f56bff14f..2ab1351eb082 100644
--- a/block/bsg.c
+++ b/block/bsg.c
@@ -169,7 +169,7 @@ static void bsg_device_release(struct device *dev)
 {
 	struct bsg_device *bd = container_of(dev, struct bsg_device, device);
 
-	ida_simple_remove(&bsg_minor_ida, MINOR(bd->device.devt));
+	ida_free(&bsg_minor_ida, MINOR(bd->device.devt));
 	kfree(bd);
 }
 
@@ -196,7 +196,7 @@ struct bsg_device *bsg_register_queue(struct request_queue *q,
 	bd->queue = q;
 	bd->sg_io_fn = sg_io_fn;
 
-	ret = ida_simple_get(&bsg_minor_ida, 0, BSG_MAX_DEVS, GFP_KERNEL);
+	ret = ida_alloc_max(&bsg_minor_ida, BSG_MAX_DEVS - 1, GFP_KERNEL);
 	if (ret < 0) {
 		if (ret == -ENOSPC)
 			dev_err(parent, "bsg: too many bsg devices\n");
diff --git a/block/fops.c b/block/fops.c
index d6b3276a6c68..e29d78e0e65c 100644
--- a/block/fops.c
+++ b/block/fops.c
@@ -42,6 +42,13 @@ static unsigned int dio_bio_write_op(struct kiocb *iocb)
 	return op;
 }
 
+static bool blkdev_dio_unaligned(struct block_device *bdev, loff_t pos,
+			      struct iov_iter *iter)
+{
+	return pos & (bdev_logical_block_size(bdev) - 1) ||
+		!bdev_iter_is_aligned(bdev, iter);
+}
+
 #define DIO_INLINE_BIO_VECS 4
 
 static ssize_t __blkdev_direct_IO_simple(struct kiocb *iocb,
@@ -54,8 +61,7 @@ static ssize_t __blkdev_direct_IO_simple(struct kiocb *iocb,
 	struct bio bio;
 	ssize_t ret;
 
-	if ((pos | iov_iter_alignment(iter)) &
-	    (bdev_logical_block_size(bdev) - 1))
+	if (blkdev_dio_unaligned(bdev, pos, iter))
 		return -EINVAL;
 
 	if (nr_pages <= DIO_INLINE_BIO_VECS)
@@ -173,8 +179,7 @@ static ssize_t __blkdev_direct_IO(struct kiocb *iocb, struct iov_iter *iter,
 	loff_t pos = iocb->ki_pos;
 	int ret = 0;
 
-	if ((pos | iov_iter_alignment(iter)) &
-	    (bdev_logical_block_size(bdev) - 1))
+	if (blkdev_dio_unaligned(bdev, pos, iter))
 		return -EINVAL;
 
 	if (iocb->ki_flags & IOCB_ALLOC_CACHE)
@@ -298,8 +303,7 @@ static ssize_t __blkdev_direct_IO_async(struct kiocb *iocb,
 	loff_t pos = iocb->ki_pos;
 	int ret = 0;
 
-	if ((pos | iov_iter_alignment(iter)) &
-	    (bdev_logical_block_size(bdev) - 1))
+	if (blkdev_dio_unaligned(bdev, pos, iter))
 		return -EINVAL;
 
 	if (iocb->ki_flags & IOCB_ALLOC_CACHE)
@@ -417,7 +421,7 @@ const struct address_space_operations def_blk_aops = {
 	.write_end	= blkdev_write_end,
 	.writepages	= blkdev_writepages,
 	.direct_IO	= blkdev_direct_IO,
-	.migratepage	= buffer_migrate_page_norefs,
+	.migrate_folio	= buffer_migrate_folio_norefs,
 	.is_dirty_writeback = buffer_check_dirty_writeback,
 };
 
diff --git a/block/partitions/check.h b/block/partitions/check.h
index 4ffa2359b1a3..8d70a880c372 100644
--- a/block/partitions/check.h
+++ b/block/partitions/check.h
@@ -24,13 +24,13 @@ struct parsed_partitions {
 };
 
 typedef struct {
-	struct page *v;
+	struct folio *v;
 } Sector;
 
 void *read_part_sector(struct parsed_partitions *state, sector_t n, Sector *p);
 static inline void put_dev_sector(Sector p)
 {
-	put_page(p.v);
+	folio_put(p.v);
 }
 
 static inline void
diff --git a/block/partitions/core.c b/block/partitions/core.c
index 8a0ec929023b..e103ad08a948 100644
--- a/block/partitions/core.c
+++ b/block/partitions/core.c
@@ -705,25 +705,19 @@ EXPORT_SYMBOL_GPL(bdev_disk_changed);
 void *read_part_sector(struct parsed_partitions *state, sector_t n, Sector *p)
 {
 	struct address_space *mapping = state->disk->part0->bd_inode->i_mapping;
-	struct page *page;
+	struct folio *folio;
 
 	if (n >= get_capacity(state->disk)) {
 		state->access_beyond_eod = true;
-		return NULL;
+		goto out;
 	}
 
-	page = read_mapping_page(mapping,
-			(pgoff_t)(n >> (PAGE_SHIFT - 9)), NULL);
-	if (IS_ERR(page))
+	folio = read_mapping_folio(mapping, n >> PAGE_SECTORS_SHIFT, NULL);
+	if (IS_ERR(folio))
 		goto out;
-	if (PageError(page))
-		goto out_put_page;
-
-	p->v = page;
-	return (unsigned char *)page_address(page) +
-			((n & ((1 << (PAGE_SHIFT - 9)) - 1)) << SECTOR_SHIFT);
-out_put_page:
-	put_page(page);
+
+	p->v = folio;
+	return folio_address(folio) + offset_in_folio(folio, n * SECTOR_SIZE);
 out:
 	p->v = NULL;
 	return NULL;
diff --git a/certs/Makefile b/certs/Makefile
index a8d628fd5f7b..88a73b28d254 100644
--- a/certs/Makefile
+++ b/certs/Makefile
@@ -3,8 +3,8 @@
 # Makefile for the linux kernel signature checking certificates.
 #
 
-obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o common.o
-obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o common.o
+obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o
+obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o
 obj-$(CONFIG_SYSTEM_REVOCATION_LIST) += revocation_certificates.o
 ifneq ($(CONFIG_SYSTEM_BLACKLIST_HASH_LIST),)
 
diff --git a/certs/blacklist.c b/certs/blacklist.c
index 25094ea73600..41f10601cc72 100644
--- a/certs/blacklist.c
+++ b/certs/blacklist.c
@@ -15,10 +15,9 @@
 #include <linux/err.h>
 #include <linux/seq_file.h>
 #include <linux/uidgid.h>
-#include <linux/verification.h>
+#include <keys/asymmetric-type.h>
 #include <keys/system_keyring.h>
 #include "blacklist.h"
-#include "common.h"
 
 /*
  * According to crypto/asymmetric_keys/x509_cert_parser.c:x509_note_pkey_algo(),
@@ -365,8 +364,9 @@ static __init int load_revocation_certificate_list(void)
 	if (revocation_certificate_list_size)
 		pr_notice("Loading compiled-in revocation X.509 certificates\n");
 
-	return load_certificate_list(revocation_certificate_list, revocation_certificate_list_size,
-				     blacklist_keyring);
+	return x509_load_certificate_list(revocation_certificate_list,
+					  revocation_certificate_list_size,
+					  blacklist_keyring);
 }
 late_initcall(load_revocation_certificate_list);
 #endif
diff --git a/certs/common.c b/certs/common.c
deleted file mode 100644
index 16a220887a53..000000000000
--- a/certs/common.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include <linux/kernel.h>
-#include <linux/key.h>
-#include "common.h"
-
-int load_certificate_list(const u8 cert_list[],
-			  const unsigned long list_size,
-			  const struct key *keyring)
-{
-	key_ref_t key;
-	const u8 *p, *end;
-	size_t plen;
-
-	p = cert_list;
-	end = p + list_size;
-	while (p < end) {
-		/* Each cert begins with an ASN.1 SEQUENCE tag and must be more
-		 * than 256 bytes in size.
-		 */
-		if (end - p < 4)
-			goto dodgy_cert;
-		if (p[0] != 0x30 &&
-		    p[1] != 0x82)
-			goto dodgy_cert;
-		plen = (p[2] << 8) | p[3];
-		plen += 4;
-		if (plen > end - p)
-			goto dodgy_cert;
-
-		key = key_create_or_update(make_key_ref(keyring, 1),
-					   "asymmetric",
-					   NULL,
-					   p,
-					   plen,
-					   ((KEY_POS_ALL & ~KEY_POS_SETATTR) |
-					   KEY_USR_VIEW | KEY_USR_READ),
-					   KEY_ALLOC_NOT_IN_QUOTA |
-					   KEY_ALLOC_BUILT_IN |
-					   KEY_ALLOC_BYPASS_RESTRICTION);
-		if (IS_ERR(key)) {
-			pr_err("Problem loading in-kernel X.509 certificate (%ld)\n",
-			       PTR_ERR(key));
-		} else {
-			pr_notice("Loaded X.509 cert '%s'\n",
-				  key_ref_to_ptr(key)->description);
-			key_ref_put(key);
-		}
-		p += plen;
-	}
-
-	return 0;
-
-dodgy_cert:
-	pr_err("Problem parsing in-kernel X.509 certificate list\n");
-	return 0;
-}
diff --git a/certs/common.h b/certs/common.h
deleted file mode 100644
index abdb5795936b..000000000000
--- a/certs/common.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _CERT_COMMON_H
-#define _CERT_COMMON_H
-
-int load_certificate_list(const u8 cert_list[], const unsigned long list_size,
-			  const struct key *keyring);
-
-#endif
diff --git a/certs/system_keyring.c b/certs/system_keyring.c
index 05b66ce9d1c9..5042cc54fa5e 100644
--- a/certs/system_keyring.c
+++ b/certs/system_keyring.c
@@ -16,7 +16,6 @@
 #include <keys/asymmetric-type.h>
 #include <keys/system_keyring.h>
 #include <crypto/pkcs7.h>
-#include "common.h"
 
 static struct key *builtin_trusted_keys;
 #ifdef CONFIG_SECONDARY_TRUSTED_KEYRING
@@ -183,7 +182,8 @@ __init int load_module_cert(struct key *keyring)
 
 	pr_notice("Loading compiled-in module X.509 certificates\n");
 
-	return load_certificate_list(system_certificate_list, module_cert_size, keyring);
+	return x509_load_certificate_list(system_certificate_list,
+					  module_cert_size, keyring);
 }
 
 /*
@@ -204,7 +204,7 @@ static __init int load_system_certificate_list(void)
 	size = system_certificate_list_size - module_cert_size;
 #endif
 
-	return load_certificate_list(p, size, builtin_trusted_keys);
+	return x509_load_certificate_list(p, size, builtin_trusted_keys);
 }
 late_initcall(load_system_certificate_list);
 
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 1d44893a997b..59489a300cd1 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -461,6 +461,15 @@ config CRYPTO_PCBC
 	  PCBC: Propagating Cipher Block Chaining mode
 	  This block cipher algorithm is required for RxRPC.
 
+config CRYPTO_XCTR
+	tristate
+	select CRYPTO_SKCIPHER
+	select CRYPTO_MANAGER
+	help
+	  XCTR: XOR Counter mode. This blockcipher mode is a variant of CTR mode
+	  using XORs and little-endian addition rather than big-endian arithmetic.
+	  XCTR mode is used to implement HCTR2.
+
 config CRYPTO_XTS
 	tristate "XTS support"
 	select CRYPTO_SKCIPHER
@@ -524,6 +533,17 @@ config CRYPTO_ADIANTUM
 
 	  If unsure, say N.
 
+config CRYPTO_HCTR2
+	tristate "HCTR2 support"
+	select CRYPTO_XCTR
+	select CRYPTO_POLYVAL
+	select CRYPTO_MANAGER
+	help
+	  HCTR2 is a length-preserving encryption mode for storage encryption that
+	  is efficient on processors with instructions to accelerate AES and
+	  carryless multiplication, e.g. x86 processors with AES-NI and CLMUL, and
+	  ARM processors with the ARMv8 crypto extensions.
+
 config CRYPTO_ESSIV
 	tristate "ESSIV support for block encryption"
 	select CRYPTO_AUTHENC
@@ -692,26 +712,8 @@ config CRYPTO_BLAKE2B
 
 	  See https://blake2.net for further information.
 
-config CRYPTO_BLAKE2S
-	tristate "BLAKE2s digest algorithm"
-	select CRYPTO_LIB_BLAKE2S_GENERIC
-	select CRYPTO_HASH
-	help
-	  Implementation of cryptographic hash function BLAKE2s
-	  optimized for 8-32bit platforms and can produce digests of any size
-	  between 1 to 32.  The keyed hash is also implemented.
-
-	  This module provides the following algorithms:
-
-	  - blake2s-128
-	  - blake2s-160
-	  - blake2s-224
-	  - blake2s-256
-
-	  See https://blake2.net for further information.
-
 config CRYPTO_BLAKE2S_X86
-	tristate "BLAKE2s digest algorithm (x86 accelerated version)"
+	bool "BLAKE2s digest algorithm (x86 accelerated version)"
 	depends on X86 && 64BIT
 	select CRYPTO_LIB_BLAKE2S_GENERIC
 	select CRYPTO_ARCH_HAVE_LIB_BLAKE2S
@@ -765,6 +767,23 @@ config CRYPTO_GHASH
 	  GHASH is the hash function used in GCM (Galois/Counter Mode).
 	  It is not a general-purpose cryptographic hash function.
 
+config CRYPTO_POLYVAL
+	tristate
+	select CRYPTO_GF128MUL
+	select CRYPTO_HASH
+	help
+	  POLYVAL is the hash function used in HCTR2.  It is not a general-purpose
+	  cryptographic hash function.
+
+config CRYPTO_POLYVAL_CLMUL_NI
+	tristate "POLYVAL hash function (CLMUL-NI accelerated)"
+	depends on X86 && 64BIT
+	select CRYPTO_POLYVAL
+	help
+	  This is the x86_64 CLMUL-NI accelerated implementation of POLYVAL. It is
+	  used to efficiently implement HCTR2 on x86-64 processors that support
+	  carry-less multiplication instructions.
+
 config CRYPTO_POLY1305
 	tristate "Poly1305 authenticator algorithm"
 	select CRYPTO_HASH
@@ -1142,7 +1161,7 @@ config CRYPTO_AES_NI_INTEL
 	  In addition to AES cipher algorithm support, the acceleration
 	  for some popular block cipher mode is supported too, including
 	  ECB, CBC, LRW, XTS. The 64 bit version has additional
-	  acceleration for CTR.
+	  acceleration for CTR and XCTR.
 
 config CRYPTO_AES_SPARC64
 	tristate "AES cipher algorithms (SPARC64)"
diff --git a/crypto/Makefile b/crypto/Makefile
index ceaaa9f34145..a4a84860fe43 100644
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -84,7 +84,6 @@ obj-$(CONFIG_CRYPTO_STREEBOG) += streebog_generic.o
 obj-$(CONFIG_CRYPTO_WP512) += wp512.o
 CFLAGS_wp512.o := $(call cc-option,-fno-schedule-insns)  # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149
 obj-$(CONFIG_CRYPTO_BLAKE2B) += blake2b_generic.o
-obj-$(CONFIG_CRYPTO_BLAKE2S) += blake2s_generic.o
 obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o
 obj-$(CONFIG_CRYPTO_ECB) += ecb.o
 obj-$(CONFIG_CRYPTO_CBC) += cbc.o
@@ -94,6 +93,8 @@ obj-$(CONFIG_CRYPTO_CTS) += cts.o
 obj-$(CONFIG_CRYPTO_LRW) += lrw.o
 obj-$(CONFIG_CRYPTO_XTS) += xts.o
 obj-$(CONFIG_CRYPTO_CTR) += ctr.o
+obj-$(CONFIG_CRYPTO_XCTR) += xctr.o
+obj-$(CONFIG_CRYPTO_HCTR2) += hctr2.o
 obj-$(CONFIG_CRYPTO_KEYWRAP) += keywrap.o
 obj-$(CONFIG_CRYPTO_ADIANTUM) += adiantum.o
 obj-$(CONFIG_CRYPTO_NHPOLY1305) += nhpoly1305.o
@@ -171,6 +172,7 @@ UBSAN_SANITIZE_jitterentropy.o = n
 jitterentropy_rng-y := jitterentropy.o jitterentropy-kcapi.o
 obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o
 obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o
+obj-$(CONFIG_CRYPTO_POLYVAL) += polyval-generic.o
 obj-$(CONFIG_CRYPTO_USER_API) += af_alg.o
 obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o
 obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o
diff --git a/crypto/asymmetric_keys/Kconfig b/crypto/asymmetric_keys/Kconfig
index 460bc5d0a828..3df3fe4ed95f 100644
--- a/crypto/asymmetric_keys/Kconfig
+++ b/crypto/asymmetric_keys/Kconfig
@@ -75,4 +75,14 @@ config SIGNED_PE_FILE_VERIFICATION
 	  This option provides support for verifying the signature(s) on a
 	  signed PE binary.
 
+config FIPS_SIGNATURE_SELFTEST
+	bool "Run FIPS selftests on the X.509+PKCS7 signature verification"
+	help
+	  This option causes some selftests to be run on the signature
+	  verification code, using some built in data.  This is required
+	  for FIPS.
+	depends on KEYS
+	depends on ASYMMETRIC_KEY_TYPE
+	depends on PKCS7_MESSAGE_PARSER
+
 endif # ASYMMETRIC_KEY_TYPE
diff --git a/crypto/asymmetric_keys/Makefile b/crypto/asymmetric_keys/Makefile
index c38424f55b08..0d1fa1b692c6 100644
--- a/crypto/asymmetric_keys/Makefile
+++ b/crypto/asymmetric_keys/Makefile
@@ -20,7 +20,9 @@ x509_key_parser-y := \
 	x509.asn1.o \
 	x509_akid.asn1.o \
 	x509_cert_parser.o \
+	x509_loader.o \
 	x509_public_key.o
+x509_key_parser-$(CONFIG_FIPS_SIGNATURE_SELFTEST) += selftest.o
 
 $(obj)/x509_cert_parser.o: \
 	$(obj)/x509.asn1.h \
diff --git a/crypto/asymmetric_keys/selftest.c b/crypto/asymmetric_keys/selftest.c
new file mode 100644
index 000000000000..fa0bf7f24284
--- /dev/null
+++ b/crypto/asymmetric_keys/selftest.c
@@ -0,0 +1,224 @@
+/* Self-testing for signature checking.
+ *
+ * Copyright (C) 2022 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ */
+
+#include <linux/kernel.h>
+#include <linux/cred.h>
+#include <linux/key.h>
+#include <crypto/pkcs7.h>
+#include "x509_parser.h"
+
+struct certs_test {
+	const u8	*data;
+	size_t		data_len;
+	const u8	*pkcs7;
+	size_t		pkcs7_len;
+};
+
+/*
+ * Set of X.509 certificates to provide public keys for the tests.  These will
+ * be loaded into a temporary keyring for the duration of the testing.
+ */
+static const __initconst u8 certs_selftest_keys[] = {
+	"\x30\x82\x05\x55\x30\x82\x03\x3d\xa0\x03\x02\x01\x02\x02\x14\x73"
+	"\x98\xea\x98\x2d\xd0\x2e\xa8\xb1\xcf\x57\xc7\xf2\x97\xb3\xe6\x1a"
+	"\xfc\x8c\x0a\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x01\x0b"
+	"\x05\x00\x30\x34\x31\x32\x30\x30\x06\x03\x55\x04\x03\x0c\x29\x43"
+	"\x65\x72\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69\x66"
+	"\x69\x63\x61\x74\x69\x6f\x6e\x20\x73\x65\x6c\x66\x2d\x74\x65\x73"
+	"\x74\x69\x6e\x67\x20\x6b\x65\x79\x30\x20\x17\x0d\x32\x32\x30\x35"
+	"\x31\x38\x32\x32\x33\x32\x34\x31\x5a\x18\x0f\x32\x31\x32\x32\x30"
+	"\x34\x32\x34\x32\x32\x33\x32\x34\x31\x5a\x30\x34\x31\x32\x30\x30"
+	"\x06\x03\x55\x04\x03\x0c\x29\x43\x65\x72\x74\x69\x66\x69\x63\x61"
+	"\x74\x65\x20\x76\x65\x72\x69\x66\x69\x63\x61\x74\x69\x6f\x6e\x20"
+	"\x73\x65\x6c\x66\x2d\x74\x65\x73\x74\x69\x6e\x67\x20\x6b\x65\x79"
+	"\x30\x82\x02\x22\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x01"
+	"\x01\x05\x00\x03\x82\x02\x0f\x00\x30\x82\x02\x0a\x02\x82\x02\x01"
+	"\x00\xcc\xac\x49\xdd\x3b\xca\xb0\x15\x7e\x84\x6a\xb2\x0a\x69\x5f"
+	"\x1c\x0a\x61\x82\x3b\x4f\x2c\xa3\x95\x2c\x08\x58\x4b\xb1\x5d\x99"
+	"\xe0\xc3\xc1\x79\xc2\xb3\xeb\xc0\x1e\x6d\x3e\x54\x1d\xbd\xb7\x92"
+	"\x7b\x4d\xb5\x95\x58\xb2\x52\x2e\xc6\x24\x4b\x71\x63\x80\x32\x77"
+	"\xa7\x38\x5e\xdb\x72\xae\x6e\x0d\xec\xfb\xb6\x6d\x01\x7f\xe9\x55"
+	"\x66\xdf\xbf\x1d\x76\x78\x02\x31\xe8\xe5\x07\xf8\xb7\x82\x5c\x0d"
+	"\xd4\xbb\xfb\xa2\x59\x0d\x2e\x3a\x78\x95\x3a\x8b\x46\x06\x47\x44"
+	"\x46\xd7\xcd\x06\x6a\x41\x13\xe3\x19\xf6\xbb\x6e\x38\xf4\x83\x01"
+	"\xa3\xbf\x4a\x39\x4f\xd7\x0a\xe9\x38\xb3\xf5\x94\x14\x4e\xdd\xf7"
+	"\x43\xfd\x24\xb2\x49\x3c\xa5\xf7\x7a\x7c\xd4\x45\x3d\x97\x75\x68"
+	"\xf1\xed\x4c\x42\x0b\x70\xca\x85\xf3\xde\xe5\x88\x2c\xc5\xbe\xb6"
+	"\x97\x34\xba\x24\x02\xcd\x8b\x86\x9f\xa9\x73\xca\x73\xcf\x92\x81"
+	"\xee\x75\x55\xbb\x18\x67\x5c\xff\x3f\xb5\xdd\x33\x1b\x0c\xe9\x78"
+	"\xdb\x5c\xcf\xaa\x5c\x43\x42\xdf\x5e\xa9\x6d\xec\xd7\xd7\xff\xe6"
+	"\xa1\x3a\x92\x1a\xda\xae\xf6\x8c\x6f\x7b\xd5\xb4\x6e\x06\xe9\x8f"
+	"\xe8\xde\x09\x31\x89\xed\x0e\x11\xa1\xfa\x8a\xe9\xe9\x64\x59\x62"
+	"\x53\xda\xd1\x70\xbe\x11\xd4\x99\x97\x11\xcf\x99\xde\x0b\x9d\x94"
+	"\x7e\xaa\xb8\x52\xea\x37\xdb\x90\x7e\x35\xbd\xd9\xfe\x6d\x0a\x48"
+	"\x70\x28\xdd\xd5\x0d\x7f\x03\x80\x93\x14\x23\x8f\xb9\x22\xcd\x7c"
+	"\x29\xfe\xf1\x72\xb5\x5c\x0b\x12\xcf\x9c\x15\xf6\x11\x4c\x7a\x45"
+	"\x25\x8c\x45\x0a\x34\xac\x2d\x9a\x81\xca\x0b\x13\x22\xcd\xeb\x1a"
+	"\x38\x88\x18\x97\x96\x08\x81\xaa\xcc\x8f\x0f\x8a\x32\x7b\x76\x68"
+	"\x03\x68\x43\xbf\x11\xba\x55\x60\xfd\x80\x1c\x0d\x9b\x69\xb6\x09"
+	"\x72\xbc\x0f\x41\x2f\x07\x82\xc6\xe3\xb2\x13\x91\xc4\x6d\x14\x95"
+	"\x31\xbe\x19\xbd\xbc\xed\xe1\x4c\x74\xa2\xe0\x78\x0b\xbb\x94\xec"
+	"\x4c\x53\x3a\xa2\xb5\x84\x1d\x4b\x65\x7e\xdc\xf7\xdb\x36\x7d\xbe"
+	"\x9e\x3b\x36\x66\x42\x66\x76\x35\xbf\xbe\xf0\xc1\x3c\x7c\xe9\x42"
+	"\x5c\x24\x53\x03\x05\xa8\x67\x24\x50\x02\x75\xff\x24\x46\x3b\x35"
+	"\x89\x76\xe6\x70\xda\xc5\x51\x8c\x9a\xe5\x05\xb0\x0b\xd0\x2d\xd4"
+	"\x7d\x57\x75\x94\x6b\xf9\x0a\xad\x0e\x41\x00\x15\xd0\x4f\xc0\x7f"
+	"\x90\x2d\x18\x48\x8f\x28\xfe\x5d\xa7\xcd\x99\x9e\xbd\x02\x6c\x8a"
+	"\x31\xf3\x1c\xc7\x4b\xe6\x93\xcd\x42\xa2\xe4\x68\x10\x47\x9d\xfc"
+	"\x21\x02\x03\x01\x00\x01\xa3\x5d\x30\x5b\x30\x0c\x06\x03\x55\x1d"
+	"\x13\x01\x01\xff\x04\x02\x30\x00\x30\x0b\x06\x03\x55\x1d\x0f\x04"
+	"\x04\x03\x02\x07\x80\x30\x1d\x06\x03\x55\x1d\x0e\x04\x16\x04\x14"
+	"\xf5\x87\x03\xbb\x33\xce\x1b\x73\xee\x02\xec\xcd\xee\x5b\x88\x17"
+	"\x51\x8f\xe3\xdb\x30\x1f\x06\x03\x55\x1d\x23\x04\x18\x30\x16\x80"
+	"\x14\xf5\x87\x03\xbb\x33\xce\x1b\x73\xee\x02\xec\xcd\xee\x5b\x88"
+	"\x17\x51\x8f\xe3\xdb\x30\x0d\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01"
+	"\x01\x0b\x05\x00\x03\x82\x02\x01\x00\xc0\x2e\x12\x41\x7b\x73\x85"
+	"\x16\xc8\xdb\x86\x79\xe8\xf5\xcd\x44\xf4\xc6\xe2\x81\x23\x5e\x47"
+	"\xcb\xab\x25\xf1\x1e\x58\x3e\x31\x7f\x78\xad\x85\xeb\xfe\x14\x88"
+	"\x60\xf7\x7f\xd2\x26\xa2\xf4\x98\x2a\xfd\xba\x05\x0c\x20\x33\x12"
+	"\xcc\x4d\x14\x61\x64\x81\x93\xd3\x33\xed\xc8\xff\xf1\x78\xcc\x5f"
+	"\x51\x9f\x09\xd7\xbe\x0d\x5c\x74\xfd\x9b\xdf\x52\x4a\xc9\xa8\x71"
+	"\x25\x33\x04\x10\x67\x36\xd0\xb3\x0b\xc9\xa1\x40\x72\xae\x41\x7b"
+	"\x68\xe6\xe4\x7b\xd0\x28\xf7\x6d\xe7\x3f\x50\xfc\x91\x7c\x91\x56"
+	"\xd4\xdf\xa6\xbb\xe8\x4d\x1b\x58\xaa\x28\xfa\xc1\x19\xeb\x11\x2f"
+	"\x24\x8b\x7c\xc5\xa9\x86\x26\xaa\x6e\xb7\x9b\xd5\xf8\x06\xfb\x02"
+	"\x52\x7b\x9c\x9e\xa1\xe0\x07\x8b\x5e\xe4\xb8\x55\x29\xf6\x48\x52"
+	"\x1c\x1b\x54\x2d\x46\xd8\xe5\x71\xb9\x60\xd1\x45\xb5\x92\x89\x8a"
+	"\x63\x58\x2a\xb3\xc6\xb2\x76\xe2\x3c\x82\x59\x04\xae\x5a\xc4\x99"
+	"\x7b\x2e\x4b\x46\x57\xb8\x29\x24\xb2\xfd\xee\x2c\x0d\xa4\x83\xfa"
+	"\x65\x2a\x07\x35\x8b\x97\xcf\xbd\x96\x2e\xd1\x7e\x6c\xc2\x1e\x87"
+	"\xb6\x6c\x76\x65\xb5\xb2\x62\xda\x8b\xe9\x73\xe3\xdb\x33\xdd\x13"
+	"\x3a\x17\x63\x6a\x76\xde\x8d\x8f\xe0\x47\x61\x28\x3a\x83\xff\x8f"
+	"\xe7\xc7\xe0\x4a\xa3\xe5\x07\xcf\xe9\x8c\x35\x35\x2e\xe7\x80\x66"
+	"\x31\xbf\x91\x58\x0a\xe1\x25\x3d\x38\xd3\xa4\xf0\x59\x34\x47\x07"
+	"\x62\x0f\xbe\x30\xdd\x81\x88\x58\xf0\x28\xb0\x96\xe5\x82\xf8\x05"
+	"\xb7\x13\x01\xbc\xfa\xc6\x1f\x86\x72\xcc\xf9\xee\x8e\xd9\xd6\x04"
+	"\x8c\x24\x6c\xbf\x0f\x5d\x37\x39\xcf\x45\xc1\x93\x3a\xd2\xed\x5c"
+	"\x58\x79\x74\x86\x62\x30\x7e\x8e\xbb\xdd\x7a\xa9\xed\xca\x40\xcb"
+	"\x62\x47\xf4\xb4\x9f\x52\x7f\x72\x63\xa8\xf0\x2b\xaf\x45\x2a\x48"
+	"\x19\x6d\xe3\xfb\xf9\x19\x66\x69\xc8\xcc\x62\x87\x6c\x53\x2b\x2d"
+	"\x6e\x90\x6c\x54\x3a\x82\x25\x41\xcb\x18\x6a\xa4\x22\xa8\xa1\xc4"
+	"\x47\xd7\x81\x00\x1c\x15\x51\x0f\x1a\xaf\xef\x9f\xa6\x61\x8c\xbd"
+	"\x6b\x8b\xed\xe6\xac\x0e\xb6\x3a\x4c\x92\xe6\x0f\x91\x0a\x0f\x71"
+	"\xc7\xa0\xb9\x0d\x3a\x17\x5a\x6f\x35\xc8\xe7\x50\x4f\x46\xe8\x70"
+	"\x60\x48\x06\x82\x8b\x66\x58\xe6\x73\x91\x9c\x12\x3d\x35\x8e\x46"
+	"\xad\x5a\xf5\xb3\xdb\x69\x21\x04\xfd\xd3\x1c\xdf\x94\x9d\x56\xb0"
+	"\x0a\xd1\x95\x76\x8d\xec\x9e\xdd\x0b\x15\x97\x64\xad\xe5\xf2\x62"
+	"\x02\xfc\x9e\x5f\x56\x42\x39\x05\xb3"
+};
+
+/*
+ * Signed data and detached signature blobs that form the verification tests.
+ */
+static const __initconst u8 certs_selftest_1_data[] = {
+	"\x54\x68\x69\x73\x20\x69\x73\x20\x73\x6f\x6d\x65\x20\x74\x65\x73"
+	"\x74\x20\x64\x61\x74\x61\x20\x75\x73\x65\x64\x20\x66\x6f\x72\x20"
+	"\x73\x65\x6c\x66\x2d\x74\x65\x73\x74\x69\x6e\x67\x20\x63\x65\x72"
+	"\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69\x66\x69\x63"
+	"\x61\x74\x69\x6f\x6e\x2e\x0a"
+};
+
+static const __initconst u8 certs_selftest_1_pkcs7[] = {
+	"\x30\x82\x02\xab\x06\x09\x2a\x86\x48\x86\xf7\x0d\x01\x07\x02\xa0"
+	"\x82\x02\x9c\x30\x82\x02\x98\x02\x01\x01\x31\x0d\x30\x0b\x06\x09"
+	"\x60\x86\x48\x01\x65\x03\x04\x02\x01\x30\x0b\x06\x09\x2a\x86\x48"
+	"\x86\xf7\x0d\x01\x07\x01\x31\x82\x02\x75\x30\x82\x02\x71\x02\x01"
+	"\x01\x30\x4c\x30\x34\x31\x32\x30\x30\x06\x03\x55\x04\x03\x0c\x29"
+	"\x43\x65\x72\x74\x69\x66\x69\x63\x61\x74\x65\x20\x76\x65\x72\x69"
+	"\x66\x69\x63\x61\x74\x69\x6f\x6e\x20\x73\x65\x6c\x66\x2d\x74\x65"
+	"\x73\x74\x69\x6e\x67\x20\x6b\x65\x79\x02\x14\x73\x98\xea\x98\x2d"
+	"\xd0\x2e\xa8\xb1\xcf\x57\xc7\xf2\x97\xb3\xe6\x1a\xfc\x8c\x0a\x30"
+	"\x0b\x06\x09\x60\x86\x48\x01\x65\x03\x04\x02\x01\x30\x0d\x06\x09"
+	"\x2a\x86\x48\x86\xf7\x0d\x01\x01\x01\x05\x00\x04\x82\x02\x00\xac"
+	"\xb0\xf2\x07\xd6\x99\x6d\xc0\xc0\xd9\x8d\x31\x0d\x7e\x04\xeb\xc3"
+	"\x88\x90\xc4\x58\x46\xd4\xe2\xa0\xa3\x25\xe3\x04\x50\x37\x85\x8c"
+	"\x91\xc6\xfc\xc5\xd4\x92\xfd\x05\xd8\xb8\xa3\xb8\xba\x89\x13\x00"
+	"\x88\x79\x99\x51\x6b\x5b\x28\x31\xc0\xb3\x1b\x7a\x68\x2c\x00\xdb"
+	"\x4b\x46\x11\xf3\xfa\x50\x8e\x19\x89\xa2\x4c\xda\x4c\x89\x01\x11"
+	"\x89\xee\xd3\xc8\xc1\xe7\xa7\xf6\xb2\xa2\xf8\x65\xb8\x35\x20\x33"
+	"\xba\x12\x62\xd5\xbd\xaa\x71\xe5\x5b\xc0\x6a\x32\xff\x6a\x2e\x23"
+	"\xef\x2b\xb6\x58\xb1\xfb\x5f\x82\x34\x40\x6d\x9f\xbc\x27\xac\x37"
+	"\x23\x99\xcf\x7d\x20\xb2\x39\x01\xc0\x12\xce\xd7\x5d\x2f\xb6\xab"
+	"\xb5\x56\x4f\xef\xf4\x72\x07\x58\x65\xa9\xeb\x1f\x75\x1c\x5f\x0c"
+	"\x88\xe0\xa4\xe2\xcd\x73\x2b\x9e\xb2\x05\x7e\x12\xf8\xd0\x66\x41"
+	"\xcc\x12\x63\xd4\xd6\xac\x9b\x1d\x14\x77\x8d\x1c\x57\xd5\x27\xc6"
+	"\x49\xa2\x41\x43\xf3\x59\x29\xe5\xcb\xd1\x75\xbc\x3a\x97\x2a\x72"
+	"\x22\x66\xc5\x3b\xc1\xba\xfc\x53\x18\x98\xe2\x21\x64\xc6\x52\x87"
+	"\x13\xd5\x7c\x42\xe8\xfb\x9c\x9a\x45\x32\xd5\xa5\x22\x62\x9d\xd4"
+	"\xcb\xa4\xfa\x77\xbb\x50\x24\x0b\x8b\x88\x99\x15\x56\xa9\x1e\x92"
+	"\xbf\x5d\x94\x77\xb6\xf1\x67\x01\x60\x06\x58\x5c\xdf\x18\x52\x79"
+	"\x37\x30\x93\x7d\x87\x04\xf1\xe0\x55\x59\x52\xf3\xc2\xb1\x1c\x5b"
+	"\x12\x7c\x49\x87\xfb\xf7\xed\xdd\x95\x71\xec\x4b\x1a\x85\x08\xb0"
+	"\xa0\x36\xc4\x7b\xab\x40\xe0\xf1\x98\xcc\xaf\x19\x40\x8f\x47\x6f"
+	"\xf0\x6c\x84\x29\x7f\x7f\x04\x46\xcb\x08\x0f\xe0\xc1\xc9\x70\x6e"
+	"\x95\x3b\xa4\xbc\x29\x2b\x53\x67\x45\x1b\x0d\xbc\x13\xa5\x76\x31"
+	"\xaf\xb9\xd0\xe0\x60\x12\xd2\xf4\xb7\x7c\x58\x7e\xf6\x2d\xbb\x24"
+	"\x14\x5a\x20\x24\xa8\x12\xdf\x25\xbd\x42\xce\x96\x7c\x2e\xba\x14"
+	"\x1b\x81\x9f\x18\x45\xa4\xc6\x70\x3e\x0e\xf0\xd3\x7b\x9c\x10\xbe"
+	"\xb8\x7a\x89\xc5\x9e\xd9\x97\xdf\xd7\xe7\xc6\x1d\xc0\x20\x6c\xb8"
+	"\x1e\x3a\x63\xb8\x39\x8e\x8e\x62\xd5\xd2\xb4\xcd\xff\x46\xfc\x8e"
+	"\xec\x07\x35\x0c\xff\xb0\x05\xe6\xf4\xe5\xfe\xa2\xe3\x0a\xe6\x36"
+	"\xa7\x4a\x7e\x62\x1d\xc4\x50\x39\x35\x4e\x28\xcb\x4a\xfb\x9d\xdb"
+	"\xdd\x23\xd6\x53\xb1\x74\x77\x12\xf7\x9c\xf0\x9a\x6b\xf7\xa9\x64"
+	"\x2d\x86\x21\x2a\xcf\xc6\x54\xf5\xc9\xad\xfa\xb5\x12\xb4\xf3\x51"
+	"\x77\x55\x3c\x6f\x0c\x32\xd3\x8c\x44\x39\x71\x25\xfe\x96\xd2"
+};
+
+/*
+ * List of tests to be run.
+ */
+#define TEST(data, pkcs7) { data, sizeof(data) - 1, pkcs7, sizeof(pkcs7) - 1 }
+static const struct certs_test certs_tests[] __initconst = {
+	TEST(certs_selftest_1_data, certs_selftest_1_pkcs7),
+};
+
+int __init fips_signature_selftest(void)
+{
+	struct key *keyring;
+	int ret, i;
+
+	pr_notice("Running certificate verification selftests\n");
+
+	keyring = keyring_alloc(".certs_selftest",
+				GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, current_cred(),
+				(KEY_POS_ALL & ~KEY_POS_SETATTR) |
+				KEY_USR_VIEW | KEY_USR_READ |
+				KEY_USR_SEARCH,
+				KEY_ALLOC_NOT_IN_QUOTA,
+				NULL, NULL);
+	if (IS_ERR(keyring))
+		panic("Can't allocate certs selftest keyring: %ld\n",
+		      PTR_ERR(keyring));
+
+	ret = x509_load_certificate_list(certs_selftest_keys,
+					 sizeof(certs_selftest_keys) - 1, keyring);
+	if (ret < 0)
+		panic("Can't allocate certs selftest keyring: %d\n", ret);
+
+	for (i = 0; i < ARRAY_SIZE(certs_tests); i++) {
+		const struct certs_test *test = &certs_tests[i];
+		struct pkcs7_message *pkcs7;
+
+		pkcs7 = pkcs7_parse_message(test->pkcs7, test->pkcs7_len);
+		if (IS_ERR(pkcs7))
+			panic("Certs selftest %d: pkcs7_parse_message() = %d\n", i, ret);
+
+		pkcs7_supply_detached_data(pkcs7, test->data, test->data_len);
+
+		ret = pkcs7_verify(pkcs7, VERIFYING_MODULE_SIGNATURE);
+		if (ret < 0)
+			panic("Certs selftest %d: pkcs7_verify() = %d\n", i, ret);
+
+		ret = pkcs7_validate_trust(pkcs7, keyring);
+		if (ret < 0)
+			panic("Certs selftest %d: pkcs7_validate_trust() = %d\n", i, ret);
+
+		pkcs7_free_message(pkcs7);
+	}
+
+	key_put(keyring);
+	return 0;
+}
diff --git a/crypto/asymmetric_keys/x509_loader.c b/crypto/asymmetric_keys/x509_loader.c
new file mode 100644
index 000000000000..1bc169dee22e
--- /dev/null
+++ b/crypto/asymmetric_keys/x509_loader.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/kernel.h>
+#include <linux/key.h>
+#include <keys/asymmetric-type.h>
+
+int x509_load_certificate_list(const u8 cert_list[],
+			       const unsigned long list_size,
+			       const struct key *keyring)
+{
+	key_ref_t key;
+	const u8 *p, *end;
+	size_t plen;
+
+	p = cert_list;
+	end = p + list_size;
+	while (p < end) {
+		/* Each cert begins with an ASN.1 SEQUENCE tag and must be more
+		 * than 256 bytes in size.
+		 */
+		if (end - p < 4)
+			goto dodgy_cert;
+		if (p[0] != 0x30 &&
+		    p[1] != 0x82)
+			goto dodgy_cert;
+		plen = (p[2] << 8) | p[3];
+		plen += 4;
+		if (plen > end - p)
+			goto dodgy_cert;
+
+		key = key_create_or_update(make_key_ref(keyring, 1),
+					   "asymmetric",
+					   NULL,
+					   p,
+					   plen,
+					   ((KEY_POS_ALL & ~KEY_POS_SETATTR) |
+					   KEY_USR_VIEW | KEY_USR_READ),
+					   KEY_ALLOC_NOT_IN_QUOTA |
+					   KEY_ALLOC_BUILT_IN |
+					   KEY_ALLOC_BYPASS_RESTRICTION);
+		if (IS_ERR(key)) {
+			pr_err("Problem loading in-kernel X.509 certificate (%ld)\n",
+			       PTR_ERR(key));
+		} else {
+			pr_notice("Loaded X.509 cert '%s'\n",
+				  key_ref_to_ptr(key)->description);
+			key_ref_put(key);
+		}
+		p += plen;
+	}
+
+	return 0;
+
+dodgy_cert:
+	pr_err("Problem parsing in-kernel X.509 certificate list\n");
+	return 0;
+}
diff --git a/crypto/asymmetric_keys/x509_parser.h b/crypto/asymmetric_keys/x509_parser.h
index 97a886cbe01c..a299c9c56f40 100644
--- a/crypto/asymmetric_keys/x509_parser.h
+++ b/crypto/asymmetric_keys/x509_parser.h
@@ -40,6 +40,15 @@ struct x509_certificate {
 	bool		blacklisted;
 };
 
+/*
+ * selftest.c
+ */
+#ifdef CONFIG_FIPS_SIGNATURE_SELFTEST
+extern int __init fips_signature_selftest(void);
+#else
+static inline int fips_signature_selftest(void) { return 0; }
+#endif
+
 /*
  * x509_cert_parser.c
  */
diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c
index 77ed4e93ad56..0b4943a4592b 100644
--- a/crypto/asymmetric_keys/x509_public_key.c
+++ b/crypto/asymmetric_keys/x509_public_key.c
@@ -244,9 +244,15 @@ static struct asymmetric_key_parser x509_key_parser = {
 /*
  * Module stuff
  */
+extern int __init certs_selftest(void);
 static int __init x509_key_init(void)
 {
-	return register_asymmetric_key_parser(&x509_key_parser);
+	int ret;
+
+	ret = register_asymmetric_key_parser(&x509_key_parser);
+	if (ret < 0)
+		return ret;
+	return fips_signature_selftest();
 }
 
 static void __exit x509_key_exit(void)
diff --git a/crypto/blake2s_generic.c b/crypto/blake2s_generic.c
deleted file mode 100644
index 5f96a21f8788..000000000000
--- a/crypto/blake2s_generic.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * shash interface to the generic implementation of BLAKE2s
- *
- * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
- */
-
-#include <crypto/internal/blake2s.h>
-#include <crypto/internal/hash.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-static int crypto_blake2s_update_generic(struct shash_desc *desc,
-					 const u8 *in, unsigned int inlen)
-{
-	return crypto_blake2s_update(desc, in, inlen, true);
-}
-
-static int crypto_blake2s_final_generic(struct shash_desc *desc, u8 *out)
-{
-	return crypto_blake2s_final(desc, out, true);
-}
-
-#define BLAKE2S_ALG(name, driver_name, digest_size)			\
-	{								\
-		.base.cra_name		= name,				\
-		.base.cra_driver_name	= driver_name,			\
-		.base.cra_priority	= 100,				\
-		.base.cra_flags		= CRYPTO_ALG_OPTIONAL_KEY,	\
-		.base.cra_blocksize	= BLAKE2S_BLOCK_SIZE,		\
-		.base.cra_ctxsize	= sizeof(struct blake2s_tfm_ctx), \
-		.base.cra_module	= THIS_MODULE,			\
-		.digestsize		= digest_size,			\
-		.setkey			= crypto_blake2s_setkey,	\
-		.init			= crypto_blake2s_init,		\
-		.update			= crypto_blake2s_update_generic, \
-		.final			= crypto_blake2s_final_generic,	\
-		.descsize		= sizeof(struct blake2s_state),	\
-	}
-
-static struct shash_alg blake2s_algs[] = {
-	BLAKE2S_ALG("blake2s-128", "blake2s-128-generic",
-		    BLAKE2S_128_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-160", "blake2s-160-generic",
-		    BLAKE2S_160_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-224", "blake2s-224-generic",
-		    BLAKE2S_224_HASH_SIZE),
-	BLAKE2S_ALG("blake2s-256", "blake2s-256-generic",
-		    BLAKE2S_256_HASH_SIZE),
-};
-
-static int __init blake2s_mod_init(void)
-{
-	return crypto_register_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs));
-}
-
-static void __exit blake2s_mod_exit(void)
-{
-	crypto_unregister_shashes(blake2s_algs, ARRAY_SIZE(blake2s_algs));
-}
-
-subsys_initcall(blake2s_mod_init);
-module_exit(blake2s_mod_exit);
-
-MODULE_ALIAS_CRYPTO("blake2s-128");
-MODULE_ALIAS_CRYPTO("blake2s-128-generic");
-MODULE_ALIAS_CRYPTO("blake2s-160");
-MODULE_ALIAS_CRYPTO("blake2s-160-generic");
-MODULE_ALIAS_CRYPTO("blake2s-224");
-MODULE_ALIAS_CRYPTO("blake2s-224-generic");
-MODULE_ALIAS_CRYPTO("blake2s-256");
-MODULE_ALIAS_CRYPTO("blake2s-256-generic");
-MODULE_LICENSE("GPL v2");
diff --git a/crypto/hctr2.c b/crypto/hctr2.c
new file mode 100644
index 000000000000..7d00a3bcb667
--- /dev/null
+++ b/crypto/hctr2.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * HCTR2 length-preserving encryption mode
+ *
+ * Copyright 2021 Google LLC
+ */
+
+
+/*
+ * HCTR2 is a length-preserving encryption mode that is efficient on
+ * processors with instructions to accelerate AES and carryless
+ * multiplication, e.g. x86 processors with AES-NI and CLMUL, and ARM
+ * processors with the ARMv8 crypto extensions.
+ *
+ * For more details, see the paper: "Length-preserving encryption with HCTR2"
+ * (https://eprint.iacr.org/2021/1441.pdf)
+ */
+
+#include <crypto/internal/cipher.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/polyval.h>
+#include <crypto/scatterwalk.h>
+#include <linux/module.h>
+
+#define BLOCKCIPHER_BLOCK_SIZE		16
+
+/*
+ * The specification allows variable-length tweaks, but Linux's crypto API
+ * currently only allows algorithms to support a single length.  The "natural"
+ * tweak length for HCTR2 is 16, since that fits into one POLYVAL block for
+ * the best performance.  But longer tweaks are useful for fscrypt, to avoid
+ * needing to derive per-file keys.  So instead we use two blocks, or 32 bytes.
+ */
+#define TWEAK_SIZE		32
+
+struct hctr2_instance_ctx {
+	struct crypto_cipher_spawn blockcipher_spawn;
+	struct crypto_skcipher_spawn xctr_spawn;
+	struct crypto_shash_spawn polyval_spawn;
+};
+
+struct hctr2_tfm_ctx {
+	struct crypto_cipher *blockcipher;
+	struct crypto_skcipher *xctr;
+	struct crypto_shash *polyval;
+	u8 L[BLOCKCIPHER_BLOCK_SIZE];
+	int hashed_tweak_offset;
+	/*
+	 * This struct is allocated with extra space for two exported hash
+	 * states.  Since the hash state size is not known at compile-time, we
+	 * can't add these to the struct directly.
+	 *
+	 * hashed_tweaklen_divisible;
+	 * hashed_tweaklen_remainder;
+	 */
+};
+
+struct hctr2_request_ctx {
+	u8 first_block[BLOCKCIPHER_BLOCK_SIZE];
+	u8 xctr_iv[BLOCKCIPHER_BLOCK_SIZE];
+	struct scatterlist *bulk_part_dst;
+	struct scatterlist *bulk_part_src;
+	struct scatterlist sg_src[2];
+	struct scatterlist sg_dst[2];
+	/*
+	 * Sub-request sizes are unknown at compile-time, so they need to go
+	 * after the members with known sizes.
+	 */
+	union {
+		struct shash_desc hash_desc;
+		struct skcipher_request xctr_req;
+	} u;
+	/*
+	 * This struct is allocated with extra space for one exported hash
+	 * state.  Since the hash state size is not known at compile-time, we
+	 * can't add it to the struct directly.
+	 *
+	 * hashed_tweak;
+	 */
+};
+
+static inline u8 *hctr2_hashed_tweaklen(const struct hctr2_tfm_ctx *tctx,
+					bool has_remainder)
+{
+	u8 *p = (u8 *)tctx + sizeof(*tctx);
+
+	if (has_remainder) /* For messages not a multiple of block length */
+		p += crypto_shash_statesize(tctx->polyval);
+	return p;
+}
+
+static inline u8 *hctr2_hashed_tweak(const struct hctr2_tfm_ctx *tctx,
+				     struct hctr2_request_ctx *rctx)
+{
+	return (u8 *)rctx + tctx->hashed_tweak_offset;
+}
+
+/*
+ * The input data for each HCTR2 hash step begins with a 16-byte block that
+ * contains the tweak length and a flag that indicates whether the input is evenly
+ * divisible into blocks.  Since this implementation only supports one tweak
+ * length, we precompute the two hash states resulting from hashing the two
+ * possible values of this initial block.  This reduces by one block the amount of
+ * data that needs to be hashed for each encryption/decryption
+ *
+ * These precomputed hashes are stored in hctr2_tfm_ctx.
+ */
+static int hctr2_hash_tweaklen(struct hctr2_tfm_ctx *tctx, bool has_remainder)
+{
+	SHASH_DESC_ON_STACK(shash, tfm->polyval);
+	__le64 tweak_length_block[2];
+	int err;
+
+	shash->tfm = tctx->polyval;
+	memset(tweak_length_block, 0, sizeof(tweak_length_block));
+
+	tweak_length_block[0] = cpu_to_le64(TWEAK_SIZE * 8 * 2 + 2 + has_remainder);
+	err = crypto_shash_init(shash);
+	if (err)
+		return err;
+	err = crypto_shash_update(shash, (u8 *)tweak_length_block,
+				  POLYVAL_BLOCK_SIZE);
+	if (err)
+		return err;
+	return crypto_shash_export(shash, hctr2_hashed_tweaklen(tctx, has_remainder));
+}
+
+static int hctr2_setkey(struct crypto_skcipher *tfm, const u8 *key,
+			unsigned int keylen)
+{
+	struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+	u8 hbar[BLOCKCIPHER_BLOCK_SIZE];
+	int err;
+
+	crypto_cipher_clear_flags(tctx->blockcipher, CRYPTO_TFM_REQ_MASK);
+	crypto_cipher_set_flags(tctx->blockcipher,
+				crypto_skcipher_get_flags(tfm) &
+				CRYPTO_TFM_REQ_MASK);
+	err = crypto_cipher_setkey(tctx->blockcipher, key, keylen);
+	if (err)
+		return err;
+
+	crypto_skcipher_clear_flags(tctx->xctr, CRYPTO_TFM_REQ_MASK);
+	crypto_skcipher_set_flags(tctx->xctr,
+				  crypto_skcipher_get_flags(tfm) &
+				  CRYPTO_TFM_REQ_MASK);
+	err = crypto_skcipher_setkey(tctx->xctr, key, keylen);
+	if (err)
+		return err;
+
+	memset(hbar, 0, sizeof(hbar));
+	crypto_cipher_encrypt_one(tctx->blockcipher, hbar, hbar);
+
+	memset(tctx->L, 0, sizeof(tctx->L));
+	tctx->L[0] = 0x01;
+	crypto_cipher_encrypt_one(tctx->blockcipher, tctx->L, tctx->L);
+
+	crypto_shash_clear_flags(tctx->polyval, CRYPTO_TFM_REQ_MASK);
+	crypto_shash_set_flags(tctx->polyval, crypto_skcipher_get_flags(tfm) &
+			       CRYPTO_TFM_REQ_MASK);
+	err = crypto_shash_setkey(tctx->polyval, hbar, BLOCKCIPHER_BLOCK_SIZE);
+	if (err)
+		return err;
+	memzero_explicit(hbar, sizeof(hbar));
+
+	return hctr2_hash_tweaklen(tctx, true) ?: hctr2_hash_tweaklen(tctx, false);
+}
+
+static int hctr2_hash_tweak(struct skcipher_request *req)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	const struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+	struct hctr2_request_ctx *rctx = skcipher_request_ctx(req);
+	struct shash_desc *hash_desc = &rctx->u.hash_desc;
+	int err;
+	bool has_remainder = req->cryptlen % POLYVAL_BLOCK_SIZE;
+
+	hash_desc->tfm = tctx->polyval;
+	err = crypto_shash_import(hash_desc, hctr2_hashed_tweaklen(tctx, has_remainder));
+	if (err)
+		return err;
+	err = crypto_shash_update(hash_desc, req->iv, TWEAK_SIZE);
+	if (err)
+		return err;
+
+	// Store the hashed tweak, since we need it when computing both
+	// H(T || N) and H(T || V).
+	return crypto_shash_export(hash_desc, hctr2_hashed_tweak(tctx, rctx));
+}
+
+static int hctr2_hash_message(struct skcipher_request *req,
+			      struct scatterlist *sgl,
+			      u8 digest[POLYVAL_DIGEST_SIZE])
+{
+	static const u8 padding[BLOCKCIPHER_BLOCK_SIZE] = { 0x1 };
+	struct hctr2_request_ctx *rctx = skcipher_request_ctx(req);
+	struct shash_desc *hash_desc = &rctx->u.hash_desc;
+	const unsigned int bulk_len = req->cryptlen - BLOCKCIPHER_BLOCK_SIZE;
+	struct sg_mapping_iter miter;
+	unsigned int remainder = bulk_len % BLOCKCIPHER_BLOCK_SIZE;
+	int i;
+	int err = 0;
+	int n = 0;
+
+	sg_miter_start(&miter, sgl, sg_nents(sgl),
+		       SG_MITER_FROM_SG | SG_MITER_ATOMIC);
+	for (i = 0; i < bulk_len; i += n) {
+		sg_miter_next(&miter);
+		n = min_t(unsigned int, miter.length, bulk_len - i);
+		err = crypto_shash_update(hash_desc, miter.addr, n);
+		if (err)
+			break;
+	}
+	sg_miter_stop(&miter);
+
+	if (err)
+		return err;
+
+	if (remainder) {
+		err = crypto_shash_update(hash_desc, padding,
+					  BLOCKCIPHER_BLOCK_SIZE - remainder);
+		if (err)
+			return err;
+	}
+	return crypto_shash_final(hash_desc, digest);
+}
+
+static int hctr2_finish(struct skcipher_request *req)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	const struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+	struct hctr2_request_ctx *rctx = skcipher_request_ctx(req);
+	u8 digest[POLYVAL_DIGEST_SIZE];
+	struct shash_desc *hash_desc = &rctx->u.hash_desc;
+	int err;
+
+	// U = UU ^ H(T || V)
+	// or M = MM ^ H(T || N)
+	hash_desc->tfm = tctx->polyval;
+	err = crypto_shash_import(hash_desc, hctr2_hashed_tweak(tctx, rctx));
+	if (err)
+		return err;
+	err = hctr2_hash_message(req, rctx->bulk_part_dst, digest);
+	if (err)
+		return err;
+	crypto_xor(rctx->first_block, digest, BLOCKCIPHER_BLOCK_SIZE);
+
+	// Copy U (or M) into dst scatterlist
+	scatterwalk_map_and_copy(rctx->first_block, req->dst,
+				 0, BLOCKCIPHER_BLOCK_SIZE, 1);
+	return 0;
+}
+
+static void hctr2_xctr_done(struct crypto_async_request *areq,
+				    int err)
+{
+	struct skcipher_request *req = areq->data;
+
+	if (!err)
+		err = hctr2_finish(req);
+
+	skcipher_request_complete(req, err);
+}
+
+static int hctr2_crypt(struct skcipher_request *req, bool enc)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	const struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+	struct hctr2_request_ctx *rctx = skcipher_request_ctx(req);
+	u8 digest[POLYVAL_DIGEST_SIZE];
+	int bulk_len = req->cryptlen - BLOCKCIPHER_BLOCK_SIZE;
+	int err;
+
+	// Requests must be at least one block
+	if (req->cryptlen < BLOCKCIPHER_BLOCK_SIZE)
+		return -EINVAL;
+
+	// Copy M (or U) into a temporary buffer
+	scatterwalk_map_and_copy(rctx->first_block, req->src,
+				 0, BLOCKCIPHER_BLOCK_SIZE, 0);
+
+	// Create scatterlists for N and V
+	rctx->bulk_part_src = scatterwalk_ffwd(rctx->sg_src, req->src,
+					       BLOCKCIPHER_BLOCK_SIZE);
+	rctx->bulk_part_dst = scatterwalk_ffwd(rctx->sg_dst, req->dst,
+					       BLOCKCIPHER_BLOCK_SIZE);
+
+	// MM = M ^ H(T || N)
+	// or UU = U ^ H(T || V)
+	err = hctr2_hash_tweak(req);
+	if (err)
+		return err;
+	err = hctr2_hash_message(req, rctx->bulk_part_src, digest);
+	if (err)
+		return err;
+	crypto_xor(digest, rctx->first_block, BLOCKCIPHER_BLOCK_SIZE);
+
+	// UU = E(MM)
+	// or MM = D(UU)
+	if (enc)
+		crypto_cipher_encrypt_one(tctx->blockcipher, rctx->first_block,
+					  digest);
+	else
+		crypto_cipher_decrypt_one(tctx->blockcipher, rctx->first_block,
+					  digest);
+
+	// S = MM ^ UU ^ L
+	crypto_xor(digest, rctx->first_block, BLOCKCIPHER_BLOCK_SIZE);
+	crypto_xor_cpy(rctx->xctr_iv, digest, tctx->L, BLOCKCIPHER_BLOCK_SIZE);
+
+	// V = XCTR(S, N)
+	// or N = XCTR(S, V)
+	skcipher_request_set_tfm(&rctx->u.xctr_req, tctx->xctr);
+	skcipher_request_set_crypt(&rctx->u.xctr_req, rctx->bulk_part_src,
+				   rctx->bulk_part_dst, bulk_len,
+				   rctx->xctr_iv);
+	skcipher_request_set_callback(&rctx->u.xctr_req,
+				      req->base.flags,
+				      hctr2_xctr_done, req);
+	return crypto_skcipher_encrypt(&rctx->u.xctr_req) ?:
+		hctr2_finish(req);
+}
+
+static int hctr2_encrypt(struct skcipher_request *req)
+{
+	return hctr2_crypt(req, true);
+}
+
+static int hctr2_decrypt(struct skcipher_request *req)
+{
+	return hctr2_crypt(req, false);
+}
+
+static int hctr2_init_tfm(struct crypto_skcipher *tfm)
+{
+	struct skcipher_instance *inst = skcipher_alg_instance(tfm);
+	struct hctr2_instance_ctx *ictx = skcipher_instance_ctx(inst);
+	struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+	struct crypto_skcipher *xctr;
+	struct crypto_cipher *blockcipher;
+	struct crypto_shash *polyval;
+	unsigned int subreq_size;
+	int err;
+
+	xctr = crypto_spawn_skcipher(&ictx->xctr_spawn);
+	if (IS_ERR(xctr))
+		return PTR_ERR(xctr);
+
+	blockcipher = crypto_spawn_cipher(&ictx->blockcipher_spawn);
+	if (IS_ERR(blockcipher)) {
+		err = PTR_ERR(blockcipher);
+		goto err_free_xctr;
+	}
+
+	polyval = crypto_spawn_shash(&ictx->polyval_spawn);
+	if (IS_ERR(polyval)) {
+		err = PTR_ERR(polyval);
+		goto err_free_blockcipher;
+	}
+
+	tctx->xctr = xctr;
+	tctx->blockcipher = blockcipher;
+	tctx->polyval = polyval;
+
+	BUILD_BUG_ON(offsetofend(struct hctr2_request_ctx, u) !=
+				 sizeof(struct hctr2_request_ctx));
+	subreq_size = max(sizeof_field(struct hctr2_request_ctx, u.hash_desc) +
+			  crypto_shash_descsize(polyval),
+			  sizeof_field(struct hctr2_request_ctx, u.xctr_req) +
+			  crypto_skcipher_reqsize(xctr));
+
+	tctx->hashed_tweak_offset = offsetof(struct hctr2_request_ctx, u) +
+				    subreq_size;
+	crypto_skcipher_set_reqsize(tfm, tctx->hashed_tweak_offset +
+				    crypto_shash_statesize(polyval));
+	return 0;
+
+err_free_blockcipher:
+	crypto_free_cipher(blockcipher);
+err_free_xctr:
+	crypto_free_skcipher(xctr);
+	return err;
+}
+
+static void hctr2_exit_tfm(struct crypto_skcipher *tfm)
+{
+	struct hctr2_tfm_ctx *tctx = crypto_skcipher_ctx(tfm);
+
+	crypto_free_cipher(tctx->blockcipher);
+	crypto_free_skcipher(tctx->xctr);
+	crypto_free_shash(tctx->polyval);
+}
+
+static void hctr2_free_instance(struct skcipher_instance *inst)
+{
+	struct hctr2_instance_ctx *ictx = skcipher_instance_ctx(inst);
+
+	crypto_drop_cipher(&ictx->blockcipher_spawn);
+	crypto_drop_skcipher(&ictx->xctr_spawn);
+	crypto_drop_shash(&ictx->polyval_spawn);
+	kfree(inst);
+}
+
+static int hctr2_create_common(struct crypto_template *tmpl,
+			       struct rtattr **tb,
+			       const char *xctr_name,
+			       const char *polyval_name)
+{
+	u32 mask;
+	struct skcipher_instance *inst;
+	struct hctr2_instance_ctx *ictx;
+	struct skcipher_alg *xctr_alg;
+	struct crypto_alg *blockcipher_alg;
+	struct shash_alg *polyval_alg;
+	char blockcipher_name[CRYPTO_MAX_ALG_NAME];
+	int len;
+	int err;
+
+	err = crypto_check_attr_type(tb, CRYPTO_ALG_TYPE_SKCIPHER, &mask);
+	if (err)
+		return err;
+
+	inst = kzalloc(sizeof(*inst) + sizeof(*ictx), GFP_KERNEL);
+	if (!inst)
+		return -ENOMEM;
+	ictx = skcipher_instance_ctx(inst);
+
+	/* Stream cipher, xctr(block_cipher) */
+	err = crypto_grab_skcipher(&ictx->xctr_spawn,
+				   skcipher_crypto_instance(inst),
+				   xctr_name, 0, mask);
+	if (err)
+		goto err_free_inst;
+	xctr_alg = crypto_spawn_skcipher_alg(&ictx->xctr_spawn);
+
+	err = -EINVAL;
+	if (strncmp(xctr_alg->base.cra_name, "xctr(", 5))
+		goto err_free_inst;
+	len = strscpy(blockcipher_name, xctr_alg->base.cra_name + 5,
+		      sizeof(blockcipher_name));
+	if (len < 1)
+		goto err_free_inst;
+	if (blockcipher_name[len - 1] != ')')
+		goto err_free_inst;
+	blockcipher_name[len - 1] = 0;
+
+	/* Block cipher, e.g. "aes" */
+	err = crypto_grab_cipher(&ictx->blockcipher_spawn,
+				 skcipher_crypto_instance(inst),
+				 blockcipher_name, 0, mask);
+	if (err)
+		goto err_free_inst;
+	blockcipher_alg = crypto_spawn_cipher_alg(&ictx->blockcipher_spawn);
+
+	/* Require blocksize of 16 bytes */
+	err = -EINVAL;
+	if (blockcipher_alg->cra_blocksize != BLOCKCIPHER_BLOCK_SIZE)
+		goto err_free_inst;
+
+	/* Polyval ε-∆U hash function */
+	err = crypto_grab_shash(&ictx->polyval_spawn,
+				skcipher_crypto_instance(inst),
+				polyval_name, 0, mask);
+	if (err)
+		goto err_free_inst;
+	polyval_alg = crypto_spawn_shash_alg(&ictx->polyval_spawn);
+
+	/* Ensure Polyval is being used */
+	err = -EINVAL;
+	if (strcmp(polyval_alg->base.cra_name, "polyval") != 0)
+		goto err_free_inst;
+
+	/* Instance fields */
+
+	err = -ENAMETOOLONG;
+	if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, "hctr2(%s)",
+		     blockcipher_alg->cra_name) >= CRYPTO_MAX_ALG_NAME)
+		goto err_free_inst;
+	if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
+		     "hctr2_base(%s,%s)",
+		     xctr_alg->base.cra_driver_name,
+		     polyval_alg->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME)
+		goto err_free_inst;
+
+	inst->alg.base.cra_blocksize = BLOCKCIPHER_BLOCK_SIZE;
+	inst->alg.base.cra_ctxsize = sizeof(struct hctr2_tfm_ctx) +
+				     polyval_alg->statesize * 2;
+	inst->alg.base.cra_alignmask = xctr_alg->base.cra_alignmask |
+				       polyval_alg->base.cra_alignmask;
+	/*
+	 * The hash function is called twice, so it is weighted higher than the
+	 * xctr and blockcipher.
+	 */
+	inst->alg.base.cra_priority = (2 * xctr_alg->base.cra_priority +
+				       4 * polyval_alg->base.cra_priority +
+				       blockcipher_alg->cra_priority) / 7;
+
+	inst->alg.setkey = hctr2_setkey;
+	inst->alg.encrypt = hctr2_encrypt;
+	inst->alg.decrypt = hctr2_decrypt;
+	inst->alg.init = hctr2_init_tfm;
+	inst->alg.exit = hctr2_exit_tfm;
+	inst->alg.min_keysize = crypto_skcipher_alg_min_keysize(xctr_alg);
+	inst->alg.max_keysize = crypto_skcipher_alg_max_keysize(xctr_alg);
+	inst->alg.ivsize = TWEAK_SIZE;
+
+	inst->free = hctr2_free_instance;
+
+	err = skcipher_register_instance(tmpl, inst);
+	if (err) {
+err_free_inst:
+		hctr2_free_instance(inst);
+	}
+	return err;
+}
+
+static int hctr2_create_base(struct crypto_template *tmpl, struct rtattr **tb)
+{
+	const char *xctr_name;
+	const char *polyval_name;
+
+	xctr_name = crypto_attr_alg_name(tb[1]);
+	if (IS_ERR(xctr_name))
+		return PTR_ERR(xctr_name);
+
+	polyval_name = crypto_attr_alg_name(tb[2]);
+	if (IS_ERR(polyval_name))
+		return PTR_ERR(polyval_name);
+
+	return hctr2_create_common(tmpl, tb, xctr_name, polyval_name);
+}
+
+static int hctr2_create(struct crypto_template *tmpl, struct rtattr **tb)
+{
+	const char *blockcipher_name;
+	char xctr_name[CRYPTO_MAX_ALG_NAME];
+
+	blockcipher_name = crypto_attr_alg_name(tb[1]);
+	if (IS_ERR(blockcipher_name))
+		return PTR_ERR(blockcipher_name);
+
+	if (snprintf(xctr_name, CRYPTO_MAX_ALG_NAME, "xctr(%s)",
+		    blockcipher_name) >= CRYPTO_MAX_ALG_NAME)
+		return -ENAMETOOLONG;
+
+	return hctr2_create_common(tmpl, tb, xctr_name, "polyval");
+}
+
+static struct crypto_template hctr2_tmpls[] = {
+	{
+		/* hctr2_base(xctr_name, polyval_name) */
+		.name = "hctr2_base",
+		.create = hctr2_create_base,
+		.module = THIS_MODULE,
+	}, {
+		/* hctr2(blockcipher_name) */
+		.name = "hctr2",
+		.create = hctr2_create,
+		.module = THIS_MODULE,
+	}
+};
+
+static int __init hctr2_module_init(void)
+{
+	return crypto_register_templates(hctr2_tmpls, ARRAY_SIZE(hctr2_tmpls));
+}
+
+static void __exit hctr2_module_exit(void)
+{
+	return crypto_unregister_templates(hctr2_tmpls,
+					   ARRAY_SIZE(hctr2_tmpls));
+}
+
+subsys_initcall(hctr2_module_init);
+module_exit(hctr2_module_exit);
+
+MODULE_DESCRIPTION("HCTR2 length-preserving encryption mode");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("hctr2");
+MODULE_IMPORT_NS(CRYPTO_INTERNAL);
diff --git a/crypto/polyval-generic.c b/crypto/polyval-generic.c
new file mode 100644
index 000000000000..16bfa6925b31
--- /dev/null
+++ b/crypto/polyval-generic.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * POLYVAL: hash function for HCTR2.
+ *
+ * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
+ * Copyright (c) 2009 Intel Corp.
+ *   Author: Huang Ying <ying.huang@intel.com>
+ * Copyright 2021 Google LLC
+ */
+
+/*
+ * Code based on crypto/ghash-generic.c
+ *
+ * POLYVAL is a keyed hash function similar to GHASH. POLYVAL uses a different
+ * modulus for finite field multiplication which makes hardware accelerated
+ * implementations on little-endian machines faster. POLYVAL is used in the
+ * kernel to implement HCTR2, but was originally specified for AES-GCM-SIV
+ * (RFC 8452).
+ *
+ * For more information see:
+ * Length-preserving encryption with HCTR2:
+ *   https://eprint.iacr.org/2021/1441.pdf
+ * AES-GCM-SIV: Nonce Misuse-Resistant Authenticated Encryption:
+ *   https://datatracker.ietf.org/doc/html/rfc8452
+ *
+ * Like GHASH, POLYVAL is not a cryptographic hash function and should
+ * not be used outside of crypto modes explicitly designed to use POLYVAL.
+ *
+ * This implementation uses a convenient trick involving the GHASH and POLYVAL
+ * fields. This trick allows multiplication in the POLYVAL field to be
+ * implemented by using multiplication in the GHASH field as a subroutine. An
+ * element of the POLYVAL field can be converted to an element of the GHASH
+ * field by computing x*REVERSE(a), where REVERSE reverses the byte-ordering of
+ * a. Similarly, an element of the GHASH field can be converted back to the
+ * POLYVAL field by computing REVERSE(x^{-1}*a). For more information, see:
+ * https://datatracker.ietf.org/doc/html/rfc8452#appendix-A
+ *
+ * By using this trick, we do not need to implement the POLYVAL field for the
+ * generic implementation.
+ *
+ * Warning: this generic implementation is not intended to be used in practice
+ * and is not constant time. For practical use, a hardware accelerated
+ * implementation of POLYVAL should be used instead.
+ *
+ */
+
+#include <asm/unaligned.h>
+#include <crypto/algapi.h>
+#include <crypto/gf128mul.h>
+#include <crypto/polyval.h>
+#include <crypto/internal/hash.h>
+#include <linux/crypto.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+struct polyval_tfm_ctx {
+	struct gf128mul_4k *gf128;
+};
+
+struct polyval_desc_ctx {
+	union {
+		u8 buffer[POLYVAL_BLOCK_SIZE];
+		be128 buffer128;
+	};
+	u32 bytes;
+};
+
+static void copy_and_reverse(u8 dst[POLYVAL_BLOCK_SIZE],
+			     const u8 src[POLYVAL_BLOCK_SIZE])
+{
+	u64 a = get_unaligned((const u64 *)&src[0]);
+	u64 b = get_unaligned((const u64 *)&src[8]);
+
+	put_unaligned(swab64(a), (u64 *)&dst[8]);
+	put_unaligned(swab64(b), (u64 *)&dst[0]);
+}
+
+/*
+ * Performs multiplication in the POLYVAL field using the GHASH field as a
+ * subroutine.  This function is used as a fallback for hardware accelerated
+ * implementations when simd registers are unavailable.
+ *
+ * Note: This function is not used for polyval-generic, instead we use the 4k
+ * lookup table implementation for finite field multiplication.
+ */
+void polyval_mul_non4k(u8 *op1, const u8 *op2)
+{
+	be128 a, b;
+
+	// Assume one argument is in Montgomery form and one is not.
+	copy_and_reverse((u8 *)&a, op1);
+	copy_and_reverse((u8 *)&b, op2);
+	gf128mul_x_lle(&a, &a);
+	gf128mul_lle(&a, &b);
+	copy_and_reverse(op1, (u8 *)&a);
+}
+EXPORT_SYMBOL_GPL(polyval_mul_non4k);
+
+/*
+ * Perform a POLYVAL update using non4k multiplication.  This function is used
+ * as a fallback for hardware accelerated implementations when simd registers
+ * are unavailable.
+ *
+ * Note: This function is not used for polyval-generic, instead we use the 4k
+ * lookup table implementation of finite field multiplication.
+ */
+void polyval_update_non4k(const u8 *key, const u8 *in,
+			  size_t nblocks, u8 *accumulator)
+{
+	while (nblocks--) {
+		crypto_xor(accumulator, in, POLYVAL_BLOCK_SIZE);
+		polyval_mul_non4k(accumulator, key);
+		in += POLYVAL_BLOCK_SIZE;
+	}
+}
+EXPORT_SYMBOL_GPL(polyval_update_non4k);
+
+static int polyval_setkey(struct crypto_shash *tfm,
+			  const u8 *key, unsigned int keylen)
+{
+	struct polyval_tfm_ctx *ctx = crypto_shash_ctx(tfm);
+	be128 k;
+
+	if (keylen != POLYVAL_BLOCK_SIZE)
+		return -EINVAL;
+
+	gf128mul_free_4k(ctx->gf128);
+
+	BUILD_BUG_ON(sizeof(k) != POLYVAL_BLOCK_SIZE);
+	copy_and_reverse((u8 *)&k, key);
+	gf128mul_x_lle(&k, &k);
+
+	ctx->gf128 = gf128mul_init_4k_lle(&k);
+	memzero_explicit(&k, POLYVAL_BLOCK_SIZE);
+
+	if (!ctx->gf128)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int polyval_init(struct shash_desc *desc)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	memset(dctx, 0, sizeof(*dctx));
+
+	return 0;
+}
+
+static int polyval_update(struct shash_desc *desc,
+			 const u8 *src, unsigned int srclen)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *ctx = crypto_shash_ctx(desc->tfm);
+	u8 *pos;
+	u8 tmp[POLYVAL_BLOCK_SIZE];
+	int n;
+
+	if (dctx->bytes) {
+		n = min(srclen, dctx->bytes);
+		pos = dctx->buffer + dctx->bytes - 1;
+
+		dctx->bytes -= n;
+		srclen -= n;
+
+		while (n--)
+			*pos-- ^= *src++;
+
+		if (!dctx->bytes)
+			gf128mul_4k_lle(&dctx->buffer128, ctx->gf128);
+	}
+
+	while (srclen >= POLYVAL_BLOCK_SIZE) {
+		copy_and_reverse(tmp, src);
+		crypto_xor(dctx->buffer, tmp, POLYVAL_BLOCK_SIZE);
+		gf128mul_4k_lle(&dctx->buffer128, ctx->gf128);
+		src += POLYVAL_BLOCK_SIZE;
+		srclen -= POLYVAL_BLOCK_SIZE;
+	}
+
+	if (srclen) {
+		dctx->bytes = POLYVAL_BLOCK_SIZE - srclen;
+		pos = dctx->buffer + POLYVAL_BLOCK_SIZE - 1;
+		while (srclen--)
+			*pos-- ^= *src++;
+	}
+
+	return 0;
+}
+
+static int polyval_final(struct shash_desc *desc, u8 *dst)
+{
+	struct polyval_desc_ctx *dctx = shash_desc_ctx(desc);
+	const struct polyval_tfm_ctx *ctx = crypto_shash_ctx(desc->tfm);
+
+	if (dctx->bytes)
+		gf128mul_4k_lle(&dctx->buffer128, ctx->gf128);
+	copy_and_reverse(dst, dctx->buffer);
+	return 0;
+}
+
+static void polyval_exit_tfm(struct crypto_tfm *tfm)
+{
+	struct polyval_tfm_ctx *ctx = crypto_tfm_ctx(tfm);
+
+	gf128mul_free_4k(ctx->gf128);
+}
+
+static struct shash_alg polyval_alg = {
+	.digestsize	= POLYVAL_DIGEST_SIZE,
+	.init		= polyval_init,
+	.update		= polyval_update,
+	.final		= polyval_final,
+	.setkey		= polyval_setkey,
+	.descsize	= sizeof(struct polyval_desc_ctx),
+	.base		= {
+		.cra_name		= "polyval",
+		.cra_driver_name	= "polyval-generic",
+		.cra_priority		= 100,
+		.cra_blocksize		= POLYVAL_BLOCK_SIZE,
+		.cra_ctxsize		= sizeof(struct polyval_tfm_ctx),
+		.cra_module		= THIS_MODULE,
+		.cra_exit		= polyval_exit_tfm,
+	},
+};
+
+static int __init polyval_mod_init(void)
+{
+	return crypto_register_shash(&polyval_alg);
+}
+
+static void __exit polyval_mod_exit(void)
+{
+	crypto_unregister_shash(&polyval_alg);
+}
+
+subsys_initcall(polyval_mod_init);
+module_exit(polyval_mod_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("POLYVAL hash function");
+MODULE_ALIAS_CRYPTO("polyval");
+MODULE_ALIAS_CRYPTO("polyval-generic");
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 2bacf8384f59..a8831060c4ce 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -1556,6 +1556,7 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 		ret += tcrypt_test("rfc3686(ctr(aes))");
 		ret += tcrypt_test("ofb(aes)");
 		ret += tcrypt_test("cfb(aes)");
+		ret += tcrypt_test("xctr(aes)");
 		break;
 
 	case 11:
@@ -1669,10 +1670,6 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 		ret += tcrypt_test("rmd160");
 		break;
 
-	case 41:
-		ret += tcrypt_test("blake2s-256");
-		break;
-
 	case 42:
 		ret += tcrypt_test("blake2b-512");
 		break;
@@ -1729,6 +1726,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 		ret += tcrypt_test("ccm(sm4)");
 		break;
 
+	case 57:
+		ret += tcrypt_test("polyval");
+		break;
+
 	case 100:
 		ret += tcrypt_test("hmac(md5)");
 		break;
@@ -2186,6 +2187,11 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 				   16, 16, aead_speed_template_19, num_mb);
 		break;
 
+	case 226:
+		test_cipher_speed("hctr2(aes)", ENCRYPT, sec, NULL,
+				  0, speed_template_32);
+		break;
+
 	case 300:
 		if (alg) {
 			test_hash_speed(alg, sec, generic_hash_speed_template);
@@ -2240,10 +2246,6 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 		test_hash_speed("rmd160", sec, generic_hash_speed_template);
 		if (mode > 300 && mode < 400) break;
 		fallthrough;
-	case 316:
-		test_hash_speed("blake2s-256", sec, generic_hash_speed_template);
-		if (mode > 300 && mode < 400) break;
-		fallthrough;
 	case 317:
 		test_hash_speed("blake2b-512", sec, generic_hash_speed_template);
 		if (mode > 300 && mode < 400) break;
@@ -2352,10 +2354,6 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb)
 		test_ahash_speed("rmd160", sec, generic_hash_speed_template);
 		if (mode > 400 && mode < 500) break;
 		fallthrough;
-	case 416:
-		test_ahash_speed("blake2s-256", sec, generic_hash_speed_template);
-		if (mode > 400 && mode < 500) break;
-		fallthrough;
 	case 417:
 		test_ahash_speed("blake2b-512", sec, generic_hash_speed_template);
 		if (mode > 400 && mode < 500) break;
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 5801a8f9f713..7a8a56749960 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -4375,30 +4375,6 @@ static const struct alg_test_desc alg_test_descs[] = {
 		.suite = {
 			.hash = __VECS(blake2b_512_tv_template)
 		}
-	}, {
-		.alg = "blake2s-128",
-		.test = alg_test_hash,
-		.suite = {
-			.hash = __VECS(blakes2s_128_tv_template)
-		}
-	}, {
-		.alg = "blake2s-160",
-		.test = alg_test_hash,
-		.suite = {
-			.hash = __VECS(blakes2s_160_tv_template)
-		}
-	}, {
-		.alg = "blake2s-224",
-		.test = alg_test_hash,
-		.suite = {
-			.hash = __VECS(blakes2s_224_tv_template)
-		}
-	}, {
-		.alg = "blake2s-256",
-		.test = alg_test_hash,
-		.suite = {
-			.hash = __VECS(blakes2s_256_tv_template)
-		}
 	}, {
 		.alg = "cbc(aes)",
 		.test = alg_test_skcipher,
@@ -5088,6 +5064,14 @@ static const struct alg_test_desc alg_test_descs[] = {
 		.suite = {
 			.hash = __VECS(ghash_tv_template)
 		}
+	}, {
+		.alg = "hctr2(aes)",
+		.generic_driver =
+		    "hctr2_base(xctr(aes-generic),polyval-generic)",
+		.test = alg_test_skcipher,
+		.suite = {
+			.cipher = __VECS(aes_hctr2_tv_template)
+		}
 	}, {
 		.alg = "hmac(md5)",
 		.test = alg_test_hash,
@@ -5342,6 +5326,12 @@ static const struct alg_test_desc alg_test_descs[] = {
 		.suite = {
 			.hash = __VECS(poly1305_tv_template)
 		}
+	}, {
+		.alg = "polyval",
+		.test = alg_test_hash,
+		.suite = {
+			.hash = __VECS(polyval_tv_template)
+		}
 	}, {
 		.alg = "rfc3686(ctr(aes))",
 		.test = alg_test_skcipher,
@@ -5548,6 +5538,12 @@ static const struct alg_test_desc alg_test_descs[] = {
 		.suite = {
 			.cipher = __VECS(xchacha20_tv_template)
 		},
+	}, {
+		.alg = "xctr(aes)",
+		.test = alg_test_skcipher,
+		.suite = {
+			.cipher = __VECS(aes_xctr_tv_template)
+		}
 	}, {
 		.alg = "xts(aes)",
 		.generic_driver = "xts(ecb(aes-generic))",
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index 4d7449fc6a65..4f3955ea40bf 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -34034,221 +34034,1540 @@ static const struct hash_testvec blake2b_512_tv_template[] = {{
 			  0xae, 0x15, 0x81, 0x15, 0xd0, 0x88, 0xa0, 0x3c, },
 }};
 
-static const struct hash_testvec blakes2s_128_tv_template[] = {{
-	.digest = (u8[]){ 0x64, 0x55, 0x0d, 0x6f, 0xfe, 0x2c, 0x0a, 0x01,
-			  0xa1, 0x4a, 0xba, 0x1e, 0xad, 0xe0, 0x20, 0x0c, },
-}, {
-	.plaintext = blake2_ordered_sequence,
-	.psize = 64,
-	.digest = (u8[]){ 0xdc, 0x66, 0xca, 0x8f, 0x03, 0x86, 0x58, 0x01,
-			  0xb0, 0xff, 0xe0, 0x6e, 0xd8, 0xa1, 0xa9, 0x0e, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 1,
-	.digest = (u8[]){ 0x88, 0x1e, 0x42, 0xe7, 0xbb, 0x35, 0x80, 0x82,
-			  0x63, 0x7c, 0x0a, 0x0f, 0xd7, 0xec, 0x6c, 0x2f, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 7,
-	.digest = (u8[]){ 0xcf, 0x9e, 0x07, 0x2a, 0xd5, 0x22, 0xf2, 0xcd,
-			  0xa2, 0xd8, 0x25, 0x21, 0x80, 0x86, 0x73, 0x1c, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 15,
-	.digest = (u8[]){ 0xf6, 0x33, 0x5a, 0x2c, 0x22, 0xa0, 0x64, 0xb2,
-			  0xb6, 0x3f, 0xeb, 0xbc, 0xd1, 0xc3, 0xe5, 0xb2, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 247,
-	.digest = (u8[]){ 0x72, 0x66, 0x49, 0x60, 0xf9, 0x4a, 0xea, 0xbe,
-			  0x1f, 0xf4, 0x60, 0xce, 0xb7, 0x81, 0xcb, 0x09, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 256,
-	.digest = (u8[]){ 0xd5, 0xa4, 0x0e, 0xc3, 0x16, 0xc7, 0x51, 0xa6,
-			  0x3c, 0xd0, 0xd9, 0x11, 0x57, 0xfa, 0x1e, 0xbb, },
-}};
+/*
+ * Test vectors generated using https://github.com/google/hctr2
+ */
+static const struct cipher_testvec aes_xctr_tv_template[] = {
+	{
+		.key	= "\x9c\x8d\xc4\xbd\x71\x36\xdc\x82"
+			  "\x7c\xa1\xca\xa3\x23\x5a\xdb\xa4",
+		.iv	= "\x8d\xe7\xa5\x6a\x95\x86\x42\xde"
+			  "\xba\xea\x6e\x69\x03\x33\x86\x0f",
+		.ptext	= "\xbd",
+		.ctext	= "\xb9",
+		.klen	= 16,
+		.len	= 1,
+	},
+	{
+		.key	= "\xbc\x1b\x12\x0c\x3f\x18\xcc\x1f"
+			  "\x5a\x1d\xab\x81\xa8\x68\x7c\x63",
+		.iv	= "\x22\xc1\xdd\x25\x0b\x18\xcb\xa5"
+			  "\x4a\xda\x15\x07\x73\xd9\x88\x10",
+		.ptext	= "\x24\x6e\x64\xc6\x15\x26\x9c\xda"
+			  "\x2a\x4b\x57\x12\xff\x7c\xd6\xb5",
+		.ctext	= "\xd6\x47\x8d\x58\x92\xb2\x84\xf9"
+			  "\xb7\xee\x0d\x98\xa1\x39\x4d\x8f",
+		.klen	= 16,
+		.len	= 16,
+	},
+	{
+		.key	= "\x44\x03\xbf\x4c\x30\xf0\xa7\xd6"
+			  "\xbd\x54\xbb\x66\x8e\xa6\x0e\x8a",
+		.iv	= "\xe6\xf7\x26\xdf\x8c\x3c\xaa\x88"
+			  "\xce\xc1\xbd\x43\x3b\x09\x62\xad",
+		.ptext	= "\x3c\xe3\x46\xb9\x8f\x9d\x3f\x8d"
+			  "\xef\xf2\x53\xab\x24\xe2\x29\x08"
+			  "\xf8\x7e\x1d\xa6\x6d\x86\x7d\x60"
+			  "\x97\x63\x93\x29\x71\x94\xb4",
+		.ctext	= "\xd4\xa3\xc6\xb8\xc1\x6f\x70\x1a"
+			  "\x52\x0c\xed\x4c\xaf\x51\x56\x23"
+			  "\x48\x45\x07\x10\x34\xc5\xba\x71"
+			  "\xe5\xf8\x1e\xd8\xcb\xa6\xe7",
+		.klen	= 16,
+		.len	= 31,
+	},
+	{
+		.key	= "\x5b\x17\x30\x94\x19\x31\xa1\xae"
+			  "\x24\x8e\x42\x1e\x82\xe6\xec\xb8",
+		.iv	= "\xd1\x2e\xb9\xb8\xf8\x49\xeb\x68"
+			  "\x06\xeb\x65\x33\x34\xa2\xeb\xf0",
+		.ptext	= "\x19\x75\xec\x59\x60\x1b\x7a\x3e"
+			  "\x62\x46\x87\xf0\xde\xab\x81\x36"
+			  "\x63\x53\x11\xa0\x1f\xce\x25\x85"
+			  "\x49\x6b\x28\xfa\x1c\x92\xe5\x18"
+			  "\x38\x14\x00\x79\xf2\x9e\xeb\xfc"
+			  "\x36\xa7\x6b\xe1\xe5\xcf\x04\x48"
+			  "\x44\x6d\xbd\x64\xb3\xcb\x78\x05"
+			  "\x8d\x7f\x9a\xaf\x3c\xcf\x6c\x45"
+			  "\x6c\x7c\x46\x4c\xa8\xc0\x1e\xe4"
+			  "\x33\xa5\x7b\xbb\x26\xd9\xc0\x32"
+			  "\x9d\x8a\xb3\xf3\x3d\x52\xe6\x48"
+			  "\x4c\x9b\x4c\x6e\xa4\xa3\xad\x66"
+			  "\x56\x48\xd5\x98\x3a\x93\xc4\x85"
+			  "\xe9\x89\xca\xa6\xc1\xc8\xe7\xf8"
+			  "\xc3\xe9\xef\xbe\x77\xe6\xd1\x3a"
+			  "\xa6\x99\xc8\x2d\xdf\x40\x0f\x44",
+		.ctext	= "\xc6\x1a\x01\x1a\x00\xba\x04\xff"
+			  "\x10\xd1\x7e\x5d\xad\x91\xde\x8c"
+			  "\x08\x55\x95\xae\xd7\x22\x77\x40"
+			  "\xf0\x33\x1b\x51\xef\xfe\x3d\x67"
+			  "\xdf\xc4\x9f\x39\x47\x67\x93\xab"
+			  "\xaa\x37\x55\xfe\x41\xe0\xba\xcd"
+			  "\x25\x02\x7c\x61\x51\xa1\xcc\x72"
+			  "\x7a\x20\x26\xb9\x06\x68\xbd\x19"
+			  "\xc5\x2e\x1b\x75\x4a\x40\xb2\xd2"
+			  "\xc4\xee\xd8\x5b\xa4\x55\x7d\x25"
+			  "\xfc\x01\x4d\x6f\x0a\xfd\x37\x5d"
+			  "\x3e\x67\xc0\x35\x72\x53\x7b\xe2"
+			  "\xd6\x19\x5b\x92\x6c\x3a\x8c\x2a"
+			  "\xe2\xc2\xa2\x4f\x2a\xf2\xb5\x15"
+			  "\x65\xc5\x8d\x97\xf9\xbf\x8c\x98"
+			  "\xe4\x50\x1a\xf2\x76\x55\x07\x49",
+		.klen	= 16,
+		.len	= 128,
+	},
+	{
+		.key	= "\x17\xa6\x01\x3d\x5d\xd6\xef\x2d"
+			  "\x69\x8f\x4c\x54\x5b\xae\x43\xf0",
+		.iv	= "\xa9\x1b\x47\x60\x26\x82\xf7\x1c"
+			  "\x80\xf8\x88\xdd\xfb\x44\xd9\xda",
+		.ptext	= "\xf7\x67\xcd\xa6\x04\x65\x53\x99"
+			  "\x90\x5c\xa2\x56\x74\xd7\x9d\xf2"
+			  "\x0b\x03\x7f\x4e\xa7\x84\x72\x2b"
+			  "\xf0\xa5\xbf\xe6\x9a\x62\x3a\xfe"
+			  "\x69\x5c\x93\x79\x23\x86\x64\x85"
+			  "\xeb\x13\xb1\x5a\xd5\x48\x39\xa0"
+			  "\x70\xfb\x06\x9a\xd7\x12\x5a\xb9"
+			  "\xbe\xed\x2c\x81\x64\xf7\xcf\x80"
+			  "\xee\xe6\x28\x32\x2d\x37\x4c\x32"
+			  "\xf4\x1f\x23\x21\xe9\xc8\xc9\xbf"
+			  "\x54\xbc\xcf\xb4\xc2\x65\x39\xdf"
+			  "\xa5\xfb\x14\x11\xed\x62\x38\xcf"
+			  "\x9b\x58\x11\xdd\xe9\xbd\x37\x57"
+			  "\x75\x4c\x9e\xd5\x67\x0a\x48\xc6"
+			  "\x0d\x05\x4e\xb1\x06\xd7\xec\x2e"
+			  "\x9e\x59\xde\x4f\xab\x38\xbb\xe5"
+			  "\x87\x04\x5a\x2c\x2a\xa2\x8f\x3c"
+			  "\xe7\xe1\x46\xa9\x49\x9f\x24\xad"
+			  "\x2d\xb0\x55\x40\x64\xd5\xda\x7e"
+			  "\x1e\x77\xb8\x29\x72\x73\xc3\x84"
+			  "\xcd\xf3\x94\x90\x58\x76\xc9\x2c"
+			  "\x2a\xad\x56\xde\x33\x18\xb6\x3b"
+			  "\x10\xe9\xe9\x8d\xf0\xa9\x7f\x05"
+			  "\xf7\xb5\x8c\x13\x7e\x11\x3d\x1e"
+			  "\x02\xbb\x5b\xea\x69\xff\x85\xcf"
+			  "\x6a\x18\x97\x45\xe3\x96\xba\x4d"
+			  "\x2d\x7a\x70\x78\x15\x2c\xe9\xdc"
+			  "\x4e\x09\x92\x57\x04\xd8\x0b\xa6"
+			  "\x20\x71\x76\x47\x76\x96\x89\xa0"
+			  "\xd9\x29\xa2\x5a\x06\xdb\x56\x39"
+			  "\x60\x33\x59\x04\x95\x89\xf6\x18"
+			  "\x1d\x70\x75\x85\x3a\xb7\x6e",
+		.ctext	= "\xe1\xe7\x3f\xd3\x6a\xb9\x2f\x64"
+			  "\x37\xc5\xa4\xe9\xca\x0a\xa1\xd6"
+			  "\xea\x7d\x39\xe5\xe6\xcc\x80\x54"
+			  "\x74\x31\x2a\x04\x33\x79\x8c\x8e"
+			  "\x4d\x47\x84\x28\x27\x9b\x3c\x58"
+			  "\x54\x58\x20\x4f\x70\x01\x52\x5b"
+			  "\xac\x95\x61\x49\x5f\xef\xba\xce"
+			  "\xd7\x74\x56\xe7\xbb\xe0\x3c\xd0"
+			  "\x7f\xa9\x23\x57\x33\x2a\xf6\xcb"
+			  "\xbe\x42\x14\x95\xa8\xf9\x7a\x7e"
+			  "\x12\x53\x3a\xe2\x13\xfe\x2d\x89"
+			  "\xeb\xac\xd7\xa8\xa5\xf8\x27\xf3"
+			  "\x74\x9a\x65\x63\xd1\x98\x3a\x7e"
+			  "\x27\x7b\xc0\x20\x00\x4d\xf4\xe5"
+			  "\x7b\x69\xa6\xa8\x06\x50\x85\xb6"
+			  "\x7f\xac\x7f\xda\x1f\xf5\x37\x56"
+			  "\x9b\x2f\xd3\x86\x6b\x70\xbd\x0e"
+			  "\x55\x9a\x9d\x4b\x08\xb5\x5b\x7b"
+			  "\xd4\x7c\xb4\x71\x49\x92\x4a\x1e"
+			  "\xed\x6d\x11\x09\x47\x72\x32\x6a"
+			  "\x97\x53\x36\xaf\xf3\x06\x06\x2c"
+			  "\x69\xf1\x59\x00\x36\x95\x28\x2a"
+			  "\xb6\xcd\x10\x21\x84\x73\x5c\x96"
+			  "\x86\x14\x2c\x3d\x02\xdb\x53\x9a"
+			  "\x61\xde\xea\x99\x84\x7a\x27\xf6"
+			  "\xf7\xc8\x49\x73\x4b\xb8\xeb\xd3"
+			  "\x41\x33\xdd\x09\x68\xe2\x64\xb8"
+			  "\x5f\x75\x74\x97\x91\x54\xda\xc2"
+			  "\x73\x2c\x1e\x5a\x84\x48\x01\x1a"
+			  "\x0d\x8b\x0a\xdf\x07\x2e\xee\x77"
+			  "\x1d\x17\x41\x7a\xc9\x33\x63\xfa"
+			  "\x9f\xc3\x74\x57\x5f\x03\x4c",
+		.klen	= 16,
+		.len	= 255,
+	},
+	{
+		.key	= "\xe5\xf1\x48\x2e\x88\xdb\xc7\x28"
+			  "\xa2\x55\x5d\x2f\x90\x02\xdc\xd3"
+			  "\xf5\xd3\x9e\x87\xd5\x58\x30\x4a",
+		.iv	= "\xa6\x40\x39\xf9\x63\x6c\x2d\xd4"
+			  "\x1b\x71\x05\xa4\x88\x86\x11\xd3",
+		.ptext	= "\xb6\x06\xae\x15\x11\x96\xc1\x44"
+			  "\x44\xc2\x98\xf9\xa8\x0a\x0b",
+		.ctext	= "\x27\x3b\x68\x40\xa9\x5e\x74\x6b"
+			  "\x74\x67\x18\xf9\x37\xed\xed",
+		.klen	= 24,
+		.len	= 15,
+	},
+	{
+		.key	= "\xc8\xa0\x27\x67\x04\x3f\xed\xa5"
+			  "\xb4\x0c\x51\x91\x2d\x27\x77\x33"
+			  "\xa5\xfc\x2a\x9f\x78\xd8\x1c\x68",
+		.iv	= "\x83\x99\x1a\xe2\x84\xca\xa9\x16"
+			  "\x8d\xc4\x2d\x1b\x67\xc8\x86\x21",
+		.ptext	= "\xd6\x22\x85\xb8\x5d\x7e\x26\x2e"
+			  "\xbe\x04\x9d\x0c\x03\x91\x45\x4a"
+			  "\x36",
+		.ctext	= "\x0f\x44\xa9\x62\x72\xec\x12\x26"
+			  "\x3a\xc6\x83\x26\x62\x5e\xb7\x13"
+			  "\x05",
+		.klen	= 24,
+		.len	= 17,
+	},
+	{
+		.key	= "\xc5\x87\x18\x09\x0a\x4e\x66\x3e"
+			  "\x50\x90\x19\x93\xc0\x33\xcf\x80"
+			  "\x3a\x36\x6b\x6c\x43\xd7\xe4\x93",
+		.iv	= "\xdd\x0b\x75\x1f\xee\x2f\xb4\x52"
+			  "\x10\x82\x1f\x79\x8a\xa4\x9b\x87",
+		.ptext	= "\x56\xf9\x13\xce\x9f\x30\x10\x11"
+			  "\x1b\x59\xfd\x39\x5a\x29\xa3\x44"
+			  "\x78\x97\x8c\xf6\x99\x6d\x26\xf1"
+			  "\x32\x60\x6a\xeb\x04\x47\x29\x4c"
+			  "\x7e\x14\xef\x4d\x55\x29\xfe\x36"
+			  "\x37\xcf\x0b\x6e\xf3\xce\x15\xd2",
+		.ctext	= "\x8f\x98\xe1\x5a\x7f\xfe\xc7\x05"
+			  "\x76\xb0\xd5\xde\x90\x52\x2b\xa8"
+			  "\xf3\x6e\x3c\x77\xa5\x33\x63\xdd"
+			  "\x6f\x62\x12\xb0\x80\x10\xc1\x28"
+			  "\x58\xe5\xd6\x24\x44\x04\x55\xf3"
+			  "\x6d\x94\xcb\x2c\x7e\x7a\x85\x79",
+		.klen	= 24,
+		.len	= 48,
+	},
+	{
+		.key	= "\x84\x9b\xe8\x10\x4c\xb3\xd1\x7a"
+			  "\xb3\xab\x4e\x6f\x90\x12\x07\xf8"
+			  "\xef\xde\x42\x09\xbf\x34\x95\xb2",
+		.iv	= "\x66\x62\xf9\x48\x9d\x17\xf7\xdf"
+			  "\x06\x67\xf4\x6d\xf2\xbc\xa2\xe5",
+		.ptext	= "\x2f\xd6\x16\x6b\xf9\x4b\x44\x14"
+			  "\x90\x93\xe5\xfd\x05\xaa\x00\x26"
+			  "\xbd\xab\x11\xb8\xf0\xcb\x11\x72"
+			  "\xdd\xc5\x15\x4f\x4e\x1b\xf8\xc9"
+			  "\x8f\x4a\xd5\x69\xf8\x9e\xfb\x05"
+			  "\x8a\x37\x46\xfe\xfa\x58\x9b\x0e"
+			  "\x72\x90\x9a\x06\xa5\x42\xf4\x7c"
+			  "\x35\xd5\x64\x70\x72\x67\xfc\x8b"
+			  "\xab\x5a\x2f\x64\x9b\xa1\xec\xe7"
+			  "\xe6\x92\x69\xdb\x62\xa4\xe7\x44"
+			  "\x88\x28\xd4\x52\x64\x19\xa9\xd7"
+			  "\x0c\x00\xe6\xe7\xc1\x28\xc1\xf5"
+			  "\x72\xc5\xfa\x09\x22\x2e\xf4\x82"
+			  "\xa3\xdc\xc1\x68\xf9\x29\x55\x8d"
+			  "\x04\x67\x13\xa6\x52\x04\x3c\x0c"
+			  "\x14\xf2\x87\x23\x61\xab\x82\xcb"
+			  "\x49\x5b\x6b\xd4\x4f\x0d\xd4\x95"
+			  "\x82\xcd\xe3\x69\x47\x1b\x31\x73"
+			  "\x73\x77\xc1\x53\x7d\x43\x5e\x4a"
+			  "\x80\x3a\xca\x9c\xc7\x04\x1a\x31"
+			  "\x8e\xe6\x76\x7f\xe1\xb3\xd0\x57"
+			  "\xa2\xb2\xf6\x09\x51\xc9\x6d\xbc"
+			  "\x79\xed\x57\x50\x36\xd2\x93\xa4"
+			  "\x40\x5d\xac\x3a\x3b\xb6\x2d\x89"
+			  "\x78\xa2\xbd\x23\xec\x35\x06\xf0"
+			  "\xa8\xc8\xc9\xb0\xe3\x28\x2b\xba"
+			  "\x70\xa0\xfe\xed\x13\xc4\xd7\x90"
+			  "\xb1\x6a\xe0\xe1\x30\x71\x15\xd0"
+			  "\xe2\xb3\xa6\x4e\xb0\x01\xf9\xe7"
+			  "\x59\xc6\x1e\xed\x46\x2b\xe3\xa8"
+			  "\x22\xeb\x7f\x1c\xd9\xcd\xe0\xa6"
+			  "\x72\x42\x2c\x06\x75\xbb\xb7\x6b"
+			  "\xca\x49\x5e\xa1\x47\x8d\x9e\xfe"
+			  "\x60\xcc\x34\x95\x8e\xfa\x1e\x3e"
+			  "\x85\x4b\x03\x54\xea\x34\x1c\x41"
+			  "\x90\x45\xa6\xbe\xcf\x58\x4f\xca"
+			  "\x2c\x79\xc0\x3e\x8f\xd7\x3b\xd4"
+			  "\x55\x74\xa8\xe1\x57\x09\xbf\xab"
+			  "\x2c\xf9\xe4\xdd\x17\x99\x57\x60"
+			  "\x4b\x88\x2a\x7f\x43\x86\xb9\x9a"
+			  "\x60\xbf\x4c\xcf\x9b\x41\xb8\x99"
+			  "\x69\x15\x4f\x91\x4d\xeb\xdf\x6f"
+			  "\xcc\x4c\xf9\x6f\xf2\x33\x23\xe7"
+			  "\x02\x44\xaa\xa2\xfa\xb1\x39\xa5"
+			  "\xff\x88\xf5\x37\x02\x33\x24\xfc"
+			  "\x79\x11\x4c\x94\xc2\x31\x87\x9c"
+			  "\x53\x19\x99\x32\xe4\xde\x18\xf4"
+			  "\x8f\xe2\xe8\xa3\xfb\x0b\xaa\x7c"
+			  "\xdb\x83\x0f\xf6\xc0\x8a\x9b\xcd"
+			  "\x7b\x16\x05\x5b\xe4\xb4\x34\x03"
+			  "\xe3\x8f\xc9\x4b\x56\x84\x2a\x4c"
+			  "\x36\x72\x3c\x84\x4f\xba\xa2\x7f"
+			  "\xf7\x1b\xba\x4d\x8a\xb8\x5d\x51"
+			  "\x36\xfb\xef\x23\x18\x6f\x33\x2d"
+			  "\xbb\x06\x24\x8e\x33\x98\x6e\xcd"
+			  "\x63\x11\x18\x6b\xcc\x1b\x66\xb9"
+			  "\x38\x8d\x06\x8d\x98\x1a\xef\xaa"
+			  "\x35\x4a\x90\xfa\xb1\xd3\xcc\x11"
+			  "\x50\x4c\x54\x18\x60\x5d\xe4\x11"
+			  "\xfc\x19\xe1\x53\x20\x5c\xe7\xef"
+			  "\x8a\x2b\xa8\x82\x51\x5f\x5d\x43"
+			  "\x34\xe5\xcf\x7b\x1b\x6f\x81\x19"
+			  "\xb7\xdf\xa8\x9e\x81\x89\x5f\x33"
+			  "\x69\xaf\xde\x89\x68\x88\xf0\x71",
+		.ctext	= "\xab\x15\x46\x5b\xed\x4f\xa8\xac"
+			  "\xbf\x31\x30\x84\x55\xa4\xb8\x98"
+			  "\x79\xba\xa0\x15\xa4\x55\x20\xec"
+			  "\xf9\x94\x71\xe6\x6a\x6f\xee\x87"
+			  "\x2e\x3a\xa2\x95\xae\x6e\x56\x09"
+			  "\xe9\xc0\x0f\xe2\xc6\xb7\x30\xa9"
+			  "\x73\x8e\x59\x7c\xfd\xe3\x71\xf7"
+			  "\xae\x8b\x91\xab\x5e\x36\xe9\xa8"
+			  "\xff\x17\xfa\xa2\x94\x93\x11\x42"
+			  "\x67\x96\x99\xc5\xf0\xad\x2a\x57"
+			  "\xf9\xa6\x70\x4a\xdf\x71\xff\xc0"
+			  "\xe2\xaf\x9a\xae\x57\x58\x13\x3b"
+			  "\x2d\xf1\xc7\x8f\xdb\x8a\xcc\xce"
+			  "\x53\x1a\x69\x55\x39\xc8\xbe\xc3"
+			  "\x2d\xb1\x03\xd9\xa3\x99\xf4\x8d"
+			  "\xd9\x2d\x27\xae\xa5\xe7\x77\x7f"
+			  "\xbb\x88\x84\xea\xfa\x19\x3f\x44"
+			  "\x61\x21\x8a\x1f\xbe\xac\x60\xb4"
+			  "\xaf\xe9\x00\xab\xef\x3c\x53\x56"
+			  "\xcd\x4b\x53\xd8\x9b\xfe\x88\x23"
+			  "\x5b\x85\x76\x08\xec\xd1\x6e\x4a"
+			  "\x87\xa4\x7d\x29\x4e\x4f\x3f\xc9"
+			  "\xa4\xab\x63\xea\xdd\xef\x9f\x79"
+			  "\x38\x18\x7d\x90\x90\xf9\x12\x57"
+			  "\x1d\x89\xea\xfe\xd4\x47\x45\x32"
+			  "\x6a\xf6\xe7\xde\x22\x7e\xee\xc1"
+			  "\xbc\x2d\xc3\xbb\xe5\xd4\x13\xac"
+			  "\x63\xff\x5b\xb1\x05\x96\xd5\xf3"
+			  "\x07\x9a\x62\xb6\x30\xea\x7d\x1e"
+			  "\xee\x75\x0a\x1b\xcc\x6e\x4d\xa7"
+			  "\xf7\x4d\x74\xd8\x60\x32\x5e\xd0"
+			  "\x93\xd7\x19\x90\x4e\x26\xdb\xe4"
+			  "\x5e\xd4\xa8\xb9\x76\xba\x56\x91"
+			  "\xc4\x75\x04\x1e\xc2\x77\x24\x6f"
+			  "\xf9\xe8\x4a\xec\x7f\x86\x95\xb3"
+			  "\x5c\x2c\x97\xab\xf0\xf7\x74\x5b"
+			  "\x0b\xc2\xda\x42\x40\x34\x16\xed"
+			  "\x06\xc1\x25\x53\x17\x0d\x81\x4e"
+			  "\xe6\xf2\x0f\x6d\x94\x3c\x90\x7a"
+			  "\xae\x20\xe9\x3f\xf8\x18\x67\x6a"
+			  "\x49\x1e\x41\xb6\x46\xab\xc8\xa7"
+			  "\xcb\x19\x96\xf5\x99\xc0\x66\x3e"
+			  "\x77\xcf\x73\x52\x83\x2a\xe2\x48"
+			  "\x27\x6c\xeb\xe7\xe7\xc4\xd5\x6a"
+			  "\x40\x67\xbc\xbf\x6b\x3c\xf3\xbb"
+			  "\x51\x5e\x31\xac\x03\x81\xab\x61"
+			  "\xfa\xa5\xa6\x7d\x8b\xc3\x8a\x75"
+			  "\x28\x7a\x71\x9c\xac\x8f\x76\xfc"
+			  "\xf9\x6c\x5d\x9b\xd7\xf6\x36\x2d"
+			  "\x61\xd5\x61\xaa\xdd\x01\xfc\x57"
+			  "\x91\x10\xcd\xcd\x6d\x27\x63\x24"
+			  "\x67\x46\x7a\xbb\x61\x56\x39\xb1"
+			  "\xd6\x79\xfe\x77\xca\xd6\x73\x59"
+			  "\x6e\x58\x11\x90\x03\x26\x74\x2a"
+			  "\xfa\x52\x12\x47\xfb\x12\xeb\x3e"
+			  "\x88\xf0\x52\x6c\xc0\x54\x7a\x88"
+			  "\x8c\xe5\xde\x9e\xba\xb9\xf2\xe1"
+			  "\x97\x2e\x5c\xbd\xf4\x13\x7e\xf3"
+			  "\xc4\xe1\x87\xa5\x35\xfa\x7c\x71"
+			  "\x1a\xc9\xf4\xa8\x57\xe2\x5a\x6b"
+			  "\x14\xe0\x73\xaf\x56\x6b\xa0\x00"
+			  "\x9e\x5f\x64\xac\x00\xfb\xc4\x92"
+			  "\xe5\xe2\x8a\xb2\x9e\x75\x49\x85"
+			  "\x25\x66\xa5\x1a\xf9\x7d\x1d\x60",
+		.klen	= 24,
+		.len	= 512,
+	},
+	{
+		.key	= "\x05\x60\x3a\x7e\x60\x90\x46\x18"
+			  "\x6c\x60\xba\xeb\x12\xd7\xbe\xd1"
+			  "\xd3\xf6\x10\x46\x9d\xf1\x0c\xb4"
+			  "\x73\xe3\x93\x27\xa8\x2c\x13\xaa",
+		.iv	= "\xf5\x96\xd1\xb6\xcb\x44\xd8\xd0"
+			  "\x3e\xdb\x92\x80\x08\x94\xcd\xd3",
+		.ptext	= "\x78",
+		.ctext	= "\xc5",
+		.klen	= 32,
+		.len	= 1,
+	},
+	{
+		.key	= "\x35\xca\x38\xf3\xd9\xd6\x34\xef"
+			  "\xcd\xee\xa3\x26\x86\xba\xfb\x45"
+			  "\x01\xfa\x52\x67\xff\xc5\x9d\xaa"
+			  "\x64\x9a\x05\xbb\x85\x20\xa7\xf2",
+		.iv	= "\xe3\xda\xf5\xff\x42\x59\x87\x86"
+			  "\xee\x7b\xd6\xb4\x6a\x25\x44\xff",
+		.ptext	= "\x44\x67\x1e\x04\x53\xd2\x4b\xd9"
+			  "\x96\x33\x07\x54\xe4\x8e\x20",
+		.ctext	= "\xcc\x55\x40\x79\x47\x5c\x8b\xa6"
+			  "\xca\x7b\x9f\x50\xe3\x21\xea",
+		.klen	= 32,
+		.len	= 15,
+	},
+	{
+		.key	= "\xaf\xd9\x14\x14\xd5\xdb\xc9\xce"
+			  "\x76\x5c\x5a\xbf\x43\x05\x29\x24"
+			  "\xc4\x13\x68\xcc\xe8\x37\xbd\xb9"
+			  "\x41\x20\xf5\x53\x48\xd0\xa2\xd6",
+		.iv	= "\xa7\xb4\x00\x08\x79\x10\xae\xf5"
+			  "\x02\xbf\x85\xb2\x69\x4c\xc6\x04",
+		.ptext	= "\xac\x6a\xa8\x0c\xb0\x84\xbf\x4c"
+			  "\xae\x94\x20\x58\x7e\x00\x93\x89",
+		.ctext	= "\xd5\xaa\xe2\xe9\x86\x4c\x95\x4e"
+			  "\xde\xb6\x15\xcb\xdc\x1f\x13\x38",
+		.klen	= 32,
+		.len	= 16,
+	},
+	{
+		.key	= "\xed\xe3\x8b\xe7\x1c\x17\xbf\x4a"
+			  "\x02\xe2\xfc\x76\xac\xf5\x3c\x00"
+			  "\x5d\xdc\xfc\x83\xeb\x45\xb4\xcb"
+			  "\x59\x62\x60\xec\x69\x9c\x16\x45",
+		.iv	= "\xe4\x0e\x2b\x90\xd2\xfa\x94\x2e"
+			  "\x10\xe5\x64\x2b\x97\x28\x15\xc7",
+		.ptext	= "\xe6\x53\xff\x60\x0e\xc4\x51\xe4"
+			  "\x93\x4d\xe5\x55\xc5\xd9\xad\x48"
+			  "\x52",
+		.ctext	= "\xba\x25\x28\xf5\xcf\x31\x91\x80"
+			  "\xda\x2b\x95\x5f\x20\xcb\xfb\x9f"
+			  "\xc6",
+		.klen	= 32,
+		.len	= 17,
+	},
+	{
+		.key	= "\x77\x5c\xc0\x73\x9a\x64\x97\x91"
+			  "\x2f\xee\xe0\x20\xc2\x04\x59\x2e"
+			  "\x97\xd2\xa7\x70\xb3\xb0\x21\x6b"
+			  "\x8f\xbf\xb8\x51\xa8\xea\x0f\x62",
+		.iv	= "\x31\x8e\x1f\xcd\xfd\x23\xeb\x7f"
+			  "\x8a\x1f\x1b\x23\x53\x27\x44\xe5",
+		.ptext	= "\xcd\xff\x8c\x9b\x94\x5a\x51\x3f"
+			  "\x40\x93\x56\x93\x66\x39\x63\x1f"
+			  "\xbf\xe6\xa4\xfa\xbe\x79\x93\x03"
+			  "\xf5\x66\x74\x16\xfc\xe4\xce",
+		.ctext	= "\x8b\xd3\xc3\xce\x66\xf8\x66\x4c"
+			  "\xad\xd6\xf5\x0f\xd8\x99\x5a\x75"
+			  "\xa1\x3c\xab\x0b\x21\x36\x57\x72"
+			  "\x88\x29\xe9\xea\x4a\x8d\xe9",
+		.klen	= 32,
+		.len	= 31,
+	},
+	{
+		.key	= "\xa1\x2f\x4d\xde\xfe\xa1\xff\xa8"
+			  "\x73\xdd\xe3\xe2\x95\xfc\xea\x9c"
+			  "\xd0\x80\x42\x0c\xb8\x43\x3e\x99"
+			  "\x39\x38\x0a\x8c\xe8\x45\x3a\x7b",
+		.iv	= "\x32\xc4\x6f\xb1\x14\x43\xd1\x87"
+			  "\xe2\x6f\x5a\x58\x02\x36\x7e\x2a",
+		.ptext	= "\x9e\x5c\x1e\xf1\xd6\x7d\x09\x57"
+			  "\x18\x48\x55\xda\x7d\x44\xf9\x6d"
+			  "\xac\xcd\x59\xbb\x10\xa2\x94\x67"
+			  "\xd1\x6f\xfe\x6b\x4a\x11\xe8\x04"
+			  "\x09\x26\x4f\x8d\x5d\xa1\x7b\x42"
+			  "\xf9\x4b\x66\x76\x38\x12\xfe\xfe",
+		.ctext	= "\x42\xbc\xa7\x64\x15\x9a\x04\x71"
+			  "\x2c\x5f\x94\xba\x89\x3a\xad\xbc"
+			  "\x87\xb3\xf4\x09\x4f\x57\x06\x18"
+			  "\xdc\x84\x20\xf7\x64\x85\xca\x3b"
+			  "\xab\xe6\x33\x56\x34\x60\x5d\x4b"
+			  "\x2e\x16\x13\xd4\x77\xde\x2d\x2b",
+		.klen	= 32,
+		.len	= 48,
+	},
+	{
+		.key	= "\xfb\xf5\xb7\x3d\xa6\x95\x42\xbf"
+			  "\xd2\x94\x6c\x74\x0f\xbc\x5a\x28"
+			  "\x35\x3c\x51\x58\x84\xfb\x7d\x11"
+			  "\x16\x1e\x00\x97\x37\x08\xb7\x16",
+		.iv	= "\x9b\x53\x57\x40\xe6\xd9\xa7\x27"
+			  "\x78\xd4\x9b\xd2\x29\x1d\x24\xa9",
+		.ptext	= "\x8b\x02\x60\x0a\x3e\xb7\x10\x59"
+			  "\xc3\xac\xd5\x2a\x75\x81\xf2\xdb"
+			  "\x55\xca\x65\x86\x44\xfb\xfe\x91"
+			  "\x26\xbb\x45\xb2\x46\x22\x3e\x08"
+			  "\xa2\xbf\x46\xcb\x68\x7d\x45\x7b"
+			  "\xa1\x6a\x3c\x6e\x25\xeb\xed\x31"
+			  "\x7a\x8b\x47\xf9\xde\xec\x3d\x87"
+			  "\x09\x20\x2e\xfa\xba\x8b\x9b\xc5"
+			  "\x6c\x25\x9c\x9d\x2a\xe8\xab\x90"
+			  "\x3f\x86\xee\x61\x13\x21\xd4\xde"
+			  "\xe1\x0c\x95\xfc\x5c\x8a\x6e\x0a"
+			  "\x73\xcf\x08\x69\x44\x4e\xde\x25"
+			  "\xaf\xaa\x56\x04\xc4\xb3\x60\x44"
+			  "\x3b\x8b\x3d\xee\xae\x42\x4b\xd2"
+			  "\x9a\x6c\xa0\x8e\x52\x06\xb2\xd1"
+			  "\x5d\x38\x30\x6d\x27\x9b\x1a\xd8",
+		.ctext	= "\xa3\x78\x33\x78\x95\x95\x97\x07"
+			  "\x53\xa3\xa1\x5b\x18\x32\x27\xf7"
+			  "\x09\x12\x53\x70\x83\xb5\x6a\x9f"
+			  "\x26\x6d\x10\x0d\xe0\x1c\xe6\x2b"
+			  "\x70\x00\xdc\xa1\x60\xef\x1b\xee"
+			  "\xc5\xa5\x51\x17\xae\xcc\xf2\xed"
+			  "\xc4\x60\x07\xdf\xd5\x7a\xe9\x90"
+			  "\x3c\x9f\x96\x5d\x72\x65\x5d\xef"
+			  "\xd0\x94\x32\xc4\x85\x90\x78\xa1"
+			  "\x2e\x64\xf6\xee\x8e\x74\x3f\x20"
+			  "\x2f\x12\x3b\x3d\xd5\x39\x8e\x5a"
+			  "\xf9\x8f\xce\x94\x5d\x82\x18\x66"
+			  "\x14\xaf\x4c\xfe\xe0\x91\xc3\x4a"
+			  "\x85\xcf\xe7\xe8\xf7\xcb\xf0\x31"
+			  "\x88\x7d\xc9\x5b\x71\x9d\x5f\xd2"
+			  "\xfa\xed\xa6\x24\xda\xbb\xb1\x84",
+		.klen	= 32,
+		.len	= 128,
+	},
+	{
+		.key	= "\x32\x37\x2b\x8f\x7b\xb1\x23\x79"
+			  "\x05\x52\xde\x05\xf1\x68\x3f\x6c"
+			  "\xa4\xae\xbc\x21\xc2\xc6\xf0\xbd"
+			  "\x0f\x20\xb7\xa4\xc5\x05\x7b\x64",
+		.iv	= "\xff\x26\x4e\x67\x48\xdd\xcf\xfe"
+			  "\x42\x09\x04\x98\x5f\x1e\xfa\x80",
+		.ptext	= "\x99\xdc\x3b\x19\x41\xf9\xff\x6e"
+			  "\x76\xb5\x03\xfa\x61\xed\xf8\x44"
+			  "\x70\xb9\xf0\x83\x80\x6e\x31\x77"
+			  "\x77\xe4\xc7\xb4\x77\x02\xab\x91"
+			  "\x82\xc6\xf8\x7c\x46\x61\x03\x69"
+			  "\x09\xa0\xf7\x12\xb7\x81\x6c\xa9"
+			  "\x10\x5c\xbb\x55\xb3\x44\xed\xb5"
+			  "\xa2\x52\x48\x71\x90\x5d\xda\x40"
+			  "\x0b\x7f\x4a\x11\x6d\xa7\x3d\x8e"
+			  "\x1b\xcd\x9d\x4e\x75\x8b\x7d\x87"
+			  "\xe5\x39\x34\x32\x1e\xe6\x8d\x51"
+			  "\xd4\x1f\xe3\x1d\x50\xa0\x22\x37"
+			  "\x7c\xb0\xd9\xfb\xb6\xb2\x16\xf6"
+			  "\x6d\x26\xa0\x4e\x8c\x6a\xe6\xb6"
+			  "\xbe\x4c\x7c\xe3\x88\x10\x18\x90"
+			  "\x11\x50\x19\x90\xe7\x19\x3f\xd0"
+			  "\x31\x15\x0f\x06\x96\xfe\xa7\x7b"
+			  "\xc3\x32\x88\x69\xa4\x12\xe3\x64"
+			  "\x02\x30\x17\x74\x6c\x88\x7c\x9b"
+			  "\xd6\x6d\x75\xdf\x11\x86\x70\x79"
+			  "\x48\x7d\x34\x3e\x33\x58\x07\x8b"
+			  "\xd2\x50\xac\x35\x15\x45\x05\xb4"
+			  "\x4d\x31\x97\x19\x87\x23\x4b\x87"
+			  "\x53\xdc\xa9\x19\x78\xf1\xbf\x35"
+			  "\x30\x04\x14\xd4\xcf\xb2\x8c\x87"
+			  "\x7d\xdb\x69\xc9\xcd\xfe\x40\x3e"
+			  "\x8d\x66\x5b\x61\xe5\xf0\x2d\x87"
+			  "\x93\x3a\x0c\x2b\x04\x98\x05\xc2"
+			  "\x56\x4d\xc4\x6c\xcd\x7a\x98\x7e"
+			  "\xe2\x2d\x79\x07\x91\x9f\xdf\x2f"
+			  "\x72\xc9\x8f\xcb\x0b\x87\x1b\xb7"
+			  "\x04\x86\xcb\x47\xfa\x5d\x03",
+		.ctext	= "\x0b\x00\xf7\xf2\xc8\x6a\xba\x9a"
+			  "\x0a\x97\x18\x7a\x00\xa0\xdb\xf4"
+			  "\x5e\x8e\x4a\xb7\xe0\x51\xf1\x75"
+			  "\x17\x8b\xb4\xf1\x56\x11\x05\x9f"
+			  "\x2f\x2e\xba\x67\x04\xe1\xb4\xa5"
+			  "\xfc\x7c\x8c\xad\xc6\xb9\xd1\x64"
+			  "\xca\xbd\x5d\xaf\xdb\x65\x48\x4f"
+			  "\x1b\xb3\x94\x5c\x0b\xd0\xee\xcd"
+			  "\xb5\x7f\x43\x8a\xd8\x8b\x66\xde"
+			  "\xd2\x9c\x13\x65\xa4\x47\xa7\x03"
+			  "\xc5\xa1\x46\x8f\x2f\x84\xbc\xef"
+			  "\x48\x9d\x9d\xb5\xbd\x43\xff\xd2"
+			  "\xd2\x7a\x5a\x13\xbf\xb4\xf6\x05"
+			  "\x17\xcd\x01\x12\xf0\x35\x27\x96"
+			  "\xf4\xc1\x65\xf7\x69\xef\x64\x1b"
+			  "\x6e\x4a\xe8\x77\xce\x83\x01\xb7"
+			  "\x60\xe6\x45\x2a\xcd\x41\x4a\xb5"
+			  "\x8e\xcc\x45\x93\xf1\xd6\x64\x5f"
+			  "\x32\x60\xe4\x29\x4a\x82\x6c\x86"
+			  "\x16\xe4\xcc\xdb\x5f\xc8\x11\xa6"
+			  "\xfe\x88\xd6\xc3\xe5\x5c\xbb\x67"
+			  "\xec\xa5\x7b\xf5\xa8\x4f\x77\x25"
+			  "\x5d\x0c\x2a\x99\xf9\xb9\xd1\xae"
+			  "\x3c\x83\x2a\x93\x9b\x66\xec\x68"
+			  "\x2c\x93\x02\x8a\x8a\x1e\x2f\x50"
+			  "\x09\x37\x19\x5c\x2a\x3a\xc2\xcb"
+			  "\xcb\x89\x82\x81\xb7\xbb\xef\x73"
+			  "\x8b\xc9\xae\x42\x96\xef\x70\xc0"
+			  "\x89\xc7\x3e\x6a\x26\xc3\xe4\x39"
+			  "\x53\xa9\xcf\x63\x7d\x05\xf3\xff"
+			  "\x52\x04\xf6\x7f\x23\x96\xe9\xf7"
+			  "\xff\xd6\x50\xa3\x0e\x20\x71",
+		.klen	= 32,
+		.len	= 255,
+	},
+	{
+		.key	= "\x39\x5f\xf4\x9c\x90\x3a\x9a\x25"
+			  "\x15\x11\x79\x39\xed\x26\x5e\xf6"
+			  "\xda\xcf\x33\x4f\x82\x97\xab\x10"
+			  "\xc1\x55\x48\x82\x80\xa8\x02\xb2",
+		.iv	= "\x82\x60\xd9\x06\xeb\x40\x99\x76"
+			  "\x08\xc5\xa4\x83\x45\xb8\x38\x5a",
+		.ptext	= "\xa1\xa8\xac\xac\x08\xaf\x8f\x84"
+			  "\xbf\xcc\x79\x31\x5e\x61\x01\xd1"
+			  "\x4d\x5f\x9b\xcd\x91\x92\x9a\xa1"
+			  "\x99\x0d\x49\xb2\xd7\xfd\x25\x93"
+			  "\x51\x96\xbd\x91\x8b\x08\xf1\xc6"
+			  "\x0d\x17\xf6\xef\xfd\xd2\x78\x16"
+			  "\xc8\x08\x27\x7b\xca\x98\xc6\x12"
+			  "\x86\x11\xdb\xd5\x08\x3d\x5a\x2c"
+			  "\xcf\x15\x0e\x9b\x42\x78\xeb\x1f"
+			  "\x52\xbc\xd7\x5a\x8a\x33\x6c\x14"
+			  "\xfc\x61\xad\x2e\x1e\x03\x66\xea"
+			  "\x79\x0e\x88\x88\xde\x93\xe3\x81"
+			  "\xb5\xc4\x1c\xe6\x9c\x08\x18\x8e"
+			  "\xa0\x87\xda\xe6\xf8\xcb\x30\x44"
+			  "\x2d\x4e\xc0\xa3\x60\xf9\x62\x7b"
+			  "\x4b\xd5\x61\x6d\xe2\x67\x95\x54"
+			  "\x10\xd1\xca\x22\xe8\xb6\xb1\x3a"
+			  "\x2d\xd7\x35\x5b\x22\x88\x55\x67"
+			  "\x3d\x83\x8f\x07\x98\xa8\xf2\xcf"
+			  "\x04\xb7\x9e\x52\xca\xe0\x98\x72"
+			  "\x5c\xc1\x00\xd4\x1f\x2c\x61\xf3"
+			  "\xe8\x40\xaf\x4a\xee\x66\x41\xa0"
+			  "\x02\x77\x29\x30\x65\x59\x4b\x20"
+			  "\x7b\x0d\x80\x97\x27\x7f\xd5\x90"
+			  "\xbb\x9d\x76\x90\xe5\x43\x43\x72"
+			  "\xd0\xd4\x14\x75\x66\xb3\xb6\xaf"
+			  "\x09\xe4\x23\xb0\x62\xad\x17\x28"
+			  "\x39\x26\xab\xf5\xf7\x5c\xb6\x33"
+			  "\xbd\x27\x09\x5b\x29\xe4\x40\x0b"
+			  "\xc1\x26\x32\xdb\x9a\xdf\xf9\x5a"
+			  "\xae\x03\x2c\xa4\x40\x84\x9a\xb7"
+			  "\x4e\x47\xa8\x0f\x23\xc7\xbb\xcf"
+			  "\x2b\xf2\x32\x6c\x35\x6a\x91\xba"
+			  "\x0e\xea\xa2\x8b\x2f\xbd\xb5\xea"
+			  "\x6e\xbc\xb5\x4b\x03\xb3\x86\xe0"
+			  "\x86\xcf\xba\xcb\x38\x2c\x32\xa6"
+			  "\x6d\xe5\x28\xa6\xad\xd2\x7f\x73"
+			  "\x43\x14\xf8\xb1\x99\x12\x2d\x2b"
+			  "\xdf\xcd\xf2\x81\x43\x94\xdf\xb1"
+			  "\x17\xc9\x33\xa6\x3d\xef\x96\xb8"
+			  "\xd6\x0d\x00\xec\x49\x66\x85\x5d"
+			  "\x44\x62\x12\x04\x55\x5c\x48\xd3"
+			  "\xbd\x73\xac\x54\x8f\xbf\x97\x8e"
+			  "\x85\xfd\xc2\xa1\x25\x32\x38\x6a"
+			  "\x1f\xac\x57\x3c\x4f\x56\x73\xf2"
+			  "\x1d\xb6\x48\x68\xc7\x0c\xe7\x60"
+			  "\xd2\x8e\x4d\xfb\xc7\x20\x7b\xb7"
+			  "\x45\x28\x12\xc6\x26\xae\xea\x7c"
+			  "\x5d\xe2\x46\xb5\xae\xe1\xc3\x98"
+			  "\x6f\x72\xd5\xa2\xfd\xed\x40\xfd"
+			  "\xf9\xdf\x61\xec\x45\x2c\x15\xe0"
+			  "\x1e\xbb\xde\x71\x37\x5f\x73\xc2"
+			  "\x11\xcc\x6e\x6d\xe1\xb5\x1b\xd2"
+			  "\x2a\xdd\x19\x8a\xc2\xe1\xa0\xa4"
+			  "\x26\xeb\xb2\x2c\x4f\x77\x52\xf1"
+			  "\x42\x72\x6c\xad\xd7\x78\x5d\x72"
+			  "\xc9\x16\x26\x25\x1b\x4c\xe6\x58"
+			  "\x79\x57\xb5\x06\x15\x4f\xe5\xba"
+			  "\xa2\x7f\x2d\x5b\x87\x8a\x44\x70"
+			  "\xec\xc7\xef\x84\xae\x60\xa2\x61"
+			  "\x86\xe9\x18\xcd\x28\xc4\xa4\xf5"
+			  "\xbc\x84\xb8\x86\xa0\xba\xf1\xf1"
+			  "\x08\x3b\x32\x75\x35\x22\x7a\x65"
+			  "\xca\x48\xe8\xef\x6e\xe2\x8e\x00",
+		.ctext	= "\x2f\xae\xd8\x67\xeb\x15\xde\x75"
+			  "\x53\xa3\x0e\x5a\xcf\x1c\xbe\xea"
+			  "\xde\xf9\xcf\xc2\x9f\xfd\x0f\x44"
+			  "\xc0\xe0\x7a\x76\x1d\xcb\x4a\xf8"
+			  "\x35\xd6\xe3\x95\x98\x6b\x3f\x89"
+			  "\xc4\xe6\xb6\x6f\xe1\x8b\x39\x4b"
+			  "\x1c\x6c\x77\xe4\xe1\x8a\xbc\x61"
+			  "\x00\x6a\xb1\x37\x2f\x45\xe6\x04"
+			  "\x52\x0b\xfc\x1e\x32\xc1\xd8\x9d"
+			  "\xfa\xdd\x67\x5c\xe0\x75\x83\xd0"
+			  "\x21\x9e\x02\xea\xc0\x7f\xc0\x29"
+			  "\xb3\x6c\xa5\x97\xb3\x29\x82\x1a"
+			  "\x94\xa5\xb4\xb6\x49\xe5\xa5\xad"
+			  "\x95\x40\x52\x7c\x84\x88\xa4\xa8"
+			  "\x26\xe4\xd9\x5d\x41\xf2\x93\x7b"
+			  "\xa4\x48\x1b\x66\x91\xb9\x7c\xc2"
+			  "\x99\x29\xdf\xd8\x30\xac\xd4\x47"
+			  "\x42\xa0\x14\x87\x67\xb8\xfd\x0b"
+			  "\x1e\xcb\x5e\x5c\x9a\xc2\x04\x8b"
+			  "\x17\x29\x9d\x99\x7f\x86\x4c\xe2"
+			  "\x5c\x96\xa6\x0f\xb6\x47\x33\x5c"
+			  "\xe4\x50\x49\xd5\x4f\x92\x0b\x9a"
+			  "\xbc\x52\x4c\x41\xf5\xc9\x3e\x76"
+			  "\x55\x55\xd4\xdc\x71\x14\x23\xfc"
+			  "\x5f\xd5\x08\xde\xa0\xf7\x28\xc0"
+			  "\xe1\x61\xac\x64\x66\xf6\xd1\x31"
+			  "\xe4\xa4\xa9\xed\xbc\xad\x4f\x3b"
+			  "\x59\xb9\x48\x1b\xe7\xb1\x6f\xc6"
+			  "\xba\x40\x1c\x0b\xe7\x2f\x31\x65"
+			  "\x85\xf5\xe9\x14\x0a\x31\xf5\xf3"
+			  "\xc0\x1c\x20\x35\x73\x38\x0f\x8e"
+			  "\x39\xf0\x68\xae\x08\x9c\x87\x4b"
+			  "\x42\xfc\x22\x17\xee\x96\x51\x2a"
+			  "\xd8\x57\x5a\x35\xea\x72\x74\xfc"
+			  "\xb3\x0e\x69\x9a\xe1\x4f\x24\x90"
+			  "\xc5\x4b\xe5\xd7\xe3\x82\x2f\xc5"
+			  "\x62\x46\x3e\xab\x72\x4e\xe0\xf3"
+			  "\x90\x09\x4c\xb2\xe1\xe8\xa0\xf5"
+			  "\x46\x40\x2b\x47\x85\x3c\x21\x90"
+			  "\x3d\xad\x25\x5a\x36\xdf\xe5\xbc"
+			  "\x7e\x80\x4d\x53\x77\xf1\x79\xa6"
+			  "\xec\x22\x80\x88\x68\xd6\x2d\x8b"
+			  "\x3e\xf7\x52\xc7\x2a\x20\x42\x5c"
+			  "\xed\x99\x4f\x32\x80\x00\x7e\x73"
+			  "\xd7\x6d\x7f\x7d\x42\x54\x4a\xfe"
+			  "\xff\x6f\x61\xca\x2a\xbb\x4f\xeb"
+			  "\x4f\xe4\x4e\xaf\x2c\x4f\x82\xcd"
+			  "\xa1\xa7\x11\xb3\x34\x33\xcf\x32"
+			  "\x63\x0e\x24\x3a\x35\xbe\x06\xd5"
+			  "\x17\xcb\x02\x30\x33\x6e\x8c\x49"
+			  "\x40\x6e\x34\x8c\x07\xd4\x3e\xe6"
+			  "\xaf\x78\x6d\x8c\x10\x5f\x21\x58"
+			  "\x49\x26\xc5\xaf\x0d\x7d\xd4\xaf"
+			  "\xcd\x5b\xa1\xe3\xf6\x39\x1c\x9b"
+			  "\x8e\x00\xa1\xa7\x9e\x17\x4a\xc0"
+			  "\x54\x56\x9e\xcf\xcf\x88\x79\x8d"
+			  "\x50\xf7\x56\x8e\x0a\x73\x46\x6b"
+			  "\xc3\xb9\x9b\x6c\x7d\xc4\xc8\xb6"
+			  "\x03\x5f\x30\x62\x7d\xe6\xdb\x15"
+			  "\xe1\x39\x02\x8c\xff\xda\xc8\x43"
+			  "\xf2\xa9\xbf\x00\xe7\x3a\x61\x89"
+			  "\xdf\xb0\xca\x7d\x8c\x8a\x6a\x9f"
+			  "\x18\x89\x3d\x39\xac\x36\x6f\x05"
+			  "\x1f\xb5\xda\x00\xea\xe1\x51\x21",
+		.klen	= 32,
+		.len	= 512,
+	},
 
-static const struct hash_testvec blakes2s_160_tv_template[] = {{
-	.plaintext = blake2_ordered_sequence,
-	.psize = 7,
-	.digest = (u8[]){ 0xb4, 0xf2, 0x03, 0x49, 0x37, 0xed, 0xb1, 0x3e,
-			  0x5b, 0x2a, 0xca, 0x64, 0x82, 0x74, 0xf6, 0x62,
-			  0xe3, 0xf2, 0x84, 0xff, },
-}, {
-	.plaintext = blake2_ordered_sequence,
-	.psize = 256,
-	.digest = (u8[]){ 0xaa, 0x56, 0x9b, 0xdc, 0x98, 0x17, 0x75, 0xf2,
-			  0xb3, 0x68, 0x83, 0xb7, 0x9b, 0x8d, 0x48, 0xb1,
-			  0x9b, 0x2d, 0x35, 0x05, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.digest = (u8[]){ 0x50, 0x16, 0xe7, 0x0c, 0x01, 0xd0, 0xd3, 0xc3,
-			  0xf4, 0x3e, 0xb1, 0x6e, 0x97, 0xa9, 0x4e, 0xd1,
-			  0x79, 0x65, 0x32, 0x93, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 1,
-	.digest = (u8[]){ 0x1c, 0x2b, 0xcd, 0x9a, 0x68, 0xca, 0x8c, 0x71,
-			  0x90, 0x29, 0x6c, 0x54, 0xfa, 0x56, 0x4a, 0xef,
-			  0xa2, 0x3a, 0x56, 0x9c, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 15,
-	.digest = (u8[]){ 0x36, 0xc3, 0x5f, 0x9a, 0xdc, 0x7e, 0xbf, 0x19,
-			  0x68, 0xaa, 0xca, 0xd8, 0x81, 0xbf, 0x09, 0x34,
-			  0x83, 0x39, 0x0f, 0x30, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 64,
-	.digest = (u8[]){ 0x86, 0x80, 0x78, 0xa4, 0x14, 0xec, 0x03, 0xe5,
-			  0xb6, 0x9a, 0x52, 0x0e, 0x42, 0xee, 0x39, 0x9d,
-			  0xac, 0xa6, 0x81, 0x63, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 247,
-	.digest = (u8[]){ 0x2d, 0xd8, 0xd2, 0x53, 0x66, 0xfa, 0xa9, 0x01,
-			  0x1c, 0x9c, 0xaf, 0xa3, 0xe2, 0x9d, 0x9b, 0x10,
-			  0x0a, 0xf6, 0x73, 0xe8, },
-}};
+};
 
-static const struct hash_testvec blakes2s_224_tv_template[] = {{
-	.plaintext = blake2_ordered_sequence,
-	.psize = 1,
-	.digest = (u8[]){ 0x61, 0xb9, 0x4e, 0xc9, 0x46, 0x22, 0xa3, 0x91,
-			  0xd2, 0xae, 0x42, 0xe6, 0x45, 0x6c, 0x90, 0x12,
-			  0xd5, 0x80, 0x07, 0x97, 0xb8, 0x86, 0x5a, 0xfc,
-			  0x48, 0x21, 0x97, 0xbb, },
-}, {
-	.plaintext = blake2_ordered_sequence,
-	.psize = 247,
-	.digest = (u8[]){ 0x9e, 0xda, 0xc7, 0x20, 0x2c, 0xd8, 0x48, 0x2e,
-			  0x31, 0x94, 0xab, 0x46, 0x6d, 0x94, 0xd8, 0xb4,
-			  0x69, 0xcd, 0xae, 0x19, 0x6d, 0x9e, 0x41, 0xcc,
-			  0x2b, 0xa4, 0xd5, 0xf6, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.digest = (u8[]){ 0x32, 0xc0, 0xac, 0xf4, 0x3b, 0xd3, 0x07, 0x9f,
-			  0xbe, 0xfb, 0xfa, 0x4d, 0x6b, 0x4e, 0x56, 0xb3,
-			  0xaa, 0xd3, 0x27, 0xf6, 0x14, 0xbf, 0xb9, 0x32,
-			  0xa7, 0x19, 0xfc, 0xb8, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 7,
-	.digest = (u8[]){ 0x73, 0xad, 0x5e, 0x6d, 0xb9, 0x02, 0x8e, 0x76,
-			  0xf2, 0x66, 0x42, 0x4b, 0x4c, 0xfa, 0x1f, 0xe6,
-			  0x2e, 0x56, 0x40, 0xe5, 0xa2, 0xb0, 0x3c, 0xe8,
-			  0x7b, 0x45, 0xfe, 0x05, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 15,
-	.digest = (u8[]){ 0x16, 0x60, 0xfb, 0x92, 0x54, 0xb3, 0x6e, 0x36,
-			  0x81, 0xf4, 0x16, 0x41, 0xc3, 0x3d, 0xd3, 0x43,
-			  0x84, 0xed, 0x10, 0x6f, 0x65, 0x80, 0x7a, 0x3e,
-			  0x25, 0xab, 0xc5, 0x02, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 64,
-	.digest = (u8[]){ 0xca, 0xaa, 0x39, 0x67, 0x9c, 0xf7, 0x6b, 0xc7,
-			  0xb6, 0x82, 0xca, 0x0e, 0x65, 0x36, 0x5b, 0x7c,
-			  0x24, 0x00, 0xfa, 0x5f, 0xda, 0x06, 0x91, 0x93,
-			  0x6a, 0x31, 0x83, 0xb5, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 256,
-	.digest = (u8[]){ 0x90, 0x02, 0x26, 0xb5, 0x06, 0x9c, 0x36, 0x86,
-			  0x94, 0x91, 0x90, 0x1e, 0x7d, 0x2a, 0x71, 0xb2,
-			  0x48, 0xb5, 0xe8, 0x16, 0xfd, 0x64, 0x33, 0x45,
-			  0xb3, 0xd7, 0xec, 0xcc, },
-}};
+/*
+ * Test vectors generated using https://github.com/google/hctr2
+ *
+ * To ensure compatibility with RFC 8452, some tests were sourced from
+ * https://datatracker.ietf.org/doc/html/rfc8452
+ */
+static const struct hash_testvec polyval_tv_template[] = {
+	{ // From RFC 8452
+		.key	= "\x31\x07\x28\xd9\x91\x1f\x1f\x38"
+			  "\x37\xb2\x43\x16\xc3\xfa\xb9\xa0",
+		.plaintext	= "\x65\x78\x61\x6d\x70\x6c\x65\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"
+			  "\x72\x6c\x64\x00\x00\x00\x00\x00"
+			  "\x38\x00\x00\x00\x00\x00\x00\x00"
+			  "\x58\x00\x00\x00\x00\x00\x00\x00",
+		.digest	= "\xad\x7f\xcf\x0b\x51\x69\x85\x16"
+			  "\x62\x67\x2f\x3c\x5f\x95\x13\x8f",
+		.psize	= 48,
+		.ksize	= 16,
+	},
+	{ // From RFC 8452
+		.key	= "\xd9\xb3\x60\x27\x96\x94\x94\x1a"
+			  "\xc5\xdb\xc6\x98\x7a\xda\x73\x77",
+		.plaintext	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+		.digest	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+		.psize	= 16,
+		.ksize	= 16,
+	},
+	{ // From RFC 8452
+		.key	= "\xd9\xb3\x60\x27\x96\x94\x94\x1a"
+			  "\xc5\xdb\xc6\x98\x7a\xda\x73\x77",
+		.plaintext	= "\x01\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x40\x00\x00\x00\x00\x00\x00\x00",
+		.digest	= "\xeb\x93\xb7\x74\x09\x62\xc5\xe4"
+			  "\x9d\x2a\x90\xa7\xdc\x5c\xec\x74",
+		.psize	= 32,
+		.ksize	= 16,
+	},
+	{ // From RFC 8452
+		.key	= "\xd9\xb3\x60\x27\x96\x94\x94\x1a"
+			  "\xc5\xdb\xc6\x98\x7a\xda\x73\x77",
+		.plaintext	= "\x01\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x02\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x03\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x80\x01\x00\x00\x00\x00\x00\x00",
+		.digest	= "\x81\x38\x87\x46\xbc\x22\xd2\x6b"
+			  "\x2a\xbc\x3d\xcb\x15\x75\x42\x22",
+		.psize	= 64,
+		.ksize	= 16,
+	},
+	{ // From RFC 8452
+		.key	= "\xd9\xb3\x60\x27\x96\x94\x94\x1a"
+			  "\xc5\xdb\xc6\x98\x7a\xda\x73\x77",
+		.plaintext	= "\x01\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x02\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x03\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x04\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x02\x00\x00\x00\x00\x00\x00",
+		.digest	= "\x1e\x39\xb6\xd3\x34\x4d\x34\x8f"
+			  "\x60\x44\xf8\x99\x35\xd1\xcf\x78",
+		.psize	= 80,
+		.ksize	= 16,
+	},
+	{ // From RFC 8452
+		.key	= "\xd9\xb3\x60\x27\x96\x94\x94\x1a"
+			  "\xc5\xdb\xc6\x98\x7a\xda\x73\x77",
+		.plaintext	= "\x01\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x02\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x03\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x04\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x05\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x08\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x02\x00\x00\x00\x00\x00\x00",
+		.digest	= "\xff\xcd\x05\xd5\x77\x0f\x34\xad"
+			  "\x92\x67\xf0\xa5\x99\x94\xb1\x5a",
+		.psize	= 96,
+		.ksize	= 16,
+	},
+	{ // Random ( 1)
+		.key	= "\x90\xcc\xac\xee\xba\xd7\xd4\x68"
+			  "\x98\xa6\x79\x70\xdf\x66\x15\x6c",
+		.plaintext	= "",
+		.digest	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+		.psize	= 0,
+		.ksize	= 16,
+	},
+	{ // Random ( 1)
+		.key	= "\xc1\x45\x71\xf0\x30\x07\x94\xe7"
+			  "\x3a\xdd\xe4\xc6\x19\x2d\x02\xa2",
+		.plaintext	= "\xc1\x5d\x47\xc7\x4c\x7c\x5e\x07"
+			  "\x85\x14\x8f\x79\xcc\x73\x83\xf7"
+			  "\x35\xb8\xcb\x73\x61\xf0\x53\x31"
+			  "\xbf\x84\xde\xb6\xde\xaf\xb0\xb8"
+			  "\xb7\xd9\x11\x91\x89\xfd\x1e\x4c"
+			  "\x84\x4a\x1f\x2a\x87\xa4\xaf\x62"
+			  "\x8d\x7d\x58\xf6\x43\x35\xfc\x53"
+			  "\x8f\x1a\xf6\x12\xe1\x13\x3f\x66"
+			  "\x91\x4b\x13\xd6\x45\xfb\xb0\x7a"
+			  "\xe0\x8b\x8e\x99\xf7\x86\x46\x37"
+			  "\xd1\x22\x9e\x52\xf3\x3f\xd9\x75"
+			  "\x2c\x2c\xc6\xbb\x0e\x08\x14\x29"
+			  "\xe8\x50\x2f\xd8\xbe\xf4\xe9\x69"
+			  "\x4a\xee\xf7\xae\x15\x65\x35\x1e",
+		.digest	= "\x00\x4f\x5d\xe9\x3b\xc0\xd6\x50"
+			  "\x3e\x38\x73\x86\xc6\xda\xca\x7f",
+		.psize	= 112,
+		.ksize	= 16,
+	},
+	{ // Random ( 1)
+		.key	= "\x37\xbe\x68\x16\x50\xb9\x4e\xb0"
+			  "\x47\xde\xe2\xbd\xde\xe4\x48\x09",
+		.plaintext	= "\x87\xfc\x68\x9f\xff\xf2\x4a\x1e"
+			  "\x82\x3b\x73\x8f\xc1\xb2\x1b\x7a"
+			  "\x6c\x4f\x81\xbc\x88\x9b\x6c\xa3"
+			  "\x9c\xc2\xa5\xbc\x14\x70\x4c\x9b"
+			  "\x0c\x9f\x59\x92\x16\x4b\x91\x3d"
+			  "\x18\x55\x22\x68\x12\x8c\x63\xb2"
+			  "\x51\xcb\x85\x4b\xd2\xae\x0b\x1c"
+			  "\x5d\x28\x9d\x1d\xb1\xc8\xf0\x77"
+			  "\xe9\xb5\x07\x4e\x06\xc8\xee\xf8"
+			  "\x1b\xed\x72\x2a\x55\x7d\x16\xc9"
+			  "\xf2\x54\xe7\xe9\xe0\x44\x5b\x33"
+			  "\xb1\x49\xee\xff\x43\xfb\x82\xcd"
+			  "\x4a\x70\x78\x81\xa4\x34\x36\xe8"
+			  "\x4c\x28\x54\xa6\x6c\xc3\x6b\x78"
+			  "\xe7\xc0\x5d\xc6\x5d\x81\xab\x70"
+			  "\x08\x86\xa1\xfd\xf4\x77\x55\xfd"
+			  "\xa3\xe9\xe2\x1b\xdf\x99\xb7\x80"
+			  "\xf9\x0a\x4f\x72\x4a\xd3\xaf\xbb"
+			  "\xb3\x3b\xeb\x08\x58\x0f\x79\xce"
+			  "\xa5\x99\x05\x12\x34\xd4\xf4\x86"
+			  "\x37\x23\x1d\xc8\x49\xc0\x92\xae"
+			  "\xa6\xac\x9b\x31\x55\xed\x15\xc6"
+			  "\x05\x17\x37\x8d\x90\x42\xe4\x87"
+			  "\x89\x62\x88\x69\x1c\x6a\xfd\xe3"
+			  "\x00\x2b\x47\x1a\x73\xc1\x51\xc2"
+			  "\xc0\x62\x74\x6a\x9e\xb2\xe5\x21"
+			  "\xbe\x90\xb5\xb0\x50\xca\x88\x68"
+			  "\xe1\x9d\x7a\xdf\x6c\xb7\xb9\x98"
+			  "\xee\x28\x62\x61\x8b\xd1\x47\xf9"
+			  "\x04\x7a\x0b\x5d\xcd\x2b\x65\xf5"
+			  "\x12\xa3\xfe\x1a\xaa\x2c\x78\x42"
+			  "\xb8\xbe\x7d\x74\xeb\x59\xba\xba",
+		.digest	= "\xae\x11\xd4\x60\x2a\x5f\x9e\x42"
+			  "\x89\x04\xc2\x34\x8d\x55\x94\x0a",
+		.psize	= 256,
+		.ksize	= 16,
+	},
 
-static const struct hash_testvec blakes2s_256_tv_template[] = {{
-	.plaintext = blake2_ordered_sequence,
-	.psize = 15,
-	.digest = (u8[]){ 0xd9, 0x7c, 0x82, 0x8d, 0x81, 0x82, 0xa7, 0x21,
-			  0x80, 0xa0, 0x6a, 0x78, 0x26, 0x83, 0x30, 0x67,
-			  0x3f, 0x7c, 0x4e, 0x06, 0x35, 0x94, 0x7c, 0x04,
-			  0xc0, 0x23, 0x23, 0xfd, 0x45, 0xc0, 0xa5, 0x2d, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.digest = (u8[]){ 0x48, 0xa8, 0x99, 0x7d, 0xa4, 0x07, 0x87, 0x6b,
-			  0x3d, 0x79, 0xc0, 0xd9, 0x23, 0x25, 0xad, 0x3b,
-			  0x89, 0xcb, 0xb7, 0x54, 0xd8, 0x6a, 0xb7, 0x1a,
-			  0xee, 0x04, 0x7a, 0xd3, 0x45, 0xfd, 0x2c, 0x49, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 1,
-	.digest = (u8[]){ 0x22, 0x27, 0xae, 0xaa, 0x6e, 0x81, 0x56, 0x03,
-			  0xa7, 0xe3, 0xa1, 0x18, 0xa5, 0x9a, 0x2c, 0x18,
-			  0xf4, 0x63, 0xbc, 0x16, 0x70, 0xf1, 0xe7, 0x4b,
-			  0x00, 0x6d, 0x66, 0x16, 0xae, 0x9e, 0x74, 0x4e, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 7,
-	.digest = (u8[]){ 0x58, 0x5d, 0xa8, 0x60, 0x1c, 0xa4, 0xd8, 0x03,
-			  0x86, 0x86, 0x84, 0x64, 0xd7, 0xa0, 0x8e, 0x15,
-			  0x2f, 0x05, 0xa2, 0x1b, 0xbc, 0xef, 0x7a, 0x34,
-			  0xb3, 0xc5, 0xbc, 0x4b, 0xf0, 0x32, 0xeb, 0x12, },
-}, {
-	.ksize = 32,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 64,
-	.digest = (u8[]){ 0x89, 0x75, 0xb0, 0x57, 0x7f, 0xd3, 0x55, 0x66,
-			  0xd7, 0x50, 0xb3, 0x62, 0xb0, 0x89, 0x7a, 0x26,
-			  0xc3, 0x99, 0x13, 0x6d, 0xf0, 0x7b, 0xab, 0xab,
-			  0xbd, 0xe6, 0x20, 0x3f, 0xf2, 0x95, 0x4e, 0xd4, },
-}, {
-	.ksize = 1,
-	.key = "B",
-	.plaintext = blake2_ordered_sequence,
-	.psize = 247,
-	.digest = (u8[]){ 0x2e, 0x74, 0x1c, 0x1d, 0x03, 0xf4, 0x9d, 0x84,
-			  0x6f, 0xfc, 0x86, 0x32, 0x92, 0x49, 0x7e, 0x66,
-			  0xd7, 0xc3, 0x10, 0x88, 0xfe, 0x28, 0xb3, 0xe0,
-			  0xbf, 0x50, 0x75, 0xad, 0x8e, 0xa4, 0xe6, 0xb2, },
-}, {
-	.ksize = 16,
-	.key = blake2_ordered_sequence,
-	.plaintext = blake2_ordered_sequence,
-	.psize = 256,
-	.digest = (u8[]){ 0xb9, 0xd2, 0x81, 0x0e, 0x3a, 0xb1, 0x62, 0x9b,
-			  0xad, 0x44, 0x05, 0xf4, 0x92, 0x2e, 0x99, 0xc1,
-			  0x4a, 0x47, 0xbb, 0x5b, 0x6f, 0xb2, 0x96, 0xed,
-			  0xd5, 0x06, 0xb5, 0x3a, 0x7c, 0x7a, 0x65, 0x1d, },
-}};
+};
+
+/*
+ * Test vectors generated using https://github.com/google/hctr2
+ */
+static const struct cipher_testvec aes_hctr2_tv_template[] = {
+	{
+		.key	= "\xe1\x15\x66\x3c\x8d\xc6\x3a\xff"
+			  "\xef\x41\xd7\x47\xa2\xcc\x8a\xba",
+		.iv	= "\xc3\xbe\x2a\xcb\xb5\x39\x86\xf1"
+			  "\x91\xad\x6c\xf4\xde\x74\x45\x63"
+			  "\x5c\x7a\xd5\xcc\x8b\x76\xef\x0e"
+			  "\xcf\x2c\x60\x69\x37\xfd\x07\x96",
+		.ptext	= "\x65\x75\xae\xd3\xe2\xbc\x43\x5c"
+			  "\xb3\x1a\xd8\x05\xc3\xd0\x56\x29",
+		.ctext	= "\x11\x91\xea\x74\x58\xcc\xd5\xa2"
+			  "\xd0\x55\x9e\x3d\xfe\x7f\xc8\xfe",
+		.klen	= 16,
+		.len	= 16,
+	},
+	{
+		.key	= "\xe7\xd1\x77\x48\x76\x0b\xcd\x34"
+			  "\x2a\x2d\xe7\x74\xca\x11\x9c\xae",
+		.iv	= "\x71\x1c\x49\x62\xd9\x5b\x50\x5e"
+			  "\x68\x87\xbc\xf6\x89\xff\xed\x30"
+			  "\xe4\xe5\xbd\xb6\x10\x4f\x9f\x66"
+			  "\x28\x06\x5a\xf4\x27\x35\xcd\xe5",
+		.ptext	= "\x87\x03\x8f\x06\xa8\x61\x54\xda"
+			  "\x01\x45\xd4\x01\xef\x4a\x22\xcf"
+			  "\x78\x15\x9f\xbd\x64\xbd\x2c\xb9"
+			  "\x40\x1d\x72\xae\x53\x63\xa5",
+		.ctext	= "\x4e\xa1\x05\x27\xb8\x45\xe4\xa1"
+			  "\xbb\x30\xb4\xa6\x12\x74\x63\xd6"
+			  "\x17\xc9\xcc\x2f\x18\x64\xe0\x06"
+			  "\x0a\xa0\xff\x72\x10\x7b\x22",
+		.klen	= 16,
+		.len	= 31,
+	},
+	{
+		.key	= "\x59\x65\x3b\x1d\x43\x5e\xc0\xae"
+			  "\xb8\x9d\x9b\xdd\x22\x03\xbf\xca",
+		.iv	= "\xec\x95\xfa\x5a\xcf\x5e\xd2\x93"
+			  "\xa3\xb5\xe5\xbe\xf3\x01\x7b\x01"
+			  "\xd1\xca\x6c\x06\x82\xf0\xbd\x67"
+			  "\xd9\x6c\xa4\xdc\xb4\x38\x0f\x74",
+		.ptext	= "\x45\xdf\x75\x87\xbc\x72\xce\x55"
+			  "\xc9\xfa\xcb\xfc\x9f\x40\x82\x2b"
+			  "\xc6\x4f\x4f\x5b\x8b\x3b\x6d\x67"
+			  "\xa6\x93\x62\x89\x8c\x19\xf4\xe3"
+			  "\x08\x92\x9c\xc9\x47\x2c\x6e\xd0"
+			  "\xa3\x02\x2b\xdb\x2c\xf2\x8d\x46"
+			  "\xcd\xb0\x9d\x26\x63\x4c\x40\x6b"
+			  "\x79\x43\xe5\xce\x42\xa8\xec\x3b"
+			  "\x5b\xd0\xea\xa4\xe6\xdb\x66\x55"
+			  "\x7a\x76\xec\xab\x7d\x2a\x2b\xbd"
+			  "\xa9\xab\x22\x64\x1a\xa1\xae\x84"
+			  "\x86\x79\x67\xe9\xb2\x50\xbe\x12"
+			  "\x2f\xb2\x14\xf0\xdb\x71\xd8\xa7"
+			  "\x41\x8a\x88\xa0\x6a\x6e\x9d\x2a"
+			  "\xfa\x11\x37\x40\x32\x09\x4c\x47"
+			  "\x41\x07\x31\x85\x3d\xa8\xf7\x64",
+		.ctext	= "\x2d\x4b\x9f\x93\xca\x5a\x48\x26"
+			  "\x01\xcc\x54\xe4\x31\x50\x12\xf0"
+			  "\x49\xff\x59\x42\x68\xbd\x87\x8f"
+			  "\x9e\x62\x96\xcd\xb9\x24\x57\xa4"
+			  "\x0b\x7b\xf5\x2e\x0e\xa8\x65\x07"
+			  "\xab\x05\xd5\xca\xe7\x9c\x6c\x34"
+			  "\x5d\x42\x34\xa4\x62\xe9\x75\x48"
+			  "\x3d\x9e\x8f\xfa\x42\xe9\x75\x08"
+			  "\x4e\x54\x91\x2b\xbd\x11\x0f\x8e"
+			  "\xf0\x82\xf5\x24\xf1\xc4\xfc\xae"
+			  "\x42\x54\x7f\xce\x15\xa8\xb2\x33"
+			  "\xc0\x86\xb6\x2b\xe8\x44\xce\x1f"
+			  "\x68\x57\x66\x94\x6e\xad\xeb\xf3"
+			  "\x30\xf8\x11\xbd\x60\x00\xc6\xd5"
+			  "\x4c\x81\xf1\x20\x2b\x4a\x5b\x99"
+			  "\x79\x3b\xc9\x5c\x74\x23\xe6\x5d",
+		.klen	= 16,
+		.len	= 128,
+	},
+	{
+		.key	= "\x3e\x08\x5d\x64\x6c\x98\xec\xec"
+			  "\x70\x0e\x0d\xa1\x41\x20\x99\x82",
+		.iv	= "\x11\xb7\x77\x91\x0d\x99\xd9\x8d"
+			  "\x35\x3a\xf7\x14\x6b\x09\x37\xe5"
+			  "\xad\x51\xf6\xc3\x96\x4b\x64\x56"
+			  "\xa8\xbd\x81\xcc\xbe\x94\xaf\xe4",
+		.ptext	= "\xff\x8d\xb9\xc0\xe3\x69\xb3\xb2"
+			  "\x8b\x11\x26\xb3\x11\xec\xfb\xb9"
+			  "\x9c\xc1\x71\xd6\xe3\x26\x0e\xe0"
+			  "\x68\x40\x60\xb9\x3a\x63\x56\x8a"
+			  "\x9e\xc1\xf0\x10\xb1\x64\x32\x70"
+			  "\xf8\xcd\xc6\xc4\x49\x4c\xe1\xce"
+			  "\xf3\xe1\x03\xf8\x35\xae\xe0\x5e"
+			  "\xef\x5f\xbc\x41\x75\x26\x13\xcc"
+			  "\x37\x85\xdf\xc0\x5d\xa6\x47\x98"
+			  "\xf1\x97\x52\x58\x04\xe6\xb5\x01"
+			  "\xc0\xb8\x17\x6d\x74\xbd\x9a\xdf"
+			  "\xa4\x37\x94\x86\xb0\x13\x83\x28"
+			  "\xc9\xa2\x07\x3f\xb5\xb2\x72\x40"
+			  "\x0e\x60\xdf\x57\x07\xb7\x2c\x66"
+			  "\x10\x3f\x8d\xdd\x30\x0a\x47\xd5"
+			  "\xe8\x9d\xfb\xa1\xaf\x53\xd7\x05"
+			  "\xc7\xd2\xba\xe7\x2c\xa0\xbf\xb8"
+			  "\xd1\x93\xe7\x41\x82\xa3\x41\x3a"
+			  "\xaf\x12\xd6\xf8\x34\xda\x92\x46"
+			  "\xad\xa2\x2f\xf6\x7e\x46\x96\xd8"
+			  "\x03\xf3\x49\x64\xde\xd8\x06\x8b"
+			  "\xa0\xbc\x63\x35\x38\xb6\x6b\xda"
+			  "\x5b\x50\x3f\x13\xa5\x84\x1b\x1b"
+			  "\x66\x89\x95\xb7\xc2\x16\x3c\xe9"
+			  "\x24\xb0\x8c\x6f\x49\xef\xf7\x28"
+			  "\x6a\x24\xfd\xbe\x25\xe2\xb4\x90"
+			  "\x77\x44\x08\xb8\xda\xd2\xde\x2c"
+			  "\xa0\x57\x45\x57\x29\x47\x6b\x89"
+			  "\x4a\xf6\xa7\x2a\xc3\x9e\x7b\xc8"
+			  "\xfd\x9f\x89\xab\xee\x6d\xa3\xb4"
+			  "\x23\x90\x7a\xe9\x89\xa0\xc7\xb3"
+			  "\x17\x41\x87\x91\xfc\x97\x42",
+		.ctext	= "\xfc\x9b\x96\x66\xc4\x82\x2a\x4a"
+			  "\xb1\x24\xba\xc7\x78\x5f\x79\xc1"
+			  "\x57\x2e\x47\x29\x4d\x7b\xd2\x9a"
+			  "\xbd\xc6\xc1\x26\x7b\x8e\x3f\x5d"
+			  "\xd4\xb4\x9f\x6a\x02\x24\x4a\xad"
+			  "\x0c\x00\x1b\xdf\x92\xc5\x8a\xe1"
+			  "\x77\x79\xcc\xd5\x20\xbf\x83\xf4"
+			  "\x4b\xad\x11\xbf\xdb\x47\x65\x70"
+			  "\x43\xf3\x65\xdf\xb7\xdc\xb2\xb9"
+			  "\xaa\x3f\xb3\xdf\x79\x69\x0d\xa0"
+			  "\x86\x1c\xba\x48\x0b\x01\xc1\x88"
+			  "\xdf\x03\xb1\x06\x3c\x1d\x56\xa1"
+			  "\x8e\x98\xc1\xa6\x95\xa2\x5b\x72"
+			  "\x76\x59\xd2\x26\x25\xcd\xef\x7c"
+			  "\xc9\x60\xea\x43\xd1\x12\x8a\x8a"
+			  "\x63\x12\x78\xcb\x2f\x88\x1e\x88"
+			  "\x78\x59\xde\xba\x4d\x2c\x78\x61"
+			  "\x75\x37\x54\xfd\x80\xc7\x5e\x98"
+			  "\xcf\x14\x62\x8e\xfb\x72\xee\x4d"
+			  "\x9f\xaf\x8b\x09\xe5\x21\x0a\x91"
+			  "\x8f\x88\x87\xd5\xb1\x84\xab\x18"
+			  "\x08\x57\xed\x72\x35\xa6\x0e\xc6"
+			  "\xff\xcb\xfe\x2c\x48\x39\x14\x44"
+			  "\xba\x59\x32\x3a\x2d\xc4\x5f\xcb"
+			  "\xbe\x68\x8e\x7b\xee\x21\xa4\x32"
+			  "\x11\xa0\x99\xfd\x90\xde\x59\x43"
+			  "\xeb\xed\xd5\x87\x68\x46\xc6\xde"
+			  "\x0b\x07\x17\x59\x6a\xab\xca\x15"
+			  "\x65\x02\x01\xb6\x71\x8c\x3b\xaa"
+			  "\x18\x3b\x30\xae\x38\x5b\x2c\x74"
+			  "\xd4\xee\x4a\xfc\xf7\x1b\x09\xd4"
+			  "\xda\x8b\x1d\x5d\x6f\x21\x6c",
+		.klen	= 16,
+		.len	= 255,
+	},
+	{
+		.key	= "\x24\xf6\xe1\x62\xe5\xaf\x99\xda"
+			  "\x84\xec\x41\xb0\xa3\x0b\xd5\xa8"
+			  "\xa0\x3e\x7b\xa6\xdd\x6c\x8f\xa8",
+		.iv	= "\x7f\x80\x24\x62\x32\xdd\xab\x66"
+			  "\xf2\x87\x29\x24\xec\xd2\x4b\x9f"
+			  "\x0c\x33\x52\xd9\xe0\xcc\x6e\xe4"
+			  "\x90\x85\x43\x97\xc4\x62\x14\x33",
+		.ptext	= "\xef\x58\xe7\x7f\xa9\xd9\xb8\xd7"
+			  "\xa2\x91\x97\x07\x27\x9e\xba\xe8"
+			  "\xaa",
+		.ctext	= "\xd7\xc3\x81\x91\xf2\x40\x17\x73"
+			  "\x3e\x3b\x1c\x2a\x8e\x11\x9c\x17"
+			  "\xf1",
+		.klen	= 24,
+		.len	= 17,
+	},
+	{
+		.key	= "\xbf\xaf\xd7\x67\x8c\x47\xcf\x21"
+			  "\x8a\xa5\xdd\x32\x25\x47\xbe\x4f"
+			  "\xf1\x3a\x0b\xa6\xaa\x2d\xcf\x09",
+		.iv	= "\xd9\xe8\xf0\x92\x4e\xfc\x1d\xf2"
+			  "\x81\x37\x7c\x8f\xf1\x59\x09\x20"
+			  "\xf4\x46\x51\x86\x4f\x54\x8b\x32"
+			  "\x58\xd1\x99\x8b\x8c\x03\xeb\x5d",
+		.ptext	= "\xcd\x64\x90\xf9\x7c\xe5\x0e\x5a"
+			  "\x75\xe7\x8e\x39\x86\xec\x20\x43"
+			  "\x8a\x49\x09\x15\x47\xf4\x3c\x89"
+			  "\x21\xeb\xcf\x4e\xcf\x91\xb5\x40"
+			  "\xcd\xe5\x4d\x5c\x6f\xf2\xd2\x80"
+			  "\xfa\xab\xb3\x76\x9f\x7f\x84\x0a",
+		.ctext	= "\x44\x98\x64\x15\xb7\x0b\x80\xa3"
+			  "\xb9\xca\x23\xff\x3b\x0b\x68\x74"
+			  "\xbb\x3e\x20\x19\x9f\x28\x71\x2a"
+			  "\x48\x3c\x7c\xe2\xef\xb5\x10\xac"
+			  "\x82\x9f\xcd\x08\x8f\x6b\x16\x6f"
+			  "\xc3\xbb\x07\xfb\x3c\xb0\x1b\x27",
+		.klen	= 24,
+		.len	= 48,
+	},
+	{
+		.key	= "\xb8\x35\xa2\x5f\x86\xbb\x82\x99"
+			  "\x27\xeb\x01\x3f\x92\xaf\x80\x24"
+			  "\x4c\x66\xa2\x89\xff\x2e\xa2\x25",
+		.iv	= "\x0a\x1d\x96\xd3\xe0\xe8\x0c\x9b"
+			  "\x9d\x6f\x21\x97\xc2\x17\xdb\x39"
+			  "\x3f\xd8\x64\x48\x80\x04\xee\x43"
+			  "\x02\xce\x88\xe2\x81\x81\x5f\x81",
+		.ptext	= "\xb8\xf9\x16\x8b\x25\x68\xd0\x9c"
+			  "\xd2\x28\xac\xa8\x79\xc2\x30\xc1"
+			  "\x31\xde\x1c\x37\x1b\xa2\xb5\xe6"
+			  "\xf0\xd0\xf8\x9c\x7f\xc6\x46\x07"
+			  "\x5c\xc3\x06\xe4\xf0\x02\xec\xf8"
+			  "\x59\x7c\xc2\x5d\xf8\x0c\x21\xae"
+			  "\x9e\x82\xb1\x1a\x5f\x78\x44\x15"
+			  "\x00\xa7\x2e\x52\xc5\x98\x98\x35"
+			  "\x03\xae\xd0\x8e\x07\x57\xe2\x5a"
+			  "\x17\xbf\x52\x40\x54\x5b\x74\xe5"
+			  "\x2d\x35\xaf\x9e\x37\xf7\x7e\x4a"
+			  "\x8c\x9e\xa1\xdc\x40\xb4\x5b\x36"
+			  "\xdc\x3a\x68\xe6\xb7\x35\x0b\x8a"
+			  "\x90\xec\x74\x8f\x09\x9a\x7f\x02"
+			  "\x4d\x03\x46\x35\x62\xb1\xbd\x08"
+			  "\x3f\x54\x2a\x10\x0b\xdc\x69\xaf"
+			  "\x25\x3a\x0c\x5f\xe0\x51\xe7\x11"
+			  "\xb7\x00\xab\xbb\x9a\xb0\xdc\x4d"
+			  "\xc3\x7d\x1a\x6e\xd1\x09\x52\xbd"
+			  "\x6b\x43\x55\x22\x3a\x78\x14\x7d"
+			  "\x79\xfd\x8d\xfc\x9b\x1d\x0f\xa2"
+			  "\xc7\xb9\xf8\x87\xd5\x96\x50\x61"
+			  "\xa7\x5e\x1e\x57\x97\xe0\xad\x2f"
+			  "\x93\xe6\xe8\x83\xec\x85\x26\x5e"
+			  "\xd9\x2a\x15\xe0\xe9\x09\x25\xa1"
+			  "\x77\x2b\x88\xdc\xa4\xa5\x48\xb6"
+			  "\xf7\xcc\xa6\xa9\xba\xf3\x42\x5c"
+			  "\x70\x9d\xe9\x29\xc1\xf1\x33\xdd"
+			  "\x56\x48\x17\x86\x14\x51\x5c\x10"
+			  "\xab\xfd\xd3\x26\x8c\x21\xf5\x93"
+			  "\x1b\xeb\x47\x97\x73\xbb\x88\x10"
+			  "\xf3\xfe\xf5\xde\xf3\x2e\x05\x46"
+			  "\x1c\x0d\xa3\x10\x48\x9c\x71\x16"
+			  "\x78\x33\x4d\x0a\x74\x3b\xe9\x34"
+			  "\x0b\xa7\x0e\x9e\x61\xe9\xe9\xfd"
+			  "\x85\xa0\xcb\x19\xfd\x7c\x33\xe3"
+			  "\x0e\xce\xc2\x6f\x9d\xa4\x2d\x77"
+			  "\xfd\xad\xee\x5e\x08\x3e\xd7\xf5"
+			  "\xfb\xc3\xd7\x93\x96\x08\x96\xca"
+			  "\x58\x81\x16\x9b\x98\x0a\xe2\xef"
+			  "\x7f\xda\x40\xe4\x1f\x46\x9e\x67"
+			  "\x2b\x84\xcb\x42\xc4\xd6\x6a\xcf"
+			  "\x2d\xb2\x33\xc0\x56\xb3\x35\x6f"
+			  "\x29\x36\x8f\x6a\x5b\xec\xd5\x4f"
+			  "\xa0\x70\xff\xb6\x5b\xde\x6a\x93"
+			  "\x20\x3c\xe2\x76\x7a\xef\x3c\x79"
+			  "\x31\x65\xce\x3a\x0e\xd0\xbe\xa8"
+			  "\x21\x95\xc7\x2b\x62\x8e\x67\xdd"
+			  "\x20\x79\xe4\xe5\x01\x15\xc0\xec"
+			  "\x0f\xd9\x23\xc8\xca\xdf\xd4\x7d"
+			  "\x1d\xf8\x64\x4f\x56\xb1\x83\xa7"
+			  "\x43\xbe\xfc\xcf\xc2\x8c\x33\xda"
+			  "\x36\xd0\x52\xef\x9e\x9e\x88\xf4"
+			  "\xa8\x21\x0f\xaa\xee\x8d\xa0\x24"
+			  "\x4d\xcb\xb1\x72\x07\xf0\xc2\x06"
+			  "\x60\x65\x85\x84\x2c\x60\xcf\x61"
+			  "\xe7\x56\x43\x5b\x2b\x50\x74\xfa"
+			  "\xdb\x4e\xea\x88\xd4\xb3\x83\x8f"
+			  "\x6f\x97\x4b\x57\x7a\x64\x64\xae"
+			  "\x0a\x37\x66\xc5\x03\xad\xb5\xf9"
+			  "\x08\xb0\x3a\x74\xde\x97\x51\xff"
+			  "\x48\x4f\x5c\xa4\xf8\x7a\xb4\x05"
+			  "\x27\x70\x52\x86\x1b\x78\xfc\x18"
+			  "\x06\x27\xa9\x62\xf7\xda\xd2\x8e",
+		.ctext	= "\x3b\xe1\xdb\xb3\xc5\x9a\xde\x69"
+			  "\x58\x05\xcc\xeb\x02\x51\x78\x4a"
+			  "\xac\x28\xe9\xed\xd1\xc9\x15\x7d"
+			  "\x33\x7d\xc1\x47\x12\x41\x11\xf8"
+			  "\x4a\x2c\xb7\xa3\x41\xbe\x59\xf7"
+			  "\x22\xdb\x2c\xda\x9c\x00\x61\x9b"
+			  "\x73\xb3\x0b\x84\x2b\xc1\xf3\x80"
+			  "\x84\xeb\x19\x60\x80\x09\xe1\xcd"
+			  "\x16\x3a\x20\x23\xc4\x82\x4f\xba"
+			  "\x3b\x8e\x55\xd7\xa9\x0b\x75\xd0"
+			  "\xda\xce\xd2\xee\x7e\x4b\x7f\x65"
+			  "\x4d\x28\xc5\xd3\x15\x2c\x40\x96"
+			  "\x52\xd4\x18\x61\x2b\xe7\x83\xec"
+			  "\x89\x62\x9c\x4c\x50\xe6\xe2\xbb"
+			  "\x25\xa1\x0f\xa7\xb0\xb4\xb2\xde"
+			  "\x54\x20\xae\xa3\x56\xa5\x26\x4c"
+			  "\xd5\xcc\xe5\xcb\x28\x44\xb1\xef"
+			  "\x67\x2e\x93\x6d\x00\x88\x83\x9a"
+			  "\xf2\x1c\x48\x38\xec\x1a\x24\x90"
+			  "\x73\x0a\xdb\xe8\xce\x95\x7a\x2c"
+			  "\x8c\xe9\xb7\x07\x1d\xb3\xa3\x20"
+			  "\xbe\xad\x61\x84\xac\xde\x76\xb5"
+			  "\xa6\x28\x29\x47\x63\xc4\xfc\x13"
+			  "\x3f\x71\xfb\x58\x37\x34\x82\xed"
+			  "\x9e\x05\x19\x1f\xc1\x67\xc1\xab"
+			  "\xf5\xfd\x7c\xea\xfa\xa4\xf8\x0a"
+			  "\xac\x4c\x92\xdf\x65\x73\xd7\xdb"
+			  "\xed\x2c\xe0\x84\x5f\x57\x8c\x76"
+			  "\x3e\x05\xc0\xc3\x68\x96\x95\x0b"
+			  "\x88\x97\xfe\x2e\x99\xd5\xc2\xb9"
+			  "\x53\x9f\xf3\x32\x10\x1f\x1f\x5d"
+			  "\xdf\x21\x95\x70\x91\xe8\xa1\x3e"
+			  "\x19\x3e\xb6\x0b\xa8\xdb\xf8\xd4"
+			  "\x54\x27\xb8\xab\x5d\x78\x0c\xe6"
+			  "\xb7\x08\xee\xa4\xb6\x6b\xeb\x5a"
+			  "\x89\x69\x2b\xbd\xd4\x21\x5b\xbf"
+			  "\x79\xbb\x0f\xff\xdb\x23\x9a\xeb"
+			  "\x8d\xf2\xc4\x39\xb4\x90\x77\x6f"
+			  "\x68\xe2\xb8\xf3\xf1\x65\x4f\xd5"
+			  "\x24\x80\x06\xaf\x7c\x8d\x15\x0c"
+			  "\xfd\x56\xe5\xe3\x01\xa5\xf7\x1c"
+			  "\x31\xd6\xa2\x01\x1e\x59\xf9\xa9"
+			  "\x42\xd5\xc2\x34\xda\x25\xde\xc6"
+			  "\x5d\x38\xef\xd1\x4c\xc1\xd9\x1b"
+			  "\x98\xfd\xcd\x57\x6f\xfd\x46\x91"
+			  "\x90\x3d\x52\x2b\x2c\x7d\xcf\x71"
+			  "\xcf\xd1\x77\x23\x71\x36\xb1\xce"
+			  "\xc7\x5d\xf0\x5b\x44\x3d\x43\x71"
+			  "\xac\xb8\xa0\x6a\xea\x89\x5c\xff"
+			  "\x81\x73\xd4\x83\xd1\xc9\xe9\xe2"
+			  "\xa8\xa6\x0f\x36\xe6\xaa\x57\xd4"
+			  "\x27\xd2\xc9\xda\x94\x02\x1f\xfb"
+			  "\xe1\xa1\x07\xbe\xe1\x1b\x15\x94"
+			  "\x1e\xac\x2f\x57\xbb\x41\x22\xaf"
+			  "\x60\x5e\xcc\x66\xcb\x16\x62\xab"
+			  "\xb8\x7c\x99\xf4\x84\x93\x0c\xc2"
+			  "\xa2\x49\xe4\xfd\x17\x55\xe1\xa6"
+			  "\x8d\x5b\xc6\x1b\xc8\xac\xec\x11"
+			  "\x33\xcf\xb0\xe8\xc7\x28\x4f\xb2"
+			  "\x5c\xa6\xe2\x71\xab\x80\x0a\xa7"
+			  "\x5c\x59\x50\x9f\x7a\x32\xb7\xe5"
+			  "\x24\x9a\x8e\x25\x21\x2e\xb7\x18"
+			  "\xd0\xf2\xe7\x27\x6f\xda\xc1\x00"
+			  "\xd9\xa6\x03\x59\xac\x4b\xcb\xba",
+		.klen	= 24,
+		.len	= 512,
+	},
+	{
+		.key	= "\x9e\xeb\xb2\x49\x3c\x1c\xf5\xf4"
+			  "\x6a\x99\xc2\xc4\xdf\xb1\xf4\xdd"
+			  "\x75\x20\x57\xea\x2c\x4f\xcd\xb2"
+			  "\xa5\x3d\x7b\x49\x1e\xab\xfd\x0f",
+		.iv	= "\xdf\x63\xd4\xab\xd2\x49\xf3\xd8"
+			  "\x33\x81\x37\x60\x7d\xfa\x73\x08"
+			  "\xd8\x49\x6d\x80\xe8\x2f\x62\x54"
+			  "\xeb\x0e\xa9\x39\x5b\x45\x7f\x8a",
+		.ptext	= "\x67\xc9\xf2\x30\x84\x41\x8e\x43"
+			  "\xfb\xf3\xb3\x3e\x79\x36\x7f\xe8",
+		.ctext	= "\x27\x38\x78\x47\x16\xd9\x71\x35"
+			  "\x2e\x7e\xdd\x7e\x43\x3c\xb8\x40",
+		.klen	= 32,
+		.len	= 16,
+	},
+	{
+		.key	= "\x93\xfa\x7e\xe2\x0e\x67\xc4\x39"
+			  "\xe7\xca\x47\x95\x68\x9d\x5e\x5a"
+			  "\x7c\x26\x19\xab\xc6\xca\x6a\x4c"
+			  "\x45\xa6\x96\x42\xae\x6c\xff\xe7",
+		.iv	= "\xea\x82\x47\x95\x3b\x22\xa1\x3a"
+			  "\x6a\xca\x24\x4c\x50\x7e\x23\xcd"
+			  "\x0e\x50\xe5\x41\xb6\x65\x29\xd8"
+			  "\x30\x23\x00\xd2\x54\xa7\xd6\x56",
+		.ptext	= "\xdb\x1f\x1f\xec\xad\x83\x6e\x5d"
+			  "\x19\xa5\xf6\x3b\xb4\x93\x5a\x57"
+			  "\x6f",
+		.ctext	= "\xf1\x46\x6e\x9d\xb3\x01\xf0\x6b"
+			  "\xc2\xac\x57\x88\x48\x6d\x40\x72"
+			  "\x68",
+		.klen	= 32,
+		.len	= 17,
+	},
+	{
+		.key	= "\x36\x2b\x57\x97\xf8\x5d\xcd\x99"
+			  "\x5f\x1a\x5a\x44\x1d\x92\x0f\x27"
+			  "\xcc\x16\xd7\x2b\x85\x63\x99\xd3"
+			  "\xba\x96\xa1\xdb\xd2\x60\x68\xda",
+		.iv	= "\xef\x58\x69\xb1\x2c\x5e\x9a\x47"
+			  "\x24\xc1\xb1\x69\xe1\x12\x93\x8f"
+			  "\x43\x3d\x6d\x00\xdb\x5e\xd8\xd9"
+			  "\x12\x9a\xfe\xd9\xff\x2d\xaa\xc4",
+		.ptext	= "\x5e\xa8\x68\x19\x85\x98\x12\x23"
+			  "\x26\x0a\xcc\xdb\x0a\x04\xb9\xdf"
+			  "\x4d\xb3\x48\x7b\xb0\xe3\xc8\x19"
+			  "\x43\x5a\x46\x06\x94\x2d\xf2",
+		.ctext	= "\xdb\xfd\xc8\x03\xd0\xec\xc1\xfe"
+			  "\xbd\x64\x37\xb8\x82\x43\x62\x4e"
+			  "\x7e\x54\xa3\xe2\x24\xa7\x27\xe8"
+			  "\xa4\xd5\xb3\x6c\xb2\x26\xb4",
+		.klen	= 32,
+		.len	= 31,
+	},
+	{
+		.key	= "\x03\x65\x03\x6e\x4d\xe6\xe8\x4e"
+			  "\x8b\xbe\x22\x19\x48\x31\xee\xd9"
+			  "\xa0\x91\x21\xbe\x62\x89\xde\x78"
+			  "\xd9\xb0\x36\xa3\x3c\xce\x43\xd5",
+		.iv	= "\xa9\xc3\x4b\xe7\x0f\xfc\x6d\xbf"
+			  "\x56\x27\x21\x1c\xfc\xd6\x04\x10"
+			  "\x5f\x43\xe2\x30\x35\x29\x6c\x10"
+			  "\x90\xf1\xbf\x61\xed\x0f\x8a\x91",
+		.ptext	= "\x07\xaa\x02\x26\xb4\x98\x11\x5e"
+			  "\x33\x41\x21\x51\x51\x63\x2c\x72"
+			  "\x00\xab\x32\xa7\x1c\xc8\x3c\x9c"
+			  "\x25\x0e\x8b\x9a\xdf\x85\xed\x2d"
+			  "\xf4\xf2\xbc\x55\xca\x92\x6d\x22"
+			  "\xfd\x22\x3b\x42\x4c\x0b\x74\xec",
+		.ctext	= "\x7b\xb1\x43\x6d\xd8\x72\x6c\xf6"
+			  "\x67\x6a\x00\xc4\xf1\xf0\xf5\xa4"
+			  "\xfc\x60\x91\xab\x46\x0b\x15\xfc"
+			  "\xd7\xc1\x28\x15\xa1\xfc\xf7\x68"
+			  "\x8e\xcc\x27\x62\x00\x64\x56\x72"
+			  "\xa6\x17\xd7\x3f\x67\x80\x10\x58",
+		.klen	= 32,
+		.len	= 48,
+	},
+	{
+		.key	= "\xa5\x28\x24\x34\x1a\x3c\xd8\xf7"
+			  "\x05\x91\x8f\xee\x85\x1f\x35\x7f"
+			  "\x80\x3d\xfc\x9b\x94\xf6\xfc\x9e"
+			  "\x19\x09\x00\xa9\x04\x31\x4f\x11",
+		.iv	= "\xa1\xba\x49\x95\xff\x34\x6d\xb8"
+			  "\xcd\x87\x5d\x5e\xfd\xea\x85\xdb"
+			  "\x8a\x7b\x5e\xb2\x5d\x57\xdd\x62"
+			  "\xac\xa9\x8c\x41\x42\x94\x75\xb7",
+		.ptext	= "\x69\xb4\xe8\x8c\x37\xe8\x67\x82"
+			  "\xf1\xec\x5d\x04\xe5\x14\x91\x13"
+			  "\xdf\xf2\x87\x1b\x69\x81\x1d\x71"
+			  "\x70\x9e\x9c\x3b\xde\x49\x70\x11"
+			  "\xa0\xa3\xdb\x0d\x54\x4f\x66\x69"
+			  "\xd7\xdb\x80\xa7\x70\x92\x68\xce"
+			  "\x81\x04\x2c\xc6\xab\xae\xe5\x60"
+			  "\x15\xe9\x6f\xef\xaa\x8f\xa7\xa7"
+			  "\x63\x8f\xf2\xf0\x77\xf1\xa8\xea"
+			  "\xe1\xb7\x1f\x9e\xab\x9e\x4b\x3f"
+			  "\x07\x87\x5b\x6f\xcd\xa8\xaf\xb9"
+			  "\xfa\x70\x0b\x52\xb8\xa8\xa7\x9e"
+			  "\x07\x5f\xa6\x0e\xb3\x9b\x79\x13"
+			  "\x79\xc3\x3e\x8d\x1c\x2c\x68\xc8"
+			  "\x51\x1d\x3c\x7b\x7d\x79\x77\x2a"
+			  "\x56\x65\xc5\x54\x23\x28\xb0\x03",
+		.ctext	= "\xeb\xf9\x98\x86\x3c\x40\x9f\x16"
+			  "\x84\x01\xf9\x06\x0f\xeb\x3c\xa9"
+			  "\x4c\xa4\x8e\x5d\xc3\x8d\xe5\xd3"
+			  "\xae\xa6\xe6\xcc\xd6\x2d\x37\x4f"
+			  "\x99\xc8\xa3\x21\x46\xb8\x69\xf2"
+			  "\xe3\x14\x89\xd7\xb9\xf5\x9e\x4e"
+			  "\x07\x93\x6f\x78\x8e\x6b\xea\x8f"
+			  "\xfb\x43\xb8\x3e\x9b\x4c\x1d\x7e"
+			  "\x20\x9a\xc5\x87\xee\xaf\xf6\xf9"
+			  "\x46\xc5\x18\x8a\xe8\x69\xe7\x96"
+			  "\x52\x55\x5f\x00\x1e\x1a\xdc\xcc"
+			  "\x13\xa5\xee\xff\x4b\x27\xca\xdc"
+			  "\x10\xa6\x48\x76\x98\x43\x94\xa3"
+			  "\xc7\xe2\xc9\x65\x9b\x08\x14\x26"
+			  "\x1d\x68\xfb\x15\x0a\x33\x49\x84"
+			  "\x84\x33\x5a\x1b\x24\x46\x31\x92",
+		.klen	= 32,
+		.len	= 128,
+	},
+	{
+		.key	= "\x36\x45\x11\xa2\x98\x5f\x96\x7c"
+			  "\xc6\xb4\x94\x31\x0a\x67\x09\x32"
+			  "\x6c\x6f\x6f\x00\xf0\x17\xcb\xac"
+			  "\xa5\xa9\x47\x9e\x2e\x85\x2f\xfa",
+		.iv	= "\x28\x88\xaa\x9b\x59\x3b\x1e\x97"
+			  "\x82\xe5\x5c\x9e\x6d\x14\x11\x19"
+			  "\x6e\x38\x8f\xd5\x40\x2b\xca\xf9"
+			  "\x7b\x4c\xe4\xa3\xd0\xd2\x8a\x13",
+		.ptext	= "\x95\xd2\xf7\x71\x1b\xca\xa5\x86"
+			  "\xd9\x48\x01\x93\x2f\x79\x55\x29"
+			  "\x71\x13\x15\x0e\xe6\x12\xbc\x4d"
+			  "\x8a\x31\xe3\x40\x2a\xc6\x5e\x0d"
+			  "\x68\xbb\x4a\x62\x8d\xc7\x45\x77"
+			  "\xd2\xb8\xc7\x1d\xf1\xd2\x5d\x97"
+			  "\xcf\xac\x52\xe5\x32\x77\xb6\xda"
+			  "\x30\x85\xcf\x2b\x98\xe9\xaa\x34"
+			  "\x62\xb5\x23\x9e\xb7\xa6\xd4\xe0"
+			  "\xb4\x58\x18\x8c\x4d\xde\x4d\x01"
+			  "\x83\x89\x24\xca\xfb\x11\xd4\x82"
+			  "\x30\x7a\x81\x35\xa0\xb4\xd4\xb6"
+			  "\x84\xea\x47\x91\x8c\x19\x86\x25"
+			  "\xa6\x06\x8d\x78\xe6\xed\x87\xeb"
+			  "\xda\xea\x73\x7c\xbf\x66\xb8\x72"
+			  "\xe3\x0a\xb8\x0c\xcb\x1a\x73\xf1"
+			  "\xa7\xca\x0a\xde\x57\x2b\xbd\x2b"
+			  "\xeb\x8b\x24\x38\x22\xd3\x0e\x1f"
+			  "\x17\xa0\x84\x98\x31\x77\xfd\x34"
+			  "\x6a\x4e\x3d\x84\x4c\x0e\xfb\xed"
+			  "\xc8\x2a\x51\xfa\xd8\x73\x21\x8a"
+			  "\xdb\xb5\xfe\x1f\xee\xc4\xe8\x65"
+			  "\x54\x84\xdd\x96\x6d\xfd\xd3\x31"
+			  "\x77\x36\x52\x6b\x80\x4f\x9e\xb4"
+			  "\xa2\x55\xbf\x66\x41\x49\x4e\x87"
+			  "\xa7\x0c\xca\xe7\xa5\xc5\xf6\x6f"
+			  "\x27\x56\xe2\x48\x22\xdd\x5f\x59"
+			  "\x3c\xf1\x9f\x83\xe5\x2d\xfb\x71"
+			  "\xad\xd1\xae\x1b\x20\x5c\x47\xb7"
+			  "\x3b\xd3\x14\xce\x81\x42\xb1\x0a"
+			  "\xf0\x49\xfa\xc2\xe7\x86\xbf\xcd"
+			  "\xb0\x95\x9f\x8f\x79\x41\x54",
+		.ctext	= "\xf6\x57\x51\xc4\x25\x61\x2d\xfa"
+			  "\xd6\xd9\x3f\x9a\x81\x51\xdd\x8e"
+			  "\x3d\xe7\xaa\x2d\xb1\xda\xc8\xa6"
+			  "\x9d\xaa\x3c\xab\x62\xf2\x80\xc3"
+			  "\x2c\xe7\x58\x72\x1d\x44\xc5\x28"
+			  "\x7f\xb4\xf9\xbc\x9c\xb2\xab\x8e"
+			  "\xfa\xd1\x4d\x72\xd9\x79\xf5\xa0"
+			  "\x24\x3e\x90\x25\x31\x14\x38\x45"
+			  "\x59\xc8\xf6\xe2\xc6\xf6\xc1\xa7"
+			  "\xb2\xf8\xa7\xa9\x2b\x6f\x12\x3a"
+			  "\xb0\x81\xa4\x08\x57\x59\xb1\x56"
+			  "\x4c\x8f\x18\x55\x33\x5f\xd6\x6a"
+			  "\xc6\xa0\x4b\xd6\x6b\x64\x3e\x9e"
+			  "\xfd\x66\x16\xe2\xdb\xeb\x5f\xb3"
+			  "\x50\x50\x3e\xde\x8d\x72\x76\x01"
+			  "\xbe\xcc\xc9\x52\x09\x2d\x8d\xe7"
+			  "\xd6\xc3\x66\xdb\x36\x08\xd1\x77"
+			  "\xc8\x73\x46\x26\x24\x29\xbf\x68"
+			  "\x2d\x2a\x99\x43\x56\x55\xe4\x93"
+			  "\xaf\xae\x4d\xe7\x55\x4a\xc0\x45"
+			  "\x26\xeb\x3b\x12\x90\x7c\xdc\xd1"
+			  "\xd5\x6f\x0a\xd0\xa9\xd7\x4b\x89"
+			  "\x0b\x07\xd8\x86\xad\xa1\xc4\x69"
+			  "\x1f\x5e\x8b\xc4\x9e\x91\x41\x25"
+			  "\x56\x98\x69\x78\x3a\x9e\xae\x91"
+			  "\xd8\xd9\xfa\xfb\xff\x81\x25\x09"
+			  "\xfc\xed\x2d\x87\xbc\x04\x62\x97"
+			  "\x35\xe1\x26\xc2\x46\x1c\xcf\xd7"
+			  "\x14\xed\x02\x09\xa5\xb2\xb6\xaa"
+			  "\x27\x4e\x61\xb3\x71\x6b\x47\x16"
+			  "\xb7\xe8\xd4\xaf\x52\xeb\x6a\x6b"
+			  "\xdb\x4c\x65\x21\x9e\x1c\x36",
+		.klen	= 32,
+		.len	= 255,
+	},
+	{
+		.key	= "\xd3\x81\x72\x18\x23\xff\x6f\x4a"
+			  "\x25\x74\x29\x0d\x51\x8a\x0e\x13"
+			  "\xc1\x53\x5d\x30\x8d\xee\x75\x0d"
+			  "\x14\xd6\x69\xc9\x15\xa9\x0c\x60",
+		.iv	= "\x65\x9b\xd4\xa8\x7d\x29\x1d\xf4"
+			  "\xc4\xd6\x9b\x6a\x28\xab\x64\xe2"
+			  "\x62\x81\x97\xc5\x81\xaa\xf9\x44"
+			  "\xc1\x72\x59\x82\xaf\x16\xc8\x2c",
+		.ptext	= "\xc7\x6b\x52\x6a\x10\xf0\xcc\x09"
+			  "\xc1\x12\x1d\x6d\x21\xa6\x78\xf5"
+			  "\x05\xa3\x69\x60\x91\x36\x98\x57"
+			  "\xba\x0c\x14\xcc\xf3\x2d\x73\x03"
+			  "\xc6\xb2\x5f\xc8\x16\x27\x37\x5d"
+			  "\xd0\x0b\x87\xb2\x50\x94\x7b\x58"
+			  "\x04\xf4\xe0\x7f\x6e\x57\x8e\xc9"
+			  "\x41\x84\xc1\xb1\x7e\x4b\x91\x12"
+			  "\x3a\x8b\x5d\x50\x82\x7b\xcb\xd9"
+			  "\x9a\xd9\x4e\x18\x06\x23\x9e\xd4"
+			  "\xa5\x20\x98\xef\xb5\xda\xe5\xc0"
+			  "\x8a\x6a\x83\x77\x15\x84\x1e\xae"
+			  "\x78\x94\x9d\xdf\xb7\xd1\xea\x67"
+			  "\xaa\xb0\x14\x15\xfa\x67\x21\x84"
+			  "\xd3\x41\x2a\xce\xba\x4b\x4a\xe8"
+			  "\x95\x62\xa9\x55\xf0\x80\xad\xbd"
+			  "\xab\xaf\xdd\x4f\xa5\x7c\x13\x36"
+			  "\xed\x5e\x4f\x72\xad\x4b\xf1\xd0"
+			  "\x88\x4e\xec\x2c\x88\x10\x5e\xea"
+			  "\x12\xc0\x16\x01\x29\xa3\xa0\x55"
+			  "\xaa\x68\xf3\xe9\x9d\x3b\x0d\x3b"
+			  "\x6d\xec\xf8\xa0\x2d\xf0\x90\x8d"
+			  "\x1c\xe2\x88\xd4\x24\x71\xf9\xb3"
+			  "\xc1\x9f\xc5\xd6\x76\x70\xc5\x2e"
+			  "\x9c\xac\xdb\x90\xbd\x83\x72\xba"
+			  "\x6e\xb5\xa5\x53\x83\xa9\xa5\xbf"
+			  "\x7d\x06\x0e\x3c\x2a\xd2\x04\xb5"
+			  "\x1e\x19\x38\x09\x16\xd2\x82\x1f"
+			  "\x75\x18\x56\xb8\x96\x0b\xa6\xf9"
+			  "\xcf\x62\xd9\x32\x5d\xa9\xd7\x1d"
+			  "\xec\xe4\xdf\x1b\xbe\xf1\x36\xee"
+			  "\xe3\x7b\xb5\x2f\xee\xf8\x53\x3d"
+			  "\x6a\xb7\x70\xa9\xfc\x9c\x57\x25"
+			  "\xf2\x89\x10\xd3\xb8\xa8\x8c\x30"
+			  "\xae\x23\x4f\x0e\x13\x66\x4f\xe1"
+			  "\xb6\xc0\xe4\xf8\xef\x93\xbd\x6e"
+			  "\x15\x85\x6b\xe3\x60\x81\x1d\x68"
+			  "\xd7\x31\x87\x89\x09\xab\xd5\x96"
+			  "\x1d\xf3\x6d\x67\x80\xca\x07\x31"
+			  "\x5d\xa7\xe4\xfb\x3e\xf2\x9b\x33"
+			  "\x52\x18\xc8\x30\xfe\x2d\xca\x1e"
+			  "\x79\x92\x7a\x60\x5c\xb6\x58\x87"
+			  "\xa4\x36\xa2\x67\x92\x8b\xa4\xb7"
+			  "\xf1\x86\xdf\xdc\xc0\x7e\x8f\x63"
+			  "\xd2\xa2\xdc\x78\xeb\x4f\xd8\x96"
+			  "\x47\xca\xb8\x91\xf9\xf7\x94\x21"
+			  "\x5f\x9a\x9f\x5b\xb8\x40\x41\x4b"
+			  "\x66\x69\x6a\x72\xd0\xcb\x70\xb7"
+			  "\x93\xb5\x37\x96\x05\x37\x4f\xe5"
+			  "\x8c\xa7\x5a\x4e\x8b\xb7\x84\xea"
+			  "\xc7\xfc\x19\x6e\x1f\x5a\xa1\xac"
+			  "\x18\x7d\x52\x3b\xb3\x34\x62\x99"
+			  "\xe4\x9e\x31\x04\x3f\xc0\x8d\x84"
+			  "\x17\x7c\x25\x48\x52\x67\x11\x27"
+			  "\x67\xbb\x5a\x85\xca\x56\xb2\x5c"
+			  "\xe6\xec\xd5\x96\x3d\x15\xfc\xfb"
+			  "\x22\x25\xf4\x13\xe5\x93\x4b\x9a"
+			  "\x77\xf1\x52\x18\xfa\x16\x5e\x49"
+			  "\x03\x45\xa8\x08\xfa\xb3\x41\x92"
+			  "\x79\x50\x33\xca\xd0\xd7\x42\x55"
+			  "\xc3\x9a\x0c\x4e\xd9\xa4\x3c\x86"
+			  "\x80\x9f\x53\xd1\xa4\x2e\xd1\xbc"
+			  "\xf1\x54\x6e\x93\xa4\x65\x99\x8e"
+			  "\xdf\x29\xc0\x64\x63\x07\xbb\xea",
+		.ctext	= "\x9f\x72\x87\xc7\x17\xfb\x20\x15"
+			  "\x65\xb3\x55\xa8\x1c\x8e\x52\x32"
+			  "\xb1\x82\x8d\xbf\xb5\x9f\x10\x0a"
+			  "\xe8\x0c\x70\x62\xef\x89\xb6\x1f"
+			  "\x73\xcc\xe4\xcc\x7a\x3a\x75\x4a"
+			  "\x26\xe7\xf5\xd7\x7b\x17\x39\x2d"
+			  "\xd2\x27\x6e\xf9\x2f\x9e\xe2\xf6"
+			  "\xfa\x16\xc2\xf2\x49\x26\xa7\x5b"
+			  "\xe7\xca\x25\x0e\x45\xa0\x34\xc2"
+			  "\x9a\x37\x79\x7e\x7c\x58\x18\x94"
+			  "\x10\xa8\x7c\x48\xa9\xd7\x63\x89"
+			  "\x9e\x61\x4d\x26\x34\xd9\xf0\xb1"
+			  "\x2d\x17\x2c\x6f\x7c\x35\x0e\xbe"
+			  "\x77\x71\x7c\x17\x5b\xab\x70\xdb"
+			  "\x2f\x54\x0f\xa9\xc8\xf4\xf5\xab"
+			  "\x52\x04\x3a\xb8\x03\xa7\xfd\x57"
+			  "\x45\x5e\xbc\x77\xe1\xee\x79\x8c"
+			  "\x58\x7b\x1f\xf7\x75\xde\x68\x17"
+			  "\x98\x85\x8a\x18\x5c\xd2\x39\x78"
+			  "\x7a\x6f\x26\x6e\xe1\x13\x91\xdd"
+			  "\xdf\x0e\x6e\x67\xcc\x51\x53\xd8"
+			  "\x17\x5e\xce\xa7\xe4\xaf\xfa\xf3"
+			  "\x4f\x9f\x01\x9b\x04\xe7\xfc\xf9"
+			  "\x6a\xdc\x1d\x0c\x9a\xaa\x3a\x7a"
+			  "\x73\x03\xdf\xbf\x3b\x82\xbe\xb0"
+			  "\xb4\xa4\xcf\x07\xd7\xde\x71\x25"
+			  "\xc5\x10\xee\x0a\x15\x96\x8b\x4f"
+			  "\xfe\xb8\x28\xbd\x4a\xcd\xeb\x9f"
+			  "\x5d\x00\xc1\xee\xe8\x16\x44\xec"
+			  "\xe9\x7b\xd6\x85\x17\x29\xcf\x58"
+			  "\x20\xab\xf7\xce\x6b\xe7\x71\x7d"
+			  "\x4f\xa8\xb0\xe9\x7d\x70\xd6\x0b"
+			  "\x2e\x20\xb1\x1a\x63\x37\xaa\x2c"
+			  "\x94\xee\xd5\xf6\x58\x2a\xf4\x7a"
+			  "\x4c\xba\xf5\xe9\x3c\x6f\x95\x13"
+			  "\x5f\x96\x81\x5b\xb5\x62\xf2\xd7"
+			  "\x8d\xbe\xa1\x31\x51\xe6\xfe\xc9"
+			  "\x07\x7d\x0f\x00\x3a\x66\x8c\x4b"
+			  "\x94\xaa\xe5\x56\xde\xcd\x74\xa7"
+			  "\x48\x67\x6f\xed\xc9\x6a\xef\xaf"
+			  "\x9a\xb7\xae\x60\xfa\xc0\x37\x39"
+			  "\xa5\x25\xe5\x22\xea\x82\x55\x68"
+			  "\x3e\x30\xc3\x5a\xb6\x29\x73\x7a"
+			  "\xb6\xfb\x34\xee\x51\x7c\x54\xe5"
+			  "\x01\x4d\x72\x25\x32\x4a\xa3\x68"
+			  "\x80\x9a\x89\xc5\x11\x66\x4c\x8c"
+			  "\x44\x50\xbe\xd7\xa0\xee\xa6\xbb"
+			  "\x92\x0c\xe6\xd7\x83\x51\xb1\x69"
+			  "\x63\x40\xf3\xf4\x92\x84\xc4\x38"
+			  "\x29\xfb\xb4\x84\xa0\x19\x75\x16"
+			  "\x60\xbf\x0a\x9c\x89\xee\xad\xb4"
+			  "\x43\xf9\x71\x39\x45\x7c\x24\x83"
+			  "\x30\xbb\xee\x28\xb0\x86\x7b\xec"
+			  "\x93\xc1\xbf\xb9\x97\x1b\x96\xef"
+			  "\xee\x58\x35\x61\x12\x19\xda\x25"
+			  "\x77\xe5\x80\x1a\x31\x27\x9b\xe4"
+			  "\xda\x8b\x7e\x51\x4d\xcb\x01\x19"
+			  "\x4f\xdc\x92\x1a\x17\xd5\x6b\xf4"
+			  "\x50\xe3\x06\xe4\x76\x9f\x65\x00"
+			  "\xbd\x7a\xe2\x64\x26\xf2\xe4\x7e"
+			  "\x40\xf2\x80\xab\x62\xd5\xef\x23"
+			  "\x8b\xfb\x6f\x24\x6e\x9b\x66\x0e"
+			  "\xf4\x1c\x24\x1e\x1d\x26\x95\x09"
+			  "\x94\x3c\xb2\xb6\x02\xa7\xd9\x9a",
+		.klen	= 32,
+		.len	= 512,
+	},
+
+};
 
 #endif	/* _CRYPTO_TESTMGR_H */
diff --git a/crypto/xctr.c b/crypto/xctr.c
new file mode 100644
index 000000000000..5c00147e8ec4
--- /dev/null
+++ b/crypto/xctr.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * XCTR: XOR Counter mode - Adapted from ctr.c
+ *
+ * (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
+ * Copyright 2021 Google LLC
+ */
+
+/*
+ * XCTR mode is a blockcipher mode of operation used to implement HCTR2. XCTR is
+ * closely related to the CTR mode of operation; the main difference is that CTR
+ * generates the keystream using E(CTR + IV) whereas XCTR generates the
+ * keystream using E(CTR ^ IV). This allows implementations to avoid dealing
+ * with multi-limb integers (as is required in CTR mode). XCTR is also specified
+ * using little-endian arithmetic which makes it slightly faster on LE machines.
+ *
+ * See the HCTR2 paper for more details:
+ *	Length-preserving encryption with HCTR2
+ *      (https://eprint.iacr.org/2021/1441.pdf)
+ */
+
+#include <crypto/algapi.h>
+#include <crypto/internal/cipher.h>
+#include <crypto/internal/skcipher.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+/* For now this implementation is limited to 16-byte blocks for simplicity */
+#define XCTR_BLOCKSIZE 16
+
+static void crypto_xctr_crypt_final(struct skcipher_walk *walk,
+				   struct crypto_cipher *tfm, u32 byte_ctr)
+{
+	u8 keystream[XCTR_BLOCKSIZE];
+	const u8 *src = walk->src.virt.addr;
+	u8 *dst = walk->dst.virt.addr;
+	unsigned int nbytes = walk->nbytes;
+	__le32 ctr32 = cpu_to_le32(byte_ctr / XCTR_BLOCKSIZE + 1);
+
+	crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+	crypto_cipher_encrypt_one(tfm, keystream, walk->iv);
+	crypto_xor_cpy(dst, keystream, src, nbytes);
+	crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+}
+
+static int crypto_xctr_crypt_segment(struct skcipher_walk *walk,
+				    struct crypto_cipher *tfm, u32 byte_ctr)
+{
+	void (*fn)(struct crypto_tfm *, u8 *, const u8 *) =
+		   crypto_cipher_alg(tfm)->cia_encrypt;
+	const u8 *src = walk->src.virt.addr;
+	u8 *dst = walk->dst.virt.addr;
+	unsigned int nbytes = walk->nbytes;
+	__le32 ctr32 = cpu_to_le32(byte_ctr / XCTR_BLOCKSIZE + 1);
+
+	do {
+		crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+		fn(crypto_cipher_tfm(tfm), dst, walk->iv);
+		crypto_xor(dst, src, XCTR_BLOCKSIZE);
+		crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+
+		le32_add_cpu(&ctr32, 1);
+
+		src += XCTR_BLOCKSIZE;
+		dst += XCTR_BLOCKSIZE;
+	} while ((nbytes -= XCTR_BLOCKSIZE) >= XCTR_BLOCKSIZE);
+
+	return nbytes;
+}
+
+static int crypto_xctr_crypt_inplace(struct skcipher_walk *walk,
+				    struct crypto_cipher *tfm, u32 byte_ctr)
+{
+	void (*fn)(struct crypto_tfm *, u8 *, const u8 *) =
+		   crypto_cipher_alg(tfm)->cia_encrypt;
+	unsigned long alignmask = crypto_cipher_alignmask(tfm);
+	unsigned int nbytes = walk->nbytes;
+	u8 *data = walk->src.virt.addr;
+	u8 tmp[XCTR_BLOCKSIZE + MAX_CIPHER_ALIGNMASK];
+	u8 *keystream = PTR_ALIGN(tmp + 0, alignmask + 1);
+	__le32 ctr32 = cpu_to_le32(byte_ctr / XCTR_BLOCKSIZE + 1);
+
+	do {
+		crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+		fn(crypto_cipher_tfm(tfm), keystream, walk->iv);
+		crypto_xor(data, keystream, XCTR_BLOCKSIZE);
+		crypto_xor(walk->iv, (u8 *)&ctr32, sizeof(ctr32));
+
+		le32_add_cpu(&ctr32, 1);
+
+		data += XCTR_BLOCKSIZE;
+	} while ((nbytes -= XCTR_BLOCKSIZE) >= XCTR_BLOCKSIZE);
+
+	return nbytes;
+}
+
+static int crypto_xctr_crypt(struct skcipher_request *req)
+{
+	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+	struct crypto_cipher *cipher = skcipher_cipher_simple(tfm);
+	struct skcipher_walk walk;
+	unsigned int nbytes;
+	int err;
+	u32 byte_ctr = 0;
+
+	err = skcipher_walk_virt(&walk, req, false);
+
+	while (walk.nbytes >= XCTR_BLOCKSIZE) {
+		if (walk.src.virt.addr == walk.dst.virt.addr)
+			nbytes = crypto_xctr_crypt_inplace(&walk, cipher,
+							   byte_ctr);
+		else
+			nbytes = crypto_xctr_crypt_segment(&walk, cipher,
+							   byte_ctr);
+
+		byte_ctr += walk.nbytes - nbytes;
+		err = skcipher_walk_done(&walk, nbytes);
+	}
+
+	if (walk.nbytes) {
+		crypto_xctr_crypt_final(&walk, cipher, byte_ctr);
+		err = skcipher_walk_done(&walk, 0);
+	}
+
+	return err;
+}
+
+static int crypto_xctr_create(struct crypto_template *tmpl, struct rtattr **tb)
+{
+	struct skcipher_instance *inst;
+	struct crypto_alg *alg;
+	int err;
+
+	inst = skcipher_alloc_instance_simple(tmpl, tb);
+	if (IS_ERR(inst))
+		return PTR_ERR(inst);
+
+	alg = skcipher_ialg_simple(inst);
+
+	/* Block size must be 16 bytes. */
+	err = -EINVAL;
+	if (alg->cra_blocksize != XCTR_BLOCKSIZE)
+		goto out_free_inst;
+
+	/* XCTR mode is a stream cipher. */
+	inst->alg.base.cra_blocksize = 1;
+
+	/*
+	 * To simplify the implementation, configure the skcipher walk to only
+	 * give a partial block at the very end, never earlier.
+	 */
+	inst->alg.chunksize = alg->cra_blocksize;
+
+	inst->alg.encrypt = crypto_xctr_crypt;
+	inst->alg.decrypt = crypto_xctr_crypt;
+
+	err = skcipher_register_instance(tmpl, inst);
+	if (err) {
+out_free_inst:
+		inst->free(inst);
+	}
+
+	return err;
+}
+
+static struct crypto_template crypto_xctr_tmpl = {
+	.name = "xctr",
+	.create = crypto_xctr_create,
+	.module = THIS_MODULE,
+};
+
+static int __init crypto_xctr_module_init(void)
+{
+	return crypto_register_template(&crypto_xctr_tmpl);
+}
+
+static void __exit crypto_xctr_module_exit(void)
+{
+	crypto_unregister_template(&crypto_xctr_tmpl);
+}
+
+subsys_initcall(crypto_xctr_module_init);
+module_exit(crypto_xctr_module_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("XCTR block cipher mode of operation");
+MODULE_ALIAS_CRYPTO("xctr");
+MODULE_IMPORT_NS(CRYPTO_INTERNAL);
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b6a172d32a7d..19ee995bd0ae 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -183,8 +183,6 @@ source "drivers/iio/Kconfig"
 
 source "drivers/ntb/Kconfig"
 
-source "drivers/vme/Kconfig"
-
 source "drivers/pwm/Kconfig"
 
 source "drivers/irqchip/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 9a30842b22c5..dadf2678277f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -165,7 +165,6 @@ obj-$(CONFIG_PM_DEVFREQ)	+= devfreq/
 obj-$(CONFIG_EXTCON)		+= extcon/
 obj-$(CONFIG_MEMORY)		+= memory/
 obj-$(CONFIG_IIO)		+= iio/
-obj-$(CONFIG_VME_BUS)		+= vme/
 obj-$(CONFIG_IPACK_BUS)		+= ipack/
 obj-$(CONFIG_NTB)		+= ntb/
 obj-$(CONFIG_POWERCAP)		+= powercap/
diff --git a/drivers/accessibility/braille/braille_console.c b/drivers/accessibility/braille/braille_console.c
index fdc6b593f500..c4d54a5326b1 100644
--- a/drivers/accessibility/braille/braille_console.c
+++ b/drivers/accessibility/braille/braille_console.c
@@ -131,7 +131,7 @@ static void vc_refresh(struct vc_data *vc)
 	for (i = 0; i < WIDTH; i++) {
 		u16 glyph = screen_glyph(vc,
 				2 * (vc_x + i) + vc_y * vc->vc_size_row);
-		buf[i] = inverse_translate(vc, glyph, 1);
+		buf[i] = inverse_translate(vc, glyph, true);
 	}
 	braille_write(buf);
 }
diff --git a/drivers/accessibility/speakup/main.c b/drivers/accessibility/speakup/main.c
index d726537fa16c..f52265293482 100644
--- a/drivers/accessibility/speakup/main.c
+++ b/drivers/accessibility/speakup/main.c
@@ -470,7 +470,7 @@ static u16 get_char(struct vc_data *vc, u16 *pos, u_char *attribs)
 			c |= 0x100;
 		}
 
-		ch = inverse_translate(vc, c, 1);
+		ch = inverse_translate(vc, c, true);
 		*attribs = (w & 0xff00) >> 8;
 	}
 	return ch;
diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
index e07782b1fbb6..7e3cab70b718 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video.c
@@ -1149,24 +1149,25 @@ acpi_video_get_device_type(struct acpi_video_bus *video,
 	return 0;
 }
 
-static int
-acpi_video_bus_get_one_device(struct acpi_device *device,
-			      struct acpi_video_bus *video)
+static int acpi_video_bus_get_one_device(struct acpi_device *device, void *arg)
 {
-	unsigned long long device_id;
-	int status, device_type;
-	struct acpi_video_device *data;
+	struct acpi_video_bus *video = arg;
 	struct acpi_video_device_attrib *attribute;
+	struct acpi_video_device *data;
+	unsigned long long device_id;
+	acpi_status status;
+	int device_type;
 
-	status =
-	    acpi_evaluate_integer(device->handle, "_ADR", NULL, &device_id);
-	/* Some device omits _ADR, we skip them instead of fail */
+	status = acpi_evaluate_integer(device->handle, "_ADR", NULL, &device_id);
+	/* Skip devices without _ADR instead of failing. */
 	if (ACPI_FAILURE(status))
-		return 0;
+		goto exit;
 
 	data = kzalloc(sizeof(struct acpi_video_device), GFP_KERNEL);
-	if (!data)
+	if (!data) {
+		dev_dbg(&device->dev, "Cannot attach\n");
 		return -ENOMEM;
+	}
 
 	strcpy(acpi_device_name(device), ACPI_VIDEO_DEVICE_NAME);
 	strcpy(acpi_device_class(device), ACPI_VIDEO_CLASS);
@@ -1226,7 +1227,9 @@ acpi_video_bus_get_one_device(struct acpi_device *device,
 	list_add_tail(&data->entry, &video->video_device_list);
 	mutex_unlock(&video->device_list_lock);
 
-	return status;
+exit:
+	video->child_count++;
+	return 0;
 }
 
 /*
@@ -1538,9 +1541,6 @@ static int
 acpi_video_bus_get_devices(struct acpi_video_bus *video,
 			   struct acpi_device *device)
 {
-	int status = 0;
-	struct acpi_device *dev;
-
 	/*
 	 * There are systems where video module known to work fine regardless
 	 * of broken _DOD and ignoring returned value here doesn't cause
@@ -1548,16 +1548,7 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video,
 	 */
 	acpi_video_device_enumerate(video);
 
-	list_for_each_entry(dev, &device->children, node) {
-
-		status = acpi_video_bus_get_one_device(dev, video);
-		if (status) {
-			dev_err(&dev->dev, "Can't attach device\n");
-			break;
-		}
-		video->child_count++;
-	}
-	return status;
+	return acpi_dev_for_each_child(device, acpi_video_bus_get_one_device, video);
 }
 
 /* acpi_video interface */
diff --git a/drivers/acpi/apei/apei-base.c b/drivers/acpi/apei/apei-base.c
index 33b7fbbeda82..9f49272cad39 100644
--- a/drivers/acpi/apei/apei-base.c
+++ b/drivers/acpi/apei/apei-base.c
@@ -3,7 +3,7 @@
  * apei-base.c - ACPI Platform Error Interface (APEI) supporting
  * infrastructure
  *
- * APEI allows to report errors (for example from the chipset) to the
+ * APEI allows to report errors (for example from the chipset) to
  * the operating system. This improves NMI handling especially. In
  * addition it supports error serialization and error injection.
  *
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 86fa61a21826..4d7c51a33b01 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1102,6 +1102,7 @@ static int acpi_dev_for_one_check(struct device *dev, void *context)
 
 	return adwc->fn(to_acpi_device(dev), adwc->data);
 }
+EXPORT_SYMBOL_GPL(acpi_dev_for_each_child);
 
 int acpi_dev_for_each_child(struct acpi_device *adev,
 			    int (*fn)(struct acpi_device *, void *), void *data)
@@ -1114,6 +1115,18 @@ int acpi_dev_for_each_child(struct acpi_device *adev,
 	return device_for_each_child(&adev->dev, &adwc, acpi_dev_for_one_check);
 }
 
+int acpi_dev_for_each_child_reverse(struct acpi_device *adev,
+				    int (*fn)(struct acpi_device *, void *),
+				    void *data)
+{
+	struct acpi_dev_walk_context adwc = {
+		.fn = fn,
+		.data = data,
+	};
+
+	return device_for_each_child_reverse(&adev->dev, &adwc, acpi_dev_for_one_check);
+}
+
 /* --------------------------------------------------------------------------
                              Initialization/Cleanup
    -------------------------------------------------------------------------- */
diff --git a/drivers/acpi/container.c b/drivers/acpi/container.c
index ccaa647ac3d4..5b7e3b9ae370 100644
--- a/drivers/acpi/container.c
+++ b/drivers/acpi/container.c
@@ -23,17 +23,18 @@ static const struct acpi_device_id container_device_ids[] = {
 
 #ifdef CONFIG_ACPI_CONTAINER
 
-static int acpi_container_offline(struct container_dev *cdev)
+static int check_offline(struct acpi_device *adev, void *not_used)
 {
-	struct acpi_device *adev = ACPI_COMPANION(&cdev->dev);
-	struct acpi_device *child;
+	if (acpi_scan_is_offline(adev, false))
+		return 0;
 
-	/* Check all of the dependent devices' physical companions. */
-	list_for_each_entry(child, &adev->children, node)
-		if (!acpi_scan_is_offline(child, false))
-			return -EBUSY;
+	return -EBUSY;
+}
 
-	return 0;
+static int acpi_container_offline(struct container_dev *cdev)
+{
+	/* Check all of the dependent devices' physical companions. */
+	return acpi_dev_for_each_child(ACPI_COMPANION(&cdev->dev), check_offline, NULL);
 }
 
 static void acpi_container_release(struct device *dev)
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index 130b5f4a50a3..9dce1245689c 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -369,6 +369,28 @@ int acpi_device_fix_up_power(struct acpi_device *device)
 }
 EXPORT_SYMBOL_GPL(acpi_device_fix_up_power);
 
+static int fix_up_power_if_applicable(struct acpi_device *adev, void *not_used)
+{
+	if (adev->status.present && adev->status.enabled)
+		acpi_device_fix_up_power(adev);
+
+	return 0;
+}
+
+/**
+ * acpi_device_fix_up_power_extended - Force device and its children into D0.
+ * @adev: Parent device object whose power state is to be fixed up.
+ *
+ * Call acpi_device_fix_up_power() for @adev and its children so long as they
+ * are reported as present and enabled.
+ */
+void acpi_device_fix_up_power_extended(struct acpi_device *adev)
+{
+	acpi_device_fix_up_power(adev);
+	acpi_dev_for_each_child(adev, fix_up_power_if_applicable, NULL);
+}
+EXPORT_SYMBOL_GPL(acpi_device_fix_up_power_extended);
+
 int acpi_device_update_power(struct acpi_device *device, int *state_p)
 {
 	int state;
diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c
index 8d769114a048..204fe94c7e45 100644
--- a/drivers/acpi/glue.c
+++ b/drivers/acpi/glue.c
@@ -77,12 +77,22 @@ static struct acpi_bus_type *acpi_get_bus_type(struct device *dev)
 #define FIND_CHILD_MIN_SCORE	1
 #define FIND_CHILD_MAX_SCORE	2
 
+static int match_any(struct acpi_device *adev, void *not_used)
+{
+	return 1;
+}
+
+static bool acpi_dev_has_children(struct acpi_device *adev)
+{
+	return acpi_dev_for_each_child(adev, match_any, NULL) > 0;
+}
+
 static int find_child_checks(struct acpi_device *adev, bool check_children)
 {
 	unsigned long long sta;
 	acpi_status status;
 
-	if (check_children && list_empty(&adev->children))
+	if (check_children && !acpi_dev_has_children(adev))
 		return -ENODEV;
 
 	status = acpi_evaluate_integer(adev->handle, "_STA", NULL, &sta);
@@ -105,54 +115,97 @@ static int find_child_checks(struct acpi_device *adev, bool check_children)
 	return FIND_CHILD_MAX_SCORE;
 }
 
-struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
-					   u64 address, bool check_children)
-{
-	struct acpi_device *adev, *ret = NULL;
-	int ret_score = 0;
-
-	if (!parent)
-		return NULL;
+struct find_child_walk_data {
+	struct acpi_device *adev;
+	u64 address;
+	int score;
+	bool check_sta;
+	bool check_children;
+};
 
-	list_for_each_entry(adev, &parent->children, node) {
-		acpi_bus_address addr = acpi_device_adr(adev);
-		int score;
+static int check_one_child(struct acpi_device *adev, void *data)
+{
+	struct find_child_walk_data *wd = data;
+	int score;
 
-		if (!adev->pnp.type.bus_address || addr != address)
-			continue;
+	if (!adev->pnp.type.bus_address || acpi_device_adr(adev) != wd->address)
+		return 0;
 
-		if (!ret) {
-			/* This is the first matching object.  Save it. */
-			ret = adev;
-			continue;
-		}
+	if (!wd->adev) {
 		/*
-		 * There is more than one matching device object with the same
-		 * _ADR value.  That really is unexpected, so we are kind of
-		 * beyond the scope of the spec here.  We have to choose which
-		 * one to return, though.
-		 *
-		 * First, check if the previously found object is good enough
-		 * and return it if so.  Second, do the same for the object that
-		 * we've just found.
+		 * This is the first matching object, so save it.  If it is not
+		 * necessary to look for any other matching objects, stop the
+		 * search.
 		 */
-		if (!ret_score) {
-			ret_score = find_child_checks(ret, check_children);
-			if (ret_score == FIND_CHILD_MAX_SCORE)
-				return ret;
-		}
-		score = find_child_checks(adev, check_children);
-		if (score == FIND_CHILD_MAX_SCORE) {
-			return adev;
-		} else if (score > ret_score) {
-			ret = adev;
-			ret_score = score;
-		}
+		wd->adev = adev;
+		return !(wd->check_sta || wd->check_children);
 	}
-	return ret;
+
+	/*
+	 * There is more than one matching device object with the same _ADR
+	 * value.  That really is unexpected, so we are kind of beyond the scope
+	 * of the spec here.  We have to choose which one to return, though.
+	 *
+	 * First, get the score for the previously found object and terminate
+	 * the walk if it is maximum.
+	*/
+	if (!wd->score) {
+		score = find_child_checks(wd->adev, wd->check_children);
+		if (score == FIND_CHILD_MAX_SCORE)
+			return 1;
+
+		wd->score = score;
+	}
+	/*
+	 * Second, if the object that has just been found has a better score,
+	 * replace the previously found one with it and terminate the walk if
+	 * the new score is maximum.
+	 */
+	score = find_child_checks(adev, wd->check_children);
+	if (score > wd->score) {
+		wd->adev = adev;
+		if (score == FIND_CHILD_MAX_SCORE)
+			return 1;
+
+		wd->score = score;
+	}
+
+	/* Continue, because there may be better matches. */
+	return 0;
+}
+
+static struct acpi_device *acpi_find_child(struct acpi_device *parent,
+					   u64 address, bool check_children,
+					   bool check_sta)
+{
+	struct find_child_walk_data wd = {
+		.address = address,
+		.check_children = check_children,
+		.check_sta = check_sta,
+		.adev = NULL,
+		.score = 0,
+	};
+
+	if (parent)
+		acpi_dev_for_each_child(parent, check_one_child, &wd);
+
+	return wd.adev;
+}
+
+struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
+					   u64 address, bool check_children)
+{
+	return acpi_find_child(parent, address, check_children, true);
 }
 EXPORT_SYMBOL_GPL(acpi_find_child_device);
 
+struct acpi_device *acpi_find_child_by_adr(struct acpi_device *adev,
+					   acpi_bus_address adr)
+{
+	return acpi_find_child(adev, adr, false, false);
+}
+EXPORT_SYMBOL_GPL(acpi_find_child_by_adr);
+
 static void acpi_physnode_link_name(char *buf, unsigned int node_id)
 {
 	if (node_id > 0)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 6a5572a1a80c..16a1663d02d4 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -23,6 +23,7 @@
 #include <linux/minmax.h>
 #include <linux/perf_event.h>
 #include <acpi/processor.h>
+#include <linux/context_tracking.h>
 
 /*
  * Include the apic definitions for x86 to have the APIC timer related defines
@@ -607,7 +608,7 @@ static DEFINE_RAW_SPINLOCK(c3_lock);
  * @cx: Target state context
  * @index: index of target state
  */
-static int acpi_idle_enter_bm(struct cpuidle_driver *drv,
+static int __cpuidle acpi_idle_enter_bm(struct cpuidle_driver *drv,
 			       struct acpi_processor *pr,
 			       struct acpi_processor_cx *cx,
 			       int index)
@@ -647,11 +648,11 @@ static int acpi_idle_enter_bm(struct cpuidle_driver *drv,
 		raw_spin_unlock(&c3_lock);
 	}
 
-	rcu_idle_enter();
+	ct_idle_enter();
 
 	acpi_idle_do_entry(cx);
 
-	rcu_idle_exit();
+	ct_idle_exit();
 
 	/* Re-enable bus master arbitration */
 	if (dis_bm) {
@@ -664,7 +665,7 @@ static int acpi_idle_enter_bm(struct cpuidle_driver *drv,
 	return index;
 }
 
-static int acpi_idle_enter(struct cpuidle_device *dev,
+static int __cpuidle acpi_idle_enter(struct cpuidle_device *dev,
 			   struct cpuidle_driver *drv, int index)
 {
 	struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
@@ -693,7 +694,7 @@ static int acpi_idle_enter(struct cpuidle_device *dev,
 	return index;
 }
 
-static int acpi_idle_enter_s2idle(struct cpuidle_device *dev,
+static int __cpuidle acpi_idle_enter_s2idle(struct cpuidle_device *dev,
 				  struct cpuidle_driver *drv, int index)
 {
 	struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
index d3173811614e..e764f9ac9cf8 100644
--- a/drivers/acpi/property.c
+++ b/drivers/acpi/property.c
@@ -1012,6 +1012,22 @@ static int acpi_node_prop_read(const struct fwnode_handle *fwnode,
 				   propname, proptype, val, nval);
 }
 
+static int stop_on_next(struct acpi_device *adev, void *data)
+{
+	struct acpi_device **ret_p = data;
+
+	if (!*ret_p) {
+		*ret_p = adev;
+		return 1;
+	}
+
+	/* Skip until the "previous" object is found. */
+	if (*ret_p == adev)
+		*ret_p = NULL;
+
+	return 0;
+}
+
 /**
  * acpi_get_next_subnode - Return the next child node handle for a fwnode
  * @fwnode: Firmware node to find the next child node for.
@@ -1020,35 +1036,22 @@ static int acpi_node_prop_read(const struct fwnode_handle *fwnode,
 struct fwnode_handle *acpi_get_next_subnode(const struct fwnode_handle *fwnode,
 					    struct fwnode_handle *child)
 {
-	const struct acpi_device *adev = to_acpi_device_node(fwnode);
-	const struct list_head *head;
-	struct list_head *next;
+	struct acpi_device *adev = to_acpi_device_node(fwnode);
 
 	if ((!child || is_acpi_device_node(child)) && adev) {
-		struct acpi_device *child_adev;
+		struct acpi_device *child_adev = to_acpi_device_node(child);
 
-		head = &adev->children;
-		if (list_empty(head))
-			goto nondev;
+		acpi_dev_for_each_child(adev, stop_on_next, &child_adev);
+		if (child_adev)
+			return acpi_fwnode_handle(child_adev);
 
-		if (child) {
-			adev = to_acpi_device_node(child);
-			next = adev->node.next;
-			if (next == head) {
-				child = NULL;
-				goto nondev;
-			}
-			child_adev = list_entry(next, struct acpi_device, node);
-		} else {
-			child_adev = list_first_entry(head, struct acpi_device,
-						      node);
-		}
-		return acpi_fwnode_handle(child_adev);
+		child = NULL;
 	}
 
- nondev:
 	if (!child || is_acpi_data_node(child)) {
 		const struct acpi_data_node *data = to_acpi_data_node(fwnode);
+		const struct list_head *head;
+		struct list_head *next;
 		struct acpi_data_node *dn;
 
 		/*
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 762b61f67e6c..7b085826d881 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -334,10 +334,9 @@ static int acpi_scan_device_check(struct acpi_device *adev)
 	return error;
 }
 
-static int acpi_scan_bus_check(struct acpi_device *adev)
+static int acpi_scan_bus_check(struct acpi_device *adev, void *not_used)
 {
 	struct acpi_scan_handler *handler = adev->handler;
-	struct acpi_device *child;
 	int error;
 
 	acpi_bus_get_status(adev);
@@ -353,19 +352,14 @@ static int acpi_scan_bus_check(struct acpi_device *adev)
 		dev_warn(&adev->dev, "Namespace scan failure\n");
 		return error;
 	}
-	list_for_each_entry(child, &adev->children, node) {
-		error = acpi_scan_bus_check(child);
-		if (error)
-			return error;
-	}
-	return 0;
+	return acpi_dev_for_each_child(adev, acpi_scan_bus_check, NULL);
 }
 
 static int acpi_generic_hotplug_event(struct acpi_device *adev, u32 type)
 {
 	switch (type) {
 	case ACPI_NOTIFY_BUS_CHECK:
-		return acpi_scan_bus_check(adev);
+		return acpi_scan_bus_check(adev, NULL);
 	case ACPI_NOTIFY_DEVICE_CHECK:
 		return acpi_scan_device_check(adev);
 	case ACPI_NOTIFY_EJECT_REQUEST:
@@ -2187,9 +2181,8 @@ static int acpi_scan_attach_handler(struct acpi_device *device)
 	return ret;
 }
 
-static void acpi_bus_attach(struct acpi_device *device, bool first_pass)
+static int acpi_bus_attach(struct acpi_device *device, void *first_pass)
 {
-	struct acpi_device *child;
 	bool skip = !first_pass && device->flags.visited;
 	acpi_handle ejd;
 	int ret;
@@ -2206,7 +2199,7 @@ static void acpi_bus_attach(struct acpi_device *device, bool first_pass)
 		device->flags.initialized = false;
 		acpi_device_clear_enumerated(device);
 		device->flags.power_manageable = 0;
-		return;
+		return 0;
 	}
 	if (device->handler)
 		goto ok;
@@ -2224,7 +2217,7 @@ static void acpi_bus_attach(struct acpi_device *device, bool first_pass)
 
 	ret = acpi_scan_attach_handler(device);
 	if (ret < 0)
-		return;
+		return 0;
 
 	device->flags.match_driver = true;
 	if (ret > 0 && !device->flags.enumeration_by_parent) {
@@ -2234,19 +2227,20 @@ static void acpi_bus_attach(struct acpi_device *device, bool first_pass)
 
 	ret = device_attach(&device->dev);
 	if (ret < 0)
-		return;
+		return 0;
 
 	if (device->pnp.type.platform_id || device->flags.enumeration_by_parent)
 		acpi_default_enumeration(device);
 	else
 		acpi_device_set_enumerated(device);
 
- ok:
-	list_for_each_entry(child, &device->children, node)
-		acpi_bus_attach(child, first_pass);
+ok:
+	acpi_dev_for_each_child(device, acpi_bus_attach, first_pass);
 
 	if (!skip && device->handler && device->handler->hotplug.notify_online)
 		device->handler->hotplug.notify_online(device);
+
+	return 0;
 }
 
 static int acpi_dev_get_first_consumer_dev_cb(struct acpi_dep_data *dep, void *data)
@@ -2274,7 +2268,7 @@ static void acpi_scan_clear_dep_fn(struct work_struct *work)
 	cdw = container_of(work, struct acpi_scan_clear_dep_work, work);
 
 	acpi_scan_lock_acquire();
-	acpi_bus_attach(cdw->adev, true);
+	acpi_bus_attach(cdw->adev, (void *)true);
 	acpi_scan_lock_release();
 
 	acpi_dev_put(cdw->adev);
@@ -2432,7 +2426,7 @@ int acpi_bus_scan(acpi_handle handle)
 	if (!device)
 		return -ENODEV;
 
-	acpi_bus_attach(device, true);
+	acpi_bus_attach(device, (void *)true);
 
 	if (!acpi_bus_scan_second_pass)
 		return 0;
@@ -2446,25 +2440,17 @@ int acpi_bus_scan(acpi_handle handle)
 				    acpi_bus_check_add_2, NULL, NULL,
 				    (void **)&device);
 
-	acpi_bus_attach(device, false);
+	acpi_bus_attach(device, NULL);
 
 	return 0;
 }
 EXPORT_SYMBOL(acpi_bus_scan);
 
-/**
- * acpi_bus_trim - Detach scan handlers and drivers from ACPI device objects.
- * @adev: Root of the ACPI namespace scope to walk.
- *
- * Must be called under acpi_scan_lock.
- */
-void acpi_bus_trim(struct acpi_device *adev)
+static int acpi_bus_trim_one(struct acpi_device *adev, void *not_used)
 {
 	struct acpi_scan_handler *handler = adev->handler;
-	struct acpi_device *child;
 
-	list_for_each_entry_reverse(child, &adev->children, node)
-		acpi_bus_trim(child);
+	acpi_dev_for_each_child_reverse(adev, acpi_bus_trim_one, NULL);
 
 	adev->flags.match_driver = false;
 	if (handler) {
@@ -2482,6 +2468,19 @@ void acpi_bus_trim(struct acpi_device *adev)
 	acpi_device_set_power(adev, ACPI_STATE_D3_COLD);
 	adev->flags.initialized = false;
 	acpi_device_clear_enumerated(adev);
+
+	return 0;
+}
+
+/**
+ * acpi_bus_trim - Detach scan handlers and drivers from ACPI device objects.
+ * @adev: Root of the ACPI namespace scope to walk.
+ *
+ * Must be called under acpi_scan_lock.
+ */
+void acpi_bus_trim(struct acpi_device *adev)
+{
+	acpi_bus_trim_one(adev, NULL);
 }
 EXPORT_SYMBOL_GPL(acpi_bus_trim);
 
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 0e3ed5eb367b..0cb20324da16 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -493,13 +493,8 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent)
 		goto skip_probe;
 
 	ret = amba_read_periphid(dev);
-	if (ret) {
-		if (ret != -EPROBE_DEFER) {
-			amba_device_put(dev);
-			goto err_out;
-		}
+	if (ret)
 		goto err_release;
-	}
 
 skip_probe:
 	ret = device_add(&dev->dev);
@@ -546,6 +541,7 @@ static int amba_deferred_retry(void)
 			continue;
 
 		list_del_init(&ddev->node);
+		amba_device_put(ddev->dev);
 		kfree(ddev);
 	}
 
diff --git a/drivers/android/Kconfig b/drivers/android/Kconfig
index 53b22e26266c..bc10eebd3ad3 100644
--- a/drivers/android/Kconfig
+++ b/drivers/android/Kconfig
@@ -20,6 +20,12 @@ config ANDROID_BINDER_IPC
 	  Android process, using Binder to identify, invoke and pass arguments
 	  between said processes.
 
+config ANDROID_BINDER_IPC_RUST
+	bool "Android Binder IPC Driver in Rust"
+	depends on MMU && RUST
+	help
+	  Implementation of the Binder IPC in Rust.
+
 config ANDROID_BINDERFS
 	bool "Android Binderfs filesystem"
 	depends on ANDROID_BINDER_IPC
diff --git a/drivers/android/Makefile b/drivers/android/Makefile
index c9d3d0c99c25..c428f2ce2f05 100644
--- a/drivers/android/Makefile
+++ b/drivers/android/Makefile
@@ -4,3 +4,5 @@ ccflags-y += -I$(src)			# needed for trace events
 obj-$(CONFIG_ANDROID_BINDERFS)		+= binderfs.o
 obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o binder_alloc.o
 obj-$(CONFIG_ANDROID_BINDER_IPC_SELFTEST) += binder_alloc_selftest.o
+
+obj-$(CONFIG_ANDROID_BINDER_IPC_RUST) += rust_binder.o
diff --git a/drivers/android/allocation.rs b/drivers/android/allocation.rs
new file mode 100644
index 000000000000..3ed7b649eeb7
--- /dev/null
+++ b/drivers/android/allocation.rs
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::mem::{replace, size_of, MaybeUninit};
+use kernel::{
+    bindings, linked_list::List, pages::Pages, prelude::*, sync::Ref, user_ptr::UserSlicePtrReader,
+};
+
+use crate::{
+    defs::*,
+    node::NodeRef,
+    process::{AllocationInfo, Process},
+    thread::{BinderError, BinderResult},
+    transaction::FileInfo,
+};
+
+pub(crate) struct Allocation<'a> {
+    pub(crate) offset: usize,
+    size: usize,
+    pub(crate) ptr: usize,
+    pages: Ref<[Pages<0>]>,
+    pub(crate) process: &'a Process,
+    allocation_info: Option<AllocationInfo>,
+    free_on_drop: bool,
+    file_list: List<Box<FileInfo>>,
+}
+
+impl<'a> Allocation<'a> {
+    pub(crate) fn new(
+        process: &'a Process,
+        offset: usize,
+        size: usize,
+        ptr: usize,
+        pages: Ref<[Pages<0>]>,
+    ) -> Self {
+        Self {
+            process,
+            offset,
+            size,
+            ptr,
+            pages,
+            allocation_info: None,
+            free_on_drop: true,
+            file_list: List::new(),
+        }
+    }
+
+    pub(crate) fn take_file_list(&mut self) -> List<Box<FileInfo>> {
+        replace(&mut self.file_list, List::new())
+    }
+
+    pub(crate) fn add_file_info(&mut self, file: Box<FileInfo>) {
+        self.file_list.push_back(file);
+    }
+
+    fn iterate<T>(&self, mut offset: usize, mut size: usize, mut cb: T) -> Result
+    where
+        T: FnMut(&Pages<0>, usize, usize) -> Result,
+    {
+        // Check that the request is within the buffer.
+        if offset.checked_add(size).ok_or(EINVAL)? > self.size {
+            return Err(EINVAL);
+        }
+        offset += self.offset;
+        let mut page_index = offset >> bindings::PAGE_SHIFT;
+        offset &= (1 << bindings::PAGE_SHIFT) - 1;
+        while size > 0 {
+            let available = core::cmp::min(size, (1 << bindings::PAGE_SHIFT) as usize - offset);
+            cb(&self.pages[page_index], offset, available)?;
+            size -= available;
+            page_index += 1;
+            offset = 0;
+        }
+        Ok(())
+    }
+
+    pub(crate) fn copy_into(
+        &self,
+        reader: &mut UserSlicePtrReader,
+        offset: usize,
+        size: usize,
+    ) -> Result {
+        self.iterate(offset, size, |page, offset, to_copy| {
+            page.copy_into_page(reader, offset, to_copy)
+        })
+    }
+
+    pub(crate) fn read<T>(&self, offset: usize) -> Result<T> {
+        let mut out = MaybeUninit::<T>::uninit();
+        let mut out_offset = 0;
+        self.iterate(offset, size_of::<T>(), |page, offset, to_copy| {
+            // SAFETY: Data buffer is allocated on the stack.
+            unsafe {
+                page.read(
+                    (out.as_mut_ptr() as *mut u8).add(out_offset),
+                    offset,
+                    to_copy,
+                )
+            }?;
+            out_offset += to_copy;
+            Ok(())
+        })?;
+        // SAFETY: We just initialised the data.
+        Ok(unsafe { out.assume_init() })
+    }
+
+    pub(crate) fn write<T>(&self, offset: usize, obj: &T) -> Result {
+        let mut obj_offset = 0;
+        self.iterate(offset, size_of::<T>(), |page, offset, to_copy| {
+            // SAFETY: The sum of `offset` and `to_copy` is bounded by the size of T.
+            let obj_ptr = unsafe { (obj as *const T as *const u8).add(obj_offset) };
+            // SAFETY: We have a reference to the object, so the pointer is valid.
+            unsafe { page.write(obj_ptr, offset, to_copy) }?;
+            obj_offset += to_copy;
+            Ok(())
+        })
+    }
+
+    pub(crate) fn keep_alive(mut self) {
+        self.process
+            .buffer_make_freeable(self.offset, self.allocation_info.take());
+        self.free_on_drop = false;
+    }
+
+    pub(crate) fn set_info(&mut self, info: AllocationInfo) {
+        self.allocation_info = Some(info);
+    }
+}
+
+impl Drop for Allocation<'_> {
+    fn drop(&mut self) {
+        if !self.free_on_drop {
+            return;
+        }
+
+        if let Some(info) = &self.allocation_info {
+            let offsets = info.offsets.clone();
+            let view = AllocationView::new(self, offsets.start);
+            for i in offsets.step_by(size_of::<usize>()) {
+                if view.cleanup_object(i).is_err() {
+                    pr_warn!("Error cleaning up object at offset {}\n", i)
+                }
+            }
+        }
+
+        self.process.buffer_raw_free(self.ptr);
+    }
+}
+
+pub(crate) struct AllocationView<'a, 'b> {
+    pub(crate) alloc: &'a mut Allocation<'b>,
+    limit: usize,
+}
+
+impl<'a, 'b> AllocationView<'a, 'b> {
+    pub(crate) fn new(alloc: &'a mut Allocation<'b>, limit: usize) -> Self {
+        AllocationView { alloc, limit }
+    }
+
+    pub(crate) fn read<T>(&self, offset: usize) -> Result<T> {
+        if offset.checked_add(size_of::<T>()).ok_or(EINVAL)? > self.limit {
+            return Err(EINVAL);
+        }
+        self.alloc.read(offset)
+    }
+
+    pub(crate) fn write<T>(&self, offset: usize, obj: &T) -> Result {
+        if offset.checked_add(size_of::<T>()).ok_or(EINVAL)? > self.limit {
+            return Err(EINVAL);
+        }
+        self.alloc.write(offset, obj)
+    }
+
+    pub(crate) fn transfer_binder_object<T>(
+        &self,
+        offset: usize,
+        strong: bool,
+        get_node: T,
+    ) -> BinderResult
+    where
+        T: FnOnce(&bindings::flat_binder_object) -> BinderResult<NodeRef>,
+    {
+        // TODO: Do we want this function to take a &mut self?
+        let obj = self.read::<bindings::flat_binder_object>(offset)?;
+        let node_ref = get_node(&obj)?;
+
+        if core::ptr::eq(&*node_ref.node.owner, self.alloc.process) {
+            // The receiving process is the owner of the node, so send it a binder object (instead
+            // of a handle).
+            let (ptr, cookie) = node_ref.node.get_id();
+            let newobj = bindings::flat_binder_object {
+                hdr: bindings::binder_object_header {
+                    type_: if strong {
+                        BINDER_TYPE_BINDER
+                    } else {
+                        BINDER_TYPE_WEAK_BINDER
+                    },
+                },
+                flags: obj.flags,
+                __bindgen_anon_1: bindings::flat_binder_object__bindgen_ty_1 { binder: ptr as _ },
+                cookie: cookie as _,
+            };
+            self.write(offset, &newobj)?;
+
+            // Increment the user ref count on the node. It will be decremented as part of the
+            // destruction of the buffer, when we see a binder or weak-binder object.
+            node_ref.node.update_refcount(true, strong);
+        } else {
+            // The receiving process is different from the owner, so we need to insert a handle to
+            // the binder object.
+            let handle = self
+                .alloc
+                .process
+                .insert_or_update_handle(node_ref, false)?;
+
+            let newobj = bindings::flat_binder_object {
+                hdr: bindings::binder_object_header {
+                    type_: if strong {
+                        BINDER_TYPE_HANDLE
+                    } else {
+                        BINDER_TYPE_WEAK_HANDLE
+                    },
+                },
+                flags: obj.flags,
+                // TODO: To avoid padding, we write to `binder` instead of `handle` here. We need a
+                // better solution though.
+                __bindgen_anon_1: bindings::flat_binder_object__bindgen_ty_1 {
+                    binder: handle as _,
+                },
+                ..bindings::flat_binder_object::default()
+            };
+            if self.write(offset, &newobj).is_err() {
+                // Decrement ref count on the handle we just created.
+                let _ = self.alloc.process.update_ref(handle, false, strong);
+                return Err(BinderError::new_failed());
+            }
+        }
+        Ok(())
+    }
+
+    fn cleanup_object(&self, index_offset: usize) -> Result {
+        let offset = self.alloc.read(index_offset)?;
+        let header = self.read::<bindings::binder_object_header>(offset)?;
+        // TODO: Handle other types.
+        match header.type_ {
+            BINDER_TYPE_WEAK_BINDER | BINDER_TYPE_BINDER => {
+                let obj = self.read::<bindings::flat_binder_object>(offset)?;
+                let strong = header.type_ == BINDER_TYPE_BINDER;
+                // SAFETY: The type is `BINDER_TYPE_{WEAK_}BINDER`, so the `binder` field is
+                // populated.
+                let ptr = unsafe { obj.__bindgen_anon_1.binder } as usize;
+                let cookie = obj.cookie as usize;
+                self.alloc.process.update_node(ptr, cookie, strong, false);
+                Ok(())
+            }
+            BINDER_TYPE_WEAK_HANDLE | BINDER_TYPE_HANDLE => {
+                let obj = self.read::<bindings::flat_binder_object>(offset)?;
+                let strong = header.type_ == BINDER_TYPE_HANDLE;
+                // SAFETY: The type is `BINDER_TYPE_{WEAK_}HANDLE`, so the `handle` field is
+                // populated.
+                let handle = unsafe { obj.__bindgen_anon_1.handle } as _;
+                self.alloc.process.update_ref(handle, false, strong)
+            }
+            _ => Ok(()),
+        }
+    }
+}
diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c
index 5649a0371a1f..f555eebceef6 100644
--- a/drivers/android/binder_alloc.c
+++ b/drivers/android/binder_alloc.c
@@ -213,7 +213,7 @@ static int binder_update_page_range(struct binder_alloc *alloc, int allocate,
 
 	if (mm) {
 		mmap_read_lock(mm);
-		vma = alloc->vma;
+		vma = vma_lookup(mm, alloc->vma_addr);
 	}
 
 	if (!vma && need_mm) {
@@ -313,16 +313,15 @@ static int binder_update_page_range(struct binder_alloc *alloc, int allocate,
 static inline void binder_alloc_set_vma(struct binder_alloc *alloc,
 		struct vm_area_struct *vma)
 {
-	if (vma)
+	unsigned long vm_start = 0;
+
+	if (vma) {
+		vm_start = vma->vm_start;
 		alloc->vma_vm_mm = vma->vm_mm;
-	/*
-	 * If we see alloc->vma is not NULL, buffer data structures set up
-	 * completely. Look at smp_rmb side binder_alloc_get_vma.
-	 * We also want to guarantee new alloc->vma_vm_mm is always visible
-	 * if alloc->vma is set.
-	 */
-	smp_wmb();
-	alloc->vma = vma;
+	}
+
+	mmap_assert_write_locked(alloc->vma_vm_mm);
+	alloc->vma_addr = vm_start;
 }
 
 static inline struct vm_area_struct *binder_alloc_get_vma(
@@ -330,11 +329,9 @@ static inline struct vm_area_struct *binder_alloc_get_vma(
 {
 	struct vm_area_struct *vma = NULL;
 
-	if (alloc->vma) {
-		/* Look at description in binder_alloc_set_vma */
-		smp_rmb();
-		vma = alloc->vma;
-	}
+	if (alloc->vma_addr)
+		vma = vma_lookup(alloc->vma_vm_mm, alloc->vma_addr);
+
 	return vma;
 }
 
@@ -817,7 +814,8 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)
 
 	buffers = 0;
 	mutex_lock(&alloc->mutex);
-	BUG_ON(alloc->vma);
+	BUG_ON(alloc->vma_addr &&
+	       vma_lookup(alloc->vma_vm_mm, alloc->vma_addr));
 
 	while ((n = rb_first(&alloc->allocated_buffers))) {
 		buffer = rb_entry(n, struct binder_buffer, rb_node);
@@ -1084,7 +1082,7 @@ int binder_alloc_shrinker_init(void)
 	int ret = list_lru_init(&binder_alloc_lru);
 
 	if (ret == 0) {
-		ret = register_shrinker(&binder_shrinker);
+		ret = register_shrinker(&binder_shrinker, "android-binder");
 		if (ret)
 			list_lru_destroy(&binder_alloc_lru);
 	}
diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h
index 7dea57a84c79..1e4fd37af5e0 100644
--- a/drivers/android/binder_alloc.h
+++ b/drivers/android/binder_alloc.h
@@ -100,7 +100,7 @@ struct binder_lru_page {
  */
 struct binder_alloc {
 	struct mutex mutex;
-	struct vm_area_struct *vma;
+	unsigned long vma_addr;
 	struct mm_struct *vma_vm_mm;
 	void __user *buffer;
 	struct list_head buffers;
diff --git a/drivers/android/binder_alloc_selftest.c b/drivers/android/binder_alloc_selftest.c
index c2b323bc3b3a..43a881073a42 100644
--- a/drivers/android/binder_alloc_selftest.c
+++ b/drivers/android/binder_alloc_selftest.c
@@ -287,7 +287,7 @@ void binder_selftest_alloc(struct binder_alloc *alloc)
 	if (!binder_selftest_run)
 		return;
 	mutex_lock(&binder_selftest_lock);
-	if (!binder_selftest_run || !alloc->vma)
+	if (!binder_selftest_run || !alloc->vma_addr)
 		goto done;
 	pr_info("STARTED\n");
 	binder_selftest_alloc_offset(alloc, end_offset, 0);
diff --git a/drivers/android/context.rs b/drivers/android/context.rs
new file mode 100644
index 000000000000..2bb448df6641
--- /dev/null
+++ b/drivers/android/context.rs
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::{
+    bindings,
+    prelude::*,
+    security,
+    sync::{Mutex, Ref, UniqueRef},
+};
+
+use crate::{
+    node::NodeRef,
+    thread::{BinderError, BinderResult},
+};
+
+struct Manager {
+    node: Option<NodeRef>,
+    uid: Option<bindings::kuid_t>,
+}
+
+pub(crate) struct Context {
+    manager: Mutex<Manager>,
+}
+
+#[allow(clippy::non_send_fields_in_send_ty)]
+unsafe impl Send for Context {}
+unsafe impl Sync for Context {}
+
+impl Context {
+    pub(crate) fn new() -> Result<Ref<Self>> {
+        let mut ctx = Pin::from(UniqueRef::try_new(Self {
+            // SAFETY: Init is called below.
+            manager: unsafe {
+                Mutex::new(Manager {
+                    node: None,
+                    uid: None,
+                })
+            },
+        })?);
+
+        // SAFETY: `manager` is also pinned when `ctx` is.
+        let manager = unsafe { ctx.as_mut().map_unchecked_mut(|c| &mut c.manager) };
+        kernel::mutex_init!(manager, "Context::manager");
+
+        Ok(ctx.into())
+    }
+
+    pub(crate) fn set_manager_node(&self, node_ref: NodeRef) -> Result {
+        let mut manager = self.manager.lock();
+        if manager.node.is_some() {
+            return Err(EBUSY);
+        }
+        security::binder_set_context_mgr(&node_ref.node.owner.cred)?;
+
+        // TODO: Get the actual caller id.
+        let caller_uid = bindings::kuid_t::default();
+        if let Some(ref uid) = manager.uid {
+            if uid.val != caller_uid.val {
+                return Err(EPERM);
+            }
+        }
+
+        manager.node = Some(node_ref);
+        manager.uid = Some(caller_uid);
+        Ok(())
+    }
+
+    pub(crate) fn unset_manager_node(&self) {
+        let node_ref = self.manager.lock().node.take();
+        drop(node_ref);
+    }
+
+    pub(crate) fn get_manager_node(&self, strong: bool) -> BinderResult<NodeRef> {
+        self.manager
+            .lock()
+            .node
+            .as_ref()
+            .ok_or_else(BinderError::new_dead)?
+            .clone(strong)
+    }
+}
diff --git a/drivers/android/defs.rs b/drivers/android/defs.rs
new file mode 100644
index 000000000000..ec2dde9b3dd8
--- /dev/null
+++ b/drivers/android/defs.rs
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::ops::{Deref, DerefMut};
+use kernel::{
+    bindings,
+    bindings::*,
+    io_buffer::{ReadableFromBytes, WritableToBytes},
+};
+
+macro_rules! pub_no_prefix {
+    ($prefix:ident, $($newname:ident),+) => {
+        $(pub(crate) const $newname: u32 = concat_idents!($prefix, $newname);)+
+    };
+}
+
+pub_no_prefix!(
+    binder_driver_return_protocol_,
+    BR_OK,
+    BR_ERROR,
+    BR_TRANSACTION,
+    BR_REPLY,
+    BR_DEAD_REPLY,
+    BR_TRANSACTION_COMPLETE,
+    BR_INCREFS,
+    BR_ACQUIRE,
+    BR_RELEASE,
+    BR_DECREFS,
+    BR_NOOP,
+    BR_SPAWN_LOOPER,
+    BR_DEAD_BINDER,
+    BR_CLEAR_DEATH_NOTIFICATION_DONE,
+    BR_FAILED_REPLY
+);
+
+pub_no_prefix!(
+    binder_driver_command_protocol_,
+    BC_TRANSACTION,
+    BC_REPLY,
+    BC_FREE_BUFFER,
+    BC_INCREFS,
+    BC_ACQUIRE,
+    BC_RELEASE,
+    BC_DECREFS,
+    BC_INCREFS_DONE,
+    BC_ACQUIRE_DONE,
+    BC_REGISTER_LOOPER,
+    BC_ENTER_LOOPER,
+    BC_EXIT_LOOPER,
+    BC_REQUEST_DEATH_NOTIFICATION,
+    BC_CLEAR_DEATH_NOTIFICATION,
+    BC_DEAD_BINDER_DONE
+);
+
+pub_no_prefix!(transaction_flags_, TF_ONE_WAY, TF_ACCEPT_FDS);
+
+pub(crate) use bindings::{
+    BINDER_TYPE_BINDER, BINDER_TYPE_FD, BINDER_TYPE_HANDLE, BINDER_TYPE_WEAK_BINDER,
+    BINDER_TYPE_WEAK_HANDLE, FLAT_BINDER_FLAG_ACCEPTS_FDS,
+};
+
+macro_rules! decl_wrapper {
+    ($newname:ident, $wrapped:ty) => {
+        #[derive(Copy, Clone, Default)]
+        pub(crate) struct $newname($wrapped);
+
+        // TODO: This must be justified by inspecting the type, so should live outside the macro or
+        // the macro should be somehow marked unsafe.
+        unsafe impl ReadableFromBytes for $newname {}
+        unsafe impl WritableToBytes for $newname {}
+
+        impl Deref for $newname {
+            type Target = $wrapped;
+            fn deref(&self) -> &Self::Target {
+                &self.0
+            }
+        }
+
+        impl DerefMut for $newname {
+            fn deref_mut(&mut self) -> &mut Self::Target {
+                &mut self.0
+            }
+        }
+    };
+}
+
+decl_wrapper!(BinderNodeDebugInfo, bindings::binder_node_debug_info);
+decl_wrapper!(BinderNodeInfoForRef, bindings::binder_node_info_for_ref);
+decl_wrapper!(FlatBinderObject, bindings::flat_binder_object);
+decl_wrapper!(BinderTransactionData, bindings::binder_transaction_data);
+decl_wrapper!(BinderWriteRead, bindings::binder_write_read);
+decl_wrapper!(BinderVersion, bindings::binder_version);
+
+impl BinderVersion {
+    pub(crate) fn current() -> Self {
+        Self(bindings::binder_version {
+            protocol_version: bindings::BINDER_CURRENT_PROTOCOL_VERSION as _,
+        })
+    }
+}
diff --git a/drivers/android/node.rs b/drivers/android/node.rs
new file mode 100644
index 000000000000..1a46de1e736c
--- /dev/null
+++ b/drivers/android/node.rs
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::sync::atomic::{AtomicU64, Ordering};
+use kernel::{
+    io_buffer::IoBufferWriter,
+    linked_list::{GetLinks, Links, List},
+    prelude::*,
+    sync::{Guard, LockedBy, Mutex, Ref, SpinLock},
+    user_ptr::UserSlicePtrWriter,
+};
+
+use crate::{
+    defs::*,
+    process::{Process, ProcessInner},
+    thread::{BinderError, BinderResult, Thread},
+    DeliverToRead,
+};
+
+struct CountState {
+    count: usize,
+    has_count: bool,
+    is_biased: bool,
+}
+
+impl CountState {
+    fn new() -> Self {
+        Self {
+            count: 0,
+            has_count: false,
+            is_biased: false,
+        }
+    }
+
+    fn add_bias(&mut self) {
+        self.count += 1;
+        self.is_biased = true;
+    }
+}
+
+struct NodeInner {
+    strong: CountState,
+    weak: CountState,
+    death_list: List<Ref<NodeDeath>>,
+}
+
+struct NodeDeathInner {
+    dead: bool,
+    cleared: bool,
+    notification_done: bool,
+
+    /// Indicates whether the normal flow was interrupted by removing the handle. In this case, we
+    /// need behave as if the death notification didn't exist (i.e., we don't deliver anything to
+    /// the user.
+    aborted: bool,
+}
+
+pub(crate) struct NodeDeath {
+    node: Ref<Node>,
+    process: Ref<Process>,
+    // TODO: Make this private.
+    pub(crate) cookie: usize,
+    work_links: Links<dyn DeliverToRead>,
+    // TODO: Add the moment we're using this for two lists, which isn't safe because we want to
+    // remove from the list without knowing the list it's in. We need to separate this out.
+    death_links: Links<NodeDeath>,
+    inner: SpinLock<NodeDeathInner>,
+}
+
+impl NodeDeath {
+    /// Constructs a new node death notification object.
+    ///
+    /// # Safety
+    ///
+    /// The caller must call `NodeDeath::init` before using the notification object.
+    pub(crate) unsafe fn new(node: Ref<Node>, process: Ref<Process>, cookie: usize) -> Self {
+        Self {
+            node,
+            process,
+            cookie,
+            work_links: Links::new(),
+            death_links: Links::new(),
+            inner: unsafe {
+                SpinLock::new(NodeDeathInner {
+                    dead: false,
+                    cleared: false,
+                    notification_done: false,
+                    aborted: false,
+                })
+            },
+        }
+    }
+
+    pub(crate) fn init(self: Pin<&mut Self>) {
+        // SAFETY: `inner` is pinned when `self` is.
+        let inner = unsafe { self.map_unchecked_mut(|n| &mut n.inner) };
+        kernel::spinlock_init!(inner, "NodeDeath::inner");
+    }
+
+    /// Sets the cleared flag to `true`.
+    ///
+    /// It removes `self` from the node's death notification list if needed. It must only be called
+    /// once.
+    ///
+    /// Returns whether it needs to be queued.
+    pub(crate) fn set_cleared(self: &Ref<Self>, abort: bool) -> bool {
+        let (needs_removal, needs_queueing) = {
+            // Update state and determine if we need to queue a work item. We only need to do it
+            // when the node is not dead or if the user already completed the death notification.
+            let mut inner = self.inner.lock();
+            inner.cleared = true;
+            if abort {
+                inner.aborted = true;
+            }
+            (!inner.dead, !inner.dead || inner.notification_done)
+        };
+
+        // Remove death notification from node.
+        if needs_removal {
+            let mut owner_inner = self.node.owner.inner.lock();
+            let node_inner = self.node.inner.access_mut(&mut owner_inner);
+            unsafe { node_inner.death_list.remove(self) };
+        }
+
+        needs_queueing
+    }
+
+    /// Sets the 'notification done' flag to `true`.
+    ///
+    /// Returns whether it needs to be queued.
+    pub(crate) fn set_notification_done(self: Ref<Self>, thread: &Thread) {
+        let needs_queueing = {
+            let mut inner = self.inner.lock();
+            inner.notification_done = true;
+            inner.cleared
+        };
+
+        if needs_queueing {
+            let _ = thread.push_work_if_looper(self);
+        }
+    }
+
+    /// Sets the 'dead' flag to `true` and queues work item if needed.
+    pub(crate) fn set_dead(self: Ref<Self>) {
+        let needs_queueing = {
+            let mut inner = self.inner.lock();
+            if inner.cleared {
+                false
+            } else {
+                inner.dead = true;
+                true
+            }
+        };
+
+        if needs_queueing {
+            // Push the death notification to the target process. There is nothing else to do if
+            // it's already dead.
+            let process = self.process.clone();
+            let _ = process.push_work(self);
+        }
+    }
+}
+
+impl GetLinks for NodeDeath {
+    type EntryType = NodeDeath;
+    fn get_links(data: &NodeDeath) -> &Links<NodeDeath> {
+        &data.death_links
+    }
+}
+
+impl DeliverToRead for NodeDeath {
+    fn do_work(self: Ref<Self>, _thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool> {
+        let done = {
+            let inner = self.inner.lock();
+            if inner.aborted {
+                return Ok(true);
+            }
+            inner.cleared && (!inner.dead || inner.notification_done)
+        };
+
+        let cookie = self.cookie;
+        let cmd = if done {
+            BR_CLEAR_DEATH_NOTIFICATION_DONE
+        } else {
+            let process = self.process.clone();
+            let mut process_inner = process.inner.lock();
+            let inner = self.inner.lock();
+            if inner.aborted {
+                return Ok(true);
+            }
+            // We're still holding the inner lock, so it cannot be aborted while we insert it into
+            // the delivered list.
+            process_inner.death_delivered(self.clone());
+            BR_DEAD_BINDER
+        };
+
+        writer.write(&cmd)?;
+        writer.write(&cookie)?;
+
+        // Mimic the original code: we stop processing work items when we get to a death
+        // notification.
+        Ok(cmd != BR_DEAD_BINDER)
+    }
+
+    fn get_links(&self) -> &Links<dyn DeliverToRead> {
+        &self.work_links
+    }
+}
+
+pub(crate) struct Node {
+    pub(crate) global_id: u64,
+    ptr: usize,
+    cookie: usize,
+    pub(crate) flags: u32,
+    pub(crate) owner: Ref<Process>,
+    inner: LockedBy<NodeInner, Mutex<ProcessInner>>,
+    links: Links<dyn DeliverToRead>,
+}
+
+impl Node {
+    pub(crate) fn new(ptr: usize, cookie: usize, flags: u32, owner: Ref<Process>) -> Self {
+        static NEXT_ID: AtomicU64 = AtomicU64::new(1);
+        let inner = LockedBy::new(
+            &owner.inner,
+            NodeInner {
+                strong: CountState::new(),
+                weak: CountState::new(),
+                death_list: List::new(),
+            },
+        );
+        Self {
+            global_id: NEXT_ID.fetch_add(1, Ordering::Relaxed),
+            ptr,
+            cookie,
+            flags,
+            owner,
+            inner,
+            links: Links::new(),
+        }
+    }
+
+    pub(crate) fn get_id(&self) -> (usize, usize) {
+        (self.ptr, self.cookie)
+    }
+
+    pub(crate) fn next_death(
+        &self,
+        guard: &mut Guard<'_, Mutex<ProcessInner>>,
+    ) -> Option<Ref<NodeDeath>> {
+        self.inner.access_mut(guard).death_list.pop_front()
+    }
+
+    pub(crate) fn add_death(
+        &self,
+        death: Ref<NodeDeath>,
+        guard: &mut Guard<'_, Mutex<ProcessInner>>,
+    ) {
+        self.inner.access_mut(guard).death_list.push_back(death);
+    }
+
+    pub(crate) fn update_refcount_locked(
+        &self,
+        inc: bool,
+        strong: bool,
+        biased: bool,
+        owner_inner: &mut ProcessInner,
+    ) -> bool {
+        let inner = self.inner.access_from_mut(owner_inner);
+
+        // Get a reference to the state we'll update.
+        let state = if strong {
+            &mut inner.strong
+        } else {
+            &mut inner.weak
+        };
+
+        // Update biased state: if the count is not biased, there is nothing to do; otherwise,
+        // we're removing the bias, so mark the state as such.
+        if biased {
+            if !state.is_biased {
+                return false;
+            }
+
+            state.is_biased = false;
+        }
+
+        // Update the count and determine whether we need to push work.
+        // TODO: Here we may want to check the weak count being zero but the strong count being 1,
+        // because in such cases, we won't deliver anything to userspace, so we shouldn't queue
+        // either.
+        if inc {
+            state.count += 1;
+            !state.has_count
+        } else {
+            state.count -= 1;
+            state.count == 0 && state.has_count
+        }
+    }
+
+    pub(crate) fn update_refcount(self: &Ref<Self>, inc: bool, strong: bool) {
+        self.owner
+            .inner
+            .lock()
+            .update_node_refcount(self, inc, strong, false, None);
+    }
+
+    pub(crate) fn populate_counts(
+        &self,
+        out: &mut BinderNodeInfoForRef,
+        guard: &Guard<'_, Mutex<ProcessInner>>,
+    ) {
+        let inner = self.inner.access(guard);
+        out.strong_count = inner.strong.count as _;
+        out.weak_count = inner.weak.count as _;
+    }
+
+    pub(crate) fn populate_debug_info(
+        &self,
+        out: &mut BinderNodeDebugInfo,
+        guard: &Guard<'_, Mutex<ProcessInner>>,
+    ) {
+        out.ptr = self.ptr as _;
+        out.cookie = self.cookie as _;
+        let inner = self.inner.access(guard);
+        if inner.strong.has_count {
+            out.has_strong_ref = 1;
+        }
+        if inner.weak.has_count {
+            out.has_weak_ref = 1;
+        }
+    }
+
+    pub(crate) fn force_has_count(&self, guard: &mut Guard<'_, Mutex<ProcessInner>>) {
+        let inner = self.inner.access_mut(guard);
+        inner.strong.has_count = true;
+        inner.weak.has_count = true;
+    }
+
+    fn write(&self, writer: &mut UserSlicePtrWriter, code: u32) -> Result {
+        writer.write(&code)?;
+        writer.write(&self.ptr)?;
+        writer.write(&self.cookie)?;
+        Ok(())
+    }
+}
+
+impl DeliverToRead for Node {
+    fn do_work(self: Ref<Self>, _thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool> {
+        let mut owner_inner = self.owner.inner.lock();
+        let inner = self.inner.access_mut(&mut owner_inner);
+        let strong = inner.strong.count > 0;
+        let has_strong = inner.strong.has_count;
+        let weak = strong || inner.weak.count > 0;
+        let has_weak = inner.weak.has_count;
+        inner.weak.has_count = weak;
+        inner.strong.has_count = strong;
+
+        if !weak {
+            // Remove the node if there are no references to it.
+            owner_inner.remove_node(self.ptr);
+        } else {
+            if !has_weak {
+                inner.weak.add_bias();
+            }
+
+            if !has_strong && strong {
+                inner.strong.add_bias();
+            }
+        }
+
+        drop(owner_inner);
+
+        // This could be done more compactly but we write out all the posibilities for
+        // compatibility with the original implementation wrt the order of events.
+        if weak && !has_weak {
+            self.write(writer, BR_INCREFS)?;
+        }
+
+        if strong && !has_strong {
+            self.write(writer, BR_ACQUIRE)?;
+        }
+
+        if !strong && has_strong {
+            self.write(writer, BR_RELEASE)?;
+        }
+
+        if !weak && has_weak {
+            self.write(writer, BR_DECREFS)?;
+        }
+
+        Ok(true)
+    }
+
+    fn get_links(&self) -> &Links<dyn DeliverToRead> {
+        &self.links
+    }
+}
+
+pub(crate) struct NodeRef {
+    pub(crate) node: Ref<Node>,
+    strong_count: usize,
+    weak_count: usize,
+}
+
+impl NodeRef {
+    pub(crate) fn new(node: Ref<Node>, strong_count: usize, weak_count: usize) -> Self {
+        Self {
+            node,
+            strong_count,
+            weak_count,
+        }
+    }
+
+    pub(crate) fn absorb(&mut self, mut other: Self) {
+        self.strong_count += other.strong_count;
+        self.weak_count += other.weak_count;
+        other.strong_count = 0;
+        other.weak_count = 0;
+    }
+
+    pub(crate) fn clone(&self, strong: bool) -> BinderResult<NodeRef> {
+        if strong && self.strong_count == 0 {
+            return Err(BinderError::new_failed());
+        }
+
+        Ok(self
+            .node
+            .owner
+            .inner
+            .lock()
+            .new_node_ref(self.node.clone(), strong, None))
+    }
+
+    /// Updates (increments or decrements) the number of references held against the node. If the
+    /// count being updated transitions from 0 to 1 or from 1 to 0, the node is notified by having
+    /// its `update_refcount` function called.
+    ///
+    /// Returns whether `self` should be removed (when both counts are zero).
+    pub(crate) fn update(&mut self, inc: bool, strong: bool) -> bool {
+        if strong && self.strong_count == 0 {
+            return false;
+        }
+
+        let (count, other_count) = if strong {
+            (&mut self.strong_count, self.weak_count)
+        } else {
+            (&mut self.weak_count, self.strong_count)
+        };
+
+        if inc {
+            if *count == 0 {
+                self.node.update_refcount(true, strong);
+            }
+            *count += 1;
+        } else {
+            *count -= 1;
+            if *count == 0 {
+                self.node.update_refcount(false, strong);
+                return other_count == 0;
+            }
+        }
+
+        false
+    }
+}
+
+impl Drop for NodeRef {
+    fn drop(&mut self) {
+        if self.strong_count > 0 {
+            self.node.update_refcount(false, true);
+        }
+
+        if self.weak_count > 0 {
+            self.node.update_refcount(false, false);
+        }
+    }
+}
diff --git a/drivers/android/process.rs b/drivers/android/process.rs
new file mode 100644
index 000000000000..e77cd09df50f
--- /dev/null
+++ b/drivers/android/process.rs
@@ -0,0 +1,960 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::{convert::TryFrom, mem::take, ops::Range};
+use kernel::{
+    bindings,
+    cred::Credential,
+    file::{self, File, IoctlCommand, IoctlHandler, PollTable},
+    io_buffer::{IoBufferReader, IoBufferWriter},
+    linked_list::List,
+    mm,
+    pages::Pages,
+    prelude::*,
+    rbtree::RBTree,
+    sync::{Guard, Mutex, Ref, RefBorrow, UniqueRef},
+    task::Task,
+    user_ptr::{UserSlicePtr, UserSlicePtrReader},
+};
+
+use crate::{
+    allocation::Allocation,
+    context::Context,
+    defs::*,
+    node::{Node, NodeDeath, NodeRef},
+    range_alloc::RangeAllocator,
+    thread::{BinderError, BinderResult, Thread},
+    DeliverToRead, DeliverToReadListAdapter, Either,
+};
+
+// TODO: Review this:
+// Lock order: Process::node_refs -> Process::inner -> Thread::inner
+
+pub(crate) struct AllocationInfo {
+    /// Range within the allocation where we can find the offsets to the object descriptors.
+    pub(crate) offsets: Range<usize>,
+}
+
+struct Mapping {
+    address: usize,
+    alloc: RangeAllocator<AllocationInfo>,
+    pages: Ref<[Pages<0>]>,
+}
+
+impl Mapping {
+    fn new(address: usize, size: usize, pages: Ref<[Pages<0>]>) -> Result<Self> {
+        let alloc = RangeAllocator::new(size)?;
+        Ok(Self {
+            address,
+            alloc,
+            pages,
+        })
+    }
+}
+
+// TODO: Make this private.
+pub(crate) struct ProcessInner {
+    is_manager: bool,
+    is_dead: bool,
+    threads: RBTree<i32, Ref<Thread>>,
+    ready_threads: List<Ref<Thread>>,
+    work: List<DeliverToReadListAdapter>,
+    mapping: Option<Mapping>,
+    nodes: RBTree<usize, Ref<Node>>,
+
+    delivered_deaths: List<Ref<NodeDeath>>,
+
+    /// The number of requested threads that haven't registered yet.
+    requested_thread_count: u32,
+
+    /// The maximum number of threads used by the process thread pool.
+    max_threads: u32,
+
+    /// The number of threads the started and registered with the thread pool.
+    started_thread_count: u32,
+}
+
+impl ProcessInner {
+    fn new() -> Self {
+        Self {
+            is_manager: false,
+            is_dead: false,
+            threads: RBTree::new(),
+            ready_threads: List::new(),
+            work: List::new(),
+            mapping: None,
+            nodes: RBTree::new(),
+            requested_thread_count: 0,
+            max_threads: 0,
+            started_thread_count: 0,
+            delivered_deaths: List::new(),
+        }
+    }
+
+    fn push_work(&mut self, work: Ref<dyn DeliverToRead>) -> BinderResult {
+        // Try to find a ready thread to which to push the work.
+        if let Some(thread) = self.ready_threads.pop_front() {
+            // Push to thread while holding state lock. This prevents the thread from giving up
+            // (for example, because of a signal) when we're about to deliver work.
+            thread.push_work(work)
+        } else if self.is_dead {
+            Err(BinderError::new_dead())
+        } else {
+            // There are no ready threads. Push work to process queue.
+            self.work.push_back(work);
+
+            // Wake up polling threads, if any.
+            for thread in self.threads.values() {
+                thread.notify_if_poll_ready();
+            }
+            Ok(())
+        }
+    }
+
+    // TODO: Should this be private?
+    pub(crate) fn remove_node(&mut self, ptr: usize) {
+        self.nodes.remove(&ptr);
+    }
+
+    /// Updates the reference count on the given node.
+    // TODO: Decide if this should be private.
+    pub(crate) fn update_node_refcount(
+        &mut self,
+        node: &Ref<Node>,
+        inc: bool,
+        strong: bool,
+        biased: bool,
+        othread: Option<&Thread>,
+    ) {
+        let push = node.update_refcount_locked(inc, strong, biased, self);
+
+        // If we decided that we need to push work, push either to the process or to a thread if
+        // one is specified.
+        if push {
+            if let Some(thread) = othread {
+                thread.push_work_deferred(node.clone());
+            } else {
+                let _ = self.push_work(node.clone());
+                // Nothing to do: `push_work` may fail if the process is dead, but that's ok as in
+                // that case, it doesn't care about the notification.
+            }
+        }
+    }
+
+    // TODO: Make this private.
+    pub(crate) fn new_node_ref(
+        &mut self,
+        node: Ref<Node>,
+        strong: bool,
+        thread: Option<&Thread>,
+    ) -> NodeRef {
+        self.update_node_refcount(&node, true, strong, false, thread);
+        let strong_count = if strong { 1 } else { 0 };
+        NodeRef::new(node, strong_count, 1 - strong_count)
+    }
+
+    /// Returns an existing node with the given pointer and cookie, if one exists.
+    ///
+    /// Returns an error if a node with the given pointer but a different cookie exists.
+    fn get_existing_node(&self, ptr: usize, cookie: usize) -> Result<Option<Ref<Node>>> {
+        match self.nodes.get(&ptr) {
+            None => Ok(None),
+            Some(node) => {
+                let (_, node_cookie) = node.get_id();
+                if node_cookie == cookie {
+                    Ok(Some(node.clone()))
+                } else {
+                    Err(EINVAL)
+                }
+            }
+        }
+    }
+
+    /// Returns a reference to an existing node with the given pointer and cookie. It requires a
+    /// mutable reference because it needs to increment the ref count on the node, which may
+    /// require pushing work to the work queue (to notify userspace of 0 to 1 transitions).
+    fn get_existing_node_ref(
+        &mut self,
+        ptr: usize,
+        cookie: usize,
+        strong: bool,
+        thread: Option<&Thread>,
+    ) -> Result<Option<NodeRef>> {
+        Ok(self
+            .get_existing_node(ptr, cookie)?
+            .map(|node| self.new_node_ref(node, strong, thread)))
+    }
+
+    fn register_thread(&mut self) -> bool {
+        if self.requested_thread_count == 0 {
+            return false;
+        }
+
+        self.requested_thread_count -= 1;
+        self.started_thread_count += 1;
+        true
+    }
+
+    /// Finds a delivered death notification with the given cookie, removes it from the thread's
+    /// delivered list, and returns it.
+    fn pull_delivered_death(&mut self, cookie: usize) -> Option<Ref<NodeDeath>> {
+        let mut cursor = self.delivered_deaths.cursor_front_mut();
+        while let Some(death) = cursor.current() {
+            if death.cookie == cookie {
+                return cursor.remove_current();
+            }
+            cursor.move_next();
+        }
+        None
+    }
+
+    pub(crate) fn death_delivered(&mut self, death: Ref<NodeDeath>) {
+        self.delivered_deaths.push_back(death);
+    }
+}
+
+struct NodeRefInfo {
+    node_ref: NodeRef,
+    death: Option<Ref<NodeDeath>>,
+}
+
+impl NodeRefInfo {
+    fn new(node_ref: NodeRef) -> Self {
+        Self {
+            node_ref,
+            death: None,
+        }
+    }
+}
+
+struct ProcessNodeRefs {
+    by_handle: RBTree<u32, NodeRefInfo>,
+    by_global_id: RBTree<u64, u32>,
+}
+
+impl ProcessNodeRefs {
+    fn new() -> Self {
+        Self {
+            by_handle: RBTree::new(),
+            by_global_id: RBTree::new(),
+        }
+    }
+}
+
+pub(crate) struct Process {
+    ctx: Ref<Context>,
+
+    // The task leader (process).
+    pub(crate) task: Task,
+
+    // Credential associated with file when `Process` is created.
+    pub(crate) cred: ARef<Credential>,
+
+    // TODO: For now this a mutex because we have allocations in RangeAllocator while holding the
+    // lock. We may want to split up the process state at some point to use a spin lock for the
+    // other fields.
+    // TODO: Make this private again.
+    pub(crate) inner: Mutex<ProcessInner>,
+
+    // References are in a different mutex to avoid recursive acquisition when
+    // incrementing/decrementing a node in another process.
+    node_refs: Mutex<ProcessNodeRefs>,
+}
+
+#[allow(clippy::non_send_fields_in_send_ty)]
+unsafe impl Send for Process {}
+unsafe impl Sync for Process {}
+
+impl Process {
+    fn new(ctx: Ref<Context>, cred: ARef<Credential>) -> Result<Ref<Self>> {
+        let mut process = Pin::from(UniqueRef::try_new(Self {
+            ctx,
+            cred,
+            task: Task::current().group_leader().clone(),
+            // SAFETY: `inner` is initialised in the call to `mutex_init` below.
+            inner: unsafe { Mutex::new(ProcessInner::new()) },
+            // SAFETY: `node_refs` is initialised in the call to `mutex_init` below.
+            node_refs: unsafe { Mutex::new(ProcessNodeRefs::new()) },
+        })?);
+
+        // SAFETY: `inner` is pinned when `Process` is.
+        let pinned = unsafe { process.as_mut().map_unchecked_mut(|p| &mut p.inner) };
+        kernel::mutex_init!(pinned, "Process::inner");
+
+        // SAFETY: `node_refs` is pinned when `Process` is.
+        let pinned = unsafe { process.as_mut().map_unchecked_mut(|p| &mut p.node_refs) };
+        kernel::mutex_init!(pinned, "Process::node_refs");
+
+        Ok(process.into())
+    }
+
+    /// Attempts to fetch a work item from the process queue.
+    pub(crate) fn get_work(&self) -> Option<Ref<dyn DeliverToRead>> {
+        self.inner.lock().work.pop_front()
+    }
+
+    /// Attempts to fetch a work item from the process queue. If none is available, it registers the
+    /// given thread as ready to receive work directly.
+    ///
+    /// This must only be called when the thread is not participating in a transaction chain; when
+    /// it is, work will always be delivered directly to the thread (and not through the process
+    /// queue).
+    pub(crate) fn get_work_or_register<'a>(
+        &'a self,
+        thread: &'a Ref<Thread>,
+    ) -> Either<Ref<dyn DeliverToRead>, Registration<'a>> {
+        let mut inner = self.inner.lock();
+
+        // Try to get work from the process queue.
+        if let Some(work) = inner.work.pop_front() {
+            return Either::Left(work);
+        }
+
+        // Register the thread as ready.
+        Either::Right(Registration::new(self, thread, &mut inner))
+    }
+
+    fn get_thread(self: RefBorrow<'_, Self>, id: i32) -> Result<Ref<Thread>> {
+        // TODO: Consider using read/write locks here instead.
+        {
+            let inner = self.inner.lock();
+            if let Some(thread) = inner.threads.get(&id) {
+                return Ok(thread.clone());
+            }
+        }
+
+        // Allocate a new `Thread` without holding any locks.
+        let ta = Thread::new(id, self.into())?;
+        let node = RBTree::try_allocate_node(id, ta.clone())?;
+
+        let mut inner = self.inner.lock();
+
+        // Recheck. It's possible the thread was create while we were not holding the lock.
+        if let Some(thread) = inner.threads.get(&id) {
+            return Ok(thread.clone());
+        }
+
+        inner.threads.insert(node);
+        Ok(ta)
+    }
+
+    pub(crate) fn push_work(&self, work: Ref<dyn DeliverToRead>) -> BinderResult {
+        self.inner.lock().push_work(work)
+    }
+
+    fn set_as_manager(
+        self: RefBorrow<'_, Self>,
+        info: Option<FlatBinderObject>,
+        thread: &Thread,
+    ) -> Result {
+        let (ptr, cookie, flags) = if let Some(obj) = info {
+            (
+                // SAFETY: The object type for this ioctl is implicitly `BINDER_TYPE_BINDER`, so it
+                // is safe to access the `binder` field.
+                unsafe { obj.__bindgen_anon_1.binder },
+                obj.cookie,
+                obj.flags,
+            )
+        } else {
+            (0, 0, 0)
+        };
+        let node_ref = self.get_node(ptr as _, cookie as _, flags as _, true, Some(thread))?;
+        let node = node_ref.node.clone();
+        self.ctx.set_manager_node(node_ref)?;
+        self.inner.lock().is_manager = true;
+
+        // Force the state of the node to prevent the delivery of acquire/increfs.
+        let mut owner_inner = node.owner.inner.lock();
+        node.force_has_count(&mut owner_inner);
+        Ok(())
+    }
+
+    pub(crate) fn get_node(
+        self: RefBorrow<'_, Self>,
+        ptr: usize,
+        cookie: usize,
+        flags: u32,
+        strong: bool,
+        thread: Option<&Thread>,
+    ) -> Result<NodeRef> {
+        // Try to find an existing node.
+        {
+            let mut inner = self.inner.lock();
+            if let Some(node) = inner.get_existing_node_ref(ptr, cookie, strong, thread)? {
+                return Ok(node);
+            }
+        }
+
+        // Allocate the node before reacquiring the lock.
+        let node = Ref::try_new(Node::new(ptr, cookie, flags, self.into()))?;
+        let rbnode = RBTree::try_allocate_node(ptr, node.clone())?;
+
+        let mut inner = self.inner.lock();
+        if let Some(node) = inner.get_existing_node_ref(ptr, cookie, strong, thread)? {
+            return Ok(node);
+        }
+
+        inner.nodes.insert(rbnode);
+        Ok(inner.new_node_ref(node, strong, thread))
+    }
+
+    pub(crate) fn insert_or_update_handle(
+        &self,
+        node_ref: NodeRef,
+        is_mananger: bool,
+    ) -> Result<u32> {
+        {
+            let mut refs = self.node_refs.lock();
+
+            // Do a lookup before inserting.
+            if let Some(handle_ref) = refs.by_global_id.get(&node_ref.node.global_id) {
+                let handle = *handle_ref;
+                let info = refs.by_handle.get_mut(&handle).unwrap();
+                info.node_ref.absorb(node_ref);
+                return Ok(handle);
+            }
+        }
+
+        // Reserve memory for tree nodes.
+        let reserve1 = RBTree::try_reserve_node()?;
+        let reserve2 = RBTree::try_reserve_node()?;
+
+        let mut refs = self.node_refs.lock();
+
+        // Do a lookup again as node may have been inserted before the lock was reacquired.
+        if let Some(handle_ref) = refs.by_global_id.get(&node_ref.node.global_id) {
+            let handle = *handle_ref;
+            let info = refs.by_handle.get_mut(&handle).unwrap();
+            info.node_ref.absorb(node_ref);
+            return Ok(handle);
+        }
+
+        // Find id.
+        let mut target = if is_mananger { 0 } else { 1 };
+        for handle in refs.by_handle.keys() {
+            if *handle > target {
+                break;
+            }
+            if *handle == target {
+                target = target.checked_add(1).ok_or(ENOMEM)?;
+            }
+        }
+
+        // Ensure the process is still alive while we insert a new reference.
+        let inner = self.inner.lock();
+        if inner.is_dead {
+            return Err(ESRCH);
+        }
+        refs.by_global_id
+            .insert(reserve1.into_node(node_ref.node.global_id, target));
+        refs.by_handle
+            .insert(reserve2.into_node(target, NodeRefInfo::new(node_ref)));
+        Ok(target)
+    }
+
+    pub(crate) fn get_transaction_node(&self, handle: u32) -> BinderResult<NodeRef> {
+        // When handle is zero, try to get the context manager.
+        if handle == 0 {
+            self.ctx.get_manager_node(true)
+        } else {
+            self.get_node_from_handle(handle, true)
+        }
+    }
+
+    pub(crate) fn get_node_from_handle(&self, handle: u32, strong: bool) -> BinderResult<NodeRef> {
+        self.node_refs
+            .lock()
+            .by_handle
+            .get(&handle)
+            .ok_or(ENOENT)?
+            .node_ref
+            .clone(strong)
+    }
+
+    pub(crate) fn remove_from_delivered_deaths(&self, death: &Ref<NodeDeath>) {
+        let mut inner = self.inner.lock();
+        let removed = unsafe { inner.delivered_deaths.remove(death) };
+        drop(inner);
+        drop(removed);
+    }
+
+    pub(crate) fn update_ref(&self, handle: u32, inc: bool, strong: bool) -> Result {
+        if inc && handle == 0 {
+            if let Ok(node_ref) = self.ctx.get_manager_node(strong) {
+                if core::ptr::eq(self, &*node_ref.node.owner) {
+                    return Err(EINVAL);
+                }
+                let _ = self.insert_or_update_handle(node_ref, true);
+                return Ok(());
+            }
+        }
+
+        // To preserve original binder behaviour, we only fail requests where the manager tries to
+        // increment references on itself.
+        let mut refs = self.node_refs.lock();
+        if let Some(info) = refs.by_handle.get_mut(&handle) {
+            if info.node_ref.update(inc, strong) {
+                // Clean up death if there is one attached to this node reference.
+                if let Some(death) = info.death.take() {
+                    death.set_cleared(true);
+                    self.remove_from_delivered_deaths(&death);
+                }
+
+                // Remove reference from process tables.
+                let id = info.node_ref.node.global_id;
+                refs.by_handle.remove(&handle);
+                refs.by_global_id.remove(&id);
+            }
+        }
+        Ok(())
+    }
+
+    /// Decrements the refcount of the given node, if one exists.
+    pub(crate) fn update_node(&self, ptr: usize, cookie: usize, strong: bool, biased: bool) {
+        let mut inner = self.inner.lock();
+        if let Ok(Some(node)) = inner.get_existing_node(ptr, cookie) {
+            inner.update_node_refcount(&node, false, strong, biased, None);
+        }
+    }
+
+    pub(crate) fn inc_ref_done(&self, reader: &mut UserSlicePtrReader, strong: bool) -> Result {
+        let ptr = reader.read::<usize>()?;
+        let cookie = reader.read::<usize>()?;
+        self.update_node(ptr, cookie, strong, true);
+        Ok(())
+    }
+
+    pub(crate) fn buffer_alloc(&self, size: usize) -> BinderResult<Allocation<'_>> {
+        let mut inner = self.inner.lock();
+        let mapping = inner.mapping.as_mut().ok_or_else(BinderError::new_dead)?;
+
+        let offset = mapping.alloc.reserve_new(size)?;
+        Ok(Allocation::new(
+            self,
+            offset,
+            size,
+            mapping.address + offset,
+            mapping.pages.clone(),
+        ))
+    }
+
+    // TODO: Review if we want an Option or a Result.
+    pub(crate) fn buffer_get(&self, ptr: usize) -> Option<Allocation<'_>> {
+        let mut inner = self.inner.lock();
+        let mapping = inner.mapping.as_mut()?;
+        let offset = ptr.checked_sub(mapping.address)?;
+        let (size, odata) = mapping.alloc.reserve_existing(offset).ok()?;
+        let mut alloc = Allocation::new(self, offset, size, ptr, mapping.pages.clone());
+        if let Some(data) = odata {
+            alloc.set_info(data);
+        }
+        Some(alloc)
+    }
+
+    pub(crate) fn buffer_raw_free(&self, ptr: usize) {
+        let mut inner = self.inner.lock();
+        if let Some(ref mut mapping) = &mut inner.mapping {
+            if ptr < mapping.address
+                || mapping
+                    .alloc
+                    .reservation_abort(ptr - mapping.address)
+                    .is_err()
+            {
+                pr_warn!(
+                    "Pointer {:x} failed to free, base = {:x}\n",
+                    ptr,
+                    mapping.address
+                );
+            }
+        }
+    }
+
+    pub(crate) fn buffer_make_freeable(&self, offset: usize, data: Option<AllocationInfo>) {
+        let mut inner = self.inner.lock();
+        if let Some(ref mut mapping) = &mut inner.mapping {
+            if mapping.alloc.reservation_commit(offset, data).is_err() {
+                pr_warn!("Offset {} failed to be marked freeable\n", offset);
+            }
+        }
+    }
+
+    fn create_mapping(&self, vma: &mut mm::virt::Area) -> Result {
+        let size = core::cmp::min(vma.end() - vma.start(), bindings::SZ_4M as usize);
+        let page_count = size / kernel::PAGE_SIZE;
+
+        // Allocate and map all pages.
+        //
+        // N.B. If we fail halfway through mapping these pages, the kernel will unmap them.
+        let mut pages = Vec::new();
+        pages.try_reserve_exact(page_count)?;
+        let mut address = vma.start();
+        for _ in 0..page_count {
+            let page = Pages::<0>::new()?;
+            vma.insert_page(address, &page)?;
+            pages.try_push(page)?;
+            address += kernel::PAGE_SIZE;
+        }
+
+        let ref_pages = Ref::try_from(pages)?;
+
+        // Save pages for later.
+        let mut inner = self.inner.lock();
+        match &inner.mapping {
+            None => inner.mapping = Some(Mapping::new(vma.start(), size, ref_pages)?),
+            Some(_) => return Err(EBUSY),
+        }
+        Ok(())
+    }
+
+    fn version(&self, data: UserSlicePtr) -> Result {
+        data.writer().write(&BinderVersion::current())
+    }
+
+    pub(crate) fn register_thread(&self) -> bool {
+        self.inner.lock().register_thread()
+    }
+
+    fn remove_thread(&self, thread: Ref<Thread>) {
+        self.inner.lock().threads.remove(&thread.id);
+        thread.release();
+    }
+
+    fn set_max_threads(&self, max: u32) {
+        self.inner.lock().max_threads = max;
+    }
+
+    fn get_node_debug_info(&self, data: UserSlicePtr) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+
+        // Read the starting point.
+        let ptr = reader.read::<BinderNodeDebugInfo>()?.ptr as usize;
+        let mut out = BinderNodeDebugInfo::default();
+
+        {
+            let inner = self.inner.lock();
+            for (node_ptr, node) in &inner.nodes {
+                if *node_ptr > ptr {
+                    node.populate_debug_info(&mut out, &inner);
+                    break;
+                }
+            }
+        }
+
+        writer.write(&out)
+    }
+
+    fn get_node_info_from_ref(&self, data: UserSlicePtr) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+        let mut out = reader.read::<BinderNodeInfoForRef>()?;
+
+        if out.strong_count != 0
+            || out.weak_count != 0
+            || out.reserved1 != 0
+            || out.reserved2 != 0
+            || out.reserved3 != 0
+        {
+            return Err(EINVAL);
+        }
+
+        // Only the context manager is allowed to use this ioctl.
+        if !self.inner.lock().is_manager {
+            return Err(EPERM);
+        }
+
+        let node_ref = self
+            .get_node_from_handle(out.handle, true)
+            .or(Err(EINVAL))?;
+
+        // Get the counts from the node.
+        {
+            let owner_inner = node_ref.node.owner.inner.lock();
+            node_ref.node.populate_counts(&mut out, &owner_inner);
+        }
+
+        // Write the result back.
+        writer.write(&out)
+    }
+
+    pub(crate) fn needs_thread(&self) -> bool {
+        let mut inner = self.inner.lock();
+        let ret = inner.requested_thread_count == 0
+            && inner.ready_threads.is_empty()
+            && inner.started_thread_count < inner.max_threads;
+        if ret {
+            inner.requested_thread_count += 1
+        };
+        ret
+    }
+
+    pub(crate) fn request_death(
+        self: &Ref<Self>,
+        reader: &mut UserSlicePtrReader,
+        thread: &Thread,
+    ) -> Result {
+        let handle: u32 = reader.read()?;
+        let cookie: usize = reader.read()?;
+
+        // TODO: First two should result in error, but not the others.
+
+        // TODO: Do we care about the context manager dying?
+
+        // Queue BR_ERROR if we can't allocate memory for the death notification.
+        let death = UniqueRef::try_new_uninit().map_err(|err| {
+            thread.push_return_work(BR_ERROR);
+            err
+        })?;
+
+        let mut refs = self.node_refs.lock();
+        let info = refs.by_handle.get_mut(&handle).ok_or(EINVAL)?;
+
+        // Nothing to do if there is already a death notification request for this handle.
+        if info.death.is_some() {
+            return Ok(());
+        }
+
+        let death = {
+            let mut pinned = Pin::from(death.write(
+                // SAFETY: `init` is called below.
+                unsafe { NodeDeath::new(info.node_ref.node.clone(), self.clone(), cookie) },
+            ));
+            pinned.as_mut().init();
+            Ref::<NodeDeath>::from(pinned)
+        };
+
+        info.death = Some(death.clone());
+
+        // Register the death notification.
+        {
+            let mut owner_inner = info.node_ref.node.owner.inner.lock();
+            if owner_inner.is_dead {
+                drop(owner_inner);
+                let _ = self.push_work(death);
+            } else {
+                info.node_ref.node.add_death(death, &mut owner_inner);
+            }
+        }
+        Ok(())
+    }
+
+    pub(crate) fn clear_death(&self, reader: &mut UserSlicePtrReader, thread: &Thread) -> Result {
+        let handle: u32 = reader.read()?;
+        let cookie: usize = reader.read()?;
+
+        let mut refs = self.node_refs.lock();
+        let info = refs.by_handle.get_mut(&handle).ok_or(EINVAL)?;
+
+        let death = info.death.take().ok_or(EINVAL)?;
+        if death.cookie != cookie {
+            info.death = Some(death);
+            return Err(EINVAL);
+        }
+
+        // Update state and determine if we need to queue a work item. We only need to do it when
+        // the node is not dead or if the user already completed the death notification.
+        if death.set_cleared(false) {
+            let _ = thread.push_work_if_looper(death);
+        }
+
+        Ok(())
+    }
+
+    pub(crate) fn dead_binder_done(&self, cookie: usize, thread: &Thread) {
+        if let Some(death) = self.inner.lock().pull_delivered_death(cookie) {
+            death.set_notification_done(thread);
+        }
+    }
+}
+
+impl IoctlHandler for Process {
+    type Target<'a> = RefBorrow<'a, Process>;
+
+    fn write(
+        this: RefBorrow<'_, Process>,
+        _file: &File,
+        cmd: u32,
+        reader: &mut UserSlicePtrReader,
+    ) -> Result<i32> {
+        let thread = this.get_thread(Task::current().pid())?;
+        match cmd {
+            bindings::BINDER_SET_MAX_THREADS => this.set_max_threads(reader.read()?),
+            bindings::BINDER_SET_CONTEXT_MGR => this.set_as_manager(None, &thread)?,
+            bindings::BINDER_THREAD_EXIT => this.remove_thread(thread),
+            bindings::BINDER_SET_CONTEXT_MGR_EXT => {
+                this.set_as_manager(Some(reader.read()?), &thread)?
+            }
+            _ => return Err(EINVAL),
+        }
+        Ok(0)
+    }
+
+    fn read_write(
+        this: RefBorrow<'_, Process>,
+        file: &File,
+        cmd: u32,
+        data: UserSlicePtr,
+    ) -> Result<i32> {
+        let thread = this.get_thread(Task::current().pid())?;
+        match cmd {
+            bindings::BINDER_WRITE_READ => thread.write_read(data, file.is_blocking())?,
+            bindings::BINDER_GET_NODE_DEBUG_INFO => this.get_node_debug_info(data)?,
+            bindings::BINDER_GET_NODE_INFO_FOR_REF => this.get_node_info_from_ref(data)?,
+            bindings::BINDER_VERSION => this.version(data)?,
+            _ => return Err(EINVAL),
+        }
+        Ok(0)
+    }
+}
+
+impl file::Operations for Process {
+    type Data = Ref<Self>;
+    type OpenData = Ref<Context>;
+
+    kernel::declare_file_operations!(ioctl, compat_ioctl, mmap, poll);
+
+    fn open(ctx: &Ref<Context>, file: &File) -> Result<Self::Data> {
+        Self::new(ctx.clone(), file.cred().into())
+    }
+
+    fn release(obj: Self::Data, _file: &File) {
+        // Mark this process as dead. We'll do the same for the threads later.
+        obj.inner.lock().is_dead = true;
+
+        // If this process is the manager, unset it.
+        if obj.inner.lock().is_manager {
+            obj.ctx.unset_manager_node();
+        }
+
+        // TODO: Do this in a worker?
+
+        // Cancel all pending work items.
+        while let Some(work) = obj.get_work() {
+            work.cancel();
+        }
+
+        // Free any resources kept alive by allocated buffers.
+        let omapping = obj.inner.lock().mapping.take();
+        if let Some(mut mapping) = omapping {
+            let address = mapping.address;
+            let pages = mapping.pages.clone();
+            mapping.alloc.for_each(|offset, size, odata| {
+                let ptr = offset + address;
+                let mut alloc = Allocation::new(&obj, offset, size, ptr, pages.clone());
+                if let Some(data) = odata {
+                    alloc.set_info(data);
+                }
+                drop(alloc)
+            });
+        }
+
+        // Drop all references. We do this dance with `swap` to avoid destroying the references
+        // while holding the lock.
+        let mut refs = obj.node_refs.lock();
+        let mut node_refs = take(&mut refs.by_handle);
+        drop(refs);
+
+        // Remove all death notifications from the nodes (that belong to a different process).
+        for info in node_refs.values_mut() {
+            let death = if let Some(existing) = info.death.take() {
+                existing
+            } else {
+                continue;
+            };
+
+            death.set_cleared(false);
+        }
+
+        // Do similar dance for the state lock.
+        let mut inner = obj.inner.lock();
+        let threads = take(&mut inner.threads);
+        let nodes = take(&mut inner.nodes);
+        drop(inner);
+
+        // Release all threads.
+        for thread in threads.values() {
+            thread.release();
+        }
+
+        // Deliver death notifications.
+        for node in nodes.values() {
+            loop {
+                let death = {
+                    let mut inner = obj.inner.lock();
+                    if let Some(death) = node.next_death(&mut inner) {
+                        death
+                    } else {
+                        break;
+                    }
+                };
+
+                death.set_dead();
+            }
+        }
+    }
+
+    fn ioctl(this: RefBorrow<'_, Process>, file: &File, cmd: &mut IoctlCommand) -> Result<i32> {
+        cmd.dispatch::<Self>(this, file)
+    }
+
+    fn compat_ioctl(
+        this: RefBorrow<'_, Process>,
+        file: &File,
+        cmd: &mut IoctlCommand,
+    ) -> Result<i32> {
+        cmd.dispatch::<Self>(this, file)
+    }
+
+    fn mmap(this: RefBorrow<'_, Process>, _file: &File, vma: &mut mm::virt::Area) -> Result {
+        // We don't allow mmap to be used in a different process.
+        if !Task::current().group_leader().eq(&this.task) {
+            return Err(EINVAL);
+        }
+
+        if vma.start() == 0 {
+            return Err(EINVAL);
+        }
+
+        let mut flags = vma.flags();
+        use mm::virt::flags::*;
+        if flags & WRITE != 0 {
+            return Err(EPERM);
+        }
+
+        flags |= DONTCOPY | MIXEDMAP;
+        flags &= !MAYWRITE;
+        vma.set_flags(flags);
+
+        // TODO: Set ops. We need to learn when the user unmaps so that we can stop using it.
+        this.create_mapping(vma)
+    }
+
+    fn poll(this: RefBorrow<'_, Process>, file: &File, table: &PollTable) -> Result<u32> {
+        let thread = this.get_thread(Task::current().pid())?;
+        let (from_proc, mut mask) = thread.poll(file, table);
+        if mask == 0 && from_proc && !this.inner.lock().work.is_empty() {
+            mask |= bindings::POLLIN;
+        }
+        Ok(mask)
+    }
+}
+
+pub(crate) struct Registration<'a> {
+    process: &'a Process,
+    thread: &'a Ref<Thread>,
+}
+
+impl<'a> Registration<'a> {
+    fn new(
+        process: &'a Process,
+        thread: &'a Ref<Thread>,
+        guard: &mut Guard<'_, Mutex<ProcessInner>>,
+    ) -> Self {
+        guard.ready_threads.push_back(thread.clone());
+        Self { process, thread }
+    }
+}
+
+impl Drop for Registration<'_> {
+    fn drop(&mut self) {
+        let mut inner = self.process.inner.lock();
+        unsafe { inner.ready_threads.remove(self.thread) };
+    }
+}
diff --git a/drivers/android/range_alloc.rs b/drivers/android/range_alloc.rs
new file mode 100644
index 000000000000..7b149048879b
--- /dev/null
+++ b/drivers/android/range_alloc.rs
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::ptr::NonNull;
+use kernel::{
+    linked_list::{CursorMut, GetLinks, Links, List},
+    prelude::*,
+};
+
+pub(crate) struct RangeAllocator<T> {
+    list: List<Box<Descriptor<T>>>,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+enum DescriptorState {
+    Free,
+    Reserved,
+    Allocated,
+}
+
+impl<T> RangeAllocator<T> {
+    pub(crate) fn new(size: usize) -> Result<Self> {
+        let desc = Box::try_new(Descriptor::new(0, size))?;
+        let mut list = List::new();
+        list.push_back(desc);
+        Ok(Self { list })
+    }
+
+    fn find_best_match(&self, size: usize) -> Option<NonNull<Descriptor<T>>> {
+        // TODO: Use a binary tree instead of list for this lookup.
+        let mut best = None;
+        let mut best_size = usize::MAX;
+        let mut cursor = self.list.cursor_front();
+        while let Some(desc) = cursor.current() {
+            if desc.state == DescriptorState::Free {
+                if size == desc.size {
+                    return Some(NonNull::from(desc));
+                }
+
+                if size < desc.size && desc.size < best_size {
+                    best = Some(NonNull::from(desc));
+                    best_size = desc.size;
+                }
+            }
+
+            cursor.move_next();
+        }
+        best
+    }
+
+    pub(crate) fn reserve_new(&mut self, size: usize) -> Result<usize> {
+        let desc_ptr = match self.find_best_match(size) {
+            None => return Err(ENOMEM),
+            Some(found) => found,
+        };
+
+        // SAFETY: We hold the only mutable reference to list, so it cannot have changed.
+        let desc = unsafe { &mut *desc_ptr.as_ptr() };
+        if desc.size == size {
+            desc.state = DescriptorState::Reserved;
+            return Ok(desc.offset);
+        }
+
+        // We need to break up the descriptor.
+        let new = Box::try_new(Descriptor::new(desc.offset + size, desc.size - size))?;
+        unsafe { self.list.insert_after(desc_ptr, new) };
+        desc.state = DescriptorState::Reserved;
+        desc.size = size;
+        Ok(desc.offset)
+    }
+
+    fn free_with_cursor(cursor: &mut CursorMut<'_, Box<Descriptor<T>>>) -> Result {
+        let mut size = match cursor.current() {
+            None => return Err(EINVAL),
+            Some(ref mut entry) => {
+                match entry.state {
+                    DescriptorState::Free => return Err(EINVAL),
+                    DescriptorState::Allocated => return Err(EPERM),
+                    DescriptorState::Reserved => {}
+                }
+                entry.state = DescriptorState::Free;
+                entry.size
+            }
+        };
+
+        // Try to merge with the next entry.
+        if let Some(next) = cursor.peek_next() {
+            if next.state == DescriptorState::Free {
+                next.offset -= size;
+                next.size += size;
+                size = next.size;
+                cursor.remove_current();
+            }
+        }
+
+        // Try to merge with the previous entry.
+        if let Some(prev) = cursor.peek_prev() {
+            if prev.state == DescriptorState::Free {
+                prev.size += size;
+                cursor.remove_current();
+            }
+        }
+
+        Ok(())
+    }
+
+    fn find_at_offset(&mut self, offset: usize) -> Option<CursorMut<'_, Box<Descriptor<T>>>> {
+        let mut cursor = self.list.cursor_front_mut();
+        while let Some(desc) = cursor.current() {
+            if desc.offset == offset {
+                return Some(cursor);
+            }
+
+            if desc.offset > offset {
+                return None;
+            }
+
+            cursor.move_next();
+        }
+        None
+    }
+
+    pub(crate) fn reservation_abort(&mut self, offset: usize) -> Result {
+        // TODO: The force case is currently O(n), but could be made O(1) with unsafe.
+        let mut cursor = self.find_at_offset(offset).ok_or(EINVAL)?;
+        Self::free_with_cursor(&mut cursor)
+    }
+
+    pub(crate) fn reservation_commit(&mut self, offset: usize, data: Option<T>) -> Result {
+        // TODO: This is currently O(n), make it O(1).
+        let mut cursor = self.find_at_offset(offset).ok_or(ENOENT)?;
+        let desc = cursor.current().unwrap();
+        desc.state = DescriptorState::Allocated;
+        desc.data = data;
+        Ok(())
+    }
+
+    /// Takes an entry at the given offset from [`DescriptorState::Allocated`] to
+    /// [`DescriptorState::Reserved`].
+    ///
+    /// Returns the size of the existing entry and the data associated with it.
+    pub(crate) fn reserve_existing(&mut self, offset: usize) -> Result<(usize, Option<T>)> {
+        // TODO: This is currently O(n), make it O(log n).
+        let mut cursor = self.find_at_offset(offset).ok_or(ENOENT)?;
+        let desc = cursor.current().unwrap();
+        if desc.state != DescriptorState::Allocated {
+            return Err(ENOENT);
+        }
+        desc.state = DescriptorState::Reserved;
+        Ok((desc.size, desc.data.take()))
+    }
+
+    pub(crate) fn for_each<F: Fn(usize, usize, Option<T>)>(&mut self, callback: F) {
+        let mut cursor = self.list.cursor_front_mut();
+        while let Some(desc) = cursor.current() {
+            if desc.state == DescriptorState::Allocated {
+                callback(desc.offset, desc.size, desc.data.take());
+            }
+
+            cursor.move_next();
+        }
+    }
+}
+
+struct Descriptor<T> {
+    state: DescriptorState,
+    size: usize,
+    offset: usize,
+    links: Links<Descriptor<T>>,
+    data: Option<T>,
+}
+
+impl<T> Descriptor<T> {
+    fn new(offset: usize, size: usize) -> Self {
+        Self {
+            size,
+            offset,
+            state: DescriptorState::Free,
+            links: Links::new(),
+            data: None,
+        }
+    }
+}
+
+impl<T> GetLinks for Descriptor<T> {
+    type EntryType = Self;
+    fn get_links(desc: &Self) -> &Links<Self> {
+        &desc.links
+    }
+}
diff --git a/drivers/android/rust_binder.rs b/drivers/android/rust_binder.rs
new file mode 100644
index 000000000000..d059077238ce
--- /dev/null
+++ b/drivers/android/rust_binder.rs
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! Binder -- the Android IPC mechanism.
+//!
+//! TODO: This module is a work in progress.
+
+use kernel::{
+    io_buffer::IoBufferWriter,
+    linked_list::{GetLinks, GetLinksWrapped, Links},
+    miscdev::Registration,
+    prelude::*,
+    str::CStr,
+    sync::Ref,
+    user_ptr::UserSlicePtrWriter,
+};
+
+mod allocation;
+mod context;
+mod defs;
+mod node;
+mod process;
+mod range_alloc;
+mod thread;
+mod transaction;
+
+use {context::Context, thread::Thread};
+
+module! {
+    type: BinderModule,
+    name: b"rust_binder",
+    author: b"Wedson Almeida Filho",
+    description: b"Android Binder",
+    license: b"GPL",
+}
+
+enum Either<L, R> {
+    Left(L),
+    Right(R),
+}
+
+trait DeliverToRead {
+    /// Performs work. Returns true if remaining work items in the queue should be processed
+    /// immediately, or false if it should return to caller before processing additional work
+    /// items.
+    fn do_work(self: Ref<Self>, thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool>;
+
+    /// Cancels the given work item. This is called instead of [`DeliverToRead::do_work`] when work
+    /// won't be delivered.
+    fn cancel(self: Ref<Self>) {}
+
+    /// Returns the linked list links for the work item.
+    fn get_links(&self) -> &Links<dyn DeliverToRead>;
+}
+
+struct DeliverToReadListAdapter {}
+
+impl GetLinks for DeliverToReadListAdapter {
+    type EntryType = dyn DeliverToRead;
+
+    fn get_links(data: &Self::EntryType) -> &Links<Self::EntryType> {
+        data.get_links()
+    }
+}
+
+impl GetLinksWrapped for DeliverToReadListAdapter {
+    type Wrapped = Ref<dyn DeliverToRead>;
+}
+
+struct DeliverCode {
+    code: u32,
+    links: Links<dyn DeliverToRead>,
+}
+
+impl DeliverCode {
+    fn new(code: u32) -> Self {
+        Self {
+            code,
+            links: Links::new(),
+        }
+    }
+}
+
+impl DeliverToRead for DeliverCode {
+    fn do_work(self: Ref<Self>, _thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool> {
+        writer.write(&self.code)?;
+        Ok(true)
+    }
+
+    fn get_links(&self) -> &Links<dyn DeliverToRead> {
+        &self.links
+    }
+}
+
+const fn ptr_align(value: usize) -> usize {
+    let size = core::mem::size_of::<usize>() - 1;
+    (value + size) & !size
+}
+
+unsafe impl Sync for BinderModule {}
+
+struct BinderModule {
+    _reg: Pin<Box<Registration<process::Process>>>,
+}
+
+impl kernel::Module for BinderModule {
+    fn init(name: &'static CStr, _module: &'static kernel::ThisModule) -> Result<Self> {
+        let ctx = Context::new()?;
+        let reg = Registration::new_pinned(fmt!("{name}"), ctx)?;
+        Ok(Self { _reg: reg })
+    }
+}
diff --git a/drivers/android/thread.rs b/drivers/android/thread.rs
new file mode 100644
index 000000000000..817fca0890a7
--- /dev/null
+++ b/drivers/android/thread.rs
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::{
+    alloc::AllocError,
+    mem::size_of,
+    sync::atomic::{AtomicU32, Ordering},
+};
+use kernel::{
+    bindings,
+    file::{File, PollTable},
+    io_buffer::{IoBufferReader, IoBufferWriter},
+    linked_list::{GetLinks, Links, List},
+    prelude::*,
+    security,
+    sync::{CondVar, Ref, SpinLock, UniqueRef},
+    user_ptr::{UserSlicePtr, UserSlicePtrWriter},
+};
+
+use crate::{
+    allocation::{Allocation, AllocationView},
+    defs::*,
+    process::{AllocationInfo, Process},
+    ptr_align,
+    transaction::{FileInfo, Transaction},
+    DeliverCode, DeliverToRead, DeliverToReadListAdapter, Either,
+};
+
+pub(crate) type BinderResult<T = ()> = core::result::Result<T, BinderError>;
+
+pub(crate) struct BinderError {
+    pub(crate) reply: u32,
+}
+
+impl BinderError {
+    pub(crate) fn new_failed() -> Self {
+        Self {
+            reply: BR_FAILED_REPLY,
+        }
+    }
+
+    pub(crate) fn new_dead() -> Self {
+        Self {
+            reply: BR_DEAD_REPLY,
+        }
+    }
+}
+
+impl From<Error> for BinderError {
+    fn from(_: Error) -> Self {
+        Self::new_failed()
+    }
+}
+
+impl From<AllocError> for BinderError {
+    fn from(_: AllocError) -> Self {
+        Self::new_failed()
+    }
+}
+
+const LOOPER_REGISTERED: u32 = 0x01;
+const LOOPER_ENTERED: u32 = 0x02;
+const LOOPER_EXITED: u32 = 0x04;
+const LOOPER_INVALID: u32 = 0x08;
+const LOOPER_WAITING: u32 = 0x10;
+const LOOPER_POLL: u32 = 0x20;
+
+struct InnerThread {
+    /// Determines the looper state of the thread. It is a bit-wise combination of the constants
+    /// prefixed with `LOOPER_`.
+    looper_flags: u32,
+
+    /// Determines if thread is dead.
+    is_dead: bool,
+
+    /// Work item used to deliver error codes to the thread that started a transaction. When set to
+    /// `Some(x)`, it will hold the only reference to the object so that it can update the error
+    /// code to be delivered before queuing it.
+    reply_work: Option<Ref<ThreadError>>,
+
+    /// Work item used to deliver error codes to the current thread. When set to `Some(x)`, it will
+    /// hold the only reference to the object so that it can update the error code to be delivered
+    /// before queuing.
+    return_work: Option<Ref<ThreadError>>,
+
+    /// Determines whether the work list below should be processed. When set to false, `work_list`
+    /// is treated as if it were empty.
+    process_work_list: bool,
+    work_list: List<DeliverToReadListAdapter>,
+    current_transaction: Option<Ref<Transaction>>,
+}
+
+impl InnerThread {
+    fn new() -> Self {
+        Self {
+            looper_flags: 0,
+            is_dead: false,
+            process_work_list: false,
+            work_list: List::new(),
+            current_transaction: None,
+            return_work: None,
+            reply_work: None,
+        }
+    }
+
+    fn set_reply_work(&mut self, reply_work: Ref<ThreadError>) {
+        self.reply_work = Some(reply_work);
+    }
+
+    fn push_reply_work(&mut self, code: u32) {
+        let work = self.reply_work.take();
+        self.push_existing_work(work, code);
+    }
+
+    fn set_return_work(&mut self, return_work: Ref<ThreadError>) {
+        self.return_work = Some(return_work);
+    }
+
+    fn push_return_work(&mut self, code: u32) {
+        let work = self.return_work.take();
+        self.push_existing_work(work, code);
+    }
+
+    fn push_existing_work(&mut self, owork: Option<Ref<ThreadError>>, code: u32) {
+        // TODO: Write some warning when the following fails. It should not happen, and
+        // if it does, there is likely something wrong.
+        if let Some(work) = owork {
+            // `error_code` is written to with relaxed semantics because the queue onto which it is
+            // being inserted is protected by a lock. The release barrier when the lock is released
+            // by the caller matches with the acquire barrier of the future reader to guarantee
+            // that `error_code` is visible.
+            work.error_code.store(code, Ordering::Relaxed);
+            self.push_work(work);
+        }
+    }
+
+    fn pop_work(&mut self) -> Option<Ref<dyn DeliverToRead>> {
+        if !self.process_work_list {
+            return None;
+        }
+
+        let ret = self.work_list.pop_front();
+        // Once the queue is drained, we stop processing it until a non-deferred item is pushed
+        // again onto it.
+        self.process_work_list = !self.work_list.is_empty();
+        ret
+    }
+
+    fn push_work_deferred(&mut self, work: Ref<dyn DeliverToRead>) {
+        self.work_list.push_back(work);
+    }
+
+    fn push_work(&mut self, work: Ref<dyn DeliverToRead>) {
+        self.push_work_deferred(work);
+        self.process_work_list = true;
+    }
+
+    fn has_work(&self) -> bool {
+        self.process_work_list && !self.work_list.is_empty()
+    }
+
+    /// Fetches the transaction the thread can reply to. If the thread has a pending transaction
+    /// (that it could respond to) but it has also issued a transaction, it must first wait for the
+    /// previously-issued transaction to complete.
+    fn pop_transaction_to_reply(&mut self, thread: &Thread) -> Result<Ref<Transaction>> {
+        let transaction = self.current_transaction.take().ok_or(EINVAL)?;
+
+        if core::ptr::eq(thread, transaction.from.as_ref()) {
+            self.current_transaction = Some(transaction);
+            return Err(EINVAL);
+        }
+
+        // Find a new current transaction for this thread.
+        self.current_transaction = transaction.find_from(thread);
+        Ok(transaction)
+    }
+
+    fn pop_transaction_replied(&mut self, transaction: &Ref<Transaction>) -> bool {
+        match self.current_transaction.take() {
+            None => false,
+            Some(old) => {
+                if !Ref::ptr_eq(transaction, &old) {
+                    self.current_transaction = Some(old);
+                    return false;
+                }
+                self.current_transaction = old.clone_next();
+                true
+            }
+        }
+    }
+
+    fn looper_enter(&mut self) {
+        self.looper_flags |= LOOPER_ENTERED;
+        if self.looper_flags & LOOPER_REGISTERED != 0 {
+            self.looper_flags |= LOOPER_INVALID;
+        }
+    }
+
+    fn looper_register(&mut self, valid: bool) {
+        self.looper_flags |= LOOPER_REGISTERED;
+        if !valid || self.looper_flags & LOOPER_ENTERED != 0 {
+            self.looper_flags |= LOOPER_INVALID;
+        }
+    }
+
+    fn looper_exit(&mut self) {
+        self.looper_flags |= LOOPER_EXITED;
+    }
+
+    /// Determines whether the thread is part of a pool, i.e., if it is a looper.
+    fn is_looper(&self) -> bool {
+        self.looper_flags & (LOOPER_ENTERED | LOOPER_REGISTERED) != 0
+    }
+
+    /// Determines whether the thread should attempt to fetch work items from the process queue
+    /// (when its own queue is empty). This is case when the thread is not part of a transaction
+    /// stack and it is registered as a looper.
+    fn should_use_process_work_queue(&self) -> bool {
+        self.current_transaction.is_none() && self.is_looper()
+    }
+
+    fn poll(&mut self) -> u32 {
+        self.looper_flags |= LOOPER_POLL;
+        if self.has_work() {
+            bindings::POLLIN
+        } else {
+            0
+        }
+    }
+}
+
+pub(crate) struct Thread {
+    pub(crate) id: i32,
+    pub(crate) process: Ref<Process>,
+    inner: SpinLock<InnerThread>,
+    work_condvar: CondVar,
+    links: Links<Thread>,
+}
+
+impl Thread {
+    pub(crate) fn new(id: i32, process: Ref<Process>) -> Result<Ref<Self>> {
+        let return_work = Ref::try_new(ThreadError::new(InnerThread::set_return_work))?;
+        let reply_work = Ref::try_new(ThreadError::new(InnerThread::set_reply_work))?;
+        let mut thread = Pin::from(UniqueRef::try_new(Self {
+            id,
+            process,
+            // SAFETY: `inner` is initialised in the call to `spinlock_init` below.
+            inner: unsafe { SpinLock::new(InnerThread::new()) },
+            // SAFETY: `work_condvar` is initialised in the call to `condvar_init` below.
+            work_condvar: unsafe { CondVar::new() },
+            links: Links::new(),
+        })?);
+
+        // SAFETY: `inner` is pinned when `thread` is.
+        let inner = unsafe { thread.as_mut().map_unchecked_mut(|t| &mut t.inner) };
+        kernel::spinlock_init!(inner, "Thread::inner");
+
+        // SAFETY: `work_condvar` is pinned when `thread` is.
+        let condvar = unsafe { thread.as_mut().map_unchecked_mut(|t| &mut t.work_condvar) };
+        kernel::condvar_init!(condvar, "Thread::work_condvar");
+
+        {
+            let mut inner = thread.inner.lock();
+            inner.set_reply_work(reply_work);
+            inner.set_return_work(return_work);
+        }
+
+        Ok(thread.into())
+    }
+
+    pub(crate) fn set_current_transaction(&self, transaction: Ref<Transaction>) {
+        self.inner.lock().current_transaction = Some(transaction);
+    }
+
+    /// Attempts to fetch a work item from the thread-local queue. The behaviour if the queue is
+    /// empty depends on `wait`: if it is true, the function waits for some work to be queued (or a
+    /// signal); otherwise it returns indicating that none is available.
+    fn get_work_local(self: &Ref<Self>, wait: bool) -> Result<Ref<dyn DeliverToRead>> {
+        // Try once if the caller does not want to wait.
+        if !wait {
+            return self.inner.lock().pop_work().ok_or(EAGAIN);
+        }
+
+        // Loop waiting only on the local queue (i.e., not registering with the process queue).
+        let mut inner = self.inner.lock();
+        loop {
+            if let Some(work) = inner.pop_work() {
+                return Ok(work);
+            }
+
+            inner.looper_flags |= LOOPER_WAITING;
+            let signal_pending = self.work_condvar.wait(&mut inner);
+            inner.looper_flags &= !LOOPER_WAITING;
+
+            if signal_pending {
+                return Err(ERESTARTSYS);
+            }
+        }
+    }
+
+    /// Attempts to fetch a work item from the thread-local queue, falling back to the process-wide
+    /// queue if none is available locally.
+    ///
+    /// This must only be called when the thread is not participating in a transaction chain. If it
+    /// is, the local version (`get_work_local`) should be used instead.
+    fn get_work(self: &Ref<Self>, wait: bool) -> Result<Ref<dyn DeliverToRead>> {
+        // Try to get work from the thread's work queue, using only a local lock.
+        {
+            let mut inner = self.inner.lock();
+            if let Some(work) = inner.pop_work() {
+                return Ok(work);
+            }
+        }
+
+        // If the caller doesn't want to wait, try to grab work from the process queue.
+        //
+        // We know nothing will have been queued directly to the thread queue because it is not in
+        // a transaction and it is not in the process' ready list.
+        if !wait {
+            return self.process.get_work().ok_or(EAGAIN);
+        }
+
+        // Get work from the process queue. If none is available, atomically register as ready.
+        let reg = match self.process.get_work_or_register(self) {
+            Either::Left(work) => return Ok(work),
+            Either::Right(reg) => reg,
+        };
+
+        let mut inner = self.inner.lock();
+        loop {
+            if let Some(work) = inner.pop_work() {
+                return Ok(work);
+            }
+
+            inner.looper_flags |= LOOPER_WAITING;
+            let signal_pending = self.work_condvar.wait(&mut inner);
+            inner.looper_flags &= !LOOPER_WAITING;
+
+            if signal_pending {
+                // A signal is pending. We need to pull the thread off the list, then check the
+                // state again after it's off the list to ensure that something was not queued in
+                // the meantime. If something has been queued, we just return it (instead of the
+                // error).
+                drop(inner);
+                drop(reg);
+                return self.inner.lock().pop_work().ok_or(ERESTARTSYS);
+            }
+        }
+    }
+
+    pub(crate) fn push_work(&self, work: Ref<dyn DeliverToRead>) -> BinderResult {
+        {
+            let mut inner = self.inner.lock();
+            if inner.is_dead {
+                return Err(BinderError::new_dead());
+            }
+            inner.push_work(work);
+        }
+        self.work_condvar.notify_one();
+        Ok(())
+    }
+
+    /// Attempts to push to given work item to the thread if it's a looper thread (i.e., if it's
+    /// part of a thread pool) and is alive. Otherwise, push the work item to the process instead.
+    pub(crate) fn push_work_if_looper(&self, work: Ref<dyn DeliverToRead>) -> BinderResult {
+        let mut inner = self.inner.lock();
+        if inner.is_looper() && !inner.is_dead {
+            inner.push_work(work);
+            Ok(())
+        } else {
+            drop(inner);
+            self.process.push_work(work)
+        }
+    }
+
+    pub(crate) fn push_work_deferred(&self, work: Ref<dyn DeliverToRead>) {
+        self.inner.lock().push_work_deferred(work);
+    }
+
+    fn translate_object(
+        &self,
+        index_offset: usize,
+        view: &mut AllocationView<'_, '_>,
+        allow_fds: bool,
+    ) -> BinderResult {
+        let offset = view.alloc.read(index_offset)?;
+        let header = view.read::<bindings::binder_object_header>(offset)?;
+        // TODO: Handle other types.
+        match header.type_ {
+            BINDER_TYPE_WEAK_BINDER | BINDER_TYPE_BINDER => {
+                let strong = header.type_ == BINDER_TYPE_BINDER;
+                view.transfer_binder_object(offset, strong, |obj| {
+                    // SAFETY: `binder` is a `binder_uintptr_t`; any bit pattern is a valid
+                    // representation.
+                    let ptr = unsafe { obj.__bindgen_anon_1.binder } as _;
+                    let cookie = obj.cookie as _;
+                    let flags = obj.flags as _;
+                    let node = self.process.as_ref_borrow().get_node(
+                        ptr,
+                        cookie,
+                        flags,
+                        strong,
+                        Some(self),
+                    )?;
+                    security::binder_transfer_binder(&self.process.cred, &view.alloc.process.cred)?;
+                    Ok(node)
+                })?;
+            }
+            BINDER_TYPE_WEAK_HANDLE | BINDER_TYPE_HANDLE => {
+                let strong = header.type_ == BINDER_TYPE_HANDLE;
+                view.transfer_binder_object(offset, strong, |obj| {
+                    // SAFETY: `handle` is a `u32`; any bit pattern is a valid representation.
+                    let handle = unsafe { obj.__bindgen_anon_1.handle } as _;
+                    let node = self.process.get_node_from_handle(handle, strong)?;
+                    security::binder_transfer_binder(&self.process.cred, &view.alloc.process.cred)?;
+                    Ok(node)
+                })?;
+            }
+            BINDER_TYPE_FD => {
+                if !allow_fds {
+                    return Err(BinderError::new_failed());
+                }
+
+                let obj = view.read::<bindings::binder_fd_object>(offset)?;
+                // SAFETY: `fd` is a `u32`; any bit pattern is a valid representation.
+                let fd = unsafe { obj.__bindgen_anon_1.fd };
+                let file = File::from_fd(fd)?;
+                security::binder_transfer_file(
+                    &self.process.cred,
+                    &view.alloc.process.cred,
+                    &file,
+                )?;
+                let field_offset =
+                    kernel::offset_of!(bindings::binder_fd_object, __bindgen_anon_1.fd) as usize;
+                let file_info = Box::try_new(FileInfo::new(file, offset + field_offset))?;
+                view.alloc.add_file_info(file_info);
+            }
+            _ => pr_warn!("Unsupported binder object type: {:x}\n", header.type_),
+        }
+        Ok(())
+    }
+
+    fn translate_objects(
+        &self,
+        alloc: &mut Allocation<'_>,
+        start: usize,
+        end: usize,
+        allow_fds: bool,
+    ) -> BinderResult {
+        let mut view = AllocationView::new(alloc, start);
+        for i in (start..end).step_by(size_of::<usize>()) {
+            if let Err(err) = self.translate_object(i, &mut view, allow_fds) {
+                alloc.set_info(AllocationInfo { offsets: start..i });
+                return Err(err);
+            }
+        }
+        alloc.set_info(AllocationInfo {
+            offsets: start..end,
+        });
+        Ok(())
+    }
+
+    pub(crate) fn copy_transaction_data<'a>(
+        &self,
+        to_process: &'a Process,
+        tr: &BinderTransactionData,
+        allow_fds: bool,
+    ) -> BinderResult<Allocation<'a>> {
+        let data_size = tr.data_size as _;
+        let adata_size = ptr_align(data_size);
+        let offsets_size = tr.offsets_size as _;
+        let aoffsets_size = ptr_align(offsets_size);
+
+        // This guarantees that at least `sizeof(usize)` bytes will be allocated.
+        let len = core::cmp::max(
+            adata_size.checked_add(aoffsets_size).ok_or(ENOMEM)?,
+            size_of::<usize>(),
+        );
+        let mut alloc = to_process.buffer_alloc(len)?;
+
+        // Copy raw data.
+        let mut reader = unsafe { UserSlicePtr::new(tr.data.ptr.buffer as _, data_size) }.reader();
+        alloc.copy_into(&mut reader, 0, data_size)?;
+
+        // Copy offsets if there are any.
+        if offsets_size > 0 {
+            let mut reader =
+                unsafe { UserSlicePtr::new(tr.data.ptr.offsets as _, offsets_size) }.reader();
+            alloc.copy_into(&mut reader, adata_size, offsets_size)?;
+
+            // Traverse the objects specified.
+            self.translate_objects(
+                &mut alloc,
+                adata_size,
+                adata_size + aoffsets_size,
+                allow_fds,
+            )?;
+        }
+
+        Ok(alloc)
+    }
+
+    fn unwind_transaction_stack(self: &Ref<Self>) {
+        let mut thread = self.clone();
+        while let Ok(transaction) = {
+            let mut inner = thread.inner.lock();
+            inner.pop_transaction_to_reply(thread.as_ref())
+        } {
+            let reply = Either::Right(BR_DEAD_REPLY);
+            if !transaction.from.deliver_single_reply(reply, &transaction) {
+                break;
+            }
+
+            thread = transaction.from.clone();
+        }
+    }
+
+    pub(crate) fn deliver_reply(
+        &self,
+        reply: Either<Ref<Transaction>, u32>,
+        transaction: &Ref<Transaction>,
+    ) {
+        if self.deliver_single_reply(reply, transaction) {
+            transaction.from.unwind_transaction_stack();
+        }
+    }
+
+    /// Delivers a reply to the thread that started a transaction. The reply can either be a
+    /// reply-transaction or an error code to be delivered instead.
+    ///
+    /// Returns whether the thread is dead. If it is, the caller is expected to unwind the
+    /// transaction stack by completing transactions for threads that are dead.
+    fn deliver_single_reply(
+        &self,
+        reply: Either<Ref<Transaction>, u32>,
+        transaction: &Ref<Transaction>,
+    ) -> bool {
+        {
+            let mut inner = self.inner.lock();
+            if !inner.pop_transaction_replied(transaction) {
+                return false;
+            }
+
+            if inner.is_dead {
+                return true;
+            }
+
+            match reply {
+                Either::Left(work) => inner.push_work(work),
+                Either::Right(code) => inner.push_reply_work(code),
+            }
+        }
+
+        // Notify the thread now that we've released the inner lock.
+        self.work_condvar.notify_one();
+        false
+    }
+
+    /// Determines if the given transaction is the current transaction for this thread.
+    fn is_current_transaction(&self, transaction: &Ref<Transaction>) -> bool {
+        let inner = self.inner.lock();
+        match &inner.current_transaction {
+            None => false,
+            Some(current) => Ref::ptr_eq(current, transaction),
+        }
+    }
+
+    fn transaction<T>(self: &Ref<Self>, tr: &BinderTransactionData, inner: T)
+    where
+        T: FnOnce(&Ref<Self>, &BinderTransactionData) -> BinderResult,
+    {
+        if let Err(err) = inner(self, tr) {
+            self.inner.lock().push_return_work(err.reply);
+        }
+    }
+
+    fn reply_inner(self: &Ref<Self>, tr: &BinderTransactionData) -> BinderResult {
+        let orig = self.inner.lock().pop_transaction_to_reply(self)?;
+        if !orig.from.is_current_transaction(&orig) {
+            return Err(BinderError::new_failed());
+        }
+
+        // We need to complete the transaction even if we cannot complete building the reply.
+        (|| -> BinderResult<_> {
+            let completion = Ref::try_new(DeliverCode::new(BR_TRANSACTION_COMPLETE))?;
+            let process = orig.from.process.clone();
+            let allow_fds = orig.flags & TF_ACCEPT_FDS != 0;
+            let reply = Transaction::new_reply(self, process, tr, allow_fds)?;
+            self.inner.lock().push_work(completion);
+            orig.from.deliver_reply(Either::Left(reply), &orig);
+            Ok(())
+        })()
+        .map_err(|mut err| {
+            // At this point we only return `BR_TRANSACTION_COMPLETE` to the caller, and we must let
+            // the sender know that the transaction has completed (with an error in this case).
+            let reply = Either::Right(BR_FAILED_REPLY);
+            orig.from.deliver_reply(reply, &orig);
+            err.reply = BR_TRANSACTION_COMPLETE;
+            err
+        })
+    }
+
+    /// Determines the current top of the transaction stack. It fails if the top is in another
+    /// thread (i.e., this thread belongs to a stack but it has called another thread). The top is
+    /// [`None`] if the thread is not currently participating in a transaction stack.
+    fn top_of_transaction_stack(&self) -> Result<Option<Ref<Transaction>>> {
+        let inner = self.inner.lock();
+        Ok(if let Some(cur) = &inner.current_transaction {
+            if core::ptr::eq(self, cur.from.as_ref()) {
+                return Err(EINVAL);
+            }
+            Some(cur.clone())
+        } else {
+            None
+        })
+    }
+
+    fn oneway_transaction_inner(self: &Ref<Self>, tr: &BinderTransactionData) -> BinderResult {
+        let handle = unsafe { tr.target.handle };
+        let node_ref = self.process.get_transaction_node(handle)?;
+        security::binder_transaction(&self.process.cred, &node_ref.node.owner.cred)?;
+        let completion = Ref::try_new(DeliverCode::new(BR_TRANSACTION_COMPLETE))?;
+        let transaction = Transaction::new(node_ref, None, self, tr)?;
+        self.inner.lock().push_work(completion);
+        // TODO: Remove the completion on error?
+        transaction.submit()?;
+        Ok(())
+    }
+
+    fn transaction_inner(self: &Ref<Self>, tr: &BinderTransactionData) -> BinderResult {
+        let handle = unsafe { tr.target.handle };
+        let node_ref = self.process.get_transaction_node(handle)?;
+        security::binder_transaction(&self.process.cred, &node_ref.node.owner.cred)?;
+        // TODO: We need to ensure that there isn't a pending transaction in the work queue. How
+        // could this happen?
+        let top = self.top_of_transaction_stack()?;
+        let completion = Ref::try_new(DeliverCode::new(BR_TRANSACTION_COMPLETE))?;
+        let transaction = Transaction::new(node_ref, top, self, tr)?;
+
+        // Check that the transaction stack hasn't changed while the lock was released, then update
+        // it with the new transaction.
+        {
+            let mut inner = self.inner.lock();
+            if !transaction.is_stacked_on(&inner.current_transaction) {
+                return Err(BinderError::new_failed());
+            }
+            inner.current_transaction = Some(transaction.clone());
+        }
+
+        // We push the completion as a deferred work so that we wait for the reply before returning
+        // to userland.
+        self.push_work_deferred(completion);
+        // TODO: Remove completion if submission fails?
+        transaction.submit()?;
+        Ok(())
+    }
+
+    fn write(self: &Ref<Self>, req: &mut BinderWriteRead) -> Result {
+        let write_start = req.write_buffer.wrapping_add(req.write_consumed);
+        let write_len = req.write_size - req.write_consumed;
+        let mut reader = unsafe { UserSlicePtr::new(write_start as _, write_len as _).reader() };
+
+        while reader.len() >= size_of::<u32>() && self.inner.lock().return_work.is_some() {
+            let before = reader.len();
+            match reader.read::<u32>()? {
+                BC_TRANSACTION => {
+                    let tr = reader.read::<BinderTransactionData>()?;
+                    if tr.flags & TF_ONE_WAY != 0 {
+                        self.transaction(&tr, Self::oneway_transaction_inner)
+                    } else {
+                        self.transaction(&tr, Self::transaction_inner)
+                    }
+                }
+                BC_REPLY => self.transaction(&reader.read()?, Self::reply_inner),
+                BC_FREE_BUFFER => drop(self.process.buffer_get(reader.read()?)),
+                BC_INCREFS => self.process.update_ref(reader.read()?, true, false)?,
+                BC_ACQUIRE => self.process.update_ref(reader.read()?, true, true)?,
+                BC_RELEASE => self.process.update_ref(reader.read()?, false, true)?,
+                BC_DECREFS => self.process.update_ref(reader.read()?, false, false)?,
+                BC_INCREFS_DONE => self.process.inc_ref_done(&mut reader, false)?,
+                BC_ACQUIRE_DONE => self.process.inc_ref_done(&mut reader, true)?,
+                BC_REQUEST_DEATH_NOTIFICATION => self.process.request_death(&mut reader, self)?,
+                BC_CLEAR_DEATH_NOTIFICATION => self.process.clear_death(&mut reader, self)?,
+                BC_DEAD_BINDER_DONE => self.process.dead_binder_done(reader.read()?, self),
+                BC_REGISTER_LOOPER => {
+                    let valid = self.process.register_thread();
+                    self.inner.lock().looper_register(valid);
+                }
+                BC_ENTER_LOOPER => self.inner.lock().looper_enter(),
+                BC_EXIT_LOOPER => self.inner.lock().looper_exit(),
+
+                // TODO: Add support for BC_TRANSACTION_SG and BC_REPLY_SG.
+                // BC_ATTEMPT_ACQUIRE and BC_ACQUIRE_RESULT are no longer supported.
+                _ => return Err(EINVAL),
+            }
+
+            // Update the number of write bytes consumed.
+            req.write_consumed += (before - reader.len()) as u64;
+        }
+        Ok(())
+    }
+
+    fn read(self: &Ref<Self>, req: &mut BinderWriteRead, wait: bool) -> Result {
+        let read_start = req.read_buffer.wrapping_add(req.read_consumed);
+        let read_len = req.read_size - req.read_consumed;
+        let mut writer = unsafe { UserSlicePtr::new(read_start as _, read_len as _) }.writer();
+        let (in_pool, getter) = {
+            let inner = self.inner.lock();
+            (
+                inner.is_looper(),
+                if inner.should_use_process_work_queue() {
+                    Self::get_work
+                } else {
+                    Self::get_work_local
+                },
+            )
+        };
+
+        // Reserve some room at the beginning of the read buffer so that we can send a
+        // BR_SPAWN_LOOPER if we need to.
+        if req.read_consumed == 0 {
+            writer.write(&BR_NOOP)?;
+        }
+
+        // Loop doing work while there is room in the buffer.
+        let initial_len = writer.len();
+        while writer.len() >= size_of::<u32>() {
+            match getter(self, wait && initial_len == writer.len()) {
+                Ok(work) => {
+                    if !work.do_work(self, &mut writer)? {
+                        break;
+                    }
+                }
+                Err(err) => {
+                    // Propagate the error if we haven't written anything else.
+                    if initial_len == writer.len() {
+                        return Err(err);
+                    } else {
+                        break;
+                    }
+                }
+            }
+        }
+
+        req.read_consumed += read_len - writer.len() as u64;
+
+        // Write BR_SPAWN_LOOPER if the process needs more threads for its pool.
+        if in_pool && self.process.needs_thread() {
+            let mut writer =
+                unsafe { UserSlicePtr::new(req.read_buffer as _, req.read_size as _) }.writer();
+            writer.write(&BR_SPAWN_LOOPER)?;
+        }
+
+        Ok(())
+    }
+
+    pub(crate) fn write_read(self: &Ref<Self>, data: UserSlicePtr, wait: bool) -> Result {
+        let (mut reader, mut writer) = data.reader_writer();
+        let mut req = reader.read::<BinderWriteRead>()?;
+
+        // TODO: `write(&req)` happens in all exit paths from here on. Find a better way to encode
+        // it.
+
+        // Go through the write buffer.
+        if req.write_size > 0 {
+            if let Err(err) = self.write(&mut req) {
+                req.read_consumed = 0;
+                writer.write(&req)?;
+                return Err(err);
+            }
+        }
+
+        // Go through the work queue.
+        let mut ret = Ok(());
+        if req.read_size > 0 {
+            ret = self.read(&mut req, wait);
+        }
+
+        // Write the request back so that the consumed fields are visible to the caller.
+        writer.write(&req)?;
+        ret
+    }
+
+    pub(crate) fn poll(&self, file: &File, table: &PollTable) -> (bool, u32) {
+        // SAFETY: `free_waiters` is called on release.
+        unsafe { table.register_wait(file, &self.work_condvar) };
+        let mut inner = self.inner.lock();
+        (inner.should_use_process_work_queue(), inner.poll())
+    }
+
+    pub(crate) fn notify_if_poll_ready(&self) {
+        // Determine if we need to notify. This requires the lock.
+        let inner = self.inner.lock();
+        let notify = inner.looper_flags & LOOPER_POLL != 0
+            && inner.should_use_process_work_queue()
+            && !inner.has_work();
+        drop(inner);
+
+        // Now that the lock is no longer held, notify the waiters if we have to.
+        if notify {
+            self.work_condvar.notify_one();
+        }
+    }
+
+    pub(crate) fn push_return_work(&self, code: u32) {
+        self.inner.lock().push_return_work(code)
+    }
+
+    pub(crate) fn release(self: &Ref<Self>) {
+        // Mark the thread as dead.
+        self.inner.lock().is_dead = true;
+
+        // Cancel all pending work items.
+        while let Ok(work) = self.get_work_local(false) {
+            work.cancel();
+        }
+
+        // Complete the transaction stack as far as we can.
+        self.unwind_transaction_stack();
+
+        // Remove epoll items if polling was ever used on the thread.
+        let poller = self.inner.lock().looper_flags & LOOPER_POLL != 0;
+        if poller {
+            self.work_condvar.free_waiters();
+
+            unsafe { bindings::synchronize_rcu() };
+        }
+    }
+}
+
+impl GetLinks for Thread {
+    type EntryType = Thread;
+    fn get_links(data: &Thread) -> &Links<Thread> {
+        &data.links
+    }
+}
+
+struct ThreadError {
+    error_code: AtomicU32,
+    return_fn: fn(&mut InnerThread, Ref<ThreadError>),
+    links: Links<dyn DeliverToRead>,
+}
+
+impl ThreadError {
+    fn new(return_fn: fn(&mut InnerThread, Ref<ThreadError>)) -> Self {
+        Self {
+            error_code: AtomicU32::new(BR_OK),
+            return_fn,
+            links: Links::new(),
+        }
+    }
+}
+
+impl DeliverToRead for ThreadError {
+    fn do_work(self: Ref<Self>, thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool> {
+        // See `ThreadInner::push_existing_work` for the reason why `error_code` is up to date even
+        // though we use relaxed semantics.
+        let code = self.error_code.load(Ordering::Relaxed);
+
+        // Return the `ThreadError` to the thread.
+        (self.return_fn)(&mut *thread.inner.lock(), self);
+
+        // Deliver the error code to userspace.
+        writer.write(&code)?;
+        Ok(true)
+    }
+
+    fn get_links(&self) -> &Links<dyn DeliverToRead> {
+        &self.links
+    }
+}
diff --git a/drivers/android/transaction.rs b/drivers/android/transaction.rs
new file mode 100644
index 000000000000..8ddf6e21c9cd
--- /dev/null
+++ b/drivers/android/transaction.rs
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use core::sync::atomic::{AtomicBool, Ordering};
+use kernel::{
+    bindings,
+    file::{File, FileDescriptorReservation},
+    io_buffer::IoBufferWriter,
+    linked_list::List,
+    linked_list::{GetLinks, Links},
+    prelude::*,
+    sync::{Ref, SpinLock, UniqueRef},
+    user_ptr::UserSlicePtrWriter,
+    ScopeGuard,
+};
+
+use crate::{
+    defs::*,
+    node::NodeRef,
+    process::Process,
+    ptr_align,
+    thread::{BinderResult, Thread},
+    DeliverToRead, Either,
+};
+
+struct TransactionInner {
+    file_list: List<Box<FileInfo>>,
+}
+
+pub(crate) struct Transaction {
+    inner: SpinLock<TransactionInner>,
+    // TODO: Node should be released when the buffer is released.
+    node_ref: Option<NodeRef>,
+    stack_next: Option<Ref<Transaction>>,
+    pub(crate) from: Ref<Thread>,
+    to: Ref<Process>,
+    free_allocation: AtomicBool,
+    code: u32,
+    pub(crate) flags: u32,
+    data_size: usize,
+    offsets_size: usize,
+    data_address: usize,
+    links: Links<dyn DeliverToRead>,
+}
+
+impl Transaction {
+    pub(crate) fn new(
+        node_ref: NodeRef,
+        stack_next: Option<Ref<Transaction>>,
+        from: &Ref<Thread>,
+        tr: &BinderTransactionData,
+    ) -> BinderResult<Ref<Self>> {
+        let allow_fds = node_ref.node.flags & FLAT_BINDER_FLAG_ACCEPTS_FDS != 0;
+        let to = node_ref.node.owner.clone();
+        let mut alloc = from.copy_transaction_data(&to, tr, allow_fds)?;
+        let data_address = alloc.ptr;
+        let file_list = alloc.take_file_list();
+        alloc.keep_alive();
+        let mut tr = Pin::from(UniqueRef::try_new(Self {
+            // SAFETY: `spinlock_init` is called below.
+            inner: unsafe { SpinLock::new(TransactionInner { file_list }) },
+            node_ref: Some(node_ref),
+            stack_next,
+            from: from.clone(),
+            to,
+            code: tr.code,
+            flags: tr.flags,
+            data_size: tr.data_size as _,
+            data_address,
+            offsets_size: tr.offsets_size as _,
+            links: Links::new(),
+            free_allocation: AtomicBool::new(true),
+        })?);
+
+        // SAFETY: `inner` is pinned when `tr` is.
+        let pinned = unsafe { tr.as_mut().map_unchecked_mut(|t| &mut t.inner) };
+        kernel::spinlock_init!(pinned, "Transaction::inner");
+
+        Ok(tr.into())
+    }
+
+    pub(crate) fn new_reply(
+        from: &Ref<Thread>,
+        to: Ref<Process>,
+        tr: &BinderTransactionData,
+        allow_fds: bool,
+    ) -> BinderResult<Ref<Self>> {
+        let mut alloc = from.copy_transaction_data(&to, tr, allow_fds)?;
+        let data_address = alloc.ptr;
+        let file_list = alloc.take_file_list();
+        alloc.keep_alive();
+        let mut tr = Pin::from(UniqueRef::try_new(Self {
+            // SAFETY: `spinlock_init` is called below.
+            inner: unsafe { SpinLock::new(TransactionInner { file_list }) },
+            node_ref: None,
+            stack_next: None,
+            from: from.clone(),
+            to,
+            code: tr.code,
+            flags: tr.flags,
+            data_size: tr.data_size as _,
+            data_address,
+            offsets_size: tr.offsets_size as _,
+            links: Links::new(),
+            free_allocation: AtomicBool::new(true),
+        })?);
+
+        // SAFETY: `inner` is pinned when `tr` is.
+        let pinned = unsafe { tr.as_mut().map_unchecked_mut(|t| &mut t.inner) };
+        kernel::spinlock_init!(pinned, "Transaction::inner");
+
+        Ok(tr.into())
+    }
+
+    /// Determines if the transaction is stacked on top of the given transaction.
+    pub(crate) fn is_stacked_on(&self, onext: &Option<Ref<Self>>) -> bool {
+        match (&self.stack_next, onext) {
+            (None, None) => true,
+            (Some(stack_next), Some(next)) => Ref::ptr_eq(stack_next, next),
+            _ => false,
+        }
+    }
+
+    /// Returns a pointer to the next transaction on the transaction stack, if there is one.
+    pub(crate) fn clone_next(&self) -> Option<Ref<Self>> {
+        let next = self.stack_next.as_ref()?;
+        Some(next.clone())
+    }
+
+    /// Searches in the transaction stack for a thread that belongs to the target process. This is
+    /// useful when finding a target for a new transaction: if the node belongs to a process that
+    /// is already part of the transaction stack, we reuse the thread.
+    fn find_target_thread(&self) -> Option<Ref<Thread>> {
+        let process = &self.node_ref.as_ref()?.node.owner;
+
+        let mut it = &self.stack_next;
+        while let Some(transaction) = it {
+            if Ref::ptr_eq(&transaction.from.process, process) {
+                return Some(transaction.from.clone());
+            }
+            it = &transaction.stack_next;
+        }
+        None
+    }
+
+    /// Searches in the transaction stack for a transaction originating at the given thread.
+    pub(crate) fn find_from(&self, thread: &Thread) -> Option<Ref<Transaction>> {
+        let mut it = &self.stack_next;
+        while let Some(transaction) = it {
+            if core::ptr::eq(thread, transaction.from.as_ref()) {
+                return Some(transaction.clone());
+            }
+
+            it = &transaction.stack_next;
+        }
+        None
+    }
+
+    /// Submits the transaction to a work queue. Use a thread if there is one in the transaction
+    /// stack, otherwise use the destination process.
+    pub(crate) fn submit(self: Ref<Self>) -> BinderResult {
+        if let Some(thread) = self.find_target_thread() {
+            thread.push_work(self)
+        } else {
+            let process = self.to.clone();
+            process.push_work(self)
+        }
+    }
+
+    /// Prepares the file list for delivery to the caller.
+    fn prepare_file_list(&self) -> Result<List<Box<FileInfo>>> {
+        // Get list of files that are being transferred as part of the transaction.
+        let mut file_list = core::mem::replace(&mut self.inner.lock().file_list, List::new());
+
+        // If the list is non-empty, prepare the buffer.
+        if !file_list.is_empty() {
+            let alloc = self.to.buffer_get(self.data_address).ok_or(ESRCH)?;
+            let cleanup = ScopeGuard::new(|| {
+                self.free_allocation.store(false, Ordering::Relaxed);
+            });
+
+            let mut it = file_list.cursor_front_mut();
+            while let Some(file_info) = it.current() {
+                let reservation = FileDescriptorReservation::new(bindings::O_CLOEXEC)?;
+                alloc.write(file_info.buffer_offset, &reservation.reserved_fd())?;
+                file_info.reservation = Some(reservation);
+                it.move_next();
+            }
+
+            alloc.keep_alive();
+            cleanup.dismiss();
+        }
+
+        Ok(file_list)
+    }
+}
+
+impl DeliverToRead for Transaction {
+    fn do_work(self: Ref<Self>, thread: &Thread, writer: &mut UserSlicePtrWriter) -> Result<bool> {
+        /* TODO: Initialise the following fields from tr:
+            pub sender_pid: pid_t,
+            pub sender_euid: uid_t,
+        */
+        let send_failed_reply = ScopeGuard::new(|| {
+            if self.node_ref.is_some() && self.flags & TF_ONE_WAY == 0 {
+                let reply = Either::Right(BR_FAILED_REPLY);
+                self.from.deliver_reply(reply, &self);
+            }
+        });
+        let mut file_list = if let Ok(list) = self.prepare_file_list() {
+            list
+        } else {
+            // On failure to process the list, we send a reply back to the sender and ignore the
+            // transaction on the recipient.
+            return Ok(true);
+        };
+
+        let mut tr = BinderTransactionData::default();
+
+        if let Some(nref) = &self.node_ref {
+            let (ptr, cookie) = nref.node.get_id();
+            tr.target.ptr = ptr as _;
+            tr.cookie = cookie as _;
+        };
+
+        tr.code = self.code;
+        tr.flags = self.flags;
+        tr.data_size = self.data_size as _;
+        tr.data.ptr.buffer = self.data_address as _;
+        tr.offsets_size = self.offsets_size as _;
+        if tr.offsets_size > 0 {
+            tr.data.ptr.offsets = (self.data_address + ptr_align(self.data_size)) as _;
+        }
+
+        let code = if self.node_ref.is_none() {
+            BR_REPLY
+        } else {
+            BR_TRANSACTION
+        };
+
+        // Write the transaction code and data to the user buffer.
+        writer.write(&code)?;
+        writer.write(&tr)?;
+
+        // Dismiss the completion of transaction with a failure. No failure paths are allowed from
+        // here on out.
+        send_failed_reply.dismiss();
+
+        // Commit all files.
+        {
+            let mut it = file_list.cursor_front_mut();
+            while let Some(file_info) = it.current() {
+                if let Some(reservation) = file_info.reservation.take() {
+                    if let Some(file) = file_info.file.take() {
+                        reservation.commit(file);
+                    }
+                }
+
+                it.move_next();
+            }
+        }
+
+        // When `drop` is called, we don't want the allocation to be freed because it is now the
+        // user's reponsibility to free it.
+        //
+        // `drop` is guaranteed to see this relaxed store because `Ref` guarantess that everything
+        // that happens when an object is referenced happens-before the eventual `drop`.
+        self.free_allocation.store(false, Ordering::Relaxed);
+
+        // When this is not a reply and not an async transaction, update `current_transaction`. If
+        // it's a reply, `current_transaction` has already been updated appropriately.
+        if self.node_ref.is_some() && tr.flags & TF_ONE_WAY == 0 {
+            thread.set_current_transaction(self);
+        }
+
+        Ok(false)
+    }
+
+    fn cancel(self: Ref<Self>) {
+        let reply = Either::Right(BR_DEAD_REPLY);
+        self.from.deliver_reply(reply, &self);
+    }
+
+    fn get_links(&self) -> &Links<dyn DeliverToRead> {
+        &self.links
+    }
+}
+
+impl Drop for Transaction {
+    fn drop(&mut self) {
+        if self.free_allocation.load(Ordering::Relaxed) {
+            self.to.buffer_get(self.data_address);
+        }
+    }
+}
+
+pub(crate) struct FileInfo {
+    links: Links<FileInfo>,
+
+    /// The file for which a descriptor will be created in the recipient process.
+    file: Option<ARef<File>>,
+
+    /// The file descriptor reservation on the recipient process.
+    reservation: Option<FileDescriptorReservation>,
+
+    /// The offset in the buffer where the file descriptor is stored.
+    buffer_offset: usize,
+}
+
+impl FileInfo {
+    pub(crate) fn new(file: ARef<File>, buffer_offset: usize) -> Self {
+        Self {
+            file: Some(file),
+            reservation: None,
+            buffer_offset,
+            links: Links::new(),
+        }
+    }
+}
+
+impl GetLinks for FileInfo {
+    type EntryType = Self;
+
+    fn get_links(data: &Self::EntryType) -> &Links<Self::EntryType> {
+        &data.links
+    }
+}
diff --git a/drivers/ata/libata-acpi.c b/drivers/ata/libata-acpi.c
index 3d345d173556..61b4ccf88bf1 100644
--- a/drivers/ata/libata-acpi.c
+++ b/drivers/ata/libata-acpi.c
@@ -480,10 +480,10 @@ static int ata_dev_get_GTF(struct ata_device *dev, struct ata_acpi_gtf **gtf)
  * RETURNS:
  * Determined xfermask.
  */
-unsigned long ata_acpi_gtm_xfermask(struct ata_device *dev,
-				    const struct ata_acpi_gtm *gtm)
+unsigned int ata_acpi_gtm_xfermask(struct ata_device *dev,
+				   const struct ata_acpi_gtm *gtm)
 {
-	unsigned long xfer_mask = 0;
+	unsigned int xfer_mask = 0;
 	unsigned int type;
 	int unit;
 	u8 mode;
@@ -525,7 +525,7 @@ int ata_acpi_cbl_80wire(struct ata_port *ap, const struct ata_acpi_gtm *gtm)
 	struct ata_device *dev;
 
 	ata_for_each_dev(dev, &ap->link, ENABLED) {
-		unsigned long xfer_mask, udma_mask;
+		unsigned int xfer_mask, udma_mask;
 
 		xfer_mask = ata_acpi_gtm_xfermask(dev, gtm);
 		ata_unpack_xfermask(xfer_mask, NULL, NULL, &udma_mask);
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 9601fa92950a..826d41f341e4 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -93,7 +93,7 @@ struct ata_force_param {
 	const char	*name;
 	u8		cbl;
 	u8		spd_limit;
-	unsigned long	xfer_mask;
+	unsigned int	xfer_mask;
 	unsigned int	horkage_on;
 	unsigned int	horkage_off;
 	u16		lflags_on;
@@ -425,7 +425,7 @@ static void ata_force_xfermask(struct ata_device *dev)
 
 	for (i = ata_force_tbl_size - 1; i >= 0; i--) {
 		const struct ata_force_ent *fe = &ata_force_tbl[i];
-		unsigned long pio_mask, mwdma_mask, udma_mask;
+		unsigned int pio_mask, mwdma_mask, udma_mask;
 
 		if (fe->port != -1 && fe->port != dev->link->ap->print_id)
 			continue;
@@ -803,11 +803,11 @@ int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
  *	RETURNS:
  *	Packed xfer_mask.
  */
-unsigned long ata_pack_xfermask(unsigned long pio_mask,
-				unsigned long mwdma_mask,
-				unsigned long udma_mask)
+unsigned int ata_pack_xfermask(unsigned int pio_mask,
+			       unsigned int mwdma_mask,
+			       unsigned int udma_mask)
 {
-	return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
+	return	((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
 		((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
 		((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
 }
@@ -823,8 +823,8 @@ EXPORT_SYMBOL_GPL(ata_pack_xfermask);
  *	Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
  *	Any NULL destination masks will be ignored.
  */
-void ata_unpack_xfermask(unsigned long xfer_mask, unsigned long *pio_mask,
-			 unsigned long *mwdma_mask, unsigned long *udma_mask)
+void ata_unpack_xfermask(unsigned int xfer_mask, unsigned int *pio_mask,
+			 unsigned int *mwdma_mask, unsigned int *udma_mask)
 {
 	if (pio_mask)
 		*pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
@@ -857,7 +857,7 @@ static const struct ata_xfer_ent {
  *	RETURNS:
  *	Matching XFER_* value, 0xff if no match found.
  */
-u8 ata_xfer_mask2mode(unsigned long xfer_mask)
+u8 ata_xfer_mask2mode(unsigned int xfer_mask)
 {
 	int highbit = fls(xfer_mask) - 1;
 	const struct ata_xfer_ent *ent;
@@ -881,7 +881,7 @@ EXPORT_SYMBOL_GPL(ata_xfer_mask2mode);
  *	RETURNS:
  *	Matching xfer_mask, 0 if no match found.
  */
-unsigned long ata_xfer_mode2mask(u8 xfer_mode)
+unsigned int ata_xfer_mode2mask(u8 xfer_mode)
 {
 	const struct ata_xfer_ent *ent;
 
@@ -930,7 +930,7 @@ EXPORT_SYMBOL_GPL(ata_xfer_mode2shift);
  *	Constant C string representing highest speed listed in
  *	@mode_mask, or the constant C string "<n/a>".
  */
-const char *ata_mode_string(unsigned long xfer_mask)
+const char *ata_mode_string(unsigned int xfer_mask)
 {
 	static const char * const xfer_mode_str[] = {
 		"PIO0",
@@ -1103,16 +1103,16 @@ static u64 ata_id_n_sectors(const u16 *id)
 	if (ata_id_has_lba(id)) {
 		if (ata_id_has_lba48(id))
 			return ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
-		else
-			return ata_id_u32(id, ATA_ID_LBA_CAPACITY);
-	} else {
-		if (ata_id_current_chs_valid(id))
-			return id[ATA_ID_CUR_CYLS] * id[ATA_ID_CUR_HEADS] *
-			       id[ATA_ID_CUR_SECTORS];
-		else
-			return id[ATA_ID_CYLS] * id[ATA_ID_HEADS] *
-			       id[ATA_ID_SECTORS];
+
+		return ata_id_u32(id, ATA_ID_LBA_CAPACITY);
 	}
+
+	if (ata_id_current_chs_valid(id))
+		return (u32)id[ATA_ID_CUR_CYLS] * (u32)id[ATA_ID_CUR_HEADS] *
+		       (u32)id[ATA_ID_CUR_SECTORS];
+
+	return (u32)id[ATA_ID_CYLS] * (u32)id[ATA_ID_HEADS] *
+	       (u32)id[ATA_ID_SECTORS];
 }
 
 u64 ata_tf_to_lba48(const struct ata_taskfile *tf)
@@ -1383,9 +1383,9 @@ static inline void ata_dump_id(struct ata_device *dev, const u16 *id)
  *	RETURNS:
  *	Computed xfermask
  */
-unsigned long ata_id_xfermask(const u16 *id)
+unsigned int ata_id_xfermask(const u16 *id)
 {
-	unsigned long pio_mask, mwdma_mask, udma_mask;
+	unsigned int pio_mask, mwdma_mask, udma_mask;
 
 	/* Usual case. Word 53 indicates word 64 is valid */
 	if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
@@ -1467,10 +1467,10 @@ static void ata_qc_complete_internal(struct ata_queued_cmd *qc)
  *	RETURNS:
  *	Zero on success, AC_ERR_* mask on failure
  */
-unsigned ata_exec_internal_sg(struct ata_device *dev,
-			      struct ata_taskfile *tf, const u8 *cdb,
-			      int dma_dir, struct scatterlist *sgl,
-			      unsigned int n_elem, unsigned long timeout)
+static unsigned ata_exec_internal_sg(struct ata_device *dev,
+				     struct ata_taskfile *tf, const u8 *cdb,
+				     int dma_dir, struct scatterlist *sgl,
+				     unsigned int n_elem, unsigned int timeout)
 {
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
@@ -1645,7 +1645,7 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
 unsigned ata_exec_internal(struct ata_device *dev,
 			   struct ata_taskfile *tf, const u8 *cdb,
 			   int dma_dir, void *buf, unsigned int buflen,
-			   unsigned long timeout)
+			   unsigned int timeout)
 {
 	struct scatterlist *psg = NULL, sg;
 	unsigned int n_elem = 0;
@@ -2534,7 +2534,7 @@ int ata_dev_configure(struct ata_device *dev)
 	struct ata_port *ap = dev->link->ap;
 	bool print_info = ata_dev_print_info(dev);
 	const u16 *id = dev->id;
-	unsigned long xfer_mask;
+	unsigned int xfer_mask;
 	unsigned int err_mask;
 	char revbuf[7];		/* XYZ-99\0 */
 	char fwrevbuf[ATA_ID_FW_REV_LEN+1];
@@ -3202,8 +3202,8 @@ u8 ata_timing_cycle2mode(unsigned int xfer_shift, int cycle)
 int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel)
 {
 	char buf[32];
-	unsigned long orig_mask, xfer_mask;
-	unsigned long pio_mask, mwdma_mask, udma_mask;
+	unsigned int orig_mask, xfer_mask;
+	unsigned int pio_mask, mwdma_mask, udma_mask;
 	int quiet, highbit;
 
 	quiet = !!(sel & ATA_DNXFER_QUIET);
@@ -3381,7 +3381,7 @@ int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
 
 	/* step 1: calculate xfer_mask */
 	ata_for_each_dev(dev, link, ENABLED) {
-		unsigned long pio_mask, dma_mask;
+		unsigned int pio_mask, dma_mask;
 		unsigned int mode_mask;
 
 		mode_mask = ATA_DMA_MASK_ATA;
@@ -4217,7 +4217,7 @@ static void ata_dev_xfermask(struct ata_device *dev)
 	struct ata_link *link = dev->link;
 	struct ata_port *ap = link->ap;
 	struct ata_host *host = ap->host;
-	unsigned long xfer_mask;
+	unsigned int xfer_mask;
 
 	/* controller modes available */
 	xfer_mask = ata_pack_xfermask(ap->pio_mask,
@@ -4342,7 +4342,7 @@ unsigned int ata_dev_set_feature(struct ata_device *dev, u8 enable, u8 feature)
 {
 	struct ata_taskfile tf;
 	unsigned int err_mask;
-	unsigned long timeout = 0;
+	unsigned int timeout = 0;
 
 	/* set up set-features taskfile */
 	ata_dev_dbg(dev, "set features - SATA features\n");
@@ -5776,7 +5776,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
 	/* set cable, sata_spd_limit and report */
 	for (i = 0; i < host->n_ports; i++) {
 		struct ata_port *ap = host->ports[i];
-		unsigned long xfer_mask;
+		unsigned int xfer_mask;
 
 		/* set SATA cable type if still unset */
 		if (ap->cbl == ATA_CBL_NONE && (ap->flags & ATA_FLAG_SATA))
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 3307ed45fe4d..ef4508d72c02 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -86,36 +86,36 @@ static const unsigned long ata_eh_reset_timeouts[] = {
 	ULONG_MAX, /* > 1 min has elapsed, give up */
 };
 
-static const unsigned long ata_eh_identify_timeouts[] = {
+static const unsigned int ata_eh_identify_timeouts[] = {
 	 5000,	/* covers > 99% of successes and not too boring on failures */
 	10000,  /* combined time till here is enough even for media access */
 	30000,	/* for true idiots */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
-static const unsigned long ata_eh_revalidate_timeouts[] = {
+static const unsigned int ata_eh_revalidate_timeouts[] = {
 	15000,	/* Some drives are slow to read log pages when waking-up */
 	15000,  /* combined time till here is enough even for media access */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
-static const unsigned long ata_eh_flush_timeouts[] = {
+static const unsigned int ata_eh_flush_timeouts[] = {
 	15000,	/* be generous with flush */
 	15000,  /* ditto */
 	30000,	/* and even more generous */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
-static const unsigned long ata_eh_other_timeouts[] = {
+static const unsigned int ata_eh_other_timeouts[] = {
 	 5000,	/* same rationale as identify timeout */
 	10000,	/* ditto */
 	/* but no merciful 30sec for other commands, it just isn't worth it */
-	ULONG_MAX,
+	UINT_MAX,
 };
 
 struct ata_eh_cmd_timeout_ent {
 	const u8		*commands;
-	const unsigned long	*timeouts;
+	const unsigned int	*timeouts;
 };
 
 /* The following table determines timeouts to use for EH internal
@@ -326,7 +326,7 @@ static int ata_lookup_timeout_table(u8 cmd)
  *	RETURNS:
  *	Determined timeout.
  */
-unsigned long ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd)
+unsigned int ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd)
 {
 	struct ata_eh_context *ehc = &dev->link->eh_context;
 	int ent = ata_lookup_timeout_table(cmd);
@@ -361,7 +361,7 @@ void ata_internal_cmd_timed_out(struct ata_device *dev, u8 cmd)
 		return;
 
 	idx = ehc->cmd_timeout_idx[dev->devno][ent];
-	if (ata_eh_cmd_timeout_table[ent].timeouts[idx + 1] != ULONG_MAX)
+	if (ata_eh_cmd_timeout_table[ent].timeouts[idx + 1] != UINT_MAX)
 		ehc->cmd_timeout_idx[dev->devno][ent]++;
 }
 
@@ -802,11 +802,11 @@ void ata_port_wait_eh(struct ata_port *ap)
 }
 EXPORT_SYMBOL_GPL(ata_port_wait_eh);
 
-static int ata_eh_nr_in_flight(struct ata_port *ap)
+static unsigned int ata_eh_nr_in_flight(struct ata_port *ap)
 {
 	struct ata_queued_cmd *qc;
 	unsigned int tag;
-	int nr = 0;
+	unsigned int nr = 0;
 
 	/* count only non-internal commands */
 	ata_qc_for_each(ap, qc, tag) {
@@ -821,7 +821,7 @@ void ata_eh_fastdrain_timerfn(struct timer_list *t)
 {
 	struct ata_port *ap = from_timer(ap, t, fastdrain_timer);
 	unsigned long flags;
-	int cnt;
+	unsigned int cnt;
 
 	spin_lock_irqsave(ap->lock, flags);
 
@@ -870,7 +870,7 @@ void ata_eh_fastdrain_timerfn(struct timer_list *t)
  */
 static void ata_eh_set_pending(struct ata_port *ap, int fastdrain)
 {
-	int cnt;
+	unsigned int cnt;
 
 	/* already scheduled? */
 	if (ap->pflags & ATA_PFLAG_EH_PENDING)
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c
index c38027887499..a7e9a75410a3 100644
--- a/drivers/ata/libata-transport.c
+++ b/drivers/ata/libata-transport.c
@@ -9,7 +9,7 @@
  * and various sysfs attributes to expose these topologies and management
  * interfaces to user-space.
  *
- * There are 3 objects defined in in this class:
+ * There are 3 objects defined in this class:
  * - ata_port
  * - ata_link
  * - ata_device
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 926a7f41303d..98bc8649c63f 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -52,11 +52,7 @@ extern u64 ata_tf_read_block(const struct ata_taskfile *tf,
 extern unsigned ata_exec_internal(struct ata_device *dev,
 				  struct ata_taskfile *tf, const u8 *cdb,
 				  int dma_dir, void *buf, unsigned int buflen,
-				  unsigned long timeout);
-extern unsigned ata_exec_internal_sg(struct ata_device *dev,
-				     struct ata_taskfile *tf, const u8 *cdb,
-				     int dma_dir, struct scatterlist *sg,
-				     unsigned int n_elem, unsigned long timeout);
+				  unsigned int timeout);
 extern int ata_wait_ready(struct ata_link *link, unsigned long deadline,
 			  int (*check_ready)(struct ata_link *link));
 extern int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
@@ -136,7 +132,7 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev);
 int __ata_scsi_queuecmd(struct scsi_cmnd *scmd, struct ata_device *dev);
 
 /* libata-eh.c */
-extern unsigned long ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd);
+extern unsigned int ata_internal_cmd_timeout(struct ata_device *dev, u8 cmd);
 extern void ata_internal_cmd_timed_out(struct ata_device *dev, u8 cmd);
 extern void ata_eh_acquire(struct ata_port *ap);
 extern void ata_eh_release(struct ata_port *ap);
diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c
index ade4c3eee230..f8706ee427d2 100644
--- a/drivers/ata/pata_acpi.c
+++ b/drivers/ata/pata_acpi.c
@@ -97,7 +97,7 @@ static unsigned long pacpi_discover_modes(struct ata_port *ap, struct ata_device
  *	this case the list of discovered valid modes obtained by ACPI probing
  */
 
-static unsigned long pacpi_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int pacpi_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	struct pata_acpi *acpi = adev->link->ap->private_data;
 	return mask & acpi->mask[adev->devno];
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index 1b90cda27246..76ad0e73fe2a 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -115,7 +115,7 @@ static int ali_c2_cable_detect(struct ata_port *ap)
  *	fix that later on. Also ensure we do not do UDMA on WDC drives
  */
 
-static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int ali_20_filter(struct ata_device *adev, unsigned int mask)
 {
 	char model_num[ATA_ID_PROD_LEN + 1];
 	/* No DMA on anything but a disk for now */
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 154748cfcc79..f216f9d7b9ec 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -264,8 +264,8 @@ static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  * cached during driver attach and are consulted to select transfer
  * mode.
  */
-static unsigned long nv_mode_filter(struct ata_device *dev,
-				    unsigned long xfer_mask)
+static unsigned int nv_mode_filter(struct ata_device *dev,
+				   unsigned int xfer_mask)
 {
 	static const unsigned int udma_mask_map[] =
 		{ ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
@@ -274,7 +274,7 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
 	char acpi_str[32] = "";
 	u32 saved_udma, udma;
 	const struct ata_acpi_gtm *gtm;
-	unsigned long bios_limit = 0, acpi_limit = 0, limit;
+	unsigned int bios_limit = 0, acpi_limit = 0, limit;
 
 	/* find out what BIOS configured */
 	udma = saved_udma = (unsigned long)ap->host->private_data;
@@ -310,10 +310,10 @@ static unsigned long nv_mode_filter(struct ata_device *dev,
 	   cable detection result */
 	limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
 
-	ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
-			"BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
-			xfer_mask, limit, xfer_mask & limit, bios_limit,
-			saved_udma, acpi_limit, acpi_str);
+	ata_port_dbg(ap,
+		     "nv_mode_filter: 0x%x&0x%x->0x%x, BIOS=0x%x (0x%x) ACPI=0x%x%s\n",
+		     xfer_mask, limit, xfer_mask & limit, bios_limit,
+		     saved_udma, acpi_limit, acpi_str);
 
 	return xfer_mask & limit;
 }
diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
index c99e8f0708b3..7e441fb304d3 100644
--- a/drivers/ata/pata_hpt366.c
+++ b/drivers/ata/pata_hpt366.c
@@ -194,7 +194,7 @@ static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt366_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
 		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index 156f304ef051..ce3c5eaa7e76 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -23,7 +23,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.25"
+#define DRV_VERSION	"0.6.30"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -278,7 +278,7 @@ static const char * const bad_ata100_5[] = {
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt370_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
 		if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
@@ -297,7 +297,7 @@ static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt370a_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA) {
 		if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
@@ -314,7 +314,7 @@ static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
  *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
  *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  */
-static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt372_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (ata_id_is_sata(adev->id))
 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
@@ -592,21 +592,19 @@ static struct ata_port_operations hpt374_fn1_port_ops = {
 
 /**
  *	hpt37x_clock_slot	-	Turn timing to PC clock entry
- *	@freq: Reported frequency timing
- *	@base: Base timing
+ *	@freq: Reported frequency in MHz
  *
- *	Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
+ *	Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
  *	and 3 for 66Mhz)
  */
 
-static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
+static int hpt37x_clock_slot(unsigned int freq)
 {
-	unsigned int f = (base * freq) / 192;	/* Mhz */
-	if (f < 40)
+	if (freq < 40)
 		return 0;	/* 33Mhz slot */
-	if (f < 45)
+	if (freq < 45)
 		return 1;	/* 40Mhz slot */
-	if (f < 55)
+	if (freq < 55)
 		return 2;	/* 50Mhz slot */
 	return 3;		/* 60Mhz slot */
 }
@@ -646,24 +644,57 @@ static int hpt37x_calibrate_dpll(struct pci_dev *dev)
 	return 0;
 }
 
-static u32 hpt374_read_freq(struct pci_dev *pdev)
+static int hpt37x_pci_clock(struct pci_dev *pdev, unsigned int base)
 {
-	u32 freq;
-	unsigned long io_base = pci_resource_start(pdev, 4);
+	unsigned int freq;
+	u32 fcnt;
 
-	if (PCI_FUNC(pdev->devfn) & 1) {
-		struct pci_dev *pdev_0;
+	/*
+	 * Some devices do not let this value be accessed via PCI space
+	 * according to the old driver. In addition we must use the value
+	 * from FN 0 on the HPT374.
+	 */
+	if (pdev->device == PCI_DEVICE_ID_TTI_HPT374 &&
+	    (PCI_FUNC(pdev->devfn) & 1)) {
+		struct pci_dev *pdev_fn0;
 
-		pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
-		/* Someone hot plugged the controller on us ? */
-		if (pdev_0 == NULL)
+		pdev_fn0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
+		/* Someone hot plugged the controller on us? */
+		if (!pdev_fn0)
 			return 0;
-		io_base = pci_resource_start(pdev_0, 4);
-		freq = inl(io_base + 0x90);
-		pci_dev_put(pdev_0);
-	} else
-		freq = inl(io_base + 0x90);
-	return freq;
+		fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90);
+		pci_dev_put(pdev_fn0);
+	} else	{
+		fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
+	}
+
+	if ((fcnt >> 12) != 0xABCDE) {
+		u32 total = 0;
+		int i;
+		u16 sr;
+
+		dev_warn(&pdev->dev, "BIOS clock data not set\n");
+
+		/* This is the process the HPT371 BIOS is reported to use */
+		for (i = 0; i < 128; i++) {
+			pci_read_config_word(pdev, 0x78, &sr);
+			total += sr & 0x1FF;
+			udelay(15);
+		}
+		fcnt = total / 128;
+	}
+	fcnt &= 0x1FF;
+
+	freq = (fcnt * base) / 192;	/* in MHz */
+
+	/* Clamp to bands */
+	if (freq < 40)
+		return 33;
+	if (freq < 45)
+		return 40;
+	if (freq < 55)
+		return 50;
+	return 66;
 }
 
 /**
@@ -770,7 +801,7 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	u8 rev = dev->revision;
 	u8 irqmask;
 	u8 mcr1;
-	u32 freq;
+	unsigned int freq; /* MHz */
 	int prefer_dpll = 1;
 
 	unsigned long iobase = pci_resource_start(dev, 4);
@@ -896,42 +927,16 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	if (chip_table == &hpt372a)
 		outb(0x0e, iobase + 0x9c);
 
-	/*
-	 * Some devices do not let this value be accessed via PCI space
-	 * according to the old driver. In addition we must use the value
-	 * from FN 0 on the HPT374.
-	 */
-
-	if (chip_table == &hpt374) {
-		freq = hpt374_read_freq(dev);
-		if (freq == 0)
-			return -ENODEV;
-	} else
-		freq = inl(iobase + 0x90);
-
-	if ((freq >> 12) != 0xABCDE) {
-		int i;
-		u16 sr;
-		u32 total = 0;
-
-		dev_warn(&dev->dev, "BIOS has not set timing clocks\n");
-
-		/* This is the process the HPT371 BIOS is reported to use */
-		for (i = 0; i < 128; i++) {
-			pci_read_config_word(dev, 0x78, &sr);
-			total += sr & 0x1FF;
-			udelay(15);
-		}
-		freq = total / 128;
-	}
-	freq &= 0x1FF;
+	freq = hpt37x_pci_clock(dev, chip_table->base);
+	if (!freq)
+		return -ENODEV;
 
 	/*
 	 *	Turn the frequency check into a band and then find a timing
 	 *	table to match it.
 	 */
 
-	clock_slot = hpt37x_clock_slot(freq, chip_table->base);
+	clock_slot = hpt37x_clock_slot(freq);
 	if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
 		/*
 		 *	We need to try PLL mode instead
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index 1f6afd8ee29b..617c95522f43 100644
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -24,7 +24,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt3x2n"
-#define DRV_VERSION	"0.3.18"
+#define DRV_VERSION	"0.3.19"
 
 enum {
 	PCI66		=	(1 << 1),
@@ -113,7 +113,7 @@ static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
  *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
  *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
  */
-static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int hpt372n_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (ata_id_is_sata(adev->id))
 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
@@ -403,17 +403,20 @@ static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
 	return 0;
 }
 
-static int hpt3x2n_pci_clock(struct pci_dev *pdev)
+static int hpt3x2n_pci_clock(struct pci_dev *pdev, unsigned int base)
 {
-	unsigned long freq;
+	unsigned int freq;
 	u32 fcnt;
-	unsigned long iobase = pci_resource_start(pdev, 4);
 
-	fcnt = inl(iobase + 0x90);	/* Not PCI readable for some chips */
+	/*
+	 * Some devices do not let this value be accessed via PCI space
+	 * according to the old driver.
+	 */
+	fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
 	if ((fcnt >> 12) != 0xABCDE) {
+		u32 total = 0;
 		int i;
 		u16 sr;
-		u32 total = 0;
 
 		dev_warn(&pdev->dev, "BIOS clock data not set\n");
 
@@ -427,7 +430,7 @@ static int hpt3x2n_pci_clock(struct pci_dev *pdev)
 	}
 	fcnt &= 0x1FF;
 
-	freq = (fcnt * 77) / 192;
+	freq = (fcnt * base) / 192;	/* in MHz */
 
 	/* Clamp to bands */
 	if (freq < 40)
@@ -559,7 +562,7 @@ static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 	 * 50 for UDMA100. Right now we always use 66
 	 */
 
-	pci_mhz = hpt3x2n_pci_clock(dev);
+	pci_mhz = hpt3x2n_pci_clock(dev, 77);
 
 	f_low = (pci_mhz * 48) / 66;	/* PCI Mhz for 66Mhz DPLL */
 	f_high = f_low + 2;		/* Tolerance */
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
index 42798402cf63..bfea2be2959a 100644
--- a/drivers/ata/pata_macio.c
+++ b/drivers/ata/pata_macio.c
@@ -1028,7 +1028,7 @@ static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
 		}
 		i++;
 	}
-	dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
+	dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",
 		pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
 }
 
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index 4fbb3eed8b0b..4191aa61c8e4 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -57,7 +57,7 @@ static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
-static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
+static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask);
 static int pdc2027x_cable_detect(struct ata_port *ap);
 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
 
@@ -251,7 +251,7 @@ static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
  *	Block UDMA on devices that cause trouble with this controller.
  */
 
-static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
 	struct ata_device *pair = ata_dev_pair(adev);
diff --git a/drivers/ata/pata_serverworks.c b/drivers/ata/pata_serverworks.c
index e410fe44177f..c0bc4af0d196 100644
--- a/drivers/ata/pata_serverworks.c
+++ b/drivers/ata/pata_serverworks.c
@@ -150,7 +150,7 @@ static u8 serverworks_is_csb(struct pci_dev *pdev)
  *	bug we hit.
  */
 
-static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int serverworks_osb4_filter(struct ata_device *adev, unsigned int mask)
 {
 	if (adev->class == ATA_DEV_ATA)
 		mask &= ~ATA_MASK_UDMA;
@@ -166,7 +166,7 @@ static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned l
  *	Check the blacklist and disable UDMA5 if matched
  */
 
-static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int serverworks_csb_filter(struct ata_device *adev, unsigned int mask)
 {
 	const char *p;
 	char model_num[ATA_ID_PROD_LEN + 1];
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index b5b764e18adf..92e4cf05de2c 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -525,7 +525,7 @@ static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
  *	Block UDMA6 on devices that do not support it.
  */
 
-static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
+static unsigned int sis_133_mode_filter(struct ata_device *adev, unsigned int mask)
 {
 	struct ata_port *ap = adev->link->ap;
 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
diff --git a/drivers/ata/pata_via.c b/drivers/ata/pata_via.c
index 215c02d4056a..34f00f389932 100644
--- a/drivers/ata/pata_via.c
+++ b/drivers/ata/pata_via.c
@@ -352,7 +352,7 @@ static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  *	one breed of Transcend SSD. Return the updated mask.
  */
 
-static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
+static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)
 {
 	struct ata_host *host = dev->link->ap->host;
 	const struct via_isa_bridge *config = host->private_data;
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c
index 3e726ee91fdc..324148686953 100644
--- a/drivers/atm/iphase.c
+++ b/drivers/atm/iphase.c
@@ -739,7 +739,7 @@ static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
         u32	t;
 	int	i;
 	/*
-	 * Read the first bit that was clocked with the falling edge of the
+	 * Read the first bit that was clocked with the falling edge of
 	 * the last command data clock
 	 */
 	NVRAM_CMD(IAREAD + addr);
diff --git a/drivers/base/base.h b/drivers/base/base.h
index ab71403d102f..b3a43a164dcd 100644
--- a/drivers/base/base.h
+++ b/drivers/base/base.h
@@ -160,6 +160,7 @@ extern int devres_release_all(struct device *dev);
 extern void device_block_probing(void);
 extern void device_unblock_probing(void);
 extern void deferred_probe_extend_timeout(void);
+extern void driver_deferred_probe_trigger(void);
 
 /* /sys/devices directory */
 extern struct kset *devices_kset;
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 7cd789c4985d..839f64485a55 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -54,6 +54,7 @@ static unsigned int defer_sync_state_count = 1;
 static DEFINE_MUTEX(fwnode_link_lock);
 static bool fw_devlink_is_permissive(void);
 static bool fw_devlink_drv_reg_done;
+static bool fw_devlink_best_effort;
 
 /**
  * fwnode_link_add - Create a link between two fwnode_handles.
@@ -965,6 +966,11 @@ static void device_links_missing_supplier(struct device *dev)
 	}
 }
 
+static bool dev_is_best_effort(struct device *dev)
+{
+	return fw_devlink_best_effort && dev->can_match;
+}
+
 /**
  * device_links_check_suppliers - Check presence of supplier drivers.
  * @dev: Consumer device.
@@ -984,7 +990,7 @@ static void device_links_missing_supplier(struct device *dev)
 int device_links_check_suppliers(struct device *dev)
 {
 	struct device_link *link;
-	int ret = 0;
+	int ret = 0, fwnode_ret = 0;
 	struct fwnode_handle *sup_fw;
 
 	/*
@@ -997,12 +1003,17 @@ int device_links_check_suppliers(struct device *dev)
 		sup_fw = list_first_entry(&dev->fwnode->suppliers,
 					  struct fwnode_link,
 					  c_hook)->supplier;
-		dev_err_probe(dev, -EPROBE_DEFER, "wait for supplier %pfwP\n",
-			      sup_fw);
-		mutex_unlock(&fwnode_link_lock);
-		return -EPROBE_DEFER;
+		if (!dev_is_best_effort(dev)) {
+			fwnode_ret = -EPROBE_DEFER;
+			dev_err_probe(dev, -EPROBE_DEFER,
+				    "wait for supplier %pfwP\n", sup_fw);
+		} else {
+			fwnode_ret = -EAGAIN;
+		}
 	}
 	mutex_unlock(&fwnode_link_lock);
+	if (fwnode_ret == -EPROBE_DEFER)
+		return fwnode_ret;
 
 	device_links_write_lock();
 
@@ -1012,6 +1023,14 @@ int device_links_check_suppliers(struct device *dev)
 
 		if (link->status != DL_STATE_AVAILABLE &&
 		    !(link->flags & DL_FLAG_SYNC_STATE_ONLY)) {
+
+			if (dev_is_best_effort(dev) &&
+			    link->flags & DL_FLAG_INFERRED &&
+			    !link->supplier->can_match) {
+				ret = -EAGAIN;
+				continue;
+			}
+
 			device_links_missing_supplier(dev);
 			dev_err_probe(dev, -EPROBE_DEFER,
 				      "supplier %s not ready\n",
@@ -1024,7 +1043,8 @@ int device_links_check_suppliers(struct device *dev)
 	dev->links.status = DL_DEV_PROBING;
 
 	device_links_write_unlock();
-	return ret;
+
+	return ret ? ret : fwnode_ret;
 }
 
 /**
@@ -1289,6 +1309,18 @@ void device_links_driver_bound(struct device *dev)
 			 * save to drop the managed link completely.
 			 */
 			device_link_drop_managed(link);
+		} else if (dev_is_best_effort(dev) &&
+			   link->flags & DL_FLAG_INFERRED &&
+			   link->status != DL_STATE_CONSUMER_PROBE &&
+			   !link->supplier->can_match) {
+			/*
+			 * When dev_is_best_effort() is true, we ignore device
+			 * links to suppliers that don't have a driver.  If the
+			 * consumer device still managed to probe, there's no
+			 * point in maintaining a device link in a weird state
+			 * (consumer probed before supplier). So delete it.
+			 */
+			device_link_drop_managed(link);
 		} else {
 			WARN_ON(link->status != DL_STATE_CONSUMER_PROBE);
 			WRITE_ONCE(link->status, DL_STATE_ACTIVE);
@@ -1581,7 +1613,7 @@ static int __init fw_devlink_setup(char *arg)
 }
 early_param("fw_devlink", fw_devlink_setup);
 
-static bool fw_devlink_strict;
+static bool fw_devlink_strict = true;
 static int __init fw_devlink_strict_setup(char *arg)
 {
 	return strtobool(arg, &fw_devlink_strict);
@@ -1655,6 +1687,62 @@ void fw_devlink_drivers_done(void)
 	device_links_write_unlock();
 }
 
+/**
+ * wait_for_init_devices_probe - Try to probe any device needed for init
+ *
+ * Some devices might need to be probed and bound successfully before the kernel
+ * boot sequence can finish and move on to init/userspace. For example, a
+ * network interface might need to be bound to be able to mount a NFS rootfs.
+ *
+ * With fw_devlink=on by default, some of these devices might be blocked from
+ * probing because they are waiting on a optional supplier that doesn't have a
+ * driver. While fw_devlink will eventually identify such devices and unblock
+ * the probing automatically, it might be too late by the time it unblocks the
+ * probing of devices. For example, the IP4 autoconfig might timeout before
+ * fw_devlink unblocks probing of the network interface.
+ *
+ * This function is available to temporarily try and probe all devices that have
+ * a driver even if some of their suppliers haven't been added or don't have
+ * drivers.
+ *
+ * The drivers can then decide which of the suppliers are optional vs mandatory
+ * and probe the device if possible. By the time this function returns, all such
+ * "best effort" probes are guaranteed to be completed. If a device successfully
+ * probes in this mode, we delete all fw_devlink discovered dependencies of that
+ * device where the supplier hasn't yet probed successfully because they have to
+ * be optional dependencies.
+ *
+ * Any devices that didn't successfully probe go back to being treated as if
+ * this function was never called.
+ *
+ * This also means that some devices that aren't needed for init and could have
+ * waited for their optional supplier to probe (when the supplier's module is
+ * loaded later on) would end up probing prematurely with limited functionality.
+ * So call this function only when boot would fail without it.
+ */
+void __init wait_for_init_devices_probe(void)
+{
+	if (!fw_devlink_flags || fw_devlink_is_permissive())
+		return;
+
+	/*
+	 * Wait for all ongoing probes to finish so that the "best effort" is
+	 * only applied to devices that can't probe otherwise.
+	 */
+	wait_for_device_probe();
+
+	pr_info("Trying to probe devices needed for running init ...\n");
+	fw_devlink_best_effort = true;
+	driver_deferred_probe_trigger();
+
+	/*
+	 * Wait for all "best effort" probes to finish before going back to
+	 * normal enforcement.
+	 */
+	wait_for_device_probe();
+	fw_devlink_best_effort = false;
+}
+
 static void fw_devlink_unblock_consumers(struct device *dev)
 {
 	struct device_link *link;
@@ -3832,6 +3920,26 @@ struct device *device_find_child_by_name(struct device *parent,
 }
 EXPORT_SYMBOL_GPL(device_find_child_by_name);
 
+static int match_any(struct device *dev, void *unused)
+{
+	return 1;
+}
+
+/**
+ * device_find_any_child - device iterator for locating a child device, if any.
+ * @parent: parent struct device
+ *
+ * This is similar to the device_find_child() function above, but it
+ * returns a reference to a child device, if any.
+ *
+ * NOTE: you will need to drop the reference with put_device() after use.
+ */
+struct device *device_find_any_child(struct device *parent)
+{
+	return device_find_child(parent, NULL, match_any);
+}
+EXPORT_SYMBOL_GPL(device_find_any_child);
+
 int __init devices_init(void)
 {
 	devices_kset = kset_create_and_add("devices", &device_uevent_ops, NULL);
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 11b0fb6414d3..e600dd2afc35 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -172,7 +172,7 @@ static bool driver_deferred_probe_enable;
  * changes in the midst of a probe, then deferred processing should be triggered
  * again.
  */
-static void driver_deferred_probe_trigger(void)
+void driver_deferred_probe_trigger(void)
 {
 	if (!driver_deferred_probe_enable)
 		return;
@@ -256,7 +256,12 @@ static int deferred_devs_show(struct seq_file *s, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(deferred_devs);
 
+#ifdef CONFIG_MODULES
+int driver_deferred_probe_timeout = 10;
+#else
 int driver_deferred_probe_timeout;
+#endif
+
 EXPORT_SYMBOL_GPL(driver_deferred_probe_timeout);
 
 static int __init deferred_probe_timeout_setup(char *str)
@@ -269,42 +274,12 @@ static int __init deferred_probe_timeout_setup(char *str)
 }
 __setup("deferred_probe_timeout=", deferred_probe_timeout_setup);
 
-/**
- * driver_deferred_probe_check_state() - Check deferred probe state
- * @dev: device to check
- *
- * Return:
- * * -ENODEV if initcalls have completed and modules are disabled.
- * * -ETIMEDOUT if the deferred probe timeout was set and has expired
- *   and modules are enabled.
- * * -EPROBE_DEFER in other cases.
- *
- * Drivers or subsystems can opt-in to calling this function instead of directly
- * returning -EPROBE_DEFER.
- */
-int driver_deferred_probe_check_state(struct device *dev)
-{
-	if (!IS_ENABLED(CONFIG_MODULES) && initcalls_done) {
-		dev_warn(dev, "ignoring dependency for device, assuming no driver\n");
-		return -ENODEV;
-	}
-
-	if (!driver_deferred_probe_timeout && initcalls_done) {
-		dev_warn(dev, "deferred probe timeout, ignoring dependency\n");
-		return -ETIMEDOUT;
-	}
-
-	return -EPROBE_DEFER;
-}
-EXPORT_SYMBOL_GPL(driver_deferred_probe_check_state);
-
 static void deferred_probe_timeout_work_func(struct work_struct *work)
 {
 	struct device_private *p;
 
 	fw_devlink_drivers_done();
 
-	driver_deferred_probe_timeout = 0;
 	driver_deferred_probe_trigger();
 	flush_work(&deferred_probe_work);
 
@@ -580,7 +555,7 @@ static int really_probe(struct device *dev, struct device_driver *drv)
 {
 	bool test_remove = IS_ENABLED(CONFIG_DEBUG_TEST_DRIVER_REMOVE) &&
 			   !drv->suppress_bind_attrs;
-	int ret;
+	int ret, link_ret;
 
 	if (defer_all_probes) {
 		/*
@@ -592,9 +567,9 @@ static int really_probe(struct device *dev, struct device_driver *drv)
 		return -EPROBE_DEFER;
 	}
 
-	ret = device_links_check_suppliers(dev);
-	if (ret)
-		return ret;
+	link_ret = device_links_check_suppliers(dev);
+	if (link_ret == -EPROBE_DEFER)
+		return link_ret;
 
 	pr_debug("bus: '%s': %s: probing driver %s with device %s\n",
 		 drv->bus->name, __func__, drv->name, dev_name(dev));
@@ -633,6 +608,15 @@ static int really_probe(struct device *dev, struct device_driver *drv)
 
 	ret = call_driver_probe(dev, drv);
 	if (ret) {
+		/*
+		 * If fw_devlink_best_effort is active (denoted by -EAGAIN), the
+		 * device might actually probe properly once some of its missing
+		 * suppliers have probed. So, treat this as if the driver
+		 * returned -EPROBE_DEFER.
+		 */
+		if (link_ret == -EAGAIN)
+			ret = -EPROBE_DEFER;
+
 		/*
 		 * Return probe errors as positive values so that the callers
 		 * can distinguish them from other errors.
diff --git a/drivers/base/devcoredump.c b/drivers/base/devcoredump.c
index f4d794d6bb85..8535f0bd5dfb 100644
--- a/drivers/base/devcoredump.c
+++ b/drivers/base/devcoredump.c
@@ -173,15 +173,13 @@ static void devcd_freev(void *data)
  * @dev: the struct device for the crashed device
  * @data: vmalloc data containing the device coredump
  * @datalen: length of the data
- * @gfp: allocation flags
  *
  * This function takes ownership of the vmalloc'ed data and will free
  * it when it is no longer used. See dev_coredumpm() for more information.
  */
-void dev_coredumpv(struct device *dev, void *data, size_t datalen,
-		   gfp_t gfp)
+void dev_coredumpv(struct device *dev, void *data, size_t datalen)
 {
-	dev_coredumpm(dev, NULL, data, datalen, gfp, devcd_readv, devcd_freev);
+	dev_coredumpm(dev, NULL, data, datalen, devcd_readv, devcd_freev);
 }
 EXPORT_SYMBOL_GPL(dev_coredumpv);
 
@@ -236,7 +234,6 @@ static ssize_t devcd_read_from_sgtable(char *buffer, loff_t offset,
  * @owner: the module that contains the read/free functions, use %THIS_MODULE
  * @data: data cookie for the @read/@free functions
  * @datalen: length of the data
- * @gfp: allocation flags
  * @read: function to read from the given buffer
  * @free: function to free the given buffer
  *
@@ -246,7 +243,7 @@ static ssize_t devcd_read_from_sgtable(char *buffer, loff_t offset,
  * function will be called to free the data.
  */
 void dev_coredumpm(struct device *dev, struct module *owner,
-		   void *data, size_t datalen, gfp_t gfp,
+		   void *data, size_t datalen,
 		   ssize_t (*read)(char *buffer, loff_t offset, size_t count,
 				   void *data, size_t datalen),
 		   void (*free)(void *data))
@@ -268,7 +265,7 @@ void dev_coredumpm(struct device *dev, struct module *owner,
 	if (!try_module_get(owner))
 		goto free;
 
-	devcd = kzalloc(sizeof(*devcd), gfp);
+	devcd = kzalloc(sizeof(*devcd), GFP_KERNEL);
 	if (!devcd)
 		goto put_module;
 
@@ -318,7 +315,6 @@ EXPORT_SYMBOL_GPL(dev_coredumpm);
  * @dev: the struct device for the crashed device
  * @table: the dump data
  * @datalen: length of the data
- * @gfp: allocation flags
  *
  * Creates a new device coredump for the given device. If a previous one hasn't
  * been read yet, the new coredump is discarded. The data lifetime is determined
@@ -326,9 +322,9 @@ EXPORT_SYMBOL_GPL(dev_coredumpm);
  * it will free the data.
  */
 void dev_coredumpsg(struct device *dev, struct scatterlist *table,
-		    size_t datalen, gfp_t gfp)
+		    size_t datalen)
 {
-	dev_coredumpm(dev, NULL, table, datalen, gfp, devcd_read_from_sgtable,
+	dev_coredumpm(dev, NULL, table, datalen, devcd_read_from_sgtable,
 		      devcd_free_sgtable);
 }
 EXPORT_SYMBOL_GPL(dev_coredumpsg);
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 084d67fd55cc..bc60c9cd3230 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -558,7 +558,7 @@ static ssize_t hard_offline_page_store(struct device *dev,
 	if (kstrtoull(buf, 0, &pfn) < 0)
 		return -EINVAL;
 	pfn >>= PAGE_SHIFT;
-	ret = memory_failure(pfn, 0);
+	ret = memory_failure(pfn, MF_SW_SIMULATED);
 	if (ret == -EOPNOTSUPP)
 		ret = 0;
 	return ret ? ret : count;
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index 739e52cd4aba..3e86772d5fac 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -2730,7 +2730,7 @@ static int __genpd_dev_pm_attach(struct device *dev, struct device *base_dev,
 		mutex_unlock(&gpd_list_lock);
 		dev_dbg(dev, "%s() failed to find PM domain: %ld\n",
 			__func__, PTR_ERR(pd));
-		return driver_deferred_probe_check_state(base_dev);
+		return -ENODEV;
 	}
 
 	dev_dbg(dev, "adding to PM domain %s\n", pd->name);
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index d0f5bc827978..2eaffd3224c9 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -531,7 +531,7 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
  * @enable: flag if changes should not be written to the cache
  *
  * When a register map is marked with the cache bypass option, writes
- * to the register map API will only update the hardware and not the
+ * to the register map API will only update the hardware and not
  * the cache directly.  This is useful when syncing the cache back to
  * the hardware.
  */
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 400c7412a7dc..a6db605707b0 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -252,6 +252,7 @@ static void regmap_irq_enable(struct irq_data *data)
 	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 	struct regmap *map = d->map;
 	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
+	unsigned int reg = irq_data->reg_offset / map->reg_stride;
 	unsigned int mask, type;
 
 	type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
@@ -268,14 +269,14 @@ static void regmap_irq_enable(struct irq_data *data)
 	 * at the corresponding offset in regmap_irq_set_type().
 	 */
 	if (d->chip->type_in_mask && type)
-		mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
+		mask = d->type_buf[reg] & irq_data->mask;
 	else
 		mask = irq_data->mask;
 
 	if (d->chip->clear_on_unmask)
 		d->clear_status = true;
 
-	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
+	d->mask_buf[reg] &= ~mask;
 }
 
 static void regmap_irq_disable(struct irq_data *data)
@@ -386,6 +387,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 		subreg = &chip->sub_reg_offsets[b];
 		for (i = 0; i < subreg->num_regs; i++) {
 			unsigned int offset = subreg->offset[i];
+			unsigned int index = offset / map->reg_stride;
 
 			if (chip->not_fixed_stride)
 				ret = regmap_read(map,
@@ -394,7 +396,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 			else
 				ret = regmap_read(map,
 						chip->status_base + offset,
-						&data->status_buf[offset]);
+						&data->status_buf[index]);
 
 			if (ret)
 				break;
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 2221d9863831..4cf59e10d01b 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1880,8 +1880,7 @@ static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg,
  */
 bool regmap_can_raw_write(struct regmap *map)
 {
-	return map->bus && map->bus->write && map->format.format_val &&
-		map->format.format_reg;
+	return map->write && map->format.format_val && map->format.format_reg;
 }
 EXPORT_SYMBOL_GPL(regmap_can_raw_write);
 
@@ -2155,10 +2154,9 @@ int regmap_noinc_write(struct regmap *map, unsigned int reg,
 	size_t write_len;
 	int ret;
 
-	if (!map->bus)
-		return -EINVAL;
-	if (!map->bus->write)
+	if (!map->write)
 		return -ENOTSUPP;
+
 	if (val_len % map->format.val_bytes)
 		return -EINVAL;
 	if (!IS_ALIGNED(reg, map->reg_stride))
@@ -2220,6 +2218,28 @@ int regmap_field_update_bits_base(struct regmap_field *field,
 }
 EXPORT_SYMBOL_GPL(regmap_field_update_bits_base);
 
+/**
+ * regmap_field_test_bits() - Check if all specified bits are set in a
+ *                            register field.
+ *
+ * @field: Register field to operate on
+ * @bits: Bits to test
+ *
+ * Returns -1 if the underlying regmap_field_read() fails, 0 if at least one of the
+ * tested bits is not set and 1 if all tested bits are set.
+ */
+int regmap_field_test_bits(struct regmap_field *field, unsigned int bits)
+{
+	unsigned int val, ret;
+
+	ret = regmap_field_read(field, &val);
+	if (ret)
+		return ret;
+
+	return (val & bits) == bits;
+}
+EXPORT_SYMBOL_GPL(regmap_field_test_bits);
+
 /**
  * regmap_fields_update_bits_base() - Perform a read/modify/write cycle a
  *                                    register field with port ID
@@ -2278,7 +2298,7 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val,
 	 * Some devices don't support bulk write, for them we have a series of
 	 * single write operations.
 	 */
-	if (!map->bus || !map->format.parse_inplace) {
+	if (!map->write || !map->format.parse_inplace) {
 		map->lock(map->lock_arg);
 		for (i = 0; i < val_count; i++) {
 			unsigned int ival;
@@ -2904,6 +2924,9 @@ int regmap_noinc_read(struct regmap *map, unsigned int reg,
 	size_t read_len;
 	int ret;
 
+	if (!map->read)
+		return -ENOTSUPP;
+
 	if (val_len % map->format.val_bytes)
 		return -EINVAL;
 	if (!IS_ALIGNED(reg, map->reg_stride))
@@ -3017,7 +3040,7 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val,
 	if (val_count == 0)
 		return -EINVAL;
 
-	if (map->format.parse_inplace && (vol || map->cache_type == REGCACHE_NONE)) {
+	if (map->read && map->format.parse_inplace && (vol || map->cache_type == REGCACHE_NONE)) {
 		ret = regmap_raw_read(map, reg, val, val_bytes * val_count);
 		if (ret != 0)
 			return ret;
diff --git a/drivers/block/drbd/drbd_bitmap.c b/drivers/block/drbd/drbd_bitmap.c
index 9e060e49b3f8..bd2133ef6e0a 100644
--- a/drivers/block/drbd/drbd_bitmap.c
+++ b/drivers/block/drbd/drbd_bitmap.c
@@ -974,25 +974,58 @@ static void drbd_bm_endio(struct bio *bio)
 	}
 }
 
+/* For the layout, see comment above drbd_md_set_sector_offsets(). */
+static inline sector_t drbd_md_last_bitmap_sector(struct drbd_backing_dev *bdev)
+{
+	switch (bdev->md.meta_dev_idx) {
+	case DRBD_MD_INDEX_INTERNAL:
+	case DRBD_MD_INDEX_FLEX_INT:
+		return bdev->md.md_offset + bdev->md.al_offset -1;
+	case DRBD_MD_INDEX_FLEX_EXT:
+	default:
+		return bdev->md.md_offset + bdev->md.md_size_sect -1;
+	}
+}
+
 static void bm_page_io_async(struct drbd_bm_aio_ctx *ctx, int page_nr) __must_hold(local)
 {
 	struct drbd_device *device = ctx->device;
 	unsigned int op = (ctx->flags & BM_AIO_READ) ? REQ_OP_READ : REQ_OP_WRITE;
-	struct bio *bio = bio_alloc_bioset(device->ldev->md_bdev, 1, op,
-					   GFP_NOIO, &drbd_md_io_bio_set);
 	struct drbd_bitmap *b = device->bitmap;
+	struct bio *bio;
 	struct page *page;
+	sector_t last_bm_sect;
+	sector_t first_bm_sect;
+	sector_t on_disk_sector;
 	unsigned int len;
 
-	sector_t on_disk_sector =
-		device->ldev->md.md_offset + device->ldev->md.bm_offset;
-	on_disk_sector += ((sector_t)page_nr) << (PAGE_SHIFT-9);
+	first_bm_sect = device->ldev->md.md_offset + device->ldev->md.bm_offset;
+	on_disk_sector = first_bm_sect + (((sector_t)page_nr) << (PAGE_SHIFT-SECTOR_SHIFT));
 
 	/* this might happen with very small
 	 * flexible external meta data device,
 	 * or with PAGE_SIZE > 4k */
-	len = min_t(unsigned int, PAGE_SIZE,
-		(drbd_md_last_sector(device->ldev) - on_disk_sector + 1)<<9);
+	last_bm_sect = drbd_md_last_bitmap_sector(device->ldev);
+	if (first_bm_sect <= on_disk_sector && last_bm_sect >= on_disk_sector) {
+		sector_t len_sect = last_bm_sect - on_disk_sector + 1;
+		if (len_sect < PAGE_SIZE/SECTOR_SIZE)
+			len = (unsigned int)len_sect*SECTOR_SIZE;
+		else
+			len = PAGE_SIZE;
+	} else {
+		if (__ratelimit(&drbd_ratelimit_state)) {
+			drbd_err(device, "Invalid offset during on-disk bitmap access: "
+				 "page idx %u, sector %llu\n", page_nr, on_disk_sector);
+		}
+		ctx->error = -EIO;
+		bm_set_page_io_err(b->bm_pages[page_nr]);
+		if (atomic_dec_and_test(&ctx->in_flight)) {
+			ctx->done = 1;
+			wake_up(&device->misc_wait);
+			kref_put(&ctx->kref, &drbd_bm_aio_ctx_destroy);
+		}
+		return;
+	}
 
 	/* serialize IO on this page */
 	bm_page_lock_io(device, page_nr);
@@ -1007,6 +1040,8 @@ static void bm_page_io_async(struct drbd_bm_aio_ctx *ctx, int page_nr) __must_ho
 		bm_store_page_idx(page, page_nr);
 	} else
 		page = b->bm_pages[page_nr];
+	bio = bio_alloc_bioset(device->ldev->md_bdev, 1, op, GFP_NOIO,
+			&drbd_md_io_bio_set);
 	bio->bi_iter.bi_sector = on_disk_sector;
 	/* bio_add_page of a single page to an empty bio will always succeed,
 	 * according to api.  Do we want to assert that? */
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index a88ce4426400..33f04ef78984 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -2114,9 +2114,11 @@ static void blkfront_closing(struct blkfront_info *info)
 		return;
 
 	/* No more blkif_request(). */
-	blk_mq_stop_hw_queues(info->rq);
-	blk_mark_disk_dead(info->gd);
-	set_capacity(info->gd, 0);
+	if (info->rq && info->gd) {
+		blk_mq_stop_hw_queues(info->rq);
+		blk_mark_disk_dead(info->gd);
+		set_capacity(info->gd, 0);
+	}
 
 	for_each_rinfo(info, rinfo, i) {
 		/* No more gnttab callback work. */
@@ -2457,16 +2459,19 @@ static int blkfront_remove(struct xenbus_device *xbdev)
 
 	dev_dbg(&xbdev->dev, "%s removed", xbdev->nodename);
 
-	del_gendisk(info->gd);
+	if (info->gd)
+		del_gendisk(info->gd);
 
 	mutex_lock(&blkfront_mutex);
 	list_del(&info->info_list);
 	mutex_unlock(&blkfront_mutex);
 
 	blkif_free(info, 0);
-	xlbd_release_minors(info->gd->first_minor, info->gd->minors);
-	blk_cleanup_disk(info->gd);
-	blk_mq_free_tag_set(&info->tag_set);
+	if (info->gd) {
+		xlbd_release_minors(info->gd->first_minor, info->gd->minors);
+		blk_cleanup_disk(info->gd);
+		blk_mq_free_tag_set(&info->tag_set);
+	}
 
 	kfree(info);
 	return 0;
diff --git a/drivers/block/zram/zcomp.c b/drivers/block/zram/zcomp.c
index 052aa3f65514..398eb9e24eff 100644
--- a/drivers/block/zram/zcomp.c
+++ b/drivers/block/zram/zcomp.c
@@ -63,12 +63,6 @@ static int zcomp_strm_init(struct zcomp_strm *zstrm, struct zcomp *comp)
 
 bool zcomp_available_algorithm(const char *comp)
 {
-	int i;
-
-	i = sysfs_match_string(backends, comp);
-	if (i >= 0)
-		return true;
-
 	/*
 	 * Crypto does not ignore a trailing new line symbol,
 	 * so make sure you don't supply a string containing
diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
index 76fbb046bdbe..3006e2a0f37e 100644
--- a/drivers/bluetooth/btbcm.c
+++ b/drivers/bluetooth/btbcm.c
@@ -403,6 +403,13 @@ static int btbcm_read_info(struct hci_dev *hdev)
 	bt_dev_info(hdev, "BCM: chip id %u", skb->data[1]);
 	kfree_skb(skb);
 
+	return 0;
+}
+
+static int btbcm_print_controller_features(struct hci_dev *hdev)
+{
+	struct sk_buff *skb;
+
 	/* Read Controller Features */
 	skb = btbcm_read_controller_features(hdev);
 	if (IS_ERR(skb))
@@ -454,6 +461,8 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = {
 	{ 0x6606, "BCM4345C5"	},	/* 003.006.006 */
 	{ 0x230f, "BCM4356A2"	},	/* 001.003.015 */
 	{ 0x220e, "BCM20702A1"  },	/* 001.002.014 */
+	{ 0x420d, "BCM4349B1"	},	/* 002.002.013 */
+	{ 0x420e, "BCM4349B1"	},	/* 002.002.014 */
 	{ 0x4217, "BCM4329B1"   },	/* 002.002.023 */
 	{ 0x6106, "BCM4359C0"	},	/* 003.001.006 */
 	{ 0x4106, "BCM4335A0"	},	/* 002.001.006 */
@@ -514,7 +523,7 @@ static const char *btbcm_get_board_name(struct device *dev)
 #endif
 }
 
-int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done)
+int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode)
 {
 	u16 subver, rev, pid, vid;
 	struct sk_buff *skb;
@@ -551,9 +560,16 @@ int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done)
 		if (err)
 			return err;
 	}
-	err = btbcm_print_local_name(hdev);
-	if (err)
-		return err;
+
+	if (!use_autobaud_mode) {
+		err = btbcm_print_controller_features(hdev);
+		if (err)
+			return err;
+
+		err = btbcm_print_local_name(hdev);
+		if (err)
+			return err;
+	}
 
 	bcm_subver_table = (hdev->bus == HCI_USB) ? bcm_usb_subver_table :
 						    bcm_uart_subver_table;
@@ -636,13 +652,13 @@ int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done)
 }
 EXPORT_SYMBOL_GPL(btbcm_initialize);
 
-int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done)
+int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode)
 {
 	int err;
 
 	/* Re-initialize if necessary */
 	if (*fw_load_done) {
-		err = btbcm_initialize(hdev, fw_load_done);
+		err = btbcm_initialize(hdev, fw_load_done, use_autobaud_mode);
 		if (err)
 			return err;
 	}
@@ -658,15 +674,16 @@ EXPORT_SYMBOL_GPL(btbcm_finalize);
 int btbcm_setup_patchram(struct hci_dev *hdev)
 {
 	bool fw_load_done = false;
+	bool use_autobaud_mode = false;
 	int err;
 
 	/* Initialize */
-	err = btbcm_initialize(hdev, &fw_load_done);
+	err = btbcm_initialize(hdev, &fw_load_done, use_autobaud_mode);
 	if (err)
 		return err;
 
 	/* Re-initialize after loading Patch */
-	return btbcm_finalize(hdev, &fw_load_done);
+	return btbcm_finalize(hdev, &fw_load_done, use_autobaud_mode);
 }
 EXPORT_SYMBOL_GPL(btbcm_setup_patchram);
 
diff --git a/drivers/bluetooth/btbcm.h b/drivers/bluetooth/btbcm.h
index 8bf01565fdfc..b4cb24231a20 100644
--- a/drivers/bluetooth/btbcm.h
+++ b/drivers/bluetooth/btbcm.h
@@ -62,8 +62,8 @@ int btbcm_write_pcm_int_params(struct hci_dev *hdev,
 int btbcm_setup_patchram(struct hci_dev *hdev);
 int btbcm_setup_apple(struct hci_dev *hdev);
 
-int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done);
-int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done);
+int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode);
+int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode);
 
 #else
 
@@ -104,12 +104,12 @@ static inline int btbcm_setup_apple(struct hci_dev *hdev)
 	return 0;
 }
 
-static inline int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done)
+static inline int btbcm_initialize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode)
 {
 	return 0;
 }
 
-static inline int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done)
+static inline int btbcm_finalize(struct hci_dev *hdev, bool *fw_load_done, bool use_autobaud_mode)
 {
 	return 0;
 }
diff --git a/drivers/bluetooth/btmrvl_debugfs.c b/drivers/bluetooth/btmrvl_debugfs.c
index db35b917aecf..32329a2e526f 100644
--- a/drivers/bluetooth/btmrvl_debugfs.c
+++ b/drivers/bluetooth/btmrvl_debugfs.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Bluetooth driver: debugfs related functions
  *
  * Copyright (C) 2009, Marvell International Ltd.
- *
- * This software file (the "File") is distributed by Marvell International
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
- * (the "License").  You may use, redistribute and/or modify this File in
- * accordance with the terms and conditions of the License, a copy of which
- * is available by writing to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
- * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
- *
- *
- * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
- * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
- * this warranty disclaimer.
  **/
 
 #include <linux/debugfs.h>
diff --git a/drivers/bluetooth/btmrvl_drv.h b/drivers/bluetooth/btmrvl_drv.h
index fb7729779166..d7df05c56b28 100644
--- a/drivers/bluetooth/btmrvl_drv.h
+++ b/drivers/bluetooth/btmrvl_drv.h
@@ -1,22 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Marvell Bluetooth driver: global definitions & declarations
  *
  * Copyright (C) 2009, Marvell International Ltd.
- *
- * This software file (the "File") is distributed by Marvell International
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
- * (the "License").  You may use, redistribute and/or modify this File in
- * accordance with the terms and conditions of the License, a copy of which
- * is available by writing to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
- * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
- *
- *
- * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
- * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
- * this warranty disclaimer.
- *
  */
 
 #include <linux/kthread.h>
diff --git a/drivers/bluetooth/btmrvl_main.c b/drivers/bluetooth/btmrvl_main.c
index 181338f60530..9658b33c824a 100644
--- a/drivers/bluetooth/btmrvl_main.c
+++ b/drivers/bluetooth/btmrvl_main.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell Bluetooth driver
  *
  * Copyright (C) 2009, Marvell International Ltd.
- *
- * This software file (the "File") is distributed by Marvell International
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
- * (the "License").  You may use, redistribute and/or modify this File in
- * accordance with the terms and conditions of the License, a copy of which
- * is available by writing to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
- * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
- *
- *
- * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
- * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
- * this warranty disclaimer.
  **/
 
 #include <linux/module.h>
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index b8ef66f89fc1..ab1b93b27ff1 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Marvell BT-over-SDIO driver: SDIO interface related functions.
  *
  * Copyright (C) 2009, Marvell International Ltd.
- *
- * This software file (the "File") is distributed by Marvell International
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
- * (the "License").  You may use, redistribute and/or modify this File in
- * accordance with the terms and conditions of the License, a copy of which
- * is available by writing to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
- * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
- *
- *
- * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
- * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
- * this warranty disclaimer.
  **/
 
 #include <linux/firmware.h>
@@ -1515,7 +1502,7 @@ static void btmrvl_sdio_coredump(struct device *dev)
 	/* fw_dump_data will be free in device coredump release function
 	 * after 5 min
 	 */
-	dev_coredumpv(&card->func->dev, fw_dump_data, fw_dump_len, GFP_KERNEL);
+	dev_coredumpv(&card->func->dev, fw_dump_data, fw_dump_len);
 	BT_INFO("== btmrvl firmware dump to /sys/class/devcoredump end");
 }
 
diff --git a/drivers/bluetooth/btmrvl_sdio.h b/drivers/bluetooth/btmrvl_sdio.h
index 3a522d23ee6e..72dd3b7d82aa 100644
--- a/drivers/bluetooth/btmrvl_sdio.h
+++ b/drivers/bluetooth/btmrvl_sdio.h
@@ -1,22 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /**
  * Marvell BT-over-SDIO driver: SDIO interface related definitions
  *
  * Copyright (C) 2009, Marvell International Ltd.
- *
- * This software file (the "File") is distributed by Marvell International
- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
- * (the "License").  You may use, redistribute and/or modify this File in
- * accordance with the terms and conditions of the License, a copy of which
- * is available by writing to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
- * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
- *
- *
- * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
- * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
- * this warranty disclaimer.
- *
  **/
 
 #define SDIO_HEADER_LEN			4
diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
index e25fcd49db70..fb1a67189412 100644
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
@@ -477,6 +477,9 @@ static const struct usb_device_id blacklist_table[] = {
 	{ USB_DEVICE(0x0489, 0xe0d9), .driver_info = BTUSB_MEDIATEK |
 						     BTUSB_WIDEBAND_SPEECH |
 						     BTUSB_VALID_LE_STATES },
+	{ USB_DEVICE(0x13d3, 0x3568), .driver_info = BTUSB_MEDIATEK |
+						     BTUSB_WIDEBAND_SPEECH |
+						     BTUSB_VALID_LE_STATES },
 
 	/* Additional Realtek 8723AE Bluetooth devices */
 	{ USB_DEVICE(0x0930, 0x021d), .driver_info = BTUSB_REALTEK },
diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
index 785f445dd60d..6f834ff1b44b 100644
--- a/drivers/bluetooth/hci_bcm.c
+++ b/drivers/bluetooth/hci_bcm.c
@@ -99,6 +99,7 @@ struct bcm_device_data {
  * @no_early_set_baudrate: don't set_baudrate before setup()
  * @drive_rts_on_open: drive RTS signal on ->open() when platform requires it
  * @pcm_int_params: keep the initial PCM configuration
+ * @use_autobaud_mode: start Bluetooth device in autobaud mode
  */
 struct bcm_device {
 	/* Must be the first member, hci_serdev.c expects this. */
@@ -136,6 +137,7 @@ struct bcm_device {
 #endif
 	bool			no_early_set_baudrate;
 	bool			drive_rts_on_open;
+	bool			use_autobaud_mode;
 	u8			pcm_int_params[5];
 };
 
@@ -472,7 +474,9 @@ static int bcm_open(struct hci_uart *hu)
 
 out:
 	if (bcm->dev) {
-		if (bcm->dev->drive_rts_on_open)
+		if (bcm->dev->use_autobaud_mode)
+			hci_uart_set_flow_control(hu, false);	/* Assert BT_UART_CTS_N */
+		else if (bcm->dev->drive_rts_on_open)
 			hci_uart_set_flow_control(hu, true);
 
 		hu->init_speed = bcm->dev->init_speed;
@@ -564,6 +568,7 @@ static int bcm_setup(struct hci_uart *hu)
 {
 	struct bcm_data *bcm = hu->priv;
 	bool fw_load_done = false;
+	bool use_autobaud_mode = (bcm->dev ? bcm->dev->use_autobaud_mode : 0);
 	unsigned int speed;
 	int err;
 
@@ -572,7 +577,7 @@ static int bcm_setup(struct hci_uart *hu)
 	hu->hdev->set_diag = bcm_set_diag;
 	hu->hdev->set_bdaddr = btbcm_set_bdaddr;
 
-	err = btbcm_initialize(hu->hdev, &fw_load_done);
+	err = btbcm_initialize(hu->hdev, &fw_load_done, use_autobaud_mode);
 	if (err)
 		return err;
 
@@ -616,7 +621,7 @@ static int bcm_setup(struct hci_uart *hu)
 		btbcm_write_pcm_int_params(hu->hdev, &params);
 	}
 
-	err = btbcm_finalize(hu->hdev, &fw_load_done);
+	err = btbcm_finalize(hu->hdev, &fw_load_done, use_autobaud_mode);
 	if (err)
 		return err;
 
@@ -1197,6 +1202,11 @@ static int bcm_acpi_probe(struct bcm_device *dev)
 
 static int bcm_of_probe(struct bcm_device *bdev)
 {
+	bdev->use_autobaud_mode = device_property_read_bool(bdev->dev,
+							    "brcm,requires-autobaud-mode");
+	if (bdev->use_autobaud_mode)
+		bdev->no_early_set_baudrate = true;
+
 	device_property_read_u32(bdev->dev, "max-speed", &bdev->oper_speed);
 	device_property_read_u8_array(bdev->dev, "brcm,bt-pcm-int-params",
 				      bdev->pcm_int_params, 5);
@@ -1544,6 +1554,7 @@ static const struct of_device_id bcm_bluetooth_of_match[] = {
 	{ .compatible = "brcm,bcm43430a0-bt" },
 	{ .compatible = "brcm,bcm43430a1-bt" },
 	{ .compatible = "brcm,bcm43438-bt", .data = &bcm43438_device_data },
+	{ .compatible = "brcm,bcm4349-bt", .data = &bcm43438_device_data },
 	{ .compatible = "brcm,bcm43540-bt", .data = &bcm4354_device_data },
 	{ .compatible = "brcm,bcm4335a0" },
 	{ },
diff --git a/drivers/bluetooth/hci_intel.c b/drivers/bluetooth/hci_intel.c
index 7249b91d9b91..78afb9a348e7 100644
--- a/drivers/bluetooth/hci_intel.c
+++ b/drivers/bluetooth/hci_intel.c
@@ -1217,7 +1217,11 @@ static struct platform_driver intel_driver = {
 
 int __init intel_init(void)
 {
-	platform_driver_register(&intel_driver);
+	int err;
+
+	err = platform_driver_register(&intel_driver);
+	if (err)
+		return err;
 
 	return hci_uart_register_proto(&intel_proto);
 }
diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
index eab34e24d944..95a97b380823 100644
--- a/drivers/bluetooth/hci_qca.c
+++ b/drivers/bluetooth/hci_qca.c
@@ -1120,7 +1120,7 @@ static void qca_controller_memdump(struct work_struct *work)
 				    qca_memdump->ram_dump_size);
 			memdump_buf = qca_memdump->memdump_buf_head;
 			dev_coredumpv(&hu->serdev->dev, memdump_buf,
-				      qca_memdump->received_dump, GFP_KERNEL);
+				      qca_memdump->received_dump);
 			cancel_delayed_work(&qca->ctrl_memdump_timeout);
 			kfree(qca->qca_memdump);
 			qca->qca_memdump = NULL;
@@ -1588,7 +1588,7 @@ static bool qca_wakeup(struct hci_dev *hdev)
 	wakeup = device_may_wakeup(hu->serdev->ctrl->dev.parent);
 	bt_dev_dbg(hu->hdev, "wakeup status : %d", wakeup);
 
-	return !wakeup;
+	return wakeup;
 }
 
 static int qca_regulator_init(struct hci_uart *hu)
diff --git a/drivers/bus/bt1-apb.c b/drivers/bus/bt1-apb.c
index b25ff941e7c7..63b1b4a76671 100644
--- a/drivers/bus/bt1-apb.c
+++ b/drivers/bus/bt1-apb.c
@@ -175,10 +175,9 @@ static int bt1_apb_request_rst(struct bt1_apb *apb)
 	int ret;
 
 	apb->prst = devm_reset_control_get_optional_exclusive(apb->dev, "prst");
-	if (IS_ERR(apb->prst)) {
-		dev_warn(apb->dev, "Couldn't get reset control line\n");
-		return PTR_ERR(apb->prst);
-	}
+	if (IS_ERR(apb->prst))
+		return dev_err_probe(apb->dev, PTR_ERR(apb->prst),
+				     "Couldn't get reset control line\n");
 
 	ret = reset_control_deassert(apb->prst);
 	if (ret)
@@ -199,10 +198,9 @@ static int bt1_apb_request_clk(struct bt1_apb *apb)
 	int ret;
 
 	apb->pclk = devm_clk_get(apb->dev, "pclk");
-	if (IS_ERR(apb->pclk)) {
-		dev_err(apb->dev, "Couldn't get APB clock descriptor\n");
-		return PTR_ERR(apb->pclk);
-	}
+	if (IS_ERR(apb->pclk))
+		return dev_err_probe(apb->dev, PTR_ERR(apb->pclk),
+				     "Couldn't get APB clock descriptor\n");
 
 	ret = clk_prepare_enable(apb->pclk);
 	if (ret) {
diff --git a/drivers/bus/bt1-axi.c b/drivers/bus/bt1-axi.c
index e7a6744acc7b..70e49a6e5374 100644
--- a/drivers/bus/bt1-axi.c
+++ b/drivers/bus/bt1-axi.c
@@ -135,10 +135,9 @@ static int bt1_axi_request_rst(struct bt1_axi *axi)
 	int ret;
 
 	axi->arst = devm_reset_control_get_optional_exclusive(axi->dev, "arst");
-	if (IS_ERR(axi->arst)) {
-		dev_warn(axi->dev, "Couldn't get reset control line\n");
-		return PTR_ERR(axi->arst);
-	}
+	if (IS_ERR(axi->arst))
+		return dev_err_probe(axi->dev, PTR_ERR(axi->arst),
+				     "Couldn't get reset control line\n");
 
 	ret = reset_control_deassert(axi->arst);
 	if (ret)
@@ -159,10 +158,9 @@ static int bt1_axi_request_clk(struct bt1_axi *axi)
 	int ret;
 
 	axi->aclk = devm_clk_get(axi->dev, "aclk");
-	if (IS_ERR(axi->aclk)) {
-		dev_err(axi->dev, "Couldn't get AXI Interconnect clock\n");
-		return PTR_ERR(axi->aclk);
-	}
+	if (IS_ERR(axi->aclk))
+		return dev_err_probe(axi->dev, PTR_ERR(axi->aclk),
+				     "Couldn't get AXI Interconnect clock\n");
 
 	ret = clk_prepare_enable(axi->aclk);
 	if (ret) {
diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
index 841626727f6b..a7511e18b7e3 100644
--- a/drivers/bus/mhi/host/pci_generic.c
+++ b/drivers/bus/mhi/host/pci_generic.c
@@ -557,6 +557,8 @@ static const struct pci_device_id mhi_pci_id_table[] = {
 		.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
 	{ PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
 		.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+	{ PCI_DEVICE(0x1eac, 0x2001), /* EM120R-GL for FCCL (sdx24) */
+		.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
 	/* T99W175 (sdx55), Both for eSIM and Non-eSIM */
 	{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
 		.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
@@ -578,6 +580,9 @@ static const struct pci_device_id mhi_pci_id_table[] = {
 	/* MV31-W (Cinterion) */
 	{ PCI_DEVICE(0x1269, 0x00b3),
 		.driver_data = (kernel_ulong_t) &mhi_mv31_info },
+	/* MV31-W (Cinterion), based on new baseline */
+	{ PCI_DEVICE(0x1269, 0x00b4),
+		.driver_data = (kernel_ulong_t) &mhi_mv31_info },
 	/* MV32-WA (Cinterion) */
 	{ PCI_DEVICE(0x1269, 0x00ba),
 		.driver_data = (kernel_ulong_t) &mhi_mv32_info },
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index db612045616f..a6ec0566db12 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
  * 370/XP, Dove, Orion5x and MV78xx0)
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The Marvell EBU SoCs have a configurable physical address space:
  * the physical address at which certain devices (PCIe, NOR, NAND,
  * etc.) sit can be configured. The configuration takes place through
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index dcfb32ee5cb6..eb1ba6319fda 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP L3 Interconnect error handling driver
  *
  * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  *	Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/init.h>
 #include <linux/interrupt.h>
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index 73431f81da28..bb3eebd3465d 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -1,18 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * OMAP L3 Interconnect  error handling driver header
  *
  * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  *	sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #ifndef __OMAP_L3_NOC_H
 #define __OMAP_L3_NOC_H
diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
index 60b082fe2ed0..4cd2e127946e 100644
--- a/drivers/bus/sunxi-rsb.c
+++ b/drivers/bus/sunxi-rsb.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * RSB (Reduced Serial Bus) driver.
  *
  * Author: Chen-Yu Tsai <wens@csie.org>
  *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
  * The RSB controller looks like an SMBus controller which only supports
  * byte and word data transfers. But, it differs from standard SMBus
  * protocol on several aspects:
@@ -31,7 +28,6 @@
  * This document is officially released by Allwinner.
  *
  * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver.
- *
  */
 
 #include <linux/clk.h>
diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
index 35b59f92fa66..662266719682 100644
--- a/drivers/bus/tegra-gmi.c
+++ b/drivers/bus/tegra-gmi.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Driver for NVIDIA Generic Memory Interface
  *
  * Copyright (C) 2016 Host Mobility AB. All rights reserved.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/bus/ts-nbus.c b/drivers/bus/ts-nbus.c
index 9989ce904a37..38c886dc2ed6 100644
--- a/drivers/bus/ts-nbus.c
+++ b/drivers/bus/ts-nbus.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * NBUS driver for TS-4600 based boards
  *
  * Copyright (c) 2016 - Savoir-faire Linux
  * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * This driver implements a GPIOs bit-banged bus, called the NBUS by Technologic
  * Systems. It is used to communicate with the peripherals in the FPGA on the
  * TS-4600 SoM.
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
index a43743887db1..06bc060534d8 100644
--- a/drivers/char/hw_random/iproc-rng200.c
+++ b/drivers/char/hw_random/iproc-rng200.c
@@ -1,14 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
 * Copyright (C) 2015 Broadcom Corporation
 *
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
 */
 /*
  * DESCRIPTION: The Broadcom iProc RNG200 Driver
diff --git a/drivers/char/random.c b/drivers/char/random.c
index 655e327d425e..e3dd1dd3dd22 100644
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -87,7 +87,7 @@ static struct fasync_struct *fasync;
 
 /* Control how we warn userspace. */
 static struct ratelimit_state urandom_warning =
-	RATELIMIT_STATE_INIT("warn_urandom_randomness", HZ, 3);
+	RATELIMIT_STATE_INIT_FLAGS("urandom_warning", HZ, 3, RATELIMIT_MSG_ON_RELEASE);
 static int ratelimit_disable __read_mostly =
 	IS_ENABLED(CONFIG_WARN_ALL_UNSEEDED_RANDOM);
 module_param_named(ratelimit_disable, ratelimit_disable, int, 0644);
@@ -408,7 +408,7 @@ static ssize_t get_random_bytes_user(struct iov_iter *iter)
 
 	/*
 	 * Immediately overwrite the ChaCha key at index 4 with random
-	 * bytes, in case userspace causes copy_to_user() below to sleep
+	 * bytes, in case userspace causes copy_to_iter() below to sleep
 	 * forever, so that we still retain forward secrecy in that case.
 	 */
 	crng_make_state(chacha_state, (u8 *)&chacha_state[4], CHACHA_KEY_SIZE);
@@ -1009,7 +1009,7 @@ void add_interrupt_randomness(int irq)
 	if (new_count & MIX_INFLIGHT)
 		return;
 
-	if (new_count < 64 && !time_is_before_jiffies(fast_pool->last + HZ))
+	if (new_count < 1024 && !time_is_before_jiffies(fast_pool->last + HZ))
 		return;
 
 	if (unlikely(!fast_pool->mix.func))
diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c
index e9da0e69bf6c..e1fda6ad5cd5 100644
--- a/drivers/clk/axs10x/i2s_pll_clock.c
+++ b/drivers/clk/axs10x/i2s_pll_clock.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Synopsys AXS10X SDP I2S PLL clock driver
  *
  * Copyright (C) 2016 Synopsys
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/platform_device.h>
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
index 500345d99adb..90fb0e6ff573 100644
--- a/drivers/clk/axs10x/pll_clock.c
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Synopsys AXS10X SDP Generic PLL clock driver
  *
  * Copyright (C) 2017 Synopsys
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/platform_device.h>
diff --git a/drivers/clk/bcm/clk-bcm21664.c b/drivers/clk/bcm/clk-bcm21664.c
index eeae4cad2281..520c3aeb4ea9 100644
--- a/drivers/clk/bcm/clk-bcm21664.c
+++ b/drivers/clk/bcm/clk-bcm21664.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2014 Broadcom Corporation
  * Copyright 2014 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include "clk-kona.h"
diff --git a/drivers/clk/bcm/clk-bcm281xx.c b/drivers/clk/bcm/clk-bcm281xx.c
index 502a487d62c5..823d5dfa31b8 100644
--- a/drivers/clk/bcm/clk-bcm281xx.c
+++ b/drivers/clk/bcm/clk-bcm281xx.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2013 Broadcom Corporation
  * Copyright 2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include "clk-kona.h"
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
index fbc17ae5ff2b..c8383834fb39 100644
--- a/drivers/clk/bcm/clk-bcm63xx.c
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015 Broadcom Corporation
 #include <linux/init.h>
 #include <linux/clk-provider.h>
 #include <linux/of.h>
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index b8d073e4855f..43b04fc4c493 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/bcm/clk-hr2.c b/drivers/clk/bcm/clk-hr2.c
index f7c5b7379475..9f6318f3752b 100644
--- a/drivers/clk/bcm/clk-hr2.c
+++ b/drivers/clk/bcm/clk-hr2.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2017 Broadcom
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/bcm/clk-iproc-armpll.c b/drivers/clk/bcm/clk-iproc-armpll.c
index d7d628214b85..9e86c0c10b57 100644
--- a/drivers/clk/bcm/clk-iproc-armpll.c
+++ b/drivers/clk/bcm/clk-iproc-armpll.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
index e062dd4992ea..dcacf55c55ae 100644
--- a/drivers/clk/bcm/clk-iproc-asiu.c
+++ b/drivers/clk/bcm/clk-iproc-asiu.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 33da30f99c79..1a098db12062 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2014 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index d7e5b94bed45..0151d6ae1661 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (C) 2014 Broadcom Corporation */
 
 #ifndef _CLK_IPROC_H
 #define _CLK_IPROC_H
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index 5dd65164c8b1..338558f6fbae 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2013 Broadcom Corporation
  * Copyright 2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/io.h>
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index cc3b1e1bc087..ec5749e301ba 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2013 Broadcom Corporation
  * Copyright 2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include "clk-kona.h"
diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h
index f4b39bb5558a..e09655024ac2 100644
--- a/drivers/clk/bcm/clk-kona.h
+++ b/drivers/clk/bcm/clk-kona.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2013 Broadcom Corporation
  * Copyright 2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef _CLK_KONA_H
diff --git a/drivers/clk/bcm/clk-ns2.c b/drivers/clk/bcm/clk-ns2.c
index adc14145861a..065f4290aaad 100644
--- a/drivers/clk/bcm/clk-ns2.c
+++ b/drivers/clk/bcm/clk-ns2.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c
index cf66f640a47d..c24c9adbc6f3 100644
--- a/drivers/clk/bcm/clk-nsp.c
+++ b/drivers/clk/bcm/clk-nsp.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015 Broadcom Corporation
 
 #include <linux/kernel.h>
 #include <linux/err.h>
diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
index f9d5b7334341..4fb4fd4b06bd 100644
--- a/drivers/clk/clk-devres.c
+++ b/drivers/clk/clk-devres.c
@@ -4,42 +4,101 @@
 #include <linux/export.h>
 #include <linux/gfp.h>
 
+struct devm_clk_state {
+	struct clk *clk;
+	void (*exit)(struct clk *clk);
+};
+
 static void devm_clk_release(struct device *dev, void *res)
 {
-	clk_put(*(struct clk **)res);
+	struct devm_clk_state *state = res;
+
+	if (state->exit)
+		state->exit(state->clk);
+
+	clk_put(state->clk);
 }
 
-struct clk *devm_clk_get(struct device *dev, const char *id)
+static struct clk *__devm_clk_get(struct device *dev, const char *id,
+				  struct clk *(*get)(struct device *dev, const char *id),
+				  int (*init)(struct clk *clk),
+				  void (*exit)(struct clk *clk))
 {
-	struct clk **ptr, *clk;
+	struct devm_clk_state *state;
+	struct clk *clk;
+	int ret;
 
-	ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
-	if (!ptr)
+	state = devres_alloc(devm_clk_release, sizeof(*state), GFP_KERNEL);
+	if (!state)
 		return ERR_PTR(-ENOMEM);
 
-	clk = clk_get(dev, id);
-	if (!IS_ERR(clk)) {
-		*ptr = clk;
-		devres_add(dev, ptr);
-	} else {
-		devres_free(ptr);
+	clk = get(dev, id);
+	if (IS_ERR(clk)) {
+		ret = PTR_ERR(clk);
+		goto err_clk_get;
 	}
 
+	if (init) {
+		ret = init(clk);
+		if (ret)
+			goto err_clk_init;
+	}
+
+	state->clk = clk;
+	state->exit = exit;
+
+	devres_add(dev, state);
+
 	return clk;
+
+err_clk_init:
+
+	clk_put(clk);
+err_clk_get:
+
+	devres_free(state);
+	return ERR_PTR(ret);
+}
+
+struct clk *devm_clk_get(struct device *dev, const char *id)
+{
+	return __devm_clk_get(dev, id, clk_get, NULL, NULL);
 }
 EXPORT_SYMBOL(devm_clk_get);
 
-struct clk *devm_clk_get_optional(struct device *dev, const char *id)
+struct clk *devm_clk_get_prepared(struct device *dev, const char *id)
 {
-	struct clk *clk = devm_clk_get(dev, id);
+	return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare);
+}
+EXPORT_SYMBOL_GPL(devm_clk_get_prepared);
 
-	if (clk == ERR_PTR(-ENOENT))
-		return NULL;
+struct clk *devm_clk_get_enabled(struct device *dev, const char *id)
+{
+	return __devm_clk_get(dev, id, clk_get,
+			      clk_prepare_enable, clk_disable_unprepare);
+}
+EXPORT_SYMBOL_GPL(devm_clk_get_enabled);
 
-	return clk;
+struct clk *devm_clk_get_optional(struct device *dev, const char *id)
+{
+	return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL);
 }
 EXPORT_SYMBOL(devm_clk_get_optional);
 
+struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id)
+{
+	return __devm_clk_get(dev, id, clk_get_optional,
+			      clk_prepare, clk_unprepare);
+}
+EXPORT_SYMBOL_GPL(devm_clk_get_optional_prepared);
+
+struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id)
+{
+	return __devm_clk_get(dev, id, clk_get_optional,
+			      clk_prepare_enable, clk_disable_unprepare);
+}
+EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled);
+
 struct clk_bulk_devres {
 	struct clk_bulk_data *clks;
 	int num_clks;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 54942d758ee6..e6b36247c16b 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -210,16 +210,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
 EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
 
 #ifdef CONFIG_OF
-static const struct of_device_id set_rate_parent_matches[] = {
-	{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
-	{ /* Sentinel */ },
-};
-
 static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
 {
 	struct clk_hw *hw;
 	const char *clk_name = node->name;
-	unsigned long flags = 0;
 	u32 div, mult;
 	int ret;
 
@@ -237,11 +231,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	if (of_match_node(set_rate_parent_matches, node))
-		flags |= CLK_SET_RATE_PARENT;
-
 	hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
-					    flags, mult, div, false);
+					    0, mult, div, false);
 	if (IS_ERR(hw)) {
 		/*
 		 * Clear OF_POPULATED flag so that clock registration can be
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index b4f8852201cb..60007b508590 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Synopsys HSDK SDP Generic PLL clock driver
  *
  * Copyright (C) 2017 Synopsys
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c
index 58428d0043fd..3786a0153ad1 100644
--- a/drivers/clk/clk-moxart.c
+++ b/drivers/clk/clk-moxart.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MOXA ART SoCs clock driver.
  *
  * Copyright (C) 2013 Jonas Jensen
  *
  * Jonas Jensen <jonas.jensen@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f00d4c1158d7..7fc191c15507 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -4279,54 +4279,6 @@ int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
 }
 EXPORT_SYMBOL_GPL(devm_clk_hw_register);
 
-static int devm_clk_match(struct device *dev, void *res, void *data)
-{
-	struct clk *c = res;
-	if (WARN_ON(!c))
-		return 0;
-	return c == data;
-}
-
-static int devm_clk_hw_match(struct device *dev, void *res, void *data)
-{
-	struct clk_hw *hw = res;
-
-	if (WARN_ON(!hw))
-		return 0;
-	return hw == data;
-}
-
-/**
- * devm_clk_unregister - resource managed clk_unregister()
- * @dev: device that is unregistering the clock data
- * @clk: clock to unregister
- *
- * Deallocate a clock allocated with devm_clk_register(). Normally
- * this function will not need to be called and the resource management
- * code will ensure that the resource is freed.
- */
-void devm_clk_unregister(struct device *dev, struct clk *clk)
-{
-	WARN_ON(devres_release(dev, devm_clk_unregister_cb, devm_clk_match, clk));
-}
-EXPORT_SYMBOL_GPL(devm_clk_unregister);
-
-/**
- * devm_clk_hw_unregister - resource managed clk_hw_unregister()
- * @dev: device that is unregistering the hardware-specific clock data
- * @hw: link to hardware-specific clock data
- *
- * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
- * this function will not need to be called and the resource management
- * code will ensure that the resource is freed.
- */
-void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
-{
-	WARN_ON(devres_release(dev, devm_clk_hw_unregister_cb, devm_clk_hw_match,
-				hw));
-}
-EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
-
 static void devm_clk_release(struct device *dev, void *res)
 {
 	clk_put(*(struct clk **)res);
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 71c102d950ab..a2aaa14fc1ae 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -64,10 +64,13 @@ struct clk_fracn_gppll {
  * Fout = Fvco / (rdiv * odiv)
  */
 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
-	PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3),
-	PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8),
-	PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3),
-	PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3),
+	PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),
+	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
+	PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),
+	PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4),
+	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
+	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
+	PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),
 	PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5)
 };
 
@@ -131,18 +134,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
 	mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
 
 	rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
-	rdiv = rdiv + 1;
 	odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
-	switch (odiv) {
-	case 0:
-		odiv = 2;
-		break;
-	case 1:
-		odiv = 3;
-		break;
-	default:
-		break;
-	}
 
 	/*
 	 * Sometimes, the recalculated rate has deviation due to
@@ -160,6 +152,20 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
 	if (rate)
 		return (unsigned long)rate;
 
+	if (!rdiv)
+		rdiv = rdiv + 1;
+
+	switch (odiv) {
+	case 0:
+		odiv = 2;
+		break;
+	case 1:
+		odiv = 3;
+		break;
+	default:
+		break;
+	}
+
 	/* Fvco = Fref * (MFI + MFN / MFD) */
 	fvco = fvco * mfi * mfd + fvco * mfn;
 	do_div(fvco, mfd * rdiv * odiv);
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index edcc87661d1f..f5c9fa40491c 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -150,7 +150,7 @@ static const struct imx93_clk_ccgr {
 	{ IMX93_CLK_A55_GATE,		"a55",		"a55_root",		0x8000, },
 	/* M33 critical clk for system run */
 	{ IMX93_CLK_CM33_GATE,		"cm33",		"m33_root",		0x8040, CLK_IS_CRITICAL },
-	{ IMX93_CLK_ADC1_GATE,		"adc1",		"osc_24m",		0x82c0, },
+	{ IMX93_CLK_ADC1_GATE,		"adc1",		"adc_root",		0x82c0, },
 	{ IMX93_CLK_WDOG1_GATE,		"wdog1",	"osc_24m",		0x8300, },
 	{ IMX93_CLK_WDOG2_GATE,		"wdog2",	"osc_24m",		0x8340, },
 	{ IMX93_CLK_WDOG3_GATE,		"wdog3",	"osc_24m",		0x8380, },
@@ -160,7 +160,7 @@ static const struct imx93_clk_ccgr {
 	{ IMX93_CLK_SEMA2_GATE,		"sema2",	"bus_wakeup_root",	0x8480, },
 	{ IMX93_CLK_MU_A_GATE,		"mu_a",		"bus_aon_root",		0x84c0, },
 	{ IMX93_CLK_MU_B_GATE,		"mu_b",		"bus_aon_root",		0x8500, },
-	{ IMX93_CLK_EDMA1_GATE,		"edma1",	"wakeup_axi_root",	0x8540, },
+	{ IMX93_CLK_EDMA1_GATE,		"edma1",	"m33_root",		0x8540, },
 	{ IMX93_CLK_EDMA2_GATE,		"edma2",	"wakeup_axi_root",	0x8580, },
 	{ IMX93_CLK_FLEXSPI1_GATE,	"flexspi",	"flexspi_root",		0x8640, },
 	{ IMX93_CLK_GPIO1_GATE,		"gpio1",	"m33_root",		0x8880, },
@@ -219,7 +219,7 @@ static const struct imx93_clk_ccgr {
 	{ IMX93_CLK_LCDIF_GATE,		"lcdif",	"media_apb_root",	0x9640, },
 	{ IMX93_CLK_PXP_GATE,		"pxp",		"media_apb_root",	0x9680, },
 	{ IMX93_CLK_ISI_GATE,		"isi",		"media_apb_root",	0x96c0, },
-	{ IMX93_CLK_NIC_MEDIA_GATE,	"nic_media",	"media_apb_root",	0x9700, },
+	{ IMX93_CLK_NIC_MEDIA_GATE,	"nic_media",	"media_axi_root",	0x9700, },
 	{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root",		0x9a00, },
 	{ IMX93_CLK_USB_TEST_60M_GATE,	"usb_test_60m",	"hsio_usb_test_60m_root", 0x9a40, },
 	{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m",		0x9a80, },
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index 7e1b136e71ae..d4b4e74e22da 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * SCI Clock driver for keystone based devices
  *
  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
  *	Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 #include <linux/clk-provider.h>
 #include <linux/err.h>
diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 47c2289f3d1d..edf1e2ed2b59 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -36,6 +36,14 @@ static const struct mtk_gate eth_clks[] = {
 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static const struct of_device_id of_match_clk_mt2701_eth[] = {
 	{ .compatible = "mediatek,mt2701-ethsys", },
 	{}
@@ -58,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index 79929ed37f83..1458109d99d9 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -35,6 +35,14 @@ static const struct mtk_gate g3d_clks[] = {
 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
 };
 
+static u16 rst_ofs[] = { 0xc, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -52,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0xc);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 1aa36cb93ad0..434cbbe8c037 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -33,6 +33,14 @@ static const struct mtk_gate hif_clks[] = {
 	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static const struct of_device_id of_match_clk_mt2701_hif[] = {
 	{ .compatible = "mediatek,mt2701-hifsys", },
 	{}
@@ -57,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 04ba356db2d7..9b442af37e67 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -735,6 +735,24 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
 	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 };
 
+static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
+static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = infrasys_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = pericfg_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+	},
+};
+
 static struct clk_hw_onecell_data *infra_clk_data;
 
 static void __init mtk_infrasys_init_early(struct device_node *node)
@@ -787,7 +805,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -910,7 +928,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 410b059727ea..56980dd6c2ea 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1258,6 +1258,24 @@ static const struct mtk_pll_data plls[] = {
 		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
 };
 
+static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
+static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infra */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = infrasys_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
+	},
+	/* peri */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = pericfg_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+	},
+};
+
 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -1361,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return r;
 }
@@ -1383,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index b12d48705496..43de0477d5d9 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -65,6 +65,14 @@ static const struct mtk_gate sgmii_clks[] = {
 		   "ssusb_cdr_fb", 5),
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -82,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 58728e35e80a..67e96231dd25 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -76,6 +76,14 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -93,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -115,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index e4a5e5230861..3b55f8641fae 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -610,6 +610,24 @@ static struct mtk_composite peri_muxes[] = {
 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
 };
 
+static u16 infrasys_rst_ofs[] = { 0x30, };
+static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = infrasys_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = pericfg_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+	},
+};
+
 static int mtk_topckgen_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -663,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
 	if (r)
 		return r;
 
-	mtk_register_reset_controller(node, 1, 0x30);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
 	return 0;
 }
@@ -714,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
 	clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
 
-	mtk_register_reset_controller(node, 2, 0x0);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
 	return 0;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index c49fd732c9b2..282dd6559465 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -76,6 +76,14 @@ static const struct mtk_gate sgmii_clks[2][4] = {
 	}
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -92,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index acaa97fda331..0c8b9e139789 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -71,6 +71,14 @@ static const struct mtk_gate pcie_clks[] = {
 	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
 };
 
+static u16 rst_ofs[] = { 0x34, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SIMPLE,
+	.rst_bank_ofs = rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+};
+
 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -88,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
@@ -110,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	mtk_register_reset_controller(node, 1, 0x34);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 9ef524b44862..b68888a034c4 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -514,6 +514,24 @@ static const struct mtk_composite peri_clks[] __initconst = {
 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 };
 
+static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
+static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = infrasys_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = pericfg_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+	}
+};
+
 static void __init mtk_topckgen_init(struct device_node *node)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -559,7 +577,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 
@@ -587,7 +605,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 0929db330852..b8529ee7199d 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -819,6 +819,24 @@ static const struct mtk_gate venclt_clks[] __initconst = {
 	GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
 };
 
+static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
+static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
+
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+	/* infrasys */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = infrasys_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
+	},
+	/* pericfg */
+	{
+		.version = MTK_RST_SIMPLE,
+		.rst_bank_ofs = pericfg_rst_ofs,
+		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
+	}
+};
+
 static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
 static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
 
@@ -882,7 +900,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0x30);
+	mtk_register_reset_controller(node, &clk_rst_desc[0]);
 }
 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
 
@@ -910,7 +928,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
 		pr_err("%s(): could not register clock provider: %d\n",
 			__func__, r);
 
-	mtk_register_reset_controller(node, 2, 0);
+	mtk_register_reset_controller(node, &clk_rst_desc[1]);
 }
 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index b5c17988c337..8512101e1189 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -18,9 +18,6 @@
 
 #include <dt-bindings/clock/mt8183-clk.h>
 
-/* Infra global controller reset set register */
-#define INFRA_RST0_SET_OFFSET		0x120
-
 static DEFINE_SPINLOCK(mt8183_clk_lock);
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
@@ -1153,6 +1150,19 @@ static const struct mtk_pll_data plls[] = {
 		0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
 };
 
+static u16 infra_rst_ofs[] = {
+	INFRA_RST0_SET_OFFSET,
+	INFRA_RST1_SET_OFFSET,
+	INFRA_RST2_SET_OFFSET,
+	INFRA_RST3_SET_OFFSET,
+};
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
+};
+
 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
 {
 	struct clk_hw_onecell_data *clk_data;
@@ -1240,7 +1250,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
 		return r;
 	}
 
-	mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
+	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
 	return r;
 }
diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/mediatek/clk-mt8186-infra_ao.c
index 2a7adc25abaa..df2a6bd1aefa 100644
--- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c
@@ -6,6 +6,7 @@
 #include <linux/clk-provider.h>
 #include <linux/platform_device.h>
 #include <dt-bindings/clock/mt8186-clk.h>
+#include <dt-bindings/reset/mt8186-resets.h>
 
 #include "clk-gate.h"
 #include "clk-mtk.h"
@@ -191,9 +192,31 @@ static const struct mtk_gate infra_ao_clks[] = {
 	GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
 };
 
+static u16 infra_ao_rst_ofs[] = {
+	INFRA_RST0_SET_OFFSET,
+	INFRA_RST1_SET_OFFSET,
+	INFRA_RST2_SET_OFFSET,
+	INFRA_RST3_SET_OFFSET,
+	INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+	[MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
+	[MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
+};
+
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_ao_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+	.rst_idx_map = infra_ao_idx_map,
+	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c
index 87c3b79b79cf..635f7a0b629a 100644
--- a/drivers/clk/mediatek/clk-mt8192-msdc.c
+++ b/drivers/clk/mediatek/clk-mt8192-msdc.c
@@ -12,28 +12,15 @@
 
 #include <dt-bindings/clock/mt8192-clk.h>
 
-static const struct mtk_gate_regs msdc_cg_regs = {
-	.set_ofs = 0xb4,
-	.clr_ofs = 0xb4,
-	.sta_ofs = 0xb4,
-};
-
 static const struct mtk_gate_regs msdc_top_cg_regs = {
 	.set_ofs = 0x0,
 	.clr_ofs = 0x0,
 	.sta_ofs = 0x0,
 };
 
-#define GATE_MSDC(_id, _name, _parent, _shift)	\
-	GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
-
 #define GATE_MSDC_TOP(_id, _name, _parent, _shift)	\
 	GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 
-static const struct mtk_gate msdc_clks[] = {
-	GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22),
-};
-
 static const struct mtk_gate msdc_top_clks[] = {
 	GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
 	GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1),
@@ -52,11 +39,6 @@ static const struct mtk_gate msdc_top_clks[] = {
 	GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
 };
 
-static const struct mtk_clk_desc msdc_desc = {
-	.clks = msdc_clks,
-	.num_clks = ARRAY_SIZE(msdc_clks),
-};
-
 static const struct mtk_clk_desc msdc_top_desc = {
 	.clks = msdc_top_clks,
 	.num_clks = ARRAY_SIZE(msdc_top_clks),
@@ -64,9 +46,6 @@ static const struct mtk_clk_desc msdc_top_desc = {
 
 static const struct of_device_id of_match_clk_mt8192_msdc[] = {
 	{
-		.compatible = "mediatek,mt8192-msdc",
-		.data = &msdc_desc,
-	}, {
 		.compatible = "mediatek,mt8192-msdc_top",
 		.data = &msdc_top_desc,
 	}, {
diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index dda211b7a745..ebbd2798d9a3 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -18,6 +18,7 @@
 #include "clk-pll.h"
 
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/reset/mt8192-resets.h>
 
 static DEFINE_SPINLOCK(mt8192_clk_lock);
 
@@ -1114,6 +1115,30 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
 };
 
+static u16 infra_ao_rst_ofs[] = {
+	INFRA_RST0_SET_OFFSET,
+	INFRA_RST1_SET_OFFSET,
+	INFRA_RST2_SET_OFFSET,
+	INFRA_RST3_SET_OFFSET,
+	INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+	[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+	[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
+	[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
+	[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
+	[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
+};
+
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_ao_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+	.rst_idx_map = infra_ao_idx_map,
+	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
 #define MT8192_PLL_FMAX		(3800UL * MHZ)
 #define MT8192_PLL_FMIN		(1500UL * MHZ)
 #define MT8192_INTEGER_BITS	8
@@ -1240,6 +1265,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
 	if (r)
 		goto free_clk_data;
 
+	r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+	if (r)
+		goto free_clk_data;
+
 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 	if (r)
 		goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 8ebe3b9415c4..97657f255618 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -7,6 +7,7 @@
 #include "clk-mtk.h"
 
 #include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/reset/mt8195-resets.h>
 #include <linux/clk-provider.h>
 #include <linux/platform_device.h>
 
@@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] = {
 	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
 };
 
+static u16 infra_ao_rst_ofs[] = {
+	INFRA_RST0_SET_OFFSET,
+	INFRA_RST1_SET_OFFSET,
+	INFRA_RST2_SET_OFFSET,
+	INFRA_RST3_SET_OFFSET,
+	INFRA_RST4_SET_OFFSET,
+};
+
+static u16 infra_ao_idx_map[] = {
+	[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+	[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
+	[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
+};
+
+static struct mtk_clk_rst_desc infra_ao_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_ao_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
+	.rst_idx_map = infra_ao_idx_map,
+	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
+};
+
 static const struct mtk_clk_desc infra_ao_desc = {
 	.clks = infra_ao_clks,
 	.num_clks = ARRAY_SIZE(infra_ao_clks),
+	.rst_desc = &infra_ao_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index b9188000ab3c..05a188c62119 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -444,6 +444,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, clk_data);
 
+	if (mcd->rst_desc) {
+		r = mtk_register_reset_controller_with_dev(&pdev->dev,
+							   mcd->rst_desc);
+		if (r)
+			goto unregister_clks;
+	}
+
 	return r;
 
 unregister_clks:
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index adb1304d35d4..1b95c484d5aa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -187,15 +189,10 @@ void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data);
 struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
+	const struct mtk_clk_rst_desc *rst_desc;
 };
 
 int mtk_clk_simple_probe(struct platform_device *pdev);
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..179505549a7c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,55 +8,39 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
+#include "reset.h"
 
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
-
-static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4);
-
-	return regmap_write(data->regmap, reg, 1);
+	return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
 }
 
-static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+static int mtk_reset_update(struct reset_controller_dev *rcdev,
+			    unsigned long id, bool deassert)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-	unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int val = deassert ? 0 : ~0;
 
-	return regmap_write(data->regmap, reg, 1);
+	return regmap_update_bits(data->regmap,
+				  data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
+				  BIT(id % RST_NR_PER_BANK), val);
 }
 
 static int mtk_reset_assert(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+			    unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), ~0);
+	return mtk_reset_update(rcdev, id, false);
 }
 
 static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
-				unsigned long id)
+			      unsigned long id)
 {
-	struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
-
-	return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
-			BIT(id % 32), 0);
+	return mtk_reset_update(rcdev, id, true);
 }
 
-static int mtk_reset(struct reset_controller_dev *rcdev,
-			      unsigned long id)
+static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
 {
 	int ret;
 
@@ -67,8 +51,32 @@ static int mtk_reset(struct reset_controller_dev *rcdev,
 	return mtk_reset_deassert(rcdev, id);
 }
 
+static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id, bool deassert)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int deassert_ofs = deassert ? 0x4 : 0;
+
+	return regmap_write(data->regmap,
+			    data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
+			    deassert_ofs,
+			    BIT(id % RST_NR_PER_BANK));
+}
+
+static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
+				    unsigned long id)
+{
+	return mtk_reset_update_set_clr(rcdev, id, false);
+}
+
+static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
+				      unsigned long id)
+{
+	return mtk_reset_update_set_clr(rcdev, id, true);
+}
+
 static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
-	unsigned long id)
+			     unsigned long id)
 {
 	int ret;
 
@@ -90,51 +98,135 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
-static void mtk_register_reset_controller_common(struct device_node *np,
-			unsigned int num_regs, int regofs,
-			const struct reset_control_ops *reset_ops)
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+
+	if (reset_spec->args[0] >= rcdev->nr_resets ||
+	    reset_spec->args[0] >= data->desc->rst_idx_map_nr)
+		return -EINVAL;
+
+	return data->desc->rst_idx_map[reset_spec->args[0]];
+}
+
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc)
 {
-	struct mtk_reset *data;
-	int ret;
 	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		pr_err("mtk clock reset desc is NULL\n");
+		return -EINVAL;
+	}
+
+	switch (desc->version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", desc->version);
+		return -EINVAL;
+	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
 		pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
-		return;
+		return -EINVAL;
 	}
 
 	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	if (!data)
-		return;
+		return -ENOMEM;
 
+	data->desc = desc;
 	data->regmap = regmap;
-	data->regofs = regofs;
 	data->rcdev.owner = THIS_MODULE;
-	data->rcdev.nr_resets = num_regs * 32;
-	data->rcdev.ops = reset_ops;
+	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 
+	if (data->desc->rst_idx_map_nr > 0) {
+		data->rcdev.of_reset_n_cells = 1;
+		data->rcdev.nr_resets = desc->rst_idx_map_nr;
+		data->rcdev.of_xlate = reset_xlate;
+	} else {
+		data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
+	}
+
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
-		return;
+		return ret;
 	}
-}
 
-void mtk_register_reset_controller(struct device_node *np,
-	unsigned int num_regs, int regofs)
-{
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops);
+	return 0;
 }
 
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs)
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc)
 {
-	mtk_register_reset_controller_common(np, num_regs, regofs,
-		&mtk_reset_ops_set_clr);
+	struct device_node *np = dev->of_node;
+	struct regmap *regmap;
+	const struct reset_control_ops *rcops = NULL;
+	struct mtk_clk_rst_data *data;
+	int ret;
+
+	if (!desc) {
+		dev_err(dev, "mtk clock reset desc is NULL\n");
+		return -EINVAL;
+	}
+
+	switch (desc->version) {
+	case MTK_RST_SIMPLE:
+		rcops = &mtk_reset_ops;
+		break;
+	case MTK_RST_SET_CLR:
+		rcops = &mtk_reset_ops_set_clr;
+		break;
+	default:
+		dev_err(dev, "Unknown reset version %d\n", desc->version);
+		return -EINVAL;
+	}
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "Cannot find regmap %pe\n", regmap);
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->desc = desc;
+	data->regmap = regmap;
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = rcops;
+	data->rcdev.of_node = np;
+	data->rcdev.dev = dev;
+
+	if (data->desc->rst_idx_map_nr > 0) {
+		data->rcdev.of_reset_n_cells = 1;
+		data->rcdev.nr_resets = desc->rst_idx_map_nr;
+		data->rcdev.of_xlate = reset_xlate;
+	} else {
+		data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
+	}
+
+	ret = devm_reset_controller_register(dev, &data->rcdev);
+	if (ret) {
+		dev_err(dev, "could not register reset controller: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..6a58a3d59165
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+#define RST_NR_PER_BANK 32
+
+/* Infra global controller reset set register */
+#define INFRA_RST0_SET_OFFSET 0x120
+#define INFRA_RST1_SET_OFFSET 0x130
+#define INFRA_RST2_SET_OFFSET 0x140
+#define INFRA_RST3_SET_OFFSET 0x150
+#define INFRA_RST4_SET_OFFSET 0x730
+
+/**
+ * enum mtk_reset_version - Version of MediaTek clock reset controller.
+ * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
+ * @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
+ * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
+ */
+enum mtk_reset_version {
+	MTK_RST_SIMPLE = 0,
+	MTK_RST_SET_CLR,
+	MTK_RST_MAX,
+};
+
+/**
+ * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
+ * @version: Reset version which is defined in enum mtk_reset_version.
+ * @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
+ * @rst_bank_nr: Quantity of reset bank.
+ * @rst_idx_map:Pointer to an array containing ids if input argument is index.
+ *		This array is not necessary if our input argument does not mean index.
+ * @rst_idx_map_nr: Quantity of reset index map.
+ */
+struct mtk_clk_rst_desc {
+	enum mtk_reset_version version;
+	u16 *rst_bank_ofs;
+	u32 rst_bank_nr;
+	u16 *rst_idx_map;
+	u32 rst_idx_map_nr;
+};
+
+/**
+ * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
+ * @regmap: Pointer to base address of reset register address.
+ * @rcdev: Reset controller device.
+ * @desc: Pointer to description of the reset controller.
+ */
+struct mtk_clk_rst_data {
+	struct regmap *regmap;
+	struct reset_controller_dev rcdev;
+	const struct mtk_clk_rst_desc *desc;
+};
+
+/**
+ * mtk_register_reset_controller - Register MediaTek clock reset controller
+ * @np: Pointer to device node.
+ * @desc: Constant pointer to description of clock reset.
+ *
+ * Return: 0 on success and errorno otherwise.
+ */
+int mtk_register_reset_controller(struct device_node *np,
+				  const struct mtk_clk_rst_desc *desc);
+
+/**
+ * mtk_register_reset_controller - Register mediatek clock reset controller with device
+ * @np: Pointer to device.
+ * @desc: Constant pointer to description of clock reset.
+ *
+ * Return: 0 on success and errorno otherwise.
+ */
+int mtk_register_reset_controller_with_dev(struct device *dev,
+					   const struct mtk_clk_rst_desc *desc);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index bfe36bd41339..5016682e47c8 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -1657,35 +1657,6 @@ static struct clk_regmap *const sm1_clk_regmaps[] = {
 	&sm1_sysclk_b_en,
 };
 
-static int devm_clk_get_enable(struct device *dev, char *id)
-{
-	struct clk *clk;
-	int ret;
-
-	clk = devm_clk_get(dev, id);
-	if (IS_ERR(clk)) {
-		ret = PTR_ERR(clk);
-		dev_err_probe(dev, ret, "failed to get %s", id);
-		return ret;
-	}
-
-	ret = clk_prepare_enable(clk);
-	if (ret) {
-		dev_err(dev, "failed to enable %s", id);
-		return ret;
-	}
-
-	ret = devm_add_action_or_reset(dev,
-				       (void(*)(void *))clk_disable_unprepare,
-				       clk);
-	if (ret) {
-		dev_err(dev, "failed to add reset action on %s", id);
-		return ret;
-	}
-
-	return 0;
-}
-
 struct axg_audio_reset_data {
 	struct reset_controller_dev rstc;
 	struct regmap *map;
@@ -1787,6 +1758,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
 	struct regmap *map;
 	void __iomem *regs;
 	struct clk_hw *hw;
+	struct clk *clk;
 	int ret, i;
 
 	data = of_device_get_match_data(dev);
@@ -1804,9 +1776,9 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
 	}
 
 	/* Get the mandatory peripheral clock */
-	ret = devm_clk_get_enable(dev, "pclk");
-	if (ret)
-		return ret;
+	clk = devm_clk_get_enabled(dev, "pclk");
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
 
 	ret = device_reset(dev);
 	if (ret) {
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
index fb294ada0b03..23c43a46604e 100644
--- a/drivers/clk/mmp/clk-apbc.c
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp APB clock operation source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
index b7ce8f52026e..9313428b083a 100644
--- a/drivers/clk/mmp/clk-apmu.c
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp AXI peripharal clock operation source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 48f592bd633d..1b90867b60c4 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp factor clock operation source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
index 1755916ddef2..350eeb3e9e25 100644
--- a/drivers/clk/mmp/clk-gate.c
+++ b/drivers/clk/mmp/clk-gate.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp gate clock operation source file
  *
  * Copyright (C) 2014 Marvell
  * Chao Xie <chao.xie@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index 7a351ec65564..454d131f475e 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp mix(div and mux) clock operation source file
  *
  * Copyright (C) 2014 Marvell
  * Chao Xie <chao.xie@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index 7460031714da..aabacfa10158 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp2 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index 50a780274ba0..bcf60f43aa13 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * mmp2 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
  * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/module.h>
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index f110c02e83cb..48dfb18b490e 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * pxa168 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/module.h>
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c
index 998fc4207b0e..2508a0d795f8 100644
--- a/drivers/clk/mmp/clk-of-pxa1928.c
+++ b/drivers/clk/mmp/clk-of-pxa1928.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * pxa1928 clock framework source file
  *
@@ -7,10 +8,6 @@
  * Based on drivers/clk/mmp/clk-of-mmp2.c:
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 #include <linux/kernel.h>
 #include <linux/io.h>
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
index 1dcabe95cb67..4d15bac987eb 100644
--- a/drivers/clk/mmp/clk-of-pxa910.c
+++ b/drivers/clk/mmp/clk-of-pxa910.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * pxa910 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/module.h>
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index b351039cac09..8a9b8fb3a465 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * pxa168 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index f254ceff3ea7..9fcd76316d7e 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * pxa910 clock framework source file
  *
  * Copyright (C) 2012 Marvell
  * Chao Xie <xiechao.mail@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
index f2e171a01fb4..ddb28b38f549 100644
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)
  *
  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index c23ac463ab0f..f253ef1996b1 100644
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)
  *
  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/nxp/clk-lpc18xx-creg.c b/drivers/clk/nxp/clk-lpc18xx-creg.c
index c6e802e7e6ec..3d3982e9c661 100644
--- a/drivers/clk/nxp/clk-lpc18xx-creg.c
+++ b/drivers/clk/nxp/clk-lpc18xx-creg.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)
  *
  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c
index cfed11c659d9..f45c2c45808b 100644
--- a/drivers/clk/renesas/clk-r8a73a4.c
+++ b/drivers/clk/renesas/clk-r8a73a4.c
@@ -18,7 +18,6 @@
 struct r8a73a4_cpg {
 	struct clk_onecell_data data;
 	spinlock_t lock;
-	void __iomem *reg;
 };
 
 #define CPG_CKSCR	0xc0
@@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = {
 
 static struct clk * __init
 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
-			     const char *name)
+			   void __iomem *base, const char *name)
 {
 	const struct clk_div_table *table = NULL;
 	const char *parent_name;
@@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 
 
 	if (!strcmp(name, "main")) {
-		u32 ckscr = readl(cpg->reg + CPG_CKSCR);
+		u32 ckscr = readl(base + CPG_CKSCR);
 
 		switch ((ckscr >> 28) & 3) {
 		case 0:	/* extal1 */
@@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 		 * clock implementation and we currently have no need to change
 		 * the multiplier value.
 		 */
-		u32 value = readl(cpg->reg + CPG_PLL0CR);
+		u32 value = readl(base + CPG_PLL0CR);
 
 		parent_name = "main";
 		mult = ((value >> 24) & 0x7f) + 1;
 		if (value & BIT(20))
 			div = 2;
 	} else if (!strcmp(name, "pll1")) {
-		u32 value = readl(cpg->reg + CPG_PLL1CR);
+		u32 value = readl(base + CPG_PLL1CR);
 
 		parent_name = "main";
 		/* XXX: enable bit? */
@@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 		default:
 			return ERR_PTR(-EINVAL);
 		}
-		value = readl(cpg->reg + cr);
+		value = readl(base + cr);
 		switch ((value >> 5) & 7) {
 		case 0:
 			parent_name = "main";
@@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 			shift = 0;
 		}
 		div *= 32;
-		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
+		mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
 	} else {
 		struct div4_clk *c;
 
@@ -181,7 +180,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 						 mult, div);
 	} else {
 		return clk_register_divider_table(NULL, name, parent_name, 0,
-						  cpg->reg + reg, shift, 4, 0,
+						  base + reg, shift, 4, 0,
 						  table, &cpg->lock);
 	}
 }
@@ -189,6 +188,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
 {
 	struct r8a73a4_cpg *cpg;
+	void __iomem *base;
 	struct clk **clks;
 	unsigned int i;
 	int num_clks;
@@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
 	cpg->data.clks = clks;
 	cpg->data.clk_num = num_clks;
 
-	cpg->reg = of_iomap(np, 0);
-	if (WARN_ON(cpg->reg == NULL))
+	base = of_iomap(np, 0);
+	if (WARN_ON(base == NULL))
 		return;
 
 	for (i = 0; i < num_clks; ++i) {
@@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
 		of_property_read_string_index(np, "clock-output-names", i,
 					      &name);
 
-		clk = r8a73a4_cpg_register_clock(np, cpg, name);
+		clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
index d8190f007a81..3ee3f57e4e9a 100644
--- a/drivers/clk/renesas/clk-r8a7740.c
+++ b/drivers/clk/renesas/clk-r8a7740.c
@@ -18,7 +18,6 @@
 struct r8a7740_cpg {
 	struct clk_onecell_data data;
 	spinlock_t lock;
-	void __iomem *reg;
 };
 
 #define CPG_FRQCRA	0x00
@@ -61,7 +60,7 @@ static u32 cpg_mode __initdata;
 
 static struct clk * __init
 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
-			     const char *name)
+			   void __iomem *base, const char *name)
 {
 	const struct clk_div_table *table = NULL;
 	const char *parent_name;
@@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
 		 * clock implementation and we currently have no need to change
 		 * the multiplier value.
 		 */
-		u32 value = readl(cpg->reg + CPG_FRQCRC);
+		u32 value = readl(base + CPG_FRQCRC);
 		parent_name = "system";
 		mult = ((value >> 24) & 0x7f) + 1;
 	} else if (!strcmp(name, "pllc1")) {
-		u32 value = readl(cpg->reg + CPG_FRQCRA);
+		u32 value = readl(base + CPG_FRQCRA);
 		parent_name = "system";
 		mult = ((value >> 24) & 0x7f) + 1;
 		div = 2;
 	} else if (!strcmp(name, "pllc2")) {
-		u32 value = readl(cpg->reg + CPG_PLLC2CR);
+		u32 value = readl(base + CPG_PLLC2CR);
 		parent_name = "system";
 		mult = ((value >> 24) & 0x3f) + 1;
 	} else if (!strcmp(name, "usb24s")) {
-		u32 value = readl(cpg->reg + CPG_USBCKCR);
+		u32 value = readl(base + CPG_USBCKCR);
 		if (value & BIT(7))
 			/* extal2 */
 			parent_name = of_clk_get_parent_name(np, 1);
@@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
 						 mult, div);
 	} else {
 		return clk_register_divider_table(NULL, name, parent_name, 0,
-						  cpg->reg + reg, shift, 4, 0,
+						  base + reg, shift, 4, 0,
 						  table, &cpg->lock);
 	}
 }
@@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
 static void __init r8a7740_cpg_clocks_init(struct device_node *np)
 {
 	struct r8a7740_cpg *cpg;
+	void __iomem *base;
 	struct clk **clks;
 	unsigned int i;
 	int num_clks;
@@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
 	cpg->data.clks = clks;
 	cpg->data.clk_num = num_clks;
 
-	cpg->reg = of_iomap(np, 0);
-	if (WARN_ON(cpg->reg == NULL))
+	base = of_iomap(np, 0);
+	if (WARN_ON(base == NULL))
 		return;
 
 	for (i = 0; i < num_clks; ++i) {
@@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
 		of_property_read_string_index(np, "clock-output-names", i,
 					      &name);
 
-		clk = r8a7740_cpg_register_clock(np, cpg, name);
+		clk = r8a7740_cpg_register_clock(np, cpg, base, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
diff --git a/drivers/clk/renesas/clk-r8a7778.c b/drivers/clk/renesas/clk-r8a7778.c
index 3ccc53685bdd..797556259370 100644
--- a/drivers/clk/renesas/clk-r8a7778.c
+++ b/drivers/clk/renesas/clk-r8a7778.c
@@ -11,12 +11,6 @@
 #include <linux/slab.h>
 #include <linux/soc/renesas/rcar-rst.h>
 
-struct r8a7778_cpg {
-	struct clk_onecell_data data;
-	spinlock_t lock;
-	void __iomem *reg;
-};
-
 /* PLL multipliers per bits 11, 12, and 18 of MODEMR */
 static const struct {
 	unsigned long plla_mult;
@@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata;
 static u32 cpg_mode_divs __initdata;
 
 static struct clk * __init
-r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
-			     const char *name)
+r8a7778_cpg_register_clock(struct device_node *np, const char *name)
 {
 	if (!strcmp(name, "plla")) {
 		return clk_register_fixed_factor(NULL, "plla",
@@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
 
 static void __init r8a7778_cpg_clocks_init(struct device_node *np)
 {
-	struct r8a7778_cpg *cpg;
+	struct clk_onecell_data *data;
 	struct clk **clks;
 	unsigned int i;
 	int num_clks;
@@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
 		return;
 	}
 
-	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
-	if (cpg == NULL || clks == NULL) {
+	if (data == NULL || clks == NULL) {
 		/* We're leaking memory on purpose, there's no point in cleaning
 		 * up as the system won't boot anyway.
 		 */
 		return;
 	}
 
-	spin_lock_init(&cpg->lock);
-
-	cpg->data.clks = clks;
-	cpg->data.clk_num = num_clks;
-
-	cpg->reg = of_iomap(np, 0);
-	if (WARN_ON(cpg->reg == NULL))
-		return;
+	data->clks = clks;
+	data->clk_num = num_clks;
 
 	for (i = 0; i < num_clks; ++i) {
 		const char *name;
@@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
 		of_property_read_string_index(np, "clock-output-names", i,
 					      &name);
 
-		clk = r8a7778_cpg_register_clock(np, cpg, name);
+		clk = r8a7778_cpg_register_clock(np, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
 		else
-			cpg->data.clks[i] = clk;
+			data->clks[i] = clk;
 	}
 
-	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+	of_clk_add_provider(np, of_clk_src_onecell_get, data);
 
 	cpg_mstp_add_clk_domain(np);
 }
diff --git a/drivers/clk/renesas/clk-r8a7779.c b/drivers/clk/renesas/clk-r8a7779.c
index 9f3b5522eef5..9a2fea8cf4d7 100644
--- a/drivers/clk/renesas/clk-r8a7779.c
+++ b/drivers/clk/renesas/clk-r8a7779.c
@@ -21,12 +21,6 @@
 
 #define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
 
-struct r8a7779_cpg {
-	struct clk_onecell_data data;
-	spinlock_t lock;
-	void __iomem *reg;
-};
-
 /* -----------------------------------------------------------------------------
  * CPG Clock Data
  */
@@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
  */
 
 static struct clk * __init
-r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+r8a7779_cpg_register_clock(struct device_node *np,
 			   const struct cpg_clk_config *config,
 			   unsigned int plla_mult, const char *name)
 {
@@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
 static void __init r8a7779_cpg_clocks_init(struct device_node *np)
 {
 	const struct cpg_clk_config *config;
-	struct r8a7779_cpg *cpg;
+	struct clk_onecell_data *data;
 	struct clk **clks;
 	unsigned int i, plla_mult;
 	int num_clks;
@@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
 		return;
 	}
 
-	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
-	if (cpg == NULL || clks == NULL) {
+	if (data == NULL || clks == NULL) {
 		/* We're leaking memory on purpose, there's no point in cleaning
 		 * up as the system won't boot anyway.
 		 */
 		return;
 	}
 
-	spin_lock_init(&cpg->lock);
-
-	cpg->data.clks = clks;
-	cpg->data.clk_num = num_clks;
+	data->clks = clks;
+	data->clk_num = num_clks;
 
 	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
 	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
@@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
 		of_property_read_string_index(np, "clock-output-names", i,
 					      &name);
 
-		clk = r8a7779_cpg_register_clock(np, cpg, config,
-						 plla_mult, name);
+		clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
 		else
-			cpg->data.clks[i] = clk;
+			data->clks[i] = clk;
 	}
 
-	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+	of_clk_add_provider(np, of_clk_src_onecell_get, data);
 
 	cpg_mstp_add_clk_domain(np);
 }
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
index 7b703f14e20b..e770f09a27ed 100644
--- a/drivers/clk/renesas/clk-rz.c
+++ b/drivers/clk/renesas/clk-rz.c
@@ -15,11 +15,6 @@
 #include <linux/of_address.h>
 #include <linux/slab.h>
 
-struct rz_cpg {
-	struct clk_onecell_data data;
-	void __iomem *reg;
-};
-
 #define CPG_FRQCR	0x10
 #define CPG_FRQCR2	0x14
 
@@ -49,7 +44,8 @@ static u16 __init rz_cpg_read_mode_pins(void)
 }
 
 static struct clk * __init
-rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
+rz_cpg_register_clock(struct device_node *np, void __iomem *base,
+		      const char *name)
 {
 	u32 val;
 	unsigned mult;
@@ -65,7 +61,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
 	}
 
 	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
-	if (!cpg->reg)
+	if (!base)
 		return ERR_PTR(-ENXIO);
 
 	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
@@ -73,9 +69,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
 	 * let them run at fixed current speed and implement the details later.
 	 */
 	if (strcmp(name, "i") == 0)
-		val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
+		val = (readl(base + CPG_FRQCR) >> 8) & 3;
 	else if (strcmp(name, "g") == 0)
-		val = readl(cpg->reg + CPG_FRQCR2) & 3;
+		val = readl(base + CPG_FRQCR2) & 3;
 	else
 		return ERR_PTR(-EINVAL);
 
@@ -85,8 +81,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
 
 static void __init rz_cpg_clocks_init(struct device_node *np)
 {
-	struct rz_cpg *cpg;
+	struct clk_onecell_data *data;
 	struct clk **clks;
+	void __iomem *base;
 	unsigned i;
 	int num_clks;
 
@@ -94,14 +91,14 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
 	if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
 		return;
 
-	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
-	BUG_ON(!cpg || !clks);
+	BUG_ON(!data || !clks);
 
-	cpg->data.clks = clks;
-	cpg->data.clk_num = num_clks;
+	data->clks = clks;
+	data->clk_num = num_clks;
 
-	cpg->reg = of_iomap(np, 0);
+	base = of_iomap(np, 0);
 
 	for (i = 0; i < num_clks; ++i) {
 		const char *name;
@@ -109,15 +106,15 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
 
 		of_property_read_string_index(np, "clock-output-names", i, &name);
 
-		clk = rz_cpg_register_clock(np, cpg, name);
+		clk = rz_cpg_register_clock(np, base, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
 		else
-			cpg->data.clks[i] = clk;
+			data->clks[i] = clk;
 	}
 
-	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+	of_clk_add_provider(np, of_clk_src_onecell_get, data);
 
 	cpg_mstp_add_clk_domain(np);
 }
diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
index 4146c1d717b9..8c51090f13e1 100644
--- a/drivers/clk/renesas/clk-sh73a0.c
+++ b/drivers/clk/renesas/clk-sh73a0.c
@@ -18,7 +18,6 @@
 struct sh73a0_cpg {
 	struct clk_onecell_data data;
 	spinlock_t lock;
-	void __iomem *reg;
 };
 
 #define CPG_FRQCRA	0x00
@@ -73,7 +72,7 @@ static const struct clk_div_table z_div_table[] = {
 
 static struct clk * __init
 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
-			     const char *name)
+			  void __iomem *base, const char *name)
 {
 	const struct clk_div_table *table = NULL;
 	unsigned int shift, reg, width;
@@ -83,12 +82,12 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
 
 	if (!strcmp(name, "main")) {
 		/* extal1, extal1_div2, extal2, extal2_div2 */
-		u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
+		u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;
 
 		parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
 		div = (parent_idx & 1) + 1;
 	} else if (!strncmp(name, "pll", 3)) {
-		void __iomem *enable_reg = cpg->reg;
+		void __iomem *enable_reg = base;
 		u32 enable_bit = name[3] - '0';
 
 		parent_name = "main";
@@ -108,7 +107,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
 		default:
 			return ERR_PTR(-EINVAL);
 		}
-		if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
+		if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
 			mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
 			/* handle CFG bit for PLL1 and PLL2 */
 			if (enable_bit == 1 || enable_bit == 2)
@@ -117,7 +116,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
 		}
 	} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
 		u32 phy_no = name[3] - '0';
-		void __iomem *dsi_reg = cpg->reg +
+		void __iomem *dsi_reg = base +
 			(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
 
 		parent_name = phy_no ? "dsi1pck" : "dsi0pck";
@@ -154,7 +153,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
 						 mult, div);
 	} else {
 		return clk_register_divider_table(NULL, name, parent_name, 0,
-						  cpg->reg + reg, shift, width, 0,
+						  base + reg, shift, width, 0,
 						  table, &cpg->lock);
 	}
 }
@@ -162,6 +161,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
 static void __init sh73a0_cpg_clocks_init(struct device_node *np)
 {
 	struct sh73a0_cpg *cpg;
+	void __iomem *base;
 	struct clk **clks;
 	unsigned int i;
 	int num_clks;
@@ -186,14 +186,14 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
 	cpg->data.clks = clks;
 	cpg->data.clk_num = num_clks;
 
-	cpg->reg = of_iomap(np, 0);
-	if (WARN_ON(cpg->reg == NULL))
+	base = of_iomap(np, 0);
+	if (WARN_ON(base == NULL))
 		return;
 
 	/* Set SDHI clocks to a known state */
-	writel(0x108, cpg->reg + CPG_SD0CKCR);
-	writel(0x108, cpg->reg + CPG_SD1CKCR);
-	writel(0x108, cpg->reg + CPG_SD2CKCR);
+	writel(0x108, base + CPG_SD0CKCR);
+	writel(0x108, base + CPG_SD1CKCR);
+	writel(0x108, base + CPG_SD2CKCR);
 
 	for (i = 0; i < num_clks; ++i) {
 		const char *name;
@@ -202,7 +202,7 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
 		of_property_read_string_index(np, "clock-output-names", i,
 					      &name);
 
-		clk = sh73a0_cpg_register_clock(np, cpg, name);
+		clk = sh73a0_cpg_register_clock(np, cpg, base, name);
 		if (IS_ERR(clk))
 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 			       __func__, np, name, PTR_ERR(clk));
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index c17ebe6b5992..cd80b6084ece 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -77,6 +77,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
 	DEF_BASE(".rpcsrc",	CLK_RPCSRC,	CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
 
 	/* Core Clock Outputs */
+	DEF_GEN4_Z("z0",	R8A779F0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 0),
+	DEF_GEN4_Z("z1",	R8A779F0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 8),
 	DEF_FIXED("s0d2",	R8A779F0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779F0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779F0_CLK_S0D4,	CLK_S0,		4, 1),
@@ -118,20 +120,28 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
+	DEF_MOD("hscif0",	514,	R8A779F0_CLK_S0D3),
+	DEF_MOD("hscif1",	515,	R8A779F0_CLK_S0D3),
+	DEF_MOD("hscif2",	516,	R8A779F0_CLK_S0D3),
+	DEF_MOD("hscif3",	517,	R8A779F0_CLK_S0D3),
 	DEF_MOD("i2c0",		518,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c1",		519,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c2",		520,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c3",		521,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c4",		522,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c5",		523,	R8A779F0_CLK_S0D6_PER),
+	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),
+	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),
 	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),
 	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),
 	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),
 	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),
+	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),
 	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),
 	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),
 	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),
 	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),
+	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),
 	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),
 };
 
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 35ffc462af1a..1488c9d6e639 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -51,11 +51,9 @@ struct r9a06g032_clkdesc {
 		struct {
 			u16 div, mul;
 		};
-		unsigned int factor;
-		unsigned int frequency;
 		/* for dual gate */
 		struct {
-			uint16_t group : 1, index: 3;
+			uint16_t group : 1;
 			u16 sel, g1, r1, g2, r2;
 		} dual;
 	};
@@ -85,10 +83,10 @@ struct r9a06g032_clkdesc {
 		.source = 1 + R9A06G032_##_src, .name = _n, \
 		.reg = _reg, .div_min = _min, .div_max = _max, \
 		.div_table = { __VA_ARGS__ } }
-#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
+#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
 	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
 		.source = 1 + R9A06G032_##_src, .name = _n, \
-		.dual = { .group = _g, .index = _gi, \
+		.dual = { .group = _g, \
 			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
 
 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
@@ -290,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.name = "uart_group_012",
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_UART,
-		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
-		.dual.sel = ((0xec / 4) << 5) | 24,
+		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
+		.dual.sel = ((0x34 / 4) << 5) | 30,
 		.dual.group = 0,
 	},
 	{
@@ -299,18 +297,18 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.name = "uart_group_34567",
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_P2_PG,
-		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
-		.dual.sel = ((0x34 / 4) << 5) | 30,
+		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+		.dual.sel = ((0xec / 4) << 5) | 24,
 		.dual.group = 1,
 	},
-	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
-	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
-	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
-	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
-	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
-	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
-	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
-	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
+	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
+	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
+	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
+	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
+	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
+	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
+	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
+	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
 };
 
 struct r9a06g032_priv {
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b288897852c7..fd7c4eecd398 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-	struct rzg2l_mod_clk common[71];
+	struct rzg2l_mod_clk common[76];
 #ifdef CONFIG_CLK_R9A07G054
 	struct rzg2l_mod_clk drp[0];
 #endif
@@ -204,6 +204,16 @@ static const struct {
 					0x534, 1),
 		DEF_MOD("ostm2_pclk",	R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
 					0x534, 2),
+		DEF_MOD("gpt_pclk",	R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
+					0x540, 0),
+		DEF_MOD("poeg_a_clkp",	R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
+					0x544, 0),
+		DEF_MOD("poeg_b_clkp",	R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
+					0x544, 1),
+		DEF_MOD("poeg_c_clkp",	R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
+					0x544, 2),
+		DEF_MOD("poeg_d_clkp",	R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
+					0x544, 3),
 		DEF_MOD("wdt0_pclk",	R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
 					0x548, 0),
 		DEF_MOD("wdt0_clk",	R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -346,6 +356,11 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
 	DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
 	DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+	DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
+	DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
+	DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
+	DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
+	DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
 	DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
 	DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
 	DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index 40693bb85b80..b21915cf6648 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -126,19 +126,24 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
 };
 
 static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
+	DEF_MOD("pfc",		R9A09G011_PFC_PCLK,	 CLK_MAIN,     0x400, 2),
 	DEF_MOD("gic",		R9A09G011_GIC_CLK,	 CLK_SEL_B_D2, 0x400, 5),
 	DEF_COUPLED("eth_axi",	R9A09G011_ETH0_CLK_AXI,	 CLK_PLL2_200, 0x40c, 8),
 	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),
 	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
 	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),
+	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),
+	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),
 	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),
 	DEF_MOD("urt0_clk",	R9A09G011_URT0_CLK,	 CLK_SEL_W0,   0x438, 5),
 	DEF_MOD("ca53",		R9A09G011_CA53_CLK,	 CLK_DIV_A,    0x448, 0),
 };
 
 static const struct rzg2l_reset r9a09g011_resets[] = {
+	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),
 	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),
 	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),
+	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),
 };
 
 static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e2999ab2b53c..3ff6ecd61756 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
 	s8 monbit = info->resets[id].monbit;
 
 	if (info->has_clk_mon_regs) {
-		return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+		return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
 	} else if (monbit >= 0) {
 		u32 monbitmask = BIT(monbit);
 
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
index 906410413bc1..637938e804f8 100644
--- a/drivers/clk/spear/clk-aux-synth.c
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * Auxiliary Synthesizer clock implementation
  */
 
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index f5be02205ac6..2380df293a2c 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * Fractional Synthesizer clock implementation
  */
 
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
index 6ed406d943ba..4ef747c2abbb 100644
--- a/drivers/clk/spear/clk-gpt-synth.c
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * General Purpose Timer Synthesizer clock implementation
  */
 
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
index fed194169666..348eeab0a906 100644
--- a/drivers/clk/spear/clk-vco-pll.c
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * VCO-PLL clock implementation
  */
 
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
index 157fe099ea6a..50847cccdf58 100644
--- a/drivers/clk/spear/clk.c
+++ b/drivers/clk/spear/clk.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * SPEAr clk - Common routines
  */
 
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
index af0e25f496c1..3d580d1bdadd 100644
--- a/drivers/clk/spear/clk.h
+++ b/drivers/clk/spear/clk.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Clock framework definitions for SPEAr platform
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __SPEAR_CLK_H
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 8c8974866789..9d5959a4251a 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear13xx/spear1310_clock.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clkdev.h>
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index c0dc94355c87..8b51229d0471 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * arch/arm/mach-spear13xx/spear1340_clock.c
  *
@@ -5,10 +6,6 @@
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clkdev.h>
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index c403c66b6583..41717ff707f6 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * SPEAr3xx machines clock framework source file
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 47810be7f15c..490701ac9e93 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * SPEAr6xx machines clock framework source file
  *
  * Copyright (C) 2012 ST Microelectronics
  * Viresh Kumar <vireshk@kernel.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/clkdev.h>
diff --git a/drivers/clk/stm32/reset-stm32.c b/drivers/clk/stm32/reset-stm32.c
index 040870130e4b..e89381528af9 100644
--- a/drivers/clk/stm32/reset-stm32.c
+++ b/drivers/clk/stm32/reset-stm32.c
@@ -111,6 +111,7 @@ int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
 	if (!reset_data)
 		return -ENOMEM;
 
+	spin_lock_init(&reset_data->lock);
 	reset_data->membase = base;
 	reset_data->rcdev.owner = THIS_MODULE;
 	reset_data->rcdev.ops = &stm32_reset_ops;
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 29a8c710ae06..001582ea71ba 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -138,19 +138,9 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
 	&r_apb2_rsb_clk.common,
 	&r_apb1_ir_clk.common,
 	&r_apb1_w1_clk.common,
-	&ir_clk.common,
-	&w1_clk.common,
-};
-
-static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
-	&r_apb1_clk.common,
-	&r_apb2_clk.common,
-	&r_apb1_twd_clk.common,
-	&r_apb2_i2c_clk.common,
-	&r_apb2_rsb_clk.common,
-	&r_apb1_ir_clk.common,
 	&r_apb1_rtc_clk.common,
 	&ir_clk.common,
+	&w1_clk.common,
 };
 
 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
@@ -218,8 +208,8 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
-	.ccu_clks	= sun50i_h616_r_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+	.ccu_clks	= sun50i_h6_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_r_ccu_clks),
 
 	.hw_clks	= &sun50i_h616_r_hw_clks,
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index e7e3ddf4a227..2f6f02f00be2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -53,65 +53,26 @@ static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
 static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
 		   CLK_SET_RATE_PARENT);
 
-static struct ccu_common *sun8i_a83t_de2_clks[] = {
+static struct ccu_common *sun8i_de2_ccu_clks[] = {
 	&mixer0_clk.common,
 	&mixer1_clk.common,
 	&wb_clk.common,
-
-	&bus_mixer0_clk.common,
-	&bus_mixer1_clk.common,
-	&bus_wb_clk.common,
-
-	&mixer0_div_a83_clk.common,
-	&mixer1_div_a83_clk.common,
-	&wb_div_a83_clk.common,
-
-	&bus_rot_clk.common,
 	&rot_clk.common,
-	&rot_div_a83_clk.common,
-};
-
-static struct ccu_common *sun8i_h3_de2_clks[] = {
-	&mixer0_clk.common,
-	&mixer1_clk.common,
-	&wb_clk.common,
-
-	&bus_mixer0_clk.common,
-	&bus_mixer1_clk.common,
-	&bus_wb_clk.common,
-
-	&mixer0_div_clk.common,
-	&mixer1_div_clk.common,
-	&wb_div_clk.common,
-};
-
-static struct ccu_common *sun8i_v3s_de2_clks[] = {
-	&mixer0_clk.common,
-	&wb_clk.common,
-
-	&bus_mixer0_clk.common,
-	&bus_wb_clk.common,
-
-	&mixer0_div_clk.common,
-	&wb_div_clk.common,
-};
-
-static struct ccu_common *sun50i_a64_de2_clks[] = {
-	&mixer0_clk.common,
-	&mixer1_clk.common,
-	&wb_clk.common,
 
 	&bus_mixer0_clk.common,
 	&bus_mixer1_clk.common,
 	&bus_wb_clk.common,
+	&bus_rot_clk.common,
 
 	&mixer0_div_clk.common,
 	&mixer1_div_clk.common,
 	&wb_div_clk.common,
-
-	&bus_rot_clk.common,
-	&rot_clk.common,
 	&rot_div_clk.common,
+
+	&mixer0_div_a83_clk.common,
+	&mixer1_div_a83_clk.common,
+	&wb_div_a83_clk.common,
+	&rot_div_a83_clk.common,
 };
 
 static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
@@ -219,8 +180,8 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = {
 };
 
 static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
-	.ccu_clks	= sun8i_a83t_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun8i_a83t_de2_hw_clks,
 
@@ -229,8 +190,8 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
-	.ccu_clks	= sun8i_h3_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun8i_h3_de2_hw_clks,
 
@@ -239,8 +200,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
-	.ccu_clks	= sun50i_a64_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun50i_a64_de2_hw_clks,
 
@@ -249,8 +210,8 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
-	.ccu_clks	= sun8i_v3s_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun8i_v3s_de2_hw_clks,
 
@@ -259,8 +220,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
-	.ccu_clks	= sun50i_a64_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun50i_a64_de2_hw_clks,
 
@@ -269,8 +230,8 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
-	.ccu_clks	= sun8i_h3_de2_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
+	.ccu_clks	= sun8i_de2_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
 
 	.hw_clks	= &sun8i_h3_de2_hw_clks,
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index e058cf691aea..d3fcb983c17c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -562,6 +562,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
 	&bus_uart2_clk.common,
 	&bus_uart3_clk.common,
 	&bus_scr0_clk.common,
+	&bus_scr1_clk.common,
 	&bus_ephy_clk.common,
 	&bus_dbg_clk.common,
 	&ths_clk.common,
@@ -612,114 +613,6 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
 	&gpu_clk.common,
 };
 
-static struct ccu_common *sun50i_h5_ccu_clks[] = {
-	&pll_cpux_clk.common,
-	&pll_audio_base_clk.common,
-	&pll_video_clk.common,
-	&pll_ve_clk.common,
-	&pll_ddr_clk.common,
-	&pll_periph0_clk.common,
-	&pll_gpu_clk.common,
-	&pll_periph1_clk.common,
-	&pll_de_clk.common,
-	&cpux_clk.common,
-	&axi_clk.common,
-	&ahb1_clk.common,
-	&apb1_clk.common,
-	&apb2_clk.common,
-	&ahb2_clk.common,
-	&bus_ce_clk.common,
-	&bus_dma_clk.common,
-	&bus_mmc0_clk.common,
-	&bus_mmc1_clk.common,
-	&bus_mmc2_clk.common,
-	&bus_nand_clk.common,
-	&bus_dram_clk.common,
-	&bus_emac_clk.common,
-	&bus_ts_clk.common,
-	&bus_hstimer_clk.common,
-	&bus_spi0_clk.common,
-	&bus_spi1_clk.common,
-	&bus_otg_clk.common,
-	&bus_ehci0_clk.common,
-	&bus_ehci1_clk.common,
-	&bus_ehci2_clk.common,
-	&bus_ehci3_clk.common,
-	&bus_ohci0_clk.common,
-	&bus_ohci1_clk.common,
-	&bus_ohci2_clk.common,
-	&bus_ohci3_clk.common,
-	&bus_ve_clk.common,
-	&bus_tcon0_clk.common,
-	&bus_tcon1_clk.common,
-	&bus_deinterlace_clk.common,
-	&bus_csi_clk.common,
-	&bus_tve_clk.common,
-	&bus_hdmi_clk.common,
-	&bus_de_clk.common,
-	&bus_gpu_clk.common,
-	&bus_msgbox_clk.common,
-	&bus_spinlock_clk.common,
-	&bus_codec_clk.common,
-	&bus_spdif_clk.common,
-	&bus_pio_clk.common,
-	&bus_ths_clk.common,
-	&bus_i2s0_clk.common,
-	&bus_i2s1_clk.common,
-	&bus_i2s2_clk.common,
-	&bus_i2c0_clk.common,
-	&bus_i2c1_clk.common,
-	&bus_i2c2_clk.common,
-	&bus_uart0_clk.common,
-	&bus_uart1_clk.common,
-	&bus_uart2_clk.common,
-	&bus_uart3_clk.common,
-	&bus_scr0_clk.common,
-	&bus_scr1_clk.common,
-	&bus_ephy_clk.common,
-	&bus_dbg_clk.common,
-	&ths_clk.common,
-	&nand_clk.common,
-	&mmc0_clk.common,
-	&mmc1_clk.common,
-	&mmc2_clk.common,
-	&ts_clk.common,
-	&ce_clk.common,
-	&spi0_clk.common,
-	&spi1_clk.common,
-	&i2s0_clk.common,
-	&i2s1_clk.common,
-	&i2s2_clk.common,
-	&spdif_clk.common,
-	&usb_phy0_clk.common,
-	&usb_phy1_clk.common,
-	&usb_phy2_clk.common,
-	&usb_phy3_clk.common,
-	&usb_ohci0_clk.common,
-	&usb_ohci1_clk.common,
-	&usb_ohci2_clk.common,
-	&usb_ohci3_clk.common,
-	&dram_clk.common,
-	&dram_ve_clk.common,
-	&dram_csi_clk.common,
-	&dram_deinterlace_clk.common,
-	&dram_ts_clk.common,
-	&de_clk.common,
-	&tcon_clk.common,
-	&tve_clk.common,
-	&deinterlace_clk.common,
-	&csi_misc_clk.common,
-	&csi_sclk_clk.common,
-	&csi_mclk_clk.common,
-	&ve_clk.common,
-	&ac_dig_clk.common,
-	&avs_clk.common,
-	&hdmi_clk.common,
-	&hdmi_ddc_clk.common,
-	&mbus_clk.common,
-	&gpu_clk.common,
-};
-
 static const struct clk_hw *clk_parent_pll_audio[] = {
 	&pll_audio_base_clk.common.hw
 };
@@ -1116,8 +1009,8 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
-	.ccu_clks	= sun50i_h5_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_h5_ccu_clks),
+	.ccu_clks	= sun8i_h3_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_ccu_clks),
 
 	.hw_clks	= &sun50i_h5_hw_clks,
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 5b7fab832a52..4221649b311f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -114,32 +114,7 @@ static struct ccu_mp a83t_ir_clk = {
 	},
 };
 
-static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
-	&ar100_clk.common,
-	&apb0_clk.common,
-	&apb0_pio_clk.common,
-	&apb0_ir_clk.common,
-	&apb0_timer_clk.common,
-	&apb0_rsb_clk.common,
-	&apb0_uart_clk.common,
-	&apb0_i2c_clk.common,
-	&apb0_twd_clk.common,
-	&a83t_ir_clk.common,
-};
-
-static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
-	&ar100_clk.common,
-	&apb0_clk.common,
-	&apb0_pio_clk.common,
-	&apb0_ir_clk.common,
-	&apb0_timer_clk.common,
-	&apb0_uart_clk.common,
-	&apb0_i2c_clk.common,
-	&apb0_twd_clk.common,
-	&ir_clk.common,
-};
-
-static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
+static struct ccu_common *sun8i_r_ccu_clks[] = {
 	&ar100_clk.common,
 	&apb0_clk.common,
 	&apb0_pio_clk.common,
@@ -150,6 +125,7 @@ static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
 	&apb0_i2c_clk.common,
 	&apb0_twd_clk.common,
 	&ir_clk.common,
+	&a83t_ir_clk.common,
 };
 
 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
@@ -226,8 +202,8 @@ static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
 };
 
 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
-	.ccu_clks	= sun8i_a83t_r_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
+	.ccu_clks	= sun8i_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),
 
 	.hw_clks	= &sun8i_a83t_r_hw_clks,
 
@@ -236,8 +212,8 @@ static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
 };
 
 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
-	.ccu_clks	= sun8i_h3_r_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_r_ccu_clks),
+	.ccu_clks	= sun8i_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),
 
 	.hw_clks	= &sun8i_h3_r_hw_clks,
 
@@ -246,8 +222,8 @@ static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
-	.ccu_clks	= sun50i_a64_r_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_r_ccu_clks),
+	.ccu_clks	= sun8i_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_r_ccu_clks),
 
 	.hw_clks	= &sun50i_a64_r_hw_clks,
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 87f87d6ea3ad..fbb3529f0d3e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -421,6 +421,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
 	&bus_de_clk.common,
 	&bus_codec_clk.common,
 	&bus_pio_clk.common,
+	&bus_i2s0_clk.common,
 	&bus_i2c0_clk.common,
 	&bus_i2c1_clk.common,
 	&bus_uart0_clk.common,
@@ -439,6 +440,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
 	&mmc2_output_clk.common,
 	&ce_clk.common,
 	&spi0_clk.common,
+	&i2s0_clk.common,
 	&usb_phy0_clk.common,
 	&usb_ohci0_clk.common,
 	&dram_clk.common,
@@ -463,80 +465,6 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
 	&pll_audio_base_clk.common.hw
 };
 
-static struct ccu_common *sun8i_v3_ccu_clks[] = {
-	&pll_cpu_clk.common,
-	&pll_audio_base_clk.common,
-	&pll_video_clk.common,
-	&pll_ve_clk.common,
-	&pll_ddr0_clk.common,
-	&pll_periph0_clk.common,
-	&pll_isp_clk.common,
-	&pll_periph1_clk.common,
-	&pll_ddr1_clk.common,
-	&cpu_clk.common,
-	&axi_clk.common,
-	&ahb1_clk.common,
-	&apb1_clk.common,
-	&apb2_clk.common,
-	&ahb2_clk.common,
-	&bus_ce_clk.common,
-	&bus_dma_clk.common,
-	&bus_mmc0_clk.common,
-	&bus_mmc1_clk.common,
-	&bus_mmc2_clk.common,
-	&bus_dram_clk.common,
-	&bus_emac_clk.common,
-	&bus_hstimer_clk.common,
-	&bus_spi0_clk.common,
-	&bus_otg_clk.common,
-	&bus_ehci0_clk.common,
-	&bus_ohci0_clk.common,
-	&bus_ve_clk.common,
-	&bus_tcon0_clk.common,
-	&bus_csi_clk.common,
-	&bus_de_clk.common,
-	&bus_codec_clk.common,
-	&bus_pio_clk.common,
-	&bus_i2s0_clk.common,
-	&bus_i2c0_clk.common,
-	&bus_i2c1_clk.common,
-	&bus_uart0_clk.common,
-	&bus_uart1_clk.common,
-	&bus_uart2_clk.common,
-	&bus_ephy_clk.common,
-	&bus_dbg_clk.common,
-	&mmc0_clk.common,
-	&mmc0_sample_clk.common,
-	&mmc0_output_clk.common,
-	&mmc1_clk.common,
-	&mmc1_sample_clk.common,
-	&mmc1_output_clk.common,
-	&mmc2_clk.common,
-	&mmc2_sample_clk.common,
-	&mmc2_output_clk.common,
-	&ce_clk.common,
-	&spi0_clk.common,
-	&i2s0_clk.common,
-	&usb_phy0_clk.common,
-	&usb_ohci0_clk.common,
-	&dram_clk.common,
-	&dram_ve_clk.common,
-	&dram_csi_clk.common,
-	&dram_ohci_clk.common,
-	&dram_ehci_clk.common,
-	&de_clk.common,
-	&tcon_clk.common,
-	&csi_misc_clk.common,
-	&csi0_mclk_clk.common,
-	&csi1_sclk_clk.common,
-	&csi1_mclk_clk.common,
-	&ve_clk.common,
-	&ac_dig_clk.common,
-	&avs_clk.common,
-	&mbus_clk.common,
-	&mipi_csi_clk.common,
-};
-
 /* We hardcode the divider to 1 for SDM support */
 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
 			    clk_parent_pll_audio,
@@ -798,8 +726,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
 };
 
 static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
-	.ccu_clks	= sun8i_v3_ccu_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3_ccu_clks),
+	.ccu_clks	= sun8i_v3s_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_ccu_clks),
 
 	.hw_clks	= &sun8i_v3_hw_clks,
 
diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c
index 962502ca7ff0..f5e7e2049241 100644
--- a/drivers/clk/ti/adpll.c
+++ b/drivers/clk/ti/adpll.c
@@ -1,13 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index e4db6b9a55c6..dd0709c9c249 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP APLL clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * J Keerthy <j-keerthy@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index d6e5f1511ace..27e6b9cb1881 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI clock autoidle support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/clk-2xxx.c b/drivers/clk/ti/clk-2xxx.c
index 657c4fe07a95..363c4fdbe01f 100644
--- a/drivers/clk/ti/clk-2xxx.c
+++ b/drivers/clk/ti/clk-2xxx.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP2 Clock init
  *
  * Copyright (C) 2013 Texas Instruments, Inc
  *     Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index b4d142adede4..85c50ea39e6d 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM33XX Clock init
  *
  * Copyright (C) 2013 Texas Instruments, Inc
  *     Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 8aa5f5793835..ae943ea63c6c 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP3 Clock init
  *
  * Copyright (C) 2013 Texas Instruments, Inc
  *     Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 2ff4ff3d95d5..f24f6eb2157a 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * AM43XX Clock init
  *
  * Copyright (C) 2013 Texas Instruments, Inc
  *     Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index d078e5d73ed9..868bc7af21b0 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
 };
 
 static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0018:26",
+	"abe-clkctrl:0018:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
 };
 
 static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0020:26",
+	"abe-clkctrl:0020:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
 };
 
 static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0028:26",
+	"abe-clkctrl:0028:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
 };
 
 static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0030:26",
+	"abe-clkctrl:0030:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
 };
 
 static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0038:26",
+	"abe-clkctrl:0038:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
 
 static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
 	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
-	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
+	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
 	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
-	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
-	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
-	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
-	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
-	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
-	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
-	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
-	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
-	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
-	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
+	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
+	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
+	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
+	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
+	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
+	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
+	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
+	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
+	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
 	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ 0 },
 };
@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
 
 static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
 	{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
-	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
+	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
 	{ 0 },
 };
 
@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
 };
 
 static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
-	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
+	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
 	{ 0 },
 };
 
@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
 };
 
 static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
-	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
+	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
 	{ 0 },
 };
 
@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
 };
 
 static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
-	"l3_init_cm:clk:0038:24",
+	"l3-init-clkctrl:0038:24",
 	NULL,
 };
 
 static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
-	"l3_init_cm:clk:0038:25",
+	"l3-init-clkctrl:0038:25",
 	NULL,
 };
 
@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
 };
 
 static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
-	"l3_init_cm:clk:0040:24",
+	"l3-init-clkctrl:0040:24",
 	NULL,
 };
 
@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
 };
 
 static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
-	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
-	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
-	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
+	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
+	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
+	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
 	{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
 	{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
 	{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
 	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
-	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
+	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
 	{ 0 },
 };
 
@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
 };
 
 static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
-	"l4_per_cm:clk:00c0:26",
+	"l4-per-clkctrl:00c0:26",
 	"pad_clks_ck",
 	NULL,
 };
@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
 };
 
 static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
-	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
-	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
-	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
-	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
-	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
-	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
+	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
+	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
+	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
+	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
+	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
+	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
 	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
 	{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
 	{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
 	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
-	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
+	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
 	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
-	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
+	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
 	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
 	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
 	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
-	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
+	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
 	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
 	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ 0 },
@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
 };
 
 static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
-	"emu_sys_cm:clk:0000:22",
+	"emu-sys-clkctrl:0000:22",
 	NULL,
 };
 
@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
 };
 
 static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
-	"emu_sys_cm:clk:0000:20",
+	"emu-sys-clkctrl:0000:20",
 	NULL,
 };
 
@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = {
 	 * hwmod support. Once hwmod is removed, these can be removed
 	 * also.
 	 */
-	DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
-	DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
-	DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
-	DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
-	DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
-	DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
-	DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
-	DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
-	DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
-	DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
-	DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
-	DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
-	DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
-	DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
-	DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
-	DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
-	DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
-	DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
-	DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
-	DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
-	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
-	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
-	DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
-	DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
-	DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
-	DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
-	DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
-	DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
-	DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
-	DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
-	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
-	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
-	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
-	DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
-	DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
-	DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
-	DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
-	DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
-	DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
-	DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
-	DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
-	DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
-	DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
-	DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
-	DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
-	DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
-	DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
-	DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
-	DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
-	DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
-	DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
-	DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
-	DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
-	DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
-	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
-	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
-	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
-	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
-	DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
-	DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
-	DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
+	DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
+	DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
+	DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
+	DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
+	DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
+	DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
+	DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
+	DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
+	DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
+	DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
+	DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
+	DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
+	DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
+	DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
+	DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
+	DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
+	DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
+	DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
+	DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
+	DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
+	DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
+	DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
+	DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
+	DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
+	DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
+	DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
+	DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
+	DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
+	DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
+	DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
+	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
+	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
+	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
+	DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
+	DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
+	DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
+	DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
+	DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
+	DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
+	DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
+	DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
+	DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
+	DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
+	DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
+	DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
+	DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
+	DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
+	DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
+	DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
+	DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
+	DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
+	DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
+	DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
+	DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
+	DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
+	DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
+	DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
 	{ .node_name = NULL },
 };
 
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 90e0a9ea6351..b4aff76eb373 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
 };
 
 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0018:26",
+	"abe-clkctrl:0018:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
 };
 
 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0028:26",
+	"abe-clkctrl:0028:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst =
 };
 
 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0030:26",
+	"abe-clkctrl:0030:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst =
 };
 
 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
-	"abe_cm:clk:0038:26",
+	"abe-clkctrl:0038:26",
 	"pad_clks_ck",
 	"slimbus_clk",
 	NULL,
@@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
 
 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
 	{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
-	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
+	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
 	{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
-	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
-	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
-	{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
-	{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
-	{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
-	{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
-	{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
-	{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
+	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
+	{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
+	{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
+	{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
+	{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
+	{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
+	{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
 	{ 0 },
 };
 
@@ -268,12 +268,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
 };
 
 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
-	{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
-	{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
-	{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
-	{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
-	{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
-	{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+	{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
+	{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
+	{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
+	{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
+	{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
+	{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
 	{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 	{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 	{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
@@ -345,7 +345,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst
 };
 
 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
-	{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+	{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
 	{ 0 },
 };
 
@@ -378,7 +378,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst
 };
 
 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
-	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
+	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
 	{ 0 },
 };
 
@@ -389,7 +389,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
 };
 
 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
-	"l3init_cm:clk:0008:24",
+	"l3init-clkctrl:0008:24",
 	NULL,
 };
 
@@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
 };
 
 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
-	"l3init_cm:clk:0010:24",
+	"l3init-clkctrl:0010:24",
 	NULL,
 };
 
@@ -430,12 +430,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons
 };
 
 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
-	"l3init_cm:clk:0038:24",
+	"l3init-clkctrl:0038:24",
 	NULL,
 };
 
 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
-	"l3init_cm:clk:0038:25",
+	"l3init-clkctrl:0038:25",
 	NULL,
 };
 
@@ -494,8 +494,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons
 };
 
 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
-	{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
-	{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+	{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
+	{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
 	{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
 	{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
 	{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
@@ -519,7 +519,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon
 	{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 	{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
-	{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+	{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
 	{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 	{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 	{ 0 },
@@ -549,58 +549,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
 static struct ti_dt_clk omap54xx_clks[] = {
 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 	DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
-	DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
-	DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
-	DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
-	DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
-	DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
-	DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
-	DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
-	DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
-	DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
-	DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
-	DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
-	DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
-	DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
-	DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
-	DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
-	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
-	DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
-	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
-	DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
-	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
-	DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
-	DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
-	DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
-	DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
-	DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
-	DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
-	DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
-	DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
-	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
-	DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
-	DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
-	DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
-	DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
-	DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
-	DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
-	DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
-	DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
-	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
-	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
-	DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
-	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
-	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
-	DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
-	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
-	DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
-	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
-	DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
-	DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
+	DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
+	DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
+	DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
+	DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
+	DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
+	DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
+	DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
+	DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
+	DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
+	DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
+	DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
+	DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
+	DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
+	DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
+	DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
+	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
+	DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
+	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
+	DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
+	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
+	DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
+	DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
+	DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
+	DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
+	DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
+	DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
+	DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
+	DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
+	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
+	DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
+	DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
+	DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
+	DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
+	DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
+	DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
+	DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
+	DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
+	DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
+	DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
+	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
+	DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
+	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
+	DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
+	DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
 	{ .node_name = NULL },
 };
 
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
index 9daf3825f289..3b8e483aec92 100644
--- a/drivers/clk/ti/clk-816x.c
+++ b/drivers/clk/ti/clk-816x.c
@@ -1,13 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <linux/kernel.h>
 #include <linux/list.h>
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index aa0950c4f498..f0f5bf68b6d2 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * DRA7 ATL (Audio Tracking Logic) clock driver
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Peter Ujfalusi <peter.ujfalusi@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/init.h>
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 3463579220b5..ef2a445c63a3 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 617360e20d86..ae5862879417 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP clkctrl clock support
  *
  * Copyright (C) 2017 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
@@ -528,10 +520,6 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
 	char *c;
 	u16 soc_mask = 0;
 
-	if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
-	    of_node_name_eq(node, "clk"))
-		ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
-
 	addrp = of_get_address(node, 0, NULL, NULL);
 	addr = (u32)of_translate_address(node, addrp);
 
diff --git a/drivers/clk/ti/clkt_dflt.c b/drivers/clk/ti/clkt_dflt.c
index 91751dd26b16..a756ab1a5856 100644
--- a/drivers/clk/ti/clkt_dflt.c
+++ b/drivers/clk/ti/clkt_dflt.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Default clock type
  *
@@ -8,15 +9,6 @@
  * Richard Woodruff <r-woodruff2@ti.com>
  * Paul Walmsley
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/kernel.h>
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index c841d2d28111..37ab53339a9b 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * TI Clock driver internal definitions
  *
  * Copyright (C) 2014 Texas Instruments, Inc
  *     Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 #ifndef __DRIVERS_CLK_TI_CLOCK__
 #define __DRIVERS_CLK_TI_CLOCK__
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index 24179c907774..c897ad7e681e 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP clockdomain support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 779b9900f636..77b771dd050a 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI composite clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 9fbea0997b43..488d3da60c31 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI Divider Clock
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 7c6dc8449b22..8ed43bc6b7cc 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP DPLL clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 749c6b73abff..2db3fc4a443e 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -1,13 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
index 8cb00d0af966..c80cee0f5d3d 100644
--- a/drivers/clk/ti/fixed-factor.c
+++ b/drivers/clk/ti/fixed-factor.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI Fixed Factor Clock
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index 0033de9beb4c..307702921431 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP gate clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index dd2b455183a9..f47beeea211e 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * OMAP interface clock support
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 15de513d2d81..46b45b3e8319 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI Multiplexer Clock
  *
  * Copyright (C) 2013 Texas Instruments, Inc.
  *
  * Tero Kristo <t-kristo@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 1244c4e568ff..c2088b3c4081 100644
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,6 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_PMC_ATOM)		+= clk-pmc-atom.o
 obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)	+= clk-fch.o
-clk-x86-lpss-y			:= clk-lpss-atom.o
-obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-x86-lpss.o
+obj-$(CONFIG_X86_INTEL_LPSS)	+= clk-lpss-atom.o clk-pmc-atom.o
 obj-$(CONFIG_CLK_LGM_CGU)	+= clk-cgu.o clk-cgu-pll.o clk-lgm.o
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3c0ee102fe73..49960eb22f19 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,7 +22,7 @@ config CLKEVT_I8253
 config I8253_LOCK
 	bool
 
-config OMAP_DM_TIMER
+config OMAP_DM_SYSTIMER
 	bool
 	select TIMER_OF
 
@@ -56,6 +56,12 @@ config DIGICOLOR_TIMER
 	help
 	  Enables the support for the digicolor timer driver.
 
+config OMAP_DM_TIMER
+	tristate "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
+	select TIMER_OF
+	help
+	  Enables the support for the TI dual-mode timer driver.
+
 config DW_APB_TIMER
 	bool "DW APB timer driver" if COMPILE_TEST
 	help
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 6ca640019e10..59c8909df9f3 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
 obj-$(CONFIG_DAVINCI_TIMER)	+= timer-davinci.o
 obj-$(CONFIG_DIGICOLOR_TIMER)	+= timer-digicolor.o
 obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
-obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm-systimer.o
+obj-$(CONFIG_OMAP_DM_SYSTIMER)	+= timer-ti-dm-systimer.o
 obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o
 obj-$(CONFIG_FTTMR010_TIMER)	+= timer-fttmr010.o
diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c
index c194e8f74e1d..469f7c91564b 100644
--- a/drivers/clocksource/timer-ti-dm.c
+++ b/drivers/clocksource/timer-ti-dm.c
@@ -44,6 +44,121 @@ enum {
 	REQUEST_BY_NODE,
 };
 
+static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
+						int posted)
+{
+	if (posted)
+		while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
+			cpu_relax();
+
+	return readl_relaxed(timer->func_base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
+					u32 reg, u32 val, int posted)
+{
+	if (posted)
+		while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
+			cpu_relax();
+
+	writel_relaxed(val, timer->func_base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+{
+	u32 tidr;
+
+	/* Assume v1 ip if bits [31:16] are zero */
+	tidr = readl_relaxed(timer->io_base);
+	if (!(tidr >> 16)) {
+		timer->revision = 1;
+		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+		timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+		timer->func_base = timer->io_base;
+	} else {
+		timer->revision = 2;
+		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+		timer->pend = timer->io_base +
+			_OMAP_TIMER_WRITE_PEND_OFFSET +
+				OMAP_TIMER_V2_FUNC_OFFSET;
+		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+	}
+}
+
+/*
+ * __omap_dm_timer_enable_posted - enables write posted mode
+ * @timer:      pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+	if (timer->posted)
+		return;
+
+	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
+		timer->posted = OMAP_TIMER_NONPOSTED;
+		__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
+		return;
+	}
+
+	__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
+			      OMAP_TIMER_CTRL_POSTED, 0);
+	timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+	timer->posted = OMAP_TIMER_POSTED;
+}
+
+static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
+					int posted, unsigned long rate)
+{
+	u32 l;
+
+	l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+	if (l & OMAP_TIMER_CTRL_ST) {
+		l &= ~0x1;
+		__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+		/* Readback to make sure write has completed */
+		__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
+		/*
+		 * Wait for functional clock period x 3.5 to make sure that
+		 * timer is stopped
+		 */
+		udelay(3500000 / rate + 1);
+#endif
+	}
+
+	/* Ack possibly pending interrupt */
+	writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+}
+
+static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
+						unsigned int value)
+{
+	writel_relaxed(value, timer->irq_ena);
+	__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+}
+
+static inline unsigned int
+__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
+{
+	return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
+}
+
+static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
+						unsigned int value)
+{
+	writel_relaxed(value, timer->irq_stat);
+}
+
 /**
  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
  * @timer:      timer pointer over which read operation to perform
@@ -921,6 +1036,10 @@ static const struct dmtimer_platform_data omap3plus_pdata = {
 	.timer_ops = &dmtimer_ops,
 };
 
+static const struct dmtimer_platform_data am6_pdata = {
+	.timer_ops = &dmtimer_ops,
+};
+
 static const struct of_device_id omap_timer_match[] = {
 	{
 		.compatible = "ti,omap2420-timer",
@@ -949,6 +1068,10 @@ static const struct of_device_id omap_timer_match[] = {
 		.compatible = "ti,dm816-timer",
 		.data = &omap3plus_pdata,
 	},
+	{
+		.compatible = "ti,am654-timer",
+		.data = &am6_pdata,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, omap_timer_match);
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 96de1536e1cb..2c96de3f2d83 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -127,6 +127,7 @@ static const struct of_device_id blocklist[] __initconst = {
 	{ .compatible = "mediatek,mt8173", },
 	{ .compatible = "mediatek,mt8176", },
 	{ .compatible = "mediatek,mt8183", },
+	{ .compatible = "mediatek,mt8186", },
 	{ .compatible = "mediatek,mt8365", },
 	{ .compatible = "mediatek,mt8516", },
 
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index 8fcaba541539..65f299acb0c4 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -220,12 +220,16 @@ static int dt_cpufreq_early_init(struct device *dev, int cpu)
 	 */
 	reg_name = find_supply_name(cpu_dev);
 	if (reg_name) {
-		priv->opp_table = dev_pm_opp_set_regulators(cpu_dev, &reg_name,
-							    1);
+		struct dev_pm_opp_config config = {
+			.regulator_names = &reg_name,
+			.regulator_count = 1,
+		};
+
+		priv->opp_table = dev_pm_opp_set_config(cpu_dev, &config);
 		if (IS_ERR(priv->opp_table)) {
 			ret = PTR_ERR(priv->opp_table);
 			if (ret != -EPROBE_DEFER)
-				dev_err(cpu_dev, "failed to set regulators: %d\n",
+				dev_err(cpu_dev, "failed to set OPP config: %d\n",
 					ret);
 			goto free_cpumask;
 		}
@@ -295,7 +299,7 @@ static int dt_cpufreq_early_init(struct device *dev, int cpu)
 out:
 	if (priv->have_static_opps)
 		dev_pm_opp_of_cpumask_remove_table(priv->cpus);
-	dev_pm_opp_put_regulators(priv->opp_table);
+	dev_pm_opp_clear_config(priv->opp_table);
 free_cpumask:
 	free_cpumask_var(priv->cpus);
 	return ret;
@@ -309,7 +313,7 @@ static void dt_cpufreq_release(void)
 		dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &priv->freq_table);
 		if (priv->have_static_opps)
 			dev_pm_opp_of_cpumask_remove_table(priv->cpus);
-		dev_pm_opp_put_regulators(priv->opp_table);
+		dev_pm_opp_clear_config(priv->opp_table);
 		free_cpumask_var(priv->cpus);
 		list_del(&priv->node);
 	}
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 2cad42774164..73432360e6e9 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -843,12 +843,14 @@ ssize_t cpufreq_show_cpus(const struct cpumask *mask, char *buf)
 	unsigned int cpu;
 
 	for_each_cpu(cpu, mask) {
-		if (i)
-			i += scnprintf(&buf[i], (PAGE_SIZE - i - 2), " ");
-		i += scnprintf(&buf[i], (PAGE_SIZE - i - 2), "%u", cpu);
+		i += scnprintf(&buf[i], (PAGE_SIZE - i - 2), "%u ", cpu);
 		if (i >= (PAGE_SIZE - 5))
 			break;
 	}
+
+	/* Remove the extra space at the end */
+	i--;
+
 	i += sprintf(&buf[i], "\n");
 	return i;
 }
@@ -971,21 +973,10 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr,
 	if (!fattr->store)
 		return -EIO;
 
-	/*
-	 * cpus_read_trylock() is used here to work around a circular lock
-	 * dependency problem with respect to the cpufreq_register_driver().
-	 */
-	if (!cpus_read_trylock())
-		return -EBUSY;
-
-	if (cpu_online(policy->cpu)) {
-		down_write(&policy->rwsem);
-		if (likely(!policy_is_inactive(policy)))
-			ret = fattr->store(policy, buf, count);
-		up_write(&policy->rwsem);
-	}
-
-	cpus_read_unlock();
+	down_write(&policy->rwsem);
+	if (likely(!policy_is_inactive(policy)))
+		ret = fattr->store(policy, buf, count);
+	up_write(&policy->rwsem);
 
 	return ret;
 }
diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
index 3fe9125156b4..57917b0670f2 100644
--- a/drivers/cpufreq/imx-cpufreq-dt.c
+++ b/drivers/cpufreq/imx-cpufreq-dt.c
@@ -86,6 +86,10 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
 	u32 cell_value, supported_hw[2];
 	int speed_grade, mkt_segment;
 	int ret;
+	struct dev_pm_opp_config config = {
+		.supported_hw = supported_hw,
+		.supported_hw_count = ARRAY_SIZE(supported_hw),
+	};
 
 	cpu_dev = get_cpu_device(0);
 
@@ -153,17 +157,17 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
 	dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
 			speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
 
-	cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
+	cpufreq_opp_table = dev_pm_opp_set_config(cpu_dev, &config);
 	if (IS_ERR(cpufreq_opp_table)) {
 		ret = PTR_ERR(cpufreq_opp_table);
-		dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
+		dev_err(&pdev->dev, "Failed to set Opp config: %d\n", ret);
 		return ret;
 	}
 
 	cpufreq_dt_pdev = platform_device_register_data(
 			&pdev->dev, "cpufreq-dt", -1, NULL, 0);
 	if (IS_ERR(cpufreq_dt_pdev)) {
-		dev_pm_opp_put_supported_hw(cpufreq_opp_table);
+		dev_pm_opp_clear_config(cpufreq_opp_table);
 		ret = PTR_ERR(cpufreq_dt_pdev);
 		dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
 		return ret;
@@ -176,7 +180,7 @@ static int imx_cpufreq_dt_remove(struct platform_device *pdev)
 {
 	platform_device_unregister(cpufreq_dt_pdev);
 	if (!of_machine_is_compatible("fsl,imx7ulp"))
-		dev_pm_opp_put_supported_hw(cpufreq_opp_table);
+		dev_pm_opp_clear_config(cpufreq_opp_table);
 	else
 		clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
 
diff --git a/drivers/cpufreq/mvebu-cpufreq.c b/drivers/cpufreq/mvebu-cpufreq.c
index 6d33a639f902..7f3cfe668f30 100644
--- a/drivers/cpufreq/mvebu-cpufreq.c
+++ b/drivers/cpufreq/mvebu-cpufreq.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * CPUFreq support for Armada 370/XP platforms.
  *
@@ -6,10 +7,6 @@
  * Yehuda Yitschak <yehuday@marvell.com>
  * Gregory Clement <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #define pr_fmt(fmt) "mvebu-pmsu: " fmt
diff --git a/drivers/cpufreq/pmac32-cpufreq.c b/drivers/cpufreq/pmac32-cpufreq.c
index 20f64a8b0a35..4b8ee2014da6 100644
--- a/drivers/cpufreq/pmac32-cpufreq.c
+++ b/drivers/cpufreq/pmac32-cpufreq.c
@@ -470,6 +470,10 @@ static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
 	if (slew_done_gpio_np)
 		slew_done_gpio = read_gpio(slew_done_gpio_np);
 
+	of_node_put(volt_gpio_np);
+	of_node_put(freq_gpio_np);
+	of_node_put(slew_done_gpio_np);
+
 	/* If we use the frequency GPIOs, calculate the min/max speeds based
 	 * on the bus frequencies
 	 */
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index 0253731d6d25..36c79580fba2 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -442,6 +442,9 @@ static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
 	struct platform_device *pdev = cpufreq_get_driver_data();
 	int ret;
 
+	if (data->throttle_irq <= 0)
+		return 0;
+
 	ret = irq_set_affinity_hint(data->throttle_irq, policy->cpus);
 	if (ret)
 		dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
@@ -469,6 +472,9 @@ static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
 
 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 {
+	if (data->throttle_irq <= 0)
+		return;
+
 	free_irq(data->throttle_irq, data);
 }
 
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 6dfa86971a75..4166b8d93b70 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -55,9 +55,7 @@ struct qcom_cpufreq_match_data {
 };
 
 struct qcom_cpufreq_drv {
-	struct opp_table **names_opp_tables;
-	struct opp_table **hw_opp_tables;
-	struct opp_table **genpd_opp_tables;
+	struct opp_table **opp_tables;
 	u32 versions;
 	const struct qcom_cpufreq_match_data *data;
 };
@@ -315,72 +313,44 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	}
 	of_node_put(np);
 
-	drv->names_opp_tables = kcalloc(num_possible_cpus(),
-				  sizeof(*drv->names_opp_tables),
+	drv->opp_tables = kcalloc(num_possible_cpus(),
+				  sizeof(*drv->opp_tables),
 				  GFP_KERNEL);
-	if (!drv->names_opp_tables) {
+	if (!drv->opp_tables) {
 		ret = -ENOMEM;
 		goto free_drv;
 	}
-	drv->hw_opp_tables = kcalloc(num_possible_cpus(),
-				  sizeof(*drv->hw_opp_tables),
-				  GFP_KERNEL);
-	if (!drv->hw_opp_tables) {
-		ret = -ENOMEM;
-		goto free_opp_names;
-	}
-
-	drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
-					sizeof(*drv->genpd_opp_tables),
-					GFP_KERNEL);
-	if (!drv->genpd_opp_tables) {
-		ret = -ENOMEM;
-		goto free_opp;
-	}
 
 	for_each_possible_cpu(cpu) {
+		struct dev_pm_opp_config config = {
+			.supported_hw = NULL,
+		};
+
 		cpu_dev = get_cpu_device(cpu);
 		if (NULL == cpu_dev) {
 			ret = -ENODEV;
-			goto free_genpd_opp;
+			goto free_opp;
 		}
 
 		if (drv->data->get_version) {
+			config.supported_hw = &drv->versions;
+			config.supported_hw_count = 1;
 
-			if (pvs_name) {
-				drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
-								     cpu_dev,
-								     pvs_name);
-				if (IS_ERR(drv->names_opp_tables[cpu])) {
-					ret = PTR_ERR(drv->names_opp_tables[cpu]);
-					dev_err(cpu_dev, "Failed to add OPP name %s\n",
-						pvs_name);
-					goto free_opp;
-				}
-			}
-
-			drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
-									 cpu_dev, &drv->versions, 1);
-			if (IS_ERR(drv->hw_opp_tables[cpu])) {
-				ret = PTR_ERR(drv->hw_opp_tables[cpu]);
-				dev_err(cpu_dev,
-					"Failed to set supported hardware\n");
-				goto free_genpd_opp;
-			}
+			if (pvs_name)
+				config.prop_name = pvs_name;
 		}
 
 		if (drv->data->genpd_names) {
-			drv->genpd_opp_tables[cpu] =
-				dev_pm_opp_attach_genpd(cpu_dev,
-							drv->data->genpd_names,
-							NULL);
-			if (IS_ERR(drv->genpd_opp_tables[cpu])) {
-				ret = PTR_ERR(drv->genpd_opp_tables[cpu]);
-				if (ret != -EPROBE_DEFER)
-					dev_err(cpu_dev,
-						"Could not attach to pm_domain: %d\n",
-						ret);
-				goto free_genpd_opp;
+			config.genpd_names = drv->data->genpd_names;
+			config.virt_devs = NULL;
+		}
+
+		if (config.supported_hw || config.genpd_names) {
+			drv->opp_tables[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
+			if (IS_ERR(drv->opp_tables[cpu])) {
+				ret = PTR_ERR(drv->opp_tables[cpu]);
+				dev_err(cpu_dev, "Failed to set OPP config\n");
+				goto free_opp;
 			}
 		}
 	}
@@ -395,27 +365,13 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	ret = PTR_ERR(cpufreq_dt_pdev);
 	dev_err(cpu_dev, "Failed to register platform device\n");
 
-free_genpd_opp:
-	for_each_possible_cpu(cpu) {
-		if (IS_ERR(drv->genpd_opp_tables[cpu]))
-			break;
-		dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
-	}
-	kfree(drv->genpd_opp_tables);
 free_opp:
 	for_each_possible_cpu(cpu) {
-		if (IS_ERR(drv->names_opp_tables[cpu]))
+		if (IS_ERR(drv->opp_tables[cpu]))
 			break;
-		dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
+		dev_pm_opp_clear_config(drv->opp_tables[cpu]);
 	}
-	for_each_possible_cpu(cpu) {
-		if (IS_ERR(drv->hw_opp_tables[cpu]))
-			break;
-		dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
-	}
-	kfree(drv->hw_opp_tables);
-free_opp_names:
-	kfree(drv->names_opp_tables);
+	kfree(drv->opp_tables);
 free_drv:
 	kfree(drv);
 
@@ -429,15 +385,10 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
 
 	platform_device_unregister(cpufreq_dt_pdev);
 
-	for_each_possible_cpu(cpu) {
-		dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
-		dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
-		dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
-	}
+	for_each_possible_cpu(cpu)
+		dev_pm_opp_clear_config(drv->opp_tables[cpu]);
 
-	kfree(drv->names_opp_tables);
-	kfree(drv->hw_opp_tables);
-	kfree(drv->genpd_opp_tables);
+	kfree(drv->opp_tables);
 	kfree(drv);
 
 	return 0;
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 6b6b20da2bcf..573b417e1483 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -275,6 +275,7 @@ static int qoriq_cpufreq_probe(struct platform_device *pdev)
 
 	np = of_find_matching_node(NULL, qoriq_cpufreq_blacklist);
 	if (np) {
+		of_node_put(np);
 		dev_info(&pdev->dev, "Disabling due to erratum A-008083");
 		return -ENODEV;
 	}
diff --git a/drivers/cpufreq/scpi-cpufreq.c b/drivers/cpufreq/scpi-cpufreq.c
index bda3e7d42964..fd2c16821d54 100644
--- a/drivers/cpufreq/scpi-cpufreq.c
+++ b/drivers/cpufreq/scpi-cpufreq.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * System Control and Power Interface (SCPI) based CPUFreq Interface driver
  *
  * Copyright (C) 2015 ARM Ltd.
  * Sudeep Holla <sudeep.holla@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
diff --git a/drivers/cpufreq/sti-cpufreq.c b/drivers/cpufreq/sti-cpufreq.c
index fdb0a722d881..f4121a9d27e5 100644
--- a/drivers/cpufreq/sti-cpufreq.c
+++ b/drivers/cpufreq/sti-cpufreq.c
@@ -159,6 +159,11 @@ static int sti_cpufreq_set_opp_info(void)
 	int ret;
 	char name[MAX_PCODE_NAME_LEN];
 	struct opp_table *opp_table;
+	struct dev_pm_opp_config config = {
+		.supported_hw = version,
+		.supported_hw_count = ARRAY_SIZE(version),
+		.prop_name = name,
+	};
 
 	reg_fields = sti_cpufreq_match();
 	if (!reg_fields) {
@@ -210,21 +215,14 @@ static int sti_cpufreq_set_opp_info(void)
 
 	snprintf(name, MAX_PCODE_NAME_LEN, "pcode%d", pcode);
 
-	opp_table = dev_pm_opp_set_prop_name(dev, name);
-	if (IS_ERR(opp_table)) {
-		dev_err(dev, "Failed to set prop name\n");
-		return PTR_ERR(opp_table);
-	}
-
 	version[0] = BIT(major);
 	version[1] = BIT(minor);
 	version[2] = BIT(substrate);
 
-	opp_table = dev_pm_opp_set_supported_hw(dev, version, VERSION_ELEMENTS);
+	opp_table = dev_pm_opp_set_config(dev, &config);
 	if (IS_ERR(opp_table)) {
-		dev_err(dev, "Failed to set supported hardware\n");
-		ret = PTR_ERR(opp_table);
-		goto err_put_prop_name;
+		dev_err(dev, "Failed to set OPP config\n");
+		return PTR_ERR(opp_table);
 	}
 
 	dev_dbg(dev, "pcode: %d major: %d minor: %d substrate: %d\n",
@@ -233,10 +231,6 @@ static int sti_cpufreq_set_opp_info(void)
 		version[0], version[1], version[2]);
 
 	return 0;
-
-err_put_prop_name:
-	dev_pm_opp_put_prop_name(opp_table);
-	return ret;
 }
 
 static int sti_cpufreq_fetch_syscon_registers(void)
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 75e1bf3a08f7..dd32da4eead2 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -106,6 +106,9 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
 	snprintf(name, MAX_NAME_LEN, "speed%d", speed);
 
 	for_each_possible_cpu(cpu) {
+		struct dev_pm_opp_config config = {
+			.prop_name = name,
+		};
 		struct device *cpu_dev = get_cpu_device(cpu);
 
 		if (!cpu_dev) {
@@ -113,10 +116,10 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
 			goto free_opp;
 		}
 
-		opp_tables[cpu] = dev_pm_opp_set_prop_name(cpu_dev, name);
+		opp_tables[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
 		if (IS_ERR(opp_tables[cpu])) {
 			ret = PTR_ERR(opp_tables[cpu]);
-			pr_err("Failed to set prop name\n");
+			pr_err("Failed to set OPP config\n");
 			goto free_opp;
 		}
 	}
@@ -135,7 +138,7 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
 	for_each_possible_cpu(cpu) {
 		if (IS_ERR_OR_NULL(opp_tables[cpu]))
 			break;
-		dev_pm_opp_put_prop_name(opp_tables[cpu]);
+		dev_pm_opp_clear_config(opp_tables[cpu]);
 	}
 	kfree(opp_tables);
 
@@ -150,7 +153,7 @@ static int sun50i_cpufreq_nvmem_remove(struct platform_device *pdev)
 	platform_device_unregister(cpufreq_dt_pdev);
 
 	for_each_possible_cpu(cpu)
-		dev_pm_opp_put_prop_name(opp_tables[cpu]);
+		dev_pm_opp_clear_config(opp_tables[cpu]);
 
 	kfree(opp_tables);
 
diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c
index e8db3d75be25..0bc496eaeedf 100644
--- a/drivers/cpufreq/tegra20-cpufreq.c
+++ b/drivers/cpufreq/tegra20-cpufreq.c
@@ -34,7 +34,7 @@ static bool cpu0_node_has_opp_v2_prop(void)
 
 static void tegra20_cpufreq_put_supported_hw(void *opp_table)
 {
-	dev_pm_opp_put_supported_hw(opp_table);
+	dev_pm_opp_clear_config(opp_table);
 }
 
 static void tegra20_cpufreq_dt_unregister(void *cpufreq_dt)
@@ -49,6 +49,10 @@ static int tegra20_cpufreq_probe(struct platform_device *pdev)
 	struct device *cpu_dev;
 	u32 versions[2];
 	int err;
+	struct dev_pm_opp_config config = {
+		.supported_hw = versions,
+		.supported_hw_count = ARRAY_SIZE(versions),
+	};
 
 	if (!cpu0_node_has_opp_v2_prop()) {
 		dev_err(&pdev->dev, "operating points not found\n");
@@ -71,10 +75,10 @@ static int tegra20_cpufreq_probe(struct platform_device *pdev)
 	if (WARN_ON(!cpu_dev))
 		return -ENODEV;
 
-	opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2);
+	opp_table = dev_pm_opp_set_config(cpu_dev, &config);
 	err = PTR_ERR_OR_ZERO(opp_table);
 	if (err) {
-		dev_err(&pdev->dev, "failed to set supported hw: %d\n", err);
+		dev_err(&pdev->dev, "failed to set OPP config: %d\n", err);
 		return err;
 	}
 
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 8f9fdd864391..cc58675df5c4 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -324,10 +324,13 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
 {
 	u32 version[VERSION_COUNT];
 	const struct of_device_id *match;
-	struct opp_table *ti_opp_table;
 	struct ti_cpufreq_data *opp_data;
 	const char * const default_reg_names[] = {"vdd", "vbb"};
 	int ret;
+	struct dev_pm_opp_config config = {
+		.supported_hw = version,
+		.supported_hw_count = ARRAY_SIZE(version),
+	};
 
 	match = dev_get_platdata(&pdev->dev);
 	if (!match)
@@ -370,33 +373,24 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
 	if (ret)
 		goto fail_put_node;
 
-	ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
-						   version, VERSION_COUNT);
-	if (IS_ERR(ti_opp_table)) {
-		dev_err(opp_data->cpu_dev,
-			"Failed to set supported hardware\n");
-		ret = PTR_ERR(ti_opp_table);
-		goto fail_put_node;
-	}
-
-	opp_data->opp_table = ti_opp_table;
-
 	if (opp_data->soc_data->multi_regulator) {
-		const char * const *reg_names = default_reg_names;
+		config.regulator_count = ARRAY_SIZE(default_reg_names);
 
 		if (opp_data->soc_data->reg_names)
-			reg_names = opp_data->soc_data->reg_names;
-		ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
-							 reg_names,
-							 ARRAY_SIZE(default_reg_names));
-		if (IS_ERR(ti_opp_table)) {
-			dev_pm_opp_put_supported_hw(opp_data->opp_table);
-			ret =  PTR_ERR(ti_opp_table);
-			goto fail_put_node;
-		}
+			config.regulator_names = opp_data->soc_data->reg_names;
+		else
+			config.regulator_names = default_reg_names;
+	}
+
+	opp_data->opp_table = dev_pm_opp_set_config(opp_data->cpu_dev, &config);
+	if (IS_ERR(opp_data->opp_table)) {
+		dev_err(opp_data->cpu_dev, "Failed to set OPP config\n");
+		ret = PTR_ERR(opp_data->opp_table);
+		goto fail_put_node;
 	}
 
 	of_node_put(opp_data->opp_node);
+
 register_cpufreq_dt:
 	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
 
diff --git a/drivers/cpuidle/cpuidle-at91.c b/drivers/cpuidle/cpuidle-at91.c
index 9c5853b6ca4a..45ee8e1e71ae 100644
--- a/drivers/cpuidle/cpuidle-at91.c
+++ b/drivers/cpuidle/cpuidle-at91.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * based on arch/arm/mach-kirkwood/cpuidle.c
  *
  * CPU idle support for AT91 SoC
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The cpu idle uses wait-for-interrupt and RAM self refresh in order
  * to implement two idle states -
  * #1 wait-for-interrupt
diff --git a/drivers/cpuidle/cpuidle-kirkwood.c b/drivers/cpuidle/cpuidle-kirkwood.c
index 511c4f46027a..13bf743f885b 100644
--- a/drivers/cpuidle/cpuidle-kirkwood.c
+++ b/drivers/cpuidle/cpuidle-kirkwood.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * CPU idle Marvell Kirkwood SoCs
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * The cpu idle uses wait-for-interrupt and DDR self refresh in order
  * to implement two idle states -
  * #1 wait-for-interrupt
diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c
index 540105ca0781..57bc3e3ae391 100644
--- a/drivers/cpuidle/cpuidle-psci.c
+++ b/drivers/cpuidle/cpuidle-psci.c
@@ -69,12 +69,12 @@ static int __psci_enter_domain_idle_state(struct cpuidle_device *dev,
 		return -1;
 
 	/* Do runtime PM to manage a hierarchical CPU toplogy. */
-	rcu_irq_enter_irqson();
+	ct_irq_enter_irqson();
 	if (s2idle)
 		dev_pm_genpd_suspend(pd_dev);
 	else
 		pm_runtime_put_sync_suspend(pd_dev);
-	rcu_irq_exit_irqson();
+	ct_irq_exit_irqson();
 
 	state = psci_get_domain_state();
 	if (!state)
@@ -82,12 +82,12 @@ static int __psci_enter_domain_idle_state(struct cpuidle_device *dev,
 
 	ret = psci_cpu_suspend_enter(state) ? -1 : idx;
 
-	rcu_irq_enter_irqson();
+	ct_irq_enter_irqson();
 	if (s2idle)
 		dev_pm_genpd_resume(pd_dev);
 	else
 		pm_runtime_get_sync(pd_dev);
-	rcu_irq_exit_irqson();
+	ct_irq_exit_irqson();
 
 	cpu_pm_exit();
 
diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.c b/drivers/cpuidle/cpuidle-riscv-sbi.c
index 1151e5e2ba82..862a2876f1c9 100644
--- a/drivers/cpuidle/cpuidle-riscv-sbi.c
+++ b/drivers/cpuidle/cpuidle-riscv-sbi.c
@@ -116,12 +116,12 @@ static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev,
 		return -1;
 
 	/* Do runtime PM to manage a hierarchical CPU toplogy. */
-	rcu_irq_enter_irqson();
+	ct_irq_enter_irqson();
 	if (s2idle)
 		dev_pm_genpd_suspend(pd_dev);
 	else
 		pm_runtime_put_sync_suspend(pd_dev);
-	rcu_irq_exit_irqson();
+	ct_irq_exit_irqson();
 
 	if (sbi_is_domain_state_available())
 		state = sbi_get_domain_state();
@@ -130,12 +130,12 @@ static int __sbi_enter_domain_idle_state(struct cpuidle_device *dev,
 
 	ret = sbi_suspend(state) ? -1 : idx;
 
-	rcu_irq_enter_irqson();
+	ct_irq_enter_irqson();
 	if (s2idle)
 		dev_pm_genpd_resume(pd_dev);
 	else
 		pm_runtime_get_sync(pd_dev);
-	rcu_irq_exit_irqson();
+	ct_irq_exit_irqson();
 
 	cpu_pm_exit();
 
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index ef2ea1b12cd8..62dd956025f3 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -23,6 +23,7 @@
 #include <linux/suspend.h>
 #include <linux/tick.h>
 #include <linux/mmu_context.h>
+#include <linux/context_tracking.h>
 #include <trace/events/power.h>
 
 #include "cpuidle.h"
@@ -150,12 +151,12 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv,
 	 */
 	stop_critical_timings();
 	if (!(target_state->flags & CPUIDLE_FLAG_RCU_IDLE))
-		rcu_idle_enter();
+		ct_idle_enter();
 	target_state->enter_s2idle(dev, drv, index);
 	if (WARN_ON_ONCE(!irqs_disabled()))
 		local_irq_disable();
 	if (!(target_state->flags & CPUIDLE_FLAG_RCU_IDLE))
-		rcu_idle_exit();
+		ct_idle_exit();
 	tick_unfreeze();
 	start_critical_timings();
 
@@ -233,10 +234,10 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv,
 
 	stop_critical_timings();
 	if (!(target_state->flags & CPUIDLE_FLAG_RCU_IDLE))
-		rcu_idle_enter();
+		ct_idle_enter();
 	entered_state = target_state->enter(dev, drv, index);
 	if (!(target_state->flags & CPUIDLE_FLAG_RCU_IDLE))
-		rcu_idle_exit();
+		ct_idle_exit();
 	start_critical_timings();
 
 	sched_clock_idle_wakeup_event();
diff --git a/drivers/cpuidle/governors/haltpoll.c b/drivers/cpuidle/governors/haltpoll.c
index cb2a96eafc02..1dff3a52917d 100644
--- a/drivers/cpuidle/governors/haltpoll.c
+++ b/drivers/cpuidle/governors/haltpoll.c
@@ -19,6 +19,7 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/kvm_para.h>
+#include <trace/events/power.h>
 
 static unsigned int guest_halt_poll_ns __read_mostly = 200000;
 module_param(guest_halt_poll_ns, uint, 0644);
@@ -90,6 +91,7 @@ static void adjust_poll_limit(struct cpuidle_device *dev, u64 block_ns)
 		if (val > guest_halt_poll_ns)
 			val = guest_halt_poll_ns;
 
+		trace_guest_halt_poll_ns_grow(val, dev->poll_limit_ns);
 		dev->poll_limit_ns = val;
 	} else if (block_ns > guest_halt_poll_ns &&
 		   guest_halt_poll_allow_shrink) {
@@ -100,6 +102,7 @@ static void adjust_poll_limit(struct cpuidle_device *dev, u64 block_ns)
 			val = 0;
 		else
 			val /= shrink;
+		trace_guest_halt_poll_ns_shrink(val, dev->poll_limit_ns);
 		dev->poll_limit_ns = val;
 	}
 }
diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c
index 5bb950182026..910d6751644c 100644
--- a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c
+++ b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c
@@ -170,6 +170,7 @@ static int sun8i_ss_setup_ivs(struct skcipher_request *areq)
 	while (i >= 0) {
 		dma_unmap_single(ss->dev, rctx->p_iv[i], ivsize, DMA_TO_DEVICE);
 		memzero_explicit(sf->iv[i], ivsize);
+		i--;
 	}
 	return err;
 }
diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
index 98593a0cff69..ac2329e2b0e5 100644
--- a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
+++ b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
@@ -528,25 +528,33 @@ static int allocate_flows(struct sun8i_ss_dev *ss)
 
 		ss->flows[i].biv = devm_kmalloc(ss->dev, AES_BLOCK_SIZE,
 						GFP_KERNEL | GFP_DMA);
-		if (!ss->flows[i].biv)
+		if (!ss->flows[i].biv) {
+			err = -ENOMEM;
 			goto error_engine;
+		}
 
 		for (j = 0; j < MAX_SG; j++) {
 			ss->flows[i].iv[j] = devm_kmalloc(ss->dev, AES_BLOCK_SIZE,
 							  GFP_KERNEL | GFP_DMA);
-			if (!ss->flows[i].iv[j])
+			if (!ss->flows[i].iv[j]) {
+				err = -ENOMEM;
 				goto error_engine;
+			}
 		}
 
 		/* the padding could be up to two block. */
 		ss->flows[i].pad = devm_kmalloc(ss->dev, MAX_PAD_SIZE,
 						GFP_KERNEL | GFP_DMA);
-		if (!ss->flows[i].pad)
+		if (!ss->flows[i].pad) {
+			err = -ENOMEM;
 			goto error_engine;
+		}
 		ss->flows[i].result = devm_kmalloc(ss->dev, SHA256_DIGEST_SIZE,
 						   GFP_KERNEL | GFP_DMA);
-		if (!ss->flows[i].result)
+		if (!ss->flows[i].result) {
+			err = -ENOMEM;
 			goto error_engine;
+		}
 
 		ss->flows[i].engine = crypto_engine_alloc_init(ss->dev, true);
 		if (!ss->flows[i].engine) {
diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
index ac417a6b39e5..36a82b22953c 100644
--- a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
+++ b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
@@ -30,8 +30,8 @@ static int sun8i_ss_hashkey(struct sun8i_ss_hash_tfm_ctx *tfmctx, const u8 *key,
 	int ret = 0;
 
 	xtfm = crypto_alloc_shash("sha1", 0, CRYPTO_ALG_NEED_FALLBACK);
-	if (!xtfm)
-		return -ENOMEM;
+	if (IS_ERR(xtfm))
+		return PTR_ERR(xtfm);
 
 	len = sizeof(*sdesc) + crypto_shash_descsize(xtfm);
 	sdesc = kmalloc(len, GFP_KERNEL);
@@ -586,7 +586,8 @@ int sun8i_ss_hash_run(struct crypto_engine *engine, void *breq)
 			rctx->t_dst[k + 1].len = rctx->t_dst[k].len;
 		}
 		addr_xpad = dma_map_single(ss->dev, tfmctx->ipad, bs, DMA_TO_DEVICE);
-		if (dma_mapping_error(ss->dev, addr_xpad)) {
+		err = dma_mapping_error(ss->dev, addr_xpad);
+		if (err) {
 			dev_err(ss->dev, "Fail to create DMA mapping of ipad\n");
 			goto err_dma_xpad;
 		}
@@ -612,7 +613,8 @@ int sun8i_ss_hash_run(struct crypto_engine *engine, void *breq)
 			goto err_dma_result;
 		}
 		addr_xpad = dma_map_single(ss->dev, tfmctx->opad, bs, DMA_TO_DEVICE);
-		if (dma_mapping_error(ss->dev, addr_xpad)) {
+		err = dma_mapping_error(ss->dev, addr_xpad);
+		if (err) {
 			dev_err(ss->dev, "Fail to create DMA mapping of opad\n");
 			goto err_dma_xpad;
 		}
diff --git a/drivers/crypto/atmel-ecc.c b/drivers/crypto/atmel-ecc.c
index 59a57279e77b..a4b13d326cfc 100644
--- a/drivers/crypto/atmel-ecc.c
+++ b/drivers/crypto/atmel-ecc.c
@@ -349,8 +349,16 @@ static int atmel_ecc_remove(struct i2c_client *client)
 
 	/* Return EBUSY if i2c client already allocated. */
 	if (atomic_read(&i2c_priv->tfm_count)) {
-		dev_err(&client->dev, "Device is busy\n");
-		return -EBUSY;
+		/*
+		 * After we return here, the memory backing the device is freed.
+		 * That happens no matter what the return value of this function
+		 * is because in the Linux device model there is no error
+		 * handling for unbinding a driver.
+		 * If there is still some action pending, it probably involves
+		 * accessing the freed memory.
+		 */
+		dev_emerg(&client->dev, "Device is busy, expect memory corruption.\n");
+		return 0;
 	}
 
 	crypto_unregister_kpp(&atmel_ecdh_nist_p256);
diff --git a/drivers/crypto/ccp/ccp-dev.h b/drivers/crypto/ccp/ccp-dev.h
index a5d9123a22ea..83350e2d9821 100644
--- a/drivers/crypto/ccp/ccp-dev.h
+++ b/drivers/crypto/ccp/ccp-dev.h
@@ -366,7 +366,7 @@ struct ccp_device {
 
 	/* Master lists that all cmds are queued on. Because there can be
 	 * more than one CCP command queue that can process a cmd a separate
-	 * backlog list is neeeded so that the backlog completion call
+	 * backlog list is needed so that the backlog completion call
 	 * completes before the cmd is available for execution.
 	 */
 	spinlock_t cmd_lock ____cacheline_aligned;
diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c
index 799b476fc3e8..0c92d940ac4e 100644
--- a/drivers/crypto/ccp/sev-dev.c
+++ b/drivers/crypto/ccp/sev-dev.c
@@ -577,6 +577,8 @@ static int sev_ioctl_do_platform_status(struct sev_issue_cmd *argp)
 	struct sev_user_data_status data;
 	int ret;
 
+	memset(&data, 0, sizeof(data));
+
 	ret = __sev_do_cmd_locked(SEV_CMD_PLATFORM_STATUS, &data, &argp->error);
 	if (ret)
 		return ret;
@@ -630,7 +632,7 @@ static int sev_ioctl_do_pek_csr(struct sev_issue_cmd *argp, bool writable)
 	if (input.length > SEV_FW_BLOB_MAX_SIZE)
 		return -EFAULT;
 
-	blob = kmalloc(input.length, GFP_KERNEL);
+	blob = kzalloc(input.length, GFP_KERNEL);
 	if (!blob)
 		return -ENOMEM;
 
@@ -854,7 +856,7 @@ static int sev_ioctl_do_get_id2(struct sev_issue_cmd *argp)
 	input_address = (void __user *)input.address;
 
 	if (input.address && input.length) {
-		id_blob = kmalloc(input.length, GFP_KERNEL);
+		id_blob = kzalloc(input.length, GFP_KERNEL);
 		if (!id_blob)
 			return -ENOMEM;
 
@@ -973,14 +975,14 @@ static int sev_ioctl_do_pdh_export(struct sev_issue_cmd *argp, bool writable)
 	if (input.cert_chain_len > SEV_FW_BLOB_MAX_SIZE)
 		return -EFAULT;
 
-	pdh_blob = kmalloc(input.pdh_cert_len, GFP_KERNEL);
+	pdh_blob = kzalloc(input.pdh_cert_len, GFP_KERNEL);
 	if (!pdh_blob)
 		return -ENOMEM;
 
 	data.pdh_cert_address = __psp_pa(pdh_blob);
 	data.pdh_cert_len = input.pdh_cert_len;
 
-	cert_blob = kmalloc(input.cert_chain_len, GFP_KERNEL);
+	cert_blob = kzalloc(input.cert_chain_len, GFP_KERNEL);
 	if (!cert_blob) {
 		ret = -ENOMEM;
 		goto e_free_pdh;
diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index b4ca2eb034d7..ad83c194d664 100644
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -877,13 +877,6 @@ static void qm_pm_put_sync(struct hisi_qm *qm)
 	pm_runtime_put_autosuspend(dev);
 }
 
-static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
-{
-	u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
-
-	return &qm->qp_array[cqn];
-}
-
 static void qm_cq_head_update(struct hisi_qp *qp)
 {
 	if (qp->qp_status.cq_head == QM_Q_DEPTH - 1) {
@@ -894,47 +887,37 @@ static void qm_cq_head_update(struct hisi_qp *qp)
 	}
 }
 
-static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
+static void qm_poll_req_cb(struct hisi_qp *qp)
 {
-	if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
-		return;
-
-	if (qp->event_cb) {
-		qp->event_cb(qp);
-		return;
-	}
-
-	if (qp->req_cb) {
-		struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
-
-		while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
-			dma_rmb();
-			qp->req_cb(qp, qp->sqe + qm->sqe_size *
-				   le16_to_cpu(cqe->sq_head));
-			qm_cq_head_update(qp);
-			cqe = qp->cqe + qp->qp_status.cq_head;
-			qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
-			      qp->qp_status.cq_head, 0);
-			atomic_dec(&qp->qp_status.used);
-		}
+	struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
+	struct hisi_qm *qm = qp->qm;
 
-		/* set c_flag */
+	while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
+		dma_rmb();
+		qp->req_cb(qp, qp->sqe + qm->sqe_size *
+			   le16_to_cpu(cqe->sq_head));
+		qm_cq_head_update(qp);
+		cqe = qp->cqe + qp->qp_status.cq_head;
 		qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
-		      qp->qp_status.cq_head, 1);
+		      qp->qp_status.cq_head, 0);
+		atomic_dec(&qp->qp_status.used);
 	}
+
+	/* set c_flag */
+	qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, qp->qp_status.cq_head, 1);
 }
 
-static void qm_work_process(struct work_struct *work)
+static int qm_get_complete_eqe_num(struct hisi_qm_poll_data *poll_data)
 {
-	struct hisi_qm *qm = container_of(work, struct hisi_qm, work);
+	struct hisi_qm *qm = poll_data->qm;
 	struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
-	struct hisi_qp *qp;
 	int eqe_num = 0;
+	u16 cqn;
 
 	while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
+		cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
+		poll_data->qp_finish_id[eqe_num] = cqn;
 		eqe_num++;
-		qp = qm_to_hisi_qp(qm, eqe);
-		qm_poll_qp(qp, qm);
 
 		if (qm->status.eq_head == QM_EQ_DEPTH - 1) {
 			qm->status.eqc_phase = !qm->status.eqc_phase;
@@ -945,37 +928,70 @@ static void qm_work_process(struct work_struct *work)
 			qm->status.eq_head++;
 		}
 
-		if (eqe_num == QM_EQ_DEPTH / 2 - 1) {
-			eqe_num = 0;
-			qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
-		}
+		if (eqe_num == (QM_EQ_DEPTH >> 1) - 1)
+			break;
 	}
 
 	qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
+
+	return eqe_num;
 }
 
-static irqreturn_t do_qm_irq(int irq, void *data)
+static void qm_work_process(struct work_struct *work)
 {
-	struct hisi_qm *qm = (struct hisi_qm *)data;
+	struct hisi_qm_poll_data *poll_data =
+		container_of(work, struct hisi_qm_poll_data, work);
+	struct hisi_qm *qm = poll_data->qm;
+	struct hisi_qp *qp;
+	int eqe_num, i;
 
-	/* the workqueue created by device driver of QM */
-	if (qm->wq)
-		queue_work(qm->wq, &qm->work);
-	else
-		schedule_work(&qm->work);
+	/* Get qp id of completed tasks and re-enable the interrupt. */
+	eqe_num = qm_get_complete_eqe_num(poll_data);
+	for (i = eqe_num - 1; i >= 0; i--) {
+		qp = &qm->qp_array[poll_data->qp_finish_id[i]];
+		if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
+			continue;
 
-	return IRQ_HANDLED;
+		if (qp->event_cb) {
+			qp->event_cb(qp);
+			continue;
+		}
+
+		if (likely(qp->req_cb))
+			qm_poll_req_cb(qp);
+	}
+}
+
+static bool do_qm_irq(struct hisi_qm *qm)
+{
+	struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
+	struct hisi_qm_poll_data *poll_data;
+	u16 cqn;
+
+	if (!readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
+		return false;
+
+	if (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
+		cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
+		poll_data = &qm->poll_data[cqn];
+		queue_work(qm->wq, &poll_data->work);
+
+		return true;
+	}
+
+	return false;
 }
 
 static irqreturn_t qm_irq(int irq, void *data)
 {
 	struct hisi_qm *qm = data;
+	bool ret;
 
-	if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
-		return do_qm_irq(irq, data);
+	ret = do_qm_irq(qm);
+	if (ret)
+		return IRQ_HANDLED;
 
 	atomic64_inc(&qm->debug.dfx.err_irq_cnt);
-	dev_err(&qm->pdev->dev, "invalid int source\n");
 	qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
 
 	return IRQ_NONE;
@@ -3134,11 +3150,8 @@ static int qm_stop_qp_nolock(struct hisi_qp *qp)
 	if (ret)
 		dev_err(dev, "Failed to drain out data for stopping!\n");
 
-	if (qp->qm->wq)
-		flush_workqueue(qp->qm->wq);
-	else
-		flush_work(&qp->qm->work);
 
+	flush_workqueue(qp->qm->wq);
 	if (unlikely(qp->is_resetting && atomic_read(&qp->qp_status.used)))
 		qp_stop_fail_cb(qp);
 
@@ -3557,8 +3570,10 @@ static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
 	for (i = num - 1; i >= 0; i--) {
 		qdma = &qm->qp_array[i].qdma;
 		dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma);
+		kfree(qm->poll_data[i].qp_finish_id);
 	}
 
+	kfree(qm->poll_data);
 	kfree(qm->qp_array);
 }
 
@@ -3567,12 +3582,18 @@ static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
 	struct device *dev = &qm->pdev->dev;
 	size_t off = qm->sqe_size * QM_Q_DEPTH;
 	struct hisi_qp *qp;
+	int ret = -ENOMEM;
+
+	qm->poll_data[id].qp_finish_id = kcalloc(qm->qp_num, sizeof(u16),
+						 GFP_KERNEL);
+	if (!qm->poll_data[id].qp_finish_id)
+		return -ENOMEM;
 
 	qp = &qm->qp_array[id];
 	qp->qdma.va = dma_alloc_coherent(dev, dma_size, &qp->qdma.dma,
 					 GFP_KERNEL);
 	if (!qp->qdma.va)
-		return -ENOMEM;
+		goto err_free_qp_finish_id;
 
 	qp->sqe = qp->qdma.va;
 	qp->sqe_dma = qp->qdma.dma;
@@ -3583,6 +3604,10 @@ static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
 	qp->qp_id = id;
 
 	return 0;
+
+err_free_qp_finish_id:
+	kfree(qm->poll_data[id].qp_finish_id);
+	return ret;
 }
 
 static void hisi_qm_pre_init(struct hisi_qm *qm)
@@ -3672,6 +3697,26 @@ static void qm_last_regs_uninit(struct hisi_qm *qm)
 	debug->qm_last_words = NULL;
 }
 
+static void hisi_qm_unint_work(struct hisi_qm *qm)
+{
+	destroy_workqueue(qm->wq);
+}
+
+static void hisi_qm_memory_uninit(struct hisi_qm *qm)
+{
+	struct device *dev = &qm->pdev->dev;
+
+	hisi_qp_memory_uninit(qm, qm->qp_num);
+	if (qm->qdma.va) {
+		hisi_qm_cache_wb(qm);
+		dma_free_coherent(dev, qm->qdma.size,
+				  qm->qdma.va, qm->qdma.dma);
+	}
+
+	idr_destroy(&qm->qp_idr);
+	kfree(qm->factor);
+}
+
 /**
  * hisi_qm_uninit() - Uninitialize qm.
  * @qm: The qm needed uninit.
@@ -3680,13 +3725,10 @@ static void qm_last_regs_uninit(struct hisi_qm *qm)
  */
 void hisi_qm_uninit(struct hisi_qm *qm)
 {
-	struct pci_dev *pdev = qm->pdev;
-	struct device *dev = &pdev->dev;
-
 	qm_last_regs_uninit(qm);
 
 	qm_cmd_uninit(qm);
-	kfree(qm->factor);
+	hisi_qm_unint_work(qm);
 	down_write(&qm->qps_lock);
 
 	if (!qm_avail_state(qm, QM_CLOSE)) {
@@ -3694,14 +3736,7 @@ void hisi_qm_uninit(struct hisi_qm *qm)
 		return;
 	}
 
-	hisi_qp_memory_uninit(qm, qm->qp_num);
-	idr_destroy(&qm->qp_idr);
-
-	if (qm->qdma.va) {
-		hisi_qm_cache_wb(qm);
-		dma_free_coherent(dev, qm->qdma.size,
-				  qm->qdma.va, qm->qdma.dma);
-	}
+	hisi_qm_memory_uninit(qm);
 	hisi_qm_set_state(qm, QM_NOT_READY);
 	up_write(&qm->qps_lock);
 
@@ -6018,14 +6053,28 @@ static int hisi_qm_pci_init(struct hisi_qm *qm)
 	return ret;
 }
 
-static void hisi_qm_init_work(struct hisi_qm *qm)
+static int hisi_qm_init_work(struct hisi_qm *qm)
 {
-	INIT_WORK(&qm->work, qm_work_process);
+	int i;
+
+	for (i = 0; i < qm->qp_num; i++)
+		INIT_WORK(&qm->poll_data[i].work, qm_work_process);
+
 	if (qm->fun_type == QM_HW_PF)
 		INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
 
 	if (qm->ver > QM_HW_V2)
 		INIT_WORK(&qm->cmd_process, qm_cmd_process);
+
+	qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
+				 WQ_UNBOUND, num_online_cpus(),
+				 pci_name(qm->pdev));
+	if (!qm->wq) {
+		pci_err(qm->pdev, "failed to alloc workqueue!\n");
+		return -ENOMEM;
+	}
+
+	return 0;
 }
 
 static int hisi_qp_alloc_memory(struct hisi_qm *qm)
@@ -6038,11 +6087,18 @@ static int hisi_qp_alloc_memory(struct hisi_qm *qm)
 	if (!qm->qp_array)
 		return -ENOMEM;
 
+	qm->poll_data = kcalloc(qm->qp_num, sizeof(struct hisi_qm_poll_data), GFP_KERNEL);
+	if (!qm->poll_data) {
+		kfree(qm->qp_array);
+		return -ENOMEM;
+	}
+
 	/* one more page for device or qp statuses */
 	qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
 		      sizeof(struct qm_cqe) * QM_Q_DEPTH;
 	qp_dma_size = PAGE_ALIGN(qp_dma_size) + PAGE_SIZE;
 	for (i = 0; i < qm->qp_num; i++) {
+		qm->poll_data[i].qm = qm;
 		ret = hisi_qp_memory_init(qm, qp_dma_size, i);
 		if (ret)
 			goto err_init_qp_mem;
@@ -6176,7 +6232,10 @@ int hisi_qm_init(struct hisi_qm *qm)
 	if (ret)
 		goto err_alloc_uacce;
 
-	hisi_qm_init_work(qm);
+	ret = hisi_qm_init_work(qm);
+	if (ret)
+		goto err_free_qm_memory;
+
 	qm_cmd_init(qm);
 	atomic_set(&qm->status.flags, QM_INIT);
 
@@ -6184,6 +6243,8 @@ int hisi_qm_init(struct hisi_qm *qm)
 
 	return 0;
 
+err_free_qm_memory:
+	hisi_qm_memory_uninit(qm);
 err_alloc_uacce:
 	if (qm->use_sva) {
 		uacce_remove(qm->uacce);
diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h
index c2e9b01187a7..42bb486f3b6d 100644
--- a/drivers/crypto/hisilicon/sec2/sec.h
+++ b/drivers/crypto/hisilicon/sec2/sec.h
@@ -143,10 +143,10 @@ struct sec_ctx {
 	/* Threshold for fake busy, trigger to return -EBUSY to user */
 	u32 fake_req_limit;
 
-	/* Currrent cyclic index to select a queue for encipher */
+	/* Current cyclic index to select a queue for encipher */
 	atomic_t enc_qcyclic;
 
-	 /* Currrent cyclic index to select a queue for decipher */
+	 /* Current cyclic index to select a queue for decipher */
 	atomic_t dec_qcyclic;
 
 	enum sec_alg_type alg_type;
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 4d85d2cbf376..2c0be91c0b09 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -508,16 +508,17 @@ static int sec_engine_init(struct hisi_qm *qm)
 
 	writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
 
-	/* HW V2 enable sm4 extra mode, as ctr/ecb */
-	if (qm->ver < QM_HW_V3)
+	if (qm->ver < QM_HW_V3) {
+		/* HW V2 enable sm4 extra mode, as ctr/ecb */
 		writel_relaxed(SEC_BD_ERR_CHK_EN0,
 			       qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
 
-	/* Enable sm4 xts mode multiple iv */
-	writel_relaxed(SEC_BD_ERR_CHK_EN1,
-		       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
-	writel_relaxed(SEC_BD_ERR_CHK_EN3,
-		       qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
+		/* HW V2 enable sm4 xts mode multiple iv */
+		writel_relaxed(SEC_BD_ERR_CHK_EN1,
+			       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
+		writel_relaxed(SEC_BD_ERR_CHK_EN3,
+			       qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
+	}
 
 	/* config endian */
 	sec_set_endian(qm);
@@ -1002,8 +1003,6 @@ static int sec_pf_probe_init(struct sec_dev *sec)
 
 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
 {
-	int ret;
-
 	qm->pdev = pdev;
 	qm->ver = pdev->revision;
 	qm->algs = "cipher\ndigest\naead";
@@ -1029,25 +1028,7 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
 		qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
 	}
 
-	/*
-	 * WQ_HIGHPRI: SEC request must be low delayed,
-	 * so need a high priority workqueue.
-	 * WQ_UNBOUND: SEC task is likely with long
-	 * running CPU intensive workloads.
-	 */
-	qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
-				 WQ_UNBOUND, num_online_cpus(),
-				 pci_name(qm->pdev));
-	if (!qm->wq) {
-		pci_err(qm->pdev, "fail to alloc workqueue\n");
-		return -ENOMEM;
-	}
-
-	ret = hisi_qm_init(qm);
-	if (ret)
-		destroy_workqueue(qm->wq);
-
-	return ret;
+	return hisi_qm_init(qm);
 }
 
 static void sec_qm_uninit(struct hisi_qm *qm)
@@ -1078,8 +1059,6 @@ static int sec_probe_init(struct sec_dev *sec)
 static void sec_probe_uninit(struct hisi_qm *qm)
 {
 	hisi_qm_dev_err_uninit(qm);
-
-	destroy_workqueue(qm->wq);
 }
 
 static void sec_iommu_used_check(struct sec_dev *sec)
diff --git a/drivers/crypto/hisilicon/trng/trng.c b/drivers/crypto/hisilicon/trng/trng.c
index 829f2caf0f67..97e500db0a82 100644
--- a/drivers/crypto/hisilicon/trng/trng.c
+++ b/drivers/crypto/hisilicon/trng/trng.c
@@ -185,7 +185,7 @@ static int hisi_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 	struct hisi_trng *trng;
 	int currsize = 0;
 	u32 val = 0;
-	u32 ret;
+	int ret;
 
 	trng = container_of(rng, struct hisi_trng, rng);
 
diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 9c925e9c0a2d..c3303d99acac 100644
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -990,8 +990,6 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
 
 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
 {
-	int ret;
-
 	qm->pdev = pdev;
 	qm->ver = pdev->revision;
 	if (pdev->revision >= QM_HW_V3)
@@ -1021,25 +1019,12 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
 		qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
 	}
 
-	qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
-				 WQ_UNBOUND, num_online_cpus(),
-				 pci_name(qm->pdev));
-	if (!qm->wq) {
-		pci_err(qm->pdev, "fail to alloc workqueue\n");
-		return -ENOMEM;
-	}
-
-	ret = hisi_qm_init(qm);
-	if (ret)
-		destroy_workqueue(qm->wq);
-
-	return ret;
+	return hisi_qm_init(qm);
 }
 
 static void hisi_zip_qm_uninit(struct hisi_qm *qm)
 {
 	hisi_qm_uninit(qm);
-	destroy_workqueue(qm->wq);
 }
 
 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
index bb02e0db3615..7503f6b18ac5 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
@@ -51,11 +51,47 @@ static const struct devlink_param otx2_cpt_dl_params[] = {
 			     NULL),
 };
 
-static int otx2_cpt_devlink_info_get(struct devlink *devlink,
+static int otx2_cpt_dl_info_firmware_version_put(struct devlink_info_req *req,
+						 struct otx2_cpt_eng_grp_info grp[],
+						 const char *ver_name, int eng_type)
+{
+	struct otx2_cpt_engs_rsvd *eng;
+	int i;
+
+	for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
+		eng = find_engines_by_type(&grp[i], eng_type);
+		if (eng)
+			return devlink_info_version_running_put(req, ver_name,
+								eng->ucode->ver_str);
+	}
+
+	return 0;
+}
+
+static int otx2_cpt_devlink_info_get(struct devlink *dl,
 				     struct devlink_info_req *req,
 				     struct netlink_ext_ack *extack)
 {
-	return devlink_info_driver_name_put(req, "rvu_cptpf");
+	struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
+	struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
+	int err;
+
+	err = devlink_info_driver_name_put(req, "rvu_cptpf");
+	if (err)
+		return err;
+
+	err = otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp,
+						    "fw.ae", OTX2_CPT_AE_TYPES);
+	if (err)
+		return err;
+
+	err = otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp,
+						    "fw.se", OTX2_CPT_SE_TYPES);
+	if (err)
+		return err;
+
+	return otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp,
+						    "fw.ie", OTX2_CPT_IE_TYPES);
 }
 
 static const struct devlink_ops otx2_cpt_devlink_ops = {
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
index 9cba2f714c7e..f10050fead16 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
@@ -476,7 +476,7 @@ static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info)
 	return ret;
 }
 
-static struct otx2_cpt_engs_rsvd *find_engines_by_type(
+struct otx2_cpt_engs_rsvd *find_engines_by_type(
 					struct otx2_cpt_eng_grp_info *eng_grp,
 					int eng_type)
 {
@@ -1605,7 +1605,10 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
 		if (!strncasecmp(val, "se", 2) && strchr(val, ':')) {
 			if (has_se || ucode_idx)
 				goto err_print;
-			tmp = strim(strsep(&val, ":"));
+			tmp = strsep(&val, ":");
+			if (!tmp)
+				goto err_print;
+			tmp = strim(tmp);
 			if (!val)
 				goto err_print;
 			if (strlen(tmp) != 2)
@@ -1617,7 +1620,10 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
 		} else if (!strncasecmp(val, "ae", 2) && strchr(val, ':')) {
 			if (has_ae || ucode_idx)
 				goto err_print;
-			tmp = strim(strsep(&val, ":"));
+			tmp = strsep(&val, ":");
+			if (!tmp)
+				goto err_print;
+			tmp = strim(tmp);
 			if (!val)
 				goto err_print;
 			if (strlen(tmp) != 2)
@@ -1629,7 +1635,10 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
 		} else if (!strncasecmp(val, "ie", 2) && strchr(val, ':')) {
 			if (has_ie || ucode_idx)
 				goto err_print;
-			tmp = strim(strsep(&val, ":"));
+			tmp = strsep(&val, ":");
+			if (!tmp)
+				goto err_print;
+			tmp = strim(tmp);
 			if (!val)
 				goto err_print;
 			if (strlen(tmp) != 2)
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
index 8f4d4e5f531a..e69320a54b5d 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
@@ -166,4 +166,7 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
 int otx2_cpt_dl_custom_egrp_delete(struct otx2_cptpf_dev *cptpf,
 				   struct devlink_param_gset_ctx *ctx);
 void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf);
+struct otx2_cpt_engs_rsvd *find_engines_by_type(
+					struct otx2_cpt_eng_grp_info *eng_grp,
+					int eng_type);
 #endif /* __OTX2_CPTPF_UCODE_H */
diff --git a/drivers/dax/super.c b/drivers/dax/super.c
index 50a08b2ec247..9b5e2a5eb0ae 100644
--- a/drivers/dax/super.c
+++ b/drivers/dax/super.c
@@ -22,6 +22,8 @@
  * @private: dax driver private data
  * @flags: state and boolean properties
  * @ops: operations for this device
+ * @holder_data: holder of a dax_device: could be filesystem or mapped device
+ * @holder_ops: operations for the inner holder
  */
 struct dax_device {
 	struct inode inode;
@@ -29,6 +31,8 @@ struct dax_device {
 	void *private;
 	unsigned long flags;
 	const struct dax_operations *ops;
+	void *holder_data;
+	const struct dax_holder_operations *holder_ops;
 };
 
 static dev_t dax_devt;
@@ -71,8 +75,11 @@ EXPORT_SYMBOL_GPL(dax_remove_host);
  * fs_dax_get_by_bdev() - temporary lookup mechanism for filesystem-dax
  * @bdev: block device to find a dax_device for
  * @start_off: returns the byte offset into the dax_device that @bdev starts
+ * @holder: filesystem or mapped device inside the dax_device
+ * @ops: operations for the inner holder
  */
-struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev, u64 *start_off)
+struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev, u64 *start_off,
+		void *holder, const struct dax_holder_operations *ops)
 {
 	struct dax_device *dax_dev;
 	u64 part_size;
@@ -92,11 +99,26 @@ struct dax_device *fs_dax_get_by_bdev(struct block_device *bdev, u64 *start_off)
 	dax_dev = xa_load(&dax_hosts, (unsigned long)bdev->bd_disk);
 	if (!dax_dev || !dax_alive(dax_dev) || !igrab(&dax_dev->inode))
 		dax_dev = NULL;
+	else if (holder) {
+		if (!cmpxchg(&dax_dev->holder_data, NULL, holder))
+			dax_dev->holder_ops = ops;
+		else
+			dax_dev = NULL;
+	}
 	dax_read_unlock(id);
 
 	return dax_dev;
 }
 EXPORT_SYMBOL_GPL(fs_dax_get_by_bdev);
+
+void fs_put_dax(struct dax_device *dax_dev, void *holder)
+{
+	if (dax_dev && holder &&
+	    cmpxchg(&dax_dev->holder_data, holder, NULL) == holder)
+		dax_dev->holder_ops = NULL;
+	put_dax(dax_dev);
+}
+EXPORT_SYMBOL_GPL(fs_put_dax);
 #endif /* CONFIG_BLOCK && CONFIG_FS_DAX */
 
 enum dax_device_flags {
@@ -204,6 +226,29 @@ size_t dax_recovery_write(struct dax_device *dax_dev, pgoff_t pgoff,
 }
 EXPORT_SYMBOL_GPL(dax_recovery_write);
 
+int dax_holder_notify_failure(struct dax_device *dax_dev, u64 off,
+			      u64 len, int mf_flags)
+{
+	int rc, id;
+
+	id = dax_read_lock();
+	if (!dax_alive(dax_dev)) {
+		rc = -ENXIO;
+		goto out;
+	}
+
+	if (!dax_dev->holder_ops) {
+		rc = -EOPNOTSUPP;
+		goto out;
+	}
+
+	rc = dax_dev->holder_ops->notify_failure(dax_dev, off, len, mf_flags);
+out:
+	dax_read_unlock(id);
+	return rc;
+}
+EXPORT_SYMBOL_GPL(dax_holder_notify_failure);
+
 #ifdef CONFIG_ARCH_HAS_PMEM_API
 void arch_wb_cache_pmem(void *addr, size_t size);
 void dax_flush(struct dax_device *dax_dev, void *addr, size_t size)
@@ -277,8 +322,15 @@ void kill_dax(struct dax_device *dax_dev)
 	if (!dax_dev)
 		return;
 
+	if (dax_dev->holder_data != NULL)
+		dax_holder_notify_failure(dax_dev, 0, U64_MAX, 0);
+
 	clear_bit(DAXDEV_ALIVE, &dax_dev->flags);
 	synchronize_srcu(&dax_srcu);
+
+	/* clear holder data */
+	dax_dev->holder_ops = NULL;
+	dax_dev->holder_data = NULL;
 }
 EXPORT_SYMBOL_GPL(kill_dax);
 
@@ -420,6 +472,19 @@ void put_dax(struct dax_device *dax_dev)
 }
 EXPORT_SYMBOL_GPL(put_dax);
 
+/**
+ * dax_holder() - obtain the holder of a dax device
+ * @dax_dev: a dax_device instance
+
+ * Return: the holder's data which represents the holder if registered,
+ * otherwize NULL.
+ */
+void *dax_holder(struct dax_device *dax_dev)
+{
+	return dax_dev->holder_data;
+}
+EXPORT_SYMBOL_GPL(dax_holder);
+
 /**
  * inode_dax: convert a public inode into its dax_dev
  * @inode: An inode with i_cdev pointing to a dax_dev
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 87eb2b837e68..9754d8b31621 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
 	  It reads ACTMON counters of memory controllers and adjusts the
 	  operating frequencies and voltages with OPP support.
 
+config ARM_MEDIATEK_CCI_DEVFREQ
+	tristate "MEDIATEK CCI DEVFREQ Driver"
+	depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
+	select DEVFREQ_GOV_PASSIVE
+	help
+	  This adds a devfreq driver for MediaTek Cache Coherent Interconnect
+	  which is shared the same regulators with the cpu cluster. It can track
+	  buck voltages and update a proper CCI frequency. Use the notification
+	  to get the regulator status.
+
 config ARM_RK3399_DMC_DEVFREQ
 	tristate "ARM RK3399 DMC DEVFREQ Driver"
 	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 0b6be92a25d9..bf40d04928d0 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o
 obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
 obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)	+= imx-bus.o
 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)	+= imx8m-ddrc.o
+obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)	+= mtk-cci-devfreq.o
 obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
 obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
 obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c
index e689101abc93..8fca24565e7d 100644
--- a/drivers/devfreq/exynos-bus.c
+++ b/drivers/devfreq/exynos-bus.c
@@ -161,8 +161,11 @@ static void exynos_bus_exit(struct device *dev)
 
 	dev_pm_opp_of_remove_table(dev);
 	clk_disable_unprepare(bus->clk);
-	dev_pm_opp_put_regulators(bus->opp_table);
-	bus->opp_table = NULL;
+
+	if (bus->opp_table) {
+		dev_pm_opp_clear_config(bus->opp_table);
+		bus->opp_table = NULL;
+	}
 }
 
 static void exynos_bus_passive_exit(struct device *dev)
@@ -182,11 +185,15 @@ static int exynos_bus_parent_parse_of(struct device_node *np,
 	struct opp_table *opp_table;
 	const char *vdd = "vdd";
 	int i, ret, count, size;
+	struct dev_pm_opp_config config = {
+		.regulator_names = &vdd,
+		.regulator_count = 1,
+	};
 
-	opp_table = dev_pm_opp_set_regulators(dev, &vdd, 1);
+	opp_table = dev_pm_opp_set_config(dev, &config);
 	if (IS_ERR(opp_table)) {
 		ret = PTR_ERR(opp_table);
-		dev_err(dev, "failed to set regulators %d\n", ret);
+		dev_err(dev, "failed to set OPP config %d\n", ret);
 		return ret;
 	}
 
@@ -236,7 +243,7 @@ static int exynos_bus_parent_parse_of(struct device_node *np,
 	return 0;
 
 err_regulator:
-	dev_pm_opp_put_regulators(bus->opp_table);
+	dev_pm_opp_clear_config(bus->opp_table);
 	bus->opp_table = NULL;
 
 	return ret;
@@ -459,8 +466,10 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	dev_pm_opp_of_remove_table(dev);
 	clk_disable_unprepare(bus->clk);
 err_reg:
-	dev_pm_opp_put_regulators(bus->opp_table);
-	bus->opp_table = NULL;
+	if (bus->opp_table) {
+		dev_pm_opp_clear_config(bus->opp_table);
+		bus->opp_table = NULL;
+	}
 
 	return ret;
 }
diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
new file mode 100644
index 000000000000..71abb3fbd042
--- /dev/null
+++ b/drivers/devfreq/mtk-cci-devfreq.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+
+struct mtk_ccifreq_platform_data {
+	int min_volt_shift;
+	int max_volt_shift;
+	int proc_max_volt;
+	int sram_min_volt;
+	int sram_max_volt;
+};
+
+struct mtk_ccifreq_drv {
+	struct device *dev;
+	struct devfreq *devfreq;
+	struct regulator *proc_reg;
+	struct regulator *sram_reg;
+	struct clk *cci_clk;
+	struct clk *inter_clk;
+	int inter_voltage;
+	unsigned long pre_freq;
+	/* Avoid race condition for regulators between notify and policy */
+	struct mutex reg_lock;
+	struct notifier_block opp_nb;
+	const struct mtk_ccifreq_platform_data *soc_data;
+	int vtrack_max;
+};
+
+static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
+{
+	const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
+	struct device *dev = drv->dev;
+	int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
+	int retry_max = drv->vtrack_max;
+
+	if (!drv->sram_reg) {
+		ret = regulator_set_voltage(drv->proc_reg, new_voltage,
+					    drv->soc_data->proc_max_volt);
+		return ret;
+	}
+
+	pre_voltage = regulator_get_voltage(drv->proc_reg);
+	if (pre_voltage < 0) {
+		dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+		return pre_voltage;
+	}
+
+	pre_vsram = regulator_get_voltage(drv->sram_reg);
+	if (pre_vsram < 0) {
+		dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
+		return pre_vsram;
+	}
+
+	new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
+			  soc_data->sram_min_volt, soc_data->sram_max_volt);
+
+	do {
+		if (pre_voltage <= new_voltage) {
+			vsram = clamp(pre_voltage + soc_data->max_volt_shift,
+				      soc_data->sram_min_volt, new_vsram);
+			ret = regulator_set_voltage(drv->sram_reg, vsram,
+						    soc_data->sram_max_volt);
+			if (ret)
+				return ret;
+
+			if (vsram == soc_data->sram_max_volt ||
+			    new_vsram == soc_data->sram_min_volt)
+				voltage = new_voltage;
+			else
+				voltage = vsram - soc_data->min_volt_shift;
+
+			ret = regulator_set_voltage(drv->proc_reg, voltage,
+						    soc_data->proc_max_volt);
+			if (ret) {
+				regulator_set_voltage(drv->sram_reg, pre_vsram,
+						      soc_data->sram_max_volt);
+				return ret;
+			}
+		} else if (pre_voltage > new_voltage) {
+			voltage = max(new_voltage,
+				      pre_vsram - soc_data->max_volt_shift);
+			ret = regulator_set_voltage(drv->proc_reg, voltage,
+						    soc_data->proc_max_volt);
+			if (ret)
+				return ret;
+
+			if (voltage == new_voltage)
+				vsram = new_vsram;
+			else
+				vsram = max(new_vsram,
+					    voltage + soc_data->min_volt_shift);
+
+			ret = regulator_set_voltage(drv->sram_reg, vsram,
+						    soc_data->sram_max_volt);
+			if (ret) {
+				regulator_set_voltage(drv->proc_reg, pre_voltage,
+						      soc_data->proc_max_volt);
+				return ret;
+			}
+		}
+
+		pre_voltage = voltage;
+		pre_vsram = vsram;
+
+		if (--retry_max < 0) {
+			dev_err(dev,
+				"over loop count, failed to set voltage\n");
+			return -EINVAL;
+		}
+	} while (voltage != new_voltage || vsram != new_vsram);
+
+	return 0;
+}
+
+static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
+			      u32 flags)
+{
+	struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
+	struct clk *cci_pll = clk_get_parent(drv->cci_clk);
+	struct dev_pm_opp *opp;
+	unsigned long opp_rate;
+	int voltage, pre_voltage, inter_voltage, target_voltage, ret;
+
+	if (!drv)
+		return -EINVAL;
+
+	if (drv->pre_freq == *freq)
+		return 0;
+
+	inter_voltage = drv->inter_voltage;
+
+	opp_rate = *freq;
+	opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+	if (IS_ERR(opp)) {
+		dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
+		return PTR_ERR(opp);
+	}
+
+	mutex_lock(&drv->reg_lock);
+
+	voltage = dev_pm_opp_get_voltage(opp);
+	dev_pm_opp_put(opp);
+
+	pre_voltage = regulator_get_voltage(drv->proc_reg);
+	if (pre_voltage < 0) {
+		dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+		ret = pre_voltage;
+		goto out_unlock;
+	}
+
+	/* scale up: set voltage first then freq. */
+	target_voltage = max(inter_voltage, voltage);
+	if (pre_voltage <= target_voltage) {
+		ret = mtk_ccifreq_set_voltage(drv, target_voltage);
+		if (ret) {
+			dev_err(dev, "failed to scale up voltage\n");
+			goto out_restore_voltage;
+		}
+	}
+
+	/* switch the cci clock to intermediate clock source. */
+	ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
+	if (ret) {
+		dev_err(dev, "failed to re-parent cci clock\n");
+		goto out_restore_voltage;
+	}
+
+	/* set the original clock to target rate. */
+	ret = clk_set_rate(cci_pll, *freq);
+	if (ret) {
+		dev_err(dev, "failed to set cci pll rate: %d\n", ret);
+		clk_set_parent(drv->cci_clk, cci_pll);
+		goto out_restore_voltage;
+	}
+
+	/* switch the cci clock back to the original clock source. */
+	ret = clk_set_parent(drv->cci_clk, cci_pll);
+	if (ret) {
+		dev_err(dev, "failed to re-parent cci clock\n");
+		mtk_ccifreq_set_voltage(drv, inter_voltage);
+		goto out_unlock;
+	}
+
+	/*
+	 * If the new voltage is lower than the intermediate voltage or the
+	 * original voltage, scale down to the new voltage.
+	 */
+	if (voltage < inter_voltage || voltage < pre_voltage) {
+		ret = mtk_ccifreq_set_voltage(drv, voltage);
+		if (ret) {
+			dev_err(dev, "failed to scale down voltage\n");
+			goto out_unlock;
+		}
+	}
+
+	drv->pre_freq = *freq;
+	mutex_unlock(&drv->reg_lock);
+
+	return 0;
+
+out_restore_voltage:
+	mtk_ccifreq_set_voltage(drv, pre_voltage);
+
+out_unlock:
+	mutex_unlock(&drv->reg_lock);
+	return ret;
+}
+
+static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
+				    unsigned long event, void *data)
+{
+	struct dev_pm_opp *opp = data;
+	struct mtk_ccifreq_drv *drv;
+	unsigned long freq, volt;
+
+	drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
+
+	if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+		freq = dev_pm_opp_get_freq(opp);
+
+		mutex_lock(&drv->reg_lock);
+		/* current opp item is changed */
+		if (freq == drv->pre_freq) {
+			volt = dev_pm_opp_get_voltage(opp);
+			mtk_ccifreq_set_voltage(drv, volt);
+		}
+		mutex_unlock(&drv->reg_lock);
+	}
+
+	return 0;
+}
+
+static struct devfreq_dev_profile mtk_ccifreq_profile = {
+	.target = mtk_ccifreq_target,
+};
+
+static int mtk_ccifreq_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_ccifreq_drv *drv;
+	struct devfreq_passive_data *passive_data;
+	struct dev_pm_opp *opp;
+	unsigned long rate, opp_volt;
+	int ret;
+
+	drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+	if (!drv)
+		return -ENOMEM;
+
+	drv->dev = dev;
+	drv->soc_data = (const struct mtk_ccifreq_platform_data *)
+				of_device_get_match_data(&pdev->dev);
+	mutex_init(&drv->reg_lock);
+	platform_set_drvdata(pdev, drv);
+
+	drv->cci_clk = devm_clk_get(dev, "cci");
+	if (IS_ERR(drv->cci_clk)) {
+		ret = PTR_ERR(drv->cci_clk);
+		return dev_err_probe(dev, ret, "failed to get cci clk\n");
+	}
+
+	drv->inter_clk = devm_clk_get(dev, "intermediate");
+	if (IS_ERR(drv->inter_clk)) {
+		ret = PTR_ERR(drv->inter_clk);
+		return dev_err_probe(dev, ret,
+				     "failed to get intermediate clk\n");
+	}
+
+	drv->proc_reg = devm_regulator_get_optional(dev, "proc");
+	if (IS_ERR(drv->proc_reg)) {
+		ret = PTR_ERR(drv->proc_reg);
+		return dev_err_probe(dev, ret,
+				     "failed to get proc regulator\n");
+	}
+
+	ret = regulator_enable(drv->proc_reg);
+	if (ret) {
+		dev_err(dev, "failed to enable proc regulator\n");
+		return ret;
+	}
+
+	drv->sram_reg = devm_regulator_get_optional(dev, "sram");
+	if (IS_ERR(drv->sram_reg))
+		drv->sram_reg = NULL;
+	else {
+		ret = regulator_enable(drv->sram_reg);
+		if (ret) {
+			dev_err(dev, "failed to enable sram regulator\n");
+			goto out_free_resources;
+		}
+	}
+
+	/*
+	 * We assume min voltage is 0 and tracking target voltage using
+	 * min_volt_shift for each iteration.
+	 * The retry_max is 3 times of expected iteration count.
+	 */
+	drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
+					       drv->soc_data->proc_max_volt),
+					   drv->soc_data->min_volt_shift);
+
+	ret = clk_prepare_enable(drv->cci_clk);
+	if (ret)
+		goto out_free_resources;
+
+	ret = dev_pm_opp_of_add_table(dev);
+	if (ret) {
+		dev_err(dev, "failed to add opp table: %d\n", ret);
+		goto out_disable_cci_clk;
+	}
+
+	rate = clk_get_rate(drv->inter_clk);
+	opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+	if (IS_ERR(opp)) {
+		ret = PTR_ERR(opp);
+		dev_err(dev, "failed to get intermediate opp: %d\n", ret);
+		goto out_remove_opp_table;
+	}
+	drv->inter_voltage = dev_pm_opp_get_voltage(opp);
+	dev_pm_opp_put(opp);
+
+	rate = U32_MAX;
+	opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
+	if (IS_ERR(opp)) {
+		dev_err(dev, "failed to get opp\n");
+		ret = PTR_ERR(opp);
+		goto out_remove_opp_table;
+	}
+
+	opp_volt = dev_pm_opp_get_voltage(opp);
+	dev_pm_opp_put(opp);
+	ret = mtk_ccifreq_set_voltage(drv, opp_volt);
+	if (ret) {
+		dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
+			opp_volt);
+		goto out_remove_opp_table;
+	}
+
+	passive_data = devm_kzalloc(dev, sizeof(*passive_data), GFP_KERNEL);
+	if (!passive_data) {
+		ret = -ENOMEM;
+		goto out_remove_opp_table;
+	}
+
+	passive_data->parent_type = CPUFREQ_PARENT_DEV;
+	drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
+					       DEVFREQ_GOV_PASSIVE,
+					       passive_data);
+	if (IS_ERR(drv->devfreq)) {
+		ret = -EPROBE_DEFER;
+		dev_err(dev, "failed to add devfreq device: %ld\n",
+			PTR_ERR(drv->devfreq));
+		goto out_remove_opp_table;
+	}
+
+	drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
+	ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
+	if (ret) {
+		dev_err(dev, "failed to register opp notifier: %d\n", ret);
+		goto out_remove_opp_table;
+	}
+	return 0;
+
+out_remove_opp_table:
+	dev_pm_opp_of_remove_table(dev);
+
+out_disable_cci_clk:
+	clk_disable_unprepare(drv->cci_clk);
+
+out_free_resources:
+	if (regulator_is_enabled(drv->proc_reg))
+		regulator_disable(drv->proc_reg);
+	if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
+		regulator_disable(drv->sram_reg);
+
+	return ret;
+}
+
+static int mtk_ccifreq_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_ccifreq_drv *drv;
+
+	drv = platform_get_drvdata(pdev);
+
+	dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
+	dev_pm_opp_of_remove_table(dev);
+	clk_disable_unprepare(drv->cci_clk);
+	regulator_disable(drv->proc_reg);
+	if (drv->sram_reg)
+		regulator_disable(drv->sram_reg);
+
+	return 0;
+}
+
+static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
+	.min_volt_shift = 100000,
+	.max_volt_shift = 200000,
+	.proc_max_volt = 1150000,
+};
+
+static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
+	.min_volt_shift = 100000,
+	.max_volt_shift = 250000,
+	.proc_max_volt = 1118750,
+	.sram_min_volt = 850000,
+	.sram_max_volt = 1118750,
+};
+
+static const struct of_device_id mtk_ccifreq_machines[] = {
+	{ .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
+	{ .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
+
+static struct platform_driver mtk_ccifreq_platdrv = {
+	.probe	= mtk_ccifreq_probe,
+	.remove	= mtk_ccifreq_remove,
+	.driver = {
+		.name = "mtk-ccifreq",
+		.of_match_table = mtk_ccifreq_machines,
+	},
+};
+module_platform_driver(mtk_ccifreq_platdrv);
+
+MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
+MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/devfreq/sun8i-a33-mbus.c b/drivers/devfreq/sun8i-a33-mbus.c
index 13d32213139f..a21dfc92b7d0 100644
--- a/drivers/devfreq/sun8i-a33-mbus.c
+++ b/drivers/devfreq/sun8i-a33-mbus.c
@@ -337,6 +337,10 @@ static int sun8i_a33_mbus_probe(struct platform_device *pdev)
 	unsigned int max_state;
 	const char *err;
 	int i, ret;
+	struct dev_pm_opp_config config = {
+		.clk_names = (const char *[]){"dram"},
+		.clk_count = 1,
+	};
 
 	variant = device_get_match_data(dev);
 	if (!variant)
@@ -404,9 +408,9 @@ static int sun8i_a33_mbus_probe(struct platform_device *pdev)
 	priv->profile.freq_table	= priv->freq_table;
 	priv->profile.max_state		= max_state;
 
-	ret = devm_pm_opp_set_clkname(dev, "dram");
+	ret = devm_pm_opp_set_config(dev, &config);
 	if (ret) {
-		err = "failed to add OPP table\n";
+		err = "failed to set OPP config\n";
 		goto err_unlock_mbus;
 	}
 
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index 65ecf17a36f4..30382bdfc655 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -830,6 +830,10 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 	unsigned int i;
 	long rate;
 	int err;
+	struct dev_pm_opp_config config = {
+		.supported_hw = &hw_version,
+		.supported_hw_count = 1,
+	};
 
 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 	if (!tegra)
@@ -874,9 +878,9 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	err = devm_pm_opp_set_supported_hw(&pdev->dev, &hw_version, 1);
+	err = devm_pm_opp_set_config(&pdev->dev, &config);
 	if (err) {
-		dev_err(&pdev->dev, "Failed to set supported HW: %d\n", err);
+		dev_err(&pdev->dev, "Failed to set OPP config: %d\n", err);
 		return err;
 	}
 
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 4c9eb53ba3f8..70ec901edf2c 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-	 dma-resv.o
+	 dma-fence-unwrap.o dma-resv.o
 obj-$(CONFIG_DMABUF_HEAPS)	+= dma-heap.o
 obj-$(CONFIG_DMABUF_HEAPS)	+= heaps/
 obj-$(CONFIG_SYNC_FILE)		+= sync_file.o
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 32f55640890c..630133284e2b 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -20,6 +20,7 @@
 #include <linux/debugfs.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
+#include <linux/sync_file.h>
 #include <linux/poll.h>
 #include <linux/dma-resv.h>
 #include <linux/mm.h>
@@ -192,6 +193,9 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence)
  * Note that this only signals the completion of the respective fences, i.e. the
  * DMA transfers are complete. Cache flushing and any other necessary
  * preparations before CPU access can begin still need to happen.
+ *
+ * As an alternative to poll(), the set of fences on DMA buffer can be
+ * exported as a &sync_file using &dma_buf_sync_file_export.
  */
 
 static void dma_buf_poll_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
@@ -326,6 +330,101 @@ static long dma_buf_set_name(struct dma_buf *dmabuf, const char __user *buf)
 	return 0;
 }
 
+#if IS_ENABLED(CONFIG_SYNC_FILE)
+static long dma_buf_export_sync_file(struct dma_buf *dmabuf,
+				     void __user *user_data)
+{
+	struct dma_buf_export_sync_file arg;
+	enum dma_resv_usage usage;
+	struct dma_fence *fence = NULL;
+	struct sync_file *sync_file;
+	int fd, ret;
+
+	if (copy_from_user(&arg, user_data, sizeof(arg)))
+		return -EFAULT;
+
+	if (arg.flags & ~DMA_BUF_SYNC_RW)
+		return -EINVAL;
+
+	if ((arg.flags & DMA_BUF_SYNC_RW) == 0)
+		return -EINVAL;
+
+	fd = get_unused_fd_flags(O_CLOEXEC);
+	if (fd < 0)
+		return fd;
+
+	usage = dma_resv_usage_rw(arg.flags & DMA_BUF_SYNC_WRITE);
+	ret = dma_resv_get_singleton(dmabuf->resv, usage, &fence);
+	if (ret)
+		goto err_put_fd;
+
+	if (!fence)
+		fence = dma_fence_get_stub();
+
+	sync_file = sync_file_create(fence);
+
+	dma_fence_put(fence);
+
+	if (!sync_file) {
+		ret = -ENOMEM;
+		goto err_put_fd;
+	}
+
+	arg.fd = fd;
+	if (copy_to_user(user_data, &arg, sizeof(arg))) {
+		ret = -EFAULT;
+		goto err_put_file;
+	}
+
+	fd_install(fd, sync_file->file);
+
+	return 0;
+
+err_put_file:
+	fput(sync_file->file);
+err_put_fd:
+	put_unused_fd(fd);
+	return ret;
+}
+
+static long dma_buf_import_sync_file(struct dma_buf *dmabuf,
+				     const void __user *user_data)
+{
+	struct dma_buf_import_sync_file arg;
+	struct dma_fence *fence;
+	enum dma_resv_usage usage;
+	int ret = 0;
+
+	if (copy_from_user(&arg, user_data, sizeof(arg)))
+		return -EFAULT;
+
+	if (arg.flags & ~DMA_BUF_SYNC_RW)
+		return -EINVAL;
+
+	if ((arg.flags & DMA_BUF_SYNC_RW) == 0)
+		return -EINVAL;
+
+	fence = sync_file_get_fence(arg.fd);
+	if (!fence)
+		return -EINVAL;
+
+	usage = (arg.flags & DMA_BUF_SYNC_WRITE) ? DMA_RESV_USAGE_WRITE :
+						   DMA_RESV_USAGE_READ;
+
+	dma_resv_lock(dmabuf->resv, NULL);
+
+	ret = dma_resv_reserve_fences(dmabuf->resv, 1);
+	if (!ret)
+		dma_resv_add_fence(dmabuf->resv, fence, usage);
+
+	dma_resv_unlock(dmabuf->resv);
+
+	dma_fence_put(fence);
+
+	return ret;
+}
+#endif
+
 static long dma_buf_ioctl(struct file *file,
 			  unsigned int cmd, unsigned long arg)
 {
@@ -369,6 +468,13 @@ static long dma_buf_ioctl(struct file *file,
 	case DMA_BUF_SET_NAME_B:
 		return dma_buf_set_name(dmabuf, (const char __user *)arg);
 
+#if IS_ENABLED(CONFIG_SYNC_FILE)
+	case DMA_BUF_IOCTL_EXPORT_SYNC_FILE:
+		return dma_buf_export_sync_file(dmabuf, (void __user *)arg);
+	case DMA_BUF_IOCTL_IMPORT_SYNC_FILE:
+		return dma_buf_import_sync_file(dmabuf, (const void __user *)arg);
+#endif
+
 	default:
 		return -ENOTTY;
 	}
@@ -1359,7 +1465,7 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused)
 		return ret;
 
 	seq_puts(s, "\nDma-buf Objects:\n");
-	seq_printf(s, "%-8s\t%-8s\t%-8s\t%-8s\texp_name\t%-8s\n",
+	seq_printf(s, "%-8s\t%-8s\t%-8s\t%-8s\texp_name\t%-8s\tname\n",
 		   "size", "flags", "mode", "count", "ino");
 
 	list_for_each_entry(buf_obj, &db_list.head, list_node) {
@@ -1376,7 +1482,7 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused)
 				file_count(buf_obj->file),
 				buf_obj->exp_name,
 				file_inode(buf_obj->file)->i_ino,
-				buf_obj->name ?: "");
+				buf_obj->name ?: "<none>");
 		spin_unlock(&buf_obj->name_lock);
 
 		dma_resv_describe(buf_obj->resv, s);
diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c
index 06f8ef97c6e8..a0d920576ba6 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -62,8 +62,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
 			replacement = NULL;
 		}
 
-		tmp = cmpxchg((struct dma_fence __force **)&chain->prev,
-			      prev, replacement);
+		tmp = unrcu_pointer(cmpxchg(&chain->prev, RCU_INITIALIZER(prev),
+					     RCU_INITIALIZER(replacement)));
 		if (tmp == prev)
 			dma_fence_put(tmp);
 		else
diff --git a/drivers/dma-buf/dma-fence-unwrap.c b/drivers/dma-buf/dma-fence-unwrap.c
new file mode 100644
index 000000000000..502a65ea6d44
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-unwrap.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dma-fence-util: misc functions for dma_fence objects
+ *
+ * Copyright (C) 2022 Advanced Micro Devices, Inc.
+ * Authors:
+ *	Christian König <christian.koenig@amd.com>
+ */
+
+#include <linux/dma-fence.h>
+#include <linux/dma-fence-array.h>
+#include <linux/dma-fence-chain.h>
+#include <linux/dma-fence-unwrap.h>
+#include <linux/slab.h>
+
+/* Internal helper to start new array iteration, don't use directly */
+static struct dma_fence *
+__dma_fence_unwrap_array(struct dma_fence_unwrap *cursor)
+{
+	cursor->array = dma_fence_chain_contained(cursor->chain);
+	cursor->index = 0;
+	return dma_fence_array_first(cursor->array);
+}
+
+/**
+ * dma_fence_unwrap_first - return the first fence from fence containers
+ * @head: the entrypoint into the containers
+ * @cursor: current position inside the containers
+ *
+ * Unwraps potential dma_fence_chain/dma_fence_array containers and return the
+ * first fence.
+ */
+struct dma_fence *dma_fence_unwrap_first(struct dma_fence *head,
+					 struct dma_fence_unwrap *cursor)
+{
+	cursor->chain = dma_fence_get(head);
+	return __dma_fence_unwrap_array(cursor);
+}
+EXPORT_SYMBOL_GPL(dma_fence_unwrap_first);
+
+/**
+ * dma_fence_unwrap_next - return the next fence from a fence containers
+ * @cursor: current position inside the containers
+ *
+ * Continue unwrapping the dma_fence_chain/dma_fence_array containers and return
+ * the next fence from them.
+ */
+struct dma_fence *dma_fence_unwrap_next(struct dma_fence_unwrap *cursor)
+{
+	struct dma_fence *tmp;
+
+	++cursor->index;
+	tmp = dma_fence_array_next(cursor->array, cursor->index);
+	if (tmp)
+		return tmp;
+
+	cursor->chain = dma_fence_chain_walk(cursor->chain);
+	return __dma_fence_unwrap_array(cursor);
+}
+EXPORT_SYMBOL_GPL(dma_fence_unwrap_next);
+
+/* Implementation for the dma_fence_merge() marco, don't use directly */
+struct dma_fence *__dma_fence_unwrap_merge(unsigned int num_fences,
+					   struct dma_fence **fences,
+					   struct dma_fence_unwrap *iter)
+{
+	struct dma_fence_array *result;
+	struct dma_fence *tmp, **array;
+	unsigned int i;
+	size_t count;
+
+	count = 0;
+	for (i = 0; i < num_fences; ++i) {
+		dma_fence_unwrap_for_each(tmp, &iter[i], fences[i])
+			++count;
+	}
+
+	if (count == 0)
+		return dma_fence_get_stub();
+
+	array = kmalloc_array(count, sizeof(*array), GFP_KERNEL);
+	if (!array)
+		return NULL;
+
+	/*
+	 * This trashes the input fence array and uses it as position for the
+	 * following merge loop. This works because the dma_fence_merge()
+	 * wrapper macro is creating this temporary array on the stack together
+	 * with the iterators.
+	 */
+	for (i = 0; i < num_fences; ++i)
+		fences[i] = dma_fence_unwrap_first(fences[i], &iter[i]);
+
+	count = 0;
+	do {
+		unsigned int sel;
+
+restart:
+		tmp = NULL;
+		for (i = 0; i < num_fences; ++i) {
+			struct dma_fence *next;
+
+			while (fences[i] && dma_fence_is_signaled(fences[i]))
+				fences[i] = dma_fence_unwrap_next(&iter[i]);
+
+			next = fences[i];
+			if (!next)
+				continue;
+
+			/*
+			 * We can't guarantee that inpute fences are ordered by
+			 * context, but it is still quite likely when this
+			 * function is used multiple times. So attempt to order
+			 * the fences by context as we pass over them and merge
+			 * fences with the same context.
+			 */
+			if (!tmp || tmp->context > next->context) {
+				tmp = next;
+				sel = i;
+
+			} else if (tmp->context < next->context) {
+				continue;
+
+			} else if (dma_fence_is_later(tmp, next)) {
+				fences[i] = dma_fence_unwrap_next(&iter[i]);
+				goto restart;
+			} else {
+				fences[sel] = dma_fence_unwrap_next(&iter[sel]);
+				goto restart;
+			}
+		}
+
+		if (tmp) {
+			array[count++] = dma_fence_get(tmp);
+			fences[sel] = dma_fence_unwrap_next(&iter[sel]);
+		}
+	} while (tmp);
+
+	if (count == 0) {
+		tmp = dma_fence_get_stub();
+		goto return_tmp;
+	}
+
+	if (count == 1) {
+		tmp = array[0];
+		goto return_tmp;
+	}
+
+	result = dma_fence_array_create(count, array,
+					dma_fence_context_alloc(1),
+					1, false);
+	if (!result) {
+		tmp = NULL;
+		goto return_tmp;
+	}
+	return &result->base;
+
+return_tmp:
+	kfree(array);
+	return tmp;
+}
+EXPORT_SYMBOL_GPL(__dma_fence_unwrap_merge);
diff --git a/drivers/dma-buf/st-dma-fence-unwrap.c b/drivers/dma-buf/st-dma-fence-unwrap.c
index 039f016b57be..4105d5ea8dde 100644
--- a/drivers/dma-buf/st-dma-fence-unwrap.c
+++ b/drivers/dma-buf/st-dma-fence-unwrap.c
@@ -4,27 +4,19 @@
  * Copyright (C) 2022 Advanced Micro Devices, Inc.
  */
 
+#include <linux/dma-fence.h>
+#include <linux/dma-fence-array.h>
+#include <linux/dma-fence-chain.h>
 #include <linux/dma-fence-unwrap.h>
-#if 0
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/mm.h>
-#include <linux/sched/signal.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/random.h>
-#endif
 
 #include "selftest.h"
 
 #define CHAIN_SZ (4 << 10)
 
-static inline struct mock_fence {
+struct mock_fence {
 	struct dma_fence base;
 	spinlock_t lock;
-} *to_mock_fence(struct dma_fence *f) {
-	return container_of(f, struct mock_fence, base);
-}
+};
 
 static const char *mock_name(struct dma_fence *f)
 {
@@ -45,7 +37,8 @@ static struct dma_fence *mock_fence(void)
 		return NULL;
 
 	spin_lock_init(&f->lock);
-	dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0);
+	dma_fence_init(&f->base, &mock_ops, &f->lock,
+		       dma_fence_context_alloc(1), 1);
 
 	return &f->base;
 }
@@ -59,7 +52,7 @@ static struct dma_fence *mock_array(unsigned int num_fences, ...)
 
 	fences = kcalloc(num_fences, sizeof(*fences), GFP_KERNEL);
 	if (!fences)
-		return NULL;
+		goto error_put;
 
 	va_start(valist, num_fences);
 	for (i = 0; i < num_fences; ++i)
@@ -70,13 +63,17 @@ static struct dma_fence *mock_array(unsigned int num_fences, ...)
 				       dma_fence_context_alloc(1),
 				       1, false);
 	if (!array)
-		goto cleanup;
+		goto error_free;
 	return &array->base;
 
-cleanup:
-	for (i = 0; i < num_fences; ++i)
-		dma_fence_put(fences[i]);
+error_free:
 	kfree(fences);
+
+error_put:
+	va_start(valist, num_fences);
+	for (i = 0; i < num_fences; ++i)
+		dma_fence_put(va_arg(valist, typeof(*fences)));
+	va_end(valist);
 	return NULL;
 }
 
@@ -113,7 +110,6 @@ static int sanitycheck(void *arg)
 	if (!chain)
 		return -ENOMEM;
 
-	dma_fence_signal(f);
 	dma_fence_put(chain);
 	return err;
 }
@@ -154,10 +150,8 @@ static int unwrap_array(void *arg)
 		err = -EINVAL;
 	}
 
-	dma_fence_signal(f1);
-	dma_fence_signal(f2);
 	dma_fence_put(array);
-	return 0;
+	return err;
 }
 
 static int unwrap_chain(void *arg)
@@ -196,10 +190,8 @@ static int unwrap_chain(void *arg)
 		err = -EINVAL;
 	}
 
-	dma_fence_signal(f1);
-	dma_fence_signal(f2);
 	dma_fence_put(chain);
-	return 0;
+	return err;
 }
 
 static int unwrap_chain_array(void *arg)
@@ -242,10 +234,115 @@ static int unwrap_chain_array(void *arg)
 		err = -EINVAL;
 	}
 
-	dma_fence_signal(f1);
-	dma_fence_signal(f2);
 	dma_fence_put(chain);
-	return 0;
+	return err;
+}
+
+static int unwrap_merge(void *arg)
+{
+	struct dma_fence *fence, *f1, *f2, *f3;
+	struct dma_fence_unwrap iter;
+	int err = 0;
+
+	f1 = mock_fence();
+	if (!f1)
+		return -ENOMEM;
+
+	f2 = mock_fence();
+	if (!f2) {
+		err = -ENOMEM;
+		goto error_put_f1;
+	}
+
+	f3 = dma_fence_unwrap_merge(f1, f2);
+	if (!f3) {
+		err = -ENOMEM;
+		goto error_put_f2;
+	}
+
+	dma_fence_unwrap_for_each(fence, &iter, f3) {
+		if (fence == f1) {
+			dma_fence_put(f1);
+			f1 = NULL;
+		} else if (fence == f2) {
+			dma_fence_put(f2);
+			f2 = NULL;
+		} else {
+			pr_err("Unexpected fence!\n");
+			err = -EINVAL;
+		}
+	}
+
+	if (f1 || f2) {
+		pr_err("Not all fences seen!\n");
+		err = -EINVAL;
+	}
+
+	dma_fence_put(f3);
+error_put_f2:
+	dma_fence_put(f2);
+error_put_f1:
+	dma_fence_put(f1);
+	return err;
+}
+
+static int unwrap_merge_complex(void *arg)
+{
+	struct dma_fence *fence, *f1, *f2, *f3, *f4, *f5;
+	struct dma_fence_unwrap iter;
+	int err = -ENOMEM;
+
+	f1 = mock_fence();
+	if (!f1)
+		return -ENOMEM;
+
+	f2 = mock_fence();
+	if (!f2)
+		goto error_put_f1;
+
+	f3 = dma_fence_unwrap_merge(f1, f2);
+	if (!f3)
+		goto error_put_f2;
+
+	/* The resulting array has the fences in reverse */
+	f4 = dma_fence_unwrap_merge(f2, f1);
+	if (!f4)
+		goto error_put_f3;
+
+	/* Signaled fences should be filtered, the two arrays merged. */
+	f5 = dma_fence_unwrap_merge(f3, f4, dma_fence_get_stub());
+	if (!f5)
+		goto error_put_f4;
+
+	err = 0;
+	dma_fence_unwrap_for_each(fence, &iter, f5) {
+		if (fence == f1) {
+			dma_fence_put(f1);
+			f1 = NULL;
+		} else if (fence == f2) {
+			dma_fence_put(f2);
+			f2 = NULL;
+		} else {
+			pr_err("Unexpected fence!\n");
+			err = -EINVAL;
+		}
+	}
+
+	if (f1 || f2) {
+		pr_err("Not all fences seen!\n");
+		err = -EINVAL;
+	}
+
+	dma_fence_put(f5);
+error_put_f4:
+	dma_fence_put(f4);
+error_put_f3:
+	dma_fence_put(f3);
+error_put_f2:
+	dma_fence_put(f2);
+error_put_f1:
+	dma_fence_put(f1);
+	return err;
 }
 
 int dma_fence_unwrap(void)
@@ -255,6 +352,8 @@ int dma_fence_unwrap(void)
 		SUBTEST(unwrap_array),
 		SUBTEST(unwrap_chain),
 		SUBTEST(unwrap_chain_array),
+		SUBTEST(unwrap_merge),
+		SUBTEST(unwrap_merge_complex),
 	};
 
 	return subtests(tests, NULL);
diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
index 0fe564539166..3ebec19a8e02 100644
--- a/drivers/dma-buf/sync_file.c
+++ b/drivers/dma-buf/sync_file.c
@@ -146,50 +146,6 @@ char *sync_file_get_name(struct sync_file *sync_file, char *buf, int len)
 	return buf;
 }
 
-static int sync_file_set_fence(struct sync_file *sync_file,
-			       struct dma_fence **fences, int num_fences)
-{
-	struct dma_fence_array *array;
-
-	/*
-	 * The reference for the fences in the new sync_file and held
-	 * in add_fence() during the merge procedure, so for num_fences == 1
-	 * we already own a new reference to the fence. For num_fence > 1
-	 * we own the reference of the dma_fence_array creation.
-	 */
-
-	if (num_fences == 0) {
-		sync_file->fence = dma_fence_get_stub();
-		kfree(fences);
-
-	} else if (num_fences == 1) {
-		sync_file->fence = fences[0];
-		kfree(fences);
-
-	} else {
-		array = dma_fence_array_create(num_fences, fences,
-					       dma_fence_context_alloc(1),
-					       1, false);
-		if (!array)
-			return -ENOMEM;
-
-		sync_file->fence = &array->base;
-	}
-
-	return 0;
-}
-
-static void add_fence(struct dma_fence **fences,
-		      int *i, struct dma_fence *fence)
-{
-	fences[*i] = fence;
-
-	if (!dma_fence_is_signaled(fence)) {
-		dma_fence_get(fence);
-		(*i)++;
-	}
-}
-
 /**
  * sync_file_merge() - merge two sync_files
  * @name:	name of new fence
@@ -203,84 +159,21 @@ static void add_fence(struct dma_fence **fences,
 static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
 					 struct sync_file *b)
 {
-	struct dma_fence *a_fence, *b_fence, **fences;
-	struct dma_fence_unwrap a_iter, b_iter;
-	unsigned int index, num_fences;
 	struct sync_file *sync_file;
+	struct dma_fence *fence;
 
 	sync_file = sync_file_alloc();
 	if (!sync_file)
 		return NULL;
 
-	num_fences = 0;
-	dma_fence_unwrap_for_each(a_fence, &a_iter, a->fence)
-		++num_fences;
-	dma_fence_unwrap_for_each(b_fence, &b_iter, b->fence)
-		++num_fences;
-
-	if (num_fences > INT_MAX)
-		goto err_free_sync_file;
-
-	fences = kcalloc(num_fences, sizeof(*fences), GFP_KERNEL);
-	if (!fences)
-		goto err_free_sync_file;
-
-	/*
-	 * We can't guarantee that fences in both a and b are ordered, but it is
-	 * still quite likely.
-	 *
-	 * So attempt to order the fences as we pass over them and merge fences
-	 * with the same context.
-	 */
-
-	index = 0;
-	for (a_fence = dma_fence_unwrap_first(a->fence, &a_iter),
-	     b_fence = dma_fence_unwrap_first(b->fence, &b_iter);
-	     a_fence || b_fence; ) {
-
-		if (!b_fence) {
-			add_fence(fences, &index, a_fence);
-			a_fence = dma_fence_unwrap_next(&a_iter);
-
-		} else if (!a_fence) {
-			add_fence(fences, &index, b_fence);
-			b_fence = dma_fence_unwrap_next(&b_iter);
-
-		} else if (a_fence->context < b_fence->context) {
-			add_fence(fences, &index, a_fence);
-			a_fence = dma_fence_unwrap_next(&a_iter);
-
-		} else if (b_fence->context < a_fence->context) {
-			add_fence(fences, &index, b_fence);
-			b_fence = dma_fence_unwrap_next(&b_iter);
-
-		} else if (__dma_fence_is_later(a_fence->seqno, b_fence->seqno,
-						a_fence->ops)) {
-			add_fence(fences, &index, a_fence);
-			a_fence = dma_fence_unwrap_next(&a_iter);
-			b_fence = dma_fence_unwrap_next(&b_iter);
-
-		} else {
-			add_fence(fences, &index, b_fence);
-			a_fence = dma_fence_unwrap_next(&a_iter);
-			b_fence = dma_fence_unwrap_next(&b_iter);
-		}
+	fence = dma_fence_unwrap_merge(a->fence, b->fence);
+	if (!fence) {
+		fput(sync_file->file);
+		return NULL;
 	}
-
-	if (sync_file_set_fence(sync_file, fences, index) < 0)
-		goto err_put_fences;
-
+	sync_file->fence = fence;
 	strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name));
 	return sync_file;
-
-err_put_fences:
-	while (index)
-		dma_fence_put(fences[--index]);
-	kfree(fences);
-
-err_free_sync_file:
-	fput(sync_file->file);
-	return NULL;
 }
 
 static int sync_file_release(struct inode *inode, struct file *file)
diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c
index e7330684d3b8..38e8767ec371 100644
--- a/drivers/dma-buf/udmabuf.c
+++ b/drivers/dma-buf/udmabuf.c
@@ -32,8 +32,11 @@ static vm_fault_t udmabuf_vm_fault(struct vm_fault *vmf)
 {
 	struct vm_area_struct *vma = vmf->vma;
 	struct udmabuf *ubuf = vma->vm_private_data;
+	pgoff_t pgoff = vmf->pgoff;
 
-	vmf->page = ubuf->pages[vmf->pgoff];
+	if (pgoff >= ubuf->pagecount)
+		return VM_FAULT_SIGBUS;
+	vmf->page = ubuf->pages[pgoff];
 	get_page(vmf->page);
 	return 0;
 }
@@ -365,7 +368,23 @@ static struct miscdevice udmabuf_misc = {
 
 static int __init udmabuf_dev_init(void)
 {
-	return misc_register(&udmabuf_misc);
+	int ret;
+
+	ret = misc_register(&udmabuf_misc);
+	if (ret < 0) {
+		pr_err("Could not initialize udmabuf device\n");
+		return ret;
+	}
+
+	ret = dma_coerce_mask_and_coherent(udmabuf_misc.this_device,
+					   DMA_BIT_MASK(64));
+	if (ret < 0) {
+		pr_err("Could not setup DMA mask for udmabuf device\n");
+		misc_deregister(&udmabuf_misc);
+		return ret;
+	}
+
+	return 0;
 }
 
 static void __exit udmabuf_dev_exit(void)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 487ed4ddc3be..a06d2a7627aa 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -85,6 +85,14 @@ config AMCC_PPC440SPE_ADMA
 	help
 	  Enable support for the AMCC PPC440SPe RAID engines.
 
+config APPLE_ADMAC
+	tristate "Apple ADMAC support"
+	depends on ARCH_APPLE || COMPILE_TEST
+	select DMA_ENGINE
+	default ARCH_APPLE
+	help
+	  Enable support for Audio DMA Controller found on Apple Silicon SoCs.
+
 config AT_HDMAC
 	tristate "Atmel AHB DMA support"
 	depends on ARCH_AT91
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2f1b87ffd7ab..10f7d4241001 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o
 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_AMD_PTDMA) += ptdma/
+obj-$(CONFIG_APPLE_ADMAC) += apple-admac.o
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
 obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o
diff --git a/drivers/dma/apple-admac.c b/drivers/dma/apple-admac.c
new file mode 100644
index 000000000000..d1f74a3aa999
--- /dev/null
+++ b/drivers/dma/apple-admac.c
@@ -0,0 +1,818 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Driver for Audio DMA Controller (ADMAC) on t8103 (M1) and other Apple chips
+ *
+ * Copyright (C) The Asahi Linux Contributors
+ */
+
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include "dmaengine.h"
+
+#define NCHANNELS_MAX	64
+#define IRQ_NOUTPUTS	4
+
+#define RING_WRITE_SLOT		GENMASK(1, 0)
+#define RING_READ_SLOT		GENMASK(5, 4)
+#define RING_FULL		BIT(9)
+#define RING_EMPTY		BIT(8)
+#define RING_ERR		BIT(10)
+
+#define STATUS_DESC_DONE	BIT(0)
+#define STATUS_ERR		BIT(6)
+
+#define FLAG_DESC_NOTIFY	BIT(16)
+
+#define REG_TX_START		0x0000
+#define REG_TX_STOP		0x0004
+#define REG_RX_START		0x0008
+#define REG_RX_STOP		0x000c
+
+#define REG_CHAN_CTL(ch)	(0x8000 + (ch) * 0x200)
+#define REG_CHAN_CTL_RST_RINGS	BIT(0)
+
+#define REG_DESC_RING(ch)	(0x8070 + (ch) * 0x200)
+#define REG_REPORT_RING(ch)	(0x8074 + (ch) * 0x200)
+
+#define REG_RESIDUE(ch)		(0x8064 + (ch) * 0x200)
+
+#define REG_BUS_WIDTH(ch)	(0x8040 + (ch) * 0x200)
+
+#define BUS_WIDTH_8BIT		0x00
+#define BUS_WIDTH_16BIT		0x01
+#define BUS_WIDTH_32BIT		0x02
+#define BUS_WIDTH_FRAME_2_WORDS	0x10
+#define BUS_WIDTH_FRAME_4_WORDS	0x20
+
+#define CHAN_BUFSIZE		0x8000
+
+#define REG_CHAN_FIFOCTL(ch)	(0x8054 + (ch) * 0x200)
+#define CHAN_FIFOCTL_LIMIT	GENMASK(31, 16)
+#define CHAN_FIFOCTL_THRESHOLD	GENMASK(15, 0)
+
+#define REG_DESC_WRITE(ch)	(0x10000 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
+#define REG_REPORT_READ(ch)	(0x10100 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
+
+#define REG_TX_INTSTATE(idx)		(0x0030 + (idx) * 4)
+#define REG_RX_INTSTATE(idx)		(0x0040 + (idx) * 4)
+#define REG_CHAN_INTSTATUS(ch, idx)	(0x8010 + (ch) * 0x200 + (idx) * 4)
+#define REG_CHAN_INTMASK(ch, idx)	(0x8020 + (ch) * 0x200 + (idx) * 4)
+
+struct admac_data;
+struct admac_tx;
+
+struct admac_chan {
+	unsigned int no;
+	struct admac_data *host;
+	struct dma_chan chan;
+	struct tasklet_struct tasklet;
+
+	spinlock_t lock;
+	struct admac_tx *current_tx;
+	int nperiod_acks;
+
+	/*
+	 * We maintain a 'submitted' and 'issued' list mainly for interface
+	 * correctness. Typical use of the driver (per channel) will be
+	 * prepping, submitting and issuing a single cyclic transaction which
+	 * will stay current until terminate_all is called.
+	 */
+	struct list_head submitted;
+	struct list_head issued;
+
+	struct list_head to_free;
+};
+
+struct admac_data {
+	struct dma_device dma;
+	struct device *dev;
+	__iomem void *base;
+
+	int irq_index;
+	int nchannels;
+	struct admac_chan channels[];
+};
+
+struct admac_tx {
+	struct dma_async_tx_descriptor tx;
+	bool cyclic;
+	dma_addr_t buf_addr;
+	dma_addr_t buf_end;
+	size_t buf_len;
+	size_t period_len;
+
+	size_t submitted_pos;
+	size_t reclaimed_pos;
+
+	struct list_head node;
+};
+
+static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val)
+{
+	void __iomem *addr = ad->base + reg;
+	u32 curr = readl_relaxed(addr);
+
+	writel_relaxed((curr & ~mask) | (val & mask), addr);
+}
+
+static struct admac_chan *to_admac_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct admac_chan, chan);
+}
+
+static struct admac_tx *to_admac_tx(struct dma_async_tx_descriptor *tx)
+{
+	return container_of(tx, struct admac_tx, tx);
+}
+
+static enum dma_transfer_direction admac_chan_direction(int channo)
+{
+	/* Channel directions are hardwired */
+	return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
+}
+
+static dma_cookie_t admac_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct admac_tx *adtx = to_admac_tx(tx);
+	struct admac_chan *adchan = to_admac_chan(tx->chan);
+	unsigned long flags;
+	dma_cookie_t cookie;
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	cookie = dma_cookie_assign(tx);
+	list_add_tail(&adtx->node, &adchan->submitted);
+	spin_unlock_irqrestore(&adchan->lock, flags);
+
+	return cookie;
+}
+
+static int admac_desc_free(struct dma_async_tx_descriptor *tx)
+{
+	kfree(to_admac_tx(tx));
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *admac_prep_dma_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_transfer_direction direction,
+		unsigned long flags)
+{
+	struct admac_chan *adchan = container_of(chan, struct admac_chan, chan);
+	struct admac_tx *adtx;
+
+	if (direction != admac_chan_direction(adchan->no))
+		return NULL;
+
+	adtx = kzalloc(sizeof(*adtx), GFP_NOWAIT);
+	if (!adtx)
+		return NULL;
+
+	adtx->cyclic = true;
+
+	adtx->buf_addr = buf_addr;
+	adtx->buf_len = buf_len;
+	adtx->buf_end = buf_addr + buf_len;
+	adtx->period_len = period_len;
+
+	adtx->submitted_pos = 0;
+	adtx->reclaimed_pos = 0;
+
+	dma_async_tx_descriptor_init(&adtx->tx, chan);
+	adtx->tx.tx_submit = admac_tx_submit;
+	adtx->tx.desc_free = admac_desc_free;
+
+	return &adtx->tx;
+}
+
+/*
+ * Write one hardware descriptor for a dmaengine cyclic transaction.
+ */
+static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,
+					struct admac_tx *tx)
+{
+	dma_addr_t addr;
+
+	addr = tx->buf_addr + (tx->submitted_pos % tx->buf_len);
+
+	/* If happens means we have buggy code */
+	WARN_ON_ONCE(addr + tx->period_len > tx->buf_end);
+
+	dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n",
+		channo, &addr, tx->period_len, FLAG_DESC_NOTIFY);
+
+	writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
+	writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
+	writel_relaxed(tx->period_len,      ad->base + REG_DESC_WRITE(channo));
+	writel_relaxed(FLAG_DESC_NOTIFY,    ad->base + REG_DESC_WRITE(channo));
+
+	tx->submitted_pos += tx->period_len;
+	tx->submitted_pos %= 2 * tx->buf_len;
+}
+
+/*
+ * Write all the hardware descriptors for a dmaengine cyclic
+ * transaction there is space for.
+ */
+static void admac_cyclic_write_desc(struct admac_data *ad, int channo,
+				    struct admac_tx *tx)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
+			break;
+		admac_cyclic_write_one_desc(ad, channo, tx);
+	}
+}
+
+static int admac_ring_noccupied_slots(int ringval)
+{
+	int wrslot = FIELD_GET(RING_WRITE_SLOT, ringval);
+	int rdslot = FIELD_GET(RING_READ_SLOT, ringval);
+
+	if (wrslot != rdslot) {
+		return (wrslot + 4 - rdslot) % 4;
+	} else {
+		WARN_ON((ringval & (RING_FULL | RING_EMPTY)) == 0);
+
+		if (ringval & RING_FULL)
+			return 4;
+		else
+			return 0;
+	}
+}
+
+/*
+ * Read from hardware the residue of a cyclic dmaengine transaction.
+ */
+static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,
+				     struct admac_tx *adtx)
+{
+	u32 ring1, ring2;
+	u32 residue1, residue2;
+	int nreports;
+	size_t pos;
+
+	ring1 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));
+	residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
+	ring2 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));
+	residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
+
+	if (residue2 > residue1) {
+		/*
+		 * Controller must have loaded next descriptor between
+		 * the two residue reads
+		 */
+		nreports = admac_ring_noccupied_slots(ring1) + 1;
+	} else {
+		/* No descriptor load between the two reads, ring2 is safe to use */
+		nreports = admac_ring_noccupied_slots(ring2);
+	}
+
+	pos = adtx->reclaimed_pos + adtx->period_len * (nreports + 1) - residue2;
+
+	return adtx->buf_len - pos % adtx->buf_len;
+}
+
+static enum dma_status admac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
+				       struct dma_tx_state *txstate)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+	struct admac_data *ad = adchan->host;
+	struct admac_tx *adtx;
+
+	enum dma_status ret;
+	size_t residue;
+	unsigned long flags;
+
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret == DMA_COMPLETE || !txstate)
+		return ret;
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	adtx = adchan->current_tx;
+
+	if (adtx && adtx->tx.cookie == cookie) {
+		ret = DMA_IN_PROGRESS;
+		residue = admac_cyclic_read_residue(ad, adchan->no, adtx);
+	} else {
+		ret = DMA_IN_PROGRESS;
+		residue = 0;
+		list_for_each_entry(adtx, &adchan->issued, node) {
+			if (adtx->tx.cookie == cookie) {
+				residue = adtx->buf_len;
+				break;
+			}
+		}
+	}
+	spin_unlock_irqrestore(&adchan->lock, flags);
+
+	dma_set_residue(txstate, residue);
+	return ret;
+}
+
+static void admac_start_chan(struct admac_chan *adchan)
+{
+	struct admac_data *ad = adchan->host;
+	u32 startbit = 1 << (adchan->no / 2);
+
+	writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
+		       ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
+	writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
+		       ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
+
+	switch (admac_chan_direction(adchan->no)) {
+	case DMA_MEM_TO_DEV:
+		writel_relaxed(startbit, ad->base + REG_TX_START);
+		break;
+	case DMA_DEV_TO_MEM:
+		writel_relaxed(startbit, ad->base + REG_RX_START);
+		break;
+	default:
+		break;
+	}
+	dev_dbg(adchan->host->dev, "ch%d start\n", adchan->no);
+}
+
+static void admac_stop_chan(struct admac_chan *adchan)
+{
+	struct admac_data *ad = adchan->host;
+	u32 stopbit = 1 << (adchan->no / 2);
+
+	switch (admac_chan_direction(adchan->no)) {
+	case DMA_MEM_TO_DEV:
+		writel_relaxed(stopbit, ad->base + REG_TX_STOP);
+		break;
+	case DMA_DEV_TO_MEM:
+		writel_relaxed(stopbit, ad->base + REG_RX_STOP);
+		break;
+	default:
+		break;
+	}
+	dev_dbg(adchan->host->dev, "ch%d stop\n", adchan->no);
+}
+
+static void admac_reset_rings(struct admac_chan *adchan)
+{
+	struct admac_data *ad = adchan->host;
+
+	writel_relaxed(REG_CHAN_CTL_RST_RINGS,
+		       ad->base + REG_CHAN_CTL(adchan->no));
+	writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
+}
+
+static void admac_start_current_tx(struct admac_chan *adchan)
+{
+	struct admac_data *ad = adchan->host;
+	int ch = adchan->no;
+
+	admac_reset_rings(adchan);
+	writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
+
+	admac_cyclic_write_one_desc(ad, ch, adchan->current_tx);
+	admac_start_chan(adchan);
+	admac_cyclic_write_desc(ad, ch, adchan->current_tx);
+}
+
+static void admac_issue_pending(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+	struct admac_tx *tx;
+	unsigned long flags;
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	list_splice_tail_init(&adchan->submitted, &adchan->issued);
+	if (!list_empty(&adchan->issued) && !adchan->current_tx) {
+		tx = list_first_entry(&adchan->issued, struct admac_tx, node);
+		list_del(&tx->node);
+
+		adchan->current_tx = tx;
+		adchan->nperiod_acks = 0;
+		admac_start_current_tx(adchan);
+	}
+	spin_unlock_irqrestore(&adchan->lock, flags);
+}
+
+static int admac_pause(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+
+	admac_stop_chan(adchan);
+
+	return 0;
+}
+
+static int admac_resume(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+
+	admac_start_chan(adchan);
+
+	return 0;
+}
+
+static int admac_terminate_all(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	admac_stop_chan(adchan);
+	admac_reset_rings(adchan);
+
+	adchan->current_tx = NULL;
+	/*
+	 * Descriptors can only be freed after the tasklet
+	 * has been killed (in admac_synchronize).
+	 */
+	list_splice_tail_init(&adchan->submitted, &adchan->to_free);
+	list_splice_tail_init(&adchan->issued, &adchan->to_free);
+	spin_unlock_irqrestore(&adchan->lock, flags);
+
+	return 0;
+}
+
+static void admac_synchronize(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+	struct admac_tx *adtx, *_adtx;
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	list_splice_tail_init(&adchan->to_free, &head);
+	spin_unlock_irqrestore(&adchan->lock, flags);
+
+	tasklet_kill(&adchan->tasklet);
+
+	list_for_each_entry_safe(adtx, _adtx, &head, node) {
+		list_del(&adtx->node);
+		admac_desc_free(&adtx->tx);
+	}
+}
+
+static int admac_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+
+	dma_cookie_init(&adchan->chan);
+	return 0;
+}
+
+static void admac_free_chan_resources(struct dma_chan *chan)
+{
+	admac_terminate_all(chan);
+	admac_synchronize(chan);
+}
+
+static struct dma_chan *admac_dma_of_xlate(struct of_phandle_args *dma_spec,
+					   struct of_dma *ofdma)
+{
+	struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data;
+	unsigned int index;
+
+	if (dma_spec->args_count != 1)
+		return NULL;
+
+	index = dma_spec->args[0];
+
+	if (index >= ad->nchannels) {
+		dev_err(ad->dev, "channel index %u out of bounds\n", index);
+		return NULL;
+	}
+
+	return &ad->channels[index].chan;
+}
+
+static int admac_drain_reports(struct admac_data *ad, int channo)
+{
+	int count;
+
+	for (count = 0; count < 4; count++) {
+		u32 countval_hi, countval_lo, unk1, flags;
+
+		if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
+			break;
+
+		countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
+		countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
+		unk1 =        readl_relaxed(ad->base + REG_REPORT_READ(channo));
+		flags =       readl_relaxed(ad->base + REG_REPORT_READ(channo));
+
+		dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n",
+			channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags);
+	}
+
+	return count;
+}
+
+static void admac_handle_status_err(struct admac_data *ad, int channo)
+{
+	bool handled = false;
+
+	if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
+		writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
+		dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);
+		handled = true;
+	}
+
+	if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
+		writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
+		dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);
+		handled = true;
+	}
+
+	if (unlikely(!handled)) {
+		dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);
+		admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),
+			     STATUS_ERR, 0);
+	}
+}
+
+static void admac_handle_status_desc_done(struct admac_data *ad, int channo)
+{
+	struct admac_chan *adchan = &ad->channels[channo];
+	unsigned long flags;
+	int nreports;
+
+	writel_relaxed(STATUS_DESC_DONE,
+		       ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
+
+	spin_lock_irqsave(&adchan->lock, flags);
+	nreports = admac_drain_reports(ad, channo);
+
+	if (adchan->current_tx) {
+		struct admac_tx *tx = adchan->current_tx;
+
+		adchan->nperiod_acks += nreports;
+		tx->reclaimed_pos += nreports * tx->period_len;
+		tx->reclaimed_pos %= 2 * tx->buf_len;
+
+		admac_cyclic_write_desc(ad, channo, tx);
+		tasklet_schedule(&adchan->tasklet);
+	}
+	spin_unlock_irqrestore(&adchan->lock, flags);
+}
+
+static void admac_handle_chan_int(struct admac_data *ad, int no)
+{
+	u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
+
+	if (cause & STATUS_ERR)
+		admac_handle_status_err(ad, no);
+
+	if (cause & STATUS_DESC_DONE)
+		admac_handle_status_desc_done(ad, no);
+}
+
+static irqreturn_t admac_interrupt(int irq, void *devid)
+{
+	struct admac_data *ad = devid;
+	u32 rx_intstate, tx_intstate;
+	int i;
+
+	rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index));
+	tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index));
+
+	if (!tx_intstate && !rx_intstate)
+		return IRQ_NONE;
+
+	for (i = 0; i < ad->nchannels; i += 2) {
+		if (tx_intstate & 1)
+			admac_handle_chan_int(ad, i);
+		tx_intstate >>= 1;
+	}
+
+	for (i = 1; i < ad->nchannels; i += 2) {
+		if (rx_intstate & 1)
+			admac_handle_chan_int(ad, i);
+		rx_intstate >>= 1;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void admac_chan_tasklet(struct tasklet_struct *t)
+{
+	struct admac_chan *adchan = from_tasklet(adchan, t, tasklet);
+	struct admac_tx *adtx;
+	struct dmaengine_desc_callback cb;
+	struct dmaengine_result tx_result;
+	int nacks;
+
+	spin_lock_irq(&adchan->lock);
+	adtx = adchan->current_tx;
+	nacks = adchan->nperiod_acks;
+	adchan->nperiod_acks = 0;
+	spin_unlock_irq(&adchan->lock);
+
+	if (!adtx || !nacks)
+		return;
+
+	tx_result.result = DMA_TRANS_NOERROR;
+	tx_result.residue = 0;
+
+	dmaengine_desc_get_callback(&adtx->tx, &cb);
+	while (nacks--)
+		dmaengine_desc_callback_invoke(&cb, &tx_result);
+}
+
+static int admac_device_config(struct dma_chan *chan,
+			       struct dma_slave_config *config)
+{
+	struct admac_chan *adchan = to_admac_chan(chan);
+	struct admac_data *ad = adchan->host;
+	bool is_tx = admac_chan_direction(adchan->no) == DMA_MEM_TO_DEV;
+	int wordsize = 0;
+	u32 bus_width = 0;
+
+	switch (is_tx ? config->dst_addr_width : config->src_addr_width) {
+	case DMA_SLAVE_BUSWIDTH_1_BYTE:
+		wordsize = 1;
+		bus_width |= BUS_WIDTH_8BIT;
+		break;
+	case DMA_SLAVE_BUSWIDTH_2_BYTES:
+		wordsize = 2;
+		bus_width |= BUS_WIDTH_16BIT;
+		break;
+	case DMA_SLAVE_BUSWIDTH_4_BYTES:
+		wordsize = 4;
+		bus_width |= BUS_WIDTH_32BIT;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * We take port_window_size to be the number of words in a frame.
+	 *
+	 * The controller has some means of out-of-band signalling, to the peripheral,
+	 * of words position in a frame. That's where the importance of this control
+	 * comes from.
+	 */
+	switch (is_tx ? config->dst_port_window_size : config->src_port_window_size) {
+	case 0 ... 1:
+		break;
+	case 2:
+		bus_width |= BUS_WIDTH_FRAME_2_WORDS;
+		break;
+	case 4:
+		bus_width |= BUS_WIDTH_FRAME_4_WORDS;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
+
+	/*
+	 * By FIFOCTL_LIMIT we seem to set the maximal number of bytes allowed to be
+	 * held in controller's per-channel FIFO. Transfers seem to be triggered
+	 * around the time FIFO occupancy touches FIFOCTL_THRESHOLD.
+	 *
+	 * The numbers we set are more or less arbitrary.
+	 */
+	writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize)
+		       | FIELD_PREP(CHAN_FIFOCTL_THRESHOLD, 0x18 * wordsize),
+		       ad->base + REG_CHAN_FIFOCTL(adchan->no));
+
+	return 0;
+}
+
+static int admac_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct admac_data *ad;
+	struct dma_device *dma;
+	int nchannels;
+	int err, irq, i;
+
+	err = of_property_read_u32(np, "dma-channels", &nchannels);
+	if (err || nchannels > NCHANNELS_MAX) {
+		dev_err(&pdev->dev, "missing or invalid dma-channels property\n");
+		return -EINVAL;
+	}
+
+	ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL);
+	if (!ad)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, ad);
+	ad->dev = &pdev->dev;
+	ad->nchannels = nchannels;
+
+	/*
+	 * The controller has 4 IRQ outputs. Try them all until
+	 * we find one we can use.
+	 */
+	for (i = 0; i < IRQ_NOUTPUTS; i++) {
+		irq = platform_get_irq_optional(pdev, i);
+		if (irq >= 0) {
+			ad->irq_index = i;
+			break;
+		}
+	}
+
+	if (irq < 0)
+		return dev_err_probe(&pdev->dev, irq, "no usable interrupt\n");
+
+	err = devm_request_irq(&pdev->dev, irq, admac_interrupt,
+			       0, dev_name(&pdev->dev), ad);
+	if (err)
+		return dev_err_probe(&pdev->dev, err,
+				     "unable to register interrupt\n");
+
+	ad->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(ad->base))
+		return dev_err_probe(&pdev->dev, PTR_ERR(ad->base),
+				     "unable to obtain MMIO resource\n");
+
+	dma = &ad->dma;
+
+	dma_cap_set(DMA_PRIVATE, dma->cap_mask);
+	dma_cap_set(DMA_CYCLIC, dma->cap_mask);
+
+	dma->dev = &pdev->dev;
+	dma->device_alloc_chan_resources = admac_alloc_chan_resources;
+	dma->device_free_chan_resources = admac_free_chan_resources;
+	dma->device_tx_status = admac_tx_status;
+	dma->device_issue_pending = admac_issue_pending;
+	dma->device_terminate_all = admac_terminate_all;
+	dma->device_synchronize = admac_synchronize;
+	dma->device_prep_dma_cyclic = admac_prep_dma_cyclic;
+	dma->device_config = admac_device_config;
+	dma->device_pause = admac_pause;
+	dma->device_resume = admac_resume;
+
+	dma->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
+	dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+	dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+			BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+			BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+
+	INIT_LIST_HEAD(&dma->channels);
+	for (i = 0; i < nchannels; i++) {
+		struct admac_chan *adchan = &ad->channels[i];
+
+		adchan->host = ad;
+		adchan->no = i;
+		adchan->chan.device = &ad->dma;
+		spin_lock_init(&adchan->lock);
+		INIT_LIST_HEAD(&adchan->submitted);
+		INIT_LIST_HEAD(&adchan->issued);
+		INIT_LIST_HEAD(&adchan->to_free);
+		list_add_tail(&adchan->chan.device_node, &dma->channels);
+		tasklet_setup(&adchan->tasklet, admac_chan_tasklet);
+	}
+
+	err = dma_async_device_register(&ad->dma);
+	if (err)
+		return dev_err_probe(&pdev->dev, err, "failed to register DMA device\n");
+
+	err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad);
+	if (err) {
+		dma_async_device_unregister(&ad->dma);
+		return dev_err_probe(&pdev->dev, err, "failed to register with OF\n");
+	}
+
+	return 0;
+}
+
+static int admac_remove(struct platform_device *pdev)
+{
+	struct admac_data *ad = platform_get_drvdata(pdev);
+
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&ad->dma);
+
+	return 0;
+}
+
+static const struct of_device_id admac_of_match[] = {
+	{ .compatible = "apple,admac", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, admac_of_match);
+
+static struct platform_driver apple_admac_driver = {
+	.driver = {
+		.name = "apple-admac",
+		.of_match_table = admac_of_match,
+	},
+	.probe = admac_probe,
+	.remove = admac_remove,
+};
+module_platform_driver(apple_admac_driver);
+
+MODULE_AUTHOR("Martin Povišer <povik+lin@cutebit.org>");
+MODULE_DESCRIPTION("Driver for Audio DMA Controller (ADMAC) on Apple SoCs");
+MODULE_LICENSE("GPL");
diff --git a/drivers/dma/bcm-sba-raid.c b/drivers/dma/bcm-sba-raid.c
index 64239da02e74..064761289a73 100644
--- a/drivers/dma/bcm-sba-raid.c
+++ b/drivers/dma/bcm-sba-raid.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2017 Broadcom
 
 /*
  * Broadcom SBA RAID Driver
diff --git a/drivers/dma/bestcomm/ata.c b/drivers/dma/bestcomm/ata.c
index e169f18da551..502a45d76adc 100644
--- a/drivers/dma/bestcomm/ata.c
+++ b/drivers/dma/bestcomm/ata.c
@@ -1,16 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Bestcomm ATA task driver
  *
- *
  * Patterned after bestcomm/fec.c by Dale Farnsworth <dfarnsworth@mvista.com>
  *                                   2003-2004 (c) MontaVista, Software, Inc.
  *
  * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
  * Copyright (C) 2006      Freescale - John Rigby
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
@@ -154,4 +150,3 @@ EXPORT_SYMBOL_GPL(bcom_ata_release);
 MODULE_DESCRIPTION("BestComm ATA task driver");
 MODULE_AUTHOR("John Rigby");
 MODULE_LICENSE("GPL v2");
-
diff --git a/drivers/dma/bestcomm/bestcomm.c b/drivers/dma/bestcomm/bestcomm.c
index 1822a7034630..eabbcfcaa7cb 100644
--- a/drivers/dma/bestcomm/bestcomm.c
+++ b/drivers/dma/bestcomm/bestcomm.c
@@ -1,16 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Driver for MPC52xx processor BestComm peripheral controller
  *
- *
  * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
  * Copyright (C) 2005      Varma Electronics Oy,
  *                         ( by Andrey Volkov <avolkov@varma-el.com> )
  * Copyright (C) 2003-2004 MontaVista, Software, Inc.
  *                         ( by Dale Farnsworth <dfarnsworth@mvista.com> )
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/module.h>
@@ -528,4 +524,3 @@ MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
 MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
 MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
 MODULE_LICENSE("GPL v2");
-
diff --git a/drivers/dma/bestcomm/fec.c b/drivers/dma/bestcomm/fec.c
index d203618ac11f..3a4a2f7910c6 100644
--- a/drivers/dma/bestcomm/fec.c
+++ b/drivers/dma/bestcomm/fec.c
@@ -1,14 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Bestcomm FEC tasks driver
  *
- *
  * Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
  * Copyright (C) 2003-2004 MontaVista, Software, Inc.
  *                         ( by Dale Farnsworth <dfarnsworth@mvista.com> )
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/kernel.h>
@@ -267,4 +263,3 @@ EXPORT_SYMBOL_GPL(bcom_fec_tx_release);
 MODULE_DESCRIPTION("BestComm FEC tasks driver");
 MODULE_AUTHOR("Dale Farnsworth <dfarnsworth@mvista.com>");
 MODULE_LICENSE("GPL v2");
-
diff --git a/drivers/dma/bestcomm/sram.c b/drivers/dma/bestcomm/sram.c
index 2074e0e3fa21..c465758e7193 100644
--- a/drivers/dma/bestcomm/sram.c
+++ b/drivers/dma/bestcomm/sram.c
@@ -1,14 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Simple memory allocator for on-board SRAM
  *
- *
  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
  *
  * Copyright (C) 2005 Sylvain Munaut <tnt@246tNt.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/err.h>
@@ -176,4 +172,3 @@ void bcom_sram_free(void *ptr)
 	spin_unlock(&bcom_sram->lock);
 }
 EXPORT_SYMBOL_GPL(bcom_sram_free);
-
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 0a2168a4ccb0..49974d5a6992 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -22,51 +22,50 @@
 #include <linux/wait.h>
 
 static unsigned int test_buf_size = 16384;
-module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
+module_param(test_buf_size, uint, 0644);
 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
 
 static char test_device[32];
-module_param_string(device, test_device, sizeof(test_device),
-		S_IRUGO | S_IWUSR);
+module_param_string(device, test_device, sizeof(test_device), 0644);
 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
 
 static unsigned int threads_per_chan = 1;
-module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
+module_param(threads_per_chan, uint, 0644);
 MODULE_PARM_DESC(threads_per_chan,
 		"Number of threads to start per channel (default: 1)");
 
 static unsigned int max_channels;
-module_param(max_channels, uint, S_IRUGO | S_IWUSR);
+module_param(max_channels, uint, 0644);
 MODULE_PARM_DESC(max_channels,
 		"Maximum number of channels to use (default: all)");
 
 static unsigned int iterations;
-module_param(iterations, uint, S_IRUGO | S_IWUSR);
+module_param(iterations, uint, 0644);
 MODULE_PARM_DESC(iterations,
 		"Iterations before stopping test (default: infinite)");
 
 static unsigned int dmatest;
-module_param(dmatest, uint, S_IRUGO | S_IWUSR);
+module_param(dmatest, uint, 0644);
 MODULE_PARM_DESC(dmatest,
 		"dmatest 0-memcpy 1-memset (default: 0)");
 
 static unsigned int xor_sources = 3;
-module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
+module_param(xor_sources, uint, 0644);
 MODULE_PARM_DESC(xor_sources,
 		"Number of xor source buffers (default: 3)");
 
 static unsigned int pq_sources = 3;
-module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
+module_param(pq_sources, uint, 0644);
 MODULE_PARM_DESC(pq_sources,
 		"Number of p+q source buffers (default: 3)");
 
 static int timeout = 3000;
-module_param(timeout, int, S_IRUGO | S_IWUSR);
+module_param(timeout, int, 0644);
 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
 		 "Pass -1 for infinite timeout");
 
 static bool noverify;
-module_param(noverify, bool, S_IRUGO | S_IWUSR);
+module_param(noverify, bool, 0644);
 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
 
 static bool norandom;
@@ -74,7 +73,7 @@ module_param(norandom, bool, 0644);
 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
 
 static bool verbose;
-module_param(verbose, bool, S_IRUGO | S_IWUSR);
+module_param(verbose, bool, 0644);
 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
 
 static int alignment = -1;
@@ -86,7 +85,7 @@ module_param(transfer_size, uint, 0644);
 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
 
 static bool polled;
-module_param(polled, bool, S_IRUGO | S_IWUSR);
+module_param(polled, bool, 0644);
 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
 
 /**
@@ -154,7 +153,7 @@ static const struct kernel_param_ops run_ops = {
 	.get = dmatest_run_get,
 };
 static bool dmatest_run;
-module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
+module_param_cb(run, &run_ops, &dmatest_run, 0644);
 MODULE_PARM_DESC(run, "Run the test (default: false)");
 
 static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
@@ -290,7 +289,7 @@ static const struct kernel_param_ops wait_ops = {
 	.get = dmatest_wait_get,
 	.set = param_set_bool,
 };
-module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
+module_param_cb(wait, &wait_ops, &wait, 0444);
 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
 
 static bool dmatest_match_channel(struct dmatest_params *params,
@@ -579,10 +578,10 @@ static int dmatest_func(void *data)
 	unsigned int		total_tests = 0;
 	dma_cookie_t		cookie;
 	enum dma_status		status;
-	enum dma_ctrl_flags 	flags;
+	enum dma_ctrl_flags	flags;
 	u8			*pq_coefs = NULL;
 	int			ret;
-	unsigned int 		buf_size;
+	unsigned int		buf_size;
 	struct dmatest_data	*src;
 	struct dmatest_data	*dst;
 	int			i;
@@ -675,16 +674,10 @@ static int dmatest_func(void *data)
 	/*
 	 * src and dst buffers are freed by ourselves below
 	 */
-	if (params->polled) {
+	if (params->polled)
 		flags = DMA_CTRL_ACK;
-	} else {
-		if (dma_has_cap(DMA_INTERRUPT, dev->cap_mask)) {
-			flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
-		} else {
-			pr_err("Channel does not support interrupt!\n");
-			goto err_pq_array;
-		}
-	}
+	else
+		flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 
 	ktime = ktime_get();
 	while (!(kthread_should_stop() ||
@@ -912,7 +905,6 @@ static int dmatest_func(void *data)
 	runtime = ktime_to_us(ktime);
 
 	ret = 0;
-err_pq_array:
 	kfree(dma_pq);
 err_srcs_array:
 	kfree(srcs);
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 33bc1e6c4cf2..c73b9ed1ce74 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -414,19 +414,11 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
 		SET_CH_32(dw, chan->dir, chan->id, ch_control1,
 			  (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
 		/* Linked list */
-
-		#ifdef CONFIG_64BIT
 		/* llp is not aligned on 64bit -> keep 32bit accesses */
 		SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
 			  lower_32_bits(chunk->ll_region.paddr));
 		SET_CH_32(dw, chan->dir, chan->id, llp.msb,
 			  upper_32_bits(chunk->ll_region.paddr));
-		#else /* CONFIG_64BIT */
-		SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
-			  lower_32_bits(chunk->ll_region.paddr));
-		SET_CH_32(dw, chan->dir, chan->id, llp.msb,
-			  upper_32_bits(chunk->ll_region.paddr));
-		#endif /* CONFIG_64BIT */
 	}
 	/* Doorbell */
 	SET_RW_32(dw, chan->dir, doorbell,
diff --git a/drivers/dma/dw/rzn1-dmamux.c b/drivers/dma/dw/rzn1-dmamux.c
index 11d254e450b0..f9912c3dd4d7 100644
--- a/drivers/dma/dw/rzn1-dmamux.c
+++ b/drivers/dma/dw/rzn1-dmamux.c
@@ -102,10 +102,12 @@ static void *rzn1_dmamux_route_allocate(struct of_phandle_args *dma_spec,
 	return ERR_PTR(ret);
 }
 
+#ifdef CONFIG_OF
 static const struct of_device_id rzn1_dmac_match[] = {
 	{ .compatible = "renesas,rzn1-dma" },
 	{}
 };
+#endif
 
 static int rzn1_dmamux_probe(struct platform_device *pdev)
 {
@@ -140,6 +142,7 @@ static const struct of_device_id rzn1_dmamux_match[] = {
 	{ .compatible = "renesas,rzn1-dmamux" },
 	{}
 };
+MODULE_DEVICE_TABLE(of, rzn1_dmamux_match);
 
 static struct platform_driver rzn1_dmamux_driver = {
 	.driver = {
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8535018ee7a2..900cafdaf359 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -2346,7 +2346,7 @@ MODULE_DESCRIPTION("i.MX SDMA driver");
 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
 #endif
-#if IS_ENABLED(CONFIG_SOC_IMX7D)
+#if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
 #endif
 MODULE_LICENSE("GPL");
diff --git a/drivers/dma/moxart-dma.c b/drivers/dma/moxart-dma.c
index 74755093e14b..7459382a8353 100644
--- a/drivers/dma/moxart-dma.c
+++ b/drivers/dma/moxart-dma.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * MOXA ART SoCs DMA Engine support.
  *
  * Copyright (C) 2013 Jonas Jensen
  *
  * Jonas Jensen <jonas.jensen@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/dmaengine.h>
diff --git a/drivers/dma/ppc4xx/adma.h b/drivers/dma/ppc4xx/adma.h
index 26b7a5ed9ac7..f8a5d7c1fb40 100644
--- a/drivers/dma/ppc4xx/adma.h
+++ b/drivers/dma/ppc4xx/adma.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * 2006-2009 (C) DENX Software Engineering.
  *
  * Author: Yuri Tikhonov <yur@emcraft.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of
- * any kind, whether express or implied.
  */
 
 #ifndef _PPC440SPE_ADMA_H
diff --git a/drivers/dma/ppc4xx/dma.h b/drivers/dma/ppc4xx/dma.h
index bcde2df2f373..1ff4be23db0f 100644
--- a/drivers/dma/ppc4xx/dma.h
+++ b/drivers/dma/ppc4xx/dma.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * 440SPe's DMA engines support header file
  *
  * 2006-2009 (C) DENX Software Engineering.
  *
  * Author: Yuri Tikhonov <yur@emcraft.com>
- *
- * This file is licensed under the term of  the GNU General Public License
- * version 2. The program licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #ifndef	_PPC440SPE_DMA_H
diff --git a/drivers/dma/ppc4xx/xor.h b/drivers/dma/ppc4xx/xor.h
index daed7384daac..da1230df2817 100644
--- a/drivers/dma/ppc4xx/xor.h
+++ b/drivers/dma/ppc4xx/xor.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * 440SPe's XOR engines support header file
  *
  * 2006-2009 (C) DENX Software Engineering.
  *
  * Author: Yuri Tikhonov <yur@emcraft.com>
- *
- * This file is licensed under the term of  the GNU General Public License
- * version 2. The program licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #ifndef _PPC440SPE_XOR_H
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index caf0cce8f528..b11927ed4367 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1328,12 +1328,7 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)
 		return IRQ_NONE;
 	}
 	id = __ffs(status);
-
 	chan = &dmadev->chan[id];
-	if (!chan) {
-		dev_warn(mdma2dev(dmadev), "MDMA channel not initialized\n");
-		return IRQ_NONE;
-	}
 
 	/* Handle interrupt for the channel */
 	spin_lock(&chan->vchan.lock);
diff --git a/drivers/dma/ti/dma-crossbar.c b/drivers/dma/ti/dma-crossbar.c
index 71d24fc07c00..f744ddbbbad7 100644
--- a/drivers/dma/ti/dma-crossbar.c
+++ b/drivers/dma/ti/dma-crossbar.c
@@ -245,6 +245,7 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 	if (dma_spec->args[0] >= xbar->xbar_requests) {
 		dev_err(&pdev->dev, "Invalid XBAR request number: %d\n",
 			dma_spec->args[0]);
+		put_device(&pdev->dev);
 		return ERR_PTR(-EINVAL);
 	}
 
@@ -252,12 +253,14 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 	dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
 	if (!dma_spec->np) {
 		dev_err(&pdev->dev, "Can't get DMA master\n");
+		put_device(&pdev->dev);
 		return ERR_PTR(-EINVAL);
 	}
 
 	map = kzalloc(sizeof(*map), GFP_KERNEL);
 	if (!map) {
 		of_node_put(dma_spec->np);
+		put_device(&pdev->dev);
 		return ERR_PTR(-ENOMEM);
 	}
 
@@ -268,6 +271,8 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
 		mutex_unlock(&xbar->mutex);
 		dev_err(&pdev->dev, "Run out of free DMA requests\n");
 		kfree(map);
+		of_node_put(dma_spec->np);
+		put_device(&pdev->dev);
 		return ERR_PTR(-ENOMEM);
 	}
 	set_bit(map->xbar_out, xbar->dma_inuse);
diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c
index 3ea8ef7f57df..4cbca80ee16e 100644
--- a/drivers/dma/ti/edma.c
+++ b/drivers/dma/ti/edma.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * TI EDMA DMA engine driver
  *
  * Copyright 2012 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/dmaengine.h>
diff --git a/drivers/edac/edac_pci.c b/drivers/edac/edac_pci.c
index 2205d7e731db..64c142aecca7 100644
--- a/drivers/edac/edac_pci.c
+++ b/drivers/edac/edac_pci.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * EDAC PCI component
  *
  * Author: Dave Jiang <djiang@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
+ * 2007 (c) MontaVista Software, Inc.
  */
 #include <asm/page.h>
 #include <linux/uaccess.h>
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 6d8ea226010d..ac2102b25706 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Freescale Memory Controller kernel module
  *
@@ -9,10 +10,7 @@
  *
  * Author: Dave Jiang <djiang@mvista.com>
  *
- * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2006-2007 (c) MontaVista Software, Inc.
  */
 #include <linux/module.h>
 #include <linux/init.h>
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 589b9b4a5e8a..332439d7b2d9 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Freescale Memory Controller kernel module
  *
@@ -7,11 +8,7 @@
  *
  * Author: Dave Jiang <djiang@mvista.com>
  *
- * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
+ * 2006-2007 (c) MontaVista Software, Inc.
  */
 #ifndef _FSL_DDR_EDAC_H_
 #define _FSL_DDR_EDAC_H_
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 3f6fb16ad34f..66a046ae33ee 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Freescale MPC85xx Memory Controller kernel module
  * Author: Dave Jiang <djiang@mvista.com>
  *
- * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
+ * 2006-2007 (c) MontaVista Software, Inc.
  */
 #ifndef _MPC85XX_EDAC_H_
 #define _MPC85XX_EDAC_H_
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 1cee64b80a7e..f7d37c282819 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -514,6 +514,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
 	memset(p, 0, sizeof(*p));
 }
 
+static void enable_intr(struct synps_edac_priv *priv)
+{
+	/* Enable UE/CE Interrupts */
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(DDR_UE_MASK | DDR_CE_MASK,
+		       priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
+
+}
+
+static void disable_intr(struct synps_edac_priv *priv)
+{
+	/* Disable UE/CE Interrupts */
+	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
+		writel(0x0, priv->baseaddr + ECC_CLR_OFST);
+	else
+		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
+}
+
 /**
  * intr_handler - Interrupt Handler for ECC interrupts.
  * @irq:        IRQ number.
@@ -555,6 +577,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
 	/* v3.0 of the controller does not have this register */
 	if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
 		writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+	else
+		enable_intr(priv);
+
 	return IRQ_HANDLED;
 }
 
@@ -837,25 +862,6 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
 	init_csrows(mci);
 }
 
-static void enable_intr(struct synps_edac_priv *priv)
-{
-	/* Enable UE/CE Interrupts */
-	if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
-		writel(DDR_UE_MASK | DDR_CE_MASK,
-		       priv->baseaddr + ECC_CLR_OFST);
-	else
-		writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
-
-}
-
-static void disable_intr(struct synps_edac_priv *priv)
-{
-	/* Disable UE/CE Interrupts */
-	writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
-			priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
-}
-
 static int setup_irq(struct mem_ctl_info *mci,
 		     struct platform_device *pdev)
 {
diff --git a/drivers/extcon/extcon-fsa9480.c b/drivers/extcon/extcon-fsa9480.c
index 08bdedbcdb0d..7cff66c29907 100644
--- a/drivers/extcon/extcon-fsa9480.c
+++ b/drivers/extcon/extcon-fsa9480.c
@@ -324,11 +324,6 @@ static int fsa9480_probe(struct i2c_client *client,
 	return 0;
 }
 
-static int fsa9480_remove(struct i2c_client *client)
-{
-	return 0;
-}
-
 #ifdef CONFIG_PM_SLEEP
 static int fsa9480_suspend(struct device *dev)
 {
@@ -376,7 +371,6 @@ static struct i2c_driver fsa9480_i2c_driver = {
 		.of_match_table = fsa9480_of_match,
 	},
 	.probe			= fsa9480_probe,
-	.remove			= fsa9480_remove,
 	.id_table		= fsa9480_id,
 };
 
diff --git a/drivers/extcon/extcon-max77843.c b/drivers/extcon/extcon-max77843.c
index 8e6e97ec65a8..1bc0426ce3f1 100644
--- a/drivers/extcon/extcon-max77843.c
+++ b/drivers/extcon/extcon-max77843.c
@@ -189,8 +189,7 @@ static const struct regmap_irq max77843_muic_irq[] = {
 static const struct regmap_irq_chip max77843_muic_irq_chip = {
 	.name           = "max77843-muic",
 	.status_base    = MAX77843_MUIC_REG_INT1,
-	.mask_base      = MAX77843_MUIC_REG_INTMASK1,
-	.mask_invert    = true,
+	.unmask_base    = MAX77843_MUIC_REG_INTMASK1,
 	.num_regs       = 3,
 	.irqs           = max77843_muic_irq,
 	.num_irqs       = ARRAY_SIZE(max77843_muic_irq),
diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c
index d2c1a8b89c08..32f8b541770b 100644
--- a/drivers/extcon/extcon-palmas.c
+++ b/drivers/extcon/extcon-palmas.c
@@ -107,7 +107,7 @@ static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb)
 				(id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
 		palmas_usb->linkstat = PALMAS_USB_STATE_ID;
 		extcon_set_state_sync(edev, EXTCON_USB_HOST, true);
-		dev_dbg(palmas_usb->dev, " USB-HOST cable is attached\n");
+		dev_dbg(palmas_usb->dev, "USB-HOST cable is attached\n");
 	}
 
 	return IRQ_HANDLED;
diff --git a/drivers/extcon/extcon-rt8973a.c b/drivers/extcon/extcon-rt8973a.c
index 40c07f4d656e..02ba770acb27 100644
--- a/drivers/extcon/extcon-rt8973a.c
+++ b/drivers/extcon/extcon-rt8973a.c
@@ -192,7 +192,6 @@ static const struct regmap_irq_chip rt8973a_muic_irq_chip = {
 	.name			= "rt8973a",
 	.status_base		= RT8973A_REG_INT1,
 	.mask_base		= RT8973A_REG_INTM1,
-	.mask_invert		= false,
 	.num_regs		= 2,
 	.irqs			= rt8973a_irqs,
 	.num_irqs		= ARRAY_SIZE(rt8973a_irqs),
diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c
index f706f5288257..8401e8b27788 100644
--- a/drivers/extcon/extcon-sm5502.c
+++ b/drivers/extcon/extcon-sm5502.c
@@ -227,7 +227,6 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = {
 	.name			= "sm5502",
 	.status_base		= SM5502_REG_INT1,
 	.mask_base		= SM5502_REG_INTMASK1,
-	.mask_invert		= false,
 	.num_regs		= 2,
 	.irqs			= sm5502_irqs,
 	.num_irqs		= ARRAY_SIZE(sm5502_irqs),
@@ -276,7 +275,6 @@ static const struct regmap_irq_chip sm5504_muic_irq_chip = {
 	.name			= "sm5504",
 	.status_base		= SM5502_REG_INT1,
 	.mask_base		= SM5502_REG_INTMASK1,
-	.mask_invert		= false,
 	.num_regs		= 2,
 	.irqs			= sm5504_irqs,
 	.num_irqs		= ARRAY_SIZE(sm5504_irqs),
diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c
index d3a32b806499..0e40418ad287 100644
--- a/drivers/extcon/extcon.c
+++ b/drivers/extcon/extcon.c
@@ -247,7 +247,7 @@ static int find_cable_index_by_id(struct extcon_dev *edev, const unsigned int id
 {
 	int i;
 
-	/* Find the the index of extcon cable in edev->supported_cable */
+	/* Find the index of extcon cable in edev->supported_cable */
 	for (i = 0; i < edev->max_supported; i++) {
 		if (edev->supported_cable[i] == id)
 			return i;
diff --git a/drivers/firewire/core-cdev.c b/drivers/firewire/core-cdev.c
index c9fe5903725a..9c89f7d53e99 100644
--- a/drivers/firewire/core-cdev.c
+++ b/drivers/firewire/core-cdev.c
@@ -1211,7 +1211,7 @@ static int ioctl_get_cycle_timer2(struct client *client, union ioctl_arg *arg)
 	struct fw_cdev_get_cycle_timer2 *a = &arg->get_cycle_timer2;
 	struct fw_card *card = client->device->card;
 	struct timespec64 ts = {0, 0};
-	u32 cycle_time;
+	u32 cycle_time = 0;
 	int ret = 0;
 
 	local_irq_disable();
diff --git a/drivers/firewire/core-device.c b/drivers/firewire/core-device.c
index 90ed8fdaba75..adddd8c45d0c 100644
--- a/drivers/firewire/core-device.c
+++ b/drivers/firewire/core-device.c
@@ -372,8 +372,7 @@ static ssize_t rom_index_show(struct device *dev,
 	struct fw_device *device = fw_device(dev->parent);
 	struct fw_unit *unit = fw_unit(dev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			(int)(unit->directory - device->config_rom));
+	return sysfs_emit(buf, "%td\n", unit->directory - device->config_rom);
 }
 
 static struct device_attribute fw_unit_attributes[] = {
@@ -403,8 +402,7 @@ static ssize_t guid_show(struct device *dev,
 	int ret;
 
 	down_read(&fw_device_rwsem);
-	ret = snprintf(buf, PAGE_SIZE, "0x%08x%08x\n",
-		       device->config_rom[3], device->config_rom[4]);
+	ret = sysfs_emit(buf, "0x%08x%08x\n", device->config_rom[3], device->config_rom[4]);
 	up_read(&fw_device_rwsem);
 
 	return ret;
diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c
index 20fba7370f4e..a52f084a6a87 100644
--- a/drivers/firmware/arm_scmi/base.c
+++ b/drivers/firmware/arm_scmi/base.c
@@ -36,7 +36,7 @@ struct scmi_msg_resp_base_attributes {
 
 struct scmi_msg_resp_base_discover_agent {
 	__le32 agent_id;
-	u8 name[SCMI_MAX_STR_SIZE];
+	u8 name[SCMI_SHORT_NAME_MAX_SIZE];
 };
 
 
@@ -119,7 +119,7 @@ scmi_base_vendor_id_get(const struct scmi_protocol_handle *ph, bool sub_vendor)
 
 	ret = ph->xops->do_xfer(ph, t);
 	if (!ret)
-		memcpy(vendor_id, t->rx.buf, size);
+		strscpy(vendor_id, t->rx.buf, size);
 
 	ph->xops->xfer_put(ph, t);
 
@@ -221,11 +221,17 @@ scmi_base_implementation_list_get(const struct scmi_protocol_handle *ph,
 		calc_list_sz = (1 + (loop_num_ret - 1) / sizeof(u32)) *
 				sizeof(u32);
 		if (calc_list_sz != real_list_sz) {
-			dev_err(dev,
-				"Malformed reply - real_sz:%zd  calc_sz:%u\n",
-				real_list_sz, calc_list_sz);
-			ret = -EPROTO;
-			break;
+			dev_warn(dev,
+				 "Malformed reply - real_sz:%zd  calc_sz:%u  (loop_num_ret:%d)\n",
+				 real_list_sz, calc_list_sz, loop_num_ret);
+			/*
+			 * Bail out if the expected list size is bigger than the
+			 * total payload size of the received reply.
+			 */
+			if (calc_list_sz > real_list_sz) {
+				ret = -EPROTO;
+				break;
+			}
 		}
 
 		for (loop = 0; loop < loop_num_ret; loop++)
@@ -270,7 +276,7 @@ static int scmi_base_discover_agent_get(const struct scmi_protocol_handle *ph,
 	ret = ph->xops->do_xfer(ph, t);
 	if (!ret) {
 		agent_info = t->rx.buf;
-		strlcpy(name, agent_info->name, SCMI_MAX_STR_SIZE);
+		strscpy(name, agent_info->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
@@ -369,7 +375,7 @@ static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)
 	int id, ret;
 	u8 *prot_imp;
 	u32 version;
-	char name[SCMI_MAX_STR_SIZE];
+	char name[SCMI_SHORT_NAME_MAX_SIZE];
 	struct device *dev = ph->dev;
 	struct scmi_revision_info *rev = scmi_revision_area_get(ph);
 
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index 4d36a9a133d1..3ed7ae0d6781 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -153,7 +153,7 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
 	if (!ret) {
 		u32 latency = 0;
 		attributes = le32_to_cpu(attr->attributes);
-		strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(clk->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 		/* clock_enable_latency field is present only since SCMI v3.1 */
 		if (PROTOCOL_REV_MAJOR(version) >= 0x2)
 			latency = le32_to_cpu(attr->clock_enable_latency);
@@ -194,6 +194,7 @@ static int rate_cmp_func(const void *_r1, const void *_r2)
 }
 
 struct scmi_clk_ipriv {
+	struct device *dev;
 	u32 clk_id;
 	struct scmi_clock_info *clk;
 };
@@ -223,6 +224,29 @@ iter_clk_describe_update_state(struct scmi_iterator_state *st,
 	st->num_returned = NUM_RETURNED(flags);
 	p->clk->rate_discrete = RATE_DISCRETE(flags);
 
+	/* Warn about out of spec replies ... */
+	if (!p->clk->rate_discrete &&
+	    (st->num_returned != 3 || st->num_remaining != 0)) {
+		dev_warn(p->dev,
+			 "Out-of-spec CLOCK_DESCRIBE_RATES reply for %s - returned:%d remaining:%d rx_len:%zd\n",
+			 p->clk->name, st->num_returned, st->num_remaining,
+			 st->rx_len);
+
+		/*
+		 * A known quirk: a triplet is returned but num_returned != 3
+		 * Check for a safe payload size and fix.
+		 */
+		if (st->num_returned != 3 && st->num_remaining == 0 &&
+		    st->rx_len == sizeof(*r) + sizeof(__le32) * 2 * 3) {
+			st->num_returned = 3;
+			st->num_remaining = 0;
+		} else {
+			dev_err(p->dev,
+				"Cannot fix out-of-spec reply !\n");
+			return -EPROTO;
+		}
+	}
+
 	return 0;
 }
 
@@ -255,7 +279,6 @@ iter_clk_describe_process_response(const struct scmi_protocol_handle *ph,
 
 		*rate = RATE_TO_U64(r->rate[st->loop_idx]);
 		p->clk->list.num_rates++;
-		//XXX dev_dbg(ph->dev, "Rate %llu Hz\n", *rate);
 	}
 
 	return ret;
@@ -266,9 +289,7 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 			      struct scmi_clock_info *clk)
 {
 	int ret;
-
 	void *iter;
-	struct scmi_msg_clock_describe_rates *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_clk_describe_prepare_message,
 		.update_state = iter_clk_describe_update_state,
@@ -277,11 +298,13 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 	struct scmi_clk_ipriv cpriv = {
 		.clk_id = clk_id,
 		.clk = clk,
+		.dev = ph->dev,
 	};
 
 	iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,
 					    CLOCK_DESCRIBE_RATES,
-					    sizeof(*msg), &cpriv);
+					    sizeof(struct scmi_msg_clock_describe_rates),
+					    &cpriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index c1922bd650ae..8b7ac6663d57 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -1223,6 +1223,7 @@ static int scmi_iterator_run(void *iter)
 		if (ret)
 			break;
 
+		st->rx_len = i->t->rx.len;
 		ret = iops->update_state(st, i->resp, i->priv);
 		if (ret)
 			break;
diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c
index 8f4051aca220..bbb0331801ff 100644
--- a/drivers/firmware/arm_scmi/perf.c
+++ b/drivers/firmware/arm_scmi/perf.c
@@ -252,7 +252,7 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
 			dom_info->mult_factor =
 					(dom_info->sustained_freq_khz * 1000) /
 					dom_info->sustained_perf_level;
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
@@ -332,7 +332,6 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_perf_describe_levels *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_perf_levels_prepare_message,
 		.update_state = iter_perf_levels_update_state,
@@ -345,7 +344,8 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
 
 	iter = ph->hops->iter_response_init(ph, &ops, MAX_OPPS,
 					    PERF_DESCRIBE_LEVELS,
-					    sizeof(*msg), &ppriv);
+					    sizeof(struct scmi_msg_perf_describe_levels),
+					    &ppriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/power.c
index 964882cc8747..356e83631664 100644
--- a/drivers/firmware/arm_scmi/power.c
+++ b/drivers/firmware/arm_scmi/power.c
@@ -122,7 +122,7 @@ scmi_power_domain_attributes_get(const struct scmi_protocol_handle *ph,
 		dom_info->state_set_notify = SUPPORTS_STATE_SET_NOTIFY(flags);
 		dom_info->state_set_async = SUPPORTS_STATE_SET_ASYNC(flags);
 		dom_info->state_set_sync = SUPPORTS_STATE_SET_SYNC(flags);
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 	ph->xops->xfer_put(ph, t);
 
diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h
index 73304af5ec4a..51c31379f9b3 100644
--- a/drivers/firmware/arm_scmi/protocols.h
+++ b/drivers/firmware/arm_scmi/protocols.h
@@ -24,8 +24,6 @@
 
 #include <asm/unaligned.h>
 
-#define SCMI_SHORT_NAME_MAX_SIZE	16
-
 #define PROTOCOL_REV_MINOR_MASK	GENMASK(15, 0)
 #define PROTOCOL_REV_MAJOR_MASK	GENMASK(31, 16)
 #define PROTOCOL_REV_MAJOR(x)	((u16)(FIELD_GET(PROTOCOL_REV_MAJOR_MASK, (x))))
@@ -181,6 +179,8 @@ struct scmi_protocol_handle {
  * @max_resources: Maximum acceptable number of items, configured by the caller
  *		   depending on the underlying resources that it is querying.
  * @loop_idx: The iterator loop index in the current multi-part reply.
+ * @rx_len: Size in bytes of the currenly processed message; it can be used by
+ *	    the user of the iterator to verify a reply size.
  * @priv: Optional pointer to some additional state-related private data setup
  *	  by the caller during the iterations.
  */
@@ -190,6 +190,7 @@ struct scmi_iterator_state {
 	unsigned int num_remaining;
 	unsigned int max_resources;
 	unsigned int loop_idx;
+	size_t rx_len;
 	void *priv;
 };
 
diff --git a/drivers/firmware/arm_scmi/reset.c b/drivers/firmware/arm_scmi/reset.c
index a420a9102094..673f3eb498f4 100644
--- a/drivers/firmware/arm_scmi/reset.c
+++ b/drivers/firmware/arm_scmi/reset.c
@@ -116,7 +116,7 @@ scmi_reset_domain_attributes_get(const struct scmi_protocol_handle *ph,
 		dom_info->latency_us = le32_to_cpu(attr->latency);
 		if (dom_info->latency_us == U32_MAX)
 			dom_info->latency_us = 0;
-		strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
+		strscpy(dom_info->name, attr->name, SCMI_SHORT_NAME_MAX_SIZE);
 	}
 
 	ph->xops->xfer_put(ph, t);
diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c
index 21e0ce89b153..7288c6117838 100644
--- a/drivers/firmware/arm_scmi/sensors.c
+++ b/drivers/firmware/arm_scmi/sensors.c
@@ -338,7 +338,6 @@ static int scmi_sensor_update_intervals(const struct scmi_protocol_handle *ph,
 					struct scmi_sensor_info *s)
 {
 	void *iter;
-	struct scmi_msg_sensor_list_update_intervals *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_intervals_prepare_message,
 		.update_state = iter_intervals_update_state,
@@ -351,22 +350,28 @@ static int scmi_sensor_update_intervals(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->intervals.count,
 					    SENSOR_LIST_UPDATE_INTERVALS,
-					    sizeof(*msg), &upriv);
+					    sizeof(struct scmi_msg_sensor_list_update_intervals),
+					    &upriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
 	return ph->hops->iter_response_run(iter);
 }
 
+struct scmi_apriv {
+	bool any_axes_support_extended_names;
+	struct scmi_sensor_info *s;
+};
+
 static void iter_axes_desc_prepare_message(void *message,
 					   const unsigned int desc_index,
 					   const void *priv)
 {
 	struct scmi_msg_sensor_axis_description_get *msg = message;
-	const struct scmi_sensor_info *s = priv;
+	const struct scmi_apriv *apriv = priv;
 
 	/* Set the number of sensors to be skipped/already read */
-	msg->id = cpu_to_le32(s->id);
+	msg->id = cpu_to_le32(apriv->s->id);
 	msg->axis_desc_index = cpu_to_le32(desc_index);
 }
 
@@ -393,19 +398,21 @@ iter_axes_desc_process_response(const struct scmi_protocol_handle *ph,
 	u32 attrh, attrl;
 	struct scmi_sensor_axis_info *a;
 	size_t dsize = SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ;
-	struct scmi_sensor_info *s = priv;
+	struct scmi_apriv *apriv = priv;
 	const struct scmi_axis_descriptor *adesc = st->priv;
 
 	attrl = le32_to_cpu(adesc->attributes_low);
+	if (SUPPORTS_EXTENDED_AXIS_NAMES(attrl))
+		apriv->any_axes_support_extended_names = true;
 
-	a = &s->axis[st->desc_index + st->loop_idx];
+	a = &apriv->s->axis[st->desc_index + st->loop_idx];
 	a->id = le32_to_cpu(adesc->id);
 	a->extended_attrs = SUPPORTS_EXTEND_ATTRS(attrl);
 
 	attrh = le32_to_cpu(adesc->attributes_high);
 	a->scale = S32_EXT(SENSOR_SCALE(attrh));
 	a->type = SENSOR_TYPE(attrh);
-	strscpy(a->name, adesc->name, SCMI_MAX_STR_SIZE);
+	strscpy(a->name, adesc->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 	if (a->extended_attrs) {
 		unsigned int ares = le32_to_cpu(adesc->resolution);
@@ -444,10 +451,19 @@ iter_axes_extended_name_process_response(const struct scmi_protocol_handle *ph,
 					 void *priv)
 {
 	struct scmi_sensor_axis_info *a;
-	const struct scmi_sensor_info *s = priv;
+	const struct scmi_apriv *apriv = priv;
 	struct scmi_sensor_axis_name_descriptor *adesc = st->priv;
+	u32 axis_id = le32_to_cpu(adesc->axis_id);
 
-	a = &s->axis[st->desc_index + st->loop_idx];
+	if (axis_id >= st->max_resources)
+		return -EPROTO;
+
+	/*
+	 * Pick the corresponding descriptor based on the axis_id embedded
+	 * in the reply since the list of axes supporting extended names
+	 * can be a subset of all the axes.
+	 */
+	a = &apriv->s->axis[axis_id];
 	strscpy(a->name, adesc->name, SCMI_MAX_STR_SIZE);
 	st->priv = ++adesc;
 
@@ -458,21 +474,36 @@ static int
 scmi_sensor_axis_extended_names_get(const struct scmi_protocol_handle *ph,
 				    struct scmi_sensor_info *s)
 {
+	int ret;
 	void *iter;
-	struct scmi_msg_sensor_axis_description_get *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_axes_desc_prepare_message,
 		.update_state = iter_axes_extended_name_update_state,
 		.process_response = iter_axes_extended_name_process_response,
 	};
+	struct scmi_apriv apriv = {
+		.any_axes_support_extended_names = false,
+		.s = s,
+	};
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_NAME_GET,
-					    sizeof(*msg), s);
+					    sizeof(struct scmi_msg_sensor_axis_description_get),
+					    &apriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
-	return ph->hops->iter_response_run(iter);
+	/*
+	 * Do not cause whole protocol initialization failure when failing to
+	 * get extended names for axes.
+	 */
+	ret = ph->hops->iter_response_run(iter);
+	if (ret)
+		dev_warn(ph->dev,
+			 "Failed to get axes extended names for %s (ret:%d).\n",
+			 s->name, ret);
+
+	return 0;
 }
 
 static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
@@ -481,12 +512,15 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_sensor_axis_description_get *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_axes_desc_prepare_message,
 		.update_state = iter_axes_desc_update_state,
 		.process_response = iter_axes_desc_process_response,
 	};
+	struct scmi_apriv apriv = {
+		.any_axes_support_extended_names = false,
+		.s = s,
+	};
 
 	s->axis = devm_kcalloc(ph->dev, s->num_axis,
 			       sizeof(*s->axis), GFP_KERNEL);
@@ -495,7 +529,8 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, s->num_axis,
 					    SENSOR_AXIS_DESCRIPTION_GET,
-					    sizeof(*msg), s);
+					    sizeof(struct scmi_msg_sensor_axis_description_get),
+					    &apriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
@@ -503,7 +538,8 @@ static int scmi_sensor_axis_description(const struct scmi_protocol_handle *ph,
 	if (ret)
 		return ret;
 
-	if (PROTOCOL_REV_MAJOR(version) >= 0x3)
+	if (PROTOCOL_REV_MAJOR(version) >= 0x3 &&
+	    apriv.any_axes_support_extended_names)
 		ret = scmi_sensor_axis_extended_names_get(ph, s);
 
 	return ret;
@@ -598,7 +634,7 @@ iter_sens_descr_process_response(const struct scmi_protocol_handle *ph,
 			    SUPPORTS_AXIS(attrh) ?
 			    SENSOR_AXIS_NUMBER(attrh) : 0,
 			    SCMI_MAX_NUM_SENSOR_AXIS);
-	strscpy(s->name, sdesc->name, SCMI_MAX_STR_SIZE);
+	strscpy(s->name, sdesc->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 	/*
 	 * If supported overwrite short name with the extended
diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c
index 9d195d8719ab..eaa8d944926a 100644
--- a/drivers/firmware/arm_scmi/voltage.c
+++ b/drivers/firmware/arm_scmi/voltage.c
@@ -180,7 +180,6 @@ static int scmi_voltage_levels_get(const struct scmi_protocol_handle *ph,
 {
 	int ret;
 	void *iter;
-	struct scmi_msg_cmd_describe_levels *msg;
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_volt_levels_prepare_message,
 		.update_state = iter_volt_levels_update_state,
@@ -193,7 +192,8 @@ static int scmi_voltage_levels_get(const struct scmi_protocol_handle *ph,
 
 	iter = ph->hops->iter_response_init(ph, &ops, v->num_levels,
 					    VOLTAGE_DESCRIBE_LEVELS,
-					    sizeof(*msg), &vpriv);
+					    sizeof(struct scmi_msg_cmd_describe_levels),
+					    &vpriv);
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
@@ -225,15 +225,14 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,
 
 		/* Retrieve domain attributes at first ... */
 		put_unaligned_le32(dom, td->tx.buf);
-		ret = ph->xops->do_xfer(ph, td);
 		/* Skip domain on comms error */
-		if (ret)
+		if (ph->xops->do_xfer(ph, td))
 			continue;
 
 		v = vinfo->domains + dom;
 		v->id = dom;
 		attributes = le32_to_cpu(resp_dom->attr);
-		strlcpy(v->name, resp_dom->name, SCMI_MAX_STR_SIZE);
+		strscpy(v->name, resp_dom->name, SCMI_SHORT_NAME_MAX_SIZE);
 
 		/*
 		 * If supported overwrite short name with the extended one;
@@ -249,12 +248,8 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,
 				v->async_level_set = true;
 		}
 
-		ret = scmi_voltage_levels_get(ph, v);
 		/* Skip invalid voltage descriptors */
-		if (ret)
-			continue;
-
-		ph->xops->reset_rx_to_maxsz(ph, td);
+		scmi_voltage_levels_get(ph, v);
 	}
 
 	ph->xops->xfer_put(ph, td);
diff --git a/drivers/firmware/efi/Kconfig b/drivers/firmware/efi/Kconfig
index 7aa4717cdcac..6fd4414c4836 100644
--- a/drivers/firmware/efi/Kconfig
+++ b/drivers/firmware/efi/Kconfig
@@ -145,6 +145,7 @@ config EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER
 
 config EFI_BOOTLOADER_CONTROL
 	tristate "EFI Bootloader Control"
+	select UCS2_STRING
 	default n
 	help
 	  This module installs a reboot hook, such that if reboot() is
diff --git a/drivers/firmware/efi/efi-init.c b/drivers/firmware/efi/efi-init.c
index b2c829e95bd1..3928dbff76d0 100644
--- a/drivers/firmware/efi/efi-init.c
+++ b/drivers/firmware/efi/efi-init.c
@@ -240,6 +240,7 @@ void __init efi_init(void)
 	 * And now, memblock is fully populated, it is time to do capping.
 	 */
 	early_init_dt_check_for_usable_mem_range();
+	efi_find_mirror();
 	efi_esrt_init();
 	efi_mokvar_table_init();
 
diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
index 860534bcfdac..1064e33b0598 100644
--- a/drivers/firmware/efi/efi.c
+++ b/drivers/firmware/efi/efi.c
@@ -57,7 +57,7 @@ static unsigned long __initdata mem_reserve = EFI_INVALID_TABLE_ADDR;
 static unsigned long __initdata rt_prop = EFI_INVALID_TABLE_ADDR;
 
 struct mm_struct efi_mm = {
-	.mm_rb			= RB_ROOT,
+	.mm_mt			= MTREE_INIT_EXT(mm_mt, MM_MT_FLAGS, efi_mm.mmap_lock),
 	.mm_users		= ATOMIC_INIT(2),
 	.mm_count		= ATOMIC_INIT(1),
 	.write_protect_seq      = SEQCNT_ZERO(efi_mm.write_protect_seq),
@@ -202,7 +202,7 @@ static void generic_ops_unregister(void)
 }
 
 #ifdef CONFIG_EFI_CUSTOM_SSDT_OVERLAYS
-#define EFIVAR_SSDT_NAME_MAX	16
+#define EFIVAR_SSDT_NAME_MAX	16UL
 static char efivar_ssdt[EFIVAR_SSDT_NAME_MAX] __initdata;
 static int __init efivar_ssdt_setup(char *str)
 {
@@ -219,83 +219,62 @@ static int __init efivar_ssdt_setup(char *str)
 }
 __setup("efivar_ssdt=", efivar_ssdt_setup);
 
-static __init int efivar_ssdt_iter(efi_char16_t *name, efi_guid_t vendor,
-				   unsigned long name_size, void *data)
-{
-	struct efivar_entry *entry;
-	struct list_head *list = data;
-	char utf8_name[EFIVAR_SSDT_NAME_MAX];
-	int limit = min_t(unsigned long, EFIVAR_SSDT_NAME_MAX, name_size);
-
-	ucs2_as_utf8(utf8_name, name, limit - 1);
-	if (strncmp(utf8_name, efivar_ssdt, limit) != 0)
-		return 0;
-
-	entry = kmalloc(sizeof(*entry), GFP_KERNEL);
-	if (!entry)
-		return 0;
-
-	memcpy(entry->var.VariableName, name, name_size);
-	memcpy(&entry->var.VendorGuid, &vendor, sizeof(efi_guid_t));
-
-	efivar_entry_add(entry, list);
-
-	return 0;
-}
-
 static __init int efivar_ssdt_load(void)
 {
-	LIST_HEAD(entries);
-	struct efivar_entry *entry, *aux;
-	unsigned long size;
-	void *data;
-	int ret;
+	unsigned long name_size = 256;
+	efi_char16_t *name = NULL;
+	efi_status_t status;
+	efi_guid_t guid;
 
 	if (!efivar_ssdt[0])
 		return 0;
 
-	ret = efivar_init(efivar_ssdt_iter, &entries, true, &entries);
-
-	list_for_each_entry_safe(entry, aux, &entries, list) {
-		pr_info("loading SSDT from variable %s-%pUl\n", efivar_ssdt,
-			&entry->var.VendorGuid);
+	name = kzalloc(name_size, GFP_KERNEL);
+	if (!name)
+		return -ENOMEM;
 
-		list_del(&entry->list);
+	for (;;) {
+		char utf8_name[EFIVAR_SSDT_NAME_MAX];
+		unsigned long data_size = 0;
+		void *data;
+		int limit;
 
-		ret = efivar_entry_size(entry, &size);
-		if (ret) {
-			pr_err("failed to get var size\n");
-			goto free_entry;
+		status = efi.get_next_variable(&name_size, name, &guid);
+		if (status == EFI_NOT_FOUND) {
+			break;
+		} else if (status == EFI_BUFFER_TOO_SMALL) {
+			name = krealloc(name, name_size, GFP_KERNEL);
+			if (!name)
+				return -ENOMEM;
+			continue;
 		}
 
-		data = kmalloc(size, GFP_KERNEL);
-		if (!data) {
-			ret = -ENOMEM;
-			goto free_entry;
-		}
+		limit = min(EFIVAR_SSDT_NAME_MAX, name_size);
+		ucs2_as_utf8(utf8_name, name, limit - 1);
+		if (strncmp(utf8_name, efivar_ssdt, limit) != 0)
+			continue;
 
-		ret = efivar_entry_get(entry, NULL, &size, data);
-		if (ret) {
-			pr_err("failed to get var data\n");
-			goto free_data;
-		}
+		pr_info("loading SSDT from variable %s-%pUl\n", efivar_ssdt, &guid);
 
-		ret = acpi_load_table(data, NULL);
-		if (ret) {
-			pr_err("failed to load table: %d\n", ret);
-			goto free_data;
-		}
+		status = efi.get_variable(name, &guid, NULL, &data_size, NULL);
+		if (status != EFI_BUFFER_TOO_SMALL || !data_size)
+			return -EIO;
 
-		goto free_entry;
+		data = kmalloc(data_size, GFP_KERNEL);
+		if (!data)
+			return -ENOMEM;
 
-free_data:
+		status = efi.get_variable(name, &guid, NULL, &data_size, data);
+		if (status == EFI_SUCCESS) {
+			acpi_status ret = acpi_load_table(data, NULL);
+			if (ret)
+				pr_err("failed to load table: %u\n", ret);
+		} else {
+			pr_err("failed to get var data: 0x%lx\n", status);
+		}
 		kfree(data);
-
-free_entry:
-		kfree(entry);
 	}
-
-	return ret;
+	return 0;
 }
 #else
 static inline int efivar_ssdt_load(void) { return 0; }
@@ -446,6 +425,29 @@ static int __init efisubsys_init(void)
 
 subsys_initcall(efisubsys_init);
 
+void __init efi_find_mirror(void)
+{
+	efi_memory_desc_t *md;
+	u64 mirror_size = 0, total_size = 0;
+
+	if (!efi_enabled(EFI_MEMMAP))
+		return;
+
+	for_each_efi_memory_desc(md) {
+		unsigned long long start = md->phys_addr;
+		unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
+
+		total_size += size;
+		if (md->attribute & EFI_MEMORY_MORE_RELIABLE) {
+			memblock_mark_mirror(start, size);
+			mirror_size += size;
+		}
+	}
+	if (mirror_size)
+		pr_info("Memory: %lldM/%lldM mirrored memory\n",
+			mirror_size>>20, total_size>>20);
+}
+
 /*
  * Find the efi memory descriptor for a given physical address.  Given a
  * physical address, determine if it exists within an EFI Memory Map entry,
diff --git a/drivers/firmware/efi/efibc.c b/drivers/firmware/efi/efibc.c
index 15a47539dc56..8ced7af8e56d 100644
--- a/drivers/firmware/efi/efibc.c
+++ b/drivers/firmware/efi/efibc.c
@@ -10,69 +10,51 @@
 #include <linux/module.h>
 #include <linux/reboot.h>
 #include <linux/slab.h>
+#include <linux/ucs2_string.h>
 
-static void efibc_str_to_str16(const char *str, efi_char16_t *str16)
-{
-	size_t i;
-
-	for (i = 0; i < strlen(str); i++)
-		str16[i] = str[i];
-
-	str16[i] = '\0';
-}
+#define MAX_DATA_LEN	512
 
-static int efibc_set_variable(const char *name, const char *value)
+static int efibc_set_variable(efi_char16_t *name, efi_char16_t *value,
+			      unsigned long len)
 {
-	int ret;
-	efi_guid_t guid = LINUX_EFI_LOADER_ENTRY_GUID;
-	struct efivar_entry *entry;
-	size_t size = (strlen(value) + 1) * sizeof(efi_char16_t);
+	efi_status_t status;
 
-	if (size > sizeof(entry->var.Data)) {
-		pr_err("value is too large (%zu bytes) for '%s' EFI variable\n", size, name);
-		return -EINVAL;
-	}
+	status = efi.set_variable(name, &LINUX_EFI_LOADER_ENTRY_GUID,
+				  EFI_VARIABLE_NON_VOLATILE
+				  | EFI_VARIABLE_BOOTSERVICE_ACCESS
+				  | EFI_VARIABLE_RUNTIME_ACCESS,
+				  len * sizeof(efi_char16_t), value);
 
-	entry = kmalloc(sizeof(*entry), GFP_KERNEL);
-	if (!entry) {
-		pr_err("failed to allocate efivar entry for '%s' EFI variable\n", name);
-		return -ENOMEM;
+	if (status != EFI_SUCCESS) {
+		pr_err("failed to set EFI variable: 0x%lx\n", status);
+		return -EIO;
 	}
-
-	efibc_str_to_str16(name, entry->var.VariableName);
-	efibc_str_to_str16(value, (efi_char16_t *)entry->var.Data);
-	memcpy(&entry->var.VendorGuid, &guid, sizeof(guid));
-
-	ret = efivar_entry_set_safe(entry->var.VariableName,
-				    entry->var.VendorGuid,
-				    EFI_VARIABLE_NON_VOLATILE
-				    | EFI_VARIABLE_BOOTSERVICE_ACCESS
-				    | EFI_VARIABLE_RUNTIME_ACCESS,
-				    false, size, entry->var.Data);
-
-	if (ret)
-		pr_err("failed to set %s EFI variable: 0x%x\n",
-		       name, ret);
-
-	kfree(entry);
-	return ret;
+	return 0;
 }
 
 static int efibc_reboot_notifier_call(struct notifier_block *notifier,
 				      unsigned long event, void *data)
 {
-	const char *reason = "shutdown";
+	efi_char16_t *reason = event == SYS_RESTART ? L"reboot"
+						    : L"shutdown";
+	const u8 *str = data;
+	efi_char16_t *wdata;
+	unsigned long l;
 	int ret;
 
-	if (event == SYS_RESTART)
-		reason = "reboot";
-
-	ret = efibc_set_variable("LoaderEntryRebootReason", reason);
+	ret = efibc_set_variable(L"LoaderEntryRebootReason", reason,
+				 ucs2_strlen(reason));
 	if (ret || !data)
 		return NOTIFY_DONE;
 
-	efibc_set_variable("LoaderEntryOneShot", (char *)data);
+	wdata = kmalloc(MAX_DATA_LEN * sizeof(efi_char16_t), GFP_KERNEL);
+	for (l = 0; l < MAX_DATA_LEN - 1 && str[l] != '\0'; l++)
+		wdata[l] = str[l];
+	wdata[l] = L'\0';
+
+	efibc_set_variable(L"LoaderEntryOneShot", wdata, l);
 
+	kfree(wdata);
 	return NOTIFY_DONE;
 }
 
@@ -84,7 +66,7 @@ static int __init efibc_init(void)
 {
 	int ret;
 
-	if (!efivars_kobject() || !efivar_supports_writes())
+	if (!efi_rt_services_supported(EFI_RT_SUPPORTED_SET_VARIABLE))
 		return -ENODEV;
 
 	ret = register_reboot_notifier(&efibc_reboot_notifier);
diff --git a/drivers/firmware/efi/memmap.c b/drivers/firmware/efi/memmap.c
index 4df55a55da84..cf87dd7bbd25 100644
--- a/drivers/firmware/efi/memmap.c
+++ b/drivers/firmware/efi/memmap.c
@@ -59,8 +59,7 @@ static void __init efi_memmap_free(void)
  * Depending on whether mm_init() has already been invoked or not,
  * either memblock or "normal" page allocation is used.
  *
- * Returns the physical address of the allocated memory map on
- * success, zero on failure.
+ * Returns zero on success, a negative error code on failure.
  */
 int __init efi_memmap_alloc(unsigned int num_entries,
 		struct efi_memory_map_data *data)
diff --git a/drivers/firmware/efi/sysfb_efi.c b/drivers/firmware/efi/sysfb_efi.c
index 4c7c9dd7733f..7882d4b3f2be 100644
--- a/drivers/firmware/efi/sysfb_efi.c
+++ b/drivers/firmware/efi/sysfb_efi.c
@@ -26,8 +26,6 @@
 #include <linux/sysfb.h>
 #include <video/vga.h>
 
-#include <asm/efi.h>
-
 enum {
 	OVERRIDE_NONE = 0x0,
 	OVERRIDE_BASE = 0x1,
diff --git a/drivers/firmware/mtk-adsp-ipc.c b/drivers/firmware/mtk-adsp-ipc.c
index cb255a99170c..3c071f814455 100644
--- a/drivers/firmware/mtk-adsp-ipc.c
+++ b/drivers/firmware/mtk-adsp-ipc.c
@@ -12,6 +12,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
+static const char * const adsp_mbox_ch_names[MTK_ADSP_MBOX_NUM] = { "rx", "tx" };
+
 /*
  * mtk_adsp_ipc_send - send ipc cmd to MTK ADSP
  *
@@ -72,7 +74,6 @@ static int mtk_adsp_ipc_probe(struct platform_device *pdev)
 	struct mtk_adsp_ipc *adsp_ipc;
 	struct mtk_adsp_chan *adsp_chan;
 	struct mbox_client *cl;
-	char *chan_name;
 	int ret;
 	int i, j;
 
@@ -83,12 +84,6 @@ static int mtk_adsp_ipc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	for (i = 0; i < MTK_ADSP_MBOX_NUM; i++) {
-		chan_name = kasprintf(GFP_KERNEL, "mbox%d", i);
-		if (!chan_name) {
-			ret = -ENOMEM;
-			goto out;
-		}
-
 		adsp_chan = &adsp_ipc->chans[i];
 		cl = &adsp_chan->cl;
 		cl->dev = dev->parent;
@@ -99,17 +94,20 @@ static int mtk_adsp_ipc_probe(struct platform_device *pdev)
 
 		adsp_chan->ipc = adsp_ipc;
 		adsp_chan->idx = i;
-		adsp_chan->ch = mbox_request_channel_byname(cl, chan_name);
+		adsp_chan->ch = mbox_request_channel_byname(cl, adsp_mbox_ch_names[i]);
 		if (IS_ERR(adsp_chan->ch)) {
 			ret = PTR_ERR(adsp_chan->ch);
 			if (ret != -EPROBE_DEFER)
-				dev_err(dev, "Failed to request mbox chan %d ret %d\n",
-					i, ret);
-			goto out_free;
-		}
+				dev_err(dev, "Failed to request mbox chan %s ret %d\n",
+					adsp_mbox_ch_names[i], ret);
+
+			for (j = 0; j < i; j++) {
+				adsp_chan = &adsp_ipc->chans[j];
+				mbox_free_channel(adsp_chan->ch);
+			}
 
-		dev_dbg(dev, "request mbox chan %s\n", chan_name);
-		kfree(chan_name);
+			return ret;
+		}
 	}
 
 	adsp_ipc->dev = dev;
@@ -117,16 +115,6 @@ static int mtk_adsp_ipc_probe(struct platform_device *pdev)
 	dev_dbg(dev, "MTK ADSP IPC initialized\n");
 
 	return 0;
-
-out_free:
-	kfree(chan_name);
-out:
-	for (j = 0; j < i; j++) {
-		adsp_chan = &adsp_ipc->chans[j];
-		mbox_free_channel(adsp_chan->ch);
-	}
-
-	return ret;
 }
 
 static int mtk_adsp_ipc_remove(struct platform_device *pdev)
diff --git a/drivers/firmware/sysfb.c b/drivers/firmware/sysfb.c
index 2bfbb05f7d89..1f276f108cc9 100644
--- a/drivers/firmware/sysfb.c
+++ b/drivers/firmware/sysfb.c
@@ -34,21 +34,59 @@
 #include <linux/screen_info.h>
 #include <linux/sysfb.h>
 
+static struct platform_device *pd;
+static DEFINE_MUTEX(disable_lock);
+static bool disabled;
+
+static bool sysfb_unregister(void)
+{
+	if (IS_ERR_OR_NULL(pd))
+		return false;
+
+	platform_device_unregister(pd);
+	pd = NULL;
+
+	return true;
+}
+
+/**
+ * sysfb_disable() - disable the Generic System Framebuffers support
+ *
+ * This disables the registration of system framebuffer devices that match the
+ * generic drivers that make use of the system framebuffer set up by firmware.
+ *
+ * It also unregisters a device if this was already registered by sysfb_init().
+ *
+ * Context: The function can sleep. A @disable_lock mutex is acquired to serialize
+ *          against sysfb_init(), that registers a system framebuffer device.
+ */
+void sysfb_disable(void)
+{
+	mutex_lock(&disable_lock);
+	sysfb_unregister();
+	disabled = true;
+	mutex_unlock(&disable_lock);
+}
+EXPORT_SYMBOL_GPL(sysfb_disable);
+
 static __init int sysfb_init(void)
 {
 	struct screen_info *si = &screen_info;
 	struct simplefb_platform_data mode;
-	struct platform_device *pd;
 	const char *name;
 	bool compatible;
-	int ret;
+	int ret = 0;
+
+	mutex_lock(&disable_lock);
+	if (disabled)
+		goto unlock_mutex;
 
 	/* try to create a simple-framebuffer device */
 	compatible = sysfb_parse_mode(si, &mode);
 	if (compatible) {
-		ret = sysfb_create_simplefb(si, &mode);
-		if (!ret)
-			return 0;
+		pd = sysfb_create_simplefb(si, &mode);
+		if (!IS_ERR(pd))
+			goto unlock_mutex;
 	}
 
 	/* if the FB is incompatible, create a legacy framebuffer device */
@@ -60,8 +98,10 @@ static __init int sysfb_init(void)
 		name = "platform-framebuffer";
 
 	pd = platform_device_alloc(name, 0);
-	if (!pd)
-		return -ENOMEM;
+	if (!pd) {
+		ret = -ENOMEM;
+		goto unlock_mutex;
+	}
 
 	sysfb_apply_efi_quirks(pd);
 
@@ -73,9 +113,11 @@ static __init int sysfb_init(void)
 	if (ret)
 		goto err;
 
-	return 0;
+	goto unlock_mutex;
 err:
 	platform_device_put(pd);
+unlock_mutex:
+	mutex_unlock(&disable_lock);
 	return ret;
 }
 
diff --git a/drivers/firmware/sysfb_simplefb.c b/drivers/firmware/sysfb_simplefb.c
index bda8712bfd8c..a353e27f83f5 100644
--- a/drivers/firmware/sysfb_simplefb.c
+++ b/drivers/firmware/sysfb_simplefb.c
@@ -57,8 +57,8 @@ __init bool sysfb_parse_mode(const struct screen_info *si,
 	return false;
 }
 
-__init int sysfb_create_simplefb(const struct screen_info *si,
-				 const struct simplefb_platform_data *mode)
+__init struct platform_device *sysfb_create_simplefb(const struct screen_info *si,
+						     const struct simplefb_platform_data *mode)
 {
 	struct platform_device *pd;
 	struct resource res;
@@ -76,7 +76,7 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 		base |= (u64)si->ext_lfb_base << 32;
 	if (!base || (u64)(resource_size_t)base != base) {
 		printk(KERN_DEBUG "sysfb: inaccessible VRAM base\n");
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 	}
 
 	/*
@@ -93,7 +93,7 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	length = mode->height * mode->stride;
 	if (length > size) {
 		printk(KERN_WARNING "sysfb: VRAM smaller than advertised\n");
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 	}
 	length = PAGE_ALIGN(length);
 
@@ -104,11 +104,11 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	res.start = base;
 	res.end = res.start + length - 1;
 	if (res.end <= res.start)
-		return -EINVAL;
+		return ERR_PTR(-EINVAL);
 
 	pd = platform_device_alloc("simple-framebuffer", 0);
 	if (!pd)
-		return -ENOMEM;
+		return ERR_PTR(-ENOMEM);
 
 	sysfb_apply_efi_quirks(pd);
 
@@ -124,10 +124,10 @@ __init int sysfb_create_simplefb(const struct screen_info *si,
 	if (ret)
 		goto err_put_device;
 
-	return 0;
+	return pd;
 
 err_put_device:
 	platform_device_put(pd);
 
-	return ret;
+	return ERR_PTR(ret);
 }
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 991b3f361ec9..0831eecc9a09 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -243,4 +243,16 @@ config FPGA_MGR_VERSAL_FPGA
 	  configure the programmable logic(PL).
 
 	  To compile this as a module, choose M here.
+
+config FPGA_M10_BMC_SEC_UPDATE
+	tristate "Intel MAX10 BMC Secure Update driver"
+	depends on MFD_INTEL_M10_BMC && FW_UPLOAD
+	help
+	  Secure update support for the Intel MAX10 board management
+	  controller.
+
+	  This is a subdriver of the Intel MAX10 board management controller
+	  (BMC) and provides support for secure updates for the BMC image,
+	  the FPGA image, the Root Entry Hashes, etc.
+
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 5935b3d0abd5..139ac1b573d3 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -22,6 +22,9 @@ obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)		+= altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)	+= altera-pr-ip-core-plat.o
 
+# FPGA Secure Update Drivers
+obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE)	+= intel-m10-bmc-sec-update.o
+
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
 obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
index be0667968d33..df8671af4a92 100644
--- a/drivers/fpga/altera-pr-ip-core.c
+++ b/drivers/fpga/altera-pr-ip-core.c
@@ -108,7 +108,7 @@ static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
 	u32 *buffer_32 = (u32 *)buf;
 	size_t i = 0;
 
-	if (count <= 0)
+	if (!count)
 		return -EINVAL;
 
 	/* Write out the complete 32-bit chunks */
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 6bff39ff21a0..5498bc337f8b 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -342,7 +342,7 @@ static void release_dfl_dev(struct device *dev)
 	if (ddev->mmio_res.parent)
 		release_resource(&ddev->mmio_res);
 
-	ida_simple_remove(&dfl_device_ida, ddev->id);
+	ida_free(&dfl_device_ida, ddev->id);
 	kfree(ddev->irqs);
 	kfree(ddev);
 }
@@ -360,7 +360,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata,
 	if (!ddev)
 		return ERR_PTR(-ENOMEM);
 
-	id = ida_simple_get(&dfl_device_ida, 0, 0, GFP_KERNEL);
+	id = ida_alloc(&dfl_device_ida, GFP_KERNEL);
 	if (id < 0) {
 		dev_err(&pdev->dev, "unable to get id\n");
 		kfree(ddev);
diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
index 16f2b164a178..727704431f61 100644
--- a/drivers/fpga/fpga-bridge.c
+++ b/drivers/fpga/fpga-bridge.c
@@ -342,7 +342,7 @@ fpga_bridge_register(struct device *parent, const char *name,
 	if (!bridge)
 		return ERR_PTR(-ENOMEM);
 
-	id = ida_simple_get(&fpga_bridge_ida, 0, 0, GFP_KERNEL);
+	id = ida_alloc(&fpga_bridge_ida, GFP_KERNEL);
 	if (id < 0) {
 		ret = id;
 		goto error_kfree;
@@ -375,7 +375,7 @@ fpga_bridge_register(struct device *parent, const char *name,
 	return bridge;
 
 error_device:
-	ida_simple_remove(&fpga_bridge_ida, id);
+	ida_free(&fpga_bridge_ida, id);
 error_kfree:
 	kfree(bridge);
 
@@ -407,7 +407,7 @@ static void fpga_bridge_dev_release(struct device *dev)
 {
 	struct fpga_bridge *bridge = to_fpga_bridge(dev);
 
-	ida_simple_remove(&fpga_bridge_ida, bridge->dev.id);
+	ida_free(&fpga_bridge_ida, bridge->dev.id);
 	kfree(bridge);
 }
 
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index a3595ecc3f79..08dc85fcd511 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -623,7 +623,7 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
 	if (!mgr)
 		return ERR_PTR(-ENOMEM);
 
-	id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
+	id = ida_alloc(&fpga_mgr_ida, GFP_KERNEL);
 	if (id < 0) {
 		ret = id;
 		goto error_kfree;
@@ -662,7 +662,7 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
 	return mgr;
 
 error_device:
-	ida_simple_remove(&fpga_mgr_ida, id);
+	ida_free(&fpga_mgr_ida, id);
 error_kfree:
 	kfree(mgr);
 
@@ -790,7 +790,7 @@ static void fpga_mgr_dev_release(struct device *dev)
 {
 	struct fpga_manager *mgr = to_fpga_manager(dev);
 
-	ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
+	ida_free(&fpga_mgr_ida, mgr->dev.id);
 	kfree(mgr);
 }
 
diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c
index 485948e3c0db..27ff9dea04ae 100644
--- a/drivers/fpga/fpga-region.c
+++ b/drivers/fpga/fpga-region.c
@@ -202,7 +202,7 @@ fpga_region_register_full(struct device *parent, const struct fpga_region_info *
 	if (!region)
 		return ERR_PTR(-ENOMEM);
 
-	id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL);
+	id = ida_alloc(&fpga_region_ida, GFP_KERNEL);
 	if (id < 0) {
 		ret = id;
 		goto err_free;
@@ -234,7 +234,7 @@ fpga_region_register_full(struct device *parent, const struct fpga_region_info *
 	return region;
 
 err_remove:
-	ida_simple_remove(&fpga_region_ida, id);
+	ida_free(&fpga_region_ida, id);
 err_free:
 	kfree(region);
 
@@ -283,7 +283,7 @@ static void fpga_region_dev_release(struct device *dev)
 {
 	struct fpga_region *region = to_fpga_region(dev);
 
-	ida_simple_remove(&fpga_region_ida, region->dev.id);
+	ida_free(&fpga_region_ida, region->dev.id);
 	kfree(region);
 }
 
diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c
new file mode 100644
index 000000000000..72c677c910de
--- /dev/null
+++ b/drivers/fpga/intel-m10-bmc-sec-update.c
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel MAX10 Board Management Controller Secure Update Driver
+ *
+ * Copyright (C) 2019-2022 Intel Corporation. All rights reserved.
+ *
+ */
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/mfd/intel-m10-bmc.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+struct m10bmc_sec {
+	struct device *dev;
+	struct intel_m10bmc *m10bmc;
+	struct fw_upload *fwl;
+	char *fw_name;
+	u32 fw_name_id;
+	bool cancel_request;
+};
+
+static DEFINE_XARRAY_ALLOC(fw_upload_xa);
+
+/* Root Entry Hash (REH) support */
+#define REH_SHA256_SIZE		32
+#define REH_SHA384_SIZE		48
+#define REH_MAGIC		GENMASK(15, 0)
+#define REH_SHA_NUM_BYTES	GENMASK(31, 16)
+
+static ssize_t
+show_root_entry_hash(struct device *dev, u32 exp_magic,
+		     u32 prog_addr, u32 reh_addr, char *buf)
+{
+	struct m10bmc_sec *sec = dev_get_drvdata(dev);
+	int sha_num_bytes, i, ret, cnt = 0;
+	u8 hash[REH_SHA384_SIZE];
+	unsigned int stride;
+	u32 magic;
+
+	stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+	ret = m10bmc_raw_read(sec->m10bmc, prog_addr, &magic);
+	if (ret)
+		return ret;
+
+	if (FIELD_GET(REH_MAGIC, magic) != exp_magic)
+		return sysfs_emit(buf, "hash not programmed\n");
+
+	sha_num_bytes = FIELD_GET(REH_SHA_NUM_BYTES, magic) / 8;
+	if ((sha_num_bytes % stride) ||
+	    (sha_num_bytes != REH_SHA256_SIZE &&
+	     sha_num_bytes != REH_SHA384_SIZE))   {
+		dev_err(sec->dev, "%s bad sha num bytes %d\n", __func__,
+			sha_num_bytes);
+		return -EINVAL;
+	}
+
+	ret = regmap_bulk_read(sec->m10bmc->regmap, reh_addr,
+			       hash, sha_num_bytes / stride);
+	if (ret) {
+		dev_err(dev, "failed to read root entry hash: %x cnt %x: %d\n",
+			reh_addr, sha_num_bytes / stride, ret);
+		return ret;
+	}
+
+	for (i = 0; i < sha_num_bytes; i++)
+		cnt += sprintf(buf + cnt, "%02x", hash[i]);
+	cnt += sprintf(buf + cnt, "\n");
+
+	return cnt;
+}
+
+#define DEVICE_ATTR_SEC_REH_RO(_name, _magic, _prog_addr, _reh_addr) \
+static ssize_t _name##_root_entry_hash_show(struct device *dev, \
+					    struct device_attribute *attr, \
+					    char *buf) \
+{ return show_root_entry_hash(dev, _magic, _prog_addr, _reh_addr, buf); } \
+static DEVICE_ATTR_RO(_name##_root_entry_hash)
+
+DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
+DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
+DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
+
+#define CSK_BIT_LEN		128U
+#define CSK_32ARRAY_SIZE	DIV_ROUND_UP(CSK_BIT_LEN, 32)
+
+static ssize_t
+show_canceled_csk(struct device *dev, u32 addr, char *buf)
+{
+	unsigned int i, stride, size = CSK_32ARRAY_SIZE * sizeof(u32);
+	struct m10bmc_sec *sec = dev_get_drvdata(dev);
+	DECLARE_BITMAP(csk_map, CSK_BIT_LEN);
+	__le32 csk_le32[CSK_32ARRAY_SIZE];
+	u32 csk32[CSK_32ARRAY_SIZE];
+	int ret;
+
+	stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+	if (size % stride) {
+		dev_err(sec->dev,
+			"CSK vector size (0x%x) not aligned to stride (0x%x)\n",
+			size, stride);
+		WARN_ON_ONCE(1);
+		return -EINVAL;
+	}
+
+	ret = regmap_bulk_read(sec->m10bmc->regmap, addr, csk_le32,
+			       size / stride);
+	if (ret) {
+		dev_err(sec->dev, "failed to read CSK vector: %x cnt %x: %d\n",
+			addr, size / stride, ret);
+		return ret;
+	}
+
+	for (i = 0; i < CSK_32ARRAY_SIZE; i++)
+		csk32[i] = le32_to_cpu(((csk_le32[i])));
+
+	bitmap_from_arr32(csk_map, csk32, CSK_BIT_LEN);
+	bitmap_complement(csk_map, csk_map, CSK_BIT_LEN);
+	return bitmap_print_to_pagebuf(1, buf, csk_map, CSK_BIT_LEN);
+}
+
+#define DEVICE_ATTR_SEC_CSK_RO(_name, _addr) \
+static ssize_t _name##_canceled_csks_show(struct device *dev, \
+					  struct device_attribute *attr, \
+					  char *buf) \
+{ return show_canceled_csk(dev, _addr, buf); } \
+static DEVICE_ATTR_RO(_name##_canceled_csks)
+
+#define CSK_VEC_OFFSET 0x34
+
+DEVICE_ATTR_SEC_CSK_RO(bmc, BMC_PROG_ADDR + CSK_VEC_OFFSET);
+DEVICE_ATTR_SEC_CSK_RO(sr, SR_PROG_ADDR + CSK_VEC_OFFSET);
+DEVICE_ATTR_SEC_CSK_RO(pr, PR_PROG_ADDR + CSK_VEC_OFFSET);
+
+#define FLASH_COUNT_SIZE 4096	/* count stored as inverted bit vector */
+
+static ssize_t flash_count_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct m10bmc_sec *sec = dev_get_drvdata(dev);
+	unsigned int stride, num_bits;
+	u8 *flash_buf;
+	int cnt, ret;
+
+	stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+	num_bits = FLASH_COUNT_SIZE * 8;
+
+	flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
+	if (!flash_buf)
+		return -ENOMEM;
+
+	if (FLASH_COUNT_SIZE % stride) {
+		dev_err(sec->dev,
+			"FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
+			FLASH_COUNT_SIZE, stride);
+		WARN_ON_ONCE(1);
+		return -EINVAL;
+	}
+
+	ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
+			       flash_buf, FLASH_COUNT_SIZE / stride);
+	if (ret) {
+		dev_err(sec->dev,
+			"failed to read flash count: %x cnt %x: %d\n",
+			STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
+		goto exit_free;
+	}
+	cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
+
+exit_free:
+	kfree(flash_buf);
+
+	return ret ? : sysfs_emit(buf, "%u\n", cnt);
+}
+static DEVICE_ATTR_RO(flash_count);
+
+static struct attribute *m10bmc_security_attrs[] = {
+	&dev_attr_flash_count.attr,
+	&dev_attr_bmc_root_entry_hash.attr,
+	&dev_attr_sr_root_entry_hash.attr,
+	&dev_attr_pr_root_entry_hash.attr,
+	&dev_attr_sr_canceled_csks.attr,
+	&dev_attr_pr_canceled_csks.attr,
+	&dev_attr_bmc_canceled_csks.attr,
+	NULL,
+};
+
+static struct attribute_group m10bmc_security_attr_group = {
+	.name = "security",
+	.attrs = m10bmc_security_attrs,
+};
+
+static const struct attribute_group *m10bmc_sec_attr_groups[] = {
+	&m10bmc_security_attr_group,
+	NULL,
+};
+
+static void log_error_regs(struct m10bmc_sec *sec, u32 doorbell)
+{
+	u32 auth_result;
+
+	dev_err(sec->dev, "RSU error status: 0x%08x\n", doorbell);
+
+	if (!m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result))
+		dev_err(sec->dev, "RSU auth result: 0x%08x\n", auth_result);
+}
+
+static enum fw_upload_err rsu_check_idle(struct m10bmc_sec *sec)
+{
+	u32 doorbell;
+	int ret;
+
+	ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	if (rsu_prog(doorbell) != RSU_PROG_IDLE &&
+	    rsu_prog(doorbell) != RSU_PROG_RSU_DONE) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_BUSY;
+	}
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+static inline bool rsu_start_done(u32 doorbell)
+{
+	u32 status, progress;
+
+	if (doorbell & DRBL_RSU_REQUEST)
+		return false;
+
+	status = rsu_stat(doorbell);
+	if (status == RSU_STAT_ERASE_FAIL || status == RSU_STAT_WEAROUT)
+		return true;
+
+	progress = rsu_prog(doorbell);
+	if (progress != RSU_PROG_IDLE && progress != RSU_PROG_RSU_DONE)
+		return true;
+
+	return false;
+}
+
+static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec)
+{
+	u32 doorbell, status;
+	int ret;
+
+	ret = regmap_update_bits(sec->m10bmc->regmap,
+				 M10BMC_SYS_BASE + M10BMC_DOORBELL,
+				 DRBL_RSU_REQUEST | DRBL_HOST_STATUS,
+				 DRBL_RSU_REQUEST |
+				 FIELD_PREP(DRBL_HOST_STATUS,
+					    HOST_STATUS_IDLE));
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	ret = regmap_read_poll_timeout(sec->m10bmc->regmap,
+				       M10BMC_SYS_BASE + M10BMC_DOORBELL,
+				       doorbell,
+				       rsu_start_done(doorbell),
+				       NIOS_HANDSHAKE_INTERVAL_US,
+				       NIOS_HANDSHAKE_TIMEOUT_US);
+
+	if (ret == -ETIMEDOUT) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_TIMEOUT;
+	} else if (ret) {
+		return FW_UPLOAD_ERR_RW_ERROR;
+	}
+
+	status = rsu_stat(doorbell);
+	if (status == RSU_STAT_WEAROUT) {
+		dev_warn(sec->dev, "Excessive flash update count detected\n");
+		return FW_UPLOAD_ERR_WEAROUT;
+	} else if (status == RSU_STAT_ERASE_FAIL) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_HW_ERROR;
+	}
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+static enum fw_upload_err rsu_prog_ready(struct m10bmc_sec *sec)
+{
+	unsigned long poll_timeout;
+	u32 doorbell, progress;
+	int ret;
+
+	ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	poll_timeout = jiffies + msecs_to_jiffies(RSU_PREP_TIMEOUT_MS);
+	while (rsu_prog(doorbell) == RSU_PROG_PREPARE) {
+		msleep(RSU_PREP_INTERVAL_MS);
+		if (time_after(jiffies, poll_timeout))
+			break;
+
+		ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
+		if (ret)
+			return FW_UPLOAD_ERR_RW_ERROR;
+	}
+
+	progress = rsu_prog(doorbell);
+	if (progress == RSU_PROG_PREPARE) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_TIMEOUT;
+	} else if (progress != RSU_PROG_READY) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_HW_ERROR;
+	}
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec)
+{
+	u32 doorbell;
+	int ret;
+
+	ret = regmap_update_bits(sec->m10bmc->regmap,
+				 M10BMC_SYS_BASE + M10BMC_DOORBELL,
+				 DRBL_HOST_STATUS,
+				 FIELD_PREP(DRBL_HOST_STATUS,
+					    HOST_STATUS_WRITE_DONE));
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	ret = regmap_read_poll_timeout(sec->m10bmc->regmap,
+				       M10BMC_SYS_BASE + M10BMC_DOORBELL,
+				       doorbell,
+				       rsu_prog(doorbell) != RSU_PROG_READY,
+				       NIOS_HANDSHAKE_INTERVAL_US,
+				       NIOS_HANDSHAKE_TIMEOUT_US);
+
+	if (ret == -ETIMEDOUT) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_TIMEOUT;
+	} else if (ret) {
+		return FW_UPLOAD_ERR_RW_ERROR;
+	}
+
+	switch (rsu_stat(doorbell)) {
+	case RSU_STAT_NORMAL:
+	case RSU_STAT_NIOS_OK:
+	case RSU_STAT_USER_OK:
+	case RSU_STAT_FACTORY_OK:
+		break;
+	default:
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_HW_ERROR;
+	}
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+static int rsu_check_complete(struct m10bmc_sec *sec, u32 *doorbell)
+{
+	if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, doorbell))
+		return -EIO;
+
+	switch (rsu_stat(*doorbell)) {
+	case RSU_STAT_NORMAL:
+	case RSU_STAT_NIOS_OK:
+	case RSU_STAT_USER_OK:
+	case RSU_STAT_FACTORY_OK:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (rsu_prog(*doorbell)) {
+	case RSU_PROG_IDLE:
+	case RSU_PROG_RSU_DONE:
+		return 0;
+	case RSU_PROG_AUTHENTICATING:
+	case RSU_PROG_COPYING:
+	case RSU_PROG_UPDATE_CANCEL:
+	case RSU_PROG_PROGRAM_KEY_HASH:
+		return -EAGAIN;
+	default:
+		return -EINVAL;
+	}
+}
+
+static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec)
+{
+	u32 doorbell;
+	int ret;
+
+	ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	if (rsu_prog(doorbell) != RSU_PROG_READY)
+		return FW_UPLOAD_ERR_BUSY;
+
+	ret = regmap_update_bits(sec->m10bmc->regmap,
+				 M10BMC_SYS_BASE + M10BMC_DOORBELL,
+				 DRBL_HOST_STATUS,
+				 FIELD_PREP(DRBL_HOST_STATUS,
+					    HOST_STATUS_ABORT_RSU));
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	return FW_UPLOAD_ERR_CANCELED;
+}
+
+static enum fw_upload_err m10bmc_sec_prepare(struct fw_upload *fwl,
+					     const u8 *data, u32 size)
+{
+	struct m10bmc_sec *sec = fwl->dd_handle;
+	u32 ret;
+
+	sec->cancel_request = false;
+
+	if (!size || size > M10BMC_STAGING_SIZE)
+		return FW_UPLOAD_ERR_INVALID_SIZE;
+
+	ret = rsu_check_idle(sec);
+	if (ret != FW_UPLOAD_ERR_NONE)
+		return ret;
+
+	ret = rsu_update_init(sec);
+	if (ret != FW_UPLOAD_ERR_NONE)
+		return ret;
+
+	ret = rsu_prog_ready(sec);
+	if (ret != FW_UPLOAD_ERR_NONE)
+		return ret;
+
+	if (sec->cancel_request)
+		return rsu_cancel(sec);
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+#define WRITE_BLOCK_SIZE 0x4000	/* Default write-block size is 0x4000 bytes */
+
+static enum fw_upload_err m10bmc_sec_write(struct fw_upload *fwl, const u8 *data,
+					   u32 offset, u32 size, u32 *written)
+{
+	struct m10bmc_sec *sec = fwl->dd_handle;
+	u32 blk_size, doorbell, extra_offset;
+	unsigned int stride, extra = 0;
+	int ret;
+
+	stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+	if (sec->cancel_request)
+		return rsu_cancel(sec);
+
+	ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell);
+	if (ret) {
+		return FW_UPLOAD_ERR_RW_ERROR;
+	} else if (rsu_prog(doorbell) != RSU_PROG_READY) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_HW_ERROR;
+	}
+
+	WARN_ON_ONCE(WRITE_BLOCK_SIZE % stride);
+	blk_size = min_t(u32, WRITE_BLOCK_SIZE, size);
+	ret = regmap_bulk_write(sec->m10bmc->regmap,
+				M10BMC_STAGING_BASE + offset,
+				(void *)data + offset,
+				blk_size / stride);
+	if (ret)
+		return FW_UPLOAD_ERR_RW_ERROR;
+
+	/*
+	 * If blk_size is not aligned to stride, then handle the extra
+	 * bytes with regmap_write.
+	 */
+	if (blk_size % stride) {
+		extra_offset = offset + ALIGN_DOWN(blk_size, stride);
+		memcpy(&extra, (u8 *)(data + extra_offset), blk_size % stride);
+		ret = regmap_write(sec->m10bmc->regmap,
+				   M10BMC_STAGING_BASE + extra_offset, extra);
+		if (ret)
+			return FW_UPLOAD_ERR_RW_ERROR;
+	}
+
+	*written = blk_size;
+	return FW_UPLOAD_ERR_NONE;
+}
+
+static enum fw_upload_err m10bmc_sec_poll_complete(struct fw_upload *fwl)
+{
+	struct m10bmc_sec *sec = fwl->dd_handle;
+	unsigned long poll_timeout;
+	u32 doorbell, result;
+	int ret;
+
+	if (sec->cancel_request)
+		return rsu_cancel(sec);
+
+	result = rsu_send_data(sec);
+	if (result != FW_UPLOAD_ERR_NONE)
+		return result;
+
+	poll_timeout = jiffies + msecs_to_jiffies(RSU_COMPLETE_TIMEOUT_MS);
+	do {
+		msleep(RSU_COMPLETE_INTERVAL_MS);
+		ret = rsu_check_complete(sec, &doorbell);
+	} while (ret == -EAGAIN && !time_after(jiffies, poll_timeout));
+
+	if (ret == -EAGAIN) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_TIMEOUT;
+	} else if (ret == -EIO) {
+		return FW_UPLOAD_ERR_RW_ERROR;
+	} else if (ret) {
+		log_error_regs(sec, doorbell);
+		return FW_UPLOAD_ERR_HW_ERROR;
+	}
+
+	return FW_UPLOAD_ERR_NONE;
+}
+
+/*
+ * m10bmc_sec_cancel() may be called asynchronously with an on-going update.
+ * All other functions are called sequentially in a single thread. To avoid
+ * contention on register accesses, m10bmc_sec_cancel() must only update
+ * the cancel_request flag. Other functions will check this flag and handle
+ * the cancel request synchronously.
+ */
+static void m10bmc_sec_cancel(struct fw_upload *fwl)
+{
+	struct m10bmc_sec *sec = fwl->dd_handle;
+
+	sec->cancel_request = true;
+}
+
+static void m10bmc_sec_cleanup(struct fw_upload *fwl)
+{
+	struct m10bmc_sec *sec = fwl->dd_handle;
+
+	(void)rsu_cancel(sec);
+}
+
+static const struct fw_upload_ops m10bmc_ops = {
+	.prepare = m10bmc_sec_prepare,
+	.write = m10bmc_sec_write,
+	.poll_complete = m10bmc_sec_poll_complete,
+	.cancel = m10bmc_sec_cancel,
+	.cleanup = m10bmc_sec_cleanup,
+};
+
+#define SEC_UPDATE_LEN_MAX 32
+static int m10bmc_sec_probe(struct platform_device *pdev)
+{
+	char buf[SEC_UPDATE_LEN_MAX];
+	struct m10bmc_sec *sec;
+	struct fw_upload *fwl;
+	unsigned int len;
+	int  ret;
+
+	sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
+	if (!sec)
+		return -ENOMEM;
+
+	sec->dev = &pdev->dev;
+	sec->m10bmc = dev_get_drvdata(pdev->dev.parent);
+	dev_set_drvdata(&pdev->dev, sec);
+
+	ret = xa_alloc(&fw_upload_xa, &sec->fw_name_id, sec,
+		       xa_limit_32b, GFP_KERNEL);
+	if (ret)
+		return ret;
+
+	len = scnprintf(buf, SEC_UPDATE_LEN_MAX, "secure-update%d",
+			sec->fw_name_id);
+	sec->fw_name = kmemdup_nul(buf, len, GFP_KERNEL);
+	if (!sec->fw_name)
+		return -ENOMEM;
+
+	fwl = firmware_upload_register(THIS_MODULE, sec->dev, sec->fw_name,
+				       &m10bmc_ops, sec);
+	if (IS_ERR(fwl)) {
+		dev_err(sec->dev, "Firmware Upload driver failed to start\n");
+		kfree(sec->fw_name);
+		xa_erase(&fw_upload_xa, sec->fw_name_id);
+		return PTR_ERR(fwl);
+	}
+
+	sec->fwl = fwl;
+	return 0;
+}
+
+static int m10bmc_sec_remove(struct platform_device *pdev)
+{
+	struct m10bmc_sec *sec = dev_get_drvdata(&pdev->dev);
+
+	firmware_upload_unregister(sec->fwl);
+	kfree(sec->fw_name);
+	xa_erase(&fw_upload_xa, sec->fw_name_id);
+
+	return 0;
+}
+
+static const struct platform_device_id intel_m10bmc_sec_ids[] = {
+	{
+		.name = "n3000bmc-sec-update",
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids);
+
+static struct platform_driver intel_m10bmc_sec_driver = {
+	.probe = m10bmc_sec_probe,
+	.remove = m10bmc_sec_remove,
+	.driver = {
+		.name = "intel-m10bmc-sec-update",
+		.dev_groups = m10bmc_sec_attr_groups,
+	},
+	.id_table = intel_m10bmc_sec_ids,
+};
+module_platform_driver(intel_m10bmc_sec_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gnss/core.c b/drivers/gnss/core.c
index e6f94501cb28..1e82b7967570 100644
--- a/drivers/gnss/core.c
+++ b/drivers/gnss/core.c
@@ -217,7 +217,7 @@ static void gnss_device_release(struct device *dev)
 
 	kfree(gdev->write_buf);
 	kfifo_free(&gdev->read_fifo);
-	ida_simple_remove(&gnss_minors, gdev->id);
+	ida_free(&gnss_minors, gdev->id);
 	kfree(gdev);
 }
 
@@ -232,7 +232,7 @@ struct gnss_device *gnss_allocate_device(struct device *parent)
 	if (!gdev)
 		return NULL;
 
-	id = ida_simple_get(&gnss_minors, 0, GNSS_MINORS, GFP_KERNEL);
+	id = ida_alloc_max(&gnss_minors, GNSS_MINORS - 1, GFP_KERNEL);
 	if (id < 0) {
 		kfree(gdev);
 		return NULL;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b01961999ced..bf942f8e9a60 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -482,6 +482,14 @@ config GPIO_PL061
 	help
 	  Say yes here to support the PrimeCell PL061 GPIO device.
 
+config GPIO_PL061_RUST
+	tristate "PrimeCell PL061 GPIO support written in Rust"
+	depends on ARM_AMBA && RUST
+	select IRQ_DOMAIN
+	select GPIOLIB_IRQCHIP
+	help
+	  Say yes here to support the PrimeCell PL061 GPIO device
+
 config GPIO_PMIC_EIC_SPRD
 	tristate "Spreadtrum PMIC EIC support"
 	depends on MFD_SC27XX_PMIC || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 14352f6dfe8e..30141fec12be 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -118,6 +118,7 @@ obj-$(CONFIG_GPIO_PCIE_IDIO_24)		+= gpio-pcie-idio-24.o
 obj-$(CONFIG_GPIO_PCI_IDIO_16)		+= gpio-pci-idio-16.o
 obj-$(CONFIG_GPIO_PISOSR)		+= gpio-pisosr.o
 obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
+obj-$(CONFIG_GPIO_PL061_RUST)		+= gpio_pl061_rust.o
 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
 obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c
index e84474494429..70770429ba48 100644
--- a/drivers/gpio/gpio-bcm-kona.c
+++ b/drivers/gpio/gpio-bcm-kona.c
@@ -1,17 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Broadcom Kona GPIO Driver
  *
  * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
  * Copyright (C) 2012-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/bitops.h>
diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
index 6b7439b44690..85429dd6b3b6 100644
--- a/drivers/gpio/gpio-brcmstb.c
+++ b/drivers/gpio/gpio-brcmstb.c
@@ -1,15 +1,5 @@
-/*
- * Copyright (C) 2015-2017 Broadcom
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2015-2017 Broadcom
 
 #include <linux/bitops.h>
 #include <linux/gpio/driver.h>
diff --git a/drivers/gpio/gpio-lp873x.c b/drivers/gpio/gpio-lp873x.c
index 70fad87ff2db..5c79ba1f229c 100644
--- a/drivers/gpio/gpio-lp873x.c
+++ b/drivers/gpio/gpio-lp873x.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  *	Keerthy <j-keerthy@ti.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether expressed or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License version 2 for more details.
- *
  * Based on the TPS65218 driver
  */
 
diff --git a/drivers/gpio/gpio-lp87565.c b/drivers/gpio/gpio-lp87565.c
index fcde6708b5df..d3ce027de081 100644
--- a/drivers/gpio/gpio-lp87565.c
+++ b/drivers/gpio/gpio-lp87565.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
  *	Keerthy <j-keerthy@ti.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether expressed or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License version 2 for more details.
- *
  * Based on the LP873X driver
  */
 
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index a964e25ea620..15049822937a 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
  *
  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
  * Copyright (C) 2016 Freescale Semiconductor Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
  */
 
 #include <linux/acpi.h>
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 2db19cd640a4..aa126ab80f0c 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * GPIO driver for Marvell SoCs
  *
@@ -7,10 +8,6 @@
  * Andrew Lunn <andrew@lunn.ch>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
  * This driver is a fairly straightforward GPIO driver for the
  * complete family of Marvell EBU SoC platforms (Orion, Dove,
  * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index 3a0bd8795741..ee37ecb615cb 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -37,6 +37,11 @@ struct pch_regs {
 	u32	reset;
 };
 
+#define PCI_DEVICE_ID_INTEL_EG20T_PCH		0x8803
+#define PCI_DEVICE_ID_ROHM_ML7223m_IOH		0x8014
+#define PCI_DEVICE_ID_ROHM_ML7223n_IOH		0x8043
+#define PCI_DEVICE_ID_ROHM_EG20T_PCH		0x8803
+
 enum pch_type_t {
 	INTEL_EG20T_PCH,
 	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
@@ -357,16 +362,12 @@ static int pch_gpio_probe(struct pci_dev *pdev,
 
 	chip->dev = dev;
 	ret = pcim_enable_device(pdev);
-	if (ret) {
-		dev_err(dev, "pci_enable_device FAILED");
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
 
 	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
-	if (ret) {
-		dev_err(dev, "pci_request_regions FAILED-%d", ret);
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
 
 	chip->base = pcim_iomap_table(pdev)[1];
 	chip->ioh = id->driver_data;
@@ -376,10 +377,8 @@ static int pch_gpio_probe(struct pci_dev *pdev,
 	pch_gpio_setup(chip);
 
 	ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
-	if (ret) {
-		dev_err(dev, "PCH gpio: Failed to register GPIO\n");
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to register GPIO\n");
 
 	irq_base = devm_irq_alloc_descs(dev, -1, 0,
 					gpio_pins[chip->ioh], NUMA_NO_NODE);
@@ -396,10 +395,8 @@ static int pch_gpio_probe(struct pci_dev *pdev,
 
 	ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
 			       IRQF_SHARED, KBUILD_MODNAME, chip);
-	if (ret) {
-		dev_err(dev, "request_irq failed\n");
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request IRQ\n");
 
 	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
 }
@@ -433,15 +430,11 @@ static int __maybe_unused pch_gpio_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
 
 static const struct pci_device_id pch_gpio_pcidev_id[] = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803),
-	  .driver_data = INTEL_EG20T_PCH },
-	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014),
-	  .driver_data = OKISEMI_ML7223m_IOH },
-	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043),
-	  .driver_data = OKISEMI_ML7223n_IOH },
-	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803),
-	  .driver_data = INTEL_EG20T_PCH },
-	{ 0, }
+	{ PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
+	{ PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
+	{ PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
+	{ PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
+	{ }
 };
 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
 
diff --git a/drivers/gpio/gpio-pisosr.c b/drivers/gpio/gpio-pisosr.c
index 81a47ae09ff8..67071bea08c2 100644
--- a/drivers/gpio/gpio-pisosr.c
+++ b/drivers/gpio/gpio-pisosr.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
  *	Andrew F. Davis <afd@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether expressed or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License version 2 for more details.
  */
 
 #include <linux/bitmap.h>
diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c
index c52b2cb1acae..63dcf42f7c20 100644
--- a/drivers/gpio/gpio-realtek-otto.c
+++ b/drivers/gpio/gpio-realtek-otto.c
@@ -172,6 +172,8 @@ static void realtek_gpio_irq_unmask(struct irq_data *data)
 	unsigned long flags;
 	u16 m;
 
+	gpiochip_enable_irq(&ctrl->gc, line);
+
 	raw_spin_lock_irqsave(&ctrl->lock, flags);
 	m = ctrl->intr_mask[port];
 	m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
@@ -195,6 +197,8 @@ static void realtek_gpio_irq_mask(struct irq_data *data)
 	ctrl->intr_mask[port] = m;
 	realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+	gpiochip_disable_irq(&ctrl->gc, line);
 }
 
 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
@@ -315,13 +319,15 @@ static int realtek_gpio_irq_init(struct gpio_chip *gc)
 	return 0;
 }
 
-static struct irq_chip realtek_gpio_irq_chip = {
+static const struct irq_chip realtek_gpio_irq_chip = {
 	.name = "realtek-otto-gpio",
 	.irq_ack = realtek_gpio_irq_ack,
 	.irq_mask = realtek_gpio_irq_mask,
 	.irq_unmask = realtek_gpio_irq_unmask,
 	.irq_set_type = realtek_gpio_irq_set_type,
 	.irq_set_affinity = realtek_gpio_irq_set_affinity,
+	.flags = IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
 static const struct of_device_id realtek_gpio_of_match[] = {
@@ -404,7 +410,7 @@ static int realtek_gpio_probe(struct platform_device *pdev)
 	irq = platform_get_irq_optional(pdev, 0);
 	if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
 		girq = &ctrl->gc.irq;
-		girq->chip = &realtek_gpio_irq_chip;
+		gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
 		girq->default_type = IRQ_TYPE_NONE;
 		girq->handler = handle_bad_irq;
 		girq->parent_handler = realtek_gpio_irq_handler;
diff --git a/drivers/gpio/gpio-spear-spics.c b/drivers/gpio/gpio-spear-spics.c
index 49aac2bb8d2c..51539185400d 100644
--- a/drivers/gpio/gpio-spear-spics.c
+++ b/drivers/gpio/gpio-spear-spics.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * SPEAr platform SPI chipselect abstraction over gpiolib
  *
  * Copyright (C) 2012 ST Microelectronics
  * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/err.h>
diff --git a/drivers/gpio/gpio-tpic2810.c b/drivers/gpio/gpio-tpic2810.c
index 99d5a84a9129..a09b1e69b072 100644
--- a/drivers/gpio/gpio-tpic2810.c
+++ b/drivers/gpio/gpio-tpic2810.c
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
  *	Andrew F. Davis <afd@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether expressed or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License version 2 for more details.
  */
 
 #include <linux/gpio/driver.h>
diff --git a/drivers/gpio/gpio-ts4800.c b/drivers/gpio/gpio-ts4800.c
index 8c0d82d926dd..95d80ba14bee 100644
--- a/drivers/gpio/gpio-ts4800.c
+++ b/drivers/gpio/gpio-ts4800.c
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * GPIO driver for the TS-4800 board
  *
  * Copyright (c) 2016 - Savoir-faire Linux
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/gpio/driver.h>
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 98cd715ccc33..8d09b619c166 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -217,8 +217,6 @@ static int giu_get_irq(unsigned int irq)
 	printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
 	       maskl, pendl, maskh, pendh);
 
-	atomic_inc(&irq_err_count);
-
 	return -EINVAL;
 }
 
diff --git a/drivers/gpio/gpio_pl061_rust.rs b/drivers/gpio/gpio_pl061_rust.rs
new file mode 100644
index 000000000000..908914080442
--- /dev/null
+++ b/drivers/gpio/gpio_pl061_rust.rs
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061).
+//!
+//! Based on the C driver written by Baruch Siach <baruch@tkos.co.il>.
+
+use kernel::{
+    amba, bit, bits_iter, define_amba_id_table, device, gpio,
+    io_mem::IoMem,
+    irq::{self, ExtraResult, IrqData, LockedIrqData},
+    power,
+    prelude::*,
+    sync::{RawSpinLock, Ref, RefBorrow},
+};
+
+const GPIODIR: usize = 0x400;
+const GPIOIS: usize = 0x404;
+const GPIOIBE: usize = 0x408;
+const GPIOIEV: usize = 0x40C;
+const GPIOIE: usize = 0x410;
+const GPIOMIS: usize = 0x418;
+const GPIOIC: usize = 0x41C;
+const GPIO_SIZE: usize = 0x1000;
+
+const PL061_GPIO_NR: u16 = 8;
+
+#[derive(Default)]
+struct ContextSaveRegs {
+    gpio_data: u8,
+    gpio_dir: u8,
+    gpio_is: u8,
+    gpio_ibe: u8,
+    gpio_iev: u8,
+    gpio_ie: u8,
+}
+
+#[derive(Default)]
+struct PL061DataInner {
+    csave_regs: ContextSaveRegs,
+}
+
+struct PL061Data {
+    dev: device::Device,
+    inner: RawSpinLock<PL061DataInner>,
+}
+
+struct PL061Resources {
+    base: IoMem<GPIO_SIZE>,
+    parent_irq: u32,
+}
+
+type PL061Registrations = gpio::RegistrationWithIrqChip<PL061Device>;
+
+type DeviceData = device::Data<PL061Registrations, PL061Resources, PL061Data>;
+
+struct PL061Device;
+
+impl gpio::Chip for PL061Device {
+    type Data = Ref<DeviceData>;
+
+    kernel::declare_gpio_chip_operations!(
+        get_direction,
+        direction_input,
+        direction_output,
+        get,
+        set
+    );
+
+    fn get_direction(data: RefBorrow<'_, DeviceData>, offset: u32) -> Result<gpio::LineDirection> {
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        Ok(if pl061.base.readb(GPIODIR) & bit(offset) != 0 {
+            gpio::LineDirection::Out
+        } else {
+            gpio::LineDirection::In
+        })
+    }
+
+    fn direction_input(data: RefBorrow<'_, DeviceData>, offset: u32) -> Result {
+        let _guard = data.inner.lock_irqdisable();
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        let mut gpiodir = pl061.base.readb(GPIODIR);
+        gpiodir &= !bit(offset);
+        pl061.base.writeb(gpiodir, GPIODIR);
+        Ok(())
+    }
+
+    fn direction_output(data: RefBorrow<'_, DeviceData>, offset: u32, value: bool) -> Result {
+        let woffset = bit(offset + 2).into();
+        let _guard = data.inner.lock_irqdisable();
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        pl061.base.try_writeb((value as u8) << offset, woffset)?;
+        let mut gpiodir = pl061.base.readb(GPIODIR);
+        gpiodir |= bit(offset);
+        pl061.base.writeb(gpiodir, GPIODIR);
+
+        // gpio value is set again, because pl061 doesn't allow to set value of a gpio pin before
+        // configuring it in OUT mode.
+        pl061.base.try_writeb((value as u8) << offset, woffset)?;
+        Ok(())
+    }
+
+    fn get(data: RefBorrow<'_, DeviceData>, offset: u32) -> Result<bool> {
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        Ok(pl061.base.try_readb(bit(offset + 2).into())? != 0)
+    }
+
+    fn set(data: RefBorrow<'_, DeviceData>, offset: u32, value: bool) {
+        if let Some(pl061) = data.resources() {
+            let woffset = bit(offset + 2).into();
+            let _ = pl061.base.try_writeb((value as u8) << offset, woffset);
+        }
+    }
+}
+
+impl gpio::ChipWithIrqChip for PL061Device {
+    fn handle_irq_flow(
+        data: RefBorrow<'_, DeviceData>,
+        desc: &irq::Descriptor,
+        domain: &irq::Domain,
+    ) {
+        let chained = desc.enter_chained();
+
+        if let Some(pl061) = data.resources() {
+            let pending = pl061.base.readb(GPIOMIS);
+            for offset in bits_iter(pending) {
+                domain.generic_handle_chained(offset, &chained);
+            }
+        }
+    }
+}
+
+impl irq::Chip for PL061Device {
+    type Data = Ref<DeviceData>;
+
+    kernel::declare_irq_chip_operations!(set_type, set_wake);
+
+    fn set_type(
+        data: RefBorrow<'_, DeviceData>,
+        irq_data: &mut LockedIrqData,
+        trigger: u32,
+    ) -> Result<ExtraResult> {
+        let offset = irq_data.hwirq();
+        let bit = bit(offset);
+
+        if offset >= PL061_GPIO_NR.into() {
+            return Err(EINVAL);
+        }
+
+        if trigger & (irq::Type::LEVEL_HIGH | irq::Type::LEVEL_LOW) != 0
+            && trigger & (irq::Type::EDGE_RISING | irq::Type::EDGE_FALLING) != 0
+        {
+            dev_err!(
+                data.dev,
+                "trying to configure line {} for both level and edge detection, choose one!\n",
+                offset
+            );
+            return Err(EINVAL);
+        }
+
+        let _guard = data.inner.lock_irqdisable();
+        let pl061 = data.resources().ok_or(ENXIO)?;
+
+        let mut gpioiev = pl061.base.readb(GPIOIEV);
+        let mut gpiois = pl061.base.readb(GPIOIS);
+        let mut gpioibe = pl061.base.readb(GPIOIBE);
+
+        if trigger & (irq::Type::LEVEL_HIGH | irq::Type::LEVEL_LOW) != 0 {
+            let polarity = trigger & irq::Type::LEVEL_HIGH != 0;
+
+            // Disable edge detection.
+            gpioibe &= !bit;
+            // Enable level detection.
+            gpiois |= bit;
+            // Select polarity.
+            if polarity {
+                gpioiev |= bit;
+            } else {
+                gpioiev &= !bit;
+            }
+            irq_data.set_level_handler();
+            dev_dbg!(
+                data.dev,
+                "line {}: IRQ on {} level\n",
+                offset,
+                if polarity { "HIGH" } else { "LOW" }
+            );
+        } else if (trigger & irq::Type::EDGE_BOTH) == irq::Type::EDGE_BOTH {
+            // Disable level detection.
+            gpiois &= !bit;
+            // Select both edges, settings this makes GPIOEV be ignored.
+            gpioibe |= bit;
+            irq_data.set_edge_handler();
+            dev_dbg!(data.dev, "line {}: IRQ on both edges\n", offset);
+        } else if trigger & (irq::Type::EDGE_RISING | irq::Type::EDGE_FALLING) != 0 {
+            let rising = trigger & irq::Type::EDGE_RISING != 0;
+
+            // Disable level detection.
+            gpiois &= !bit;
+            // Clear detection on both edges.
+            gpioibe &= !bit;
+            // Select edge.
+            if rising {
+                gpioiev |= bit;
+            } else {
+                gpioiev &= !bit;
+            }
+            irq_data.set_edge_handler();
+            dev_dbg!(
+                data.dev,
+                "line {}: IRQ on {} edge\n",
+                offset,
+                if rising { "RISING" } else { "FALLING}" }
+            );
+        } else {
+            // No trigger: disable everything.
+            gpiois &= !bit;
+            gpioibe &= !bit;
+            gpioiev &= !bit;
+            irq_data.set_bad_handler();
+            dev_warn!(data.dev, "no trigger selected for line {}\n", offset);
+        }
+
+        pl061.base.writeb(gpiois, GPIOIS);
+        pl061.base.writeb(gpioibe, GPIOIBE);
+        pl061.base.writeb(gpioiev, GPIOIEV);
+
+        Ok(ExtraResult::None)
+    }
+
+    fn mask(data: RefBorrow<'_, DeviceData>, irq_data: &IrqData) {
+        let mask = bit(irq_data.hwirq() % irq::HwNumber::from(PL061_GPIO_NR));
+        let _guard = data.inner.lock();
+        if let Some(pl061) = data.resources() {
+            let gpioie = pl061.base.readb(GPIOIE) & !mask;
+            pl061.base.writeb(gpioie, GPIOIE);
+        }
+    }
+
+    fn unmask(data: RefBorrow<'_, DeviceData>, irq_data: &IrqData) {
+        let mask = bit(irq_data.hwirq() % irq::HwNumber::from(PL061_GPIO_NR));
+        let _guard = data.inner.lock();
+        if let Some(pl061) = data.resources() {
+            let gpioie = pl061.base.readb(GPIOIE) | mask;
+            pl061.base.writeb(gpioie, GPIOIE);
+        }
+    }
+
+    // This gets called from the edge IRQ handler to ACK the edge IRQ in the GPIOIC
+    // (interrupt-clear) register. For level IRQs this is not needed: these go away when the level
+    // signal goes away.
+    fn ack(data: RefBorrow<'_, DeviceData>, irq_data: &IrqData) {
+        let mask = bit(irq_data.hwirq() % irq::HwNumber::from(PL061_GPIO_NR));
+        let _guard = data.inner.lock();
+        if let Some(pl061) = data.resources() {
+            pl061.base.writeb(mask.into(), GPIOIC);
+        }
+    }
+
+    fn set_wake(data: RefBorrow<'_, DeviceData>, _irq_data: &IrqData, on: bool) -> Result {
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        irq::set_wake(pl061.parent_irq, on)
+    }
+}
+
+impl amba::Driver for PL061Device {
+    type Data = Ref<DeviceData>;
+    type PowerOps = Self;
+
+    define_amba_id_table! {(), [
+        ({id: 0x00041061, mask: 0x000fffff}, None),
+    ]}
+
+    fn probe(dev: &mut amba::Device, _data: Option<&Self::IdInfo>) -> Result<Ref<DeviceData>> {
+        let res = dev.take_resource().ok_or(ENXIO)?;
+        let irq = dev.irq(0).ok_or(ENXIO)?;
+
+        let mut data = kernel::new_device_data!(
+            gpio::RegistrationWithIrqChip::new(),
+            PL061Resources {
+                // SAFETY: This device doesn't support DMA.
+                base: unsafe { IoMem::try_new(res)? },
+                parent_irq: irq,
+            },
+            PL061Data {
+                dev: device::Device::from_dev(dev),
+                // SAFETY: We call `rawspinlock_init` below.
+                inner: unsafe { RawSpinLock::new(PL061DataInner::default()) },
+            },
+            "PL061::Registrations"
+        )?;
+
+        // SAFETY: General part of the data is pinned when `data` is.
+        let gen_inner = unsafe { data.as_mut().map_unchecked_mut(|d| &mut (**d).inner) };
+        kernel::rawspinlock_init!(gen_inner, "PL061Data::inner");
+
+        let data = Ref::<DeviceData>::from(data);
+
+        data.resources().ok_or(ENXIO)?.base.writeb(0, GPIOIE); // disable irqs
+
+        data.registrations()
+            .ok_or(ENXIO)?
+            .as_pinned_mut()
+            .register::<Self>(PL061_GPIO_NR, None, dev, data.clone(), irq)?;
+
+        dev_info!(data.dev, "PL061 GPIO chip registered\n");
+
+        Ok(data)
+    }
+}
+
+impl power::Operations for PL061Device {
+    type Data = Ref<DeviceData>;
+
+    fn suspend(data: RefBorrow<'_, DeviceData>) -> Result {
+        let mut inner = data.inner.lock();
+        let pl061 = data.resources().ok_or(ENXIO)?;
+        inner.csave_regs.gpio_data = 0;
+        inner.csave_regs.gpio_dir = pl061.base.readb(GPIODIR);
+        inner.csave_regs.gpio_is = pl061.base.readb(GPIOIS);
+        inner.csave_regs.gpio_ibe = pl061.base.readb(GPIOIBE);
+        inner.csave_regs.gpio_iev = pl061.base.readb(GPIOIEV);
+        inner.csave_regs.gpio_ie = pl061.base.readb(GPIOIE);
+
+        for offset in 0..PL061_GPIO_NR {
+            if inner.csave_regs.gpio_dir & bit(offset) != 0 {
+                if let Ok(v) = <Self as gpio::Chip>::get(data, offset.into()) {
+                    inner.csave_regs.gpio_data |= (v as u8) << offset;
+                }
+            }
+        }
+
+        Ok(())
+    }
+
+    fn resume(data: RefBorrow<'_, DeviceData>) -> Result {
+        let inner = data.inner.lock();
+        let pl061 = data.resources().ok_or(ENXIO)?;
+
+        for offset in 0..PL061_GPIO_NR {
+            if inner.csave_regs.gpio_dir & bit(offset) != 0 {
+                let value = inner.csave_regs.gpio_data & bit(offset) != 0;
+                let _ = <Self as gpio::Chip>::direction_output(data, offset.into(), value);
+            } else {
+                let _ = <Self as gpio::Chip>::direction_input(data, offset.into());
+            }
+        }
+
+        pl061.base.writeb(inner.csave_regs.gpio_is, GPIOIS);
+        pl061.base.writeb(inner.csave_regs.gpio_ibe, GPIOIBE);
+        pl061.base.writeb(inner.csave_regs.gpio_iev, GPIOIEV);
+        pl061.base.writeb(inner.csave_regs.gpio_ie, GPIOIE);
+
+        Ok(())
+    }
+
+    fn freeze(data: RefBorrow<'_, DeviceData>) -> Result {
+        Self::suspend(data)
+    }
+
+    fn restore(data: RefBorrow<'_, DeviceData>) -> Result {
+        Self::resume(data)
+    }
+}
+
+module_amba_driver! {
+    type: PL061Device,
+    name: b"pl061_gpio",
+    author: b"Wedson Almeida Filho",
+    license: b"GPL",
+}
diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c
index f5aa5f93342a..d0dc68d04059 100644
--- a/drivers/gpio/gpiolib-cdev.c
+++ b/drivers/gpio/gpiolib-cdev.c
@@ -421,6 +421,10 @@ static int linehandle_create(struct gpio_device *gdev, void __user *ip)
  * @work: the worker that implements software debouncing
  * @sw_debounced: flag indicating if the software debouncer is active
  * @level: the current debounced physical level of the line
+ * @hdesc: the Hardware Timestamp Engine (HTE) descriptor
+ * @raw_level: the line level at the time of event
+ * @total_discard_seq: the running counter of the discarded events
+ * @last_seqno: the last sequence number before debounce period expires
  */
 struct line {
 	struct gpio_desc *desc;
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index e88c497fa010..22e7fa48d693 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -351,6 +351,8 @@ source "drivers/gpu/drm/etnaviv/Kconfig"
 
 source "drivers/gpu/drm/hisilicon/Kconfig"
 
+source "drivers/gpu/drm/logicvc/Kconfig"
+
 source "drivers/gpu/drm/mediatek/Kconfig"
 
 source "drivers/gpu/drm/mxsfb/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 15fe3163f822..13ef240b3d2b 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -121,6 +121,7 @@ obj-$(CONFIG_DRM_STM) += stm/
 obj-$(CONFIG_DRM_STI) += sti/
 obj-y 			+= imx/
 obj-$(CONFIG_DRM_INGENIC) += ingenic/
+obj-$(CONFIG_DRM_LOGICVC) += logicvc/
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-$(CONFIG_DRM_MESON)	+= meson/
 obj-y			+= i2c/
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3e0e2eb7e235..a87e42c2c8dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -88,7 +88,8 @@ amdgpu-y += \
 	gmc_v8_0.o \
 	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \
-	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o
+	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \
+	mmhub_v3_0_1.o
 
 # add UMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 30ce6bb6fa77..fb9399a999ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -223,6 +223,9 @@ static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
 static const bool __maybe_unused debug_evictions; /* = false */
 static const bool __maybe_unused no_system_mem_limit;
 #endif
+#ifdef CONFIG_HSA_AMD_P2P
+extern bool pcie_p2p;
+#endif
 
 extern int amdgpu_tmz;
 extern int amdgpu_reset_method;
@@ -274,7 +277,7 @@ extern int amdgpu_vcnfw_log;
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 
-/* smasrt shift bias level limits */
+/* smart shift bias level limits */
 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
 
@@ -667,6 +670,7 @@ enum amd_hw_ip_block_type {
 	RSMU_HWIP,
 	XGMI_HWIP,
 	DCI_HWIP,
+	PCIE_HWIP,
 	MAX_HWIP
 };
 
@@ -1044,10 +1048,18 @@ struct amdgpu_device {
 
 	/* reset dump register */
 	uint32_t                        *reset_dump_reg_list;
+	uint32_t			*reset_dump_reg_value;
 	int                             num_regs;
+#ifdef CONFIG_DEV_COREDUMP
+	struct amdgpu_task_info         reset_task_info;
+	bool                            reset_vram_lost;
+	struct timespec64               reset_time;
+#endif
 
 	bool                            scpm_enabled;
 	uint32_t                        scpm_status;
+
+	struct work_struct		reset_work;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1242,7 +1254,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job* job);
-int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job *job);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 98ac53ee6bb5..130060834b4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -66,9 +66,7 @@ struct amdgpu_atif {
 	struct amdgpu_atif_notifications notifications;
 	struct amdgpu_atif_functions functions;
 	struct amdgpu_atif_notification_cfg notification_cfg;
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	struct backlight_device *bd;
-#endif
 	struct amdgpu_dm_backlight_caps backlight_caps;
 };
 
@@ -436,7 +434,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 		DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count);
 
 		if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) {
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 			if (atif->bd) {
 				DRM_DEBUG_DRIVER("Changing brightness to %d\n",
 						 req.backlight_level);
@@ -447,7 +444,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
 				 */
 				backlight_device_set_brightness(atif->bd, req.backlight_level);
 			}
-#endif
 		}
 
 		if (req.pending & ATIF_DGPU_DISPLAY_EVENT) {
@@ -849,7 +845,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 {
 	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	if (atif->notifications.brightness_change) {
 		if (amdgpu_device_has_dc_support(adev)) {
 #if defined(CONFIG_DRM_AMD_DC)
@@ -876,7 +871,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
 			}
 		}
 	}
-#endif
 	adev->acpi_nb.notifier_call = amdgpu_acpi_event;
 	register_acpi_notifier(&adev->acpi_nb);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1f8161cd507f..513c57f839d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -33,6 +33,7 @@
 #include <uapi/linux/kfd_ioctl.h>
 #include "amdgpu_ras.h"
 #include "amdgpu_umc.h"
+#include "amdgpu_reset.h"
 
 /* Total memory size in system memory and all GPU VRAM. Used to
  * estimate worst case amount of memory to reserve for page tables
@@ -122,6 +123,15 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 	}
 }
 
+
+static void amdgpu_amdkfd_reset_work(struct work_struct *work)
+{
+	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+						  kfd.reset_work);
+
+	amdgpu_device_gpu_recover(adev, NULL);
+}
+
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 {
 	int i;
@@ -180,6 +190,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 
 		adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
 						adev_to_drm(adev), &gpu_resources);
+
+		INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
 	}
 }
 
@@ -247,7 +259,8 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
 {
 	if (amdgpu_device_should_recover_gpu(adev))
-		amdgpu_device_gpu_recover(adev, NULL);
+		amdgpu_reset_domain_schedule(adev->reset_domain,
+					     &adev->kfd.reset_work);
 }
 
 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index f8b9f27adcf5..648c031942e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -48,6 +48,7 @@ enum kfd_mem_attachment_type {
 	KFD_MEM_ATT_SHARED,	/* Share kgd_mem->bo or another attachment's */
 	KFD_MEM_ATT_USERPTR,	/* SG bo to DMA map pages from a userptr bo */
 	KFD_MEM_ATT_DMABUF,	/* DMAbuf to DMA map TTM BOs */
+	KFD_MEM_ATT_SG		/* Tag to DMA map SG BOs */
 };
 
 struct kfd_mem_attachment {
@@ -96,6 +97,7 @@ struct amdgpu_kfd_dev {
 	struct kfd_dev *dev;
 	uint64_t vram_used;
 	bool init_complete;
+	struct work_struct reset_work;
 };
 
 enum kgd_engine_type {
@@ -266,6 +268,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
 					void *drm_priv);
 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
 		void *drm_priv, struct kgd_mem **mem,
@@ -279,10 +282,9 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
 int amdgpu_amdkfd_gpuvm_sync_memory(
 		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
-int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem, void **kptr, uint64_t *size);
-void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem);
+int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
+					     void **kptr, uint64_t *size);
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
 
 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
 					    struct dma_fence **ef);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6b6d46e29e6e..8805bd1eed37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -38,6 +38,12 @@
  */
 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
 
+/*
+ * Align VRAM allocations to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
+ * BO chunk
+ */
+#define VRAM_ALLOCATION_ALIGN (1 << 21)
+
 /* Impose limit on how much memory KFD can use */
 static struct {
 	uint64_t max_system_mem_limit;
@@ -108,7 +114,7 @@ void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
  * compromise that should work in most cases without reserving too
  * much memory for page tables unnecessarily (factor 16K, >> 14).
  */
-#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
+#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
 
 static size_t amdgpu_amdkfd_acc_size(uint64_t size)
 {
@@ -148,7 +154,13 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 		system_mem_needed = acc_size;
 		ttm_mem_needed = acc_size;
-		vram_needed = size;
+
+		/*
+		 * Conservatively round up the allocation requirement to 2 MB
+		 * to avoid fragmentation caused by 4K allocations in the tail
+		 * 2M BO chunk.
+		 */
+		vram_needed = ALIGN(size, VRAM_ALLOCATION_ALIGN);
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 		system_mem_needed = acc_size + size;
 		ttm_mem_needed = acc_size;
@@ -173,7 +185,9 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
 	     kfd_mem_limit.max_ttm_mem_limit) ||
 	    (adev->kfd.vram_used + vram_needed >
-	     adev->gmc.real_vram_size - reserved_for_pt)) {
+	     adev->gmc.real_vram_size -
+	     atomic64_read(&adev->vram_pin_size) -
+	     reserved_for_pt)) {
 		ret = -ENOMEM;
 		goto release;
 	}
@@ -205,7 +219,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 		kfd_mem_limit.system_mem_used -= acc_size;
 		kfd_mem_limit.ttm_mem_used -= acc_size;
-		adev->kfd.vram_used -= size;
+		adev->kfd.vram_used -= ALIGN(size, VRAM_ALLOCATION_ALIGN);
 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 		kfd_mem_limit.system_mem_used -= (acc_size + size);
 		kfd_mem_limit.ttm_mem_used -= acc_size;
@@ -241,6 +255,42 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
 	kfree(bo->kfd_bo);
 }
 
+/**
+ * @create_dmamap_sg_bo: Creates a amdgpu_bo object to reflect information
+ * about USERPTR or DOOREBELL or MMIO BO.
+ * @adev: Device for which dmamap BO is being created
+ * @mem: BO of peer device that is being DMA mapped. Provides parameters
+ *	 in building the dmamap BO
+ * @bo_out: Output parameter updated with handle of dmamap BO
+ */
+static int
+create_dmamap_sg_bo(struct amdgpu_device *adev,
+		 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
+{
+	struct drm_gem_object *gem_obj;
+	int ret, align;
+
+	ret = amdgpu_bo_reserve(mem->bo, false);
+	if (ret)
+		return ret;
+
+	align = 1;
+	ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, align,
+			AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE,
+			ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj);
+
+	amdgpu_bo_unreserve(mem->bo);
+
+	if (ret) {
+		pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
+		return -EINVAL;
+	}
+
+	*bo_out = gem_to_amdgpu_bo(gem_obj);
+	(*bo_out)->parent = amdgpu_bo_ref(mem->bo);
+	return ret;
+}
+
 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
  *  reservation object.
  *
@@ -446,6 +496,38 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 	return pte_flags;
 }
 
+/**
+ * create_sg_table() - Create an sg_table for a contiguous DMA addr range
+ * @addr: The starting address to point to
+ * @size: Size of memory area in bytes being pointed to
+ *
+ * Allocates an instance of sg_table and initializes it to point to memory
+ * area specified by input parameters. The address used to build is assumed
+ * to be DMA mapped, if needed.
+ *
+ * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
+ * because they are physically contiguous.
+ *
+ * Return: Initialized instance of SG Table or NULL
+ */
+static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
+{
+	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
+
+	if (!sg)
+		return NULL;
+	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
+		kfree(sg);
+		return NULL;
+	}
+	sg_dma_address(sg->sgl) = addr;
+	sg->sgl->length = size;
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+	sg->sgl->dma_length = size;
+#endif
+	return sg;
+}
+
 static int
 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
 		       struct kfd_mem_attachment *attachment)
@@ -510,6 +592,87 @@ kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
 	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
 
+/**
+ * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
+ * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
+ * @attachment: Virtual address attachment of the BO on accessing device
+ *
+ * An access request from the device that owns DOORBELL does not require DMA mapping.
+ * This is because the request doesn't go through PCIe root complex i.e. it instead
+ * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
+ *
+ * In contrast, all access requests for MMIO need to be DMA mapped without regard to
+ * device ownership. This is because access requests for MMIO go through PCIe root
+ * complex.
+ *
+ * This is accomplished in two steps:
+ *   - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
+ *         in updating requesting device's page table
+ *   - Signal TTM to mark memory pointed to by requesting device's BO as GPU
+ *         accessible. This allows an update of requesting device's page table
+ *         with entries associated with DOOREBELL or MMIO memory
+ *
+ * This method is invoked in the following contexts:
+ *   - Mapping of DOORBELL or MMIO BO of same or peer device
+ *   - Validating an evicted DOOREBELL or MMIO BO on device seeking access
+ *
+ * Return: ZERO if successful, NON-ZERO otherwise
+ */
+static int
+kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
+		     struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+	enum dma_data_direction dir;
+	dma_addr_t dma_addr;
+	bool mmio;
+	int ret;
+
+	/* Expect SG Table of dmapmap BO to be NULL */
+	mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
+	if (unlikely(ttm->sg)) {
+		pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
+		return -EINVAL;
+	}
+
+	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+			DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	dma_addr = mem->bo->tbo.sg->sgl->dma_address;
+	pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
+	pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
+	dma_addr = dma_map_resource(adev->dev, dma_addr,
+			mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
+	ret = dma_mapping_error(adev->dev, dma_addr);
+	if (unlikely(ret))
+		return ret;
+	pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
+
+	ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
+	if (unlikely(!ttm->sg)) {
+		ret = -ENOMEM;
+		goto unmap_sg;
+	}
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
+	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+	if (unlikely(ret))
+		goto free_sg;
+
+	return ret;
+
+free_sg:
+	sg_free_table(ttm->sg);
+	kfree(ttm->sg);
+	ttm->sg = NULL;
+unmap_sg:
+	dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
+			   dir, DMA_ATTR_SKIP_CPU_SYNC);
+	return ret;
+}
+
 static int
 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 			  struct kfd_mem_attachment *attachment)
@@ -521,6 +684,8 @@ kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 		return kfd_mem_dmamap_userptr(mem, attachment);
 	case KFD_MEM_ATT_DMABUF:
 		return kfd_mem_dmamap_dmabuf(attachment);
+	case KFD_MEM_ATT_SG:
+		return kfd_mem_dmamap_sg_bo(mem, attachment);
 	default:
 		WARN_ON_ONCE(1);
 	}
@@ -561,6 +726,50 @@ kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 }
 
+/**
+ * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
+ * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
+ * @attachment: Virtual address attachment of the BO on accessing device
+ *
+ * The method performs following steps:
+ *   - Signal TTM to mark memory pointed to by BO as GPU inaccessible
+ *   - Free SG Table that is used to encapsulate DMA mapped memory of
+ *          peer device's DOORBELL or MMIO memory
+ *
+ * This method is invoked in the following contexts:
+ *     UNMapping of DOORBELL or MMIO BO on a device having access to its memory
+ *     Eviction of DOOREBELL or MMIO BO on device having access to its memory
+ *
+ * Return: void
+ */
+static void
+kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
+		       struct kfd_mem_attachment *attachment)
+{
+	struct ttm_operation_ctx ctx = {.interruptible = true};
+	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
+	struct amdgpu_device *adev = attachment->adev;
+	struct ttm_tt *ttm = bo->tbo.ttm;
+	enum dma_data_direction dir;
+
+	if (unlikely(!ttm->sg)) {
+		pr_err("SG Table of BO is UNEXPECTEDLY NULL");
+		return;
+	}
+
+	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+
+	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+				DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
+	dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
+			ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
+	sg_free_table(ttm->sg);
+	kfree(ttm->sg);
+	ttm->sg = NULL;
+	bo->tbo.sg = NULL;
+}
+
 static void
 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 			    struct kfd_mem_attachment *attachment)
@@ -574,38 +783,14 @@ kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 	case KFD_MEM_ATT_DMABUF:
 		kfd_mem_dmaunmap_dmabuf(attachment);
 		break;
+	case KFD_MEM_ATT_SG:
+		kfd_mem_dmaunmap_sg_bo(mem, attachment);
+		break;
 	default:
 		WARN_ON_ONCE(1);
 	}
 }
 
-static int
-kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
-		       struct amdgpu_bo **bo)
-{
-	unsigned long bo_size = mem->bo->tbo.base.size;
-	struct drm_gem_object *gobj;
-	int ret;
-
-	ret = amdgpu_bo_reserve(mem->bo, false);
-	if (ret)
-		return ret;
-
-	ret = amdgpu_gem_object_create(adev, bo_size, 1,
-				       AMDGPU_GEM_DOMAIN_CPU,
-				       AMDGPU_GEM_CREATE_PREEMPTIBLE,
-				       ttm_bo_type_sg, mem->bo->tbo.base.resv,
-				       &gobj);
-	amdgpu_bo_unreserve(mem->bo);
-	if (ret)
-		return ret;
-
-	*bo = gem_to_amdgpu_bo(gobj);
-	(*bo)->parent = amdgpu_bo_ref(mem->bo);
-
-	return 0;
-}
-
 static int
 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
 		      struct amdgpu_bo **bo)
@@ -656,6 +841,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 	uint64_t va = mem->va;
 	struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
 	struct amdgpu_bo *bo[2] = {NULL, NULL};
+	bool same_hive = false;
 	int i, ret;
 
 	if (!va) {
@@ -663,6 +849,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		return -EINVAL;
 	}
 
+	/* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
+	 *
+	 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
+	 * In contrast the access path of VRAM BOs depens upon the type of
+	 * link that connects the peer device. Access over PCIe is allowed
+	 * if peer device has large BAR. In contrast, access over xGMI is
+	 * allowed for both small and large BAR configurations of peer device
+	 */
+	if ((adev != bo_adev) &&
+	    ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
+	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
+	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
+		if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
+			same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
+		if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
+			return -EINVAL;
+	}
+
 	for (i = 0; i <= is_aql; i++) {
 		attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
 		if (unlikely(!attachment[i])) {
@@ -673,9 +877,9 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
 			 va + bo_size, vm);
 
-		if (adev == bo_adev ||
-		   (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) ||
-		   (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && amdgpu_xgmi_same_hive(adev, bo_adev))) {
+		if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
+		    (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) ||
+		    same_hive) {
 			/* Mappings on the local GPU, or VRAM mappings in the
 			 * local hive, or userptr mapping IOMMU direct map mode
 			 * share the original BO
@@ -691,26 +895,30 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 		} else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
 			/* Create an SG BO to DMA-map userptrs on other GPUs */
 			attachment[i]->type = KFD_MEM_ATT_USERPTR;
-			ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
+			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
 			if (ret)
 				goto unwind;
-		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
-			   mem->bo->tbo.type != ttm_bo_type_sg) {
-			/* GTT BOs use DMA-mapping ability of dynamic-attach
-			 * DMA bufs. TODO: The same should work for VRAM on
-			 * large-BAR GPUs.
-			 */
+		/* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
+		} else if (mem->bo->tbo.type == ttm_bo_type_sg) {
+			WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
+				    mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
+				  "Handing invalid SG BO in ATTACH request");
+			attachment[i]->type = KFD_MEM_ATT_SG;
+			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
+			if (ret)
+				goto unwind;
+		/* Enable acces to GTT and VRAM BOs of peer devices */
+		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
+			   mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
 			attachment[i]->type = KFD_MEM_ATT_DMABUF;
 			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
 			if (ret)
 				goto unwind;
+			pr_debug("Employ DMABUF mechanim to enable peer GPU access\n");
 		} else {
-			/* FIXME: Need to DMA-map other BO types:
-			 * large-BAR VRAM, doorbells, MMIO remap
-			 */
-			attachment[i]->type = KFD_MEM_ATT_SHARED;
-			bo[i] = mem->bo;
-			drm_gem_object_get(&bo[i]->tbo.base);
+			WARN_ONCE(true, "Handling invalid ATTACH request");
+			ret = -EINVAL;
+			goto unwind;
 		}
 
 		/* Add BO to VM internal data structures */
@@ -1111,24 +1319,6 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
 	return ret;
 }
 
-static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
-{
-	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
-
-	if (!sg)
-		return NULL;
-	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
-		kfree(sg);
-		return NULL;
-	}
-	sg->sgl->dma_address = addr;
-	sg->sgl->length = size;
-#ifdef CONFIG_NEED_SG_DMA_LENGTH
-	sg->sgl->dma_length = size;
-#endif
-	return sg;
-}
-
 static int process_validate_vms(struct amdkfd_process_info *process_info)
 {
 	struct amdgpu_vm *peer_vm;
@@ -1457,6 +1647,22 @@ int amdgpu_amdkfd_criu_resume(void *p)
 	return ret;
 }
 
+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev)
+{
+	uint64_t reserved_for_pt =
+		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
+	size_t available;
+
+	spin_lock(&kfd_mem_limit.mem_limit_lock);
+	available = adev->gmc.real_vram_size
+		- adev->kfd.vram_used
+		- atomic64_read(&adev->vram_pin_size)
+		- reserved_for_pt;
+	spin_unlock(&kfd_mem_limit.mem_limit_lock);
+
+	return ALIGN_DOWN(available, VRAM_ALLOCATION_ALIGN);
+}
+
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
 		void *drm_priv, struct kgd_mem **mem,
@@ -1497,7 +1703,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 			bo_type = ttm_bo_type_sg;
 			if (size > UINT_MAX)
 				return -EINVAL;
-			sg = create_doorbell_sg(*offset, size);
+			sg = create_sg_table(*offset, size);
 			if (!sg)
 				return -ENOMEM;
 		} else {
@@ -1907,8 +2113,21 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
 	return ret;
 }
 
-int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
-		struct kgd_mem *mem, void **kptr, uint64_t *size)
+/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
+ *
+ * @mem: Buffer object to be mapped for CPU access
+ * @kptr[out]: pointer in kernel CPU address space
+ * @size[out]: size of the buffer
+ *
+ * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
+ * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
+ * validate_list, so the GPU mapping can be restored after a page table was
+ * evicted.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
+					     void **kptr, uint64_t *size)
 {
 	int ret;
 	struct amdgpu_bo *bo = mem->bo;
@@ -1959,8 +2178,15 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct amdgpu_device *adev,
 	return ret;
 }
 
-void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct amdgpu_device *adev,
-						  struct kgd_mem *mem)
+/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
+ *
+ * @mem: Buffer object to be unmapped for CPU access
+ *
+ * Removes the kernel CPU mapping and unpins the BO. It does not restore the
+ * eviction fence, so this function should only be used for cleanup before the
+ * BO is destroyed.
+ */
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
 {
 	struct amdgpu_bo *bo = mem->bo;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 7dc92ef36b2b..2ef5296216d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -110,7 +110,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
 	return -EACCES;
 }
 
-static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio)
+static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio)
 {
 	switch (prio) {
 	case AMDGPU_CTX_PRIORITY_HIGH:
@@ -143,8 +143,9 @@ static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip)
 			ctx->init_priority : ctx->override_priority;
 
 	switch (hw_ip) {
+	case AMDGPU_HW_IP_GFX:
 	case AMDGPU_HW_IP_COMPUTE:
-		hw_prio = amdgpu_ctx_prio_to_compute_prio(ctx_prio);
+		hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio);
 		break;
 	case AMDGPU_HW_IP_VCE:
 	case AMDGPU_HW_IP_VCN_ENC:
@@ -779,7 +780,7 @@ static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
 				      amdgpu_ctx_to_drm_sched_prio(priority));
 
 	/* set hw priority */
-	if (hw_ip == AMDGPU_HW_IP_COMPUTE) {
+	if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) {
 		hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip);
 		hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX);
 		scheds = adev->gpu_sched[hw_ip][hw_prio].sched;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index eedb12f6b8a3..f3ac7912c29c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1709,17 +1709,24 @@ static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
 		i++;
 	} while (len < size);
 
+	new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
+	if (!new) {
+		ret = -ENOMEM;
+		goto error_free;
+	}
 	ret = down_write_killable(&adev->reset_domain->sem);
 	if (ret)
 		goto error_free;
 
 	swap(adev->reset_dump_reg_list, tmp);
+	swap(adev->reset_dump_reg_value, new);
 	adev->num_regs = i;
 	up_write(&adev->reset_domain->sem);
 	ret = size;
 
 error_free:
 	kfree(tmp);
+	kfree(new);
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 625424f3082b..9d6418bb963e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -32,6 +32,9 @@
 #include <linux/slab.h>
 #include <linux/iommu.h>
 #include <linux/pci.h>
+#include <linux/devcoredump.h>
+#include <generated/utsrelease.h>
+#include <linux/pci-p2pdma.h>
 
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
@@ -1942,35 +1945,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	}
 
 	switch (adev->asic_type) {
-#ifdef CONFIG_DRM_AMDGPU_SI
-	case CHIP_VERDE:
-	case CHIP_TAHITI:
-	case CHIP_PITCAIRN:
-	case CHIP_OLAND:
-	case CHIP_HAINAN:
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
-	case CHIP_BONAIRE:
-	case CHIP_HAWAII:
-	case CHIP_KAVERI:
-	case CHIP_KABINI:
-	case CHIP_MULLINS:
-#endif
-	case CHIP_TOPAZ:
-	case CHIP_TONGA:
-	case CHIP_FIJI:
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
-	case CHIP_VEGA20:
-	case CHIP_ALDEBARAN:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_BEIGE_GOBY:
 	default:
 		return 0;
 	case CHIP_VEGA10:
@@ -3316,38 +3290,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_MULLINS:
 		/*
 		 * We have systems in the wild with these ASICs that require
-		 * LVDS and VGA support which is not supported with DC.
+		 * VGA support which is not supported with DC.
 		 *
 		 * Fallback to the non-DC driver here by default so as not to
 		 * cause regressions.
 		 */
 		return amdgpu_dc > 0;
-	case CHIP_HAWAII:
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-	case CHIP_TONGA:
-	case CHIP_FIJI:
-	case CHIP_VEGA10:
-	case CHIP_VEGA12:
-	case CHIP_VEGA20:
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-	case CHIP_RAVEN:
-	case CHIP_NAVI10:
-	case CHIP_NAVI14:
-	case CHIP_NAVI12:
-	case CHIP_RENOIR:
-	case CHIP_CYAN_SKILLFISH:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_BEIGE_GOBY:
-	case CHIP_VANGOGH:
-	case CHIP_YELLOW_CARP:
-#endif
 	default:
 		return amdgpu_dc != 0;
 #else
@@ -3369,7 +3317,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
  */
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev) || 
+	if (amdgpu_sriov_vf(adev) ||
 	    adev->enable_virtual_display ||
 	    (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
 		return false;
@@ -3667,14 +3615,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	if (amdgpu_mcbp)
 		DRM_INFO("MCBP is enabled\n");
 
-	if (adev->asic_type >= CHIP_NAVI10) {
-		if (amdgpu_mes || amdgpu_mes_kiq)
-			adev->enable_mes = true;
-
-		if (amdgpu_mes_kiq)
-			adev->enable_mes_kiq = true;
-	}
-
 	/*
 	 * Reset domain needs to be present early, before XGMI hive discovered
 	 * (if any) and intitialized to use reset sem and in_gpu reset flag
@@ -4721,20 +4661,73 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 
 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
 {
-	uint32_t reg_value;
 	int i;
 
 	lockdep_assert_held(&adev->reset_domain->sem);
 	dump_stack();
 
 	for (i = 0; i < adev->num_regs; i++) {
-		reg_value = RREG32(adev->reset_dump_reg_list[i]);
-		trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], reg_value);
+		adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
+		trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
+					     adev->reset_dump_reg_value[i]);
 	}
 
 	return 0;
 }
 
+#ifdef CONFIG_DEV_COREDUMP
+static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
+		size_t count, void *data, size_t datalen)
+{
+	struct drm_printer p;
+	struct amdgpu_device *adev = data;
+	struct drm_print_iterator iter;
+	int i;
+
+	iter.data = buffer;
+	iter.offset = 0;
+	iter.start = offset;
+	iter.remain = count;
+
+	p = drm_coredump_printer(&iter);
+
+	drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
+	drm_printf(&p, "kernel: " UTS_RELEASE "\n");
+	drm_printf(&p, "module: " KBUILD_MODNAME "\n");
+	drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
+	if (adev->reset_task_info.pid)
+		drm_printf(&p, "process_name: %s PID: %d\n",
+			   adev->reset_task_info.process_name,
+			   adev->reset_task_info.pid);
+
+	if (adev->reset_vram_lost)
+		drm_printf(&p, "VRAM is lost due to GPU reset!\n");
+	if (adev->num_regs) {
+		drm_printf(&p, "AMDGPU register dumps:\nOffset:     Value:\n");
+
+		for (i = 0; i < adev->num_regs; i++)
+			drm_printf(&p, "0x%08x: 0x%08x\n",
+				   adev->reset_dump_reg_list[i],
+				   adev->reset_dump_reg_value[i]);
+	}
+
+	return count - iter.remain;
+}
+
+static void amdgpu_devcoredump_free(void *data)
+{
+}
+
+static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
+{
+	struct drm_device *dev = adev_to_drm(adev);
+
+	ktime_get_ts64(&adev->reset_time);
+	dev_coredumpm(dev->dev, THIS_MODULE, adev, 0,
+		      amdgpu_devcoredump_read, amdgpu_devcoredump_free);
+}
+#endif
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 			 struct amdgpu_reset_context *reset_context)
 {
@@ -4819,6 +4812,15 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 					goto out;
 
 				vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
+#ifdef CONFIG_DEV_COREDUMP
+				tmp_adev->reset_vram_lost = vram_lost;
+				memset(&tmp_adev->reset_task_info, 0,
+						sizeof(tmp_adev->reset_task_info));
+				if (reset_context->job && reset_context->job->vm)
+					tmp_adev->reset_task_info =
+						reset_context->job->vm->task_info;
+				amdgpu_reset_capture_coredumpm(tmp_adev);
+#endif
 				if (vram_lost) {
 					DRM_INFO("VRAM is lost due to GPU reset!\n");
 					amdgpu_inc_vram_lost(tmp_adev);
@@ -5055,6 +5057,27 @@ static void amdgpu_device_recheck_guilty_jobs(
 	}
 }
 
+static inline void amdggpu_device_stop_pedning_resets(struct amdgpu_device *adev)
+{
+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+
+#if defined(CONFIG_DEBUG_FS)
+	if (!amdgpu_sriov_vf(adev))
+		cancel_work(&adev->reset_work);
+#endif
+
+	if (adev->kfd.dev)
+		cancel_work(&adev->kfd.reset_work);
+
+	if (amdgpu_sriov_vf(adev))
+		cancel_work(&adev->virt.flr_work);
+
+	if (con && adev->ras_enabled)
+		cancel_work(&con->recovery_work);
+
+}
+
+
 /**
  * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler
  *
@@ -5066,7 +5089,7 @@ static void amdgpu_device_recheck_guilty_jobs(
  * Returns 0 for success or an error on failure.
  */
 
-int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 			      struct amdgpu_job *job)
 {
 	struct list_head device_list, *device_list_handle =  NULL;
@@ -5164,7 +5187,7 @@ int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
 		 */
 		amdgpu_unregister_gpu_instance(tmp_adev);
 
-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
+		drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
 
 		/* disable ras on ALL IPs */
 		if (!need_emergency_restart &&
@@ -5210,6 +5233,12 @@ int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
 				  r, adev_to_drm(tmp_adev)->unique);
 			tmp_adev->asic_reset_res = r;
 		}
+
+		/*
+		 * Drop all pending non scheduler resets. Scheduler resets
+		 * were already dropped during drm_sched_stop
+		 */
+		amdggpu_device_stop_pedning_resets(tmp_adev);
 	}
 
 	tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter));
@@ -5308,38 +5337,9 @@ int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
 
 	if (r)
 		dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
-	return r;
-}
-
-struct amdgpu_recover_work_struct {
-	struct work_struct base;
-	struct amdgpu_device *adev;
-	struct amdgpu_job *job;
-	int ret;
-};
-
-static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work)
-{
-	struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base);
-
-	recover_work->ret = amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job);
-}
-/*
- * Serialize gpu recover into reset domain single threaded wq
- */
-int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
-				    struct amdgpu_job *job)
-{
-	struct amdgpu_recover_work_struct work = {.adev = adev, .job = job};
-
-	INIT_WORK(&work.base, amdgpu_device_queue_gpu_recover_work);
 
-	if (!amdgpu_reset_domain_schedule(adev->reset_domain, &work.base))
-		return -EAGAIN;
-
-	flush_work(&work.base);
-
-	return work.ret;
+	atomic_set(&adev->reset_domain->reset_res, r);
+	return r;
 }
 
 /**
@@ -5490,6 +5490,36 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
 	}
 }
 
+/**
+ * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
+ *
+ * @adev: amdgpu_device pointer
+ * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
+ *
+ * Return true if @peer_adev can access (DMA) @adev through the PCIe
+ * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
+ * @peer_adev.
+ */
+bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+				      struct amdgpu_device *peer_adev)
+{
+#ifdef CONFIG_HSA_AMD_P2P
+	uint64_t address_mask = peer_adev->dev->dma_mask ?
+		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
+	resource_size_t aper_limit =
+		adev->gmc.aper_base + adev->gmc.aper_size - 1;
+	bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev,
+					&peer_adev->dev, 1, true) < 0);
+
+	return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
+		adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
+		!(adev->gmc.aper_base & address_mask ||
+		  aper_limit & address_mask));
+#else
+	return false;
+#endif
+}
+
 int amdgpu_device_baco_enter(struct drm_device *dev)
 {
 	struct amdgpu_device *adev = drm_to_adev(dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 47f0344205ed..37234c2998d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -194,6 +194,7 @@ static int hw_id_map[MAX_HWIP] = {
 	[UMC_HWIP]	= UMC_HWID,
 	[XGMI_HWIP]	= XGMI_HWID,
 	[DCI_HWIP]	= DCI_HWID,
+	[PCIE_HWIP]	= PCIE_HWID,
 };
 
 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary)
@@ -1435,6 +1436,11 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
 		return -EINVAL;
 	}
 
+	/* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
+	 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
+	 * but that may change in the future with new GPUs so keep this
+	 * check for defensive purposes.
+	 */
 	if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
 		dev_err(adev->dev, "invalid vcn instances\n");
 		return -EINVAL;
@@ -1450,6 +1456,9 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
 
 	switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
 	case 1:
+		/* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
+		 * so this won't overflow.
+		 */
 		for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
 			adev->vcn.vcn_codec_disable_mask[v] =
 				le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
@@ -1709,6 +1718,8 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			amdgpu_device_ip_block_add(adev, &dm_ip_block);
 			break;
 		default:
@@ -1886,6 +1897,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
 			amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 			break;
 		case IP_VERSION(4, 0, 0):
+		case IP_VERSION(4, 0, 2):
 		case IP_VERSION(4, 0, 4):
 			amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
 			amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
@@ -2321,6 +2333,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 
 	switch (adev->ip_versions[LSDMA_HWIP][0]) {
 	case IP_VERSION(6, 0, 0):
+	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
 		adev->lsdma.funcs = &lsdma_v6_0_funcs;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 17c9bbe0cbc5..8ef489fad707 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -30,6 +30,9 @@
 #include "atom.h"
 #include "amdgpu_connectors.h"
 #include "amdgpu_display.h"
+#include "soc15_common.h"
+#include "gc/gc_11_0_0_offset.h"
+#include "gc/gc_11_0_0_sh_mask.h"
 #include <asm/div64.h>
 
 #include <linux/pci.h>
@@ -663,6 +666,11 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 {
 	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 	uint64_t modifier = 0;
+	int num_pipes = 0;
+	int num_pkrs = 0;
+
+	num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
+	num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
 
 	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 		modifier = DRM_FORMAT_MOD_LINEAR;
@@ -675,7 +683,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		int bank_xor_bits = 0;
 		int packers = 0;
 		int rb = 0;
-		int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+		int pipes = ilog2(num_pipes);
 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 
 		switch (swizzle >> 2) {
@@ -691,12 +699,17 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		case 6: /* 64 KiB _X */
 			block_size_bits = 16;
 			break;
+		case 7: /* 256 KiB */
+			block_size_bits = 18;
+			break;
 		default:
 			/* RESERVED or VAR */
 			return -EINVAL;
 		}
 
-		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
+		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
+			version = AMD_FMT_MOD_TILE_VER_GFX11;
+		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
 			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 			version = AMD_FMT_MOD_TILE_VER_GFX10;
@@ -707,19 +720,33 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		case 0: /* Z microtiling */
 			return -EINVAL;
 		case 1: /* S microtiling */
-			if (!has_xor)
-				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
+				if (!has_xor)
+					version = AMD_FMT_MOD_TILE_VER_GFX9;
+			}
 			break;
 		case 2:
-			if (!has_xor && afb->base.format->cpp[0] != 4)
-				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
+				if (!has_xor && afb->base.format->cpp[0] != 4)
+					version = AMD_FMT_MOD_TILE_VER_GFX9;
+			}
 			break;
 		case 3:
 			break;
 		}
 
 		if (has_xor) {
+			if (num_pipes == num_pkrs && num_pkrs == 0) {
+				DRM_ERROR("invalid number of pipes and packers\n");
+				return -EINVAL;
+			}
+
 			switch (version) {
+			case AMD_FMT_MOD_TILE_VER_GFX11:
+				pipe_xor_bits = min(block_size_bits - 8, pipes);
+				packers = min(block_size_bits - 8 - pipe_xor_bits,
+						ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
+				break;
 			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 				pipe_xor_bits = min(block_size_bits - 8, pipes);
 				packers = min(block_size_bits - 8 - pipe_xor_bits,
@@ -753,9 +780,10 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 			u64 render_dcc_offset;
 
 			/* Enable constant encode on RAVEN2 and later. */
-			bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
+			bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
 						   (adev->asic_type == CHIP_RAVEN &&
-						    adev->external_rev_id >= 0x81);
+						    adev->external_rev_id >= 0x81)) &&
+						    adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
 
 			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
@@ -870,10 +898,11 @@ static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 	}
 	case AMD_FMT_MOD_TILE_VER_GFX10:
-	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
+	case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
+	case AMD_FMT_MOD_TILE_VER_GFX11: {
 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 
-		if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
+		if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 			++pipes_log2;
 
@@ -966,6 +995,9 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 			case DC_SW_64KB_S_X:
 				block_size_log2 = 16;
 				break;
+			case DC_SW_VAR_S_X:
+				block_size_log2 = 18;
+				break;
 			default:
 				drm_dbg_kms(rfb->base.dev,
 					    "Swizzle mode with unknown block size: %d\n", swizzle);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8890300766a5..e3d139708160 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -802,6 +802,16 @@ MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (
 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
 #endif
 
+/**
+ * DOC: pcie_p2p (bool)
+ * Enable PCIe P2P (requires large-BAR). Default value: true (on)
+ */
+#ifdef CONFIG_HSA_AMD_P2P
+bool pcie_p2p = true;
+module_param(pcie_p2p, bool, 0444);
+MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
+#endif
+
 /**
  * DOC: dcfeaturemask (uint)
  * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d16c8c1f72db..957437a5558c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -39,6 +39,7 @@
 #include <drm/drm_drv.h>
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
+#include "amdgpu_reset.h"
 
 /*
  * Fences
@@ -798,7 +799,10 @@ static int gpu_recover_get(void *data, u64 *val)
 		return 0;
 	}
 
-	*val = amdgpu_device_gpu_recover(adev, NULL);
+	if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
+		flush_work(&adev->reset_work);
+
+	*val = atomic_read(&adev->reset_domain->reset_res);
 
 	pm_runtime_mark_last_busy(dev->dev);
 	pm_runtime_put_autosuspend(dev->dev);
@@ -810,6 +814,14 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 			 "%lld\n");
 
+static void amdgpu_debugfs_reset_work(struct work_struct *work)
+{
+	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+						  reset_work);
+
+	amdgpu_device_gpu_recover(adev, NULL);
+}
+
 #endif
 
 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
@@ -821,9 +833,12 @@ void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 	debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 			    &amdgpu_debugfs_fence_info_fops);
 
-	if (!amdgpu_sriov_vf(adev))
+	if (!amdgpu_sriov_vf(adev)) {
+
+		INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
 		debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
 				    &amdgpu_debugfs_gpu_recover_fops);
+	}
 #endif
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 16699158e00d..b697353e5a7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -142,7 +142,12 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_s
 	}
 }
 
-static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
+static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
+{
+	return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
+}
+
+static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 {
 	if (amdgpu_compute_multipipe != -1) {
 		DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
@@ -158,6 +163,28 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
 	return adev->gfx.mec.num_mec > 1;
 }
 
+bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
+						struct amdgpu_ring *ring)
+{
+	int queue = ring->queue;
+	int pipe = ring->pipe;
+
+	/* Policy: use pipe1 queue0 as high priority graphics queue if we
+	 * have more than one gfx pipe.
+	 */
+	if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
+	    adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
+		int me = ring->me;
+		int bit;
+
+		bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
+		if (ring == &adev->gfx.gfx_ring[bit])
+			return true;
+	}
+
+	return false;
+}
+
 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 					       struct amdgpu_ring *ring)
 {
@@ -174,7 +201,7 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 {
 	int i, queue, pipe;
-	bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
+	bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 	int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 				     adev->gfx.mec.num_queue_per_pipe,
 				     adev->gfx.num_compute_rings);
@@ -200,18 +227,24 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 
 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 {
-	int i, queue, me;
-
-	for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
-		queue = i % adev->gfx.me.num_queue_per_pipe;
-		me = (i / adev->gfx.me.num_queue_per_pipe)
-		      / adev->gfx.me.num_pipe_per_me;
+	int i, queue, pipe;
+	bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
+	int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
+					adev->gfx.me.num_queue_per_pipe;
 
-		if (me >= adev->gfx.me.num_me)
-			break;
+	if (multipipe_policy) {
 		/* policy: amdgpu owns the first queue per pipe at this stage
 		 * will extend to mulitple queues per pipe later */
-		if (me == 0 && queue < 1)
+		for (i = 0; i < max_queues_per_me; i++) {
+			pipe = i % adev->gfx.me.num_pipe_per_me;
+			queue = (i / adev->gfx.me.num_pipe_per_me) %
+				adev->gfx.me.num_queue_per_pipe;
+
+			set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
+				adev->gfx.me.queue_bitmap);
+		}
+	} else {
+		for (i = 0; i < max_queues_per_me; ++i)
 			set_bit(i, adev->gfx.me.queue_bitmap);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 53526ffb2ce1..23a696d38390 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -396,6 +396,8 @@ bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
 				     int pipe, int queue);
 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 					       struct amdgpu_ring *ring);
+bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
+						struct amdgpu_ring *ring);
 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 			       int pipe, int queue);
 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 56cf127cdf93..484e936812e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -24,12 +24,18 @@
 #ifndef __AMDGPU_IMU_H__
 #define __AMDGPU_IMU_H__
 
+enum imu_work_mode {
+	DEBUG_MODE,
+	MISSION_MODE
+};
+
 struct amdgpu_imu_funcs {
     int (*init_microcode)(struct amdgpu_device *adev);
     int (*load_microcode)(struct amdgpu_device *adev);
     void (*setup_imu)(struct amdgpu_device *adev);
     int (*start_imu)(struct amdgpu_device *adev);
     void (*program_rlc_ram)(struct amdgpu_device *adev);
+    int (*wait_for_reset_status)(struct amdgpu_device *adev);
 };
 
 struct imu_rlc_ram_golden {
@@ -46,6 +52,7 @@ struct imu_rlc_ram_golden {
 
 struct amdgpu_imu {
     const struct amdgpu_imu_funcs *funcs;
+    enum imu_work_mode mode;
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 67f66f2f1809..26ede765eed8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -64,7 +64,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
 		  ti.process_name, ti.tgid, ti.task_name, ti.pid);
 
 	if (amdgpu_device_should_recover_gpu(ring->adev)) {
-		r = amdgpu_device_gpu_recover_imp(ring->adev, job);
+		r = amdgpu_device_gpu_recover(ring->adev, job);
 		if (r)
 			DRM_ERROR("GPU Recovery Failed: %d\n", r);
 	} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index f80b4838cea1..d788a00043a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -37,6 +37,7 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_helper.h>
+#include <drm/drm_framebuffer.h>
 #include <drm/drm_plane_helper.h>
 #include <drm/drm_probe_helper.h>
 #include <linux/i2c.h>
@@ -349,15 +350,11 @@ struct amdgpu_mode_info {
 
 #define AMDGPU_MAX_BL_LEVEL 0xFF
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 struct amdgpu_backlight_privdata {
 	struct amdgpu_encoder *encoder;
 	uint8_t negative;
 };
 
-#endif
-
 struct amdgpu_atom_ss {
 	uint16_t percentage;
 	uint16_t percentage_divider;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index dac202ae864d..285534bfc084 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -35,6 +35,8 @@
 #include "amdgpu_xgmi.h"
 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
 #include "atom.h"
+#include "amdgpu_reset.h"
+
 #ifdef CONFIG_X86_MCE_AMD
 #include <asm/mce.h>
 
@@ -2946,7 +2948,7 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
-		schedule_work(&ras->recovery_work);
+		amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index b9a6fac2b8b2..bf5a95104ec1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -328,10 +328,16 @@ struct ecc_info_per_ch {
 	uint16_t ce_count_hi_chip;
 	uint64_t mca_umc_status;
 	uint64_t mca_umc_addr;
+	uint64_t mca_ceumc_addr;
 };
 
 struct umc_ecc_info {
 	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
+
+	/* Determine smu ecctable whether support
+	 * record correctable error address
+	 */
+	int record_ce_addr_supported;
 };
 
 struct amdgpu_ras {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index c80af0889773..32c86a0b145c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -132,6 +132,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
 	}
 
 	atomic_set(&reset_domain->in_gpu_reset, 0);
+	atomic_set(&reset_domain->reset_res, 0);
 	init_rwsem(&reset_domain->sem);
 
 	return reset_domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index 1949dbe28a86..9e55a5d7a825 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -82,6 +82,7 @@ struct amdgpu_reset_domain {
 	enum amdgpu_reset_domain_type type;
 	struct rw_semaphore sem;
 	atomic_t in_gpu_reset;
+	atomic_t reset_res;
 };
 
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 13db99d653bd..d3558c34d406 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -543,12 +543,12 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
 	 */
 	prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
 
-	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
-			prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
-			prop->hqd_queue_priority =
-				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
-		}
+	if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE &&
+	     amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||
+	    (ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
+	     amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {
+		prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+		prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be6f76a30ac6..3b4c19412625 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1798,18 +1798,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
 
-	/* Compute GTT size, either bsaed on 3/4th the size of RAM size
+	/* Compute GTT size, either based on 1/2 the size of RAM size
 	 * or whatever the user passed on module init */
 	if (amdgpu_gtt_size == -1) {
 		struct sysinfo si;
 
 		si_meminfo(&si);
-		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-			       adev->gmc.mc_vram_size),
-			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
-	}
-	else
+		/* Certain GL unit tests for large textures can cause problems
+		 * with the OOM killer since there is no way to link this memory
+		 * to a process.  This was originally mitigated (but not necessarily
+		 * eliminated) by limiting the GTT size.  The problem is this limit
+		 * is often too low for many modern games so just make the limit 1/2
+		 * of system memory which aligns with TTM. The OOM accounting needs
+		 * to be addressed, but we shouldn't prevent common 3D applications
+		 * from being usable just to potentially mitigate that corner case.
+		 */
+		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+			       (u64)si.totalram * si.mem_unit / 2);
+	} else {
 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+	}
 
 	/* Initialize GTT memory pool */
 	r = amdgpu_gtt_mgr_init(adev, gtt_size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index ffa4c0d207db..c312577df596 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -486,26 +486,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 	case CHIP_POLARIS12:
 	case CHIP_VEGAM:
 		return AMDGPU_FW_LOAD_SMU;
-	case CHIP_VEGA10:
-	case CHIP_RAVEN:
-	case CHIP_VEGA12:
-	case CHIP_VEGA20:
-	case CHIP_ARCTURUS:
-	case CHIP_RENOIR:
-	case CHIP_NAVI10:
-	case CHIP_NAVI14:
-	case CHIP_NAVI12:
-	case CHIP_SIENNA_CICHLID:
-	case CHIP_NAVY_FLOUNDER:
-	case CHIP_VANGOGH:
-	case CHIP_DIMGREY_CAVEFISH:
-	case CHIP_ALDEBARAN:
-	case CHIP_BEIGE_GOBY:
-	case CHIP_YELLOW_CARP:
-		if (!load_type)
-			return AMDGPU_FW_LOAD_DIRECT;
-		else
-			return AMDGPU_FW_LOAD_PSP;
 	case CHIP_CYAN_SKILLFISH:
 		if (!(load_type &&
 		      adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index aa7acfabf360..1bfdfb9207ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -329,6 +329,18 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 	return 0;
 }
 
+/* from vcn4 and above, only unified queue is used */
+static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	bool ret = false;
+
+	if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
+		ret = true;
+
+	return ret;
+}
+
 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 {
 	bool ret = false;
@@ -718,19 +730,55 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	return r;
 }
 
+static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
+						uint32_t ib_pack_in_dw, bool enc)
+{
+	uint32_t *ib_checksum;
+
+	ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
+	ib->ptr[ib->length_dw++] = 0x30000002;
+	ib_checksum = &ib->ptr[ib->length_dw++];
+	ib->ptr[ib->length_dw++] = ib_pack_in_dw;
+
+	ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
+	ib->ptr[ib->length_dw++] = 0x30000001;
+	ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
+	ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
+
+	return ib_checksum;
+}
+
+static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
+						uint32_t ib_pack_in_dw)
+{
+	uint32_t i;
+	uint32_t checksum = 0;
+
+	for (i = 0; i < ib_pack_in_dw; i++)
+		checksum += *(*ib_checksum + 2 + i);
+
+	**ib_checksum = checksum;
+}
+
 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 				      struct amdgpu_ib *ib_msg,
 				      struct dma_fence **fence)
 {
 	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
-	const unsigned int ib_size_dw = 64;
+	unsigned int ib_size_dw = 64;
 	struct amdgpu_device *adev = ring->adev;
 	struct dma_fence *f = NULL;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
+	uint32_t *ib_checksum;
+	uint32_t ib_pack_in_dw;
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
 				AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -739,6 +787,13 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 	ib = &job->ibs[0];
 	ib->length_dw = 0;
 
+	/* single queue headers */
+	if (sq) {
+		ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
+						+ 4 + 2; /* engine info + decoding ib in dw */
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
+	}
+
 	ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 	ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
@@ -752,6 +807,9 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err_free;
@@ -838,13 +896,18 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 					 struct amdgpu_ib *ib_msg,
 					 struct dma_fence **fence)
 {
-	const unsigned ib_size_dw = 16;
+	unsigned int ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
+	uint32_t *ib_checksum = NULL;
 	uint64_t addr;
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 					AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -854,6 +917,10 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 	addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 
 	ib->length_dw = 0;
+
+	if (sq)
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
+
 	ib->ptr[ib->length_dw++] = 0x00000018;
 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 	ib->ptr[ib->length_dw++] = handle;
@@ -873,6 +940,9 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err;
@@ -892,13 +962,18 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 					  struct amdgpu_ib *ib_msg,
 					  struct dma_fence **fence)
 {
-	const unsigned ib_size_dw = 16;
+	unsigned int ib_size_dw = 16;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	struct dma_fence *f = NULL;
+	uint32_t *ib_checksum = NULL;
 	uint64_t addr;
+	bool sq = amdgpu_vcn_using_unified_queue(ring);
 	int i, r;
 
+	if (sq)
+		ib_size_dw += 8;
+
 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
 					AMDGPU_IB_POOL_DIRECT, &job);
 	if (r)
@@ -908,6 +983,10 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 	addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 
 	ib->length_dw = 0;
+
+	if (sq)
+		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
+
 	ib->ptr[ib->length_dw++] = 0x00000018;
 	ib->ptr[ib->length_dw++] = 0x00000001;
 	ib->ptr[ib->length_dw++] = handle;
@@ -927,6 +1006,9 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 	for (i = ib->length_dw; i < ib_size_dw; ++i)
 		ib->ptr[i] = 0x0;
 
+	if (sq)
+		amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
+
 	r = amdgpu_job_submit_direct(job, ring, &f);
 	if (r)
 		goto err;
@@ -977,6 +1059,20 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	return r;
 }
 
+int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+	long r;
+
+	r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
+	if (r)
+		goto error;
+
+	r =  amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
+
+error:
+	return r;
+}
+
 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
 {
 	switch(ring) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 6f90fcee0f9c..60c608144480 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -364,6 +364,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dc76d2b3ce52..8530befb2051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -54,7 +54,7 @@
  * (uncached system pages).
  * Each VM has an ID associated with it and there is a page table
  * associated with each VMID.  When executing a command buffer,
- * the kernel tells the the ring what VMID to use for that command
+ * the kernel tells the ring what VMID to use for that command
  * buffer.  VMIDs are allocated dynamically as commands are submitted.
  * The userspace drivers maintain their own address space and the kernel
  * sets up their pages tables accordingly when they submit their
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 49e4092f447f..7a5e8a7b4a1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,6 +50,35 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
 	return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
 }
 
+static inline struct drm_buddy_block *
+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+	return list_first_entry_or_null(list, struct drm_buddy_block, link);
+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
+{
+	struct drm_buddy_block *block;
+	u64 start, size;
+
+	block = amdgpu_vram_mgr_first_block(head);
+	if (!block)
+		return false;
+
+	while (head != block->link.next) {
+		start = amdgpu_vram_mgr_block_start(block);
+		size = amdgpu_vram_mgr_block_size(block);
+
+		block = list_entry(block->link.next, struct drm_buddy_block, link);
+		if (start + size != amdgpu_vram_mgr_block_start(block))
+			return false;
+	}
+
+	return true;
+}
+
+
+
 /**
  * DOC: mem_info_vram_total
  *
@@ -496,16 +525,22 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
 			list_splice_tail(trim_list, &vres->blocks);
 	}
 
-	list_for_each_entry(block, &vres->blocks, link)
-		vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
+	vres->base.start = 0;
+	list_for_each_entry(block, &vres->blocks, link) {
+		unsigned long start;
 
-	block = amdgpu_vram_mgr_first_block(&vres->blocks);
-	if (!block) {
-		r = -EINVAL;
-		goto error_fini;
-	}
+		start = amdgpu_vram_mgr_block_start(block) +
+			amdgpu_vram_mgr_block_size(block);
+		start >>= PAGE_SHIFT;
+
+		if (start > vres->base.num_pages)
+			start -= vres->base.num_pages;
+		else
+			start = 0;
+		vres->base.start = max(vres->base.start, start);
 
-	vres->base.start = amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+		vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
+	}
 
 	if (amdgpu_is_vram_mgr_blocks_contiguous(&vres->blocks))
 		vres->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 9a2db87186c7..4b267bf1c5db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,33 +53,6 @@ static inline u64 amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)
 	return PAGE_SIZE << drm_buddy_block_order(block);
 }
 
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
-	return list_first_entry_or_null(list, struct drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
-{
-	struct drm_buddy_block *block;
-	u64 start, size;
-
-	block = amdgpu_vram_mgr_first_block(head);
-	if (!block)
-		return false;
-
-	while (head != block->link.next) {
-		start = amdgpu_vram_mgr_block_start(block);
-		size = amdgpu_vram_mgr_block_size(block);
-
-		block = list_entry(block->link.next, struct drm_buddy_block, link);
-		if (start + size != amdgpu_vram_mgr_block_start(block))
-			return false;
-	}
-
-	return true;
-}
-
 static inline struct amdgpu_vram_mgr_resource *
 to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index d4f5a584075d..fa7421afb9a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -118,8 +118,6 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode
 	}
 }
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)
 {
 	u8 level;
@@ -251,18 +249,6 @@ amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder)
 	}
 }
 
-#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
-
-void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder)
-{
-}
-
-void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder)
-{
-}
-
-#endif
-
 bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
 {
 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c5f46d264b23..abf2bf7f1a79 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -53,7 +53,7 @@
  * 2. Async ring
  */
 #define GFX10_NUM_GFX_RINGS_NV1X	1
-#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
+#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
 #define GFX10_MEC_HPD_SIZE	2048
 
 #define F32_CE_PROGRAM_RAM_SIZE		65536
@@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
+	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 	uint32_t tmp = 0;
 	unsigned i;
 	int r;
 
-	WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+	WREG32(scratch, 0xCAFEDEAD);
 	r = amdgpu_ring_alloc(ring, 3);
 	if (r) {
 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 	}
 
 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-	amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+	amdgpu_ring_write(ring, scratch -
 			  PACKET3_SET_UCONFIG_REG_START);
 	amdgpu_ring_write(ring, 0xDEADBEEF);
 	amdgpu_ring_commit(ring);
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+		tmp = RREG32(scratch);
 		if (tmp == 0xDEADBEEF)
 			break;
 		if (amdgpu_emu_mode == 1)
@@ -4711,6 +4712,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 {
 	struct amdgpu_ring *ring;
 	unsigned int irq_type;
+	unsigned int hw_prio;
 
 	ring = &adev->gfx.gfx_ring[ring_id];
 
@@ -4728,8 +4730,10 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 
 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
+	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
+			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
-			     AMDGPU_RING_PRIO_DEFAULT, NULL);
+				hw_prio, NULL);
 }
 
 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
@@ -4791,7 +4795,7 @@ static int gfx_v10_0_sw_init(void *handle)
 	case IP_VERSION(10, 3, 3):
 	case IP_VERSION(10, 3, 7):
 		adev->gfx.me.num_me = 1;
-		adev->gfx.me.num_pipe_per_me = 1;
+		adev->gfx.me.num_pipe_per_me = 2;
 		adev->gfx.me.num_queue_per_pipe = 1;
 		adev->gfx.mec.num_mec = 2;
 		adev->gfx.mec.num_pipe_per_mec = 4;
@@ -6581,6 +6585,24 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 	}
 }
 
+static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
+					   struct v10_gfx_mqd *mqd,
+					   struct amdgpu_mqd_prop *prop)
+{
+	bool priority = 0;
+	u32 tmp;
+
+	/* set up default queue priority level
+	 * 0x0 = low priority, 0x1 = high priority
+	 */
+	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
+		priority = 1;
+
+	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
+	mqd->cp_gfx_hqd_queue_priority = tmp;
+}
+
 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
 				  struct amdgpu_mqd_prop *prop)
 {
@@ -6609,11 +6631,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
 	mqd->cp_gfx_hqd_vmid = 0;
 
-	/* set up default queue priority level
-	 * 0x0 = low priority, 0x1 = high priority */
-	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
-	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
-	mqd->cp_gfx_hqd_queue_priority = tmp;
+	/* set up gfx queue priority */
+	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
 
 	/* set up time quantum */
 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index a4a6751b1e44..942d41a65f2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4563,6 +4563,9 @@ static int gfx_v11_0_hw_init(void *handle)
 				if (adev->gfx.imu.funcs->start_imu)
 					adev->gfx.imu.funcs->start_imu(adev);
 			}
+
+			/* disable gpa mode in backdoor loading */
+			gfx_v11_0_disable_gpa_mode(adev);
 		}
 	}
 
@@ -4781,19 +4784,17 @@ static int gfx_v11_0_soft_reset(void *handle)
 		/* Disable MEC parsing/prefetching */
 		gfx_v11_0_cp_compute_enable(adev, false);
 
-		if (grbm_soft_reset) {
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
-			tmp |= grbm_soft_reset;
-			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
-			WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
+		tmp |= grbm_soft_reset;
+		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 
-			udelay(50);
+		udelay(50);
 
-			tmp &= ~grbm_soft_reset;
-			WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
-			tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
-		}
+		tmp &= ~grbm_soft_reset;
+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 
 		/* Wait a little for things to settle down */
 		udelay(50);
@@ -6293,6 +6294,11 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 
 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
 {
+	if (adev->flags & AMD_IS_APU)
+		adev->gfx.imu.mode = MISSION_MODE;
+	else
+		adev->gfx.imu.mode = DEBUG_MODE;
+
 	adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 9077dfccaf3c..25d5743ae91b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -456,7 +456,8 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 				gmc_v10_0_flush_gpu_tlb(adev, vmid,
 						AMDGPU_GFXHUB_0, flush_type);
 			}
-			break;
+			if (!adev->enable_mes)
+				break;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 7f4b480ae66e..e098b69d6321 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -37,6 +37,7 @@
 #include "nbio_v4_3.h"
 #include "gfxhub_v3_0.h"
 #include "mmhub_v3_0.h"
+#include "mmhub_v3_0_1.h"
 #include "mmhub_v3_0_2.h"
 #include "athub_v3_0.h"
 
@@ -258,6 +259,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 					uint32_t vmhub, uint32_t flush_type)
 {
+	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	struct dma_fence *fence;
+	struct amdgpu_job *job;
+
+	int r;
+
 	if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
 		return;
 
@@ -281,8 +288,51 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 	}
 
 	mutex_lock(&adev->mman.gtt_window_lock);
-	gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
+
+	if (vmhub == AMDGPU_MMHUB_0) {
+		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
+		mutex_unlock(&adev->mman.gtt_window_lock);
+		return;
+	}
+
+	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
+
+	if (!adev->mman.buffer_funcs_enabled ||
+	    !adev->ib_pool_ready ||
+	    amdgpu_in_reset(adev) ||
+	    ring->sched.ready == false) {
+		gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
+		mutex_unlock(&adev->mman.gtt_window_lock);
+		return;
+	}
+
+	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
+				     &job);
+	if (r)
+		goto error_alloc;
+
+	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+	job->vm_needs_flush = true;
+	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
+	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+	r = amdgpu_job_submit(job, &adev->mman.entity,
+			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+	if (r)
+		goto error_submit;
+
 	mutex_unlock(&adev->mman.gtt_window_lock);
+
+	dma_fence_wait(fence, false);
+	dma_fence_put(fence);
+
+	return;
+
+error_submit:
+	amdgpu_job_free(job);
+
+error_alloc:
+	mutex_unlock(&adev->mman.gtt_window_lock);
+	DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 	return;
 }
 
@@ -343,7 +393,6 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 				gmc_v11_0_flush_gpu_tlb(adev, vmid,
 						AMDGPU_GFXHUB_0, flush_type);
 			}
-			break;
 		}
 	}
 
@@ -548,6 +597,9 @@ static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
 	switch (adev->ip_versions[MMHUB_HWIP][0]) {
+	case IP_VERSION(3, 0, 1):
+		adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
+		break;
 	case IP_VERSION(3, 0, 2):
 		adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index d63d3f2b8a16..76383baa3929 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -24,6 +24,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_imu.h"
+#include "amdgpu_dpm.h"
 
 #include "gc/gc_11_0_0_offset.h"
 #include "gc/gc_11_0_0_sh_mask.h"
@@ -117,6 +118,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
+{
+	int i, imu_reg_val = 0;
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+		if ((imu_reg_val & 0x1f) == 0x1f)
+			break;
+		udelay(1);
+	}
+
+	if (i >= adev->usec_timeout) {
+		dev_err(adev->dev, "init imu: IMU start timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
 static void imu_v11_0_setup(struct amdgpu_device *adev)
 {
 	int imu_reg_val;
@@ -125,9 +145,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
 	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
 	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
 
-	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
-	imu_reg_val |= 0x1;
-	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+	if (adev->gfx.imu.mode == DEBUG_MODE) {
+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+		imu_reg_val |= 0x1;
+		WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+	}
 
 	//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
 	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -137,26 +159,17 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
 
 static int imu_v11_0_start(struct amdgpu_device *adev)
 {
-	int imu_reg_val, i;
+	int imu_reg_val;
 
 	//Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0
 	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
 	imu_reg_val &= 0xfffffffe;
 	WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-	for (i = 0; i < adev->usec_timeout; i++) {
-		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
-		if ((imu_reg_val & 0x1f) == 0x1f)
-			break;
-		udelay(1);
-	}
+	if (adev->flags & AMD_IS_APU)
+		amdgpu_dpm_set_gfx_power_up_by_imu(adev);
 
-	if (i >= adev->usec_timeout) {
-		dev_err(adev->dev, "init imu: IMU start timeout\n");
-		return -ETIMEDOUT;
-	}
-
-	return 0;
+	return imu_v11_0_wait_for_reset_status(adev);
 }
 
 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
@@ -364,4 +377,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
 	.setup_imu = imu_v11_0_setup,
 	.start_imu = imu_v11_0_start,
 	.program_rlc_ram = imu_v11_0_program_rlc_ram,
+	.wait_for_reset_status = imu_v11_0_wait_for_reset_status,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
new file mode 100644
index 000000000000..cac72ced94c8
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "mmhub_v3_0_1.h"
+
+#include "mmhub/mmhub_3_0_1_offset.h"
+#include "mmhub/mmhub_3_0_1_sh_mask.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+#define regMMVM_L2_CNTL3_DEFAULT				0x80100007
+#define regMMVM_L2_CNTL4_DEFAULT				0x000000c1
+#define regMMVM_L2_CNTL5_DEFAULT				0x00003fe0
+
+static const char *mmhub_client_ids_v3_0_1[][2] = {
+	[0][0] = "VMC",
+	[4][0] = "DCEDMC",
+	[5][0] = "DCEVGA",
+	[6][0] = "MP0",
+	[7][0] = "MP1",
+	[8][0] = "MPIO",
+	[16][0] = "HDP",
+	[17][0] = "LSDMA",
+	[18][0] = "JPEG",
+	[19][0] = "VCNU0",
+	[21][0] = "VSCH",
+	[22][0] = "VCNU1",
+	[23][0] = "VCN1",
+	[32+20][0] = "VCN0",
+	[2][1] = "DBGUNBIO",
+	[3][1] = "DCEDWB",
+	[4][1] = "DCEDMC",
+	[5][1] = "DCEVGA",
+	[6][1] = "MP0",
+	[7][1] = "MP1",
+	[8][1] = "MPIO",
+	[10][1] = "DBGU0",
+	[11][1] = "DBGU1",
+	[12][1] = "DBGU2",
+	[13][1] = "DBGU3",
+	[14][1] = "XDP",
+	[15][1] = "OSSSYS",
+	[16][1] = "HDP",
+	[17][1] = "LSDMA",
+	[18][1] = "JPEG",
+	[19][1] = "VCNU0",
+	[20][1] = "VCN0",
+	[21][1] = "VSCH",
+	[22][1] = "VCNU1",
+	[23][1] = "VCN1",
+};
+
+static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
+						uint32_t flush_type)
+{
+	u32 req = 0;
+
+	/* invalidate using legacy mode on vmid*/
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
+
+	return req;
+}
+
+static void
+mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
+					      uint32_t status)
+{
+	uint32_t cid, rw;
+	const char *mmhub_cid = NULL;
+
+	cid = REG_GET_FIELD(status,
+			    MMVM_L2_PROTECTION_FAULT_STATUS, CID);
+	rw = REG_GET_FIELD(status,
+			   MMVM_L2_PROTECTION_FAULT_STATUS, RW);
+
+	dev_err(adev->dev,
+		"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+		status);
+
+	switch (adev->ip_versions[MMHUB_HWIP][0]) {
+	case IP_VERSION(3, 0, 1):
+		mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
+		break;
+	default:
+		mmhub_cid = NULL;
+		break;
+	}
+
+	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+		mmhub_cid ? mmhub_cid : "unknown", cid);
+	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
+}
+
+static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
+					  uint32_t vmid,
+					  uint64_t page_table_base)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+			    hub->ctx_addr_distance * vmid,
+			    lower_32_bits(page_table_base));
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+			    hub->ctx_addr_distance * vmid,
+			    upper_32_bits(page_table_base));
+}
+
+static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+	mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+		     (u32)(adev->gmc.gart_start >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+		     (u32)(adev->gmc.gart_start >> 44));
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+		     (u32)(adev->gmc.gart_end >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+		     (u32)(adev->gmc.gart_end >> 44));
+}
+
+static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t value;
+	uint32_t tmp;
+
+	/* Program the AGP BAR */
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+
+	/*
+	 * the new L1 policy will block SRIOV guest from writing
+	 * these regs, and they will be programed at host.
+	 * so skip programing these regs.
+	 */
+	/* Program the system aperture low logical page number. */
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+		     adev->gmc.vram_start >> 18);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+		     adev->gmc.vram_end >> 18);
+
+	/* Set default page address. */
+	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+		adev->vm_manager.vram_base_offset;
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+		     (u32)(value >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+		     (u32)(value >> 44));
+
+	/* Program "protection fault". */
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+		     (u32)(adev->dummy_page_addr >> 12));
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+		     (u32)((u64)adev->dummy_page_addr >> 44));
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
+}
+
+static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
+
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC); /* UC, uncached */
+
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
+}
+
+static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
+			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
+	/* XXX for emulation, Refer to closed source code.*/
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+			    0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
+
+	tmp = regMMVM_L2_CNTL3_DEFAULT;
+	if (adev->gmc.translate_further) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+	} else {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+	}
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
+
+	tmp = regMMVM_L2_CNTL4_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
+
+	tmp = regMMVM_L2_CNTL5_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+}
+
+static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
+}
+
+static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+		     0xFFFFFFFF);
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+		     0x0000000F);
+
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
+	WREG32_SOC15(MMHUB, 0,
+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
+
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
+		     0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
+		     0);
+}
+
+static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	int i;
+	uint32_t tmp;
+
+	for (i = 0; i <= 14; i++) {
+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+				    adev->vm_manager.num_level);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+				    1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PAGE_TABLE_BLOCK_SIZE,
+				    adev->vm_manager.block_size - 9);
+		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+				    !amdgpu_noretry);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
+				    i * hub->ctx_distance, tmp);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+				    i * hub->ctx_addr_distance,
+				    lower_32_bits(adev->vm_manager.max_pfn - 1));
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+				    i * hub->ctx_addr_distance,
+				    upper_32_bits(adev->vm_manager.max_pfn - 1));
+	}
+
+	hub->vm_cntx_cntl = tmp;
+}
+
+static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	unsigned i;
+
+	for (i = 0; i < 18; ++i) {
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+				    i * hub->eng_addr_distance, 0xffffffff);
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+				    i * hub->eng_addr_distance, 0x1f);
+	}
+}
+
+static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
+{
+	/* GART Enable. */
+	mmhub_v3_0_1_init_gart_aperture_regs(adev);
+	mmhub_v3_0_1_init_system_aperture_regs(adev);
+	mmhub_v3_0_1_init_tlb_regs(adev);
+	mmhub_v3_0_1_init_cache_regs(adev);
+
+	mmhub_v3_0_1_enable_system_domain(adev);
+	mmhub_v3_0_1_disable_identity_aperture(adev);
+	mmhub_v3_0_1_setup_vmid_config(adev);
+	mmhub_v3_0_1_program_invalidation(adev);
+
+	return 0;
+}
+
+static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	u32 tmp;
+	u32 i;
+
+	/* Disable all tables */
+	for (i = 0; i < 16; i++)
+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
+				    i * hub->ctx_distance, 0);
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
+}
+
+/**
+ * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
+						  bool value)
+{
+	u32 tmp;
+
+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
+			    value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	if (!value) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_NO_RETRY_FAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_RETRY_FAULT, 1);
+	}
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
+	.print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
+	.get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
+};
+
+static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	hub->ctx0_ptb_addr_lo32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
+	hub->ctx0_ptb_addr_hi32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
+	hub->vm_inv_eng0_sem =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
+	hub->vm_inv_eng0_req =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
+	hub->vm_inv_eng0_ack =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
+	hub->vm_context0_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
+	hub->vm_l2_pro_fault_status =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
+	hub->vm_l2_pro_fault_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
+
+	hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
+	hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
+		regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+	hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
+		regMMVM_INVALIDATE_ENG0_REQ;
+	hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
+		regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+	hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+	hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
+}
+
+static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
+{
+	u64 base;
+
+	base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
+	base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
+	base <<= 24;
+
+	return base;
+}
+
+static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
+{
+	return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
+}
+
+static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+							  bool enable)
+{
+	//TODO
+}
+
+static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+							 bool enable)
+{
+	//TODO
+}
+
+static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
+					enum amd_clockgating_state state)
+{
+	mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
+			state == AMD_CG_STATE_GATE);
+	mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
+			state == AMD_CG_STATE_GATE);
+	return 0;
+}
+
+static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
+{
+	//TODO
+}
+
+const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
+	.init = mmhub_v3_0_1_init,
+	.get_fb_location = mmhub_v3_0_1_get_fb_location,
+	.get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
+	.gart_enable = mmhub_v3_0_1_gart_enable,
+	.set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
+	.gart_disable = mmhub_v3_0_1_gart_disable,
+	.set_clockgating = mmhub_v3_0_1_set_clockgating,
+	.get_clockgating = mmhub_v3_0_1_get_clockgating,
+	.setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
new file mode 100644
index 000000000000..4c1246735e7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __MMHUB_V3_0_1_H__
+#define __MMHUB_V3_0_1_H__
+
+extern const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index b81acf59870c..7ec5b5cf4bb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -284,7 +284,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
 	if (amdgpu_device_should_recover_gpu(adev)
 		&& (!amdgpu_device_has_job_running(adev) ||
 		adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 22c10b97ea81..e18b75c8fde6 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -311,7 +311,7 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
 		adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
 		adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
 		adev->video_timeout == MAX_SCHEDULE_TIMEOUT))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 7b63d30b9b79..c5016a926331 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -523,7 +523,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
 
 	/* Trigger recovery due to world switch failure */
 	if (amdgpu_device_should_recover_gpu(adev))
-		amdgpu_device_gpu_recover_imp(adev, NULL);
+		amdgpu_device_gpu_recover(adev, NULL);
 }
 
 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 6cd1fb2eb913..34c610b9157d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -547,7 +547,7 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
 {
 	uint32_t reg, reg_data;
 
-	if (adev->asic_type != CHIP_SIENNA_CICHLID)
+	if (adev->ip_versions[NBIO_HWIP][0] != IP_VERSION(3, 3, 0))
 		return;
 
 	reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index ed31d133f07a..982a89f841d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -240,8 +240,11 @@ static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *ade
 {
 	uint32_t def, data;
 
+	if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+		return;
+
 	def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
+	if (enable) {
 		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 			 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 			 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
@@ -266,9 +269,12 @@ static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev
 {
 	uint32_t def, data;
 
+	if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+		return;
+
 	/* TODO: need update in future */
 	def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+	if (enable) {
 		data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
 	} else {
 		data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
@@ -344,6 +350,121 @@ static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
 	return rom_offset;
 }
 
+#ifdef CONFIG_PCIEASPM
+static void nbio_v4_3_program_ltr(struct amdgpu_device *adev)
+{
+	uint32_t def, data;
+
+	def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
+	data = 0x35EB;
+	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
+	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);
+	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+	if (adev->pdev->ltr_path)
+		data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	else
+		data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+}
+#endif
+
+static void nbio_v4_3_program_aspm(struct amdgpu_device *adev)
+{
+#ifdef CONFIG_PCIEASPM
+	uint32_t def, data;
+
+	if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) &&
+	      !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0)))
+		return;
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);
+	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
+	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+
+	WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);
+	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
+		PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
+	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);
+	data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);
+	data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data);
+
+	nbio_v4_3_program_ltr(adev);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);
+	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
+	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);
+	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);
+	data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+	data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+	data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data);
+
+	def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);
+	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data);
+#endif
+}
+
 const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
 	.get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
@@ -365,4 +486,5 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
 	.init_registers = nbio_v4_3_init_registers,
 	.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
 	.get_rom_offset = nbio_v4_3_get_rom_offset,
+	.program_aspm = nbio_v4_3_program_aspm,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index cdc0c9779848..e786b825cea9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -58,10 +58,16 @@ static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instan
 					  bool use_doorbell, int doorbell_index,
 					  int doorbell_size)
 {
-	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
 	u32 doorbell_range = RREG32_PCIE_PORT(reg);
 
 	if (use_doorbell) {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_CSDMA_DOORBELL_RANGE,
+					       OFFSET, doorbell_index);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_CSDMA_DOORBELL_RANGE,
+					       SIZE, doorbell_size);
 		doorbell_range = REG_SET_FIELD(doorbell_range,
 					       GDC0_BIF_SDMA0_DOORBELL_RANGE,
 					       OFFSET, doorbell_index);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9e18a2b22607..495848515edf 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -310,6 +310,7 @@ static enum amd_reset_method
 soc21_asic_reset_method(struct amdgpu_device *adev)
 {
 	if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
+	    amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 		return amdgpu_reset_method;
 
@@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
 	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 0):
 		return AMD_RESET_METHOD_MODE1;
+	case IP_VERSION(13, 0, 4):
+		return AMD_RESET_METHOD_MODE2;
 	default:
 		if (amdgpu_dpm_is_baco_supported(adev))
 			return AMD_RESET_METHOD_BACO;
@@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev)
 		dev_info(adev->dev, "BACO reset\n");
 		ret = amdgpu_dpm_baco_reset(adev);
 		break;
+	case AMD_RESET_METHOD_MODE2:
+		dev_info(adev->dev, "MODE2 reset\n");
+		ret = amdgpu_dpm_mode2_reset(adev);
+		break;
 	default:
 		dev_info(adev->dev, "MODE1 reset\n");
 		ret = amdgpu_device_mode1_reset(adev);
@@ -379,11 +386,12 @@ static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void soc21_program_aspm(struct amdgpu_device *adev)
 {
-
-	if (amdgpu_aspm == 0)
+	if (!amdgpu_device_should_use_aspm(adev))
 		return;
 
-	/* todo */
+	if (!(adev->flags & AMD_IS_APU) &&
+	    (adev->nbio.funcs->program_aspm))
+		adev->nbio.funcs->program_aspm(adev);
 }
 
 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -555,8 +563,11 @@ static int soc21_common_early_init(void *handle)
 		adev->cg_flags =
 			AMD_CG_SUPPORT_GFX_CGCG |
 			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_REPEATER_FGCG |
 			AMD_CG_SUPPORT_VCN_MGCG |
-			AMD_CG_SUPPORT_JPEG_MGCG;
+			AMD_CG_SUPPORT_JPEG_MGCG |
+			AMD_CG_SUPPORT_ATHUB_MGCG |
+			AMD_CG_SUPPORT_ATHUB_LS;
 		adev->pg_flags =
 			AMD_PG_SUPPORT_VCN |
 			AMD_PG_SUPPORT_VCN_DPG |
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 606892dbea1c..bf7524f16b66 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -119,6 +119,24 @@ static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device
 		*error_count += 1;
 
 		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);
+
+		if (ras->umc_ecc.record_ce_addr_supported)	{
+			uint64_t err_addr, soc_pa;
+			uint32_t channel_index =
+				adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+
+			err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr;
+			err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
+			/* translate umc channel address to soc pa, 3 parts are included */
+			soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
+					ADDR_OF_256B_BLOCK(channel_index) |
+					OFFSET_IN_256B_BLOCK(err_addr);
+
+			/* The umc channel bits are not original values, they are hashed */
+			SET_CHANNEL_HASH(channel_index, soc_pa);
+
+			dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa);
+		}
 	}
 }
 
@@ -251,7 +269,9 @@ static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev
 
 static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
 						   uint32_t umc_reg_offset,
-						   unsigned long *error_count)
+						   unsigned long *error_count,
+						   uint32_t ch_inst,
+						   uint32_t umc_inst)
 {
 	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
 	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
@@ -295,6 +315,31 @@ static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
 		*error_count += 1;
 
 		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);
+
+		{
+			uint64_t err_addr, soc_pa;
+			uint32_t mc_umc_addrt0;
+			uint32_t channel_index;
+
+			mc_umc_addrt0 =
+				SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
+
+			channel_index =
+				adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
+
+			err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
+			err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
+
+			/* translate umc channel address to soc pa, 3 parts are included */
+			soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
+					ADDR_OF_256B_BLOCK(channel_index) |
+					OFFSET_IN_256B_BLOCK(err_addr);
+
+			/* The umc channel bits are not original values, they are hashed */
+			SET_CHANNEL_HASH(channel_index, soc_pa);
+
+			dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa);
+		}
 	}
 }
 
@@ -395,7 +440,8 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev,
 							 ch_inst);
 		umc_v6_7_query_correctable_error_count(adev,
 						       umc_reg_offset,
-						       &(err_data->ce_count));
+						       &(err_data->ce_count),
+						       ch_inst, umc_inst);
 		umc_v6_7_querry_uncorrectable_error_count(adev,
 							  umc_reg_offset,
 							  &(err_data->ue_count));
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 9119e966ffff..84ac2401895a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -29,7 +29,6 @@
 #include "soc15d.h"
 #include "soc15_hw_ip.h"
 #include "vcn_v2_0.h"
-#include "vcn_sw_ring.h"
 
 #include "vcn/vcn_4_0_0_offset.h"
 #include "vcn/vcn_4_0_0_sh_mask.h"
@@ -45,15 +44,12 @@
 #define VCN_VID_SOC_ADDRESS_2_0							0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0						0x48300
 
-bool unifiedQ_enabled = false;
-
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
 	SOC15_IH_CLIENTID_VCN1
 };
 
-static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vcn_v4_0_set_powergating_state(void *handle,
         enum amd_powergating_state state);
@@ -71,36 +67,15 @@ static int vcn_v4_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (unifiedQ_enabled) {
-		adev->vcn.num_vcn_inst = 1;
-		adev->vcn.num_enc_rings = 1;
-	} else {
-		adev->vcn.num_enc_rings = 2;
-	}
-
-	if (!unifiedQ_enabled)
-		vcn_v4_0_set_dec_ring_funcs(adev);
+	/* re-use enc ring as unified ring */
+	adev->vcn.num_enc_rings = 1;
 
-	vcn_v4_0_set_enc_ring_funcs(adev);
+	vcn_v4_0_set_unified_ring_funcs(adev);
 	vcn_v4_0_set_irq_funcs(adev);
 
 	return 0;
 }
 
-static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev)
-{
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
-		adev->firmware.fw_size +=
-			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		DRM_INFO("PSP loading VCN firmware\n");
-	}
-}
-
 /**
  * vcn_v4_0_sw_init - sw init for VCN block
  *
@@ -111,17 +86,14 @@ static void amdgpu_vcn_setup_unified_queue_ucode(struct amdgpu_device *adev)
 static int vcn_v4_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
-	int i, j, r;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, r;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
 		return r;
 
-	if (unifiedQ_enabled)
-		amdgpu_vcn_setup_unified_queue_ucode(adev);
-	else
-		amdgpu_vcn_setup_ucode(adev);
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
@@ -129,81 +101,40 @@ static int vcn_v4_0_sw_init(void *handle)
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 		volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
-		/* VCN DEC TRAP */
+
+		atomic_set(&adev->vcn.inst[i].sched_score, 0);
+
+		/* VCN UNIFIED TRAP */
 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
-				VCN_4_0__SRCID__UVD_TRAP, &adev->vcn.inst[i].irq);
+				VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 		if (r)
 			return r;
 
-		atomic_set(&adev->vcn.inst[i].sched_score, 0);
-		if (!unifiedQ_enabled) {
-			ring = &adev->vcn.inst[i].ring_dec;
-			ring->use_doorbell = true;
-
-			/* VCN4 doorbell layout
-			 * 1: VCN_JPEG_DB_CTRL UVD_JRBC_RB_WPTR; (jpeg)
-			 * 2: VCN_RB1_DB_CTRL  UVD_RB_WPTR; (decode/encode for unified queue)
-			 * 3: VCN_RB2_DB_CTRL  UVD_RB_WPTR2; (encode only for swqueue)
-			 * 4: VCN_RB3_DB_CTRL  UVD_RB_WPTR3; (Reserved)
-			 * 5: VCN_RB4_DB_CTRL  UVD_RB_WPTR4; (decode only for swqueue)
-			 */
-
-			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1)
-						+ 5 + 8 * i;
-
-			sprintf(ring->name, "vcn_dec_%d", i);
-			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-					     AMDGPU_RING_PRIO_DEFAULT,
-					     &adev->vcn.inst[i].sched_score);
-			if (r)
-				return r;
-		}
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			/* VCN ENC TRAP */
-			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
-				j + VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
-			if (r)
-				return r;
-
-			ring = &adev->vcn.inst[i].ring_enc[j];
-			ring->use_doorbell = true;
-
-			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
-
-			if (unifiedQ_enabled) {
-				sprintf(ring->name, "vcn_unified%d", i);
-				r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
-				     AMDGPU_RING_PRIO_DEFAULT, NULL);
-			} else {
-				enum amdgpu_ring_priority_level hw_prio;
+		ring = &adev->vcn.inst[i].ring_enc[0];
+		ring->use_doorbell = true;
+		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
 
-				hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
-				sprintf(ring->name, "vcn_enc_%d.%d", i, j);
-				r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-					     hw_prio, &adev->vcn.inst[i].sched_score);
-			}
-			if (r)
-				return r;
-		}
+		sprintf(ring->name, "vcn_unified_%d", i);
 
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-		fw_shared->present_flag_0 = 0;
+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
+						AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
+		if (r)
+			return r;
 
-		if (unifiedQ_enabled) {
-			fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
-			fw_shared->sq.is_enabled = 1;
-		}
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+		fw_shared->sq.is_enabled = 1;
 
 		if (amdgpu_vcnfw_log)
 			amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 	}
 
-	if (!unifiedQ_enabled) {
-		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
-			adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
-	}
+	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
+		adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
+
 	return 0;
 }
 
@@ -220,19 +151,19 @@ static int vcn_v4_0_sw_fini(void *handle)
 	int i, r, idx;
 
 	if (drm_dev_enter(&adev->ddev, &idx)) {
-                for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-                        volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+			volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 
-                        if (adev->vcn.harvest_config & (1 << i))
-                                continue;
+			if (adev->vcn.harvest_config & (1 << i))
+				continue;
 
-                        fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-                        fw_shared->present_flag_0 = 0;
-                        fw_shared->sq.is_enabled = 0;
-                }
+			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+			fw_shared->present_flag_0 = 0;
+			fw_shared->sq.is_enabled = 0;
+		}
 
-                drm_dev_exit(idx);
-        }
+		drm_dev_exit(idx);
+	}
 
 	r = amdgpu_vcn_suspend(adev);
 	if (r)
@@ -254,15 +185,13 @@ static int vcn_v4_0_hw_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_ring *ring;
-	int i, j, r;
+	int i, r;
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
-		if (unifiedQ_enabled)
-			ring = &adev->vcn.inst[i].ring_enc[0];
-		else
-			ring = &adev->vcn.inst[i].ring_dec;
+
+		ring = &adev->vcn.inst[i].ring_enc[0];
 
 		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 				((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
@@ -270,13 +199,6 @@ static int vcn_v4_0_hw_init(void *handle)
 		r = amdgpu_ring_test_helper(ring);
 		if (r)
 			goto done;
-
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			ring = &adev->vcn.inst[i].ring_enc[j];
-			r = amdgpu_ring_test_helper(ring);
-			if (r)
-				goto done;
-		}
 	}
 
 done:
@@ -464,7 +386,6 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
 		WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
-
 	}
 
 	if (!indirect)
@@ -888,7 +809,6 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 	struct amdgpu_ring *ring;
 	uint32_t tmp;
-	int i;
 
 	/* disable register anti-hang mechanism */
 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
@@ -974,74 +894,32 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 			(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 				(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 
-	if (unifiedQ_enabled) {
-		ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
-	} else
-		ring = &adev->vcn.inst[inst_idx].ring_dec;
-
-	WREG32_SOC15(VCN, inst_idx, regVCN_RB4_DB_CTRL,
-		ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT |
-		VCN_RB4_DB_CTRL__EN_MASK);
-
-	/* program the RB_BASE for ring buffer */
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO4,
-		lower_32_bits(ring->gpu_addr));
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI4,
-		upper_32_bits(ring->gpu_addr));
+	ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
 
-	/* reseting ring, fw should not check RB ring */
 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
-	tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
+	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
 
-	/* Initialize the ring buffer's read and write pointers */
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR4);
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4, tmp);
-	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
+	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
+	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
+	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 
 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
-	tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
+	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 
-	WREG32_SOC15(VCN, inst_idx, regUVD_SCRATCH2, 0);
-
-	if (unifiedQ_enabled)
-		fw_shared->sq.queue_mode &= ~FW_QUEUE_RING_RESET;
-
-	for (i = 0; i < adev->vcn.num_enc_rings; i++) {
-		ring = &adev->vcn.inst[inst_idx].ring_enc[i];
-
-		if (i) {
-			ring = &adev->vcn.inst[inst_idx].ring_enc[1];
-
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO2, ring->gpu_addr);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE2, ring->ring_size / 4);
-			tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR2);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2, tmp);
-			ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2);
-
-			WREG32_SOC15(VCN, inst_idx, regVCN_RB2_DB_CTRL,
-				ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB2_DB_CTRL__EN_MASK);
-		} else {
-			ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
-			tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
-			WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
-			ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
+	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
+			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+			VCN_RB1_DB_CTRL__EN_MASK);
 
-			WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
-				ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB1_DB_CTRL__EN_MASK);
-		}
-	}
 	return 0;
 }
 
@@ -1064,6 +942,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		amdgpu_dpm_enable_uvd(adev, true);
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+
 		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 			r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 			continue;
@@ -1081,15 +961,15 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 
 		/* enable VCPU clock */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+				UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 
 		/* disable master interrupt */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
-			~UVD_MASTINT_EN__VCPU_EN_MASK);
+				~UVD_MASTINT_EN__VCPU_EN_MASK);
 
 		/* enable LMI MC and UMC channels */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+				~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 
 		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
 		tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
@@ -1099,10 +979,10 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		/* setup regUVD_LMI_CTRL */
 		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
 		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
-		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
-		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+				UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+				UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+				UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+				UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 
 		/* setup regUVD_MPC_CNTL */
 		tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
@@ -1112,37 +992,37 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 
 		/* setup UVD_MPC_SET_MUXA0 */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
-			((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
-			(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
-			(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+				((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+				 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+				 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 
 		/* setup UVD_MPC_SET_MUXB0 */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
-			((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
-			(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
-			(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+				((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+				 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+				 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 
 		/* setup UVD_MPC_SET_MUX */
 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
-			((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
-			(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
-			(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+				((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+				 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+				 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 
 		vcn_v4_0_mc_resume(adev, i);
 
 		/* VCN global tiling registers */
 		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
-			adev->gfx.config.gb_addr_config);
+				adev->gfx.config.gb_addr_config);
 
 		/* unblock VCPU register access */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
 
 		/* release VCPU reset to boot */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
-			~UVD_VCPU_CNTL__BLK_RST_MASK);
+				~UVD_VCPU_CNTL__BLK_RST_MASK);
 
 		for (j = 0; j < 10; ++j) {
 			uint32_t status;
@@ -1166,13 +1046,13 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 				if (status & 2)
 					break;
 
-				dev_err(adev->dev, "VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
-					WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
-					UVD_VCPU_CNTL__BLK_RST_MASK,
-					~UVD_VCPU_CNTL__BLK_RST_MASK);
+				dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
+				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
+							UVD_VCPU_CNTL__BLK_RST_MASK,
+							~UVD_VCPU_CNTL__BLK_RST_MASK);
 				mdelay(10);
 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
-					~UVD_VCPU_CNTL__BLK_RST_MASK);
+						~UVD_VCPU_CNTL__BLK_RST_MASK);
 
 				mdelay(10);
 				r = -1;
@@ -1180,78 +1060,43 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
 		}
 
 		if (r) {
-			dev_err(adev->dev, "VCN[%d] decode not responding, giving up!!!\n", i);
+			dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
 			return r;
 		}
 
 		/* enable master interrupt */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
-			UVD_MASTINT_EN__VCPU_EN_MASK,
-			~UVD_MASTINT_EN__VCPU_EN_MASK);
+				UVD_MASTINT_EN__VCPU_EN_MASK,
+				~UVD_MASTINT_EN__VCPU_EN_MASK);
 
 		/* clear the busy bit of VCN_STATUS */
 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
-			~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
-
-		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
-		if (unifiedQ_enabled) {
-			ring = &adev->vcn.inst[i].ring_enc[0];
-			fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
-		} else {
-			ring = &adev->vcn.inst[i].ring_dec;
+				~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 
-			WREG32_SOC15(VCN, i, regVCN_RB4_DB_CTRL,
-				ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB4_DB_CTRL__EN_MASK);
-
-			/* program the RB_BASE for ring buffer */
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO4,
-				lower_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI4,
-				upper_32_bits(ring->gpu_addr));
-
-			WREG32_SOC15(VCN, i, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
-
-			/* resetting ring, fw should not check RB ring */
-			tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
-			tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
-			WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		ring = &adev->vcn.inst[i].ring_enc[0];
+		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
+				ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+				VCN_RB1_DB_CTRL__EN_MASK);
 
-			/* Initialize the ring buffer's read and write pointers */
-			tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4);
-			WREG32_SOC15(VCN, i, regUVD_RB_WPTR4, tmp);
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR4);
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
 
-			tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
-			tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
-			WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+		tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
+		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
 
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_RPTR4);
-		}
-		ring = &adev->vcn.inst[i].ring_enc[0];
-		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
-			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
-			VCN_RB1_DB_CTRL__EN_MASK);
 		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
 		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
 		ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-		if (unifiedQ_enabled)
-			fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
-		else {
-			ring = &adev->vcn.inst[i].ring_enc[1];
-			WREG32_SOC15(VCN, i, regVCN_RB2_DB_CTRL,
-				ring->doorbell_index << VCN_RB2_DB_CTRL__OFFSET__SHIFT |
-				VCN_RB2_DB_CTRL__EN_MASK);
-			tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR2);
-			WREG32_SOC15(VCN, i, regUVD_RB_WPTR2, tmp);
-			ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR2);
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO2, ring->gpu_addr);
-			WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-			WREG32_SOC15(VCN, i, regUVD_RB_SIZE2, ring->ring_size / 4);
-		}
+
+		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
+		fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 	}
 
 	return 0;
@@ -1277,12 +1122,6 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
 	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
 
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR2);
-	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
-
-	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
-	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR4, tmp, 0xFFFFFFFF);
-
 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 
@@ -1301,10 +1140,14 @@ static int vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
  */
 static int vcn_v4_0_stop(struct amdgpu_device *adev)
 {
+	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 	uint32_t tmp;
 	int i, r = 0;
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+		fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+
 		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 			r = vcn_v4_0_stop_dpg_mode(adev, i);
 			continue;
@@ -1414,8 +1257,6 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
 			/* unpause dpg, no need to wait */
 			reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
 			WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
-			SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
-				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 		}
 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
 	}
@@ -1424,165 +1265,72 @@ static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
 }
 
 /**
- * vcn_v4_0_dec_ring_get_rptr - get read pointer
+ * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Returns the current hardware read pointer
+ * Returns the current hardware unified read pointer
  */
-static uint64_t vcn_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR4);
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
+
+	return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
 }
 
 /**
- * vcn_v4_0_dec_ring_get_wptr - get write pointer
+ * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Returns the current hardware write pointer
+ * Returns the current hardware unified write pointer
  */
-static uint64_t vcn_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
+
 	if (ring->use_doorbell)
 		return *ring->wptr_cpu_addr;
 	else
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4);
+		return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
 }
 
 /**
- * vcn_v4_0_dec_ring_set_wptr - set write pointer
+ * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
  *
  * @ring: amdgpu_ring pointer
  *
- * Commits the write pointer to the hardware
+ * Commits the enc write pointer to the hardware
  */
-static void vcn_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
+static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
-		WREG32_SOC15(VCN, ring->me, regUVD_SCRATCH2,
-			lower_32_bits(ring->wptr));
-	}
+	if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
+		DRM_ERROR("wrong ring id is identified in %s", __func__);
 
 	if (ring->use_doorbell) {
 		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 	} else {
-		WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4, lower_32_bits(ring->wptr));
-	}
-}
-
-static const struct amdgpu_ring_funcs vcn_v4_0_dec_sw_ring_vm_funcs = {
-	.type = AMDGPU_RING_TYPE_VCN_DEC,
-	.align_mask = 0x3f,
-	.nop = VCN_DEC_SW_CMD_NO_OP,
-	.vmhub = AMDGPU_MMHUB_0,
-	.get_rptr = vcn_v4_0_dec_ring_get_rptr,
-	.get_wptr = vcn_v4_0_dec_ring_get_wptr,
-	.set_wptr = vcn_v4_0_dec_ring_set_wptr,
-	.emit_frame_size =
-		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
-		VCN_SW_RING_EMIT_FRAME_SIZE,
-	.emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */
-	.emit_ib = vcn_dec_sw_ring_emit_ib,
-	.emit_fence = vcn_dec_sw_ring_emit_fence,
-	.emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush,
-	.test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
-	.test_ib = amdgpu_vcn_dec_sw_ring_test_ib,
-	.insert_nop = amdgpu_ring_insert_nop,
-	.insert_end = vcn_dec_sw_ring_insert_end,
-	.pad_ib = amdgpu_ring_generic_pad_ib,
-	.begin_use = amdgpu_vcn_ring_begin_use,
-	.end_use = amdgpu_vcn_ring_end_use,
-	.emit_wreg = vcn_dec_sw_ring_emit_wreg,
-	.emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
-	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
-};
-
-/**
- * vcn_v4_0_enc_ring_get_rptr - get enc read pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Returns the current hardware enc read pointer
- */
-static uint64_t vcn_v4_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
-	else
-		return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR2);
-}
-
-/**
- * vcn_v4_0_enc_ring_get_wptr - get enc write pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Returns the current hardware enc write pointer
- */
-static uint64_t vcn_v4_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
-		if (ring->use_doorbell)
-			return *ring->wptr_cpu_addr;
-		else
-			return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
-	} else {
-		if (ring->use_doorbell)
-			return *ring->wptr_cpu_addr;
-		else
-			return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2);
-	}
-}
-
-/**
- * vcn_v4_0_enc_ring_set_wptr - set enc write pointer
- *
- * @ring: amdgpu_ring pointer
- *
- * Commits the enc write pointer to the hardware
- */
-static void vcn_v4_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
-		if (ring->use_doorbell) {
-			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
-			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
-		} else {
-			WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
-		}
-	} else {
-		if (ring->use_doorbell) {
-			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
-			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
-		} else {
-			WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-		}
+		WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
 	}
 }
 
-static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
+static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
 	.type = AMDGPU_RING_TYPE_VCN_ENC,
 	.align_mask = 0x3f,
 	.nop = VCN_ENC_CMD_NO_OP,
 	.vmhub = AMDGPU_MMHUB_0,
-	.get_rptr = vcn_v4_0_enc_ring_get_rptr,
-	.get_wptr = vcn_v4_0_enc_ring_get_wptr,
-	.set_wptr = vcn_v4_0_enc_ring_set_wptr,
+	.get_rptr = vcn_v4_0_unified_ring_get_rptr,
+	.get_wptr = vcn_v4_0_unified_ring_get_wptr,
+	.set_wptr = vcn_v4_0_unified_ring_set_wptr,
 	.emit_frame_size =
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
@@ -1594,7 +1342,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
 	.emit_fence = vcn_v2_0_enc_ring_emit_fence,
 	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
 	.test_ring = amdgpu_vcn_enc_ring_test_ring,
-	.test_ib = amdgpu_vcn_enc_ring_test_ib,
+	.test_ib = amdgpu_vcn_unified_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.insert_end = vcn_v2_0_enc_ring_insert_end,
 	.pad_ib = amdgpu_ring_generic_pad_ib,
@@ -1606,13 +1354,13 @@ static const struct amdgpu_ring_funcs vcn_v4_0_enc_ring_vm_funcs = {
 };
 
 /**
- * vcn_v4_0_set_dec_ring_funcs - set dec ring functions
+ * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
  *
  * @adev: amdgpu_device pointer
  *
- * Set decode ring functions
+ * Set unified ring functions
  */
-static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
 {
 	int i;
 
@@ -1620,32 +1368,10 @@ static void vcn_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
 
-		adev->vcn.inst[i].ring_dec.funcs = &vcn_v4_0_dec_sw_ring_vm_funcs;
-		adev->vcn.inst[i].ring_dec.me = i;
-		DRM_INFO("VCN(%d) decode software ring is enabled in VM mode\n", i);
-	}
-}
-
-/**
- * vcn_v4_0_set_enc_ring_funcs - set enc ring functions
- *
- * @adev: amdgpu_device pointer
- *
- * Set encode ring functions
- */
-static void vcn_v4_0_set_enc_ring_funcs(struct amdgpu_device *adev)
-{
-	int i, j;
-
-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
-		if (adev->vcn.harvest_config & (1 << i))
-			continue;
+		adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs;
+		adev->vcn.inst[i].ring_enc[0].me = i;
 
-		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-			adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v4_0_enc_ring_vm_funcs;
-			adev->vcn.inst[i].ring_enc[j].me = i;
-		}
-		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
+		DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
 	}
 }
 
@@ -1798,18 +1524,9 @@ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_
 	DRM_DEBUG("IH: VCN TRAP\n");
 
 	switch (entry->src_id) {
-	case VCN_4_0__SRCID__UVD_TRAP:
-		if (!unifiedQ_enabled) {
-			amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
-			break;
-		}
-		break;
 	case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
 		break;
-	case VCN_4_0__SRCID__UVD_ENC_LOW_LATENCY:
-		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
-		break;
 	default:
 		DRM_ERROR("Unhandled interrupt: %d %d\n",
 			  entry->src_id, entry->src_data[0]);
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
index 8cc0a76ddf9f..93bd4eda0d94 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -25,3 +25,17 @@ config HSA_AMD_SVM
 	  preemptions and one based on page faults. To enable page fault
 	  based memory management on most GFXv9 GPUs, set the module
 	  parameter amdgpu.noretry=0.
+
+config HSA_AMD_P2P
+	bool "HSA kernel driver support for peer-to-peer for AMD GPU devices"
+	depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY
+	help
+	  Enable peer-to-peer (P2P) communication between AMD GPUs over
+	  the PCIe bus. This can improve performance of multi-GPU compute
+	  applications and libraries by enabling GPUs to access data directly
+	  in peer GPUs' memory without intermediate copies in system memory.
+
+	  This P2P feature is only enabled on compatible chipsets, and between
+	  GPUs with large memory BARs that expose the entire VRAM in PCIe bus
+	  address space within the physical address limits of the GPUs.
+
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 1c7016958d6d..3bcf9bf29acb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -65,6 +65,25 @@ static int kfd_char_dev_major = -1;
 static struct class *kfd_class;
 struct device *kfd_device;
 
+static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
+{
+	struct kfd_process_device *pdd;
+
+	mutex_lock(&p->mutex);
+	pdd = kfd_process_device_data_by_id(p, gpu_id);
+
+	if (pdd)
+		return pdd;
+
+	mutex_unlock(&p->mutex);
+	return NULL;
+}
+
+static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
+{
+	mutex_unlock(&pdd->process->mutex);
+}
+
 int kfd_chardev_init(void)
 {
 	int err = 0;
@@ -958,6 +977,19 @@ bool kfd_dev_is_large_bar(struct kfd_dev *dev)
 	return false;
 }
 
+static int kfd_ioctl_get_available_memory(struct file *filep,
+					  struct kfd_process *p, void *data)
+{
+	struct kfd_ioctl_get_available_memory_args *args = data;
+	struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
+
+	if (!pdd)
+		return -EINVAL;
+	args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev);
+	kfd_unlock_pdd(pdd);
+	return 0;
+}
+
 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
 					struct kfd_process *p, void *data)
 {
@@ -2648,6 +2680,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
 			kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
 
+	AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
+			kfd_ioctl_get_available_memory, 0),
 };
 
 #define AMDKFD_CORE_IOCTL_COUNT	ARRAY_SIZE(amdkfd_ioctls)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index cbfb32b3d235..a5409531a2fd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1040,7 +1040,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
 			props->rec_transfer_size =
 					iolink->recommended_transfer_size;
 
-			dev->io_link_count++;
 			dev->node_props.io_links_count++;
 			list_add_tail(&props->list, &dev->io_link_props);
 			break;
@@ -1067,7 +1066,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
 		props2->node_from = id_to;
 		props2->node_to = id_from;
 		props2->kobj = NULL;
-		to_dev->io_link_count++;
 		to_dev->node_props.io_links_count++;
 		list_add_tail(&props2->list, &to_dev->io_link_props);
 	}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index bf4200457772..c8fee0dbfdcb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -75,7 +75,6 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
 	case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
 	case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
 	case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
-	case IP_VERSION(6, 0, 1):
 		kfd->device_info.num_sdma_queues_per_engine = 2;
 		break;
 	case IP_VERSION(4, 2, 0):/* VEGA20 */
@@ -90,6 +89,7 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
 	case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
 	case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
 	case IP_VERSION(6, 0, 0):
+	case IP_VERSION(6, 0, 1):
 	case IP_VERSION(6, 0, 2):
 		kfd->device_info.num_sdma_queues_per_engine = 8;
 		break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e1797657b04c..213246a5b4e4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -811,7 +811,6 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,
 	struct mqd_manager *mqd_mgr;
 	struct kfd_process_device *pdd;
 	bool prev_active = false;
-	bool add_queue = false;
 
 	dqm_lock(dqm);
 	pdd = kfd_get_process_device_data(q->device, q->process);
@@ -887,7 +886,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,
 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
 		if (!dqm->dev->shared_resources.enable_mes)
 			retval = map_queues_cpsch(dqm);
-		else if (add_queue)
+		else if (q->properties.is_active)
 			retval = add_queue_mes(dqm, q, &pdd->qpd);
 	} else if (q->properties.is_active &&
 		 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
@@ -1873,6 +1872,22 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	}
 
+	if (q->properties.is_active) {
+		if (!dqm->dev->shared_resources.enable_mes) {
+			retval = execute_queues_cpsch(dqm,
+						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+			if (retval == -ETIME)
+				qpd->reset_wavefronts = true;
+		} else {
+			retval = remove_queue_mes(dqm, q, qpd);
+		}
+
+		if (retval)
+			goto failed_unmap_queue;
+
+		decrement_queue_count(dqm, qpd, q);
+	}
+
 	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
 			q->properties.type)];
 
@@ -1886,17 +1901,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	list_del(&q->list);
 	qpd->queue_count--;
-	if (q->properties.is_active) {
-		if (!dqm->dev->shared_resources.enable_mes) {
-			decrement_queue_count(dqm, qpd, q);
-			retval = execute_queues_cpsch(dqm,
-						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
-			if (retval == -ETIME)
-				qpd->reset_wavefronts = true;
-		} else {
-			retval = remove_queue_mes(dqm, q, qpd);
-		}
-	}
 
 	/*
 	 * Unconditionally decrement this counter, regardless of the queue's
@@ -1913,6 +1917,7 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
 
 	return retval;
 
+failed_unmap_queue:
 failed_try_destroy_debugged_queue:
 
 	dqm_unlock(dqm);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 4df9c36146ba..3942a56c28bb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -377,8 +377,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset)
 		return -EINVAL;
 	}
 
-	err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->adev,
-					mem, &kern_addr, &size);
+	err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(mem, &kern_addr, &size);
 	if (err) {
 		pr_err("Failed to map event page to kernel\n");
 		return err;
@@ -387,7 +386,7 @@ int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset)
 	err = kfd_event_page_set(p, kern_addr, size, event_page_offset);
 	if (err) {
 		pr_err("Failed to set event page\n");
-		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kfd->adev, mem);
+		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 		return err;
 	}
 	return err;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index e44376c2ecdc..f73e3e340413 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -671,13 +671,15 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
 	migrate.vma = vma;
 	migrate.start = start;
 	migrate.end = end;
-	migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
 	migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev);
+	if (adev->gmc.xgmi.connected_to_cpu)
+		migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT;
+	else
+		migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
 
 	buf = kvcalloc(npages,
 		       2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t),
 		       GFP_KERNEL);
-
 	if (!buf)
 		goto out;
 
@@ -947,7 +949,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
 {
 	struct kfd_dev *kfddev = adev->kfd.dev;
 	struct dev_pagemap *pgmap;
-	struct resource *res;
+	struct resource *res = NULL;
 	unsigned long size;
 	void *r;
 
@@ -962,28 +964,34 @@ int svm_migrate_init(struct amdgpu_device *adev)
 	 * should remove reserved size
 	 */
 	size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20);
-	res = devm_request_free_mem_region(adev->dev, &iomem_resource, size);
-	if (IS_ERR(res))
-		return -ENOMEM;
+	if (adev->gmc.xgmi.connected_to_cpu) {
+		pgmap->range.start = adev->gmc.aper_base;
+		pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1;
+		pgmap->type = MEMORY_DEVICE_COHERENT;
+	} else {
+		res = devm_request_free_mem_region(adev->dev, &iomem_resource, size);
+		if (IS_ERR(res))
+			return -ENOMEM;
+		pgmap->range.start = res->start;
+		pgmap->range.end = res->end;
+		pgmap->type = MEMORY_DEVICE_PRIVATE;
+	}
 
-	pgmap->type = MEMORY_DEVICE_PRIVATE;
 	pgmap->nr_range = 1;
-	pgmap->range.start = res->start;
-	pgmap->range.end = res->end;
 	pgmap->ops = &svm_migrate_pgmap_ops;
 	pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev);
-	pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
-
+	pgmap->flags = 0;
 	/* Device manager releases device-specific resources, memory region and
 	 * pgmap when driver disconnects from device.
 	 */
 	r = devm_memremap_pages(adev->dev, pgmap);
 	if (IS_ERR(r)) {
 		pr_err("failed to register HMM device memory\n");
-
 		/* Disable SVM support capability */
 		pgmap->type = 0;
-		devm_release_mem_region(adev->dev, res->start, resource_size(res));
+		if (pgmap->type == MEMORY_DEVICE_PRIVATE)
+			devm_release_mem_region(adev->dev, res->start,
+						res->end - res->start + 1);
 		return PTR_ERR(r);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index e3d64ec8c353..a13e60d48b73 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -693,7 +693,7 @@ static void kfd_process_free_gpuvm(struct kgd_mem *mem,
 	struct kfd_dev *dev = pdd->dev;
 
 	if (kptr) {
-		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(dev->adev, mem);
+		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 		kptr = NULL;
 	}
 
@@ -733,7 +733,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd,
 	}
 
 	if (kptr) {
-		err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kdev->adev,
+		err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(
 				(struct kgd_mem *)*mem, kptr, NULL);
 		if (err) {
 			pr_debug("Map GTT BO to kernel failed\n");
@@ -999,7 +999,7 @@ static void kfd_process_kunmap_signal_bo(struct kfd_process *p)
 	if (!mem)
 		goto out;
 
-	amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kdev->adev, mem);
+	amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
 
 out:
 	mutex_unlock(&p->mutex);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index dc00484ff484..99f2a6412201 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -419,7 +419,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 	}
 
 	if (pqn->q) {
-		kfd_procfs_del_queue(pqn->q);
 		dqm = pqn->q->device->dqm;
 		retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
 		if (retval) {
@@ -439,6 +438,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
 		if (dev->shared_resources.enable_mes)
 			amdgpu_amdkfd_free_gtt_mem(dev->adev,
 						   pqn->q->gang_ctx_bo);
+		kfd_procfs_del_queue(pqn->q);
 		uninit_queue(pqn->q);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 8d50d207cf66..25990bec600d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -40,6 +40,7 @@
 #include "kfd_svm.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ras.h"
+#include "amdgpu.h"
 
 /* topology_device_list - Master list of all topology devices */
 static struct list_head topology_device_list;
@@ -148,6 +149,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev)
 	struct kfd_mem_properties *mem;
 	struct kfd_cache_properties *cache;
 	struct kfd_iolink_properties *iolink;
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_perf_properties *perf;
 
 	list_del(&dev->list);
@@ -173,6 +175,13 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev)
 		kfree(iolink);
 	}
 
+	while (dev->p2p_link_props.next != &dev->p2p_link_props) {
+		p2plink = container_of(dev->p2p_link_props.next,
+				struct kfd_iolink_properties, list);
+		list_del(&p2plink->list);
+		kfree(p2plink);
+	}
+
 	while (dev->perf_props.next != &dev->perf_props) {
 		perf = container_of(dev->perf_props.next,
 				struct kfd_perf_properties, list);
@@ -214,6 +223,7 @@ struct kfd_topology_device *kfd_create_topology_device(
 	INIT_LIST_HEAD(&dev->mem_props);
 	INIT_LIST_HEAD(&dev->cache_props);
 	INIT_LIST_HEAD(&dev->io_link_props);
+	INIT_LIST_HEAD(&dev->p2p_link_props);
 	INIT_LIST_HEAD(&dev->perf_props);
 
 	list_add_tail(&dev->list, device_list);
@@ -465,6 +475,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
 			      dev->node_props.caches_count);
 	sysfs_show_32bit_prop(buffer, offs, "io_links_count",
 			      dev->node_props.io_links_count);
+	sysfs_show_32bit_prop(buffer, offs, "p2p_links_count",
+			      dev->node_props.p2p_links_count);
 	sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base",
 			      dev->node_props.cpu_core_id_base);
 	sysfs_show_32bit_prop(buffer, offs, "simd_id_base",
@@ -568,6 +580,7 @@ static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr)
 
 static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 {
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_iolink_properties *iolink;
 	struct kfd_cache_properties *cache;
 	struct kfd_mem_properties *mem;
@@ -585,6 +598,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 		dev->kobj_iolink = NULL;
 	}
 
+	if (dev->kobj_p2plink) {
+		list_for_each_entry(p2plink, &dev->p2p_link_props, list)
+			if (p2plink->kobj) {
+				kfd_remove_sysfs_file(p2plink->kobj,
+							&p2plink->attr);
+				p2plink->kobj = NULL;
+			}
+		kobject_del(dev->kobj_p2plink);
+		kobject_put(dev->kobj_p2plink);
+		dev->kobj_p2plink = NULL;
+	}
+
 	if (dev->kobj_cache) {
 		list_for_each_entry(cache, &dev->cache_props, list)
 			if (cache->kobj) {
@@ -631,6 +656,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
 static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 		uint32_t id)
 {
+	struct kfd_iolink_properties *p2plink;
 	struct kfd_iolink_properties *iolink;
 	struct kfd_cache_properties *cache;
 	struct kfd_mem_properties *mem;
@@ -668,6 +694,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 	if (!dev->kobj_iolink)
 		return -ENOMEM;
 
+	dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node);
+	if (!dev->kobj_p2plink)
+		return -ENOMEM;
+
 	dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
 	if (!dev->kobj_perf)
 		return -ENOMEM;
@@ -757,6 +787,27 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
 		i++;
 	}
 
+	i = 0;
+	list_for_each_entry(p2plink, &dev->p2p_link_props, list) {
+		p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
+		if (!p2plink->kobj)
+			return -ENOMEM;
+		ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
+				dev->kobj_p2plink, "%d", i);
+		if (ret < 0) {
+			kobject_put(p2plink->kobj);
+			return ret;
+		}
+
+		p2plink->attr.name = "properties";
+		p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
+		sysfs_attr_init(&iolink->attr);
+		ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
+		if (ret < 0)
+			return ret;
+		i++;
+	}
+
 	/* All hardware blocks have the same number of attributes. */
 	num_attrs = ARRAY_SIZE(perf_attr_iommu);
 	list_for_each_entry(perf, &dev->perf_props, list) {
@@ -1145,6 +1196,7 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
 	struct kfd_mem_properties *mem;
 	struct kfd_cache_properties *cache;
 	struct kfd_iolink_properties *iolink;
+	struct kfd_iolink_properties *p2plink;
 
 	down_write(&topology_lock);
 	list_for_each_entry(dev, &topology_device_list, list) {
@@ -1165,6 +1217,8 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
 				cache->gpu = dev->gpu;
 			list_for_each_entry(iolink, &dev->io_link_props, list)
 				iolink->gpu = dev->gpu;
+			list_for_each_entry(p2plink, &dev->p2p_link_props, list)
+				p2plink->gpu = dev->gpu;
 			break;
 		}
 	}
@@ -1287,6 +1341,253 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
 			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
 		}
 	}
+
+	/* Create indirect links so apply flags setting to all */
+	list_for_each_entry(link, &dev->p2p_link_props, list) {
+		link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+		kfd_set_iolink_no_atomics(dev, NULL, link);
+		peer_dev = kfd_topology_device_by_proximity_domain(
+				link->node_to);
+
+		if (!peer_dev)
+			continue;
+
+		list_for_each_entry(inbound_link, &peer_dev->p2p_link_props,
+									list) {
+			if (inbound_link->node_to != link->node_from)
+				continue;
+
+			inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
+			kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
+			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
+		}
+	}
+}
+
+static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev,
+				struct kfd_iolink_properties *p2plink)
+{
+	int ret;
+
+	p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
+	if (!p2plink->kobj)
+		return -ENOMEM;
+
+	ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
+			dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1);
+	if (ret < 0) {
+		kobject_put(p2plink->kobj);
+		return ret;
+	}
+
+	p2plink->attr.name = "properties";
+	p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
+	sysfs_attr_init(&p2plink->attr);
+	ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node)
+{
+	struct kfd_iolink_properties *props = NULL, *props2 = NULL;
+	struct kfd_iolink_properties *gpu_link, *cpu_link;
+	struct kfd_topology_device *cpu_dev;
+	int ret = 0;
+	int i, num_cpu;
+
+	num_cpu = 0;
+	list_for_each_entry(cpu_dev, &topology_device_list, list) {
+		if (cpu_dev->gpu)
+			break;
+		num_cpu++;
+	}
+
+	gpu_link = list_first_entry(&kdev->io_link_props,
+					struct kfd_iolink_properties, list);
+	if (!gpu_link)
+		return -ENOMEM;
+
+	for (i = 0; i < num_cpu; i++) {
+		/* CPU <--> GPU */
+		if (gpu_link->node_to == i)
+			continue;
+
+		/* find CPU <-->  CPU links */
+		cpu_dev = kfd_topology_device_by_proximity_domain(i);
+		if (cpu_dev) {
+			list_for_each_entry(cpu_link,
+					&cpu_dev->io_link_props, list) {
+				if (cpu_link->node_to == gpu_link->node_to)
+					break;
+			}
+		}
+
+		if (cpu_link->node_to != gpu_link->node_to)
+			return -ENOMEM;
+
+		/* CPU <--> CPU <--> GPU, GPU node*/
+		props = kfd_alloc_struct(props);
+		if (!props)
+			return -ENOMEM;
+
+		memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties));
+		props->weight = gpu_link->weight + cpu_link->weight;
+		props->min_latency = gpu_link->min_latency + cpu_link->min_latency;
+		props->max_latency = gpu_link->max_latency + cpu_link->max_latency;
+		props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth);
+		props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth);
+
+		props->node_from = gpu_node;
+		props->node_to = i;
+		kdev->node_props.p2p_links_count++;
+		list_add_tail(&props->list, &kdev->p2p_link_props);
+		ret = kfd_build_p2p_node_entry(kdev, props);
+		if (ret < 0)
+			return ret;
+
+		/* for small Bar, no CPU --> GPU in-direct links */
+		if (kfd_dev_is_large_bar(kdev->gpu)) {
+			/* CPU <--> CPU <--> GPU, CPU node*/
+			props2 = kfd_alloc_struct(props2);
+			if (!props2)
+				return -ENOMEM;
+
+			memcpy(props2, props, sizeof(struct kfd_iolink_properties));
+			props2->node_from = i;
+			props2->node_to = gpu_node;
+			props2->kobj = NULL;
+			cpu_dev->node_props.p2p_links_count++;
+			list_add_tail(&props2->list, &cpu_dev->p2p_link_props);
+			ret = kfd_build_p2p_node_entry(cpu_dev, props2);
+			if (ret < 0)
+				return ret;
+		}
+	}
+	return ret;
+}
+
+#if defined(CONFIG_HSA_AMD_P2P)
+static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
+		struct kfd_topology_device *peer, int from, int to)
+{
+	struct kfd_iolink_properties *props = NULL;
+	struct kfd_iolink_properties *iolink1, *iolink2, *iolink3;
+	struct kfd_topology_device *cpu_dev;
+	int ret = 0;
+
+	if (!amdgpu_device_is_peer_accessible(
+				kdev->gpu->adev,
+				peer->gpu->adev))
+		return ret;
+
+	iolink1 = list_first_entry(&kdev->io_link_props,
+							struct kfd_iolink_properties, list);
+	if (!iolink1)
+		return -ENOMEM;
+
+	iolink2 = list_first_entry(&peer->io_link_props,
+							struct kfd_iolink_properties, list);
+	if (!iolink2)
+		return -ENOMEM;
+
+	props = kfd_alloc_struct(props);
+	if (!props)
+		return -ENOMEM;
+
+	memcpy(props, iolink1, sizeof(struct kfd_iolink_properties));
+
+	props->weight = iolink1->weight + iolink2->weight;
+	props->min_latency = iolink1->min_latency + iolink2->min_latency;
+	props->max_latency = iolink1->max_latency + iolink2->max_latency;
+	props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth);
+	props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth);
+
+	if (iolink1->node_to != iolink2->node_to) {
+		/* CPU->CPU  link*/
+		cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to);
+		if (cpu_dev) {
+			list_for_each_entry(iolink3, &cpu_dev->io_link_props, list)
+				if (iolink3->node_to == iolink2->node_to)
+					break;
+
+			props->weight += iolink3->weight;
+			props->min_latency += iolink3->min_latency;
+			props->max_latency += iolink3->max_latency;
+			props->min_bandwidth = min(props->min_bandwidth,
+							iolink3->min_bandwidth);
+			props->max_bandwidth = min(props->max_bandwidth,
+							iolink3->max_bandwidth);
+		} else {
+			WARN(1, "CPU node not found");
+		}
+	}
+
+	props->node_from = from;
+	props->node_to = to;
+	peer->node_props.p2p_links_count++;
+	list_add_tail(&props->list, &peer->p2p_link_props);
+	ret = kfd_build_p2p_node_entry(peer, props);
+
+	return ret;
+}
+#endif
+
+static int kfd_dev_create_p2p_links(void)
+{
+	struct kfd_topology_device *dev;
+	struct kfd_topology_device *new_dev;
+#if defined(CONFIG_HSA_AMD_P2P)
+	uint32_t i;
+#endif
+	uint32_t k;
+	int ret = 0;
+
+	k = 0;
+	list_for_each_entry(dev, &topology_device_list, list)
+		k++;
+	if (k < 2)
+		return 0;
+
+	new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list);
+	if (WARN_ON(!new_dev->gpu))
+		return 0;
+
+	k--;
+
+	/* create in-direct links */
+	ret = kfd_create_indirect_link_prop(new_dev, k);
+	if (ret < 0)
+		goto out;
+
+	/* create p2p links */
+#if defined(CONFIG_HSA_AMD_P2P)
+	i = 0;
+	list_for_each_entry(dev, &topology_device_list, list) {
+		if (dev == new_dev)
+			break;
+		if (!dev->gpu || !dev->gpu->adev ||
+		    (dev->gpu->hive_id &&
+		     dev->gpu->hive_id == new_dev->gpu->hive_id))
+			goto next;
+
+		/* check if node(s) is/are peer accessible in one direction or bi-direction */
+		ret = kfd_add_peer_prop(new_dev, dev, i, k);
+		if (ret < 0)
+			goto out;
+
+		ret = kfd_add_peer_prop(dev, new_dev, k, i);
+		if (ret < 0)
+			goto out;
+next:
+		i++;
+	}
+#endif
+
+out:
+	return ret;
 }
 
 int kfd_topology_add_device(struct kfd_dev *gpu)
@@ -1305,7 +1606,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	INIT_LIST_HEAD(&temp_topology_device_list);
 
 	gpu_id = kfd_generate_gpu_id(gpu);
-
 	pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);
 
 	/* Check to see if this gpu device exists in the topology_device_list.
@@ -1362,6 +1662,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	dev->gpu_id = gpu_id;
 	gpu->id = gpu_id;
 
+	kfd_dev_create_p2p_links();
+
 	/* TODO: Move the following lines to function
 	 *	kfd_add_non_crat_information
 	 */
@@ -1507,7 +1809,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 static void kfd_topology_update_io_links(int proximity_domain)
 {
 	struct kfd_topology_device *dev;
-	struct kfd_iolink_properties *iolink, *tmp;
+	struct kfd_iolink_properties *iolink, *p2plink, *tmp;
 
 	list_for_each_entry(dev, &topology_device_list, list) {
 		if (dev->proximity_domain > proximity_domain)
@@ -1520,7 +1822,6 @@ static void kfd_topology_update_io_links(int proximity_domain)
 			 */
 			if (iolink->node_to == proximity_domain) {
 				list_del(&iolink->list);
-				dev->io_link_count--;
 				dev->node_props.io_links_count--;
 			} else {
 				if (iolink->node_from > proximity_domain)
@@ -1529,6 +1830,22 @@ static void kfd_topology_update_io_links(int proximity_domain)
 					iolink->node_to--;
 			}
 		}
+
+		list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
+			/*
+			 * If there is a p2p link to the dev being deleted
+			 * then remove that p2p link also.
+			 */
+			if (p2plink->node_to == proximity_domain) {
+				list_del(&p2plink->list);
+				dev->node_props.p2p_links_count--;
+			} else {
+				if (p2plink->node_from > proximity_domain)
+					p2plink->node_from--;
+				if (p2plink->node_to > proximity_domain)
+					p2plink->node_to--;
+			}
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index 4f80d2ea1000..9f6c949186c1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -38,6 +38,7 @@ struct kfd_node_properties {
 	uint32_t mem_banks_count;
 	uint32_t caches_count;
 	uint32_t io_links_count;
+	uint32_t p2p_links_count;
 	uint32_t cpu_core_id_base;
 	uint32_t simd_id_base;
 	uint32_t capability;
@@ -129,14 +130,15 @@ struct kfd_topology_device {
 	struct list_head		mem_props;
 	uint32_t			cache_count;
 	struct list_head		cache_props;
-	uint32_t			io_link_count;
 	struct list_head		io_link_props;
+	struct list_head		p2p_link_props;
 	struct list_head		perf_props;
 	struct kfd_dev			*gpu;
 	struct kobject			*kobj_node;
 	struct kobject			*kobj_mem;
 	struct kobject			*kobj_cache;
 	struct kobject			*kobj_iolink;
+	struct kobject			*kobj_p2plink;
 	struct kobject			*kobj_perf;
 	struct attribute		attr_gpuid;
 	struct attribute		attr_name;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 39b425d83bb1..c004cbe1e1ee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -78,21 +78,27 @@
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_uapi.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_edid.h>
 #include <drm/drm_vblank.h>
 #include <drm/drm_audio_component.h>
+#include <drm/drm_gem_atomic_helper.h>
 
 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 
 #include "dcn/dcn_1_0_offset.h"
 #include "dcn/dcn_1_0_sh_mask.h"
 #include "soc15_hw_ip.h"
+#include "soc15_common.h"
 #include "vega10_ip_offset.h"
 
 #include "soc15_common.h"
 
+#include "gc/gc_11_0_0_offset.h"
+#include "gc/gc_11_0_0_sh_mask.h"
+
 #include "modules/inc/mod_freesync.h"
 #include "modules/power/power_helpers.h"
 #include "modules/inc/mod_info_packet.h"
@@ -118,6 +124,11 @@ MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 
+#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
+#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
+
 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 
@@ -1256,10 +1267,20 @@ static void vblank_control_worker(struct work_struct *work)
 
 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 
-	/* Control PSR based on vblank requirements from OS */
+	/*
+	 * Control PSR based on vblank requirements from OS
+	 *
+	 * If panel supports PSR SU, there's no need to disable PSR when OS is
+	 * submitting fast atomic commits (we infer this by whether the OS
+	 * requests vblank events). Fast atomic commits will simply trigger a
+	 * full-frame-update (FFU); a specific case of selective-update (SU)
+	 * where the SU region is the full hactive*vactive region. See
+	 * fill_dc_dirty_rects().
+	 */
 	if (vblank_work->stream && vblank_work->stream->link) {
 		if (vblank_work->enable) {
-			if (vblank_work->stream->link->psr_settings.psr_allow_active)
+			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
+			    vblank_work->stream->link->psr_settings.psr_allow_active)
 				amdgpu_dm_psr_disable(vblank_work->stream);
 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
@@ -1507,6 +1528,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		DRM_INFO("Seamless boot condition check passed\n");
 	}
 
+	init_data.flags.enable_mipi_converter_optimization = true;
+
 	INIT_LIST_HEAD(&adev->dm.da_list);
 	/* Display Core create. */
 	adev->dm.dc = dc_create(&init_data);
@@ -1801,6 +1824,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			return 0;
 		default:
 			break;
@@ -1924,6 +1949,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 		dmub_asic = DMUB_ASIC_DCN316;
 		fw_name_dmub = FIRMWARE_DCN316_DMUB;
 		break;
+	case IP_VERSION(3, 2, 0):
+		dmub_asic = DMUB_ASIC_DCN32;
+		fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
+		break;
+	case IP_VERSION(3, 2, 1):
+		dmub_asic = DMUB_ASIC_DCN321;
+		fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
+		break;
 	default:
 		/* ASIC doesn't support DMUB. */
 		return 0;
@@ -2170,7 +2203,8 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
 		} else {
 			ret = drm_dp_mst_topology_mgr_resume(mgr, true);
 			if (ret < 0) {
-				drm_dp_mst_topology_mgr_set_mst(mgr, false);
+				dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
+					aconnector->dc_link);
 				need_hotplug = true;
 			}
 		}
@@ -2552,34 +2586,6 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
 	return;
 }
 
-static void dm_set_dpms_off(struct dc_link *link, struct dm_crtc_state *acrtc_state)
-{
-	struct dc_stream_state *stream_state;
-	struct amdgpu_dm_connector *aconnector = link->priv;
-	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
-	struct dc_stream_update stream_update;
-	bool dpms_off = true;
-
-	memset(&stream_update, 0, sizeof(stream_update));
-	stream_update.dpms_off = &dpms_off;
-
-	mutex_lock(&adev->dm.dc_lock);
-	stream_state = dc_stream_find_from_link(link);
-
-	if (stream_state == NULL) {
-		DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
-		mutex_unlock(&adev->dm.dc_lock);
-		return;
-	}
-
-	stream_update.stream = stream_state;
-	acrtc_state->force_dpms_off = true;
-	dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
-				     stream_state, &stream_update,
-				     stream_state->ctx->dc->current_state);
-	mutex_unlock(&adev->dm.dc_lock);
-}
-
 static int dm_resume(void *handle)
 {
 	struct amdgpu_device *adev = handle;
@@ -3030,16 +3036,13 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
 	struct drm_device *dev = connector->dev;
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	struct amdgpu_device *adev = drm_to_adev(dev);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
-	struct dm_crtc_state *dm_crtc_state = NULL;
+#endif
 
 	if (adev->dm.disable_hpd_irq)
 		return;
 
-	if (dm_con_state->base.state && dm_con_state->base.crtc)
-		dm_crtc_state = to_dm_crtc_state(drm_atomic_get_crtc_state(
-					dm_con_state->base.state,
-					dm_con_state->base.crtc));
 	/*
 	 * In case of failure or MST no need to update connector status or notify the OS
 	 * since (for MST case) MST does this in its own context.
@@ -3069,11 +3072,6 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
 			drm_kms_helper_connector_hotplug_event(connector);
 
 	} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
-		if (new_connection_type == dc_connection_none &&
-		    aconnector->dc_link->type == dc_connection_none &&
-		    dm_crtc_state)
-			dm_set_dpms_off(aconnector->dc_link, dm_crtc_state);
-
 		amdgpu_dm_update_connector_after_detect(aconnector);
 
 		drm_modeset_lock_all(dev);
@@ -3866,9 +3864,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
 					    int bl_idx)
 {
@@ -4072,7 +4067,6 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
 	else
 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
 }
-#endif
 
 static int initialize_plane(struct amdgpu_display_manager *dm,
 			    struct amdgpu_mode_info *mode_info, int plane_id,
@@ -4118,9 +4112,6 @@ static int initialize_plane(struct amdgpu_display_manager *dm,
 static void register_backlight_device(struct amdgpu_display_manager *dm,
 				      struct dc_link *link)
 {
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
 	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
 	    link->type != dc_connection_none) {
 		/*
@@ -4136,7 +4127,6 @@ static void register_backlight_device(struct amdgpu_display_manager *dm,
 			dm->num_of_edps++;
 		}
 	}
-#endif
 }
 
 
@@ -4233,6 +4223,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case IP_VERSION(3, 1, 3):
 	case IP_VERSION(3, 1, 5):
 	case IP_VERSION(3, 1, 6):
+	case IP_VERSION(3, 2, 0):
+	case IP_VERSION(3, 2, 1):
 	case IP_VERSION(2, 1, 0):
 		if (register_outbox_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -4251,6 +4243,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			psr_feature_enabled = true;
 			break;
 		default:
@@ -4368,6 +4362,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			if (dcn10_register_irq_handlers(dm->adev)) {
 				DRM_ERROR("DM: Failed to initialize IRQ\n");
 				goto fail;
@@ -4554,6 +4550,8 @@ static int dm_early_init(void *handle)
 		case IP_VERSION(3, 1, 3):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
+		case IP_VERSION(3, 2, 0):
+		case IP_VERSION(3, 2, 1):
 			adev->mode_info.num_crtc = 4;
 			adev->mode_info.num_hpd = 4;
 			adev->mode_info.num_dig = 4;
@@ -4863,7 +4861,9 @@ fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
 	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
 	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
-	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
+	unsigned int pipes_log2;
+
+	pipes_log2 = min(5u, mod_pipe_xor_bits);
 
 	fill_gfx9_tiling_info_from_device(adev, tiling_info);
 
@@ -4895,8 +4895,7 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 {
 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
 	const struct drm_format_info *info = drm_format_info(format);
-	int i;
-
+	struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
 	enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
 
 	if (!info)
@@ -4912,13 +4911,53 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
 		return true;
 	}
 
-	/* Check that the modifier is on the list of the plane's supported modifiers. */
-	for (i = 0; i < plane->modifier_count; i++) {
-		if (modifier == plane->modifiers[i])
+	/* check if swizzle mode is supported by this version of DCN */
+	switch (asic_id.chip_family) {
+		case FAMILY_SI:
+		case FAMILY_CI:
+		case FAMILY_KV:
+		case FAMILY_CZ:
+		case FAMILY_VI:
+			/* asics before AI does not have modifier support */
+			return false;
+			break;
+		case FAMILY_AI:
+		case FAMILY_RV:
+		case FAMILY_NV:
+		case FAMILY_VGH:
+		case FAMILY_YELLOW_CARP:
+		case AMDGPU_FAMILY_GC_10_3_6:
+		case AMDGPU_FAMILY_GC_10_3_7:
+			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
+				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D:
+					return true;
+					break;
+				default:
+					return false;
+					break;
+			}
+			break;
+		case AMDGPU_FAMILY_GC_11_0_0:
+			switch (AMD_FMT_MOD_GET(TILE, modifier)) {
+				case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
+				case AMD_FMT_MOD_TILE_GFX9_64K_D:
+					return true;
+					break;
+				default:
+					return false;
+					break;
+			}
+			break;
+		default:
+			ASSERT(0); /* Unknown asic */
 			break;
 	}
-	if (i == plane->modifier_count)
-		return false;
 
 	/*
 	 * For D swizzle the canonical modifier depends on the bpp, so check
@@ -5199,8 +5238,69 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
 		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
 }
 
+static void
+add_gfx11_modifiers(struct amdgpu_device *adev,
+		      uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+	int num_pipes = 0;
+	int pipe_xor_bits = 0;
+	int num_pkrs = 0;
+	int pkrs = 0;
+	u32 gb_addr_config;
+	unsigned swizzle_r_x;
+	uint64_t modifier_r_x;
+	uint64_t modifier_dcc_best;
+	uint64_t modifier_dcc_4k;
+
+	/* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from
+	 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} */
+	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
+	ASSERT(gb_addr_config != 0);
+
+	num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
+	pkrs = ilog2(num_pkrs);
+	num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
+	pipe_xor_bits = ilog2(num_pipes);
+
+	/* R_X swizzle modes are the best for rendering and DCC requires them. */
+	swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
+                                              AMD_FMT_MOD_TILE_GFX9_64K_R_X;
+
+	modifier_r_x = AMD_FMT_MOD |
+		AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+		AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
+		AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		AMD_FMT_MOD_SET(PACKERS, pkrs);
+
+	/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
+	modifier_dcc_best = modifier_r_x |
+		AMD_FMT_MOD_SET(DCC, 1) |
+		AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
+		AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
+
+	/* DCC settings for 4K and greater resolutions. (required by display hw) */
+	modifier_dcc_4k = modifier_r_x |
+			AMD_FMT_MOD_SET(DCC, 1) |
+			AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+			AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+			AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
+
+	add_modifier(mods, size, capacity, modifier_dcc_best);
+	add_modifier(mods, size, capacity, modifier_dcc_4k);
+
+	add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+	add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
+
+	add_modifier(mods, size, capacity, modifier_r_x);
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+			 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
+}
+
 static int
-get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
+get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
 {
 	uint64_t size = 0, capacity = 128;
 	*mods = NULL;
@@ -5232,6 +5332,9 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
 		else
 			add_gfx10_1_modifiers(adev, mods, &size, &capacity);
 		break;
+	case AMDGPU_FAMILY_GC_11_0_0:
+		add_gfx11_modifiers(adev, mods, &size, &capacity);
+		break;
 	}
 
 	add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
@@ -5270,7 +5373,7 @@ fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
 		dcc->enable = 1;
 		dcc->meta_pitch = afb->base.pitches[1];
 		dcc->independent_64b_blks = independent_64b_blks;
-		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
+		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
 			if (independent_64b_blks && independent_128b_blks)
 				dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
 			else if (independent_128b_blks)
@@ -5638,6 +5741,117 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 	return 0;
 }
 
+/**
+ * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
+ *
+ * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
+ *         remote fb
+ * @old_plane_state: Old state of @plane
+ * @new_plane_state: New state of @plane
+ * @crtc_state: New state of CRTC connected to the @plane
+ * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
+ *
+ * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
+ * (referred to as "damage clips" in DRM nomenclature) that require updating on
+ * the eDP remote buffer. The responsibility of specifying the dirty regions is
+ * amdgpu_dm's.
+ *
+ * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
+ * plane with regions that require flushing to the eDP remote buffer. In
+ * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
+ * implicitly provide damage clips without any client support via the plane
+ * bounds.
+ *
+ * Today, amdgpu_dm only supports the MPO and cursor usecase.
+ *
+ * TODO: Also enable for FB_DAMAGE_CLIPS
+ */
+static void fill_dc_dirty_rects(struct drm_plane *plane,
+				struct drm_plane_state *old_plane_state,
+				struct drm_plane_state *new_plane_state,
+				struct drm_crtc_state *crtc_state,
+				struct dc_flip_addrs *flip_addrs)
+{
+	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
+	struct rect *dirty_rects = flip_addrs->dirty_rects;
+	uint32_t num_clips;
+	bool bb_changed;
+	bool fb_changed;
+	uint32_t i = 0;
+
+	flip_addrs->dirty_rect_count = 0;
+
+	/*
+	 * Cursor plane has it's own dirty rect update interface. See
+	 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
+	 */
+	if (plane->type == DRM_PLANE_TYPE_CURSOR)
+		return;
+
+	/*
+	 * Today, we only consider MPO use-case for PSR SU. If MPO not
+	 * requested, and there is a plane update, do FFU.
+	 */
+	if (!dm_crtc_state->mpo_requested) {
+		dirty_rects[0].x = 0;
+		dirty_rects[0].y = 0;
+		dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
+		dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
+		flip_addrs->dirty_rect_count = 1;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dm_crtc_state->base.mode.crtc_hdisplay,
+				 dm_crtc_state->base.mode.crtc_vdisplay);
+		return;
+	}
+
+	/*
+	 * MPO is requested. Add entire plane bounding box to dirty rects if
+	 * flipped to or damaged.
+	 *
+	 * If plane is moved or resized, also add old bounding box to dirty
+	 * rects.
+	 */
+	num_clips = drm_plane_get_damage_clips_count(new_plane_state);
+	fb_changed = old_plane_state->fb->base.id !=
+		     new_plane_state->fb->base.id;
+	bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
+		      old_plane_state->crtc_y != new_plane_state->crtc_y ||
+		      old_plane_state->crtc_w != new_plane_state->crtc_w ||
+		      old_plane_state->crtc_h != new_plane_state->crtc_h);
+
+	DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
+			 new_plane_state->plane->base.id,
+			 bb_changed, fb_changed, num_clips);
+
+	if (num_clips || fb_changed || bb_changed) {
+		dirty_rects[i].x = new_plane_state->crtc_x;
+		dirty_rects[i].y = new_plane_state->crtc_y;
+		dirty_rects[i].width = new_plane_state->crtc_w;
+		dirty_rects[i].height = new_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dirty_rects[i].x, dirty_rects[i].y,
+				 dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	/* Add old plane bounding-box if plane is moved or resized */
+	if (bb_changed) {
+		dirty_rects[i].x = old_plane_state->crtc_x;
+		dirty_rects[i].y = old_plane_state->crtc_y;
+		dirty_rects[i].width = old_plane_state->crtc_w;
+		dirty_rects[i].height = old_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				old_plane_state->plane->base.id,
+				dirty_rects[i].x, dirty_rects[i].y,
+				dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	flip_addrs->dirty_rect_count = i;
+}
+
 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
 					   const struct dm_connector_state *dm_state,
 					   struct dc_stream_state *stream)
@@ -6585,13 +6799,13 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 	state->freesync_config = cur->freesync_config;
 	state->cm_has_degamma = cur->cm_has_degamma;
 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
-	state->force_dpms_off = cur->force_dpms_off;
+	state->mpo_requested = cur->mpo_requested;
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
 	return &state->base;
 }
 
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
+#ifdef CONFIG_DEBUG_FS
 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 {
 	crtc_debugfs_init(crtc);
@@ -6677,7 +6891,7 @@ static void dm_disable_vblank(struct drm_crtc *crtc)
 	dm_set_vblank(crtc, false);
 }
 
-/* Implemented only the options currently availible for the driver */
+/* Implemented only the options currently available for the driver */
 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 	.reset = dm_crtc_reset_state,
 	.destroy = amdgpu_dm_crtc_destroy,
@@ -6692,7 +6906,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 	.enable_vblank = dm_enable_vblank,
 	.disable_vblank = dm_disable_vblank,
 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+#if defined(CONFIG_DEBUG_FS)
 	.late_register = amdgpu_dm_crtc_late_register,
 #endif
 };
@@ -6844,15 +7058,12 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
 	if (aconnector->mst_mgr.dev)
 		drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	for (i = 0; i < dm->num_of_edps; i++) {
 		if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
 			backlight_device_unregister(dm->backlight_dev[i]);
 			dm->backlight_dev[i] = NULL;
 		}
 	}
-#endif
 
 	if (aconnector->dc_em_sink)
 		dc_sink_release(aconnector->dc_em_sink);
@@ -7040,7 +7251,11 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			break;
 		}
 
-		dc_result = dc_validate_stream(adev->dm.dc, stream);
+		if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
+
+		if (dc_result == DC_OK)
+			dc_result = dc_validate_stream(adev->dm.dc, stream);
 
 		if (dc_result != DC_OK) {
 			DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
@@ -7340,7 +7555,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
 
 }
 
-static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
+int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
 {
 	switch (display_color_depth) {
 		case COLOR_DEPTH_666:
@@ -7598,6 +7813,10 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
 		goto error_unpin;
 	}
 
+	r = drm_gem_plane_helper_prepare_fb(plane, new_state);
+	if (unlikely(r != 0))
+		goto error_unpin;
+
 	amdgpu_bo_unreserve(rbo);
 
 	afb->address = amdgpu_bo_gpu_offset(rbo);
@@ -9132,9 +9351,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 	struct dm_crtc_state *dm_old_crtc_state =
 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
 	int planes_count = 0, vpos, hpos;
-	long r;
 	unsigned long flags;
-	struct amdgpu_bo *abo;
 	uint32_t target_vblank, last_flip_vblank;
 	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 	bool pflip_present = false;
@@ -9206,19 +9423,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			continue;
 		}
 
-		abo = gem_to_amdgpu_bo(fb->obj[0]);
-
-		/*
-		 * Wait for all fences on this FB. Do limited wait to avoid
-		 * deadlock during GPU reset when this fence will not signal
-		 * but we hold reservation lock for the BO.
-		 */
-		r = dma_resv_wait_timeout(abo->tbo.base.resv,
-					  DMA_RESV_USAGE_WRITE, false,
-					  msecs_to_jiffies(5000));
-		if (unlikely(r <= 0))
-			DRM_ERROR("Waiting for fences timed out!");
-
 		fill_dc_plane_info_and_addr(
 			dm->adev, new_plane_state,
 			afb->tiling_flags,
@@ -9233,6 +9437,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		bundle->surface_updates[planes_count].plane_info =
 			&bundle->plane_infos[planes_count];
 
+		fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
+				    new_crtc_state,
+				    &bundle->flip_addrs[planes_count]);
+
 		/*
 		 * Only allow immediate flips for fast updates that don't
 		 * change FB pitch, DCC state, rotation or mirroing.
@@ -9319,8 +9527,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		 * and rely on sending it from software.
 		 */
 		if (acrtc_attach->base.state->event &&
-		    acrtc_state->active_planes > 0 &&
-		    !acrtc_state->force_dpms_off) {
+		    acrtc_state->active_planes > 0) {
 			drm_crtc_vblank_get(pcrtc);
 
 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
@@ -9428,6 +9635,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 
 			/* Allow PSR when skip count is 0. */
 			acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
+
+			/*
+			 * If sink supports PSR SU, there is no need to rely on
+			 * a vblank event disable request to enable PSR. PSR SU
+			 * can be enabled immediately once OS demonstrates an
+			 * adequate number of fast atomic commits to notify KMD
+			 * of update events. See `vblank_control_worker()`.
+			 */
+			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
+			    acrtc_attach->dm_irq_params.allow_psr_entry &&
+			    !acrtc_state->stream->link->psr_settings.psr_allow_active)
+				amdgpu_dm_psr_enable(acrtc_state->stream);
 		} else {
 			acrtc_attach->dm_irq_params.allow_psr_entry = false;
 		}
@@ -9561,9 +9780,14 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
 	int crtc_disable_count = 0;
 	bool mode_set_reset_required = false;
+	int r;
 
 	trace_amdgpu_dm_atomic_commit_tail_begin(state);
 
+	r = drm_atomic_helper_wait_for_fences(dev, state, false);
+	if (unlikely(r))
+		DRM_ERROR("Waiting for fences timed out!");
+
 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
 	dm_state = dm_atomic_get_new_state(state);
@@ -9916,15 +10140,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 	/* Update audio instances for each connector. */
 	amdgpu_dm_commit_audio(dev, state);
 
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||		\
-	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 	/* restore the backlight level */
 	for (i = 0; i < dm->num_of_edps; i++) {
 		if (dm->backlight_dev[i] &&
 		    (dm->actual_brightness[i] != dm->brightness[i]))
 			amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
 	}
-#endif
+
 	/*
 	 * send vblank event on all events not handled in flip and
 	 * mark consumed event for drm_atomic_helper_commit_hw_done
@@ -10372,7 +10594,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
 		 * added MST connectors not found in existing crtc_state in the chained mode
 		 * TODO: need to dig out the root cause of that
 		 */
-		if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
+		if (!aconnector)
 			goto skip_modeset;
 
 		if (modereset_required(new_crtc_state))
@@ -10983,7 +11205,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 				}
 			}
 		}
-		pre_validate_dsc(state, &dm_state, vars);
+		if (!pre_validate_dsc(state, &dm_state, vars)) {
+			ret = -EINVAL;
+			goto fail;
+		}
 	}
 #endif
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -11229,6 +11454,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) {
 			DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
+			ret = -EINVAL;
 			goto fail;
 		}
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index aa34c0068f41..547fc1547977 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -583,7 +583,6 @@ struct amdgpu_dm_connector {
 	struct drm_dp_mst_port *port;
 	struct amdgpu_dm_connector *mst_port;
 	struct drm_dp_aux *dsc_aux;
-
 	/* TODO see if we can merge with ddc_bus or make a dm_connector */
 	struct amdgpu_i2c_adapter *i2c;
 
@@ -639,8 +638,6 @@ struct dm_crtc_state {
 
 	bool dsc_force_changed;
 	bool vrr_supported;
-
-	bool force_dpms_off;
 	struct mod_freesync_config freesync_config;
 	struct dc_info_packet vrr_infopacket;
 
@@ -749,4 +746,6 @@ int dm_atomic_get_state(struct drm_atomic_state *state,
 struct amdgpu_dm_connector *
 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 					     struct drm_crtc *crtc);
+
+int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
 #endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index c7a592d68feb..b64507f294ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -540,11 +540,11 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 
 	/* apply phy settings from user */
 	for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
-		link_lane_settings.lane_settings[r].VOLTAGE_SWING =
+		link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 				(enum dc_voltage_swing) (param[0]);
-		link_lane_settings.lane_settings[r].PRE_EMPHASIS =
+		link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 				(enum dc_pre_emphasis) (param[1]);
-		link_lane_settings.lane_settings[r].POST_CURSOR2 =
+		link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 				(enum dc_post_cursor2) (param[2]);
 	}
 
@@ -738,7 +738,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
 	}
 
 	for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
-		link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
+		link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 
 	dc_link_set_test_pattern(
 		link,
@@ -871,28 +871,18 @@ static int psr_capability_show(struct seq_file *m, void *data)
 }
 
 /*
- * Returns the current and maximum output bpc for the connector.
- * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
+ * Returns the current bpc for the crtc.
+ * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
  */
-static int output_bpc_show(struct seq_file *m, void *data)
+static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
 {
-	struct drm_connector *connector = m->private;
-	struct drm_device *dev = connector->dev;
-	struct drm_crtc *crtc = NULL;
+	struct drm_crtc *crtc = m->private;
+	struct drm_device *dev = crtc->dev;
 	struct dm_crtc_state *dm_crtc_state = NULL;
 	int res = -ENODEV;
 	unsigned int bpc;
 
 	mutex_lock(&dev->mode_config.mutex);
-	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-
-	if (connector->state == NULL)
-		goto unlock;
-
-	crtc = connector->state->crtc;
-	if (crtc == NULL)
-		goto unlock;
-
 	drm_modeset_lock(&crtc->mutex, NULL);
 	if (crtc->state == NULL)
 		goto unlock;
@@ -922,18 +912,15 @@ static int output_bpc_show(struct seq_file *m, void *data)
 	}
 
 	seq_printf(m, "Current: %u\n", bpc);
-	seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 	res = 0;
 
 unlock:
-	if (crtc)
-		drm_modeset_unlock(&crtc->mutex);
-
-	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	drm_modeset_unlock(&crtc->mutex);
 	mutex_unlock(&dev->mode_config.mutex);
 
 	return res;
 }
+DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 
 /*
  * Example usage:
@@ -2539,7 +2526,6 @@ static int target_backlight_show(struct seq_file *m, void *unused)
 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
-DEFINE_SHOW_ATTRIBUTE(output_bpc);
 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
@@ -2786,7 +2772,6 @@ static const struct {
 	const struct file_operations *fops;
 } connector_debugfs_entries[] = {
 		{"force_yuv420_output", &force_yuv420_output_fops},
-		{"output_bpc", &output_bpc_fops},
 		{"trigger_hotplug", &trigger_hotplug_debugfs_fops},
 		{"internal_display", &internal_display_fops}
 };
@@ -3170,9 +3155,10 @@ static int crc_win_update_get(void *data, u64 *val)
 
 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
 			 crc_win_update_set, "%llu\n");
-
+#endif
 void crtc_debugfs_init(struct drm_crtc *crtc)
 {
+#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 	struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
 
 	if (!dir)
@@ -3188,9 +3174,11 @@ void crtc_debugfs_init(struct drm_crtc *crtc)
 				   &crc_win_y_end_fops);
 	debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
 				   &crc_win_update_fops);
-
-}
 #endif
+	debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
+			    crtc, &amdgpu_current_bpc_fops);
+}
+
 /*
  * Writes DTN log state to the user supplied buffer.
  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h
index 3366cb644053..071200473c27 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h
@@ -31,8 +31,6 @@
 
 void connector_debugfs_init(struct amdgpu_dm_connector *connector);
 void dtn_debugfs_init(struct amdgpu_device *adev);
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 void crtc_debugfs_init(struct drm_crtc *crtc);
-#endif
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 15c0e3f2a9c3..d7c41c133e2c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -476,13 +476,16 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
 	display->stream_enc_idx = config->stream_enc_idx;
 	link->link_enc_idx = config->link_enc_idx;
+	link->dio_output_id = config->dio_output_idx;
 	link->phy_idx = config->phy_idx;
+
 	if (sink)
 		link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
 	link->hdcp_supported_informational = link_is_hdcp14;
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
 	link->dp.mst_enabled = config->mst_enabled;
+	link->dp.usb4_enabled = config->usb4_enabled;
 	display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
 	link->adjust.auth_delay = 3;
 	link->adjust.hdcp1.disable = 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7c799ddc1d27..137645d40b72 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -451,7 +451,6 @@ bool dm_helpers_dp_mst_stop_top_mgr(
 		struct dc_link *link)
 {
 	struct amdgpu_dm_connector *aconnector = link->priv;
-	uint8_t i;
 
 	if (!aconnector) {
 		DRM_ERROR("Failed to find connector for link!");
@@ -463,22 +462,7 @@ bool dm_helpers_dp_mst_stop_top_mgr(
 
 	if (aconnector->mst_mgr.mst_state == true) {
 		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-
-		for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
-			if (link->remote_sinks[i] == NULL)
-				continue;
-
-			if (link->remote_sinks[i]->sink_signal ==
-			    SIGNAL_TYPE_DISPLAY_PORT_MST) {
-				dc_link_remove_remote_sink(link, link->remote_sinks[i]);
-
-				if (aconnector->dc_sink) {
-					dc_sink_release(aconnector->dc_sink);
-					aconnector->dc_sink = NULL;
-					aconnector->dc_link->cur_link_settings.lane_count = 0;
-				}
-			}
-		}
+		link->cur_link_settings.lane_count = 0;
 	}
 
 	return false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9221b6690a4a..f3ce37664143 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -140,11 +140,28 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 static void
 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 {
-	struct amdgpu_dm_connector *amdgpu_dm_connector =
+	struct amdgpu_dm_connector *aconnector =
 		to_amdgpu_dm_connector(connector);
-	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+	struct drm_dp_mst_port *port = aconnector->port;
+	struct amdgpu_dm_connector *root = aconnector->mst_port;
+	struct dc_link *dc_link = aconnector->dc_link;
+	struct dc_sink *dc_sink = aconnector->dc_sink;
 
 	drm_dp_mst_connector_early_unregister(connector, port);
+
+	/*
+	 * Release dc_sink for connector which its attached port is
+	 * no longer in the mst topology
+	 */
+	drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
+	if (dc_sink) {
+		if (dc_link->sink_count)
+			dc_link_remove_remote_sink(dc_link, dc_sink);
+
+		dc_sink_release(dc_sink);
+		aconnector->dc_sink = NULL;
+	}
+	drm_modeset_unlock(&root->mst_mgr.base.lock);
 }
 
 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
@@ -344,12 +361,59 @@ dm_dp_mst_detect(struct drm_connector *connector,
 {
 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 	struct amdgpu_dm_connector *master = aconnector->mst_port;
+	struct drm_dp_mst_port *port = aconnector->port;
+	int connection_status;
 
 	if (drm_connector_is_unregistered(connector))
 		return connector_status_disconnected;
 
-	return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
-				      aconnector->port);
+	connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
+							aconnector->port);
+
+	if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
+		uint8_t dpcd_rev;
+		int ret;
+
+		ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
+
+		if (ret == 1) {
+			port->dpcd_rev = dpcd_rev;
+
+			/* Could be DP1.2 DP Rx case*/
+			if (!dpcd_rev) {
+				ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
+
+				if (ret == 1)
+					port->dpcd_rev = dpcd_rev;
+			}
+
+			if (!dpcd_rev)
+				DRM_DEBUG_KMS("Can't decide DPCD revision number!");
+		}
+
+		/*
+		 * Could be legacy sink, logical port etc on DP1.2.
+		 * Will get Nack under these cases when issue remote
+		 * DPCD read.
+		 */
+		if (ret != 1)
+			DRM_DEBUG_KMS("Can't access DPCD");
+	} else if (port->pdt == DP_PEER_DEVICE_NONE) {
+		port->dpcd_rev = 0;
+	}
+
+	/*
+	 * Release dc_sink for connector which unplug event is notified by CSN msg
+	 */
+	if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
+		if (aconnector->dc_link->sink_count)
+			dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
+
+		dc_sink_release(aconnector->dc_sink);
+		aconnector->dc_sink = NULL;
+	}
+
+	return connection_status;
 }
 
 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
@@ -634,7 +698,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 	return dsc_config.bits_per_pixel;
 }
 
-static void increase_dsc_bpp(struct drm_atomic_state *state,
+static bool increase_dsc_bpp(struct drm_atomic_state *state,
 			     struct dc_link *dc_link,
 			     struct dsc_mst_fairness_params *params,
 			     struct dsc_mst_fairness_vars *vars,
@@ -694,7 +758,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  pbn_per_timeslot) < 0)
-				return;
+				return false;
 			if (!drm_dp_mst_atomic_check(state)) {
 				vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 			} else {
@@ -704,7 +768,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 								  params[next_index].port,
 								  vars[next_index].pbn,
 								  pbn_per_timeslot) < 0)
-					return;
+					return false;
 			}
 		} else {
 			vars[next_index].pbn += initial_slack[next_index];
@@ -713,7 +777,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  pbn_per_timeslot) < 0)
-				return;
+				return false;
 			if (!drm_dp_mst_atomic_check(state)) {
 				vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 			} else {
@@ -723,16 +787,17 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
 								  params[next_index].port,
 								  vars[next_index].pbn,
 								  pbn_per_timeslot) < 0)
-					return;
+					return false;
 			}
 		}
 
 		bpp_increased[next_index] = true;
 		remaining_to_increase--;
 	}
+	return true;
 }
 
-static void try_disable_dsc(struct drm_atomic_state *state,
+static bool try_disable_dsc(struct drm_atomic_state *state,
 			    struct dc_link *dc_link,
 			    struct dsc_mst_fairness_params *params,
 			    struct dsc_mst_fairness_vars *vars,
@@ -780,7 +845,7 @@ static void try_disable_dsc(struct drm_atomic_state *state,
 						  params[next_index].port,
 						  vars[next_index].pbn,
 						  dm_mst_get_pbn_divider(dc_link)) < 0)
-			return;
+			return false;
 
 		if (!drm_dp_mst_atomic_check(state)) {
 			vars[next_index].dsc_enabled = false;
@@ -792,12 +857,13 @@ static void try_disable_dsc(struct drm_atomic_state *state,
 							  params[next_index].port,
 							  vars[next_index].pbn,
 							  dm_mst_get_pbn_divider(dc_link)) < 0)
-				return;
+				return false;
 		}
 
 		tried[next_index] = true;
 		remaining_to_try--;
 	}
+	return true;
 }
 
 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
@@ -913,9 +979,11 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 		return false;
 
 	/* Optimize degree of compression */
-	increase_dsc_bpp(state, dc_link, params, vars, count, k);
+	if (!increase_dsc_bpp(state, dc_link, params, vars, count, k))
+		return false;
 
-	try_disable_dsc(state, dc_link, params, vars, count, k);
+	if (!try_disable_dsc(state, dc_link, params, vars, count, k))
+		return false;
 
 	set_dsc_configs_from_fairness_vars(params, vars, count, k);
 
@@ -1187,21 +1255,22 @@ static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
 	return ret;
 }
 
-void pre_validate_dsc(struct drm_atomic_state *state,
+bool pre_validate_dsc(struct drm_atomic_state *state,
 		      struct dm_atomic_state **dm_state_ptr,
 		      struct dsc_mst_fairness_vars *vars)
 {
 	int i;
 	struct dm_atomic_state *dm_state;
 	struct dc_state *local_dc_state = NULL;
+	int ret = 0;
 
 	if (!is_dsc_precompute_needed(state)) {
 		DRM_INFO_ONCE("DSC precompute is not needed.\n");
-		return;
+		return true;
 	}
 	if (dm_atomic_get_state(state, dm_state_ptr)) {
 		DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
-		return;
+		return false;
 	}
 	dm_state = *dm_state_ptr;
 
@@ -1213,7 +1282,7 @@ void pre_validate_dsc(struct drm_atomic_state *state,
 
 	local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
 	if (!local_dc_state)
-		return;
+		return false;
 
 	for (i = 0; i < local_dc_state->stream_count; i++) {
 		struct dc_stream_state *stream = dm_state->context->streams[i];
@@ -1239,11 +1308,19 @@ void pre_validate_dsc(struct drm_atomic_state *state,
 								&state->crtcs[ind].new_state->mode,
 								dm_new_conn_state,
 								dm_old_crtc_state->stream);
+			if (local_dc_state->streams[i] == NULL) {
+				ret = -EINVAL;
+				break;
+			}
 		}
 	}
 
+	if (ret != 0)
+		goto clean_exit;
+
 	if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) {
 		DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
+		ret = -EINVAL;
 		goto clean_exit;
 	}
 
@@ -1273,5 +1350,43 @@ void pre_validate_dsc(struct drm_atomic_state *state,
 	}
 
 	kfree(local_dc_state);
+
+	return (ret == 0);
 }
+
 #endif
+
+enum dc_status dm_dp_mst_is_port_support_mode(
+	struct amdgpu_dm_connector *aconnector,
+	struct dc_stream_state *stream)
+{
+	int bpp, pbn, branch_max_throughput_mps = 0;
+
+	/* check if mode could be supported within fUll_pbn */
+	bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+	pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+	if (pbn > aconnector->port->full_pbn)
+		return DC_FAIL_BANDWIDTH_VALIDATE;
+
+	/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
+	switch (stream->timing.pixel_encoding) {
+	case PIXEL_ENCODING_RGB:
+	case PIXEL_ENCODING_YCBCR444:
+		branch_max_throughput_mps =
+			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
+		break;
+	case PIXEL_ENCODING_YCBCR422:
+	case PIXEL_ENCODING_YCBCR420:
+		branch_max_throughput_mps =
+			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
+		break;
+	default:
+		break;
+	}
+
+	if (branch_max_throughput_mps != 0 &&
+		((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000))
+		return DC_FAIL_BANDWIDTH_VALIDATE;
+
+	return DC_OK;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 85628ad59e6c..b92a7c5671aa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -59,8 +59,12 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 
 bool needs_dsc_aux_workaround(struct dc_link *link);
 
-void pre_validate_dsc(struct drm_atomic_state *state,
+bool pre_validate_dsc(struct drm_atomic_state *state,
 		      struct dm_atomic_state **dm_state_ptr,
 		      struct dsc_mst_fairness_vars *vars);
 
+enum dc_status dm_dp_mst_is_port_support_mode(
+	struct amdgpu_dm_connector *aconnector,
+	struct dc_stream_state *stream);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 141fd2721501..c8da18e45b0e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -79,10 +79,12 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
 		link->psr_settings.psr_feature_enabled = true;
 	}
 
-	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
+	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
 		link->psr_settings.psr_feature_enabled,
 		link->psr_settings.psr_version,
-		link->dpcd_caps.psr_info.psr_version);
+		link->dpcd_caps.psr_info.psr_version,
+		link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
+		link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
 
 }
 
@@ -97,19 +99,24 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
 	struct dc_link *link = NULL;
 	struct psr_config psr_config = {0};
 	struct psr_context psr_context = {0};
+	struct dc *dc = NULL;
 	bool ret = false;
 
 	if (stream == NULL)
 		return false;
 
 	link = stream->link;
+	dc = link->ctx->dc;
 
 	if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
-		psr_config.psr_version = link->psr_settings.psr_version;
-		psr_config.psr_frame_capture_indication_req = 0;
-		psr_config.psr_rfb_setup_time = 0x37;
-		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
-		psr_config.allow_smu_optimizations = 0x0;
+		mod_power_calc_psr_configs(&psr_config, link, stream);
+
+		/* linux DM specific updating for psr config fields */
+		psr_config.allow_smu_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
+			mod_power_only_edp(dc->current_state, stream);
+		psr_config.allow_multi_disp_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 
 		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index fdcaea22b456..d3bc9dc21771 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -34,6 +34,7 @@
 #include <drm/drm_crtc.h>
 #include <drm/drm_plane.h>
 #include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
 #include <drm/drm_encoder.h>
 #include <drm/drm_atomic.h>
 
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index b4eca0236435..4de8e1871711 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -38,6 +38,8 @@ DC_LIBS += dcn303
 DC_LIBS += dcn31
 DC_LIBS += dcn315
 DC_LIBS += dcn316
+DC_LIBS += dcn32
+DC_LIBS += dcn321
 endif
 
 DC_LIBS += dce120
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 23a3b640f0ee..25791ed0559d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -165,9 +165,21 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 	unsigned int count = 0;
 	unsigned int i;
 
-	for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-		if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
-			count++;
+	switch (bp->object_info_tbl.revision.minor) {
+	default:
+	case 4:
+		for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
+			if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
+				count++;
+
+		break;
+
+	case 5:
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
+			if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
+				count++;
+
+		break;
 	}
 	return count;
 }
@@ -182,16 +194,34 @@ static struct graphics_object_id bios_parser_get_connector_id(
 	struct object_info_table *tbl = &bp->object_info_tbl;
 	struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
 
-	if (v1_4->number_of_path > i) {
-		/* If display_objid is generic object id,  the encoderObj
-		 * /extencoderobjId should be 0
-		 */
-		if (v1_4->display_path[i].encoderobjid != 0 &&
-				v1_4->display_path[i].display_objid != 0)
-			object_id = object_id_from_bios_object_id(
+	struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
+
+	switch (bp->object_info_tbl.revision.minor) {
+	default:
+	case 4:
+		if (v1_4->number_of_path > i) {
+			/* If display_objid is generic object id,  the encoderObj
+			 * /extencoderobjId should be 0
+			 */
+			if (v1_4->display_path[i].encoderobjid != 0 &&
+			    v1_4->display_path[i].display_objid != 0)
+				object_id = object_id_from_bios_object_id(
 					v1_4->display_path[i].display_objid);
-	}
+		}
+		break;
 
+	case 5:
+		if (v1_5->number_of_path > i) {
+			/* If display_objid is generic object id,  the encoderObjId
+		 * should be 0
+		 */
+			if (v1_5->display_path[i].encoderobjid != 0 &&
+			    v1_5->display_path[i].display_objid != 0)
+				object_id = object_id_from_bios_object_id(
+					v1_5->display_path[i].display_objid);
+		}
+		break;
+	}
 	return object_id;
 }
 
@@ -201,8 +231,8 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	unsigned int i;
-	enum bp_result  bp_result = BP_RESULT_BADINPUT;
-	struct graphics_object_id obj_id = {0};
+	enum bp_result bp_result = BP_RESULT_BADINPUT;
+	struct graphics_object_id obj_id = { 0 };
 	struct object_info_table *tbl = &bp->object_info_tbl;
 
 	if (!src_object_id)
@@ -217,37 +247,84 @@ static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 		 * If found in for loop, should break.
 		 * DAL2 implementation may be changed too
 		 */
-		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-			obj_id = object_id_from_bios_object_id(
-			tbl->v1_4->display_path[i].encoderobjid);
-			if (object_id.type == obj_id.type &&
-					object_id.id == obj_id.id &&
-						object_id.enum_id ==
-							obj_id.enum_id) {
-				*src_object_id =
-				object_id_from_bios_object_id(0x1100);
-				/* break; */
+		switch (bp->object_info_tbl.revision.minor) {
+		default:
+		case 4:
+			for (i = 0; i < tbl->v1_4->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_4->display_path[i].encoderobjid);
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							0x1100);
+					/* break; */
+				}
+			}
+			bp_result = BP_RESULT_OK;
+			break;
+
+		case 5:
+			for (i = 0; i < tbl->v1_5->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_5->display_path[i].encoderobjid);
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							0x1100);
+					/* break; */
+				}
 			}
+			bp_result = BP_RESULT_OK;
+			break;
 		}
-		bp_result = BP_RESULT_OK;
 		break;
 	case OBJECT_TYPE_CONNECTOR:
-		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-			obj_id = object_id_from_bios_object_id(
-				tbl->v1_4->display_path[i].display_objid);
-
-			if (object_id.type == obj_id.type &&
-				object_id.id == obj_id.id &&
-					object_id.enum_id == obj_id.enum_id) {
-				*src_object_id =
-				object_id_from_bios_object_id(
-				tbl->v1_4->display_path[i].encoderobjid);
-				/* break; */
+		switch (bp->object_info_tbl.revision.minor) {
+		default:
+		case 4:
+			for (i = 0; i < tbl->v1_4->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+					tbl->v1_4->display_path[i]
+						.display_objid);
+
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id =
+						object_id_from_bios_object_id(
+							tbl->v1_4
+								->display_path[i]
+								.encoderobjid);
+					/* break; */
+				}
 			}
+			bp_result = BP_RESULT_OK;
+			break;
 		}
 		bp_result = BP_RESULT_OK;
 		break;
+		case 5:
+			for (i = 0; i < tbl->v1_5->number_of_path; i++) {
+				obj_id = object_id_from_bios_object_id(
+								       tbl->v1_5->display_path[i].display_objid);
+
+				if (object_id.type == obj_id.type &&
+				    object_id.id == obj_id.id &&
+				    object_id.enum_id == obj_id.enum_id) {
+					*src_object_id = object_id_from_bios_object_id(
+										       tbl->v1_5->display_path[i].encoderobjid);
+					/* break; */
+				}
+			}
+		bp_result = BP_RESULT_OK;
+		break;
+
 	default:
+		bp_result = BP_RESULT_OK;
 		break;
 	}
 
@@ -290,12 +367,55 @@ static struct atom_display_object_path_v2 *get_bios_object(
 	}
 }
 
+/* from graphics_object_id, find display path which includes the object_id */
+static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(
+	struct bios_parser *bp,
+	struct graphics_object_id id)
+{
+	unsigned int i;
+	struct graphics_object_id obj_id = {0};
+
+	switch (id.type) {
+	case OBJECT_TYPE_ENCODER:
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
+			obj_id = object_id_from_bios_object_id(
+					bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
+			if (id.type == obj_id.type && id.id == obj_id.id
+					&& id.enum_id == obj_id.enum_id)
+				return &bp->object_info_tbl.v1_5->display_path[i];
+		}
+        break;
+
+	case OBJECT_TYPE_CONNECTOR:
+	case OBJECT_TYPE_GENERIC:
+		/* Both Generic and Connector Object ID
+		 * will be stored on display_objid
+		 */
+		for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
+			obj_id = object_id_from_bios_object_id(
+					bp->object_info_tbl.v1_5->display_path[i].display_objid);
+			if (id.type == obj_id.type && id.id == obj_id.id
+					&& id.enum_id == obj_id.enum_id)
+				return &bp->object_info_tbl.v1_5->display_path[i];
+		}
+        break;
+
+	default:
+		return NULL;
+	}
+
+    return NULL;
+}
+
 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 	struct graphics_object_id id,
 	struct graphics_object_i2c_info *info)
 {
 	uint32_t offset;
 	struct atom_display_object_path_v2 *object;
+
+	struct atom_display_object_path_v3 *object_path_v3;
+
 	struct atom_common_record_header *header;
 	struct atom_i2c_record *record;
 	struct atom_i2c_record dummy_record = {0};
@@ -313,12 +433,25 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 			return BP_RESULT_NORECORD;
 	}
 
-	object = get_bios_object(bp, id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        object = get_bios_object(bp, id);
 
-	if (!object)
-		return BP_RESULT_BADINPUT;
+	        if (!object)
+				return BP_RESULT_BADINPUT;
 
-	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+	        offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, id);
+
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
+		break;
+	}
 
 	for (;;) {
 		header = GET_IMAGE(struct atom_common_record_header, offset);
@@ -421,6 +554,41 @@ static enum bp_result get_gpio_i2c_info(
 	return BP_RESULT_OK;
 }
 
+static struct atom_hpd_int_record *get_hpd_record_for_path_v3(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+			!header->record_size)
+			break;
+
+		if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
+			&& sizeof(struct atom_hpd_int_record) <=
+							header->record_size)
+			return (struct atom_hpd_int_record *) header;
+
+		offset += header->record_size;
+	}
+
+	return NULL;
+}
+
 static enum bp_result bios_parser_get_hpd_info(
 	struct dc_bios *dcb,
 	struct graphics_object_id id,
@@ -428,17 +596,32 @@ static enum bp_result bios_parser_get_hpd_info(
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
+	struct atom_display_object_path_v3 *object_path_v3;
 	struct atom_hpd_int_record *record = NULL;
 
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	object = get_bios_object(bp, id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        object = get_bios_object(bp, id);
 
-	if (!object)
-		return BP_RESULT_BADINPUT;
+			if (!object)
+				return BP_RESULT_BADINPUT;
+
+	        record = get_hpd_record(bp, object);
 
-	record = get_hpd_record(bp, object);
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, id);
+
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		record = get_hpd_record_for_path_v3(bp, object_path_v3);
+		break;
+	}
 
 	if (record != NULL) {
 		info->hpd_int_gpio_uid = record->pin_id;
@@ -526,25 +709,9 @@ static enum bp_result bios_parser_get_gpio_pin_info(
 		return BP_RESULT_UNSUPPORTED;
 
 	/* Temporary hard code gpio pin info */
-#if defined(FOR_SIMNOW_BOOT)
-	{
-		struct  atom_gpio_pin_assignment  gpio_pin[8] = {
-				{0x5db5, 0, 0, 1, 0},
-				{0x5db5, 8, 8, 2, 0},
-				{0x5db5, 0x10, 0x10, 3, 0},
-				{0x5db5, 0x18, 0x14, 4, 0},
-				{0x5db5, 0x1A, 0x18, 5, 0},
-				{0x5db5, 0x1C, 0x1C, 6, 0},
-		};
-
-		count = 6;
-		memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
-	}
-#else
 	count = (le16_to_cpu(header->table_header.structuresize)
 			- sizeof(struct atom_common_table_header))
 				/ sizeof(struct atom_gpio_pin_assignment);
-#endif
 	for (i = 0; i < count; ++i) {
 		if (header->gpio_pin[i].gpio_id != gpio_id)
 			continue;
@@ -633,19 +800,37 @@ static enum bp_result bios_parser_get_device_tag(
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
 
+	struct atom_display_object_path_v3 *object_path_v3;
+
+
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	/* getBiosObject will return MXM object */
-	object = get_bios_object(bp, connector_object_id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        /* getBiosObject will return MXM object */
+	        object = get_bios_object(bp, connector_object_id);
 
-	if (!object) {
-		BREAK_TO_DEBUGGER(); /* Invalid object id */
-		return BP_RESULT_BADINPUT;
-	}
+			if (!object) {
+				BREAK_TO_DEBUGGER(); /* Invalid object id */
+				return BP_RESULT_BADINPUT;
+			}
+
+	        info->acpi_device = 0; /* BIOS no longer provides this */
+	        info->dev_id = device_type_from_device_id(object->device_tag);
+	        break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
 
-	info->acpi_device = 0; /* BIOS no longer provides this */
-	info->dev_id = device_type_from_device_id(object->device_tag);
+		if (!object_path_v3) {
+			BREAK_TO_DEBUGGER(); /* Invalid object id */
+			return BP_RESULT_BADINPUT;
+		}
+		info->acpi_device = 0; /* BIOS no longer provides this */
+		info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
+		break;
+	}
 
 	return BP_RESULT_OK;
 }
@@ -803,6 +988,71 @@ static enum bp_result get_ss_info_v4_2(
 	return result;
 }
 
+static enum bp_result get_ss_info_v4_5(
+	struct bios_parser *bp,
+	uint32_t id,
+	uint32_t index,
+	struct spread_spectrum_info *ss_info)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!ss_info)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	ss_info->type.STEP_AND_DELAY_INFO = false;
+	ss_info->spread_percentage_divider = 1000;
+	/* BIOS no longer uses target clock.  Always enable for now */
+	ss_info->target_clock_range = 0xffffffff;
+
+	switch (id) {
+	case AS_SIGNAL_TYPE_DVI:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->dvi_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->dvi_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_HDMI:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->hdmi_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
+		ss_info->spread_spectrum_percentage =
+				disp_cntl_tbl->dp_ss_percentage;
+		ss_info->spread_spectrum_range =
+				disp_cntl_tbl->dp_ss_rate_10hz * 10;
+		if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+			ss_info->type.CENTER_MODE = true;
+		break;
+	case AS_SIGNAL_TYPE_GPU_PLL:
+		/* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
+		 * SMU Display PLL supposed to be without spread.
+		 * Better place for it would be in atom_display_controller_info_v4_5 table.
+		 */
+		result = BP_RESULT_UNSUPPORTED;
+		break;
+	default:
+		result = BP_RESULT_UNSUPPORTED;
+		break;
+	}
+
+	return result;
+}
+
 /**
  * bios_parser_get_spread_spectrum_info
  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
@@ -847,6 +1097,9 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
 		case 3:
 		case 4:
 			return get_ss_info_v4_2(bp, signal, index, ss_info);
+		case 5:
+			return get_ss_info_v4_5(bp, signal, index, ss_info);
+
 		default:
 			ASSERT(0);
 			break;
@@ -887,6 +1140,31 @@ static enum bp_result get_soc_bb_info_v4_4(
 	return result;
 }
 
+static enum bp_result get_soc_bb_info_v4_5(
+	struct bios_parser *bp,
+	struct bp_soc_bb_info *soc_bb_info)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!soc_bb_info)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
+	soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
+	soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
+
+	return result;
+}
+
 static enum bp_result bios_parser_get_soc_bb_info(
 	struct dc_bios *dcb,
 	struct bp_soc_bb_info *soc_bb_info)
@@ -916,6 +1194,9 @@ static enum bp_result bios_parser_get_soc_bb_info(
 		case 4:
 			result = get_soc_bb_info_v4_4(bp, soc_bb_info);
 			break;
+		case 5:
+			result = get_soc_bb_info_v4_5(bp, soc_bb_info);
+			break;
 		default:
 			break;
 		}
@@ -1023,6 +1304,30 @@ static enum bp_result get_disp_caps_v4_4(
 	return result;
 }
 
+static enum bp_result get_disp_caps_v4_5(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = disp_cntl_tbl->display_caps;
+
+	return result;
+}
+
 static enum bp_result bios_parser_get_lttpr_interop(
 	struct dc_bios *dcb,
 	uint8_t *dce_caps)
@@ -1057,6 +1362,11 @@ static enum bp_result bios_parser_get_lttpr_interop(
 			result = get_disp_caps_v4_4(bp, dce_caps);
 			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
 			break;
+		case 5:
+			result = get_disp_caps_v4_5(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+
 		default:
 			break;
 		}
@@ -1102,6 +1412,10 @@ static enum bp_result bios_parser_get_lttpr_caps(
 			result = get_disp_caps_v4_4(bp, dce_caps);
 			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
+		case 5:
+			result = get_disp_caps_v4_5(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+			break;
 		default:
 			break;
 		}
@@ -1274,8 +1588,17 @@ static bool bios_parser_is_device_id_supported(
 
 	uint32_t mask = get_support_mask_for_device_id(id);
 
-	return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
-								mask) != 0;
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+	        return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
+			break;
+	    case 5:
+			return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
+			break;
+	}
+
+    return false;
 }
 
 static uint32_t bios_parser_get_ss_entry_number(
@@ -1408,12 +1731,21 @@ static void bios_parser_set_scratch_critical_state(
 	bios_set_scratch_critical_state(dcb, state);
 }
 
+struct atom_dig_transmitter_info_header_v5_3 {
+    struct atom_common_table_header table_header;
+    uint16_t dpphy_hdmi_settings_offset;
+    uint16_t dpphy_dvi_settings_offset;
+    uint16_t dpphy_dp_setting_table_offset;
+    uint16_t uniphy_xbar_settings_v2_table_offset;
+    uint16_t dpphy_internal_reg_overide_offset;
+};
+
 static enum bp_result bios_parser_get_firmware_info(
 	struct dc_bios *dcb,
 	struct dc_firmware_info *info)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 	struct atom_common_table_header *header;
 
 	struct atom_data_revision revision;
@@ -1590,6 +1922,11 @@ static enum bp_result get_firmware_info_v3_4(
 	struct atom_data_revision revision;
 	struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
 	struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
+
+	struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
+	struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
+	struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
+
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
@@ -1609,6 +1946,22 @@ static enum bp_result get_firmware_info_v3_4(
 	switch (revision.major) {
 	case 4:
 		switch (revision.minor) {
+		case 5:
+			dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
+							DATA_TABLES(dce_info));
+
+			if (!dce_info_v4_5)
+				return BP_RESULT_BADBIOSTABLE;
+
+			 /* 100MHz expected */
+			info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
+			info->dp_phy_ref_clk             = dce_info_v4_5->dpphy_refclk_10khz * 10;
+			 /* 50MHz expected */
+			info->i2c_engine_ref_clk         = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
+
+			/* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
+			break;
+
 		case 4:
 			dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
 							DATA_TABLES(dce_info));
@@ -1650,6 +2003,45 @@ static enum bp_result get_firmware_info_v3_4(
 					DATA_TABLES(smu_info));
 	get_atom_data_table_revision(header, &revision);
 
+	switch (revision.major) {
+	case 3:
+		switch (revision.minor) {
+		case 5:
+			smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
+							DATA_TABLES(smu_info));
+
+			if (!smu_info_v3_5)
+				return BP_RESULT_BADBIOSTABLE;
+
+			info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case 4:
+		switch (revision.minor) {
+		case 0:
+			smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
+							DATA_TABLES(smu_info));
+
+			if (!smu_info_v4_0)
+				return BP_RESULT_BADBIOSTABLE;
+
+			/* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	default:
+		break;
+	}
+
 	 // We need to convert from 10KHz units into KHz units.
 	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
 
@@ -1675,6 +2067,12 @@ static enum bp_result bios_parser_get_encoder_cap_info(
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	/* encoder cap record not available in v1_5 */
+	if (bp->object_info_tbl.revision.minor == 5)
+		return BP_RESULT_NORECORD;
+#endif
+
 	object = get_bios_object(bp, object_id);
 
 	if (!object)
@@ -1781,6 +2179,42 @@ static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
 	return NULL;
 }
 
+static struct atom_connector_caps_record *get_connector_caps_record(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		offset += header->record_size;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+				!header->record_size)
+			break;
+
+		if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
+			continue;
+
+		if (sizeof(struct atom_connector_caps_record) <= header->record_size)
+			return (struct atom_connector_caps_record *)header;
+	}
+
+	return NULL;
+}
+
 static enum bp_result bios_parser_get_disp_connector_caps_info(
 	struct dc_bios *dcb,
 	struct graphics_object_id object_id,
@@ -1788,25 +2222,116 @@ static enum bp_result bios_parser_get_disp_connector_caps_info(
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct atom_display_object_path_v2 *object;
+
+	struct atom_display_object_path_v3 *object_path_v3;
+	struct atom_connector_caps_record *record_path_v3;
+
 	struct atom_disp_connector_caps_record *record = NULL;
 
 	if (!info)
 		return BP_RESULT_BADINPUT;
 
-	object = get_bios_object(bp, object_id);
+	switch (bp->object_info_tbl.revision.minor) {
+	    case 4:
+	    default:
+		    object = get_bios_object(bp, object_id);
 
-	if (!object)
+		    if (!object)
+			    return BP_RESULT_BADINPUT;
+
+		    record = get_disp_connector_caps_record(bp, object);
+		    if (!record)
+			    return BP_RESULT_NORECORD;
+
+		    info->INTERNAL_DISPLAY =
+			    (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
+		    info->INTERNAL_DISPLAY_BL =
+			    (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
+		    break;
+	    case 5:
+		object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
+
+		if (!object_path_v3)
+			return BP_RESULT_BADINPUT;
+
+		record_path_v3 = get_connector_caps_record(bp, object_path_v3);
+		if (!record_path_v3)
+			return BP_RESULT_NORECORD;
+
+		info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
+									? 1 : 0;
+		info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
+										? 1 : 0;
+		break;
+	}
+
+	return BP_RESULT_OK;
+}
+
+static struct atom_connector_speed_record *get_connector_speed_cap_record(
+	struct bios_parser *bp,
+	struct atom_display_object_path_v3 *object)
+{
+	struct atom_common_record_header *header;
+	uint32_t offset;
+
+	if (!object) {
+		BREAK_TO_DEBUGGER(); /* Invalid object */
+		return NULL;
+	}
+
+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
+
+	for (;;) {
+		header = GET_IMAGE(struct atom_common_record_header, offset);
+
+		if (!header)
+			return NULL;
+
+		offset += header->record_size;
+
+		if (header->record_type == ATOM_RECORD_END_TYPE ||
+				!header->record_size)
+			break;
+
+		if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
+			continue;
+
+		if (sizeof(struct atom_connector_speed_record) <= header->record_size)
+			return (struct atom_connector_speed_record *)header;
+	}
+
+	return NULL;
+}
+
+static enum bp_result bios_parser_get_connector_speed_cap_info(
+	struct dc_bios *dcb,
+	struct graphics_object_id object_id,
+	struct bp_connector_speed_cap_info *info)
+{
+	struct bios_parser *bp = BP_FROM_DCB(dcb);
+	struct atom_display_object_path_v3 *object_path_v3;
+	//struct atom_connector_speed_record *record = NULL;
+	struct atom_connector_speed_record *record;
+
+	if (!info)
+		return BP_RESULT_BADINPUT;
+
+	object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
+
+	if (!object_path_v3)
 		return BP_RESULT_BADINPUT;
 
-	record = get_disp_connector_caps_record(bp, object);
+	record = get_connector_speed_cap_record(bp, object_path_v3);
 	if (!record)
 		return BP_RESULT_NORECORD;
 
-	info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
-									? 1 : 0;
-	info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
-											? 1 : 0;
-
+	info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
+	info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
+	info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
+	info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
+	info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
+	info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
 	return BP_RESULT_OK;
 }
 
@@ -1815,7 +2340,7 @@ static enum bp_result get_vram_info_v23(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_3 *info_v23;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
 						DATA_TABLES(vram_info));
@@ -1834,7 +2359,7 @@ static enum bp_result get_vram_info_v24(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_4 *info_v24;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
 						DATA_TABLES(vram_info));
@@ -1853,7 +2378,7 @@ static enum bp_result get_vram_info_v25(
 	struct dc_vram_info *info)
 {
 	struct atom_vram_info_header_v2_5 *info_v25;
-	enum bp_result result = BP_RESULT_OK;
+	static enum bp_result result = BP_RESULT_OK;
 
 	info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
 						DATA_TABLES(vram_info));
@@ -1878,7 +2403,7 @@ static enum bp_result get_vram_info_v25(
  * integrated_info *info - [out] store and output integrated info
  *
  * @return
- * enum bp_result - BP_RESULT_OK if information is available,
+ * static enum bp_result - BP_RESULT_OK if information is available,
  *                  BP_RESULT_BADBIOSTABLE otherwise.
  */
 static enum bp_result get_integrated_info_v11(
@@ -2369,17 +2894,19 @@ static enum bp_result get_integrated_info_v2_2(
  * integrated_info *info - [out] store and output integrated info
  *
  * @return
- * enum bp_result - BP_RESULT_OK if information is available,
+ * static enum bp_result - BP_RESULT_OK if information is available,
  *                  BP_RESULT_BADBIOSTABLE otherwise.
  */
 static enum bp_result construct_integrated_info(
 	struct bios_parser *bp,
 	struct integrated_info *info)
 {
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 
 	struct atom_common_table_header *header;
 	struct atom_data_revision revision;
+
+	struct clock_voltage_caps temp = {0, 0};
 	uint32_t i;
 	uint32_t j;
 
@@ -2427,8 +2954,10 @@ static enum bp_result construct_integrated_info(
 				info->disp_clk_voltage[j-1].max_supported_clk
 				) {
 				/* swap j and j - 1*/
-				swap(info->disp_clk_voltage[j - 1],
-				     info->disp_clk_voltage[j]);
+				temp = info->disp_clk_voltage[j-1];
+				info->disp_clk_voltage[j-1] =
+					info->disp_clk_voltage[j];
+				info->disp_clk_voltage[j] = temp;
 			}
 		}
 	}
@@ -2441,7 +2970,7 @@ static enum bp_result bios_parser_get_vram_info(
 		struct dc_vram_info *info)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result = BP_RESULT_BADBIOSTABLE;
+	static enum bp_result result = BP_RESULT_BADBIOSTABLE;
 	struct atom_common_table_header *header;
 	struct atom_data_revision revision;
 
@@ -2507,7 +3036,7 @@ static enum bp_result update_slot_layout_info(
 	struct atom_display_object_path_v2 *object;
 	struct atom_bracket_layout_record *record;
 	struct atom_common_record_header *record_header;
-	enum bp_result result;
+	static enum bp_result result;
 	struct bios_parser *bp;
 	struct object_info_table *tbl;
 	struct display_object_info_table_v1_4 *v1_4;
@@ -2613,6 +3142,105 @@ static enum bp_result update_slot_layout_info(
 	return result;
 }
 
+static enum bp_result update_slot_layout_info_v2(
+	struct dc_bios *dcb,
+	unsigned int i,
+	struct slot_layout_info *slot_layout_info)
+{
+	unsigned int record_offset;
+	struct atom_display_object_path_v3 *object;
+	struct atom_bracket_layout_record_v2 *record;
+	struct atom_common_record_header *record_header;
+	static enum bp_result result;
+	struct bios_parser *bp;
+	struct object_info_table *tbl;
+	struct display_object_info_table_v1_5 *v1_5;
+	struct graphics_object_id connector_id;
+
+	record = NULL;
+	record_header = NULL;
+	result = BP_RESULT_NORECORD;
+
+	bp = BP_FROM_DCB(dcb);
+	tbl = &bp->object_info_tbl;
+	v1_5 = tbl->v1_5;
+
+	object = &v1_5->display_path[i];
+	record_offset = (unsigned int)
+		(object->disp_recordoffset) +
+		(unsigned int)(bp->object_info_tbl_offset);
+
+	for (;;) {
+
+		record_header = (struct atom_common_record_header *)
+			GET_IMAGE(struct atom_common_record_header,
+			record_offset);
+		if (record_header == NULL) {
+			result = BP_RESULT_BADBIOSTABLE;
+			break;
+		}
+
+		/* the end of the list */
+		if (record_header->record_type == ATOM_RECORD_END_TYPE ||
+			record_header->record_size == 0)	{
+			break;
+		}
+
+		if (record_header->record_type ==
+			ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
+			sizeof(struct atom_bracket_layout_record_v2)
+			<= record_header->record_size) {
+			record = (struct atom_bracket_layout_record_v2 *)
+				(record_header);
+			result = BP_RESULT_OK;
+			break;
+		}
+
+		record_offset += record_header->record_size;
+	}
+
+	/* return if the record not found */
+	if (result != BP_RESULT_OK)
+		return result;
+
+	/* get slot sizes */
+	connector_id = object_id_from_bios_object_id(object->display_objid);
+
+	slot_layout_info->length = record->bracketlen;
+	slot_layout_info->width = record->bracketwidth;
+	slot_layout_info->num_of_connectors = v1_5->number_of_path;
+	slot_layout_info->connectors[i].position = record->conn_num;
+	slot_layout_info->connectors[i].connector_id = connector_id;
+
+	switch (connector_id.id) {
+	case CONNECTOR_ID_SINGLE_LINK_DVID:
+	case CONNECTOR_ID_DUAL_LINK_DVID:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
+		break;
+
+	case CONNECTOR_ID_HDMI_TYPE_A:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
+		break;
+
+	case CONNECTOR_ID_DISPLAY_PORT:
+	case CONNECTOR_ID_USBC:
+		if (record->mini_type == MINI_TYPE_NORMAL) {
+			slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
+			slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
+		} else {
+			slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
+			slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
+		}
+		break;
+
+	default:
+		slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
+		slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
+	}
+	return result;
+}
 
 static enum bp_result get_bracket_layout_record(
 	struct dc_bios *dcb,
@@ -2621,9 +3249,10 @@ static enum bp_result get_bracket_layout_record(
 {
 	unsigned int i;
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	enum bp_result result;
+	static enum bp_result result;
 	struct object_info_table *tbl;
 	struct display_object_info_table_v1_4 *v1_4;
+	struct display_object_info_table_v1_5 *v1_5;
 
 	if (slot_layout_info == NULL) {
 		DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
@@ -2631,16 +3260,24 @@ static enum bp_result get_bracket_layout_record(
 	}
 	tbl = &bp->object_info_tbl;
 	v1_4 = tbl->v1_4;
+	v1_5 = tbl->v1_5;
 
 	result = BP_RESULT_NORECORD;
-	for (i = 0; i < v1_4->number_of_path; ++i)	{
-
-		if (bracket_layout_id ==
-			v1_4->display_path[i].display_objid) {
-			result = update_slot_layout_info(dcb, i,
-				slot_layout_info);
+	switch (bp->object_info_tbl.revision.minor) {
+		case 4:
+		default:
+			for (i = 0; i < v1_4->number_of_path; ++i)	{
+				if (bracket_layout_id ==
+					v1_4->display_path[i].display_objid) {
+					result = update_slot_layout_info(dcb, i, slot_layout_info);
+					break;
+				}
+			}
+		    break;
+		case 5:
+			for (i = 0; i < v1_5->number_of_path; ++i)
+				result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
 			break;
-		}
 	}
 	return result;
 }
@@ -2650,7 +3287,10 @@ static enum bp_result bios_get_board_layout_info(
 	struct board_layout_info *board_layout_info)
 {
 	unsigned int i;
-	enum bp_result record_result;
+
+	struct bios_parser *bp;
+
+	static enum bp_result record_result;
 
 	const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
 		GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
@@ -2658,6 +3298,9 @@ static enum bp_result bios_get_board_layout_info(
 		0, 0
 	};
 
+
+	bp = BP_FROM_DCB(dcb);
+
 	if (board_layout_info == NULL) {
 		DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
 		return BP_RESULT_BADINPUT;
@@ -2692,99 +3335,6 @@ static uint16_t bios_parser_pack_data_tables(
 	struct dc_bios *dcb,
 	void *dst)
 {
-#ifdef PACK_BIOS_DATA
-	struct bios_parser *bp = BP_FROM_DCB(dcb);
-	struct atom_rom_header_v2_2 *rom_header = NULL;
-	struct atom_rom_header_v2_2 *packed_rom_header = NULL;
-	struct atom_common_table_header *data_tbl_header = NULL;
-	struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL;
-	struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL;
-	struct atom_data_revision tbl_rev = {0};
-	uint16_t *rom_header_offset = NULL;
-	const uint8_t *bios = bp->base.bios;
-	uint8_t *bios_dst = (uint8_t *)dst;
-	uint16_t packed_rom_header_offset;
-	uint16_t packed_masterdatatable_offset;
-	uint16_t packed_data_tbl_offset;
-	uint16_t data_tbl_offset;
-	unsigned int i;
-
-	rom_header_offset =
-		GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
-
-	if (!rom_header_offset)
-		return 0;
-
-	rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
-
-	if (!rom_header)
-		return 0;
-
-	get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
-	if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
-		return 0;
-
-	get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev);
-	if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1))
-		return 0;
-
-	packed_rom_header_offset =
-		OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset);
-
-	packed_masterdatatable_offset =
-		packed_rom_header_offset + rom_header->table_header.structuresize;
-
-	packed_data_tbl_offset =
-		packed_masterdatatable_offset +
-		bp->master_data_tbl->table_header.structuresize;
-
-	packed_rom_header =
-		(struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset);
-
-	packed_master_data_tbl =
-		(struct atom_master_data_table_v2_1 *)(bios_dst +
-		packed_masterdatatable_offset);
-
-	memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
-
-	*((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) =
-		packed_rom_header_offset;
-
-	memcpy(bios_dst + packed_rom_header_offset, rom_header,
-		rom_header->table_header.structuresize);
-
-	packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset;
-
-	memcpy(&packed_master_data_tbl->table_header,
-		&bp->master_data_tbl->table_header,
-		sizeof(bp->master_data_tbl->table_header));
-
-	data_tbl_list = &bp->master_data_tbl->listOfdatatables;
-
-	/* Each data table offset in data table list is 2 bytes,
-	 * we can use that to iterate through listOfdatatables
-	 * without knowing the name of each member.
-	 */
-	for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) {
-		data_tbl_offset = *((uint16_t *)data_tbl_list + i);
-
-		if (data_tbl_offset) {
-			data_tbl_header =
-				(struct atom_common_table_header *)(bios + data_tbl_offset);
-
-			memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header,
-				data_tbl_header->structuresize);
-
-			*((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) =
-				packed_data_tbl_offset;
-
-			packed_data_tbl_offset += data_tbl_header->structuresize;
-		} else {
-			*((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0;
-		}
-	}
-	return packed_data_tbl_offset;
-#endif
 	// TODO: There is data bytes alignment issue, disable it for now.
 	return 0;
 }
@@ -2814,6 +3364,13 @@ static struct atom_dc_golden_table_v1 *bios_get_golden_table(
 			dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
 			*dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
 			break;
+		case 5:
+		default:
+			/* For atom_display_controller_info_v4_5 there is no need to get golden table from
+			 * dc_golden_table_offset as all these fields previously in golden table used for AUX
+			 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
+			 */
+			break;
 		}
 		break;
 	}
@@ -2916,6 +3473,7 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.bios_parser_destroy = firmware_parser_destroy,
 
 	.get_board_layout_info = bios_get_board_layout_info,
+	/* TODO: use this fn in hw init?*/
 	.pack_data_tables = bios_parser_pack_data_tables,
 
 	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
@@ -2929,6 +3487,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.get_lttpr_caps = bios_parser_get_lttpr_caps,
 
 	.get_lttpr_interop = bios_parser_get_lttpr_interop,
+
+	.get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
 };
 
 static bool bios_parser2_construct(
@@ -3002,6 +3562,16 @@ static bool bios_parser2_construct(
 			return false;
 
 		bp->object_info_tbl.v1_4 = tbl_v1_4;
+	} else if (bp->object_info_tbl.revision.major == 1
+		&& bp->object_info_tbl.revision.minor == 5) {
+		struct display_object_info_table_v1_5 *tbl_v1_5;
+
+		tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
+			bp->object_info_tbl_offset);
+		if (!tbl_v1_5)
+			return false;
+
+		bp->object_info_tbl.v1_5 = tbl_v1_5;
 	} else {
 		ASSERT(0);
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
index bf1f5c86e65c..41d02d473082 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
@@ -40,6 +40,7 @@ struct object_info_table {
 	struct atom_data_revision revision;
 	union {
 		struct display_object_info_table_v1_4 *v1_4;
+		struct display_object_info_table_v1_5 *v1_5;
 	};
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 32efa92422e8..818a529cacc3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -522,8 +522,8 @@ static enum bp_result transmitter_control_v2(
 		 */
 		params.acConfig.ucEncoderSel = 1;
 
-	if (CONNECTOR_ID_DISPLAY_PORT == connector_id
-		|| CONNECTOR_ID_USBC == connector_id)
+	if (CONNECTOR_ID_DISPLAY_PORT == connector_id ||
+	    CONNECTOR_ID_USBC == connector_id)
 		/* Bit4: DP connector flag
 		 * =0 connector is none-DP connector
 		 * =1 connector is DP connector
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index f3792286f571..f22593bcb862 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -77,6 +77,8 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCN_VERSION_3_1:
 	case DCN_VERSION_3_15:
 	case DCN_VERSION_3_16:
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 817871917632..7b505e1e9308 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -172,4 +172,38 @@ AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316)
 
+###############################################################################
+# DCN32
+###############################################################################
+CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o
+
+AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32))
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse2
+endif
+endif
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 772bffda68cc..d145dcbca778 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -45,6 +45,7 @@
 #include "dcn31/dcn31_clk_mgr.h"
 #include "dcn315/dcn315_clk_mgr.h"
 #include "dcn316/dcn316_clk_mgr.h"
+#include "dcn32/dcn32_clk_mgr.h"
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -316,8 +317,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 		return &clk_mgr->base.base;
 	}
 		break;
-#endif
+	case AMDGPU_FAMILY_GC_11_0_0: {
+	    struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
+
+	    if (clk_mgr == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	    }
 
+	    dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+	    return &clk_mgr->base;
+	    break;
+	}
+#endif
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
@@ -360,6 +372,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 		dcn316_clk_mgr_destroy(clk_mgr);
 		break;
 
+	case AMDGPU_FAMILY_GC_11_0_0:
+		dcn32_clk_mgr_destroy(clk_mgr);
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index cac80ba69072..0d30d1d9d67e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -126,16 +126,24 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 
 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)
 {
-	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
-	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
-
-	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
-	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+	int dpp_divider = 0;
+	int disp_divider = 0;
+	uint32_t dppclk_wdivider = 0;
+	uint32_t dispclk_wdivider = 0;
 	uint32_t current_dispclk_wdivider;
 	uint32_t i;
 
+	if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
+		return;
+
+	dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+		* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+	disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+		* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+
+	dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+	dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+
 	REG_GET(DENTIST_DISPCLK_CNTL,
 			DENTIST_DISPCLK_WDIVIDER, &current_dispclk_wdivider);
 
@@ -436,7 +444,6 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
 		clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 				* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
 	}
-
 }
 
 void dcn2_get_clock(struct clk_mgr *clk_mgr,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 30c6f9cd717f..4137394a6ace 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -41,6 +41,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x1
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_PowerUpGfx                   0x3
@@ -97,6 +103,12 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
 	/* First clear response register */
 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 5ed6a93d1708..914708cefc79 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -129,7 +129,7 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 
 	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
-	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
@@ -137,6 +137,14 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
+	clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;
+	clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
+	clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;
+	clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
+	clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;
+	clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
+	clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;
+	clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 
 	/* Set D - MALL - SR enter and exit times adjusted for MALL */
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
@@ -517,6 +525,8 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
 	if (!clk_mgr->smu_present)
 		return;
 
+	/* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */
+
 	clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 
 	for (i = 0; i < MAX_PIPES * 2; i++) {
@@ -620,7 +630,8 @@ void dcn3_clk_mgr_construct(
 
 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
 {
-	kfree(clk_mgr->base.bw_params);
+	if (clk_mgr->base.bw_params)
+		kfree(clk_mgr->base.bw_params);
 
 	if (clk_mgr->wm_range_table)
 		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
index dd4a0bd72458..2cd95ec38266 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
@@ -26,6 +26,66 @@
 #ifndef __DCN30_CLK_MGR_H__
 #define __DCN30_CLK_MGR_H__
 
+//CLK1_CLK_PLL_REQ
+#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
+//CLK1_CLK0_DFS_CNTL
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT                                                               0x0
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK                                                                 0x0000007FL
+/*DPREF clock related*/
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+
+#define mmCLK0_CLK2_DFS_CNTL                            0x16C55
+#define mmCLK00_CLK0_CLK2_DFS_CNTL                      0x16C55
+#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E55
+#define mmCLK02_CLK0_CLK2_DFS_CNTL                      0x17055
+
+#define mmCLK0_CLK3_DFS_CNTL                            0x16C60
+#define mmCLK00_CLK0_CLK3_DFS_CNTL                      0x16C60
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E60
+#define mmCLK02_CLK0_CLK3_DFS_CNTL                      0x17060
+#define mmCLK03_CLK0_CLK3_DFS_CNTL                      0x17260
+
+#define mmCLK0_CLK_PLL_REQ                              0x16C10
+#define mmCLK00_CLK0_CLK_PLL_REQ                        0x16C10
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E10
+#define mmCLK02_CLK0_CLK_PLL_REQ                        0x17010
+#define mmCLK03_CLK0_CLK_PLL_REQ                        0x17210
+
+#define mmCLK1_CLK_PLL_REQ                              0x1B00D
+#define mmCLK10_CLK1_CLK_PLL_REQ                        0x1B00D
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#define mmCLK12_CLK1_CLK_PLL_REQ                        0x1B40D
+#define mmCLK13_CLK1_CLK_PLL_REQ                        0x1B60D
+
+#define mmCLK2_CLK_PLL_REQ                              0x17E0D
+
+/*AMCLK*/
+
+#define mmCLK11_CLK1_CLK0_DFS_CNTL                      0x1B23F
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+
+#endif
 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
 
 void dcn3_clk_mgr_construct(struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index bfc960579760..1fbf1c105dc1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -28,6 +28,8 @@
 
 #include "clk_mgr_internal.h"
 #include "reg_helper.h"
+#include "dm_helpers.h"
+
 #include "dalsmc.h"
 #include "dcn30_smu11_driver_if.h"
 
@@ -74,6 +76,7 @@ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un
 
 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
 {
+	uint32_t result;
 	/* Wait for response register to be ready */
 	dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
 
@@ -86,8 +89,14 @@ static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint
 	/* Trigger the message transaction by writing the message ID */
 	REG_WRITE(DAL_MSG_REG, msg_id);
 
+	result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	if (IS_SMU_TIMEOUT(result)) {
+		dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000);
+	}
+
 	/* Wait for response */
-	if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
+	if (result == DALSMC_Result_OK) {
 		if (param_out)
 			*param_out = REG_READ(DAL_ARG_REG);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index 1cae01a91a69..d8f03328558b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -41,6 +41,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_SetDispclkFreq               0x4
 #define VBIOSSMC_MSG_SetDprefclkFreq              0x5
@@ -96,6 +102,12 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 
 	result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
 
+	smu_print("SMU response after wait: %d\n", result);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
 	/* First clear response register */
 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index c5d7d075026f..6a17f7ed4d01 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -40,6 +40,12 @@
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x1
 #define VBIOSSMC_MSG_GetSmuVersion                0x2
 #define VBIOSSMC_MSG_PowerUpGfx                   0x3
@@ -104,6 +110,8 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index fb4ae800e919..f4381725b210 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -550,7 +550,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
 	}
-	ASSERT(bw_params->clk_table.entries[i].dcfclk_mhz);
+	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
 	bw_params->vram_type = bios_info->memory_type;
 	bw_params->num_channels = bios_info->ma_channel_number;
 	if (!bw_params->num_channels)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 2600313fea57..74a78fda62fb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -70,6 +70,12 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D
 #define REG_NBIO(reg_name) \
 	(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define mmMP1_C2PMSG_3                            0x3B1050C
 
 #define VBIOSSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
@@ -132,6 +138,8 @@ static int dcn315_smu_send_msg_with_param(
 	result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index dceec4b96052..b2d1f24cfb80 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -58,6 +58,12 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000
 #define FN(reg_name, field) \
 	FD(reg_name##__##field)
 
+#include "logger_types.h"
+#undef DC_LOGGER
+#define DC_LOGGER \
+	CTX->logger
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
 #define VBIOSSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
 #define VBIOSSMC_MSG_GetPmfwVersion               0x02 ///< Get PMFW version
 #define VBIOSSMC_MSG_Spare0                       0x03 ///< Spare0
@@ -120,6 +126,8 @@ static int dcn316_smu_send_msg_with_param(
 	result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
 	ASSERT(result == VBIOSSMC_Result_OK);
 
+	smu_print("SMU response after wait: %d\n", result);
+
 	if (result == VBIOSSMC_Status_BUSY) {
 		return -1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
new file mode 100644
index 000000000000..c427be6add8a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef DALSMC_H
+#define DALSMC_H
+
+#define DALSMC_VERSION 0x1
+
+// SMU Response Codes:
+#define DALSMC_Result_OK                   0x1
+#define DALSMC_Result_Failed               0xFF
+#define DALSMC_Result_UnknownCmd           0xFE
+#define DALSMC_Result_CmdRejectedPrereq    0xFD
+#define DALSMC_Result_CmdRejectedBusy      0xFC
+
+// Message Definitions:
+#define DALSMC_MSG_TestMessage                    0x1
+#define DALSMC_MSG_GetSmuVersion                  0x2
+#define DALSMC_MSG_GetDriverIfVersion             0x3
+#define DALSMC_MSG_GetMsgHeaderVersion            0x4
+#define DALSMC_MSG_SetDalDramAddrHigh             0x5
+#define DALSMC_MSG_SetDalDramAddrLow              0x6
+#define DALSMC_MSG_TransferTableSmu2Dram          0x7
+#define DALSMC_MSG_TransferTableDram2Smu          0x8
+#define DALSMC_MSG_SetHardMinByFreq               0x9
+#define DALSMC_MSG_SetHardMaxByFreq               0xA
+#define DALSMC_MSG_GetDpmFreqByIndex              0xB
+#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC
+#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD
+#define DALSMC_MSG_NumOfDisplays                  0xE
+#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF
+#define DALSMC_MSG_BacoAudioD3PME                 0x10
+#define DALSMC_MSG_SetFclkSwitchAllow             0x11
+#define DALSMC_MSG_SetCabForUclkPstate            0x12
+#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13
+#define DALSMC_Message_Count                      0x14
+
+typedef enum {
+	FCLK_SWITCH_DISALLOW,
+	FCLK_SWITCH_ALLOW,
+} FclkSwitchAllow_e;
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
new file mode 100644
index 000000000000..113f93b3d3b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -0,0 +1,862 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+#include "dcn32/dcn32_clk_mgr_smu_msg.h"
+#include "dcn20/dcn20_clk_mgr.h"
+#include "dce100/dce_clk_mgr.h"
+#include "dcn31/dcn31_clk_mgr.h"
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dm_helpers.h"
+#include "dc_link_dp.h"
+
+#include "atomfirmware.h"
+#include "smu13_driver_if.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "dcn32/dcn32_clk_mgr.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+
+#define mmCLK1_CLK_PLL_REQ                              0x16E37
+#define mmCLK1_CLK0_DFS_CNTL                            0x16E69
+#define mmCLK1_CLK1_DFS_CNTL                            0x16E6C
+#define mmCLK1_CLK2_DFS_CNTL                            0x16E6F
+#define mmCLK1_CLK3_DFS_CNTL                            0x16E72
+#define mmCLK1_CLK4_DFS_CNTL                            0x16E75
+
+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffUL
+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000UL
+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000UL
+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
+
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E37
+#define mmCLK01_CLK0_CLK0_DFS_CNTL                      0x16E64
+#define mmCLK01_CLK0_CLK1_DFS_CNTL                      0x16E67
+#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E6A
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E6D
+#define mmCLK01_CLK0_CLK4_DFS_CNTL                      0x16E70
+
+#define CLK0_CLK_PLL_REQ__FbMult_int_MASK               0x000001ffL
+#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000f000L
+#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK              0xffff0000L
+#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT             0x00000000
+#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT            0x0000000c
+#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT            0x00000010
+
+#undef FN
+#define FN(reg_name, field_name) \
+	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
+
+#define REG(reg) \
+	(clk_mgr->regs->reg)
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define CLK_SR_DCN32(reg_name)\
+	.reg_name = mm ## reg_name
+
+static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
+	CLK_REG_LIST_DCN32()
+};
+
+static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
+	CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
+	CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define CLK_SR_DCN321(reg_name, block, inst)\
+	.reg_name = mm ## block ## _ ## reg_name
+
+static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
+	CLK_REG_LIST_DCN321()
+};
+
+static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
+	CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
+};
+
+static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
+	CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
+};
+
+
+/* Query SMU for all clock states for a particular clock */
+static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
+		unsigned int *num_levels)
+{
+	unsigned int i;
+	char *entry_i = (char *)entry_0;
+
+	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
+
+	if (ret & (1 << 31))
+		/* fine-grained, only min and max */
+		*num_levels = 2;
+	else
+		/* discrete, a number of fixed states */
+		/* will set num_levels to 0 on failure */
+		*num_levels = ret & 0xFF;
+
+	/* if the initial message failed, num_levels will be 0 */
+	for (i = 0; i < *num_levels; i++) {
+		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
+		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
+	}
+}
+
+static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
+{
+	/* defaults */
+	double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
+	double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
+	double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
+	double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
+	/* For min clocks use as reported by PM FW and report those as min */
+	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
+	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+	uint16_t setb_min_uclk_mhz		= min_uclk_mhz;
+	uint16_t setb_min_dcfclk_mhz	= min_dcfclk_mhz;
+	/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
+	if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz)
+		setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
+		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
+
+	/* Set A - Normal - default values */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
+
+	/* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
+
+	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
+	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
+	if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
+		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
+		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
+		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
+		clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
+		clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
+	}
+	/* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
+	/* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
+	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
+}
+
+void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int num_levels;
+
+	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
+	clk_mgr_base->clks.p_state_change_support = true;
+	clk_mgr_base->clks.prev_p_state_change_support = true;
+	clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
+	clk_mgr->smu_present = false;
+
+	if (!clk_mgr_base->bw_params)
+		return;
+
+	if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
+		clk_mgr->smu_present = true;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn30_smu_check_driver_if_version(clk_mgr);
+	dcn30_smu_check_msg_header_version(clk_mgr);
+
+	/* DCFCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
+			&num_levels);
+
+	/* SOCCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
+					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
+					&num_levels);
+	/* DTBCLK */
+	if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
+		dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
+				&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
+				&num_levels);
+
+	/* DISPCLK */
+	dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
+			&num_levels);
+
+	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
+		unsigned int i;
+
+		for (i = 0; i < num_levels; i++)
+			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
+				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
+					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
+	}
+
+	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
+		unsigned int i;
+
+		for (i = 0; i < num_levels; i++)
+			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
+					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
+				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
+					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
+	}
+
+	/* Get UCLK, update bounding box */
+	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
+
+	/* WM range table */
+	dcn32_build_wm_range_table(clk_mgr);
+}
+
+static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
+			struct dc_state *context,
+			int ref_dtbclk_khz)
+{
+	struct dccg *dccg = clk_mgr->dccg;
+	uint32_t tg_mask = 0;
+	int i;
+
+	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		struct dtbclk_dto_params dto_params = {0};
+
+		/* use mask to program DTO once per tg */
+		if (pipe_ctx->stream_res.tg &&
+				!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
+			tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
+
+			dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
+			dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+
+			if (is_dp_128b_132b_signal(pipe_ctx)) {
+				dto_params.pixclk_khz = pipe_ctx->stream->phy_pix_clk;
+
+				if (pipe_ctx->stream_res.audio != NULL)
+					dto_params.req_audio_dtbclk_khz = 24000;
+			}
+
+			dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
+			//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
+		}
+	}
+}
+
+/* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
+ * update DPPCLK to be the exact frequency that will be set after the DPPCLK
+ * divider is updated. This will prevent rounding issues that could cause DPP
+ * refclk and DPP DTO to not match up.
+ */
+static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
+{
+	int dpp_divider = 0;
+	int disp_divider = 0;
+
+	if (new_clocks->dppclk_khz) {
+		dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
+		new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
+	}
+	if (new_clocks->dispclk_khz > 0) {
+		disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
+		new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
+	}
+}
+
+static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
+			struct dc_state *context,
+			bool safe_to_lower)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int display_count;
+	bool update_dppclk = false;
+	bool update_dispclk = false;
+	bool enter_display_off = false;
+	bool dpp_clock_lowered = false;
+	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+	bool force_reset = false;
+	bool update_uclk = false, update_fclk = false;
+	bool p_state_change_support;
+	bool fclk_p_state_change_support;
+	int total_plane_count;
+
+	if (dc->work_arounds.skip_clock_update)
+		return;
+
+	if (clk_mgr_base->clks.dispclk_khz == 0 ||
+			(dc->debug.force_clock_mode & 0x1)) {
+		/* This is from resume or boot up, if forced_clock cfg option used,
+		 * we bypass program dispclk and DPPCLK, but need set them for S3.
+		 */
+		force_reset = true;
+
+		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
+
+		/* Force_clock_mode 0x1:  force reset the clock even it is the same clock
+		 * as long as it is in Passive level.
+		 */
+	}
+	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
+
+	if (display_count == 0)
+		enter_display_off = true;
+
+	if (clk_mgr->smu_present) {
+		if (enter_display_off == safe_to_lower)
+			dcn30_smu_set_num_of_displays(clk_mgr, display_count);
+
+		if (dc->debug.force_min_dcfclk_mhz > 0)
+			new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
+					new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
+
+		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+			clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+		}
+
+		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+			clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+			dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
+		}
+
+		if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
+			/* We don't actually care about socclk, don't notify SMU of hard min */
+			clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
+
+		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+		clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
+		clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
+
+		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
+				clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
+			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
+			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
+		}
+
+		total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
+		p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
+		fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
+		if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
+			clk_mgr_base->clks.p_state_change_support = p_state_change_support;
+
+			/* to disable P-State switching, set UCLK min = max */
+			if (!clk_mgr_base->clks.p_state_change_support)
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+						clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+		}
+
+		if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
+				clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
+			clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
+
+			/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
+			if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) {
+				/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
+				dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
+			}
+		}
+
+		/* Always update saved value, even if new value not set due to P-State switching unsupported */
+		if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
+			clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
+			update_uclk = true;
+		}
+
+		/* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
+		if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
+			update_fclk = true;
+		}
+
+		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
+		if (clk_mgr_base->clks.p_state_change_support &&
+				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+
+		if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
+			/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
+			dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
+		}
+
+		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
+				clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
+			clk_mgr_base->clks.num_ways = new_clocks->num_ways;
+			dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
+		}
+	}
+
+	dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
+		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
+			dpp_clock_lowered = true;
+
+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+
+		if (clk_mgr->smu_present && !dpp_clock_lowered)
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+
+		update_dppclk = true;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+
+		if (clk_mgr->smu_present)
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+
+		update_dispclk = true;
+	}
+
+	if (!new_clocks->dtbclk_en) {
+		new_clocks->ref_dtbclk_khz = 0;
+	}
+
+	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
+	if (!dc->debug.disable_dtb_ref_clk_switch &&
+			should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
+		/* DCCG requires KHz precision for DTBCLK */
+		clk_mgr_base->clks.ref_dtbclk_khz =
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
+
+		dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
+	}
+
+	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+		if (dpp_clock_lowered) {
+			/* if clock is being lowered, increase DTO before lowering refclk */
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+			dcn20_update_clocks_update_dentist(clk_mgr, context);
+			if (clk_mgr->smu_present)
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+		} else {
+			/* if clock is being raised, increase refclk before lowering DTO */
+			if (update_dppclk || update_dispclk)
+				dcn20_update_clocks_update_dentist(clk_mgr, context);
+			/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
+			 * that we do not lower dto when it is not safe to lower. We do not need to
+			 * compare the current and new dppclk before calling this function.
+			 */
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+		}
+	}
+
+	if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
+		/*update dmcu for wait_loop count*/
+		dmcu->funcs->set_psr_wait_loop(dmcu,
+				clk_mgr_base->clks.dispclk_khz / 1000 / 7);
+}
+
+static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+		struct fixed31_32 pll_req;
+		uint32_t pll_req_reg = 0;
+
+		/* get FbMult value */
+		if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
+			pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
+		else
+			pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
+
+		/* set up a fixed-point number
+		 * this works because the int part is on the right edge of the register
+		 * and the frac part is on the left edge
+		 */
+			pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
+		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
+
+		/* multiply by REFCLK period */
+		pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
+
+		return dc_fixpt_floor(pll_req);
+}
+
+static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	uint32_t dprefclk_did = 0;
+	uint32_t dcfclk_did = 0;
+	uint32_t dtbclk_did = 0;
+	uint32_t dispclk_did = 0;
+	uint32_t dppclk_did = 0;
+	uint32_t target_div = 0;
+
+	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
+		/* DFS Slice 0 is used for DISPCLK */
+		dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
+		/* DFS Slice 1 is used for DPPCLK */
+		dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
+		/* DFS Slice 2 is used for DPREFCLK */
+		dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
+		/* DFS Slice 3 is used for DCFCLK */
+		dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
+		/* DFS Slice 4 is used for DTBCLK */
+		dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
+	} else {
+		/* DFS Slice 0 is used for DISPCLK */
+		dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
+		/* DFS Slice 1 is used for DPPCLK */
+		dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
+		/* DFS Slice 2 is used for DPREFCLK */
+		dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
+		/* DFS Slice 3 is used for DCFCLK */
+		dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
+		/* DFS Slice 4 is used for DTBCLK */
+		dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
+	}
+
+	/* Convert DISPCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dispclk_did);
+	//Get dispclk in khz
+	regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DISPCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dppclk_did);
+	//Get dppclk in khz
+	regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DPREFCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dprefclk_did);
+	//Get dprefclk in khz
+	regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DCFCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dcfclk_did);
+	//Get dcfclk in khz
+	regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+	/* Convert DTBCLK DFS Slice DID to divider*/
+	target_div = dentist_get_divider_from_did(dtbclk_did);
+	//Get dtbclk in khz
+	regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+}
+
+static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
+{
+	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
+	int ss_info_num = bp->funcs->get_ss_entry_number(
+			bp, AS_SIGNAL_TYPE_GPU_PLL);
+
+	if (ss_info_num) {
+		struct spread_spectrum_info info = { { 0 } };
+		enum bp_result result = bp->funcs->get_spread_spectrum_info(
+				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
+
+		/* SSInfo.spreadSpectrumPercentage !=0 would be sign
+		 * that SS is enabled
+		 */
+		if (result == BP_RESULT_OK &&
+				info.spread_spectrum_percentage != 0) {
+			clk_mgr->ss_on_dprefclk = true;
+			clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
+
+			if (info.type.CENTER_MODE == 0) {
+				/* Currently for DP Reference clock we
+				 * need only SS percentage for
+				 * downspread
+				 */
+				clk_mgr->dprefclk_ss_percentage =
+						info.spread_spectrum_percentage;
+			}
+		}
+	}
+}
+static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+	unsigned int i;
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (!table)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	/* collect valid ranges, place in pmfw table */
+	for (i = 0; i < WM_SET_COUNT; i++)
+		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
+			table->Watermarks.WatermarkRow[i].WmSetting = i;
+			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
+		}
+	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
+	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
+	dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
+static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (current_mode) {
+		if (clk_mgr_base->clks.p_state_change_support)
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+		else
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+	} else {
+		dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
+				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+	}
+}
+
+/* Set max memclk to highest DPM value */
+static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
+			clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+}
+
+/* Get current memclk states, update bounding box */
+static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	unsigned int num_levels;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	/* Refresh memclk states */
+	dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
+			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
+			&num_levels);
+	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
+
+	/* Refresh bounding box */
+	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
+			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
+}
+
+static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
+					struct dc_clocks *b)
+{
+	if (a->dispclk_khz != b->dispclk_khz)
+		return false;
+	else if (a->dppclk_khz != b->dppclk_khz)
+		return false;
+	else if (a->dcfclk_khz != b->dcfclk_khz)
+		return false;
+	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+		return false;
+	else if (a->dramclk_khz != b->dramclk_khz)
+		return false;
+	else if (a->p_state_change_support != b->p_state_change_support)
+		return false;
+	else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
+		return false;
+
+	return true;
+}
+
+static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn32_smu_set_pme_workaround(clk_mgr);
+}
+
+static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	return clk_mgr->smu_present;
+}
+
+
+static struct clk_mgr_funcs dcn32_funcs = {
+		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+		.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
+		.update_clocks = dcn32_update_clocks,
+		.dump_clk_registers = dcn32_dump_clk_registers,
+		.init_clocks = dcn32_init_clocks,
+		.notify_wm_ranges = dcn32_notify_wm_ranges,
+		.set_hard_min_memclk = dcn32_set_hard_min_memclk,
+		.set_hard_max_memclk = dcn32_set_hard_max_memclk,
+		.get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
+		.are_clock_states_equal = dcn32_are_clock_states_equal,
+		.enable_pme_wa = dcn32_enable_pme_wa,
+		.is_smu_present = dcn32_is_smu_present,
+};
+
+void dcn32_clk_mgr_construct(
+		struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg)
+{
+	clk_mgr->base.ctx = ctx;
+	clk_mgr->base.funcs = &dcn32_funcs;
+	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
+		clk_mgr->regs = &clk_mgr_regs_dcn321;
+		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
+		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
+	} else {
+		clk_mgr->regs = &clk_mgr_regs_dcn32;
+		clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
+		clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
+	}
+
+	clk_mgr->dccg = dccg;
+	clk_mgr->dfs_bypass_disp_clk = 0;
+
+	clk_mgr->dprefclk_ss_percentage = 0;
+	clk_mgr->dprefclk_ss_divider = 1000;
+	clk_mgr->ss_on_dprefclk = false;
+	clk_mgr->dfs_ref_freq_khz = 100000;
+
+	/* Changed from DCN3.2_clock_frequency doc to match
+	 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
+	 * dprefclk DID divider
+	 */
+	clk_mgr->base.dprefclk_khz = 716666;
+	if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
+		//initialize DTB ref clock value if DPM disabled
+		if (ctx->dce_version == DCN_VERSION_3_21)
+			clk_mgr->base.clks.ref_dtbclk_khz = 477800;
+		else
+			clk_mgr->base.clks.ref_dtbclk_khz = 268750;
+	}
+
+	/* integer part is now VCO frequency in kHz */
+	clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
+
+	/* in case we don't get a value from the register, use default */
+	if (clk_mgr->base.dentist_vco_freq_khz == 0)
+		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
+
+	if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
+			clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
+		clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
+	}
+
+	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
+		clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
+	}
+	dcn32_clock_read_ss_info(clk_mgr);
+
+	clk_mgr->dfs_bypass_enabled = false;
+
+	clk_mgr->smu_present = false;
+
+	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
+
+	/* need physical address of table to give to PMFW */
+	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
+			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
+			&clk_mgr->wm_range_table_addr);
+}
+
+void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
+{
+	if (clk_mgr->base.bw_params)
+		kfree(clk_mgr->base.bw_params);
+
+	if (clk_mgr->wm_range_table)
+		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
+				clk_mgr->wm_range_table);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
new file mode 100644
index 000000000000..57e09c7c95f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DCN32_CLK_MGR_H_
+#define __DCN32_CLK_MGR_H_
+
+void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
+
+void dcn32_clk_mgr_construct(struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg);
+
+void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
+
+
+
+#endif /* __DCN32_CLK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
new file mode 100644
index 000000000000..3137b987f0a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn32_clk_mgr_smu_msg.h"
+
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+#include "dalsmc.h"
+#include "smu13_driver_if.h"
+
+#define mmDAL_MSG_REG  0x1628A
+#define mmDAL_ARG_REG  0x16273
+#define mmDAL_RESP_REG 0x16274
+
+#define REG(reg_name) \
+	mm ## reg_name
+
+#include "logger_types.h"
+
+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
+
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+	uint32_t reg = 0;
+
+	do {
+		reg = REG_READ(DAL_RESP_REG);
+		if (reg)
+			break;
+
+		if (delay_us >= 1000)
+			msleep(delay_us/1000);
+		else if (delay_us > 0)
+			udelay(delay_us);
+	} while (max_retries--);
+
+	return reg;
+}
+
+static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
+{
+	/* Wait for response register to be ready */
+	dcn32_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	/* Clear response register */
+	REG_WRITE(DAL_RESP_REG, 0);
+
+	/* Set the parameter register for the SMU message */
+	REG_WRITE(DAL_ARG_REG, param_in);
+
+	/* Trigger the message transaction by writing the message ID */
+	REG_WRITE(DAL_MSG_REG, msg_id);
+
+	/* Wait for response */
+	if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
+		if (param_out)
+			*param_out = REG_READ(DAL_ARG_REG);
+
+		return true;
+	}
+
+	return false;
+}
+
+void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	smu_print("FCLK P-state support value is : %d\n", enable);
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);
+}
+
+void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
+{
+	smu_print("Numways for SubVP : %d\n", num_ways);
+
+	dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL);
+}
+
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+	smu_print("SMU Transfer WM table DRAM 2 SMU\n");
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
+}
+
+void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
+{
+	smu_print("SMU Set PME workaround\n");
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+		DALSMC_MSG_BacoAudioD3PME, 0, NULL);
+}
+
+/* Returns the actual frequency that was set in MHz, 0 on failure */
+unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
+{
+	uint32_t response = 0;
+
+	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
+	uint32_t param = (clk << 16) | freq_mhz;
+
+	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
+
+	dcn32_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_SetHardMinByFreq, param, &response);
+
+	smu_print("SMU Frequency set = %d KHz\n", response);
+
+	return response;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
new file mode 100644
index 000000000000..a68038a41972
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_CLK_MGR_SMU_MSG_H_
+#define __DCN32_CLK_MGR_SMU_MSG_H_
+
+#include "core_types.h"
+#include "dcn30/dcn30_clk_mgr_smu_msg.h"
+
+#define FCLK_PSTATE_NOTSUPPORTED       0x00
+#define FCLK_PSTATE_SUPPORTED          0x01
+
+/* TODO Remove this MSG ID define after it becomes available in dalsmc */
+#define DALSMC_MSG_SetCabForUclkPstate	0x12
+#define DALSMC_Result_OK				0x1
+
+void
+dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
+void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
+void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
+
+#endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h
new file mode 100644
index 000000000000..d30fbbdd1792
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h
@@ -0,0 +1,63 @@
+// This is a stripped-down version of the smu13_driver_if.h file for the relevant DAL interfaces.
+
+#define SMU13_DRIVER_IF_VERSION  0x18
+
+//Only Clks that have DPM descriptors are listed here
+typedef enum {
+	PPCLK_GFXCLK = 0,
+	PPCLK_SOCCLK,
+	PPCLK_UCLK,
+	PPCLK_FCLK,
+	PPCLK_DCLK_0,
+	PPCLK_VCLK_0,
+	PPCLK_DCLK_1,
+	PPCLK_VCLK_1,
+	PPCLK_DISPCLK,
+	PPCLK_DPPCLK,
+	PPCLK_DPREFCLK,
+	PPCLK_DCFCLK,
+	PPCLK_DTBCLK,
+	PPCLK_COUNT,
+} PPCLK_e;
+
+typedef struct {
+	uint8_t  WmSetting;
+	uint8_t  Flags;
+	uint8_t  Padding[2];
+
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+	WATERMARKS_CLOCK_RANGE = 0,
+	WATERMARKS_DUMMY_PSTATE,
+	WATERMARKS_MALL,
+	WATERMARKS_COUNT,
+} WATERMARKS_FLAGS_e;
+
+typedef struct {
+	// Watermarks
+	WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
+} Watermarks_t;
+
+typedef struct {
+	Watermarks_t Watermarks;
+	uint32_t  Spare[16];
+
+	uint32_t     MmHubPadding[8]; // SMU internal use
+} WatermarksExternal_t;
+
+// Table types
+#define TABLE_PMFW_PPTABLE            0
+#define TABLE_COMBO_PPTABLE           1
+#define TABLE_WATERMARKS              2
+#define TABLE_AVFS_PSM_DEBUG          3
+#define TABLE_PMSTATUSLOG             4
+#define TABLE_SMU_METRICS             5
+#define TABLE_DRIVER_SMU_CONFIG       6
+#define TABLE_ACTIVITY_MONITOR_COEFF  7
+#define TABLE_OVERDRIVE               8
+#define TABLE_I2C_COMMANDS            9
+#define TABLE_DRIVER_INFO             10
+#define TABLE_COUNT                   11
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
new file mode 100644
index 000000000000..deeb85047e7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef SMU13_DRIVER_IF_DCN32_H
+#define SMU13_DRIVER_IF_DCN32_H
+
+// *** IMPORTANT ***
+// PMFW TEAM: Always increment the interface version on any change to this file
+#define SMU13_DRIVER_IF_VERSION  0x18
+
+//Only Clks that have DPM descriptors are listed here
+typedef enum {
+  PPCLK_GFXCLK = 0,
+  PPCLK_SOCCLK,
+  PPCLK_UCLK,
+  PPCLK_FCLK,
+  PPCLK_DCLK_0,
+  PPCLK_VCLK_0,
+  PPCLK_DCLK_1,
+  PPCLK_VCLK_1,
+  PPCLK_DISPCLK,
+  PPCLK_DPPCLK,
+  PPCLK_DPREFCLK,
+  PPCLK_DCFCLK,
+  PPCLK_DTBCLK,
+  PPCLK_COUNT,
+} PPCLK_e;
+
+typedef enum {
+  UCLK_DIV_BY_1 = 0,
+  UCLK_DIV_BY_2,
+  UCLK_DIV_BY_4,
+  UCLK_DIV_BY_8,
+} UCLK_DIV_e;
+
+typedef struct {
+  uint8_t  WmSetting;
+  uint8_t  Flags;
+  uint8_t  Padding[2];
+
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+  WATERMARKS_CLOCK_RANGE = 0,
+  WATERMARKS_DUMMY_PSTATE,
+  WATERMARKS_MALL,
+  WATERMARKS_COUNT,
+} WATERMARKS_FLAGS_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
+} Watermarks_t;
+
+typedef struct {
+  Watermarks_t Watermarks;
+  uint32_t  Spare[16];
+
+  uint32_t     MmHubPadding[8]; // SMU internal use
+} WatermarksExternal_t;
+
+// These defines are used with the following messages:
+// SMC_MSG_TransferTableDram2Smu
+// SMC_MSG_TransferTableSmu2Dram
+
+// Table transfer status
+#define TABLE_TRANSFER_OK         0x0
+#define TABLE_TRANSFER_FAILED     0xFF
+#define TABLE_TRANSFER_PENDING    0xAB
+
+// Table types
+#define TABLE_PMFW_PPTABLE            0
+#define TABLE_COMBO_PPTABLE           1
+#define TABLE_WATERMARKS              2
+#define TABLE_AVFS_PSM_DEBUG          3
+#define TABLE_PMSTATUSLOG             4
+#define TABLE_SMU_METRICS             5
+#define TABLE_DRIVER_SMU_CONFIG       6
+#define TABLE_ACTIVITY_MONITOR_COEFF  7
+#define TABLE_OVERDRIVE               8
+#define TABLE_I2C_COMMANDS            9
+#define TABLE_DRIVER_INFO             10
+#define TABLE_COUNT                   11
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f14449401188..146fd4b864b2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -72,6 +72,9 @@
 #include "dmub/dmub_srv.h"
 
 #include "i2caux_interface.h"
+
+#include "dce/dmub_psr.h"
+
 #include "dce/dmub_hw_lock_mgr.h"
 
 #include "dc_trace.h"
@@ -394,7 +397,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 		struct dc_crtc_timing_adjust *adjust)
 {
 	int i;
-	bool ret = false;
 
 	stream->adjust.v_total_max = adjust->v_total_max;
 	stream->adjust.v_total_mid = adjust->v_total_mid;
@@ -409,10 +411,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 					1,
 					*adjust);
 
-			ret = true;
+			return true;
 		}
 	}
-	return ret;
+	return false;
 }
 
 /**
@@ -2647,12 +2649,24 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->vrr_infopacket)
 		stream->vrr_infopacket = *update->vrr_infopacket;
 
+	if (update->allow_freesync)
+		stream->allow_freesync = *update->allow_freesync;
+
+	if (update->vrr_active_variable)
+		stream->vrr_active_variable = *update->vrr_active_variable;
+
 	if (update->crtc_timing_adjust)
 		stream->adjust = *update->crtc_timing_adjust;
 
 	if (update->dpms_off)
 		stream->dpms_off = *update->dpms_off;
 
+	if (update->hfvsif_infopacket)
+		stream->hfvsif_infopacket = *update->hfvsif_infopacket;
+
+	if (update->vtem_infopacket)
+		stream->vtem_infopacket = *update->vtem_infopacket;
+
 	if (update->vsc_infopacket)
 		stream->vsc_infopacket = *update->vsc_infopacket;
 
@@ -2727,7 +2741,9 @@ static void commit_planes_do_stream_update(struct dc *dc,
 			if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
 					stream_update->vrr_infopacket ||
 					stream_update->vsc_infopacket ||
-					stream_update->vsp_infopacket) {
+					stream_update->vsp_infopacket ||
+					stream_update->hfvsif_infopacket ||
+					stream_update->vtem_infopacket) {
 				resource_build_info_frame(pipe_ctx);
 				dc->hwss.update_info_frame(pipe_ctx);
 
@@ -2824,6 +2840,72 @@ static void commit_planes_do_stream_update(struct dc *dc,
 	}
 }
 
+static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
+{
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    dc->debug.enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc_ctx = dc->ctx;
+	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
+	unsigned int i, j;
+	unsigned int panel_inst = 0;
+
+	if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
+		return;
+
+	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+		return;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
+	cmd.update_dirty_rect.header.sub_type = 0;
+	cmd.update_dirty_rect.header.payload_bytes =
+		sizeof(cmd.update_dirty_rect) -
+		sizeof(cmd.update_dirty_rect.header);
+	update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
+	for (i = 0; i < surface_count; i++) {
+		struct dc_plane_state *plane_state = srf_updates[i].surface;
+		const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
+
+		if (!srf_updates[i].surface || !flip_addr)
+			continue;
+		/* Do not send in immediate flip mode */
+		if (srf_updates[i].surface->flip_immediate)
+			continue;
+
+		update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+		memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
+				sizeof(flip_addr->dirty_rects));
+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+
+			if (pipe_ctx->stream != stream)
+				continue;
+			if (pipe_ctx->plane_state != plane_state)
+				continue;
+
+			update_dirty_rect->panel_inst = panel_inst;
+			update_dirty_rect->pipe_idx = j;
+			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
+			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
+		}
+	}
+}
+
 static void commit_planes_for_stream(struct dc *dc,
 		struct dc_surface_update *srf_updates,
 		int surface_count,
@@ -2911,6 +2993,8 @@ static void commit_planes_for_stream(struct dc *dc,
 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 	}
 
+	dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
+
 	// Stream updates
 	if (stream_update)
 		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
@@ -3054,11 +3138,15 @@ static void commit_planes_for_stream(struct dc *dc,
 
 	}
 
-	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
-		dc->hwss.interdependent_update_lock(dc, context, false);
-	} else {
-		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
-	}
+#ifdef CONFIG_DRM_AMD_DC_DCN
+		if (update_type != UPDATE_TYPE_FAST)
+			if (dc->hwss.commit_subvp_config)
+				dc->hwss.commit_subvp_config(dc, context);
+#endif
+		if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
+			dc->hwss.interdependent_update_lock(dc, context, false);
+		else
+			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 
 	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
 		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
@@ -3237,19 +3325,6 @@ struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
 	return NULL;
 }
 
-struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
-{
-	uint8_t i;
-	struct dc_context *ctx = link->ctx;
-
-	for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
-		if (ctx->dc->current_state->streams[i]->link == link)
-			return ctx->dc->current_state->streams[i];
-	}
-
-	return NULL;
-}
-
 enum dc_irq_source dc_interrupt_to_irq_source(
 		struct dc *dc,
 		uint32_t src_id,
@@ -3389,10 +3464,13 @@ bool dc_submit_i2c_oem(
 		struct i2c_command *cmd)
 {
 	struct ddc_service *ddc = dc->res_pool->oem_device;
-	return dce_i2c_submit_command(
-		dc->res_pool,
-		ddc->ddc_pin,
-		cmd);
+	if (ddc)
+		return dce_i2c_submit_command(
+			dc->res_pool,
+			ddc->ddc_pin,
+			cmd);
+
+	return false;
 }
 
 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
@@ -3575,37 +3653,27 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 		dc->idle_optimizations_allowed = allow;
 }
 
-/*
- * blank all streams, and set min and max memory clock to
- * lowest and highest DPM level, respectively
- */
+/* set min and max memory clock to lowest and highest DPM level, respectively */
 void dc_unlock_memory_clock_frequency(struct dc *dc)
 {
-	unsigned int i;
-
-	for (i = 0; i < MAX_PIPES; i++)
-		if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
-			core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
+	if (dc->clk_mgr->funcs->set_hard_min_memclk)
+		dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
 
-	dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
-	dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 }
 
-/*
- * set min memory clock to the min required for current mode,
- * max to maxDPM, and unblank streams
- */
+/* set min memory clock to the min required for current mode, max to maxDPM */
 void dc_lock_memory_clock_frequency(struct dc *dc)
 {
-	unsigned int i;
+	if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
+		dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
 
-	dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
-	dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
-	dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+	if (dc->clk_mgr->funcs->set_hard_min_memclk)
+		dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
 
-	for (i = 0; i < MAX_PIPES; i++)
-		if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
-			core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 }
 
 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 72376075db0c..283957dbdf93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -422,6 +422,8 @@ char *dc_status_to_str(enum dc_status status)
 		return "The value specified is not supported.";
 	case DC_NO_LINK_ENC_RESOURCE:
 		return "No link encoder resource";
+	case DC_FAIL_DP_PAYLOAD_ALLOCATION:
+		return "Fail dp payload allocation";
 	case DC_ERROR_UNEXPECTED:
 		return "Unexpected error";
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a789ea8af27f..1206a3dd746f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -235,7 +235,8 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -1016,6 +1017,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 	bool same_edid = false;
 	enum dc_edid_status edid_status;
 	struct dc_context *dc_ctx = link->ctx;
+	struct dc *dc = dc_ctx->dc;
 	struct dc_sink *sink = NULL;
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
@@ -1095,6 +1097,20 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 
 			detect_edp_sink_caps(link);
 			read_current_link_settings_on_detect(link);
+
+			/* Disable power sequence on MIPI panel + converter
+			 */
+			if (dc->config.enable_mipi_converter_optimization &&
+				dc_ctx->dce_version == DCN_VERSION_3_01 &&
+				link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
+				memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
+					sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
+				dc->config.edp_no_power_sequencing = true;
+
+				if (!link->dpcd_caps.set_power_state_capable_edp)
+					link->wa_flags.dp_keep_receiver_powered = true;
+			}
+
 			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 			sink_caps.signal = SIGNAL_TYPE_EDP;
 			break;
@@ -1130,11 +1146,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,
 					(link->dpcd_caps.dongle_type !=
 							DISPLAY_DONGLE_DP_HDMI_CONVERTER))
 				converter_disable_audio = true;
-
-			// link switch from MST to non-MST stop topology manager
-			if (pre_connection_type == dc_connection_mst_branch &&
-					link->type != dc_connection_mst_branch)
-				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 			break;
 		}
 
@@ -1367,7 +1378,9 @@ bool dc_link_get_hpd_state(struct dc_link *dc_link)
 static enum hpd_source_id get_hpd_line(struct dc_link *link)
 {
 	struct gpio *hpd;
-	enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
+	enum hpd_source_id hpd_id;
+
+	hpd_id = HPD_SOURCEID_UNKNOWN;
 
 	hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 			   link->ctx->gpio_service);
@@ -1406,7 +1419,9 @@ static enum hpd_source_id get_hpd_line(struct dc_link *link)
 static enum channel_id get_ddc_line(struct dc_link *link)
 {
 	struct ddc *ddc;
-	enum channel_id channel = CHANNEL_ID_UNKNOWN;
+	enum channel_id channel;
+
+	channel = CHANNEL_ID_UNKNOWN;
 
 	ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 
@@ -1513,7 +1528,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 				     const struct link_init_data *init_params)
 {
 	uint8_t i;
-	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
+	struct ddc_service_init_data ddc_service_init_data = { 0 };
 	struct dc_context *dc_ctx = init_params->ctx;
 	struct encoder_init_data enc_init_data = { 0 };
 	struct panel_cntl_init_data panel_cntl_init_data = { 0 };
@@ -1783,6 +1798,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 	 */
 	program_hpd_filter(link);
 
+	link->psr_settings.psr_vtotal_control_support = false;
 	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
 	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
@@ -1812,7 +1828,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 static bool dc_link_construct_dpia(struct dc_link *link,
 				   const struct link_init_data *init_params)
 {
-	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
+	struct ddc_service_init_data ddc_service_init_data = { 0 };
 	struct dc_context *dc_ctx = init_params->ctx;
 
 	DC_LOGGER_INIT(dc_ctx->logger);
@@ -1993,7 +2009,8 @@ static enum dc_status enable_link_dp(struct dc_state *state,
 
 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
 		/*in case it is not on*/
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
@@ -2113,6 +2130,26 @@ void dc_link_blank_all_dp_displays(struct dc *dc)
 
 }
 
+void dc_link_blank_all_edp_displays(struct dc *dc)
+{
+	unsigned int i;
+	uint8_t dpcd_power_state = '\0';
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+
+	for (i = 0; i < dc->link_count; i++) {
+		if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
+			(!dc->links[i]->edp_sink_present))
+			continue;
+
+		/* if any of the displays are lit up turn them off */
+		status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+							&dpcd_power_state, sizeof(dpcd_power_state));
+
+		if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
+			dc_link_blank_dp_stream(dc->links[i], true);
+	}
+}
+
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
 {
 	unsigned int j;
@@ -3193,6 +3230,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 	unsigned int panel_inst;
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
+	union dpcd_alpm_configuration alpm_configuration;
+	union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3218,7 +3257,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->psr_frame_capture_indication_req;
 
 	/* Check for PSR v2*/
-	if (psr_config->psr_version == 0x2) {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 		/* For PSR v2 selective update.
 		 * Indicates whether sink should start capturing
 		 * immediately following active scan line,
@@ -3229,6 +3268,14 @@ bool dc_link_setup_psr(struct dc_link *link,
 		 * IRQ_HPD when CRC mismatch is detected.
 		 */
 		psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
+		/* For PSR v2, set the bit when the Source device will
+		 * be enabling PSR2 operation.
+		 */
+		psr_configuration.bits.ENABLE_PSR2    = 1;
+		/* For PSR v2, the Sink device must be able to receive
+		 * SU region updates early in the frame time.
+		 */
+		psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
 	}
 
 	dm_helpers_dp_write_dpcd(
@@ -3238,6 +3285,31 @@ bool dc_link_setup_psr(struct dc_link *link,
 		&psr_configuration.raw,
 		sizeof(psr_configuration.raw));
 
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+		memset(&alpm_configuration, 0, sizeof(alpm_configuration));
+
+		alpm_configuration.bits.ENABLE = 1;
+		dm_helpers_dp_write_dpcd(
+			link->ctx,
+			link,
+			DP_RECEIVER_ALPM_CONFIG,
+			&alpm_configuration.raw,
+			sizeof(alpm_configuration.raw));
+		psr_context->su_granularity_required =
+			psr_config->su_granularity_required;
+		psr_context->su_y_granularity =
+			psr_config->su_y_granularity;
+		psr_context->line_time_in_us =
+			psr_config->line_time_in_us;
+
+		if (link->psr_settings.psr_vtotal_control_support) {
+			psr_context->rate_control_caps = psr_config->rate_control_caps;
+			vtotal_control.bits.ENABLE = true;
+			core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
+							&vtotal_control.raw, sizeof(vtotal_control.raw));
+		}
+	}
+
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
 	psr_context->transmitterId = link->link_enc->transmitter;
 	psr_context->engineId = link->link_enc->preferred_engine;
@@ -3324,6 +3396,10 @@ bool dc_link_setup_psr(struct dc_link *link,
 	 */
 	psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
 
+	/* enable ALPM */
+	psr_context->psr_level.bits.DISABLE_ALPM = 0;
+	psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
+
 	/* Controls additional delay after remote frame capture before
 	 * continuing power down, default = 0
 	 */
@@ -3364,6 +3440,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 		*residency = 0;
 }
 
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	struct dc *dc = link->ctx->dc;
+	struct dmub_psr *psr = dc->res_pool->psr;
+
+	if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
+		return false;
+
+	psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
+
+	return true;
+}
+
 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
 {
 	return &link->link_status;
@@ -3533,6 +3622,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
 						"allocation table for "
 						"pipe idx: %d\n",
 						pipe_ctx->pipe_idx);
+		return DC_FAIL_DP_PAYLOAD_ALLOCATION;
 	}
 
 	proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
@@ -3741,11 +3831,14 @@ enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw
 
 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 		DC_LOG_MST("stream_enc[%d]: %p      "
+				"stream[%d].hpo_dp_stream_enc: %p      "
 				"stream[%d].vcp_id: %d      "
 				"stream[%d].slot_count: %d\n",
 				i,
 				(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
 				i,
+				(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
+				i,
 				link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
 				i,
 				link->mst_stream_alloc_table.stream_allocations[i].slot_count);
@@ -3778,7 +3871,6 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 	struct fixed31_32 avg_time_slots_per_mtp;
 	struct fixed31_32 pbn;
 	struct fixed31_32 pbn_per_slot;
-	struct link_encoder *link_encoder = link->link_enc;
 	struct dp_mst_stream_allocation_table proposed_table = {0};
 	uint8_t i;
 	enum act_return_status ret;
@@ -3806,11 +3898,14 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 
 	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 		DC_LOG_MST("stream_enc[%d]: %p      "
+				"stream[%d].hpo_dp_stream_enc: %p      "
 				"stream[%d].vcp_id: %d      "
 				"stream[%d].slot_count: %d\n",
 				i,
 				(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
 				i,
+				(void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
+				i,
 				link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
 				i,
 				link->mst_stream_alloc_table.stream_allocations[i].slot_count);
@@ -3819,8 +3914,13 @@ enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t
 	ASSERT(proposed_table.stream_count > 0);
 
 	/* update mst stream allocation table hardware state */
-	link_encoder->funcs->update_mst_stream_allocation_table(
-			link_encoder,
+	if (link_hwss->ext.update_stream_allocation_table == NULL ||
+			dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
+		DC_LOG_ERROR("Failure: unknown encoding format\n");
+		return DC_ERROR_UNEXPECTED;
+	}
+
+	link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
 			&link->mst_stream_alloc_table);
 
 	/* poll for immediate branch device ACT handled */
@@ -4284,7 +4384,7 @@ void core_link_enable_stream(
 			dp_set_dsc_enable(pipe_ctx, true);
 	}
 
-	if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
 		core_link_set_avmute(pipe_ctx, false);
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cbc47aecd00f..be1dcb0a2a06 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -329,51 +329,6 @@ static uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
 	return link_rate;
 }
 
-static void vendor_specific_lttpr_wa_one_start(struct dc_link *link)
-{
-	const uint8_t vendor_lttpr_write_data[4] = {0x1, 0x50, 0x63, 0xff};
-	const uint8_t offset = dp_convert_to_count(
-			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
-	uint32_t vendor_lttpr_write_address = 0xF004F;
-
-	if (offset != 0xFF)
-		vendor_lttpr_write_address +=
-				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
-
-	/* W/A for certain LTTPR to reset their lane settings, part one of two */
-	core_link_write_dpcd(
-			link,
-			vendor_lttpr_write_address,
-			&vendor_lttpr_write_data[0],
-			sizeof(vendor_lttpr_write_data));
-}
-
-static void vendor_specific_lttpr_wa_one_two(
-	struct dc_link *link,
-	const uint8_t rate)
-{
-	if (link->apply_vendor_specific_lttpr_link_rate_wa) {
-		uint8_t toggle_rate = 0x0;
-
-		if (rate == 0x6)
-			toggle_rate = 0xA;
-		else
-			toggle_rate = 0x6;
-
-		if (link->vendor_specific_lttpr_link_rate_wa == rate) {
-			/* W/A for certain LTTPR to reset internal state for link training */
-			core_link_write_dpcd(
-					link,
-					DP_LINK_BW_SET,
-					&toggle_rate,
-					1);
-		}
-
-		/* Store the last attempted link rate for this link */
-		link->vendor_specific_lttpr_link_rate_wa = rate;
-	}
-}
-
 static void dp_fixed_vs_pe_read_lane_adjust(
 	struct dc_link *link,
 	union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX])
@@ -423,51 +378,6 @@ static void dp_fixed_vs_pe_read_lane_adjust(
 	}
 }
 
-static void vendor_specific_lttpr_wa_four(
-	struct dc_link *link,
-	bool apply_wa)
-{
-	const uint8_t vendor_lttpr_write_data_one[4] = {0x1, 0x55, 0x63, 0x8};
-	const uint8_t vendor_lttpr_write_data_two[4] = {0x1, 0x55, 0x63, 0x0};
-	const uint8_t offset = dp_convert_to_count(
-			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
-	uint32_t vendor_lttpr_write_address = 0xF004F;
-	uint8_t sink_status = 0;
-	uint8_t i;
-
-	if (offset != 0xFF)
-		vendor_lttpr_write_address +=
-				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
-
-	/* W/A to pass through DPCD write of TPS=0 to DPRX */
-	if (apply_wa) {
-		core_link_write_dpcd(
-				link,
-				vendor_lttpr_write_address,
-				&vendor_lttpr_write_data_one[0],
-				sizeof(vendor_lttpr_write_data_one));
-	}
-
-	/* clear training pattern set */
-	dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
-
-	if (apply_wa) {
-		core_link_write_dpcd(
-				link,
-				vendor_lttpr_write_address,
-				&vendor_lttpr_write_data_two[0],
-				sizeof(vendor_lttpr_write_data_two));
-	}
-
-	/* poll for intra-hop disable */
-	for (i = 0; i < 10; i++) {
-		if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
-				(sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
-			break;
-		udelay(1000);
-	}
-}
-
 static void dp_fixed_vs_pe_set_retimer_lane_settings(
 	struct dc_link *link,
 	const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],
@@ -561,14 +471,6 @@ enum dc_status dpcd_set_link_settings(
 				&lt_settings->link_settings.link_rate_set, 1);
 	} else {
 		rate = get_dpcd_link_rate(&lt_settings->link_settings);
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-					link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
-			vendor_specific_lttpr_wa_one_start(link);
-
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN))
-			vendor_specific_lttpr_wa_one_two(link, rate);
 
 		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 	}
@@ -638,7 +540,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 	uint32_t dpcd_base_lt_offset;
 
 	uint8_t dpcd_lt_buffer[5] = {0};
-	union dpcd_training_pattern dpcd_pattern = { 0 };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t size_in_bytes;
 	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 	dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -944,7 +846,7 @@ static void override_lane_settings(const struct link_training_settings *lt_setti
 
 		return;
 
-	for (lane = 1; lane < LANE_COUNT_DP_MAX; lane++) {
+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
 		if (lt_settings->voltage_swing)
 			lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
 		if (lt_settings->pre_emphasis)
@@ -1303,12 +1205,6 @@ static enum link_training_result perform_channel_equalization_sequence(
 					dp_translate_training_aux_read_interval(
 						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-				link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-			wait_time_microsec = 16000;
-		}
-
 		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
@@ -1326,7 +1222,9 @@ static enum link_training_result perform_channel_equalization_sequence(
 
 		/* 5. check CR done*/
 		if (!dp_is_cr_done(lane_count, dpcd_lane_status))
-			return LINK_TRAINING_EQ_FAIL_CR;
+			return dpcd_lane_status[0].bits.CR_DONE_0 ?
+					LINK_TRAINING_EQ_FAIL_CR_PARTIAL :
+					LINK_TRAINING_EQ_FAIL_CR;
 
 		/* 6. check CHEQ done*/
 		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
@@ -1367,7 +1265,7 @@ static enum link_training_result perform_clock_recovery_sequence(
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 	union lane_align_status_updated dpcd_lane_status_updated;
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	retries_cr = 0;
 	retry_count = 0;
@@ -1413,11 +1311,6 @@ static enum link_training_result perform_clock_recovery_sequence(
 		/* 3. wait receiver to lock-on*/
 		wait_time_microsec = lt_settings->cr_pattern_time;
 
-		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {
-			wait_time_microsec = 16000;
-		}
-
 		dp_wait_for_training_aux_rd_interval(
 				link,
 				wait_time_microsec);
@@ -1658,22 +1551,23 @@ static void override_training_settings(
 		lt_settings->always_match_dpcd_with_hw_lane_settings = false;
 	}
 	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
-		lt_settings->lane_settings[lane].VOLTAGE_SWING =
+		lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
 			lt_settings->voltage_swing != NULL ?
 			*lt_settings->voltage_swing :
 			VOLTAGE_SWING_LEVEL0;
-		lt_settings->lane_settings[lane].PRE_EMPHASIS =
+		lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
 			lt_settings->pre_emphasis != NULL ?
 			*lt_settings->pre_emphasis
 			: PRE_EMPHASIS_DISABLED;
-		lt_settings->lane_settings[lane].POST_CURSOR2 =
+		lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
 			lt_settings->post_cursor2 != NULL ?
 			*lt_settings->post_cursor2
 			: POST_CURSOR2_DISABLED;
 	}
 
-	dp_hw_to_dpcd_lane_settings(lt_settings,
-			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
+	if (lt_settings->always_match_dpcd_with_hw_lane_settings)
+		dp_hw_to_dpcd_lane_settings(lt_settings,
+				lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 
 	/* Initialize training timings */
 	if (overrides->cr_pattern_time != NULL)
@@ -1882,6 +1776,9 @@ static void print_status_message(
 	case LINK_TRAINING_EQ_FAIL_CR:
 		lt_result = "CR failed in EQ";
 		break;
+	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
+		lt_result = "CR failed in EQ partially";
+		break;
 	case LINK_TRAINING_EQ_FAIL_EQ:
 		lt_result = "EQ failed";
 		break;
@@ -1929,8 +1826,8 @@ static void print_status_message(
 				link_rate,
 				lt_settings->link_settings.lane_count,
 				lt_result,
-				lt_settings->lane_settings[0].VOLTAGE_SWING,
-				lt_settings->lane_settings[0].PRE_EMPHASIS,
+				lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
+				lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
 				lt_spread);
 }
 
@@ -2074,7 +1971,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	uint32_t wait_time = 0;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
-	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	enum dc_status status = DC_OK;
+	enum link_training_result result = LINK_TRAINING_SUCCESS;
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	/* Transmit 128b/132b_TPS1 over Main-Link */
@@ -2099,22 +1997,24 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 			lt_settings->pattern_for_eq, DPRX);
 
 	/* poll for channel EQ done */
-	while (status == LINK_TRAINING_SUCCESS) {
+	while (result == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link, aux_rd_interval);
 		wait_time += aux_rd_interval;
-		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 				&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 		dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval);
-		if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
 				dpcd_lane_status)) {
 			/* pass */
 			break;
 		} else if (loop_count >= lt_settings->eq_loop_count_limit) {
-			status = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
+			result = DP_128b_132b_MAX_LOOP_COUNT_REACHED;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
 			dpcd_set_lane_settings(link, lt_settings, DPRX);
@@ -2123,24 +2023,26 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	}
 
 	/* poll for EQ interlane align done */
-	while (status == LINK_TRAINING_SUCCESS) {
-		if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
+	while (result == LINK_TRAINING_SUCCESS) {
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (wait_time >= lt_settings->eq_wait_time_limit) {
-			status = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
+			result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else {
 			dp_wait_for_training_aux_rd_interval(link,
 					lt_settings->eq_pattern_time);
 			wait_time += lt_settings->eq_pattern_time;
-			dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+			status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 					&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 		}
 	}
 
-	return status;
+	return result;
 }
 
 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
@@ -2149,34 +2051,37 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 		struct link_training_settings *lt_settings)
 {
 	/* Assumption: assume hardware has transmitted eq pattern */
-	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	enum dc_status status = DC_OK;
+	enum link_training_result result = LINK_TRAINING_SUCCESS;
 	union lane_align_status_updated dpcd_lane_status_updated = {0};
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint32_t wait_time = 0;
 
 	/* initiate CDS done sequence */
 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cds);
 
 	/* poll for CDS interlane align done and symbol lock */
-	while (status == LINK_TRAINING_SUCCESS) {
+	while (result  == LINK_TRAINING_SUCCESS) {
 		dp_wait_for_training_aux_rd_interval(link,
 				lt_settings->cds_pattern_time);
 		wait_time += lt_settings->cds_pattern_time;
-		dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
+		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
 						&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
-		if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
+		if (status != DC_OK) {
+			result = LINK_TRAINING_ABORT;
+		} else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
 				dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
 			break;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
-			status = DP_128b_132b_LT_FAILED;
+			result = DP_128b_132b_LT_FAILED;
 		} else if (wait_time >= lt_settings->cds_wait_time_limit) {
-			status = DP_128b_132b_CDS_DONE_TIMEOUT;
+			result = DP_128b_132b_CDS_DONE_TIMEOUT;
 		}
 	}
 
-	return status;
+	return result;
 }
 
 static enum link_training_result dp_perform_8b_10b_link_training(
@@ -2370,6 +2275,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
 	const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};
 	const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};
+	uint32_t pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;
 	uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
 	uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
 	uint32_t vendor_lttpr_write_address = 0xF004F;
@@ -2392,6 +2298,10 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 	if (offset != 0xFF) {
 		vendor_lttpr_write_address +=
 				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+		/* Certain display and cable configuration require extra delay */
+		if (offset > 2)
+			pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;
 	}
 
 	/* Vendor specific: Reset lane settings */
@@ -2471,6 +2381,7 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 
 	/* Perform Clock Recovery Sequence */
 	if (status == LINK_TRAINING_SUCCESS) {
+		const uint8_t max_vendor_dpcd_retries = 10;
 		uint32_t retries_cr;
 		uint32_t retry_count;
 		uint32_t wait_time_microsec;
@@ -2478,6 +2389,8 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 		union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 		union lane_align_status_updated dpcd_lane_status_updated;
 		union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
+		enum dc_status dpcd_status = DC_OK;
+		uint8_t i = 0;
 
 		retries_cr = 0;
 		retry_count = 0;
@@ -2508,11 +2421,23 @@ static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
 						lt_settings->pattern_for_cr,
 						0);
 				/* Vendor specific: Disable intercept */
-				core_link_write_dpcd(
-						link,
-						vendor_lttpr_write_address,
-						&vendor_lttpr_write_data_intercept_dis[0],
-						sizeof(vendor_lttpr_write_data_intercept_dis));
+				for (i = 0; i < max_vendor_dpcd_retries; i++) {
+					msleep(pre_disable_intercept_delay_ms);
+					dpcd_status = core_link_write_dpcd(
+							link,
+							vendor_lttpr_write_address,
+							&vendor_lttpr_write_data_intercept_dis[0],
+							sizeof(vendor_lttpr_write_data_intercept_dis));
+
+					if (dpcd_status == DC_OK)
+						break;
+
+					core_link_write_dpcd(
+							link,
+							vendor_lttpr_write_address,
+							&vendor_lttpr_write_data_intercept_en[0],
+							sizeof(vendor_lttpr_write_data_intercept_en));
+				}
 			} else {
 				vendor_lttpr_write_data_vs[3] = 0;
 				vendor_lttpr_write_data_pe[3] = 0;
@@ -2718,14 +2643,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 			&lt_settings);
 
 	/* reset previous training states */
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-			link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-		link->apply_vendor_specific_lttpr_link_rate_wa = true;
-		vendor_specific_lttpr_wa_four(link, true);
-	} else {
-		dpcd_exit_training_mode(link);
-	}
+	dpcd_exit_training_mode(link);
 
 	/* configure link prior to entering training mode */
 	dpcd_configure_lttpr_mode(link, &lt_settings);
@@ -2746,14 +2664,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 		ASSERT(0);
 
 	/* exit training mode */
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
-			link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
-		link->apply_vendor_specific_lttpr_link_rate_wa = false;
-		vendor_specific_lttpr_wa_four(link, (status != LINK_TRAINING_SUCCESS));
-	} else {
-		dpcd_exit_training_mode(link);
-	}
+	dpcd_exit_training_mode(link);
 
 	/* switch to video idle */
 	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
@@ -2804,8 +2715,8 @@ bool perform_link_training_with_retries(
 	j = 0;
 	while (j < attempts && fail_count < (attempts * 10)) {
 
-		DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d @ rate(%d) x lane(%d)\n",
-			__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
+		DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d)\n",
+			__func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
 			cur_link_settings.lane_count);
 
 		dp_enable_link_phy(
@@ -2867,13 +2778,16 @@ bool perform_link_training_with_retries(
 
 		fail_count++;
 		dp_trace_lt_fail_count_update(link, fail_count, false);
-		/* latest link training still fail, skip delay and keep PHY on
-		 */
-		if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
-			break;
+		if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
+			/* latest link training still fail or link training is aborted
+			 * skip delay and keep PHY on
+			 */
+			if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
+				break;
+		}
 
-		DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
-			__func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
+		DC_LOG_WARNING("%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d)\n",
+			__func__, link->link_index, (unsigned int)j + 1, attempts, cur_link_settings.link_rate,
 			cur_link_settings.lane_count);
 
 		dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
@@ -2916,8 +2830,13 @@ bool perform_link_training_with_retries(
 			 */
 			req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 			link_bw = dc_link_bandwidth_kbps(link, &cur_link_settings);
-			if (req_bw > link_bw)
-				break;
+			is_link_bw_low = (req_bw > link_bw);
+			is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&
+				(cur_link_settings.lane_count <= LANE_COUNT_ONE));
+			if (is_link_bw_low)
+				DC_LOG_WARNING(
+					"%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n",
+					__func__, link->link_index, req_bw, link_bw);
 		}
 
 		msleep(delay_between_attempts);
@@ -3596,11 +3515,6 @@ static bool decide_fallback_link_setting(
 		struct dc_link_settings *cur,
 		enum link_training_result training_result)
 {
-	if (!cur)
-		return false;
-	if (!max)
-		return false;
-
 	if (dp_get_link_encoding_format(max) == DP_128b_132b_ENCODING ||
 			link->dc->debug.force_dp2_lt_fallback_method)
 		return decide_fallback_link_setting_max_bw_policy(link, max, cur,
@@ -3630,6 +3544,7 @@ static bool decide_fallback_link_setting(
 		break;
 	}
 	case LINK_TRAINING_EQ_FAIL_EQ:
+	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
 	{
 		if (!reached_minimum_lane_count(cur->lane_count)) {
 			cur->lane_count = reduce_lane_count(cur->lane_count);
@@ -3967,6 +3882,9 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_
 	return true;
 }
 
+bool FORCE_RATE = false;
+uint32_t FORCE_LANE_COUNT = 0;
+
 void decide_link_settings(struct dc_stream_state *stream,
 	struct dc_link_settings *link_setting)
 {
@@ -4186,8 +4104,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
 			&dpcd_lane_adjustment[0].raw,
 			sizeof(dpcd_lane_adjustment));
 
-	if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+	if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 			link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
 		dp_fixed_vs_pe_read_lane_adjust(
 				link,
@@ -5118,16 +5035,13 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
 	return true;
 }
 
-bool dp_retrieve_lttpr_cap(struct dc_link *link)
+/* Logic to determine LTTPR mode */
+static void determine_lttpr_mode(struct dc_link *link)
 {
-	uint8_t lttpr_dpcd_data[8];
 	bool allow_lttpr_non_transparent_mode = 0;
 	bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-	bool is_lttpr_present = false;
 
-	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
 
 	if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
 			link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
@@ -5137,9 +5051,6 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 		allow_lttpr_non_transparent_mode = 1;
 	}
 
-	/*
-	 * Logic to determine LTTPR mode
-	 */
 	link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 	if (vbios_lttpr_enable && vbios_lttpr_interop)
 		link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
@@ -5161,8 +5072,33 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 	    link->dc->debug.dpia_debug.bits.force_non_lttpr)
 		link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 #endif
+}
+
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
+{
+	uint8_t lttpr_dpcd_data[8];
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	bool is_lttpr_present = false;
+
+	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+
+	/* Logic to determine LTTPR mode*/
+	determine_lttpr_mode(link);
 
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
+		if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+				!link->dc->debug.disable_fixed_vs_aux_timeout_wa) {
+			/* Fixed VS workaround for AUX timeout */
+			const uint32_t fixed_vs_address = 0xF004F;
+			const uint8_t fixed_vs_data[4] = {0x1, 0x22, 0x63, 0xc};
+
+			core_link_write_dpcd(
+					link,
+					fixed_vs_address,
+					fixed_vs_data,
+					sizeof(fixed_vs_data));
+		}
+
 		/* By reading LTTPR capability, RX assumes that we will enable
 		 * LTTPR extended aux timeout if LTTPR is present.
 		 */
@@ -5276,11 +5212,23 @@ static enum dc_status wa_try_to_wake_dprx(struct dc_link *link, uint64_t timeout
 	uint64_t time_taken_ms = 0;
 	enum dc_connection_type type = dc_connection_none;
 
-	status = core_link_read_dpcd(
-			link,
-			DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
-			&dpcd_data,
-			sizeof(dpcd_data));
+	determine_lttpr_mode(link);
+
+	/* Issue an AUX read to test DPRX responsiveness. If LTTPR is supported the first read is expected to
+	 * be to determine LTTPR capabilities. Otherwise trying to read power state should be an innocuous AUX read.
+	 */
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+		status = core_link_read_dpcd(
+				link,
+				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+				&dpcd_data,
+				sizeof(dpcd_data));
+	else
+		status = core_link_read_dpcd(
+				link,
+				DP_SET_POWER,
+				&dpcd_data,
+				sizeof(dpcd_data));
 
 	if (status != DC_OK) {
 		DC_LOG_WARNING("%s: Read DPCD LTTPR_CAP failed - try to toggle DPCD SET_POWER for %lld ms.",
@@ -5794,6 +5742,7 @@ void detect_edp_sink_caps(struct dc_link *link)
 	uint32_t link_rate_in_khz;
 	enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
 	uint8_t backlight_adj_cap;
+	uint8_t general_edp_cap;
 
 	retrieve_link_cap(link);
 	link->dpcd_caps.edp_supported_link_rates_count = 0;
@@ -5832,6 +5781,12 @@ void detect_edp_sink_caps(struct dc_link *link)
 	link->dpcd_caps.dynamic_backlight_capable_edp =
 				(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
 
+	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
+						&general_edp_cap, sizeof(general_edp_cap));
+
+	link->dpcd_caps.set_power_state_capable_edp =
+				(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
+
 	dc_link_set_default_brightness_aux(link);
 
 	core_link_read_dpcd(link, DP_EDP_DPCD_REV,
@@ -6119,8 +6074,7 @@ bool dc_link_dp_set_test_pattern(
 	if (is_dp_phy_pattern(test_pattern)) {
 		/* Set DPCD Lane Settings before running test pattern */
 		if (p_link_settings != NULL) {
-			if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
-					(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+			if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
 					link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
 				dp_fixed_vs_pe_set_retimer_lane_settings(
 						link,
@@ -6861,10 +6815,21 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 	if (allocate)	{
 		avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
 		req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
+		/// Validation should filter out modes that exceed link BW
+		ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
+		if (req_slot_count > MAX_MTP_SLOT_COUNT)
+			return false;
 	} else {
 		/// Leave req_slot_count = 0 if allocate is false.
 	}
 
+	proposed_table->stream_count = 1; /// Always 1 stream for SST
+	proposed_table->stream_allocations[0].slot_count = req_slot_count;
+	proposed_table->stream_allocations[0].vcp_id = vc_id;
+
+	if (link->aux_access_disabled)
+		return true;
+
 	/// Write DPCD 2C0 = 1 to start updating
 	update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;
 	core_link_write_dpcd(
@@ -6888,7 +6853,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 			&start_time_slot,
 			1);
 
-	ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); /// Validation should filter out modes that exceed link BW
 	core_link_write_dpcd(
 			link,
 			DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT,
@@ -6933,10 +6897,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 		// TODO - DP2.0 Payload: Read and log the payload table from downstream branch
 	}
 
-	proposed_table->stream_count = 1; /// Always 1 stream for SST
-	proposed_table->stream_allocations[0].slot_count = req_slot_count;
-	proposed_table->stream_allocations[0].vcp_id = vc_id;
-
 	return result;
 }
 
@@ -6952,6 +6912,8 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link)
 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 	union lane_align_status_updated lane_status_updated;
 
+	if (link->aux_access_disabled)
+		return true;
 	for (i = 0; i < act_retries; i++) {
 		get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated);
 
@@ -7099,7 +7061,8 @@ void dp_enable_link_phy(
 	unsigned int i;
 
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
-		link->dc->hwss.edp_power_control(link, true);
+		if (!link->dc->config.edp_no_power_sequencing)
+			link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
index 1b7a8774b0c9..03f7249df1ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c
@@ -177,13 +177,13 @@ static uint8_t dpia_build_set_config_data(enum dpia_set_config_type type,
 		break;
 	case DPIA_SET_CFG_SET_VSPE:
 		/* Assume all lanes have same drive settings. */
-		data.set_vspe.swing = lt_settings->lane_settings[0].VOLTAGE_SWING;
-		data.set_vspe.pre_emph = lt_settings->lane_settings[0].PRE_EMPHASIS;
+		data.set_vspe.swing = lt_settings->hw_lane_settings[0].VOLTAGE_SWING;
+		data.set_vspe.pre_emph = lt_settings->hw_lane_settings[0].PRE_EMPHASIS;
 		data.set_vspe.max_swing_reached =
-			lt_settings->lane_settings[0].VOLTAGE_SWING ==
+			lt_settings->hw_lane_settings[0].VOLTAGE_SWING ==
 			VOLTAGE_SWING_MAX_LEVEL ? 1 : 0;
 		data.set_vspe.max_pre_emph_reached =
-			lt_settings->lane_settings[0].PRE_EMPHASIS ==
+			lt_settings->hw_lane_settings[0].PRE_EMPHASIS ==
 			PRE_EMPHASIS_MAX_LEVEL ? 1 : 0;
 		break;
 	default:
@@ -226,7 +226,7 @@ static enum dc_status dpcd_set_lt_pattern(struct dc_link *link,
 	enum dc_dp_training_pattern pattern,
 	uint32_t hop)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
 	enum dc_status status;
 
@@ -287,9 +287,9 @@ static enum link_training_result dpia_training_cr_non_transparent(
 	/* From DP spec, CR read interval is always 100us. */
 	uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint8_t set_cfg_data;
 	enum dpia_set_config_ts ts;
 
@@ -405,7 +405,7 @@ static enum link_training_result dpia_training_cr_non_transparent(
 
 		/* Update VS/PE. */
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-				lt_settings->lane_settings,
+				lt_settings->hw_lane_settings,
 				lt_settings->dpcd_lane_settings);
 		retry_count++;
 	}
@@ -445,9 +445,9 @@ static enum link_training_result dpia_training_cr_transparent(
 	uint32_t retry_count = 0;
 	uint32_t wait_time_microsec = lt_settings->cr_pattern_time;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	/* Cap of LINK_TRAINING_MAX_CR_RETRY attempts at clock recovery.
 	 * Fix inherited from perform_clock_recovery_sequence() -
@@ -599,9 +599,9 @@ static enum link_training_result dpia_training_eq_non_transparent(
 	enum dc_dp_training_pattern tr_pattern;
 	uint32_t wait_time_microsec;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	uint8_t set_cfg_data;
 	enum dpia_set_config_ts ts;
 
@@ -738,9 +738,9 @@ static enum link_training_result dpia_training_eq_transparent(
 	enum dc_dp_training_pattern tr_pattern = lt_settings->pattern_for_eq;
 	uint32_t wait_time_microsec;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
-	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 
 	wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX);
 
@@ -827,7 +827,7 @@ static enum link_training_result dpia_training_eq_phase(
 /* End training of specified hop in display path. */
 static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 	uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;
 	enum dc_status status;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 42da7f430113..639a0a276a08 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -26,6 +26,8 @@
 #include "resource.h"
 #include "dc_link_dp.h"
 
+#define DC_LOGGER dc->ctx->logger
+
 /* Check whether stream is supported by DIG link encoders. */
 static bool is_dig_link_enc_stream(struct dc_stream_state *stream)
 {
@@ -383,6 +385,30 @@ void link_enc_cfg_link_encs_assign(
 			state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
 	}
 
+	/* Log encoder assignments. */
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct link_enc_assignment assignment =
+				dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
+
+		if (assignment.valid)
+			DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",
+					__func__,
+					assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
+					assignment.ep_id.link_id.enum_id - 1,
+					assignment.eng_id);
+	}
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct link_enc_assignment assignment =
+				state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
+
+		if (assignment.valid)
+			DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",
+					__func__,
+					assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
+					assignment.ep_id.link_id.enum_id - 1,
+					assignment.eng_id);
+	}
+
 	/* Current state mode will be set to steady once this state committed. */
 	state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
 }
@@ -658,8 +684,25 @@ bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state)
 			((valid_uniqueness & 0x1) << 2) |
 			((valid_avail & 0x1) << 3) |
 			((valid_streams & 0x1) << 4);
-		dm_error("Invalid link encoder assignments: 0x%x\n", valid_bitmap);
+		DC_LOG_ERROR("%s: Invalid link encoder assignments - 0x%x\n", __func__, valid_bitmap);
 	}
 
 	return is_valid;
 }
+
+void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state)
+{
+	int i = 0;
+	int num_transient_assignments = 0;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		if (current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i].valid)
+			num_transient_assignments++;
+	}
+
+	/* Only enter transient mode if the new encoder assignments are valid. */
+	if (new_state->stream_count == num_transient_assignments) {
+		current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
+		DC_LOG_DEBUG("%s: current_state(%p) mode(%d)\n", __func__, current_state, LINK_ENC_CFG_TRANSIENT);
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6774dd8bb53e..28803ca9e3f2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -67,6 +67,8 @@
 #include "dcn31/dcn31_resource.h"
 #include "dcn315/dcn315_resource.h"
 #include "dcn316/dcn316_resource.h"
+#include "../dcn32/dcn32_resource.h"
+#include "../dcn321/dcn321_resource.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -162,7 +164,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 		if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
 			dc_version = DCN_VERSION_3_16;
 		break;
-
+	case AMDGPU_FAMILY_GC_11_0_0:
+		dc_version = DCN_VERSION_3_2;
+		if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_21;
+		break;
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -258,6 +264,12 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 	case DCN_VERSION_3_16:
 		res_pool = dcn316_create_resource_pool(init_data, dc);
 		break;
+	case DCN_VERSION_3_2:
+		res_pool = dcn32_create_resource_pool(init_data, dc);
+		break;
+	case DCN_VERSION_3_21:
+		res_pool = dcn321_create_resource_pool(init_data, dc);
+		break;
 #endif
 	default:
 		break;
@@ -1982,6 +1994,10 @@ enum dc_status dc_remove_stream_from_ctx(
 				dc->res_pool,
 			del_pipe->stream_res.stream_enc,
 			false);
+	/* Release link encoder from stream in new dc_state. */
+	if (dc->res_pool->funcs->link_enc_unassign)
+		dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
+
 	if (is_dp_128b_132b_signal(del_pipe)) {
 		update_hpo_dp_stream_engine_usage(
 			&new_ctx->res_ctx, dc->res_pool,
@@ -2147,7 +2163,7 @@ static int acquire_resource_from_hw_enabled_state(
 
 		if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
 			pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
-					&numPipes, &id_src[0], &id_src[1]);
+						&numPipes, &id_src[0], &id_src[1]);
 
 		if (id_src[0] == 0xf && id_src[1] == 0xf) {
 			id_src[0] = tg_inst;
@@ -2159,6 +2175,8 @@ static int acquire_resource_from_hw_enabled_state(
 			if (id_src[i] == 0xf)
 				return -1;
 
+			pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
+
 			pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
 			pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
 			pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
@@ -2172,13 +2190,17 @@ static int acquire_resource_from_hw_enabled_state(
 
 				if (pool->mpc->funcs->read_mpcc_state) {
 					struct mpcc_state s = {0};
+
 					pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
+
 					if (s.dpp_id < MAX_MPCC)
 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
 								s.dpp_id;
+
 					if (s.bot_mpcc_id < MAX_MPCC)
 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
 								&pool->mpc->mpcc_array[s.bot_mpcc_id];
+
 					if (s.opp_id < MAX_OPP)
 						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
 				}
@@ -2187,6 +2209,7 @@ static int acquire_resource_from_hw_enabled_state(
 
 			if (id_src[i] >= pool->timing_generator_count) {
 				id_src[i] = pool->timing_generator_count - 1;
+
 				pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
 				pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
 			}
@@ -2777,6 +2800,26 @@ static void set_vsc_info_packet(
 
 	*info_packet = stream->vsc_infopacket;
 }
+static void set_hfvs_info_packet(
+		struct dc_info_packet *info_packet,
+		struct dc_stream_state *stream)
+{
+	if (!stream->hfvsif_infopacket.valid)
+		return;
+
+	*info_packet = stream->hfvsif_infopacket;
+}
+
+
+static void set_vtem_info_packet(
+		struct dc_info_packet *info_packet,
+		struct dc_stream_state *stream)
+{
+	if (!stream->vtem_infopacket.valid)
+		return;
+
+	*info_packet = stream->vtem_infopacket;
+}
 
 void dc_resource_state_destruct(struct dc_state *context)
 {
@@ -2857,7 +2900,8 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 	info->spd.valid = false;
 	info->hdrsmd.valid = false;
 	info->vsc.valid = false;
-
+	info->hfvsif.valid = false;
+	info->vtem.valid = false;
 	signal = pipe_ctx->stream->signal;
 
 	/* HDMi and DP have different info packets*/
@@ -2865,6 +2909,8 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
 		set_avi_info_frame(&info->avi, pipe_ctx);
 
 		set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
+		set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
+		set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
 
 		set_spd_info_packet(&info->spd, pipe_ctx->stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index de8b214132a2..167bb3310877 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -389,7 +389,7 @@ bool dc_stream_set_cursor_position(
 	struct dc_stream_state *stream,
 	const struct dc_cursor_position *position)
 {
-	struct dc  *dc;
+	struct dc  *dc = stream->ctx->dc;
 	bool reset_idle_optimizations = false;
 
 	if (NULL == stream) {
@@ -406,7 +406,8 @@ bool dc_stream_set_cursor_position(
 	dc_z10_restore(dc);
 
 	/* disable idle optimizations if enabling cursor */
-	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
+	if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates)
+			&& position->enable) {
 		dc_allow_idle_optimizations(dc, false);
 		reset_idle_optimizations = true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 817028d3c4a0..8292f27c1516 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.187"
+#define DC_VER "3.2.191"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
@@ -162,6 +162,10 @@ struct dc_color_caps {
 	struct mpc_color_caps mpc;
 };
 
+struct dc_dmub_caps {
+    bool psr;
+};
+
 struct dc_caps {
 	uint32_t max_streams;
 	uint32_t max_links;
@@ -196,12 +200,23 @@ struct dc_caps {
 	unsigned int cursor_cache_size;
 	struct dc_plane_cap planes[MAX_PLANES];
 	struct dc_color_caps color;
+	struct dc_dmub_caps dmub_caps;
 	bool dp_hpo;
 	bool hdmi_frl_pcon_support;
 	bool edp_dsc_support;
 	bool vbios_lttpr_aware;
 	bool vbios_lttpr_enable;
 	uint32_t max_otg_num;
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	uint32_t max_cab_allocation_bytes;
+	uint32_t cache_line_size;
+	uint32_t cache_num_ways;
+	uint16_t subvp_fw_processing_delay_us;
+	uint16_t subvp_prefetch_end_to_mall_start_us;
+	uint16_t subvp_pstate_allow_width_us;
+	uint16_t subvp_vertical_int_margin_us;
+#endif
+	bool seamless_odm;
 };
 
 struct dc_bug_wa {
@@ -337,6 +352,7 @@ struct dc_config {
 	bool is_single_rank_dimm;
 	bool use_pipe_ctx_sync_logic;
 	bool ignore_dpref_ss;
+	bool enable_mipi_converter_optimization;
 };
 
 enum visual_confirm {
@@ -417,12 +433,16 @@ struct dc_clocks {
 	enum dcn_zstate_support_state zstate_support;
 	bool dtbclk_en;
 	int ref_dtbclk_khz;
+	bool fclk_p_state_change_support;
 	enum dcn_pwr_state pwr_state;
 	/*
 	 * Elements below are not compared for the purposes of
 	 * optimization required
 	 */
 	bool prev_p_state_change_support;
+	bool fclk_prev_p_state_change_support;
+	int num_ways;
+	int prev_num_ways;
 	enum dtm_pstate dtm_level;
 	int max_supported_dppclk_khz;
 	int max_supported_dispclk_khz;
@@ -717,13 +737,19 @@ struct dc_debug_options {
 	bool enable_z9_disable_interface;
 	bool enable_sw_cntl_psr;
 	union dpia_debug_options dpia_debug;
-	bool apply_vendor_specific_lttpr_wa;
-	bool extended_blank_optimization;
-	union aux_wake_wa_options aux_wake_wa;
+	bool disable_fixed_vs_aux_timeout_wa;
+	uint32_t fixed_vs_aux_delay_config_wa;
+	bool force_disable_subvp;
+	bool force_subvp_mclk_switch;
+	bool force_usr_allow;
 	/* uses value at boot and disables switch */
 	bool disable_dtb_ref_clk_switch;
+	bool extended_blank_optimization;
+	union aux_wake_wa_options aux_wake_wa;
 	uint8_t psr_power_use_phy_fsm;
 	enum dml_hostvm_override_opts dml_hostvm_override;
+	bool use_legacy_soc_bb_mechanism;
+	bool exit_idle_opt_for_cursor_updates;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
@@ -1220,6 +1246,7 @@ struct dpcd_caps {
 	bool panel_mode_edp;
 	bool dpcd_display_control_capable;
 	bool ext_receiver_cap_field_present;
+	bool set_power_state_capable_edp;
 	bool dynamic_backlight_capable_edp;
 	union dpcd_fec_capability fec_cap;
 	struct dpcd_dsc_capabilities dsc_caps;
@@ -1412,16 +1439,10 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_
 
 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
 
-/*
- * blank all streams, and set min and max memory clock to
- * lowest and highest DPM level, respectively
- */
+/* set min and max memory clock to lowest and highest DPM level, respectively */
 void dc_unlock_memory_clock_frequency(struct dc *dc);
 
-/*
- * set min memory clock to the min required for current mode,
- * max to maxDPM, and unblank streams
- */
+/* set min memory clock to the min required for current mode, max to maxDPM */
 void dc_lock_memory_clock_frequency(struct dc *dc);
 
 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 67abda44eb1f..260ac4458870 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -156,6 +156,11 @@ struct dc_vbios_funcs {
 	enum bp_result (*get_lttpr_interop)(
 			struct dc_bios *dcb,
 			uint8_t *dce_caps);
+
+	enum bp_result (*get_connector_speed_cap_info)(
+		struct dc_bios *bios,
+		struct graphics_object_id object_id,
+		struct bp_connector_speed_cap_info *info);
 };
 
 struct bios_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 541376fabbef..548c91ad1b82 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -27,6 +27,8 @@
 #include "dc_dmub_srv.h"
 #include "../dmub/dmub_srv.h"
 #include "dm_helpers.h"
+#include "dc_hw_types.h"
+#include "core_types.h"
 
 #define CTX dc_dmub_srv->ctx
 #define DC_LOGGER CTX->logger
@@ -250,6 +252,37 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable)
 	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
 }
 
+void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
+{
+	union dmub_rb_cmd cmd = { 0 };
+	enum dmub_status status;
+
+	if (!dmub) {
+		return;
+	}
+
+	memset(&cmd, 0, sizeof(cmd));
+
+	/* Prepare fw command */
+	cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS;
+	cmd.query_feature_caps.header.sub_type = 0;
+	cmd.query_feature_caps.header.ret_status = 1;
+	cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);
+
+	/* Send command to fw */
+	status = dmub_srv_cmd_with_reply_data(dmub, &cmd);
+
+	ASSERT(status == DMUB_STATUS_OK);
+
+	/* If command was processed, copy feature caps to dmub srv */
+	if (status == DMUB_STATUS_OK &&
+	    cmd.query_feature_caps.header.ret_status == 0) {
+		memcpy(&dmub->feature_caps,
+		       &cmd.query_feature_caps.query_feature_caps_data,
+		       sizeof(struct dmub_feature_caps));
+	}
+}
+
 bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
 {
 	if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 7e4e2ec5915d..52758ff1e405 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -31,6 +31,10 @@
 
 struct dmub_srv;
 struct dc;
+struct pipe_ctx;
+struct dc_crtc_timing_adjust;
+struct dc_crtc_timing;
+struct dc_state;
 
 struct dc_reg_helper_state {
 	bool gather_in_progress;
@@ -68,6 +72,7 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_bu
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 
+void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
 void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
 void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index aa7e3a07191d..d75416dc9fae 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -780,6 +780,7 @@ struct dc_crtc_timing {
 	uint32_t v_sync_width;
 
 	uint32_t pix_clk_100hz;
+	uint32_t min_refresh_in_uhz;
 
 	uint32_t vic;
 	uint32_t hdmi_vic;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index a3c37ee3f849..29c0040a6dd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -100,6 +100,7 @@ struct psr_settings {
 	bool psr_feature_enabled;		// PSR is supported by sink
 	bool psr_allow_active;			// PSR is currently active
 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
+	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
 
 	/* These parameters are calculated in Driver,
 	 * based on display timing and Sink capabilities.
@@ -108,6 +109,7 @@ struct psr_settings {
 	 */
 	bool psr_frame_capture_indication_req;
 	unsigned int psr_sdp_transmit_line_num_deadline;
+	uint8_t force_ffu_mode;
 	unsigned int psr_power_opt;
 };
 
@@ -321,8 +323,11 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
 
 void dc_link_blank_all_dp_displays(struct dc *dc);
+void dc_link_blank_all_edp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 58941f4defb3..6f79327e0035 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -145,6 +145,24 @@ struct test_pattern {
 	unsigned int cust_pattern_size;
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DCN
+#define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR)
+
+enum mall_stream_type {
+	SUBVP_NONE, // subvp not in use
+	SUBVP_MAIN, // subvp in use, this stream is main stream
+	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
+};
+
+struct mall_stream_config {
+	/* MALL stream config to indicate if the stream is phantom or not.
+	 * We will use a phantom stream to indicate that the pipe is phantom.
+	 */
+	enum mall_stream_type type;
+	struct dc_stream_state *paired_stream;	// master / slave stream
+};
+#endif
+
 struct dc_stream_state {
 	// sink is deprecated, new code should not reference
 	// this pointer
@@ -162,6 +180,8 @@ struct dc_stream_state {
 	struct dc_info_packet vrr_infopacket;
 	struct dc_info_packet vsc_infopacket;
 	struct dc_info_packet vsp_infopacket;
+	struct dc_info_packet hfvsif_infopacket;
+	struct dc_info_packet vtem_infopacket;
 	uint8_t dsc_packed_pps[128];
 	struct rect src; /* composition area */
 	struct rect dst; /* stream addressable area */
@@ -187,6 +207,8 @@ struct dc_stream_state {
 	bool use_vsc_sdp_for_colorimetry;
 	bool ignore_msa_timing_param;
 
+	bool allow_freesync;
+	bool vrr_active_variable;
 	bool freesync_on_desktop;
 
 	bool converter_disable_audio;
@@ -255,6 +277,9 @@ struct dc_stream_state {
 
 	bool has_non_synchronizable_pclk;
 	bool vblank_synchronized;
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	struct mall_stream_config mall_stream_config;
+#endif
 };
 
 #define ABM_LEVEL_IMMEDIATE_DISABLE 255
@@ -274,9 +299,12 @@ struct dc_stream_update {
 	struct dc_info_packet *vrr_infopacket;
 	struct dc_info_packet *vsc_infopacket;
 	struct dc_info_packet *vsp_infopacket;
-
+	struct dc_info_packet *hfvsif_infopacket;
+	struct dc_info_packet *vtem_infopacket;
 	bool *dpms_off;
 	bool integer_scaling_update;
+	bool *allow_freesync;
+	bool *vrr_active_variable;
 
 	struct colorspace_transform *gamut_remap;
 	enum dc_color_space *output_color_space;
@@ -323,7 +351,6 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
 
 uint8_t dc_get_current_stream_count(struct dc *dc);
 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link);
 
 /*
  * Return the current frame counter.
@@ -529,4 +556,9 @@ bool dc_stream_get_crtc_position(struct dc *dc,
 
 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
 
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context);
 #endif /* DC_STREAM_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 2ba9f528c0fe..fa735d5f730f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -657,10 +657,17 @@ enum dc_psr_state {
 	PSR_STATE4b,
 	PSR_STATE4c,
 	PSR_STATE4d,
+	PSR_STATE4_FULL_FRAME,
+	PSR_STATE4a_FULL_FRAME,
+	PSR_STATE4b_FULL_FRAME,
+	PSR_STATE4c_FULL_FRAME,
+	PSR_STATE4_FULL_FRAME_POWERUP,
 	PSR_STATE5,
 	PSR_STATE5a,
 	PSR_STATE5b,
 	PSR_STATE5c,
+	PSR_STATE_HWLOCK_MGR,
+	PSR_STATE_POLLVUPDATE,
 	PSR_STATE_INVALID = 0xFF
 };
 
@@ -672,6 +679,12 @@ struct psr_config {
 	unsigned int psr_sdp_transmit_line_num_deadline;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 union dmcu_psr_level {
@@ -686,7 +699,9 @@ union dmcu_psr_level {
 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
-		unsigned int RESERVED:22;
+		unsigned int DISABLE_ALPM:1;
+		unsigned int ALPM_DEFAULT_PD_MODE:1;
+		unsigned int RESERVED:20;
 	} bits;
 	unsigned int u32all;
 };
@@ -775,6 +790,12 @@ struct psr_context {
 	unsigned int frame_delay;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index b699d1b2ba83..e6c06325742a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -128,6 +128,21 @@
 	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
 	NBIO_SR(BIOS_SCRATCH_2)
 
+#define ABM_DCN32_REG_LIST(id)\
+	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
+	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
+	NBIO_SR(BIOS_SCRATCH_2)
+
 #define ABM_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
 
@@ -203,6 +218,36 @@
 
 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
 
+#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_VMAX_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
+			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
+			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
+	ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
+			BL1_PWM_USER_LEVEL, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+
 #define ABM_REG_FIELD_LIST(type) \
 	type ABM1_HG_NUM_OF_BINS_SEL; \
 	type ABM1_HG_VMAX_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 845aa8a1027d..4b57657b5322 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -992,7 +992,18 @@ static bool dcn31_program_pix_clk(
 			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
 			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
 		}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		/* Enable DTO */
+		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+					DP_DTO0_ENABLE, 1,
+					PIPE0_DTO_SRC_SEL, 1);
+		else
+			REG_UPDATE(PIXEL_RATE_CNTL[inst],
+					DP_DTO0_ENABLE, 1);
+#else
 		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+#endif
 	} else {
 		if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
 			unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
@@ -1004,10 +1015,26 @@ static bool dcn31_program_pix_clk(
 			REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
 
 			/* Enable DTO */
+	#if defined(CONFIG_DRM_AMD_DC_DCN)
+			if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+						DP_DTO0_ENABLE, 1,
+						PIPE0_DTO_SRC_SEL, 1);
+			else
+				REG_UPDATE(PIXEL_RATE_CNTL[inst],
+						DP_DTO0_ENABLE, 1);
+	#else
 			REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+	#endif
 			return true;
 		}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
+			REG_UPDATE(PIXEL_RATE_CNTL[inst],
+					PIPE0_DTO_SRC_SEL, 0);
+#endif
+
 		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 		bp_pc_params.controller_id = pix_clk_params->controller_id;
 		bp_pc_params.pll_id = clock_source->id;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 9eec3524335f..e0c390fcc12c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -164,6 +164,10 @@
 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 
+#define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
+	CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
+	CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)
+
 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 		SRII(PHASE, DP_DTO, 0),\
@@ -197,12 +201,23 @@
 	type DP_DTO0_MODULO; \
 	type DP_DTO0_ENABLE;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+#define CS_REG_FIELD_LIST_DCN32(type) \
+	type PIPE0_DTO_SRC_SEL;
+#endif
+
 struct dce110_clk_src_shift {
 	CS_REG_FIELD_LIST(uint8_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	CS_REG_FIELD_LIST_DCN32(uint8_t)
+#endif
 };
 
 struct dce110_clk_src_mask{
 	CS_REG_FIELD_LIST(uint32_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	CS_REG_FIELD_LIST_DCN32(uint32_t)
+#endif
 };
 
 struct dce110_clk_src_regs {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index b1b2e3c6f379..3f32e9c3fbaf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -65,5 +65,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
 
 bool should_use_dmub_lock(struct dc_link *link)
 {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
 	return false;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 1d4f0c45b536..0df06740ec39 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -74,6 +74,22 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 		state = PSR_STATE5b;
 	else if (raw_state == 0x53)
 		state = PSR_STATE5c;
+	else if (raw_state == 0x4A)
+		state = PSR_STATE4_FULL_FRAME;
+	else if (raw_state == 0x4B)
+		state = PSR_STATE4a_FULL_FRAME;
+	else if (raw_state == 0x4C)
+		state = PSR_STATE4b_FULL_FRAME;
+	else if (raw_state == 0x4D)
+		state = PSR_STATE4c_FULL_FRAME;
+	else if (raw_state == 0x4E)
+		state = PSR_STATE4_FULL_FRAME_POWERUP;
+	else if (raw_state == 0x60)
+		state = PSR_STATE_HWLOCK_MGR;
+	else if (raw_state == 0x61)
+		state = PSR_STATE_POLLVUPDATE;
+	else
+		state = PSR_STATE_INVALID;
 
 	return state;
 }
@@ -133,6 +149,9 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 	case DC_PSR_VERSION_1:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
 		break;
+	case DC_PSR_VERSION_SU_1:
+		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
+		break;
 	case DC_PSR_VERSION_UNSUPPORTED:
 	default:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
@@ -231,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
 }
 
+/**
+ * Set PSR vtotal requirement for FreeSync PSR.
+ */
+static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc = dmub->ctx;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
+	cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
+	cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
+
+	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 /*
  * Set PSR power optimization flags.
  */
@@ -330,12 +370,35 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+	copy_settings_data->debug.bitfields.force_full_frame_update	= 0;
+
+	if (psr_context->su_granularity_required == 0)
+		copy_settings_data->su_y_granularity = 0;
+	else
+		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
+
+	copy_settings_data->line_capture_indication = 0;
+	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
+	copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
 	copy_settings_data->panel_inst = panel_inst;
 	copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
 
+	/**
+	 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
+	 * Note that PSRSU+DSC is still under development.
+	 */
+	if (copy_settings_data->dsc_enable_status &&
+		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
+		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
+			sizeof(link->dpcd_caps.sink_dev_id_str)))
+		link->psr_settings.force_ffu_mode = 1;
+	else
+		link->psr_settings.force_ffu_mode = 0;
+	copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
+
 	if (link->fec_state == dc_link_fec_enabled &&
 		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
 			sizeof(link->dpcd_caps.sink_dev_id_str)) ||
@@ -394,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = {
 	.psr_set_level			= dmub_psr_set_level,
 	.psr_force_static		= dmub_psr_force_static,
 	.psr_get_residency		= dmub_psr_get_residency,
+	.psr_set_sink_vtotal_in_psr_active	= dmub_psr_set_sink_vtotal_in_psr_active,
 	.psr_set_power_opt		= dmub_psr_set_power_opt,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 01acc01cc191..74005b9d352a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -46,6 +46,8 @@ struct dmub_psr_funcs {
 	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
 	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
 	uint8_t panel_inst);
+	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
+	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7eff7811769d..8662703f306c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1245,8 +1245,18 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
 			 * has changed or they enter protection state and hang.
 			 */
 			msleep(60);
-		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
-			edp_receiver_ready_T9(link);
+		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
+			if (!link->dc->config.edp_no_power_sequencing) {
+				/*
+				 * Sometimes, DP receiver chip power-controlled externally by an
+				 * Embedded Controller could be treated and used as eDP,
+				 * if it drives mobile display. In this case,
+				 * we shouldn't be doing power-sequencing, hence we can skip
+				 * waiting for T9-ready.
+				 */
+				edp_receiver_ready_T9(link);
+			}
+		}
 	}
 
 }
@@ -1766,29 +1776,9 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 				break;
 			}
 		}
-
-		/*
-		 * TO-DO: So far the code logic below only addresses single eDP case.
-		 * For dual eDP case, there are a few things that need to be
-		 * implemented first:
-		 *
-		 * 1. Change the fastboot logic above, so eDP link[0 or 1]'s
-		 * stream[0 or 1] will all be checked.
-		 *
-		 * 2. Change keep_edp_vdd_on to an array, and maintain keep_edp_vdd_on
-		 * for each eDP.
-		 *
-		 * Once above 2 things are completed, we can then change the logic below
-		 * correspondingly, so dual eDP case will be fully covered.
-		 */
-
-		// We are trying to enable eDP, don't power down VDD if eDP stream is existing
-		if ((edp_stream_num == 1 && edp_streams[0] != NULL) || can_apply_edp_fast_boot) {
+		// We are trying to enable eDP, don't power down VDD
+		if (can_apply_edp_fast_boot)
 			keep_edp_vdd_on = true;
-			DC_LOG_EVENT_LINK_TRAINING("Keep eDP Vdd on\n");
-		} else {
-			DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, turn eDP Vdd off\n");
-		}
 	}
 
 	// Check seamless boot support
@@ -2181,15 +2171,18 @@ static void dce110_setup_audio_dto(
 			build_audio_output(context, pipe_ctx, &audio_output);
 
 			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
-				/* disable audio DTBCLK DTO */
-				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
-					dc->res_pool->dccg, 0);
+				struct dtbclk_dto_params dto_params = {0};
 
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 						pipe_ctx->stream_res.audio,
 						pipe_ctx->stream->signal,
 						&audio_output.crtc_info,
 						&audio_output.pll_info);
+
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, &dto_params);
+
 			} else
 				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 					pipe_ctx->stream_res.audio,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 39485bdeb90e..e48fd044f572 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -158,8 +158,39 @@ struct dcn_hubbub_registers {
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
 	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;
+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;
 };
 
+#define HUBBUB_REG_FIELD_LIST_DCN32(type) \
+		type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\
+		type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\
+		type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\
+		type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\
+		type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\
+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\
+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+
 /* set field name */
 #define HUBBUB_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -337,6 +368,7 @@ struct dcn_hubbub_shift {
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
 	HUBBUB_RET_REG_FIELD_LIST(uint8_t);
+	HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
 };
 
 struct dcn_hubbub_mask {
@@ -344,6 +376,7 @@ struct dcn_hubbub_mask {
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
 	HUBBUB_RET_REG_FIELD_LIST(uint32_t);
+	HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
 };
 
 struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 3a7f76e2c598..564e061ccb58 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1188,6 +1188,8 @@ void hubp1_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e3a62873c0e7..fff724e94eed 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -51,6 +51,8 @@
 #include "link_hwss.h"
 #include "dpcd_defs.h"
 #include "dsc.h"
+#include "dce/dmub_psr.h"
+#include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
 #include "dc_trace.h"
 #include "dce/dmub_outbox.h"
@@ -2611,7 +2613,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
-
 	hubp->opp_id = pipe_ctx->stream_res.opp->inst;
 	hubp->mpcc_id = mpcc_id;
 }
@@ -3328,6 +3329,127 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 	return false;
 }
 
+static bool dcn10_dmub_should_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct dc_debug_options *debug)
+{
+	if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+		return false;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    debug->enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
+static void dcn10_dmub_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct hubp *hubp,
+		const struct dc_cursor_mi_param *param,
+		const struct dc_cursor_position *cur_pos,
+		const struct dc_cursor_attributes *cur_attr)
+{
+	union dmub_rb_cmd cmd;
+	struct dmub_cmd_update_cursor_info_data *update_cursor_info;
+	const struct dc_cursor_position *pos;
+	const struct dc_cursor_attributes *attr;
+	int src_x_offset = 0;
+	int src_y_offset = 0;
+	int x_hotspot = 0;
+	int cursor_height = 0;
+	int cursor_width = 0;
+	uint32_t cur_en = 0;
+	unsigned int panel_inst = 0;
+
+	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
+
+	if (!dcn10_dmub_should_update_cursor_data(pipe_ctx, debug))
+		return;
+	/**
+	 * if cur_pos == NULL means the caller is from cursor_set_attribute
+	 * then driver use previous cursor position data
+	 * if cur_attr == NULL means the caller is from cursor_set_position
+	 * then driver use previous cursor attribute
+	 * if cur_pos or cur_attr is not NULL then update it
+	 */
+	if (cur_pos != NULL)
+		pos = cur_pos;
+	else
+		pos = &hubp->curs_pos;
+
+	if (cur_attr != NULL)
+		attr = cur_attr;
+	else
+		attr = &hubp->curs_attr;
+
+	if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, pipe_ctx->stream->link, &panel_inst))
+		return;
+
+	src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
+	src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+	x_hotspot = pos->x_hotspot;
+	cursor_height = (int)attr->height;
+	cursor_width = (int)attr->width;
+	cur_en = pos->enable ? 1:0;
+
+	// Rotated cursor width/height and hotspots tweaks for offset calculation
+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
+		swap(cursor_height, cursor_width);
+		if (param->rotation == ROTATION_ANGLE_90) {
+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
+		}
+	} else if (param->rotation == ROTATION_ANGLE_180) {
+		src_x_offset = pos->x - param->viewport.x;
+		src_y_offset = pos->y - param->viewport.y;
+	}
+
+	if (param->mirror) {
+		x_hotspot = param->viewport.width - x_hotspot;
+		src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
+	}
+
+	if (src_x_offset >= (int)param->viewport.width)
+		cur_en = 0;  /* not visible beyond right edge*/
+
+	if (src_x_offset + cursor_width <= 0)
+		cur_en = 0;  /* not visible beyond left edge*/
+
+	if (src_y_offset >= (int)param->viewport.height)
+		cur_en = 0;  /* not visible beyond bottom edge*/
+
+	if (src_y_offset + cursor_height <= 0)
+		cur_en = 0;  /* not visible beyond top edge*/
+
+	// Cursor bitmaps have different hotspot values
+	// There's a possibility that the above logic returns a negative value, so we clamp them to 0
+	if (src_x_offset < 0)
+		src_x_offset = 0;
+	if (src_y_offset < 0)
+		src_y_offset = 0;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
+	cmd.update_cursor_info.header.payload_bytes =
+			sizeof(cmd.update_cursor_info.update_cursor_info_data);
+	update_cursor_info = &cmd.update_cursor_info.update_cursor_info_data;
+	update_cursor_info->cursor_rect.x = src_x_offset + param->viewport.x;
+	update_cursor_info->cursor_rect.y = src_y_offset + param->viewport.y;
+	update_cursor_info->cursor_rect.width = attr->width;
+	update_cursor_info->cursor_rect.height = attr->height;
+	update_cursor_info->enable = cur_en;
+	update_cursor_info->pipe_idx = pipe_ctx->pipe_idx;
+	update_cursor_info->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	update_cursor_info->panel_inst = panel_inst;
+	dc_dmub_srv_cmd_queue(pipe_ctx->stream->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(pipe_ctx->stream->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(pipe_ctx->stream->ctx->dmub_srv);
+}
+
 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
@@ -3526,6 +3648,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
 	}
 
+	dcn10_dmub_update_cursor_data(pipe_ctx, hubp, &param, &pos_cpy, NULL);
 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
 }
@@ -3533,6 +3656,25 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+	struct dc_cursor_mi_param param = { 0 };
+
+	/**
+	 * If enter PSR without cursor attribute update
+	 * the cursor attribute of dmub_restore_plane
+	 * are initial value. call dmub to exit PSR and
+	 * restore plane then update cursor attribute to
+	 * avoid override with initial value
+	 */
+	if (pipe_ctx->plane_state != NULL) {
+		param.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
+		param.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz;
+		param.viewport = pipe_ctx->plane_res.scl_data.viewport;
+		param.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz;
+		param.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert;
+		param.rotation = pipe_ctx->plane_state->rotation;
+		param.mirror = pipe_ctx->plane_state->horizontal_mirror;
+		dcn10_dmub_update_cursor_data(pipe_ctx, pipe_ctx->plane_res.hubp, &param, NULL, attributes);
+	}
 
 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
 			pipe_ctx->plane_res.hubp, attributes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 663aac0a164a..773380ef4997 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -167,6 +167,7 @@ struct dcn10_link_enc_registers {
 	uint32_t DIO_LINKD_CNTL;
 	uint32_t DIO_LINKE_CNTL;
 	uint32_t DIO_LINKF_CNTL;
+	uint32_t DIG_FIFO_CTRL0;
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -472,11 +473,15 @@ struct dcn10_link_enc_registers {
 	type HPO_DP_ENC_SEL;\
 	type HPO_HDMI_ENC_SEL
 
+#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
+	type DIG_FIFO_OUTPUT_PIXEL_MODE
+
 struct dcn10_link_enc_shift {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 };
 
 struct dcn10_link_enc_mask {
@@ -484,6 +489,7 @@ struct dcn10_link_enc_mask {
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 };
 
 struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index b1671b00ce40..e1a9a45b03b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -165,6 +165,7 @@ void optc1_program_timing(
 	optc1->vupdate_width = vupdate_width;
 	patched_crtc_timing = *dc_crtc_timing;
 	apply_front_porch_workaround(&patched_crtc_timing);
+	optc1->orginal_patched_timing = patched_crtc_timing;
 
 	/* Load horizontal timing */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index c50c29984d51..3fe5882ed018 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -521,13 +521,17 @@ struct dcn_optc_registers {
 	type OTG_CRC_DATA_FORMAT;\
 	type OTG_V_TOTAL_LAST_USED_BY_DRR;
 
+#define TG_REG_FIELD_LIST_DCN3_2(type) \
+	type OTG_H_TIMING_DIV_MODE_MANUAL;
 
 struct dcn_optc_shift {
 	TG_REG_FIELD_LIST(uint8_t)
+	TG_REG_FIELD_LIST_DCN3_2(uint8_t)
 };
 
 struct dcn_optc_mask {
 	TG_REG_FIELD_LIST(uint32_t)
+	TG_REG_FIELD_LIST_DCN3_2(uint32_t)
 };
 
 struct optc {
@@ -553,6 +557,7 @@ struct optc {
 	int vupdate_offset;
 	int vupdate_width;
 	int vready_offset;
+	struct dc_crtc_timing orginal_patched_timing;
 	enum signal_type signal;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 7608187751c8..92f474e6a96b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -675,11 +675,13 @@ static void enc1_stream_encoder_update_hdmi_info_packets(
 	/* for bring up, disable dp double  TODO */
 	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 
+	/*Always add mandatory packets first followed by optional ones*/
 	enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
-	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
+	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
 	enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
-	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
-	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
+	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
+	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
+	enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
 }
 
 static void enc1_stream_encoder_stop_hdmi_info_packets(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 293595a33982..f8d22ba6a6e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -73,6 +73,7 @@
 	SRI(HDMI_ACR_48_1, DIG, id),\
 	SRI(DP_DB_CNTL, DP, id), \
 	SRI(DP_MSA_MISC, DP, id), \
+	SRI(DP_MSA_VBID_MISC, DP, id), \
 	SRI(DP_MSA_COLORIMETRY, DP, id), \
 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
 	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
@@ -186,6 +187,7 @@ struct dcn10_stream_enc_registers {
 	uint32_t HDMI_GENERIC_PACKET_CONTROL9;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
 	uint32_t DIG_CLOCK_PATTERN;
+	uint32_t DIG_FIFO_CTRL0;
 };
 
 
@@ -337,8 +339,14 @@ struct dcn10_stream_enc_registers {
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+#else
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
+#endif
 
 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
 	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
@@ -567,16 +575,34 @@ struct dcn10_stream_enc_registers {
 	type DP_SEC_GSP11_ENABLE;\
 	type DP_SEC_GSP11_LINE_NUM
 
+#define SE_REG_FIELD_LIST_DCN3_2(type) \
+	type DIG_FIFO_OUTPUT_PIXEL_MODE;\
+	type DIG_SYMCLK_FE_ON;\
+	type DIG_FIFO_READ_START_LEVEL;\
+	type DIG_FIFO_ENABLE;\
+	type DIG_FIFO_RESET;\
+	type DIG_FIFO_RESET_DONE
+
 struct dcn10_stream_encoder_shift {
 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+	uint8_t HDMI_ACP_SEND;
+#endif
 	SE_REG_FIELD_LIST_DCN2_0(uint8_t);
 	SE_REG_FIELD_LIST_DCN3_0(uint8_t);
+	SE_REG_FIELD_LIST_DCN3_2(uint8_t);
+
 };
 
 struct dcn10_stream_encoder_mask {
 	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+	uint32_t HDMI_ACP_SEND;
+#endif
 	SE_REG_FIELD_LIST_DCN2_0(uint32_t);
 	SE_REG_FIELD_LIST_DCN3_0(uint32_t);
+	SE_REG_FIELD_LIST_DCN3_2(uint32_t);
+
 };
 
 struct dcn10_stream_encoder {
@@ -634,6 +660,9 @@ void enc1_stream_encoder_send_immediate_sdp_message(
 void enc1_stream_encoder_stop_dp_info_packets(
 	struct stream_encoder *enc);
 
+void enc1_stream_encoder_reset_fifo(
+	struct stream_encoder *enc);
+
 void enc1_stream_encoder_dp_blank(
 	struct dc_link *link,
 	struct stream_encoder *enc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index b3c9a9724efd..2b9d3e63191b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -133,6 +133,8 @@
 	type OTG_DROP_PIXEL[MAX_PIPES];
 
 #define DCCG3_REG_FIELD_LIST(type) \
+	type HDMICHARCLK0_EN;\
+	type HDMICHARCLK0_SRC_SEL;\
 	type PHYASYMCLK_FORCE_EN;\
 	type PHYASYMCLK_FORCE_SRC_SEL;\
 	type PHYBSYMCLK_FORCE_EN;\
@@ -203,16 +205,45 @@
 	type PHYDSYMCLK_GATE_DISABLE; \
 	type PHYESYMCLK_GATE_DISABLE;
 
+#define DCCG32_REG_FIELD_LIST(type) \
+	type DPSTREAMCLK0_EN;\
+	type DPSTREAMCLK1_EN;\
+	type DPSTREAMCLK2_EN;\
+	type DPSTREAMCLK3_EN;\
+	type DPSTREAMCLK0_SRC_SEL;\
+	type DPSTREAMCLK1_SRC_SEL;\
+	type DPSTREAMCLK2_SRC_SEL;\
+	type DPSTREAMCLK3_SRC_SEL;\
+	type HDMISTREAMCLK0_EN;\
+	type OTG0_PIXEL_RATE_DIVK1;\
+	type OTG0_PIXEL_RATE_DIVK2;\
+	type OTG1_PIXEL_RATE_DIVK1;\
+	type OTG1_PIXEL_RATE_DIVK2;\
+	type OTG2_PIXEL_RATE_DIVK1;\
+	type OTG2_PIXEL_RATE_DIVK2;\
+	type OTG3_PIXEL_RATE_DIVK1;\
+	type OTG3_PIXEL_RATE_DIVK2;\
+	type DTBCLK_P0_SRC_SEL;\
+	type DTBCLK_P0_EN;\
+	type DTBCLK_P1_SRC_SEL;\
+	type DTBCLK_P1_EN;\
+	type DTBCLK_P2_SRC_SEL;\
+	type DTBCLK_P2_EN;\
+	type DTBCLK_P3_SRC_SEL;\
+	type DTBCLK_P3_EN;
+
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
 	DCCG3_REG_FIELD_LIST(uint8_t)
 	DCCG31_REG_FIELD_LIST(uint8_t)
+	DCCG32_REG_FIELD_LIST(uint8_t)
 };
 
 struct dccg_mask {
 	DCCG_REG_FIELD_LIST(uint32_t)
 	DCCG3_REG_FIELD_LIST(uint32_t)
 	DCCG31_REG_FIELD_LIST(uint32_t)
+	DCCG32_REG_FIELD_LIST(uint32_t)
 };
 
 struct dccg_registers {
@@ -247,7 +278,8 @@ struct dccg_registers {
 	uint32_t DCCG_GATE_DISABLE_CNTL3;
 	uint32_t HDMISTREAMCLK0_DTO_PARAM;
 	uint32_t DCCG_GATE_DISABLE_CNTL4;
-
+	uint32_t OTG_PIXEL_RATE_DIV;
+	uint32_t DTBCLK_P_CNTL;
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 970b65efeac1..eaa7032f0f1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -212,6 +212,9 @@ static void dpp2_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index a665af19f201..9570c2118ccc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -967,6 +967,8 @@ void hubp2_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index 9204c3ef323b..efa2adf4f83d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -161,6 +161,12 @@
 	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
 	uint32_t DCN_DMDATA_VM_CNTL
 
+#define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \
+	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\
+	uint32_t DCHUBP_MALL_CONFIG;\
+	uint32_t DCHUBP_VMPG_CONFIG;\
+	uint32_t UCLK_PSTATE_FORCE
+
 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
 	type DMDATA_ADDRESS_HIGH;\
@@ -222,16 +228,29 @@
 	type CURSOR_REQ_MODE;\
 	type HUBP_SOFT_RESET
 
+#define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+	type USE_MALL_SEL; \
+	type USE_MALL_FOR_CURSOR;\
+	type VMPG_SIZE; \
+	type PTE_BUFFER_MODE; \
+	type BIGK_FRAGMENT_SIZE; \
+	type FORCE_ONE_ROW_FOR_FRAME; \
+	type DATA_UCLK_PSTATE_FORCE_EN; \
+	type DATA_UCLK_PSTATE_FORCE_VALUE; \
+	type CURSOR_UCLK_PSTATE_FORCE_EN; \
+	type CURSOR_UCLK_PSTATE_FORCE_VALUE
+
 struct dcn_hubp2_registers {
-	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
+	DCN32_HUBP_REG_COMMON_VARIABLE_LIST;
 };
 
 struct dcn_hubp2_shift {
-	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
 };
 
 struct dcn_hubp2_mask {
-	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
 };
 
 struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ec6aa8d8b251..76f8b40b2165 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -661,7 +661,17 @@ enum dc_status dcn20_enable_stream_timing(
 	struct mpc_dwb_flow_control flow_control;
 	struct mpc *mpc = dc->res_pool->mpc;
 	bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
+	unsigned int k1_div = PIXEL_RATE_DIV_NA;
+	unsigned int k2_div = PIXEL_RATE_DIV_NA;
 
+	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
+		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
+
+		dc->res_pool->dccg->funcs->set_pixel_rate_div(
+			dc->res_pool->dccg,
+			pipe_ctx->stream_res.tg->inst,
+			k1_div, k2_div);
+	}
 	/* by upper caller loop, pipe0 is parent pipe and be called first.
 	 * back end is set up by for pipe0. Other children pipe share back end
 	 * with pipe 0. No program is needed.
@@ -768,6 +778,10 @@ enum dc_status dcn20_enable_stream_timing(
 	/* TODO enable stream if timing changed */
 	/* TODO unblank stream if DP */
 
+	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+		if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
+			pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
+	}
 	return DC_OK;
 }
 
@@ -1247,6 +1261,16 @@ void dcn20_pipe_control_lock(
 					lock,
 					&hw_locks,
 					&inst_flags);
+	} else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+		union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
+		hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
+		hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
+		hw_lock_cmd.bits.lock_pipe = 1;
+		hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst;
+		hw_lock_cmd.bits.lock = lock;
+		if (!lock)
+			hw_lock_cmd.bits.should_release = 1;
+		dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 	} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
 		if (lock)
 			pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
@@ -1412,11 +1436,15 @@ static void dcn20_update_dchubp_dpp(
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+	struct dccg *dccg = dc->res_pool->dccg;
 	bool viewport_changed = false;
 
 	if (pipe_ctx->update_flags.bits.dppclk)
 		dpp->funcs->dpp_dppclk_control(dpp, false, true);
 
+	if (pipe_ctx->update_flags.bits.enable)
+		dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
+
 	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
 	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
 	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
@@ -1564,10 +1592,12 @@ static void dcn20_update_dchubp_dpp(
 		plane_state->update_flags.bits.addr_update)
 		hws->funcs.update_plane_addr(dc, pipe_ctx);
 
-
-
 	if (pipe_ctx->update_flags.bits.enable)
 		hubp->funcs->set_blank(hubp, false);
+	/* If the stream paired with this plane is phantom, the plane is also phantom */
+	if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM
+			&& hubp->funcs->phantom_hubp_post_enable)
+		hubp->funcs->phantom_hubp_post_enable(hubp);
 }
 
 
@@ -1578,6 +1608,7 @@ static void dcn20_program_pipe(
 {
 	struct dce_hwseq *hws = dc->hwseq;
 	/* Only need to unblank on top pipe */
+
 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
 		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
@@ -1585,7 +1616,6 @@ static void dcn20_program_pipe(
 	/* Only update TG on top pipe */
 	if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
 			&& !pipe_ctx->prev_odm_pipe) {
-
 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
 				pipe_ctx->stream_res.tg,
 				pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1593,7 +1623,12 @@ static void dcn20_program_pipe(
 				pipe_ctx->pipe_dlg_param.vupdate_offset,
 				pipe_ctx->pipe_dlg_param.vupdate_width);
 
-		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+		if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+				pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+				pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+		}
 
 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
@@ -1749,6 +1784,8 @@ void dcn20_program_front_end_for_ctx(
 			pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
 		}
 	}
+	if (hws->funcs.program_mall_pipe_config)
+		hws->funcs.program_mall_pipe_config(dc, context);
 }
 
 void dcn20_post_unlock_program_front_end(
@@ -2461,6 +2498,10 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	tg->funcs->set_early_control(tg, early_control);
 
+	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
+		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
+			timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);
+
 	/* enable audio only within mode set */
 	if (pipe_ctx->stream_res.audio != NULL) {
 		if (is_dp_128b_132b_signal(pipe_ctx))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index aab25ca8343a..e8f5c01688ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -159,6 +159,7 @@ static void enc2_stream_encoder_update_hdmi_info_packets(
 	enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
 	enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
 	enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
+	enc2_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
 }
 
 static void enc2_stream_encoder_stop_hdmi_info_packets(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
index f68038ceb1b1..96cbd4ccd344 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
@@ -18,7 +18,6 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index 8b6505b7dca8..f50ab961bc17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -153,6 +153,9 @@ static void dpp201_cnv_setup(
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index dfd77b3cc84d..c20331eb62e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -32,8 +32,8 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \
 
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -msse
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -45,8 +45,6 @@ ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1
 endif
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mhard-float
-CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mhard-float
 endif
 
 ifdef CONFIG_X86
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index a04ca4a98392..25e5c3bc1be9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -195,7 +195,7 @@ static void enc3_update_hdmi_info_packet(
 	}
 }
 
-static void enc3_stream_encoder_update_hdmi_info_packets(
+void enc3_stream_encoder_update_hdmi_info_packets(
 	struct stream_encoder *enc,
 	const struct encoder_info_frame *info_frame)
 {
@@ -212,9 +212,10 @@ static void enc3_stream_encoder_update_hdmi_info_packets(
 	enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
 	enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
 	enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
+	enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
 }
 
-static void enc3_stream_encoder_stop_hdmi_info_packets(
+void enc3_stream_encoder_stop_hdmi_info_packets(
 	struct stream_encoder *enc)
 {
 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@@ -318,7 +319,7 @@ static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
 }
 
 
-static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
+void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
 					bool enable,
 					uint8_t *dsc_packed_pps,
 					bool immediate_update)
@@ -404,7 +405,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
 	}
 }
 
-static void enc3_stream_encoder_update_dp_info_packets(
+void enc3_stream_encoder_update_dp_info_packets(
 	struct stream_encoder *enc,
 	const struct encoder_info_frame *info_frame)
 {
@@ -419,6 +420,21 @@ static void enc3_stream_encoder_update_dp_info_packets(
 				&info_frame->vsc,
 				true);
 	}
+	/* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
+	 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
+	 * In addition, currently the driver check the valid bit then update and
+	 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+	 * while entering PSR-SU mode. So we need another parameter(e.g. send)
+	 * in dc_info_packet to indicate which infopacket should be enabled by
+	 * default here.
+	 */
+	if (info_frame->vsc.valid) {
+		enc->vpg->funcs->update_generic_info_packet(
+				enc->vpg,
+				1,  /* packetIndex */
+				&info_frame->vsc,
+				true);
+	}
 	if (info_frame->spd.valid) {
 		enc->vpg->funcs->update_generic_info_packet(
 				enc->vpg,
@@ -652,7 +668,7 @@ static void enc3_stream_encoder_hdmi_set_stream_attribute(
 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 }
 
-static void enc3_audio_mute_control(
+void enc3_audio_mute_control(
 	struct stream_encoder *enc,
 	bool mute)
 {
@@ -660,7 +676,7 @@ static void enc3_audio_mute_control(
 	enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
 }
 
-static void enc3_se_dp_audio_setup(
+void enc3_se_dp_audio_setup(
 	struct stream_encoder *enc,
 	unsigned int az_inst,
 	struct audio_info *info)
@@ -691,7 +707,7 @@ static void enc3_se_setup_dp_audio(
 	enc->afmt->funcs->setup_dp_audio(enc->afmt);
 }
 
-static void enc3_se_dp_audio_enable(
+void enc3_se_dp_audio_enable(
 	struct stream_encoder *enc)
 {
 	enc1_se_enable_audio_clock(enc, true);
@@ -757,7 +773,7 @@ static void enc3_se_setup_hdmi_audio(
 	 */
 }
 
-static void enc3_se_hdmi_audio_setup(
+void enc3_se_hdmi_audio_setup(
 	struct stream_encoder *enc,
 	unsigned int az_inst,
 	struct audio_info *info,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
index 42140e73c3b2..d2207b35f15f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
@@ -287,4 +287,39 @@ void dcn30_dio_stream_encoder_construct(
 	const struct dcn10_stream_encoder_shift *se_shift,
 	const struct dcn10_stream_encoder_mask *se_mask);
 
+void enc3_stream_encoder_update_hdmi_info_packets(
+	struct stream_encoder *enc,
+	const struct encoder_info_frame *info_frame);
+
+void enc3_stream_encoder_stop_hdmi_info_packets(
+	struct stream_encoder *enc);
+
+void enc3_stream_encoder_update_dp_info_packets(
+	struct stream_encoder *enc,
+	const struct encoder_info_frame *info_frame);
+
+void enc3_audio_mute_control(
+	struct stream_encoder *enc,
+	bool mute);
+
+void enc3_se_dp_audio_setup(
+	struct stream_encoder *enc,
+	unsigned int az_inst,
+	struct audio_info *info);
+
+void enc3_se_dp_audio_enable(
+	struct stream_encoder *enc);
+
+void enc3_se_hdmi_audio_setup(
+	struct stream_encoder *enc,
+	unsigned int az_inst,
+	struct audio_info *info,
+	struct audio_crtc_info *audio_crtc_info);
+
+void enc3_dp_set_dsc_pps_info_packet(
+	struct stream_encoder *enc,
+	bool enable,
+	uint8_t *dsc_packed_pps,
+    bool immediate_update);
+
 #endif /* __DC_DIO_STREAM_ENCODER_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index ab3918c0a15b..3c77949b8110 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -41,9 +41,9 @@
 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
 
 
-static void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
+void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
 {
-	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 
 	REG_GET(DPP_CONTROL,
 			DPP_CLOCK_ENABLE, &s->is_enabled);
@@ -167,7 +167,7 @@ void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined t
 			PRE_DEGAM_SELECT, degamma_lut_selection);
 }
 
-static void dpp3_cnv_setup (
+void dpp3_cnv_setup (
 		struct dpp *dpp_base,
 		enum surface_pixel_format format,
 		enum expansion_mode mode,
@@ -294,6 +294,9 @@ static void dpp3_cnv_setup (
 		break;
 	}
 
+	/* Set default color space based on format if none is given. */
+	color_space = input_color_space ? input_color_space : color_space;
+
 	if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
@@ -372,7 +375,7 @@ void dpp3_set_cursor_attributes(
 }
 
 
-static bool dpp3_get_optimal_number_of_taps(
+bool dpp3_get_optimal_number_of_taps(
 		struct dpp *dpp,
 		struct scaler_data *scl_data,
 		const struct scaling_taps *in_taps)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index ac644ae6b9f2..6263408d71fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -588,6 +588,22 @@ void dpp3_program_CM_dealpha(
 		struct dpp *dpp_base,
 		uint32_t enable, uint32_t additive_blending);
 
+void dpp30_read_state(struct dpp *dpp_base,
+		struct dcn_dpp_state *s);
+
+bool dpp3_get_optimal_number_of_taps(
+		struct dpp *dpp,
+		struct scaler_data *scl_data,
+		const struct scaling_taps *in_taps);
+
+void dpp3_cnv_setup (
+		struct dpp *dpp_base,
+		enum surface_pixel_format format,
+		enum expansion_mode mode,
+		struct dc_csc_transform input_csc_color_matrix,
+		enum dc_color_space input_color_space,
+		struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+
 void dpp3_program_CM_bias(
 		struct dpp *dpp_base,
 		struct CM_bias_params *bias_params);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 782b8db451b4..08b8893ff145 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -48,6 +48,8 @@
 #include "dc_dmub_srv.h"
 #include "link_hwss.h"
 #include "dpcd_defs.h"
+#include "../dcn20/dcn20_hwseq.h"
+#include "dcn30_resource.h"
 #include "inc/dc_link_dp.h"
 #include "inc/link_dpcd.h"
 
@@ -344,17 +346,6 @@ void dcn30_enable_writeback(
 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
 }
 
-void dcn30_prepare_bandwidth(struct dc *dc,
- 	struct dc_state *context)
-{
-	if (dc->clk_mgr->dc_mode_softmax_enabled)
-		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
-				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
-			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
-
- 	dcn20_prepare_bandwidth(dc, context);
-}
-
 void dcn30_disable_writeback(
 		struct dc *dc,
 		unsigned int dwb_pipe_inst)
@@ -647,6 +638,9 @@ void dcn30_init_hw(struct dc *dc)
 	if (dc->res_pool->hubbub->funcs->init_crb)
 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 
+	// Get DMCUB capabilities
+	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 }
 
 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
@@ -959,35 +953,18 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset)
 {
-	struct stream_resource *stream_res = &pipe_ctx->stream_res;
-	struct pipe_ctx *mpcc_pipe;
-
-	if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
-		pipe_ctx->vtp_locked = false;
-		/* turning on DPG */
-		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
-				color_depth, solid_color, width, height, offset);
-
-		/* Defer hubp blank if tg is locked */
-		if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) {
-			if (stream_res->tg->funcs->is_locked(stream_res->tg))
-				pipe_ctx->vtp_locked = true;
-			else {
-				/* Blank HUBP to allow p-state during blank on all timings */
-				pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
-
-				for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
-					mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
-			}
-		}
-	} else {
-		/* turning off DPG */
-		pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
-		for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
-			if (mpcc_pipe->plane_res.hubp)
-				mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
-
-		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
-				color_depth, solid_color, width, height, offset);
-	}
+	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
+			color_space, color_depth, solid_color, width, height, offset);
 }
+
+void dcn30_prepare_bandwidth(struct dc *dc,
+ 	struct dc_state *context)
+{
+	if (dc->clk_mgr->dc_mode_softmax_enabled)
+		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
+				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
+			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
+
+ 	dcn20_prepare_bandwidth(dc, context);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index 73e7b690e82c..a24a8e33a3d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -47,9 +47,6 @@ void dcn30_disable_writeback(
 		struct dc *dc,
 		unsigned int dwb_pipe_inst);
 
-void dcn30_prepare_bandwidth(struct dc *dc,
- 	struct dc_state *context);
-
 bool dcn30_mmhubbub_warmup(
 	struct dc *dc,
 	unsigned int num_dwb,
@@ -83,4 +80,12 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset);
 
+void dcn30_set_hubp_blank(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		bool blank_enable);
+
+void dcn30_prepare_bandwidth(struct dc *dc,
+	struct dc_state *context);
+
+
 #endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index bb347319de83..4c06e6e1ba4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -59,7 +59,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.pipe_control_lock = dcn20_pipe_control_lock,
 	.interdependent_update_lock = dcn10_lock_all_pipes,
 	.cursor_lock = dcn10_cursor_lock,
-	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.prepare_bandwidth = dcn30_prepare_bandwidth,
 	.optimize_bandwidth = dcn20_optimize_bandwidth,
 	.update_bandwidth = dcn20_update_bandwidth,
 	.set_drr = dcn10_set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 0ce0d6165f43..1981a71b961b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -44,7 +44,7 @@
 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 
 
-static bool mpc3_is_dwb_idle(
+bool mpc3_is_dwb_idle(
 	struct mpc *mpc,
 	int dwb_id)
 {
@@ -59,7 +59,7 @@ static bool mpc3_is_dwb_idle(
 		return false;
 }
 
-static void mpc3_set_dwb_mux(
+void mpc3_set_dwb_mux(
 	struct mpc *mpc,
 	int dwb_id,
 	int mpcc_id)
@@ -70,7 +70,7 @@ static void mpc3_set_dwb_mux(
 		MPC_DWB0_MUX, mpcc_id);
 }
 
-static void mpc3_disable_dwb_mux(
+void mpc3_disable_dwb_mux(
 	struct mpc *mpc,
 	int dwb_id)
 {
@@ -80,7 +80,7 @@ static void mpc3_disable_dwb_mux(
 		MPC_DWB0_MUX, 0xf);
 }
 
-static void mpc3_set_out_rate_control(
+void mpc3_set_out_rate_control(
 	struct mpc *mpc,
 	int opp_id,
 	bool enable,
@@ -99,7 +99,7 @@ static void mpc3_set_out_rate_control(
 			MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1);
 }
 
-static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
+enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
 {
 	/*Contrary to DCN2 and DCN1 wherein a single status register field holds this info;
 	 *in DCN3/3AG, we need to read two separate fields to retrieve the same info
@@ -137,7 +137,7 @@ static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)
 		return mode;
 }
 
-static void mpc3_power_on_ogam_lut(
+void mpc3_power_on_ogam_lut(
 		struct mpc *mpc, int mpcc_id,
 		bool power_on)
 {
@@ -1035,7 +1035,7 @@ static void mpc3_set3dlut_ram10(
 }
 
 
-static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
 {
 	mpcc->mpcc_id = mpcc_inst;
 	mpcc->dpp_id = 0xf;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index 34b9cedbd012..a4d8f77d43bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -282,6 +282,73 @@
 	uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \
 	uint32_t MPC_OUT_CSC_COEF_FORMAT
 
+#define MPC_REG_VARIABLE_LIST_DCN32 \
+	uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \
+	uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \
+	uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \
+	uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC]
+
 #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \
 	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
@@ -580,6 +647,53 @@
 	type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
 	type MPC_RMU_SHAPER_MODE_CURRENT
 
+#define MPC_REG_FIELD_LIST_DCN32(type) \
+	type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\
+	type MPCC_MCM_SHAPER_MEM_PWR_DIS;\
+	type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_DIS;\
+	type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_DIS;\
+	type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\
+	type MPCC_MCM_SHAPER_MEM_PWR_STATE;\
+	type MPCC_MCM_3DLUT_MEM_PWR_STATE;\
+	type MPCC_MCM_1DLUT_MEM_PWR_STATE;\
+	type MPCC_MCM_3DLUT_MODE; \
+	type MPCC_MCM_3DLUT_SIZE; \
+	type MPCC_MCM_3DLUT_MODE_CURRENT; \
+	type MPCC_MCM_3DLUT_WRITE_EN_MASK;\
+	type MPCC_MCM_3DLUT_RAM_SEL;\
+	type MPCC_MCM_3DLUT_30BIT_EN;\
+	type MPCC_MCM_3DLUT_CONFIG_STATUS;\
+	type MPCC_MCM_3DLUT_READ_SEL;\
+	type MPCC_MCM_3DLUT_INDEX;\
+	type MPCC_MCM_3DLUT_DATA0;\
+	type MPCC_MCM_3DLUT_DATA1;\
+	type MPCC_MCM_3DLUT_DATA_30BIT;\
+	type MPCC_MCM_SHAPER_LUT_MODE;\
+	type MPCC_MCM_SHAPER_MODE_CURRENT;\
+	type MPCC_MCM_SHAPER_OFFSET_R;\
+	type MPCC_MCM_SHAPER_OFFSET_G;\
+	type MPCC_MCM_SHAPER_OFFSET_B;\
+	type MPCC_MCM_SHAPER_SCALE_R;\
+	type MPCC_MCM_SHAPER_SCALE_G;\
+	type MPCC_MCM_SHAPER_SCALE_B;\
+	type MPCC_MCM_SHAPER_LUT_INDEX;\
+	type MPCC_MCM_SHAPER_LUT_DATA;\
+	type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\
+	type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\
+	type MPCC_MCM_SHAPER_CONFIG_STATUS;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
+	type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS
+
 #define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \
 	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
@@ -758,14 +872,17 @@
 
 struct dcn30_mpc_registers {
 	MPC_REG_VARIABLE_LIST_DCN3_0;
+	MPC_REG_VARIABLE_LIST_DCN32;
 };
 
 struct dcn30_mpc_shift {
 	MPC_REG_FIELD_LIST_DCN3_0(uint8_t);
+	MPC_REG_FIELD_LIST_DCN32(uint8_t);
 };
 
 struct dcn30_mpc_mask {
 	MPC_REG_FIELD_LIST_DCN3_0(uint32_t);
+	MPC_REG_FIELD_LIST_DCN32(uint32_t);
 };
 
 struct dcn30_mpc {
@@ -841,4 +958,34 @@ void mpc3_set_rmu_mux(
 	int rmu_idx,
 	int value);
 
+void mpc3_set_dwb_mux(
+	struct mpc *mpc,
+	int dwb_id,
+	int mpcc_id);
+
+void mpc3_disable_dwb_mux(
+	struct mpc *mpc,
+	int dwb_id);
+
+bool mpc3_is_dwb_idle(
+	struct mpc *mpc,
+	int dwb_id);
+
+void mpc3_set_out_rate_control(
+	struct mpc *mpc,
+	int opp_id,
+	bool enable,
+	bool rate_2x_mode,
+	struct mpc_dwb_flow_control *flow_control);
+
+void mpc3_power_on_ogam_lut(
+	struct mpc *mpc, int mpcc_id,
+	bool power_on);
+
+void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
+
+enum dc_lut_mode mpc3_get_ogam_current(
+	struct mpc *mpc,
+	int mpcc_id);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index b604fb26f288..9a440ae8f865 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -27,6 +27,7 @@
 #include "dcn30_optc.h"
 #include "dc.h"
 #include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
 
 #include "dml/dcn30/dcn30_fpu.h"
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 97f11ef6e9f0..33bd12f5dc17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -28,6 +28,7 @@
 
 #include "dcn20/dcn20_optc.h"
 
+#define V_TOTAL_REGS_DCN30_SRI(inst)
 
 #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \
 	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
@@ -55,6 +56,7 @@
 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	V_TOTAL_REGS_DCN30_SRI(inst)\
 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
 	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
 	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
@@ -80,6 +82,7 @@
 	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
 	SRI(OTG_GSL_CONTROL, OTG, inst),\
 	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC_CNTL2, OTG, inst),\
 	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
 	SRI(OTG_CRC0_DATA_B, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
@@ -108,6 +111,7 @@
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SR(DWB_SOURCE_SELECT)
 
+#define DCN30_VTOTAL_REGS_SF(mask_sh)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh)\
 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -161,6 +165,7 @@
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	DCN30_VTOTAL_REGS_SF(mask_sh)\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
@@ -219,6 +224,10 @@
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
 	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 1c1a67c4cec1..4cf9a6cff46e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -89,6 +89,7 @@
 #include "vm_helper.h"
 #include "dcn20/dcn20_vmid.h"
 #include "amdgpu_socbb.h"
+#include "dc_dmub_srv.h"
 
 #define DC_LOGGER_INIT(logger)
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
index f9561d7f97a1..e4b69ad0dde5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
@@ -8,7 +8,7 @@
 DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
 
 ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -msse
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
 endif
 
 ifdef CONFIG_PPC64
@@ -16,6 +16,12 @@ CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec
 endif
 
 ifdef CONFIG_X86
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index bbc58d167c63..0faa1abd35ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -158,10 +158,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
 	}
 }
 
-void dccg31_set_dpstreamclk(
-		struct dccg *dccg,
-		enum hdmistreamclk_source src,
-		int otg_inst)
+void dccg31_set_dpstreamclk(struct dccg *dccg,
+			    enum streamclk_source src,
+			    int otg_inst)
 {
 	if (src == REFCLK)
 		dccg31_disable_dpstreamclk(dccg, otg_inst);
@@ -513,7 +512,7 @@ void dccg31_set_physymclk(
 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
 static void dccg31_set_dtbclk_dto(
 		struct dccg *dccg,
-		struct dtbclk_dto_params *params)
+		const struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 	int req_dtbclk_khz = params->pixclk_khz;
@@ -579,17 +578,17 @@ static void dccg31_set_dtbclk_dto(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		uint32_t req_audio_dtbclk_khz)
+		const struct dtbclk_dto_params *params)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-	if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) {
+	if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) {
 		uint32_t modulo, phase;
 
 		// phase / modulo = dtbclk / dtbclk ref
-		modulo = dccg->ref_dtbclk_khz * 1000;
-		phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
-			dccg->ref_dtbclk_khz);
+		modulo = params->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+			params->ref_dtbclk_khz);
 
 
 		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
@@ -663,6 +662,24 @@ void dccg31_init(struct dccg *dccg)
 	}
 }
 
+static void dccg31_otg_add_pixel(struct dccg *dccg,
+				 uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+static void dccg31_otg_drop_pixel(struct dccg *dccg,
+				  uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
 static const struct dccg_funcs dccg31_funcs = {
 	.update_dpp_dto = dccg31_update_dpp_dto,
 	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -675,6 +692,9 @@ static const struct dccg_funcs dccg31_funcs = {
 	.set_physymclk = dccg31_set_physymclk,
 	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg31_otg_add_pixel,
+	.otg_drop_pixel = dccg31_otg_drop_pixel,
 	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
 	.disable_dsc = dccg31_disable_dscclk,
 	.enable_dsc = dccg31_enable_dscclk,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 269cabbea72a..80bd80707991 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -28,10 +28,6 @@
 
 #include "dcn30/dcn30_dccg.h"
 
-#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
-	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
-
-
 #define DCCG_REG_LIST_DCN31() \
 	SR(DPPCLK_DTO_CTRL),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
@@ -124,6 +120,10 @@
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
 	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
@@ -163,7 +163,7 @@ void dccg31_init(struct dccg *dccg);
 
 void dccg31_set_dpstreamclk(
 		struct dccg *dccg,
-		enum hdmistreamclk_source src,
+		enum streamclk_source src,
 		int otg_inst);
 
 void dccg31_enable_symclk32_se(
@@ -192,10 +192,6 @@ void dccg31_set_physymclk(
 
 void dccg31_set_audio_dtbclk_dto(
 		struct dccg *dccg,
-		uint32_t req_audio_dtbclk_khz);
-
-void dccg31_set_hdmistreamclk(
-		struct dccg *dccg,
-		enum hdmistreamclk_source src);
+		const struct dtbclk_dto_params *params);
 
 #endif //__DCN31_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index 8b12b4111c88..a788d160953b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -458,6 +458,7 @@ void dcn31_link_encoder_enable_dp_output(
 	/* Enable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 
 	} else {
@@ -489,6 +490,7 @@ void dcn31_link_encoder_enable_dp_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 	}
 }
@@ -503,6 +505,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
 	/* Enable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 
 	} else {
@@ -534,6 +537,7 @@ void dcn31_link_encoder_enable_dp_mst_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 	}
 }
@@ -547,6 +551,7 @@ void dcn31_link_encoder_disable_output(
 	/* Disable transmitter and encoder. */
 	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 
+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc->preferred_engine);
 		dcn10_link_encoder_disable_output(enc, signal);
 
 	} else {
@@ -578,6 +583,7 @@ void dcn31_link_encoder_disable_output(
 			return;
 		}
 
+		DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);
 		link_dpia_control(enc->ctx, &dpia_control);
 
 		link_encoder_disable(enc10);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
index 197a5cae068b..84e1486f3d51 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
@@ -59,7 +59,7 @@ static void hubp31_program_extended_blank(struct hubp *hubp,
 {
 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 
-	REG_SET(BLANK_OFFSET_1, 0, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized);
+	REG_UPDATE(BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized);
 }
 
 static struct hubp_funcs dcn31_hubp_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 531dd2c65007..1ed1404e969d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -213,6 +213,28 @@ void dcn31_init_hw(struct dc *dc)
 	 * everything down.
 	 */
 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
+
+		// we want to turn off edp displays if odm is enabled and no seamless boot
+		if (!dc->caps.seamless_odm) {
+			for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+				struct timing_generator *tg = dc->res_pool->timing_generators[i];
+				uint32_t num_opps, opp_id_src0, opp_id_src1;
+
+				num_opps = 1;
+				if (tg) {
+					if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {
+						tg->funcs->get_optc_source(tg, &num_opps,
+								&opp_id_src0, &opp_id_src1);
+					}
+				}
+
+				if (num_opps > 1) {
+					dc_link_blank_all_edp_displays(dc);
+					break;
+				}
+			}
+		}
+
 		hws->funcs.init_pipes(dc, dc->current_state);
 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
@@ -591,7 +613,7 @@ void dcn31_reset_hw_ctx_wrap(
 	}
 
 	/* New dc_state in the process of being applied to hardware. */
-	dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
+	link_enc_cfg_set_transient_mode(dc, dc->current_state, context);
 }
 
 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index c51f7dca94f8..c4304f25ce95 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -266,6 +266,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc31_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_vtotal_min_max = optc1_set_vtotal_min_max,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index 9e881f2ce74b..3706e6f7880e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -98,7 +98,8 @@
 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SRI(OTG_CRC_CNTL2, OTG, inst),\
-	SR(DWB_SOURCE_SELECT)
+	SR(DWB_SOURCE_SELECT),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -252,7 +253,8 @@
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
-	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh)
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 void dcn31_timing_generator_init(struct optc *optc1);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 3d9f07d4770b..1a67d04cc017 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -890,7 +890,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.disable_z10 = true,
 	.optimize_edp_link_rate = true,
 	.enable_sw_cntl_psr = true,
-	.apply_vendor_specific_lttpr_wa = true,
 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 	.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
 };
@@ -1651,7 +1650,6 @@ int dcn31_populate_dml_pipes_from_context(
 			continue;
 		pipe = &res_ctx->pipe_ctx[i];
 		timing = &pipe->stream->timing;
-
 		if (pipe->plane_state &&
 				(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
 				pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 2b42af030b33..4f45753484fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1762,9 +1762,9 @@ static bool dcn315_resource_construct(
 	dc->caps.max_cursor_size = 256;
 	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
-	dc->caps.max_slave_planes = 1;
-	dc->caps.max_slave_yuv_planes = 1;
-	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
 	dc->caps.post_blend_color_processing = true;
 	dc->caps.force_dp_tps4_for_cp2520 = true;
 	dc->caps.dp_hpo = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index ef16260b7f3f..f9cee05aeccc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1764,9 +1764,9 @@ static bool dcn316_resource_construct(
 	dc->caps.max_cursor_size = 256;
 	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
-	dc->caps.max_slave_planes = 1;
-	dc->caps.max_slave_yuv_planes = 1;
-	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
 	dc->caps.post_blend_color_processing = true;
 	dc->caps.force_dp_tps4_for_cp2520 = true;
 	dc->caps.dp_hpo = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
new file mode 100644
index 000000000000..34f2e37b6704
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile
@@ -0,0 +1,45 @@
+#
+# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn32.
+
+DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_hwseq.o dcn32_init.o \
+		dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \
+		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \
+		dcn32_mpc.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn32/dcn32_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
new file mode 100644
index 000000000000..152a76ad7957
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn32_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+	container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+	(dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+	dccg_dcn->base.ctx
+#define DC_LOGGER \
+	dccg->ctx->logger
+
+static void dccg32_set_pixel_rate_div(
+		struct dccg *dccg,
+		uint32_t otg_inst,
+		enum pixel_rate_div k1,
+		enum pixel_rate_div k2)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	switch (otg_inst) {
+	case 0:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG0_PIXEL_RATE_DIVK1, k1,
+				OTG0_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 1:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG1_PIXEL_RATE_DIVK1, k1,
+				OTG1_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 2:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG2_PIXEL_RATE_DIVK1, k1,
+				OTG2_PIXEL_RATE_DIVK2, k2);
+		break;
+	case 3:
+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
+				OTG3_PIXEL_RATE_DIVK1, k1,
+				OTG3_PIXEL_RATE_DIVK2, k2);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+static void dccg32_set_dtbclk_p_src(
+		struct dccg *dccg,
+		enum streamclk_source src,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	uint32_t p_src_sel = 0; /* selects dprefclk */
+	if (src == DTBCLK0)
+		p_src_sel = 2;  /* selects dtbclk0 */
+
+	switch (otg_inst) {
+	case 0:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P0_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P0_SRC_SEL, p_src_sel,
+					DTBCLK_P0_EN, 1);
+		break;
+	case 1:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P1_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P1_SRC_SEL, p_src_sel,
+					DTBCLK_P1_EN, 1);
+		break;
+	case 2:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P2_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P2_SRC_SEL, p_src_sel,
+					DTBCLK_P2_EN, 1);
+		break;
+	case 3:
+		if (src == REFCLK)
+			REG_UPDATE(DTBCLK_P_CNTL,
+					DTBCLK_P3_EN, 0);
+		else
+			REG_UPDATE_2(DTBCLK_P_CNTL,
+					DTBCLK_P3_SRC_SEL, p_src_sel,
+					DTBCLK_P3_EN, 1);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+}
+
+/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
+void dccg32_set_dtbclk_dto(
+		struct dccg *dccg,
+		const struct dtbclk_dto_params *params)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+	/* DTO Output Rate / Pixel Rate = 1/4 */
+	int req_dtbclk_khz = params->pixclk_khz / 4;
+
+	if (params->ref_dtbclk_khz && req_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = params->ref_dtbclk_khz * 1000;
+		phase = req_dtbclk_khz * 1000;
+
+		REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
+		REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLK_DTO_ENABLE[params->otg_inst], 1);
+
+		REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
+				1, 100);
+
+		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
+		dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
+
+		/* The recommended programming sequence to enable DTBCLK DTO to generate
+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
+		 * be set only after DTO is enabled
+		 */
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				PIPE_DTO_SRC_SEL[params->otg_inst], 2);
+	} else {
+		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+				DTBCLK_DTO_ENABLE[params->otg_inst], 0,
+				PIPE_DTO_SRC_SEL[params->otg_inst], 1);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
+		REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
+	}
+}
+
+static void dccg32_set_valid_pixel_rate(
+		struct dccg *dccg,
+		int ref_dtbclk_khz,
+		int otg_inst,
+		int pixclk_khz)
+{
+	struct dtbclk_dto_params dto_params = {0};
+
+	dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+	dto_params.otg_inst = otg_inst;
+	dto_params.pixclk_khz = pixclk_khz;
+
+	dccg32_set_dtbclk_dto(dccg, &dto_params);
+}
+
+static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
+		unsigned int xtalin_freq_inKhz,
+		unsigned int *dccg_ref_freq_inKhz)
+{
+	/*
+	 * Assume refclk is sourced from xtalin
+	 * expect 100MHz
+	 */
+	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
+	return;
+}
+
+void dccg32_set_dpstreamclk(
+		struct dccg *dccg,
+		enum streamclk_source src,
+		int otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	/* set the dtbclk_p source */
+	dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
+
+	/* enabled to select one of the DTBCLKs for pipe */
+	switch (otg_inst)
+	{
+	case 0:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL,
+			     DPSTREAMCLK0_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0);
+		break;
+	case 1:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1);
+		break;
+	case 2:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2);
+		break;
+	case 3:
+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+void dccg32_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+void dccg32_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
+static const struct dccg_funcs dccg32_funcs = {
+	.update_dpp_dto = dccg2_update_dpp_dto,
+	.get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
+	.dccg_init = dccg31_init,
+	.set_dpstreamclk = dccg32_set_dpstreamclk,
+	.enable_symclk32_se = dccg31_enable_symclk32_se,
+	.disable_symclk32_se = dccg31_disable_symclk32_se,
+	.enable_symclk32_le = dccg31_enable_symclk32_le,
+	.disable_symclk32_le = dccg31_disable_symclk32_le,
+	.set_physymclk = dccg31_set_physymclk,
+	.set_dtbclk_dto = dccg32_set_dtbclk_dto,
+	.set_valid_pixel_rate = dccg32_set_valid_pixel_rate,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.otg_add_pixel = dccg32_otg_add_pixel,
+	.otg_drop_pixel = dccg32_otg_drop_pixel,
+	.set_pixel_rate_div = dccg32_set_pixel_rate_div,
+};
+
+struct dccg *dccg32_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask)
+{
+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+	struct dccg *base;
+
+	if (dccg_dcn == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	base = &dccg_dcn->base;
+	base->ctx = ctx;
+	base->funcs = &dccg32_funcs;
+
+	dccg_dcn->regs = regs;
+	dccg_dcn->dccg_shift = dccg_shift;
+	dccg_dcn->dccg_mask = dccg_mask;
+
+	return &dccg_dcn->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
new file mode 100644
index 000000000000..1c46fad0977b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_DCCG_H__
+#define __DCN32_DCCG_H__
+
+#include "dcn31/dcn31_dccg.h"
+
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
+
+#define DCCG_REG_LIST_DCN32() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
+	SR(PHYASYMCLK_CLOCK_CNTL),\
+	SR(PHYBSYMCLK_CLOCK_CNTL),\
+	SR(PHYCSYMCLK_CLOCK_CNTL),\
+	SR(PHYDSYMCLK_CLOCK_CNTL),\
+	SR(PHYESYMCLK_CLOCK_CNTL),\
+	SR(DPSTREAMCLK_CNTL),\
+	SR(HDMISTREAMCLK_CNTL),\
+	SR(SYMCLK32_SE_CNTL),\
+	SR(SYMCLK32_LE_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
+	SR(OTG_PIXEL_RATE_DIV),\
+	SR(DTBCLK_P_CNTL),\
+	SR(DCCG_AUDIO_DTO_SOURCE)
+
+
+#define DCCG_MASK_SH_LIST_DCN32(mask_sh) \
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
+
+
+struct dccg *dccg32_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+#endif //__DCN32_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
new file mode 100644
index 000000000000..d6855d4f749b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+#include "link_enc_cfg.h"
+
+#include "gpio_service_interface.h"
+
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+
+void enc32_hw_init(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+/*
+	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
+	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
+	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
+	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
+	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
+	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
+	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
+	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
+*/
+
+/*
+	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
+	AUX_RX_START_WINDOW = 1 [6:4]
+	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
+	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
+	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
+	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
+	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
+	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
+*/
+	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
+
+	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
+
+	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
+	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
+	// 27MHz -> 0xd
+	// 100MHz -> 0x32
+	// 48MHz -> 0x18
+
+	// Set TMDS_CTL0 to 1.  This is a legacy setting.
+	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
+
+	dcn10_aux_initialize(enc10);
+}
+
+
+void dcn32_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+		return;
+	}
+}
+
+bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	uint32_t dp_alt_mode_disable = 0;
+	bool is_usb_c_alt_mode = false;
+
+	if (enc->features.flags.bits.DP_IS_USB_C) {
+		/* if value == 1 alt mode is disabled, otherwise it is enabled */
+		REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+		is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
+	}
+
+	return is_usb_c_alt_mode;
+}
+
+void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
+	struct dc_link_settings *link_settings)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	uint32_t is_in_usb_c_dp4_mode = 0;
+
+	dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+	/* in usb c dp2 mode, max lane count is 2 */
+	if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+		REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+		if (!is_in_usb_c_dp4_mode)
+			link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
+	}
+
+}
+
+void enc32_set_dig_output_mode(struct link_encoder *enc, uint8_t pix_per_container)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container);
+}
+ 
+static const struct link_encoder_funcs dcn32_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc32_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn32_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn10_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+	.set_dig_output_mode = enc32_set_dig_output_mode,
+};
+
+void dcn32_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_connector_speed_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn32_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+		enc10->base.features.flags.bits.DP_IS_USB_C = 1;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	if (bp_funcs->get_connector_speed_cap_info)
+		result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.connector, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
+		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
+		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
+		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
new file mode 100644
index 000000000000..749a1e8cb811
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN32_H__
+#define __DC_LINK_ENCODER__DCN32_H__
+
+#include "dcn31/dcn31_dio_link_encoder.h"
+
+#define LE_DCN32_REG_LIST(id)\
+	LE_DCN31_REG_LIST(id),\
+	SRI(DIG_FIFO_CTRL0, DIG, id)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN32(mask_sh) \
+	LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh),\
+	LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)
+
+void dcn32_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+void enc32_hw_init(struct link_encoder *enc);
+
+void dcn32_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+void enc32_set_dig_output_mode(
+		struct link_encoder *enc,
+		uint8_t pix_per_container);
+
+#endif /* __DC_LINK_ENCODER__DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
new file mode 100644
index 000000000000..4d7588f2ee79
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -0,0 +1,461 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dc_bios_types.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32_dio_stream_encoder.h"
+#include "reg_helper.h"
+#include "hw_shared.h"
+#include "inc/link_dpcd.h"
+#include "dpcd_defs.h"
+
+#define DC_LOGGER \
+		enc1->base.ctx->logger
+
+#define REG(reg)\
+	(enc1->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc1->se_shift->field_name, enc1->se_mask->field_name
+
+#define VBI_LINE_0 0
+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
+
+#define CTX \
+	enc1->base.ctx
+
+
+
+static void enc32_dp_set_odm_combine(
+	struct stream_encoder *enc,
+	bool odm_combine)
+{
+	//struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	//TODO: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
+}
+
+/* setup stream encoder in dvi mode */
+void enc32_stream_encoder_dvi_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	bool is_dual_link)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		struct bp_encoder_control cntl = {0};
+
+		cntl.action = ENCODER_CONTROL_SETUP;
+		cntl.engine_id = enc1->base.id;
+		cntl.signal = is_dual_link ?
+			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
+		cntl.enable_dp_audio = false;
+		cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
+		cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
+
+		if (enc1->base.bp->funcs->encoder_control(
+				enc1->base.bp, &cntl) != BP_RESULT_OK)
+			return;
+
+	} else {
+
+		//Set pattern for clock channel, default vlue 0x63 does not work
+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
+
+		//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
+
+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
+
+		/* DIG_START is removed from the register spec */
+	}
+
+	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
+	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
+	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+}
+
+/* setup stream encoder in hdmi mode */
+static void enc32_stream_encoder_hdmi_set_stream_attribute(
+	struct stream_encoder *enc,
+	struct dc_crtc_timing *crtc_timing,
+	int actual_pix_clk_khz,
+	bool enable_audio)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+		struct bp_encoder_control cntl = {0};
+
+		cntl.action = ENCODER_CONTROL_SETUP;
+		cntl.engine_id = enc1->base.id;
+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
+		cntl.enable_dp_audio = enable_audio;
+		cntl.pixel_clock = actual_pix_clk_khz;
+		cntl.lanes_number = LANE_COUNT_FOUR;
+
+		if (enc1->base.bp->funcs->encoder_control(
+				enc1->base.bp, &cntl) != BP_RESULT_OK)
+			return;
+
+	} else {
+
+		//Set pattern for clock channel, default vlue 0x63 does not work
+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
+
+		//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
+
+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
+
+		/* DIG_START is removed from the register spec */
+	}
+
+	/* Configure pixel encoding */
+	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+
+	/* setup HDMI engine */
+	REG_UPDATE_6(HDMI_CONTROL,
+		HDMI_PACKET_GEN_VERSION, 1,
+		HDMI_KEEPOUT_MODE, 1,
+		HDMI_DEEP_COLOR_ENABLE, 0,
+		HDMI_DATA_SCRAMBLE_EN, 0,
+		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
+		HDMI_CLOCK_CHANNEL_RATE, 0);
+
+	/* Configure color depth */
+	switch (crtc_timing->display_color_depth) {
+	case COLOR_DEPTH_888:
+		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
+		break;
+	case COLOR_DEPTH_101010:
+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 1,
+					HDMI_DEEP_COLOR_ENABLE, 0);
+		} else {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 1,
+					HDMI_DEEP_COLOR_ENABLE, 1);
+			}
+		break;
+	case COLOR_DEPTH_121212:
+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 2,
+					HDMI_DEEP_COLOR_ENABLE, 0);
+		} else {
+			REG_UPDATE_2(HDMI_CONTROL,
+					HDMI_DEEP_COLOR_DEPTH, 2,
+					HDMI_DEEP_COLOR_ENABLE, 1);
+			}
+		break;
+	case COLOR_DEPTH_161616:
+		REG_UPDATE_2(HDMI_CONTROL,
+				HDMI_DEEP_COLOR_DEPTH, 3,
+				HDMI_DEEP_COLOR_ENABLE, 1);
+		break;
+	default:
+		break;
+	}
+
+	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
+		/* enable HDMI data scrambler
+		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
+		 * Clock channel frequency is 1/4 of character rate.
+		 */
+		REG_UPDATE_2(HDMI_CONTROL,
+			HDMI_DATA_SCRAMBLE_EN, 1,
+			HDMI_CLOCK_CHANNEL_RATE, 1);
+	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
+
+		/* TODO: New feature for DCE11, still need to implement */
+
+		/* enable HDMI data scrambler
+		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
+		 * Clock channel frequency is the same
+		 * as character rate
+		 */
+		REG_UPDATE_2(HDMI_CONTROL,
+			HDMI_DATA_SCRAMBLE_EN, 1,
+			HDMI_CLOCK_CHANNEL_RATE, 0);
+	}
+
+
+	/* Enable transmission of General Control packet on every frame */
+	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
+		HDMI_GC_CONT, 1,
+		HDMI_GC_SEND, 1,
+		HDMI_NULL_SEND, 1);
+
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+	/* Disable Audio Content Protection packet transmission */
+	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
+#endif
+
+	/* following belongs to audio */
+	/* Enable Audio InfoFrame packet transmission. */
+	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
+
+	/* update double-buffered AUDIO_INFO registers immediately */
+	ASSERT(enc->afmt);
+	enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
+
+	/* Select line number on which to send Audio InfoFrame packets */
+	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
+				VBI_LINE_0 + 2);
+
+	/* set HDMI GC AVMUTE */
+	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
+}
+
+
+
+static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+{
+	bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+
+	two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+			&& !timing->dsc_cfg.ycbcr422_simple);
+	return two_pix;
+}
+
+static void enc32_stream_encoder_dp_unblank(
+        struct dc_link *link,
+		struct stream_encoder *enc,
+		const struct encoder_unblank_param *param)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
+		uint32_t n_vid = 0x8000;
+		uint32_t m_vid;
+		uint32_t n_multiply = 0;
+		uint64_t m_vid_l = n_vid;
+
+		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
+		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
+			/*this logic should be the same in get_pixel_clock_parameters() */
+			n_multiply = 1;
+		}
+		/* M / N = Fstream / Flink
+		 * m_vid / n_vid = pixel rate / link rate
+		 */
+
+		m_vid_l *= param->timing.pix_clk_100hz / 10;
+		m_vid_l = div_u64(m_vid_l,
+			param->link_settings.link_rate
+				* LINK_RATE_REF_FREQ_IN_KHZ);
+
+		m_vid = (uint32_t) m_vid_l;
+
+		/* enable auto measurement */
+
+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
+
+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
+		 * therefore program initial value for Mvid and Nvid
+		 */
+
+		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
+
+		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
+
+		REG_UPDATE_2(DP_VID_TIMING,
+				DP_VID_M_N_GEN_EN, 1,
+				DP_VID_N_MUL, n_multiply);
+	}
+
+	/* make sure stream is disabled before resetting steer fifo */
+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
+	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
+
+	/* DIG_START is removed from the register spec */
+
+	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
+	 * that it overflows during mode transition, and sometimes doesn't recover.
+	 */
+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
+	udelay(10);
+
+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
+
+	/* DIG Resync FIFO now needs to be explicitly enabled
+	 */
+	// TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
+	REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
+
+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
+
+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
+
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
+
+	/* wait 100us for DIG/DP logic to prime
+	 * (i.e. a few video lines)
+	 */
+	udelay(100);
+
+	/* the hardware would start sending video at the start of the next DP
+	 * frame (i.e. rising edge of the vblank).
+	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
+	 * register has no effect on enable transition! HW always guarantees
+	 * VID_STREAM enable at start of next frame, and this is not
+	 * programmable
+	 */
+
+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
+
+	dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
+}
+
+/* Set DSC-related configuration.
+ *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
+ *   sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32
+ *   dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32
+ */
+static void enc32_dp_set_dsc_config(struct stream_encoder *enc,
+					enum optc_dsc_mode dsc_mode,
+					uint32_t dsc_bytes_per_pixel,
+					uint32_t dsc_slice_width)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	REG_UPDATE(DP_DSC_CNTL,	DP_DSC_MODE, dsc_mode);
+}
+
+/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
+ * into a dcn_dsc_state struct.
+ */
+static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	//if dsc is enabled, continue to read
+	REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
+	if (s->dsc_mode) {
+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
+
+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
+
+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
+		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
+	}
+}
+
+static void enc32_stream_encoder_reset_fifo(struct stream_encoder *enc)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+	uint32_t fifo_enabled;
+
+	REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &fifo_enabled);
+
+	if (fifo_enabled == 0) {
+		/* reset DIG resync FIFO */
+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
+		/* TODO: fix timeout when wait for DIG_FIFO_RESET_DONE */
+		//REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 1, 100);
+		udelay(1);
+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
+		REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 1, 100);
+	}
+}
+
+static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
+	.dp_set_odm_combine =
+		enc32_dp_set_odm_combine,
+	.dp_set_stream_attribute =
+		enc2_stream_encoder_dp_set_stream_attribute,
+	.hdmi_set_stream_attribute =
+		enc32_stream_encoder_hdmi_set_stream_attribute,
+	.dvi_set_stream_attribute =
+		enc32_stream_encoder_dvi_set_stream_attribute,
+	.set_throttled_vcp_size =
+		enc1_stream_encoder_set_throttled_vcp_size,
+	.update_hdmi_info_packets =
+		enc3_stream_encoder_update_hdmi_info_packets,
+	.stop_hdmi_info_packets =
+		enc3_stream_encoder_stop_hdmi_info_packets,
+	.update_dp_info_packets =
+		enc3_stream_encoder_update_dp_info_packets,
+	.stop_dp_info_packets =
+		enc1_stream_encoder_stop_dp_info_packets,
+	.reset_fifo =
+		enc32_stream_encoder_reset_fifo,
+	.dp_blank =
+		enc1_stream_encoder_dp_blank,
+	.dp_unblank =
+		enc32_stream_encoder_dp_unblank,
+	.audio_mute_control = enc3_audio_mute_control,
+
+	.dp_audio_setup = enc3_se_dp_audio_setup,
+	.dp_audio_enable = enc3_se_dp_audio_enable,
+	.dp_audio_disable = enc1_se_dp_audio_disable,
+
+	.hdmi_audio_setup = enc3_se_hdmi_audio_setup,
+	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
+	.setup_stereo_sync  = enc1_setup_stereo_sync,
+	.set_avmute = enc1_stream_encoder_set_avmute,
+	.dig_connect_to_otg = enc1_dig_connect_to_otg,
+	.dig_source_otg = enc1_dig_source_otg,
+
+	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
+
+	.enc_read_state = enc32_read_state,
+	.dp_set_dsc_config = enc32_dp_set_dsc_config,
+	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
+	.set_dynamic_metadata = enc2_set_dynamic_metadata,
+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+};
+
+void dcn32_dio_stream_encoder_construct(
+	struct dcn10_stream_encoder *enc1,
+	struct dc_context *ctx,
+	struct dc_bios *bp,
+	enum engine_id eng_id,
+	struct vpg *vpg,
+	struct afmt *afmt,
+	const struct dcn10_stream_enc_registers *regs,
+	const struct dcn10_stream_encoder_shift *se_shift,
+	const struct dcn10_stream_encoder_mask *se_mask)
+{
+	enc1->base.funcs = &dcn32_str_enc_funcs;
+	enc1->base.ctx = ctx;
+	enc1->base.id = eng_id;
+	enc1->base.bp = bp;
+	enc1->base.vpg = vpg;
+	enc1->base.afmt = afmt;
+	enc1->regs = regs;
+	enc1->se_shift = se_shift;
+	enc1->se_mask = se_mask;
+	enc1->base.stream_enc_inst = vpg->inst;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
new file mode 100644
index 000000000000..042bc9aca944
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2021 - Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DIO_STREAM_ENCODER_DCN32_H__
+#define __DC_DIO_STREAM_ENCODER_DCN32_H__
+
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "stream_encoder.h"
+#include "dcn20/dcn20_stream_encoder.h"
+
+#define SE_DCN32_REG_LIST(id)\
+	SRI(AFMT_CNTL, DIG, id), \
+	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(HDMI_CONTROL, DIG, id), \
+	SRI(HDMI_DB_CONTROL, DIG, id), \
+	SRI(HDMI_GC, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
+	SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
+	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
+	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
+	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
+	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
+	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
+	SRI(HDMI_ACR_32_0, DIG, id),\
+	SRI(HDMI_ACR_32_1, DIG, id),\
+	SRI(HDMI_ACR_44_0, DIG, id),\
+	SRI(HDMI_ACR_44_1, DIG, id),\
+	SRI(HDMI_ACR_48_0, DIG, id),\
+	SRI(HDMI_ACR_48_1, DIG, id),\
+	SRI(DP_DB_CNTL, DP, id), \
+	SRI(DP_MSA_MISC, DP, id), \
+	SRI(DP_MSA_VBID_MISC, DP, id), \
+	SRI(DP_MSA_COLORIMETRY, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
+	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
+	SRI(DP_MSE_RATE_CNTL, DP, id), \
+	SRI(DP_MSE_RATE_UPDATE, DP, id), \
+	SRI(DP_PIXEL_FORMAT, DP, id), \
+	SRI(DP_SEC_CNTL, DP, id), \
+	SRI(DP_SEC_CNTL2, DP, id), \
+	SRI(DP_SEC_CNTL6, DP, id), \
+	SRI(DP_STEER_FIFO, DP, id), \
+	SRI(DP_VID_M, DP, id), \
+	SRI(DP_VID_N, DP, id), \
+	SRI(DP_VID_STREAM_CNTL, DP, id), \
+	SRI(DP_VID_TIMING, DP, id), \
+	SRI(DP_SEC_AUD_N, DP, id), \
+	SRI(DP_SEC_TIMESTAMP, DP, id), \
+	SRI(DP_DSC_CNTL, DP, id), \
+	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI(DP_SEC_FRAMING4, DP, id), \
+	SRI(DP_GSP11_CNTL, DP, id), \
+	SRI(DME_CONTROL, DME, id),\
+	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
+	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
+	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_CLOCK_PATTERN, DIG, id), \
+	SRI(DIG_FIFO_CTRL0, DIG, id)
+
+
+#define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\
+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
+	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
+	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
+	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
+	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
+	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
+	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
+	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
+	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
+	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
+	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\
+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\
+	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
+	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
+	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
+	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\
+	SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\
+	SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SYMCLK_FE_ON, mask_sh),\
+	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\
+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)
+
+#if defined(CONFIG_DRM_AMD_DC_HDCP)
+#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh),\
+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)
+#else
+#define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\
+	SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)
+#endif
+
+void dcn32_dio_stream_encoder_construct(
+	struct dcn10_stream_encoder *enc1,
+	struct dc_context *ctx,
+	struct dc_bios *bp,
+	enum engine_id eng_id,
+	struct vpg *vpg,
+	struct afmt *afmt,
+	const struct dcn10_stream_enc_registers *regs,
+	const struct dcn10_stream_encoder_shift *se_shift,
+	const struct dcn10_stream_encoder_mask *se_mask);
+
+#endif /* __DC_DIO_STREAM_ENCODER_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
new file mode 100644
index 000000000000..f349cbe2a0f0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "core_types.h"
+#include "reg_helper.h"
+#include "dcn32_dpp.h"
+#include "basics/conversion.h"
+#include "dcn30/dcn30_cm_common.h"
+
+/* Compute the maximum number of lines that we can fit in the line buffer */
+void dscl32_calc_lb_num_partitions(
+		const struct scaler_data *scl_data,
+		enum lb_memory_config lb_config,
+		int *num_part_y,
+		int *num_part_c)
+{
+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,
+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
+
+	int line_size = scl_data->viewport.width < scl_data->recout.width ?
+			scl_data->viewport.width : scl_data->recout.width;
+	int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
+			scl_data->viewport_c.width : scl_data->recout.width;
+
+	if (line_size == 0)
+		line_size = 1;
+
+	if (line_size_c == 0)
+		line_size_c = 1;
+
+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
+
+	if (lb_config == LB_MEMORY_CONFIG_1) {
+		lb_memory_size = 970;
+		lb_memory_size_c = 970;
+		lb_memory_size_a = 970;
+	} else if (lb_config == LB_MEMORY_CONFIG_2) {
+		lb_memory_size = 1290;
+		lb_memory_size_c = 1290;
+		lb_memory_size_a = 1290;
+	} else if (lb_config == LB_MEMORY_CONFIG_3) {
+		if (scl_data->viewport.width  == scl_data->h_active &&
+			scl_data->viewport.height == scl_data->v_active) {
+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
+			/* use increased LB size for calculation only if Scaler not enabled */
+			lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;
+			lb_memory_size_c = 970 + 1290;
+			lb_memory_size_a = 970 + 1290 + 1170;
+		} else {
+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
+			lb_memory_size = 970 + 1290 + 484 + 484 + 484;
+			lb_memory_size_c = 970 + 1290;
+			lb_memory_size_a = 970 + 1290 + 484;
+		}
+	} else {
+		if (scl_data->viewport.width  == scl_data->h_active &&
+			scl_data->viewport.height == scl_data->v_active) {
+			/* use increased LB size for calculation only if Scaler not enabled */
+			lb_memory_size = 970 + 1290 + 1170;
+			lb_memory_size_c = 970 + 1290 + 1170;
+			lb_memory_size_a = 970 + 1290 + 1170;
+		} else {
+			lb_memory_size = 970 + 1290 + 484;
+			lb_memory_size_c = 970 + 1290 + 484;
+			lb_memory_size_a = 970 + 1290 + 484;
+		}
+	}
+	*num_part_y = lb_memory_size / memory_line_size_y;
+	*num_part_c = lb_memory_size_c / memory_line_size_c;
+	num_partitions_a = lb_memory_size_a / memory_line_size_a;
+
+	if (scl_data->lb_params.alpha_en
+			&& (num_partitions_a < *num_part_y))
+		*num_part_y = num_partitions_a;
+
+	if (*num_part_y > 32)
+		*num_part_y = 32;
+	if (*num_part_c > 32)
+		*num_part_c = 32;
+}
+
+static struct dpp_funcs dcn32_dpp_funcs = {
+	.dpp_program_gamcor_lut		= dpp3_program_gamcor_lut,
+	.dpp_read_state				= dpp30_read_state,
+	.dpp_reset					= dpp_reset,
+	.dpp_set_scaler				= dpp1_dscl_set_scaler_manual_scale,
+	.dpp_get_optimal_number_of_taps	= dpp3_get_optimal_number_of_taps,
+	.dpp_set_gamut_remap		= dpp3_cm_set_gamut_remap,
+	.dpp_set_csc_adjustment		= NULL,
+	.dpp_set_csc_default		= NULL,
+	.dpp_program_regamma_pwl	= NULL,
+	.dpp_set_pre_degam			= dpp3_set_pre_degam,
+	.dpp_program_input_lut		= NULL,
+	.dpp_full_bypass			= dpp1_full_bypass,
+	.dpp_setup					= dpp3_cnv_setup,
+	.dpp_program_degamma_pwl	= NULL,
+	.dpp_program_cm_dealpha		= dpp3_program_cm_dealpha,
+	.dpp_program_cm_bias		= dpp3_program_cm_bias,
+
+	.dpp_program_blnd_lut		= NULL, // BLNDGAM is removed completely in DCN3.2 DPP
+	.dpp_program_shaper_lut		= NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
+	.dpp_program_3dlut			= NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
+
+	.dpp_program_bias_and_scale	= NULL,
+	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,
+	.set_cursor_attributes		= dpp3_set_cursor_attributes,
+	.set_cursor_position		= dpp1_set_cursor_position,
+	.set_optional_cursor_attributes	= dpp1_cnv_set_optional_cursor_attributes,
+	.dpp_dppclk_control			= dpp1_dppclk_control,
+	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,
+};
+
+
+static struct dpp_caps dcn32_dpp_cap = {
+	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
+	.max_lb_partitions = 31,
+	.dscl_calc_lb_num_partitions = dscl32_calc_lb_num_partitions,
+};
+
+bool dpp32_construct(
+	struct dcn3_dpp *dpp,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn3_dpp_registers *tf_regs,
+	const struct dcn3_dpp_shift *tf_shift,
+	const struct dcn3_dpp_mask *tf_mask)
+{
+	dpp->base.ctx = ctx;
+
+	dpp->base.inst = inst;
+	dpp->base.funcs = &dcn32_dpp_funcs;
+	dpp->base.caps = &dcn32_dpp_cap;
+
+	dpp->tf_regs = tf_regs;
+	dpp->tf_shift = tf_shift;
+	dpp->tf_mask = tf_mask;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
new file mode 100644
index 000000000000..572958d287eb
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN32_DPP_H__
+#define __DCN32_DPP_H__
+
+#include "dcn20/dcn20_dpp.h"
+#include "dcn30/dcn30_dpp.h"
+
+bool dpp32_construct(struct dcn3_dpp *dpp3,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn3_dpp_registers *tf_regs,
+	const struct dcn3_dpp_shift *tf_shift,
+	const struct dcn3_dpp_mask *tf_mask);
+
+#endif /* __DCN32_DPP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
new file mode 100644
index 000000000000..4dbad8d4b4fc
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dc_bios_types.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32_hpo_dp_link_encoder.h"
+#include "reg_helper.h"
+#include "dc_link.h"
+#include "stream_encoder.h"
+
+#define DC_LOGGER \
+		enc3->base.ctx->logger
+
+#define REG(reg)\
+	(enc3->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name
+
+#define CTX \
+	enc3->base.ctx
+
+static bool dcn32_hpo_dp_link_enc_is_in_alt_mode(
+		struct hpo_dp_link_encoder *enc)
+{
+	struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+	uint32_t dp_alt_mode_disable = 0;
+
+	ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
+
+	/* if value == 1 alt mode is disabled, otherwise it is enabled */
+	REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+	return (dp_alt_mode_disable == 0);
+}
+
+
+
+static struct hpo_dp_link_encoder_funcs dcn32_hpo_dp_link_encoder_funcs = {
+	.enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output,
+	.disable_link_phy = dcn31_hpo_dp_link_enc_disable_output,
+	.link_enable = dcn31_hpo_dp_link_enc_enable,
+	.link_disable = dcn31_hpo_dp_link_enc_disable,
+	.set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern,
+	.update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table,
+	.set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size,
+	.is_in_alt_mode = dcn32_hpo_dp_link_enc_is_in_alt_mode,
+	.read_state = dcn31_hpo_dp_link_enc_read_state,
+	.set_ffe = dcn31_hpo_dp_link_enc_set_ffe,
+};
+
+void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+		struct dc_context *ctx,
+		uint32_t inst,
+		const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+		const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+		const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask)
+{
+	enc31->base.ctx = ctx;
+
+	enc31->base.inst = inst;
+	enc31->base.funcs = &dcn32_hpo_dp_link_encoder_funcs;
+	enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN;
+	enc31->base.transmitter = TRANSMITTER_UNKNOWN;
+
+	enc31->regs = hpo_le_regs;
+	enc31->hpo_le_shift = hpo_le_shift;
+	enc31->hpo_le_mask = hpo_le_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
new file mode 100644
index 000000000000..9db1323e1933
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
+#define __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
+
+#include "link_encoder.h"
+
+#define DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+	SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
+	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
+
+void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+	const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+	const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);
+
+#endif   // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
new file mode 100644
index 000000000000..99eb239bbc7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -0,0 +1,964 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn32_hubbub.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+
+
+#define CTX \
+	hubbub2->base.ctx
+#define DC_LOGGER \
+	hubbub2->base.ctx->logger
+#define REG(reg)\
+	hubbub2->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub2->shifts->field_name, hubbub2->masks->field_name
+
+#define DCN32_CRB_SEGMENT_SIZE_KB 64
+
+static void dcn32_init_crb(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
+		&hubbub2->det0_size);
+
+	REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
+		&hubbub2->det1_size);
+
+	REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
+		&hubbub2->det2_size);
+
+	REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
+		&hubbub2->det3_size);
+
+	REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
+		&hubbub2->compbuf_size_segments);
+
+	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
+			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
+			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
+	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);
+}
+
+static void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_UPDATE(DCHUBBUB_DET0_CTRL,
+					DET0_SIZE, det_size_segments);
+		hubbub2->det0_size = det_size_segments;
+		break;
+	case 1:
+		REG_UPDATE(DCHUBBUB_DET1_CTRL,
+					DET1_SIZE, det_size_segments);
+		hubbub2->det1_size = det_size_segments;
+		break;
+	case 2:
+		REG_UPDATE(DCHUBBUB_DET2_CTRL,
+					DET2_SIZE, det_size_segments);
+		hubbub2->det2_size = det_size_segments;
+		break;
+	case 3:
+		REG_UPDATE(DCHUBBUB_DET3_CTRL,
+					DET3_SIZE, det_size_segments);
+		hubbub2->det3_size = det_size_segments;
+		break;
+	default:
+		break;
+	}
+	/* Should never be hit, if it is we have an erroneous hw config*/
+	ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+			+ hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs);
+}
+
+static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB;
+
+	if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) {
+		if (compbuf_size_segments > hubbub2->compbuf_size_segments) {
+			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);
+		}
+		/* Should never be hit, if it is we have an erroneous hw config*/
+		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
+		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
+		hubbub2->compbuf_size_segments = compbuf_size_segments;
+		ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
+	}
+}
+
+static uint32_t convert_and_clamp(
+	uint32_t wm_ns,
+	uint32_t refclk_mhz,
+	uint32_t clamp_value)
+{
+	uint32_t ret_val = 0;
+	ret_val = wm_ns * refclk_mhz;
+
+	ret_val /= 1000;
+
+	if (ret_val > clamp_value)
+		ret_val = clamp_value;
+
+	return ret_val;
+}
+
+static bool hubbub32_program_urgent_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* Repeat for water mark set A, B, C and D. */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) {
+		hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.urgent_ns, prog_wm_value);
+	} else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
+			> hubbub2->watermarks.a.frac_urg_bw_flip) {
+		hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
+	} else if (watermarks->a.frac_urg_bw_flip
+			< hubbub2->watermarks.a.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
+			> hubbub2->watermarks.a.frac_urg_bw_nom) {
+		hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+	} else if (watermarks->a.frac_urg_bw_nom
+			< hubbub2->watermarks.a.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) {
+		hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
+	} else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) {
+		hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.urgent_ns, prog_wm_value);
+	} else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->b.frac_urg_bw_flip
+			> hubbub2->watermarks.b.frac_urg_bw_flip) {
+		hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip);
+	} else if (watermarks->b.frac_urg_bw_flip
+			< hubbub2->watermarks.b.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.frac_urg_bw_nom
+			> hubbub2->watermarks.b.frac_urg_bw_nom) {
+		hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom);
+	} else if (watermarks->b.frac_urg_bw_nom
+			< hubbub2->watermarks.b.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) {
+		hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
+	} else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) {
+		hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.urgent_ns, prog_wm_value);
+	} else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->c.frac_urg_bw_flip
+			> hubbub2->watermarks.c.frac_urg_bw_flip) {
+		hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip);
+	} else if (watermarks->c.frac_urg_bw_flip
+			< hubbub2->watermarks.c.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.frac_urg_bw_nom
+			> hubbub2->watermarks.c.frac_urg_bw_nom) {
+		hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom);
+	} else if (watermarks->c.frac_urg_bw_nom
+			< hubbub2->watermarks.c.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) {
+		hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
+	} else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) {
+		hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.urgent_ns, prog_wm_value);
+	} else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->d.frac_urg_bw_flip
+			> hubbub2->watermarks.d.frac_urg_bw_flip) {
+		hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip);
+	} else if (watermarks->d.frac_urg_bw_flip
+			< hubbub2->watermarks.d.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.frac_urg_bw_nom
+			> hubbub2->watermarks.d.frac_urg_bw_nom) {
+		hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom);
+	} else if (watermarks->d.frac_urg_bw_nom
+			< hubbub2->watermarks.d.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) {
+		hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
+	} else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub32_program_stutter_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns =
+				watermarks->a.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns =
+				watermarks->b.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns =
+				watermarks->c.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns =
+				watermarks->d.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+
+static bool hubbub32_program_pstate_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* Section for UCLK_PSTATE_CHANGE_WATERMARKS */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.pstate_change_ns =
+				watermarks->a.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.pstate_change_ns =
+				watermarks->b.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.pstate_change_ns =
+				watermarks->c.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.pstate_change_ns =
+				watermarks->d.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* Section for FCLK_PSTATE_CHANGE_WATERMARKS */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->a.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->b.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->c.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.fclk_pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns =
+				watermarks->d.cstate_pstate.fclk_pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.fclk_pstate_change_ns,
+				refclk_mhz, 0xffff);
+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.fclk_pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.fclk_pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.fclk_pstate_change_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+
+static bool hubbub32_program_usr_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.usr_retraining_ns
+			> hubbub2->watermarks.a.usr_retraining_ns) {
+		hubbub2->watermarks.a.usr_retraining_ns = watermarks->a.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->a.usr_retraining_ns
+			< hubbub2->watermarks.a.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.usr_retraining_ns
+			> hubbub2->watermarks.b.usr_retraining_ns) {
+		hubbub2->watermarks.b.usr_retraining_ns = watermarks->b.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->b.usr_retraining_ns
+			< hubbub2->watermarks.b.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.usr_retraining_ns
+			> hubbub2->watermarks.c.usr_retraining_ns) {
+		hubbub2->watermarks.c.usr_retraining_ns =
+				watermarks->c.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->c.usr_retraining_ns
+			< hubbub2->watermarks.c.usr_retraining_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.usr_retraining_ns
+			> hubbub2->watermarks.d.usr_retraining_ns) {
+		hubbub2->watermarks.d.usr_retraining_ns =
+				watermarks->d.usr_retraining_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.usr_retraining_ns,
+				refclk_mhz, 0x3fff);
+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0,
+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.usr_retraining_ns, prog_wm_value);
+	} else if (watermarks->d.usr_retraining_ns
+			< hubbub2->watermarks.d.usr_retraining_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	/*
+	 * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE = 1 means enabling forcing value
+	 * DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE = 1 or 0,  means value to be forced when force enable
+	 */
+
+	REG_UPDATE_2(DCHUBBUB_ARB_USR_RETRAINING_CNTL,
+			DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, allow,
+			DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, allow);
+}
+
+static bool hubbub32_program_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	bool wm_pending = false;
+
+	if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub32_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	/*
+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
+	 * If the memory controller is fully utilized and the DCHub requestors are
+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
+	 * from being committed and sent to the fabric.
+	 * The utilization of the memory controller is approximated by ensuring that
+	 * the number of outstanding requests is greater than a threshold specified
+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
+	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
+	 *
+	 * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF)
+	 * to turn off it for now.
+	 */
+	/*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
+
+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+
+	hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
+
+	return wm_pending;
+}
+
+/* Copy values from WM set A to all other sets */
+void hubbub32_init_watermarks(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t reg;
+
+	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
+}
+
+void hubbub32_wm_read_state(struct hubbub *hubbub,
+		struct dcn_hubbub_wm *wm)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	struct dcn_hubbub_wm_set *s;
+
+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
+
+	s = &wm->sets[0];
+	s->wm_set = 0;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
+			 DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
+			 DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change);
+
+	s = &wm->sets[1];
+	s->wm_set = 1;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change);
+
+	s = &wm->sets[2];
+	s->wm_set = 2;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change);
+
+	s = &wm->sets[3];
+	s->wm_set = 3;
+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
+
+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
+
+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+
+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
+
+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change);
+}
+
+void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
+	uint32_t prog_wm_value = convert_and_clamp(hubbub2->watermarks.a.urgent_ns,
+			refclk_mhz, 0x3fff);
+
+	REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+}
+
+static const struct hubbub_funcs hubbub32_funcs = {
+	.update_dchub = hubbub2_update_dchub,
+	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
+	.init_vm_ctx = hubbub2_init_vm_ctx,
+	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+	.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
+	.wm_read_state = hubbub32_wm_read_state,
+	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+	.program_watermarks = hubbub32_program_watermarks,
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+	.force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes,
+	.force_pstate_change_control = hubbub3_force_pstate_change_control,
+	.init_watermarks = hubbub32_init_watermarks,
+	.program_det_size = dcn32_program_det_size,
+	.program_compbuf_size = dcn32_program_compbuf_size,
+	.init_crb = dcn32_init_crb,
+	.hubbub_read_state = hubbub2_read_state,
+	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
+};
+
+void hubbub32_construct(struct dcn20_hubbub *hubbub2,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb)
+{
+	hubbub2->base.ctx = ctx;
+	hubbub2->base.funcs = &hubbub32_funcs;
+	hubbub2->regs = hubbub_regs;
+	hubbub2->shifts = hubbub_shift;
+	hubbub2->masks = hubbub_mask;
+
+	hubbub2->debug_test_index_pstate = 0xB;
+	hubbub2->detile_buf_size = det_size_kb * 1024;
+	hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024;
+	hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN32_CRB_SEGMENT_SIZE_KB;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
new file mode 100644
index 000000000000..3bae6e558971
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBBUB_DCN32_H__
+#define __DC_HUBBUB_DCN32_H__
+
+#include "dcn21/dcn21_hubbub.h"
+
+#define HUBBUB_REG_LIST_DCN32(id)\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
+	SR(DCHUBBUB_ARB_SAT_LEVEL),\
+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DCHUBBUB_SOFT_RESET),\
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DCN_VM_FB_LOCATION_BASE),\
+	SR(DCN_VM_FB_LOCATION_TOP),\
+	SR(DCN_VM_FB_OFFSET),\
+	SR(DCN_VM_AGP_BOT),\
+	SR(DCN_VM_AGP_TOP),\
+	SR(DCN_VM_AGP_BASE),\
+	HUBBUB_SR_WATERMARK_REG_LIST(), \
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
+	SR(DCHUBBUB_DET0_CTRL),\
+	SR(DCHUBBUB_DET1_CTRL),\
+	SR(DCHUBBUB_DET2_CTRL),\
+	SR(DCHUBBUB_DET3_CTRL),\
+	SR(DCHUBBUB_COMPBUF_CTRL),\
+	SR(COMPBUF_RESERVED_SPACE),\
+	SR(DCHUBBUB_DEBUG_CTRL_0),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\
+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\
+	SR(DCN_VM_FAULT_ADDR_MSB),\
+	SR(DCN_VM_FAULT_ADDR_LSB),\
+	SR(DCN_VM_FAULT_CNTL),\
+	SR(DCN_VM_FAULT_STATUS)
+
+#define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
+	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)
+
+
+void hubbub32_construct(struct dcn20_hubbub *hubbub2,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
new file mode 100644
index 000000000000..0a7d64306481
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
+#include "dcn32_hubp.h"
+
+#define REG(reg)\
+	hubp2->hubp_regs->reg
+
+#define CTX \
+	hubp2->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
+
+void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+	REG_UPDATE_2(UCLK_PSTATE_FORCE,
+			DATA_UCLK_PSTATE_FORCE_EN, pstate_disallow,
+			DATA_UCLK_PSTATE_FORCE_VALUE, 0);
+}
+
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	// Also cache cursor in MALL if using MALL for SS
+	REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
+			USE_MALL_FOR_CURSOR, mall_sel == 2 ? 1 : 0);
+}
+
+void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+	REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);
+
+	/* Programming guide suggests CURSOR_REQ_MODE = 1 for SubVP:
+	 * For Pstate change using the MALL with sub-viewport buffering,
+	 * the cursor does not use the MALL (USE_MALL_FOR_CURSOR is ignored)
+	 * and sub-viewport positioning by Display FW has to avoid the cursor
+	 * requests to DRAM (set CURSOR_REQ_MODE = 1 to minimize this exclusion).
+	 *
+	 * CURSOR_REQ_MODE = 1 begins fetching cursor data at the beginning of display prefetch.
+	 * Setting this should allow the sub-viewport position to always avoid the cursor because
+	 * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank).
+	 */
+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
+}
+
+void hubp32_phantom_hubp_post_enable(struct hubp *hubp)
+{
+	uint32_t reg_val;
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1);
+	reg_val = REG_READ(DCHUBP_CNTL);
+	if (reg_val) {
+		/* init sequence workaround: in case HUBP is
+		 * power gated, this wait would timeout.
+		 *
+		 * we just wrote reg_val to non-0, if it stay 0
+		 * it means HUBP is gated
+		 */
+		REG_WAIT(DCHUBP_CNTL,
+				HUBP_NO_OUTSTANDING_REQ, 1,
+				1, 200);
+	}
+}
+
+static struct hubp_funcs dcn32_hubp_funcs = {
+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+	.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
+	.hubp_program_surface_config = hubp3_program_surface_config,
+	.hubp_is_flip_pending = hubp2_is_flip_pending,
+	.hubp_setup = hubp3_setup,
+	.hubp_setup_interdependent = hubp2_setup_interdependent,
+	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
+	.set_blank = hubp2_set_blank,
+	.dcc_control = hubp3_dcc_control,
+	.mem_program_viewport = min_set_viewport,
+	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+	.set_cursor_position	= hubp2_cursor_set_position,
+	.hubp_clk_cntl = hubp2_clk_cntl,
+	.hubp_vtg_sel = hubp2_vtg_sel,
+	.dmdata_set_attributes = hubp3_dmdata_set_attributes,
+	.dmdata_load = hubp2_dmdata_load,
+	.dmdata_status_done = hubp2_dmdata_status_done,
+	.hubp_read_state = hubp3_read_state,
+	.hubp_clear_underflow = hubp2_clear_underflow,
+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+	.hubp_init = hubp3_init,
+	.set_unbounded_requesting = hubp31_set_unbounded_requesting,
+	.hubp_soft_reset = hubp31_soft_reset,
+	.hubp_in_blank = hubp1_in_blank,
+	.hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow,
+	.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
+	.hubp_update_mall_sel = hubp32_update_mall_sel,
+	.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
+	.hubp_set_flip_int = hubp1_set_flip_int
+};
+
+bool hubp32_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask)
+{
+	hubp2->base.funcs = &dcn32_hubp_funcs;
+	hubp2->base.ctx = ctx;
+	hubp2->hubp_regs = hubp_regs;
+	hubp2->hubp_shift = hubp_shift;
+	hubp2->hubp_mask = hubp_mask;
+	hubp2->base.inst = inst;
+	hubp2->base.opp_id = OPP_ID_INVALID;
+	hubp2->base.mpcc_id = 0xf;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
new file mode 100644
index 000000000000..00b4211389c2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBP_DCN32_H__
+#define __DC_HUBP_DCN32_H__
+
+#include "dcn20/dcn20_hubp.h"
+#include "dcn21/dcn21_hubp.h"
+#include "dcn30/dcn30_hubp.h"
+#include "dcn31/dcn31_hubp.h"
+
+#define HUBP_REG_LIST_DCN32(id)\
+	HUBP_REG_LIST_DCN30(id),\
+	SRI(DCHUBP_MALL_CONFIG, HUBP, id),\
+	SRI(DCHUBP_VMPG_CONFIG, HUBP, id),\
+	SRI(UCLK_PSTATE_FORCE, HUBPREQ, id)
+
+#define HUBP_MASK_SH_LIST_DCN32(mask_sh)\
+	HUBP_MASK_SH_LIST_DCN31(mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh)
+
+void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
+
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel);
+
+void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
+
+void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
+
+bool hubp32_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask);
+
+#endif /* __DC_HUBP_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
new file mode 100644
index 000000000000..a10ec5919194
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -0,0 +1,958 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dccg.h"
+#include "dce/dce_hwseq.h"
+#include "dcn30/dcn30_cm_common.h"
+#include "reg_helper.h"
+#include "abm.h"
+#include "hubp.h"
+#include "dchubbub.h"
+#include "timing_generator.h"
+#include "opp.h"
+#include "ipp.h"
+#include "mpc.h"
+#include "mcif_wb.h"
+#include "dc_dmub_srv.h"
+#include "link_hwss.h"
+#include "dpcd_defs.h"
+#include "dcn32_hwseq.h"
+#include "clk_mgr.h"
+#include "dsc.h"
+#include "dcn20/dcn20_optc.h"
+#include "dc_link_dp.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+#define DC_LOGGER \
+		dc->ctx->logger
+
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+void dcn32_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
+
+	if (hws->ctx->dc->debug.disable_dsc_power_gate)
+		return;
+
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
+	switch (dsc_inst) {
+	case 0: /* DSC0 */
+		REG_UPDATE(DOMAIN16_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN16_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DSC1 */
+		REG_UPDATE(DOMAIN17_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN17_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DSC2 */
+		REG_UPDATE(DOMAIN18_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN18_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 3: /* DSC3 */
+		REG_UPDATE(DOMAIN19_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN19_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+}
+
+
+void dcn32_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable)
+{
+	bool force_on = true; /* disable power gating */
+
+	if (enable)
+		force_on = false;
+
+	/* DCHUBP0/1/2/3 */
+	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DCS0/1/2/3 */
+	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+}
+
+void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
+		return;
+
+	if (REG(DOMAIN0_PG_CONFIG) == 0)
+		return;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 1:
+		REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 2:
+		REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 3:
+		REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
+{
+	int i;
+
+    /* First, check no-memory-request case */
+	for (i = 0; i < dc->current_state->stream_count; i++) {
+		if (dc->current_state->stream_status[i].plane_count)
+			/* Fail eligibility on a visible stream */
+			break;
+	}
+
+	if (i == dc->current_state->stream_count)
+		return true;
+
+	return false;
+}
+
+/* This function takes in the start address and surface size to be cached in CAB
+ * and calculates the total number of cache lines required to store the surface.
+ * The number of cache lines used for each surface is calculated independently of
+ * one another. For example, if there is a primary surface(1), meta surface(2), and
+ * cursor(3), this function should be called 3 times to calculate the number of cache
+ * lines used for each of those surfaces.
+ */
+static uint32_t dcn32_cache_lines_for_surface(struct dc *dc, uint32_t surface_size, uint64_t start_address)
+{
+	uint32_t lines_used = 1;
+	uint32_t num_cached_bytes = 0;
+	uint32_t remaining_size = 0;
+	uint32_t cache_line_size = dc->caps.cache_line_size;
+
+	/* 1. Calculate surface size minus the number of bytes stored
+	 * in the first cache line (all bytes in first cache line might
+	 * not be fully used).
+	 */
+	num_cached_bytes = cache_line_size - (start_address % cache_line_size);
+	remaining_size = surface_size - num_cached_bytes;
+
+	/* 2. Calculate number of cache lines that will be fully used with
+	 * the remaining number of bytes to be stored.
+	 */
+	lines_used += (remaining_size / cache_line_size);
+
+	/* 3. Check if we need an extra line due to the remaining size not being
+	 * a multiple of CACHE_LINE_SIZE.
+	 */
+	if (remaining_size % cache_line_size > 0)
+		lines_used++;
+
+	return lines_used;
+}
+
+/* This function loops through every surface that needs to be cached in CAB for SS,
+ * and calculates the total number of ways required to store all surfaces (primary,
+ * meta, cursor).
+ */
+static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
+{
+	uint8_t i, j;
+	struct dc_stream_state *stream = NULL;
+	struct dc_plane_state *plane = NULL;
+	uint32_t surface_size = 0;
+	uint32_t cursor_size = 0;
+	uint32_t cache_lines_used = 0;
+	uint32_t total_lines = 0;
+	uint32_t lines_per_way = 0;
+	uint32_t num_ways = 0;
+
+	for (i = 0; i < ctx->stream_count; i++) {
+		stream = ctx->streams[i];
+
+		// Don't include PSR surface in the total surface size for CAB allocation
+		if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
+			continue;
+
+		if (ctx->stream_status[i].plane_count == 0)
+			continue;
+
+		// For each stream, loop through each plane to calculate the number of cache
+		// lines required to store the surface in CAB
+		for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
+			plane = ctx->stream_status[i].plane_states[j];
+
+			// Calculate total surface size
+			surface_size = plane->plane_size.surface_pitch *
+					plane->plane_size.surface_size.height *
+					(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
+
+			// Convert surface size + starting address to number of cache lines required
+			// (alignment accounted for)
+			cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+					plane->address.grph.addr.quad_part);
+
+			if (plane->address.grph.meta_addr.quad_part) {
+				// Meta surface
+				cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+						plane->address.grph.meta_addr.quad_part);
+			}
+		}
+
+		// Include cursor size for CAB allocation
+		if (stream->cursor_position.enable && plane->address.grph.cursor_cache_addr.quad_part) {
+			cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
+			switch (stream->cursor_attributes.color_format) {
+			case CURSOR_MODE_MONO:
+				cursor_size /= 2;
+				break;
+			case CURSOR_MODE_COLOR_1BIT_AND:
+			case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+			case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+				cursor_size *= 4;
+				break;
+
+			case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+			case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+				cursor_size *= 8;
+				break;
+			}
+			cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size,
+					plane->address.grph.cursor_cache_addr.quad_part);
+		}
+	}
+
+	// Convert number of cache lines required to number of ways
+	total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
+	lines_per_way = total_lines / dc->caps.cache_num_ways;
+	num_ways = cache_lines_used / lines_per_way;
+
+	if (cache_lines_used % lines_per_way > 0)
+		num_ways++;
+
+	return num_ways;
+}
+
+bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
+{
+	union dmub_rb_cmd cmd;
+	uint8_t ways;
+
+	if (!dc->ctx->dmub_srv)
+		return false;
+
+	if (enable) {
+		if (dc->current_state) {
+
+			/* 1. Check no memory request case for CAB.
+			 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
+			 */
+			if (dcn32_check_no_memory_request_for_cab(dc)) {
+				/* Enable no-memory-requests case */
+				memset(&cmd, 0, sizeof(cmd));
+				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+				cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
+				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+
+				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+				return true;
+			}
+
+			/* 2. Check if all surfaces can fit in CAB.
+			 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
+			 * and configure HUBP's to fetch from MALL
+			 */
+			ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
+			if (ways <= dc->caps.cache_num_ways) {
+				memset(&cmd, 0, sizeof(cmd));
+				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
+				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+				cmd.cab.cab_alloc_ways = ways;
+
+				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+				return true;
+			}
+
+		}
+		return false;
+	}
+
+	/* Disable CAB */
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+	cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
+	cmd.cab.header.payload_bytes =
+			sizeof(cmd.cab) - sizeof(cmd.cab.header);
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+
+	return false;
+}
+
+/* Send DMCUB message with SubVP pipe info
+ * - For each pipe in context, populate payload with required SubVP information
+ *   if the pipe is using SubVP for MCLK switch
+ * - This function must be called while the DMUB HW lock is acquired by driver
+ */
+void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
+{
+/*
+	int i;
+	bool enable_subvp = false;
+
+	if (!dc->ctx || !dc->ctx->dmub_srv)
+		return;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
+				pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
+			// There is at least 1 SubVP pipe, so enable SubVP
+			enable_subvp = true;
+			break;
+		}
+	}
+	dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
+*/
+}
+
+static bool dcn32_set_mpc_shaper_3dlut(
+	struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
+{
+	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+	bool result = false;
+
+	const struct pwl_params *shaper_lut = NULL;
+	//get the shaper lut params
+	if (stream->func_shaper) {
+		if (stream->func_shaper->type == TF_TYPE_HWPWL)
+			shaper_lut = &stream->func_shaper->pwl;
+		else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
+			cm_helper_translate_curve_to_hw_format(
+					stream->func_shaper,
+					&dpp_base->shaper_params, true);
+			shaper_lut = &dpp_base->shaper_params;
+		}
+	}
+
+	if (stream->lut3d_func &&
+		stream->lut3d_func->state.bits.initialized == 1) {
+
+		result = mpc->funcs->program_3dlut(mpc,
+								&stream->lut3d_func->lut_3d,
+								mpcc_id);
+
+		result = mpc->funcs->program_shaper(mpc,
+								shaper_lut,
+								mpcc_id);
+	}
+
+	return result;
+}
+bool dcn32_set_output_transfer_func(struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				const struct dc_stream_state *stream)
+{
+	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+	struct pwl_params *params = NULL;
+	bool ret = false;
+
+	/* program OGAM or 3DLUT only for the top pipe*/
+	if (pipe_ctx->top_pipe == NULL) {
+		/*program shaper and 3dlut in MPC*/
+		ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
+		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
+			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
+				params = &stream->out_transfer_func->pwl;
+			else if (pipe_ctx->stream->out_transfer_func->type ==
+					TF_TYPE_DISTRIBUTED_POINTS &&
+					cm3_helper_translate_curve_to_hw_format(
+					stream->out_transfer_func,
+					&mpc->blender_params, false))
+				params = &mpc->blender_params;
+		 /* there are no ROM LUTs in OUTGAM */
+		if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
+			BREAK_TO_DEBUGGER();
+		}
+	}
+
+	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
+	return ret;
+}
+
+/* Program P-State force value according to if pipe is using SubVP or not:
+ * 1. Reset P-State force on all pipes first
+ * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
+ */
+void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	int num_subvp = 0;
+	/* Unforce p-state for each pipe
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
+			hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
+		if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			num_subvp++;
+	}
+
+	if (num_subvp == 0)
+		return;
+
+	/* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			struct hubp *hubp = pipe->plane_res.hubp;
+
+			if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
+				hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
+		}
+	}
+}
+
+/* Update MALL_SEL register based on if pipe / plane
+ * is a phantom pipe, main pipe, and if using MALL
+ * for SS.
+ */
+void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
+			if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+					hubp->funcs->hubp_update_mall_sel(hubp, 1);
+			} else {
+				hubp->funcs->hubp_update_mall_sel(hubp,
+					num_ways <= dc->caps.cache_num_ways &&
+					pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2 : 0);
+			}
+		}
+	}
+}
+
+/* Program the sub-viewport pipe configuration after the main / phantom pipes
+ * have been programmed in hardware.
+ * 1. Update force P-State for all the main pipes (disallow P-state)
+ * 2. Update MALL_SEL register
+ * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
+ */
+void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	struct dce_hwseq *hws = dc->hwseq;
+	// Update force P-state for each pipe accordingly
+	if (hws && hws->funcs.subvp_update_force_pstate)
+		hws->funcs.subvp_update_force_pstate(dc, context);
+
+	// Update MALL_SEL register for each pipe
+	if (hws && hws->funcs.update_mall_sel)
+		hws->funcs.update_mall_sel(dc, context);
+
+	// Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct hubp *hubp = pipe->plane_res.hubp;
+
+		if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
+			/* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
+			 *      - need to investigate single pipe MPO + SubVP case to
+			 *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
+			 *        when it should be 0 for MPO
+			 */
+			if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+				hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
+			}
+		}
+	}
+}
+
+void dcn32_init_hw(struct dc *dc)
+{
+	struct abm **abms = dc->res_pool->multiple_abms;
+	struct dce_hwseq *hws = dc->hwseq;
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+	struct resource_pool *res_pool = dc->res_pool;
+	int i;
+	int edp_num;
+	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
+
+	dc->debug.disable_idle_power_optimizations = true;
+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+
+	// Initialize the dccg
+	if (res_pool->dccg->funcs->dccg_init)
+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		hws->funcs.bios_golden_init(dc);
+		hws->funcs.disable_vga(dc->hwseq);
+	}
+
+	// Set default OPTC memory power states
+	if (dc->debug.enable_mem_low_power.bits.optc) {
+		// Shutdown when unassigned and light sleep in VBLANK
+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.vga) {
+		// Power down VGA memory
+		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+	}
+
+	if (dc->ctx->dc_bios->fw_info_valid) {
+		res_pool->ref_clocks.xtalin_clock_inKhz =
+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+		if (res_pool->dccg && res_pool->hubbub) {
+			(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+					&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+			(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+					res_pool->ref_clocks.dccg_ref_clock_inKhz,
+					&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+		} else {
+			// Not all ASICs have DCCG sw component
+			res_pool->ref_clocks.dccg_ref_clock_inKhz =
+					res_pool->ref_clocks.xtalin_clock_inKhz;
+			res_pool->ref_clocks.dchub_ref_clock_inKhz =
+					res_pool->ref_clocks.xtalin_clock_inKhz;
+		}
+	} else
+		ASSERT_CRITICAL(false);
+
+	for (i = 0; i < dc->link_count; i++) {
+		/* Power up AND update implementation according to the
+		 * required signal (which may be different from the
+		 * default signal on connector).
+		 */
+		struct dc_link *link = dc->links[i];
+
+		link->link_enc->funcs->hw_init(link->link_enc);
+
+		/* Check for enabled DIG to identify enabled display */
+		if (link->link_enc->funcs->is_dig_enabled &&
+			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
+			link->link_status.link_active = true;
+			if (link->link_enc->funcs->fec_is_active &&
+					link->link_enc->funcs->fec_is_active(link->link_enc))
+				link->fec_state = dc_link_fec_enabled;
+		}
+	}
+
+	/* Power gate DSCs */
+	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+		if (hws->funcs.dsc_pg_control != NULL)
+			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
+	/* we want to turn off all dp displays before doing detection */
+	dc_link_blank_all_dp_displays(dc);
+
+	/* If taking control over from VBIOS, we may want to optimize our first
+	 * mode set, so we need to skip powering down pipes until we know which
+	 * pipes we want to use.
+	 * Otherwise, if taking control is not possible, we need to power
+	 * everything down.
+	 */
+	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
+		hws->funcs.init_pipes(dc, dc->current_state);
+		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
+					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+	}
+
+	/* In headless boot cases, DIG may be turned
+	 * on which causes HW/SW discrepancies.
+	 * To avoid this, power down hardware on boot
+	 * if DIG is turned on and seamless boot not enabled
+	 */
+	if (!dc->config.seamless_boot_edp_requested) {
+		struct dc_link *edp_links[MAX_NUM_EDP];
+		struct dc_link *edp_link;
+
+		get_edp_links(dc, edp_links, &edp_num);
+		if (edp_num) {
+			for (i = 0; i < edp_num; i++) {
+				edp_link = edp_links[i];
+				if (edp_link->link_enc->funcs->is_dig_enabled &&
+						edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
+						dc->hwss.edp_backlight_control &&
+						dc->hwss.power_down &&
+						dc->hwss.edp_power_control) {
+					dc->hwss.edp_backlight_control(edp_link, false);
+					dc->hwss.power_down(dc);
+					dc->hwss.edp_power_control(edp_link, false);
+				}
+			}
+		} else {
+			for (i = 0; i < dc->link_count; i++) {
+				struct dc_link *link = dc->links[i];
+
+				if (link->link_enc->funcs->is_dig_enabled &&
+						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
+						dc->hwss.power_down) {
+					dc->hwss.power_down(dc);
+					break;
+				}
+
+			}
+		}
+	}
+
+	for (i = 0; i < res_pool->audio_count; i++) {
+		struct audio *audio = res_pool->audios[i];
+
+		audio->funcs->hw_init(audio);
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		struct dc_link *link = dc->links[i];
+
+		if (link->panel_cntl)
+			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (abms[i] != NULL && abms[i]->funcs != NULL)
+			abms[i]->funcs->abm_init(abms[i], backlight);
+	}
+
+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+	if (!dc->debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+	}
+	if (hws->funcs.enable_power_gating_plane)
+		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
+		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
+
+	if (dc->clk_mgr->funcs->notify_wm_ranges)
+		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+
+	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, false, false);
+
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+
+	// Get DMCUB capabilities
+    if (dc->ctx->dmub_srv) {
+	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
+    }
+}
+
+static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
+		int opp_cnt)
+{
+	bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
+	int flow_ctrl_cnt;
+
+	if (opp_cnt >= 2)
+		hblank_halved = true;
+
+	flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
+			stream->timing.h_border_left -
+			stream->timing.h_border_right;
+
+	if (hblank_halved)
+		flow_ctrl_cnt /= 2;
+
+	/* ODM combine 4:1 case */
+	if (opp_cnt == 4)
+		flow_ctrl_cnt /= 2;
+
+	return flow_ctrl_cnt;
+}
+
+static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+{
+	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+	struct dc_stream_state *stream = pipe_ctx->stream;
+	struct pipe_ctx *odm_pipe;
+	int opp_cnt = 1;
+
+	ASSERT(dsc);
+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+		opp_cnt++;
+
+	if (enable) {
+		struct dsc_config dsc_cfg;
+		struct dsc_optc_config dsc_optc_cfg;
+		enum optc_dsc_mode optc_dsc_mode;
+
+		/* Enable DSC hw block */
+		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
+		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
+		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
+		dsc_cfg.color_depth = stream->timing.display_color_depth;
+		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
+		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
+		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
+
+		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
+		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
+
+			ASSERT(odm_dsc);
+			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
+			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
+		}
+		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
+		dsc_cfg.pic_width *= opp_cnt;
+
+		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+
+		/* Enable DSC in OPTC */
+		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
+							optc_dsc_mode,
+							dsc_optc_cfg.bytes_per_pixel,
+							dsc_optc_cfg.slice_width);
+	} else {
+		/* disable DSC in OPTC */
+		pipe_ctx->stream_res.tg->funcs->set_dsc_config(
+				pipe_ctx->stream_res.tg,
+				OPTC_DSC_DISABLED, 0, 0);
+
+		/* disable DSC block */
+		dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+			ASSERT(odm_pipe->stream_res.dsc);
+			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
+		}
+	}
+}
+
+/*
+* Given any pipe_ctx, return the total ODM combine factor, and optionally return
+* the OPPids which are used
+* */
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+{
+	unsigned int opp_count = 1;
+	struct pipe_ctx *odm_pipe;
+
+	/* First get to the top pipe */
+	for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
+		;
+
+	/* First pipe is always used */
+	if (opp_instances)
+		opp_instances[0] = odm_pipe->stream_res.opp->inst;
+
+	/* Find and count odm pipes, if any */
+	for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+		if (opp_instances)
+			opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
+		opp_count++;
+	}
+
+	return opp_count;
+}
+
+void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+{
+	struct pipe_ctx *odm_pipe;
+	int opp_cnt = 0;
+	int opp_inst[MAX_PIPES] = {0};
+	bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
+	struct mpc_dwb_flow_control flow_control;
+	struct mpc *mpc = dc->res_pool->mpc;
+	int i;
+
+	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
+
+	if (opp_cnt > 1)
+		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+				pipe_ctx->stream_res.tg,
+				opp_inst, opp_cnt,
+				&pipe_ctx->stream->timing);
+	else
+		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
+	flow_control.flow_ctrl_mode = 0;
+	flow_control.flow_ctrl_cnt0 = 0x80;
+	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
+	if (mpc->funcs->set_out_rate_control) {
+		for (i = 0; i < opp_cnt; ++i) {
+			mpc->funcs->set_out_rate_control(
+					mpc, opp_inst[i],
+					true,
+					rate_control_2x_pclk,
+					&flow_control);
+		}
+	}
+
+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+				odm_pipe->stream_res.opp,
+				true);
+	}
+
+	// Don't program pixel clock after link is already enabled
+/*	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
+			pipe_ctx->clock_source,
+			&pipe_ctx->stream_res.pix_clk_params,
+			&pipe_ctx->pll_settings)) {
+		BREAK_TO_DEBUGGER();
+	}*/
+
+	if (pipe_ctx->stream_res.dsc)
+		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+}
+
+unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+{
+	struct dc_stream_state *stream = pipe_ctx->stream;
+	unsigned int odm_combine_factor = 0;
+
+	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+
+	if (is_dp_128b_132b_signal(pipe_ctx)) {
+		*k2_div = PIXEL_RATE_DIV_BY_1;
+	} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
+		*k1_div = PIXEL_RATE_DIV_BY_1;
+		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		else
+			*k2_div = PIXEL_RATE_DIV_BY_4;
+	} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+		if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+			*k1_div = PIXEL_RATE_DIV_BY_1;
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		} else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+			*k1_div = PIXEL_RATE_DIV_BY_2;
+			*k2_div = PIXEL_RATE_DIV_BY_2;
+		} else {
+			if (odm_combine_factor == 1)
+				*k2_div = PIXEL_RATE_DIV_BY_4;
+			else if (odm_combine_factor == 2)
+				*k2_div = PIXEL_RATE_DIV_BY_2;
+		}
+	}
+
+	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
+		ASSERT(false);
+
+	return odm_combine_factor;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
new file mode 100644
index 000000000000..2a5bdcf58bc6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -0,0 +1,66 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN32_H__
+#define __DC_HWSS_DCN32_H__
+
+#include "hw_sequencer_private.h"
+
+struct dc;
+
+void dcn32_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on);
+
+void dcn32_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable);
+
+void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+
+bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
+
+void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
+
+void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
+
+bool dcn32_set_output_transfer_func(struct dc *dc,
+				struct pipe_ctx *pipe_ctx,
+				const struct dc_stream_state *stream);
+
+void dcn32_init_hw(struct dc *dc);
+
+void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
+
+void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
+
+void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
+
+void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+
+unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
+
+#endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
new file mode 100644
index 000000000000..7f492734f881
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn31/dcn31_hwseq.h"
+#include "dcn32_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn32_funcs = {
+	.program_gamut_remap = dcn10_program_gamut_remap,
+	.init_hw = dcn32_init_hw,
+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
+	.update_pending_status = dcn10_update_pending_status,
+	.program_output_csc = dcn20_program_output_csc,
+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+	.update_info_frame = dcn31_update_info_frame,
+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+	.enable_stream = dcn20_enable_stream,
+	.disable_stream = dce110_disable_stream,
+	.unblank_stream = dcn20_unblank_stream,
+	.blank_stream = dce110_blank_stream,
+	.enable_audio_stream = dce110_enable_audio_stream,
+	.disable_audio_stream = dce110_disable_audio_stream,
+	.disable_plane = dcn20_disable_plane,
+	.pipe_control_lock = dcn20_pipe_control_lock,
+	.interdependent_update_lock = dcn10_lock_all_pipes,
+	.cursor_lock = dcn10_cursor_lock,
+	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.optimize_bandwidth = dcn20_optimize_bandwidth,
+	.update_bandwidth = dcn20_update_bandwidth,
+	.set_drr = dcn10_set_drr,
+	.get_position = dcn10_get_position,
+	.set_static_screen_control = dcn10_set_static_screen_control,
+	.setup_stereo = dcn10_setup_stereo,
+	.set_avmute = dcn30_set_avmute,
+	.log_hw_state = dcn10_log_hw_state,
+	.get_hw_state = dcn10_get_hw_state,
+	.clear_status_bits = dcn10_clear_status_bits,
+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.edp_power_control = dce110_edp_power_control,
+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
+	.set_cursor_position = dcn10_set_cursor_position,
+	.set_cursor_attribute = dcn10_set_cursor_attribute,
+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+	.set_clock = dcn10_set_clock,
+	.get_clock = dcn10_get_clock,
+	.program_triplebuffer = dcn20_program_triple_buffer,
+	.enable_writeback = dcn30_enable_writeback,
+	.disable_writeback = dcn30_disable_writeback,
+	.update_writeback = dcn30_update_writeback,
+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
+	.dmdata_status_done = dcn20_dmdata_status_done,
+	.program_dmdata_engine = dcn30_program_dmdata_engine,
+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
+	.init_sys_ctx = dcn20_init_sys_ctx,
+	.init_vm_ctx = dcn20_init_vm_ctx,
+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
+	.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
+	.does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
+	.set_backlight_level = dcn21_set_backlight_level,
+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.hardware_release = dcn30_hardware_release,
+	.set_pipe = dcn21_set_pipe,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.commit_subvp_config = dcn32_commit_subvp_config,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
+};
+
+static const struct hwseq_private_funcs dcn32_private_funcs = {
+	.init_pipes = dcn10_init_pipes,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+	.update_mpcc = dcn20_update_mpcc,
+	.set_input_transfer_func = dcn30_set_input_transfer_func,
+	.set_output_transfer_func = dcn32_set_output_transfer_func,
+	.power_down = dce110_power_down,
+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+	.blank_pixel_data = dcn20_blank_pixel_data,
+	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+	.enable_stream_timing = dcn20_enable_stream_timing,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.disable_stream_gating = dcn20_disable_stream_gating,
+	.enable_stream_gating = dcn20_enable_stream_gating,
+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur,
+	.init_blank = dcn20_init_blank,
+	.disable_vga = dcn20_disable_vga,
+	.bios_golden_init = dcn10_bios_golden_init,
+	.plane_atomic_disable = dcn20_plane_atomic_disable,
+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+	.enable_power_gating_plane = dcn32_enable_power_gating_plane,
+	.hubp_pg_control = dcn32_hubp_pg_control,
+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+	.update_odm = dcn32_update_odm,
+	.dsc_pg_control = dcn32_dsc_pg_control,
+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+	.dccg_init = dcn20_dccg_init,
+	.set_blend_lut = dcn30_set_blend_lut,
+	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+	.program_mall_pipe_config = dcn32_program_mall_pipe_config,
+	.subvp_update_force_pstate = dcn32_subvp_update_force_pstate,
+	.update_mall_sel = dcn32_update_mall_sel,
+	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
+};
+
+void dcn32_hw_sequencer_init_functions(struct dc *dc)
+{
+	dc->hwss = dcn32_funcs;
+	dc->hwseq->funcs = dcn32_private_funcs;
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		dc->hwss.init_hw = dcn20_fpga_init_hw;
+		dc->hwseq->funcs.init_pipes = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h
new file mode 100644
index 000000000000..89a591eb2c23
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN32_INIT_H__
+#define __DC_DCN32_INIT_H__
+
+struct dc;
+
+void dcn32_hw_sequencer_init_functions(struct dc *dc);
+
+#endif /* __DC_DCN32_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
new file mode 100644
index 000000000000..adf93cc8359c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "mcif_wb.h"
+#include "dcn32_mmhubbub.h"
+
+
+#define REG(reg)\
+	mcif_wb30->mcif_wb_regs->reg
+
+#define CTX \
+	mcif_wb30->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
+
+#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
+#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+
+/* wbif programming guide:
+ * 1. set up wbif parameter:
+ *    unsigned long long   luma_address[4];       //4 frame buffer
+ *    unsigned long long   chroma_address[4];
+ *    unsigned int	   luma_pitch;
+ *    unsigned int	   chroma_pitch;
+ *    unsigned int         warmup_pitch=0x10;     //256B align, the page size is 4KB when it is 0x10
+ *    unsigned int	   slice_lines;           //slice size
+ *    unsigned int         time_per_pixel;        // time per pixel, in ns
+ *    unsigned int         arbitration_slice;     // 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes
+ *    unsigned int         max_scaled_time;       // used for QOS generation
+ *    unsigned int         swlock=0x0;
+ *    unsigned int         cli_watermark[4];      //4 group urgent watermark
+ *    unsigned int         pstate_watermark[4];   //4 group pstate watermark
+ *    unsigned int         sw_int_en;             // Software interrupt enable, frame end and overflow
+ *    unsigned int         sw_slice_int_en;       // slice end interrupt enable
+ *    unsigned int         sw_overrun_int_en;     // overrun error interrupt enable
+ *    unsigned int         vce_int_en;            // VCE interrupt enable, frame end and overflow
+ *    unsigned int         vce_slice_int_en;      // VCE slice end interrupt enable, frame end and overflow
+ *
+ * 2. configure wbif register
+ *    a. call mmhubbub_config_wbif()
+ *
+ * 3. Enable wbif
+ *    call set_wbif_bufmgr_enable();
+ *
+ * 4. wbif_dump_status(), option, for debug purpose
+ *    the bufmgr status can show the progress of write back, can be used for debug purpose
+ */
+
+static void mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb,
+		struct mcif_warmup_params *params)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+	union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5};
+
+	/* Set base address and region size for warmup */
+	REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);
+	REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part);
+	REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);
+//	REG_SET(MMHUBBUB_WARMUP_P_VMID, 0, MMHUBBUB_WARMUP_P_VMID, params->p_vmid);
+
+	/* Set address increment and enable warmup */
+	REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true,
+			MMHUBBUB_WARMUP_SW_INT_EN, true,
+			MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5);
+
+	/* Wait for an interrupt to signal warmup is completed */
+	REG_WAIT(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, 1, 20, 100);
+
+	/* Acknowledge interrupt */
+	REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1);
+
+	/* Disable warmup */
+	REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
+}
+
+void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb,
+		struct mcif_buf_params *params,
+		unsigned int dest_height)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
+
+	/* buffer address for packing mode or Luma in planar mode */
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
+
+	/* buffer address for Chroma in planar mode (unused in packing mode) */
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
+
+	/* setup luma & chroma size
+	 * should be enough to contain a whole frame Luma data,
+	 * the programmed value is frame buffer size [27:8], 256-byte aligned
+	 */
+	REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
+	REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
+
+	/* enable address fence */
+	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
+
+	/* setup pitch, the programmed value is [15:8], 256B align */
+	REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
+			MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
+}
+
+static void mmhubbub32_config_mcif_arb(struct mcif_wb *mcif_wb,
+		struct mcif_arb_params *params)
+{
+	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
+
+	/* Programmed by the video driver based on the CRTC timing (for DWB) */
+	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
+
+	/* Programming dwb watermark */
+	/* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
+	/* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
+	/* urgent_watermarkA */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[0]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
+	/* urgent_watermarkB */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[1]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
+	/* urgent_watermarkC */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[2]);
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
+	/* urgent_watermarkD */
+	REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[3]);
+
+	/* Programming nb pstate watermark */
+	/* nbp_state_change_watermarkA */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
+	/* nbp_state_change_watermarkB */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
+	/* nbp_state_change_watermarkC */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
+	/* nbp_state_change_watermarkD */
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
+	REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
+			NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
+
+	/* dram_speed_change_duration - register removed */
+	//REG_UPDATE(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI,
+	//		MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, params->dram_speed_change_duration);
+
+	/* max_scaled_time */
+	REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
+
+	/* slice_lines */
+	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
+
+	/* Set arbitration unit for Luma/Chroma */
+	/* arb_unit=2 should be chosen for more efficiency */
+	/* Arbitration size, 0: 2048 bytes 1: 4096 bytes 2: 8192 Bytes */
+	REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE,  params->arbitration_slice);
+}
+
+const struct mcif_wb_funcs dcn32_mmhubbub_funcs = {
+	.warmup_mcif		= mmhubbub32_warmup_mcif,
+	.enable_mcif		= mmhubbub2_enable_mcif,
+	.disable_mcif		= mmhubbub2_disable_mcif,
+	.config_mcif_buf	= mmhubbub32_config_mcif_buf,
+	.config_mcif_arb	= mmhubbub32_config_mcif_arb,
+	.config_mcif_irq	= mmhubbub2_config_mcif_irq,
+	.dump_frame			= mcifwb2_dump_frame,
+};
+
+void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30,
+		struct dc_context *ctx,
+		const struct dcn30_mmhubbub_registers *mcif_wb_regs,
+		const struct dcn30_mmhubbub_shift *mcif_wb_shift,
+		const struct dcn30_mmhubbub_mask *mcif_wb_mask,
+		int inst)
+{
+	mcif_wb30->base.ctx = ctx;
+
+	mcif_wb30->base.inst = inst;
+	mcif_wb30->base.funcs = &dcn32_mmhubbub_funcs;
+
+	mcif_wb30->mcif_wb_regs = mcif_wb_regs;
+	mcif_wb30->mcif_wb_shift = mcif_wb_shift;
+	mcif_wb30->mcif_wb_mask = mcif_wb_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
new file mode 100644
index 000000000000..22355051f5f7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MCIF_WB_DCN32_H__
+#define __DC_MCIF_WB_DCN32_H__
+
+#include "dcn20/dcn20_mmhubbub.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+#define MCIF_WB_COMMON_REG_LIST_DCN32(inst) \
+	SRI2(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
+	SRI2(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
+	SRI2(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst),\
+	SRI2(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_WATERMARK, MMHUBBUB, inst),\
+	SRI2(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
+	SRI2(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
+	SRI2(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst),\
+	SRI2(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst)
+
+
+#define MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+	SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
+	SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
+	SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+	SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+	SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+	SF(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\
+	SF(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+	SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+	SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+	SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
+	SF(MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
+	SF(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
+	SF(MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
+	SF(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+	SF(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
+	SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
+	SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
+	SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\
+	SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\
+	SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\
+	SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh)
+
+
+void dcn32_mmhubbub_construct(struct dcn30_mmhubbub *mcif_wb30,
+	struct dc_context *ctx,
+	const struct dcn30_mmhubbub_registers *mcif_wb_regs,
+	const struct dcn30_mmhubbub_shift *mcif_wb_shift,
+	const struct dcn30_mmhubbub_mask *mcif_wb_mask,
+	int inst);
+
+#endif //__DC_MCIF_WB_DCN32_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
new file mode 100644
index 000000000000..a308f33d3d0d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_cm_common.h"
+#include "dcn30/dcn30_mpc.h"
+#include "basics/conversion.h"
+#include "dcn10/dcn10_cm_common.h"
+#include "dc.h"
+
+#define REG(reg)\
+	mpc30->mpc_regs->reg
+
+#define CTX \
+	mpc30->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
+
+
+static void mpc32_mpc_init(struct mpc *mpc)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int mpcc_id;
+
+	mpc1_mpc_init(mpc);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
+			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
+				REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
+			}
+		}
+		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
+			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
+				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
+		}
+	}
+}
+
+
+static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
+{
+	enum dc_lut_mode mode;
+	uint32_t state_mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id],
+			MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
+
+		switch (state_mode) {
+		case 0:
+			mode = LUT_BYPASS;
+			break;
+		case 1:
+			mode = LUT_RAM_A;
+			break;
+		case 2:
+			mode = LUT_RAM_B;
+			break;
+		default:
+			mode = LUT_BYPASS;
+			break;
+		}
+		return mode;
+}
+
+
+static void mpc32_configure_shaper_lut(
+		struct mpc *mpc,
+		bool is_ram_a,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
+			MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
+	REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
+			MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
+	REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
+}
+
+
+static void mpc32_program_shaper_luta_settings(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	const struct gamma_curve *curve;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
+
+	curve = params->arr_curve_points;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+
+static void mpc32_program_shaper_lutb_settings(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	const struct gamma_curve *curve;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
+
+	curve = params->arr_curve_points;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+	curve += 2;
+	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+
+static void mpc32_program_shaper_lut(
+		struct mpc *mpc,
+		const struct pwl_result_data *rgb,
+		uint32_t num,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue;
+	uint32_t  red_delta, green_delta, blue_delta;
+	uint32_t  red_value, green_value, blue_value;
+
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0 ; i < num; i++) {
+
+		red   = rgb[i].red_reg;
+		green = rgb[i].green_reg;
+		blue  = rgb[i].blue_reg;
+
+		red_delta   = rgb[i].delta_red_reg;
+		green_delta = rgb[i].delta_green_reg;
+		blue_delta  = rgb[i].delta_blue_reg;
+
+		red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
+		green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
+		blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
+
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
+		REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
+	}
+
+}
+
+
+static void mpc32_power_on_shaper_3dlut(
+		struct mpc *mpc,
+		uint32_t mpcc_id,
+		bool power_on)
+{
+	uint32_t power_status_shaper = 2;
+	uint32_t power_status_3dlut  = 2;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int max_retries = 10;
+
+	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
+	MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
+	/* wait for memory to fully power up */
+	if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+		REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+	}
+
+	/*read status is not mandatory, it is just for debugging*/
+	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
+	REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
+
+	if (power_status_shaper != 0 && power_on == true)
+		BREAK_TO_DEBUGGER();
+
+	if (power_status_3dlut != 0 && power_on == true)
+		BREAK_TO_DEBUGGER();
+}
+
+
+bool mpc32_program_shaper(
+		struct mpc *mpc,
+		const struct pwl_params *params,
+		uint32_t mpcc_id)
+{
+	enum dc_lut_mode current_mode;
+	enum dc_lut_mode next_mode;
+
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	if (params == NULL) {
+		REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
+		return false;
+	}
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
+
+	current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
+
+	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
+		next_mode = LUT_RAM_B;
+	else
+		next_mode = LUT_RAM_A;
+
+	mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id);
+
+	if (next_mode == LUT_RAM_A)
+		mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
+	else
+		mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
+
+	mpc32_program_shaper_lut(
+			mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
+
+	REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
+	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
+
+	return true;
+}
+
+
+static enum dc_lut_mode get3dlut_config(
+			struct mpc *mpc,
+			bool *is_17x17x17,
+			bool *is_12bits_color_channel,
+			int mpcc_id)
+{
+	uint32_t i_mode, i_enable_10bits, lut_size;
+	enum dc_lut_mode mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
+			MPCC_MCM_3DLUT_MODE_CURRENT,  &i_mode);
+
+	REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
+			MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
+
+	switch (i_mode) {
+	case 0:
+		mode = LUT_BYPASS;
+		break;
+	case 1:
+		mode = LUT_RAM_A;
+		break;
+	case 2:
+		mode = LUT_RAM_B;
+		break;
+	default:
+		mode = LUT_BYPASS;
+		break;
+	}
+	if (i_enable_10bits > 0)
+		*is_12bits_color_channel = false;
+	else
+		*is_12bits_color_channel = true;
+
+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
+
+	if (lut_size == 0)
+		*is_17x17x17 = true;
+	else
+		*is_17x17x17 = false;
+
+	return mode;
+}
+
+
+static void mpc32_select_3dlut_ram(
+		struct mpc *mpc,
+		enum dc_lut_mode mode,
+		bool is_color_channel_12bits,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
+		MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
+		MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
+}
+
+
+static void mpc32_select_3dlut_ram_mask(
+		struct mpc *mpc,
+		uint32_t ram_selection_mask,
+		uint32_t mpcc_id)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
+			ram_selection_mask);
+	REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
+}
+
+
+static void mpc32_set3dlut_ram12(
+		struct mpc *mpc,
+		const struct dc_rgb *lut,
+		uint32_t entries,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue, red1, green1, blue1;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0 ; i < entries; i += 2) {
+		red   = lut[i].red<<4;
+		green = lut[i].green<<4;
+		blue  = lut[i].blue<<4;
+		red1   = lut[i+1].red<<4;
+		green1 = lut[i+1].green<<4;
+		blue1  = lut[i+1].blue<<4;
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, red,
+				MPCC_MCM_3DLUT_DATA1, red1);
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, green,
+				MPCC_MCM_3DLUT_DATA1, green1);
+
+		REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
+				MPCC_MCM_3DLUT_DATA0, blue,
+				MPCC_MCM_3DLUT_DATA1, blue1);
+	}
+}
+
+
+static void mpc32_set3dlut_ram10(
+		struct mpc *mpc,
+		const struct dc_rgb *lut,
+		uint32_t entries,
+		uint32_t mpcc_id)
+{
+	uint32_t i, red, green, blue, value;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	for (i = 0; i < entries; i++) {
+		red   = lut[i].red;
+		green = lut[i].green;
+		blue  = lut[i].blue;
+		//should we shift red 22bit and green 12?
+		value = (red<<20) | (green<<10) | blue;
+
+		REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
+	}
+
+}
+
+
+static void mpc32_set_3dlut_mode(
+		struct mpc *mpc,
+		enum dc_lut_mode mode,
+		bool is_color_channel_12bits,
+		bool is_lut_size17x17x17,
+		uint32_t mpcc_id)
+{
+	uint32_t lut_mode;
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+
+	if (mode == LUT_BYPASS)
+		lut_mode = 0;
+	else if (mode == LUT_RAM_A)
+		lut_mode = 1;
+	else
+		lut_mode = 2;
+
+	REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
+			MPCC_MCM_3DLUT_MODE, lut_mode,
+			MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
+}
+
+
+bool mpc32_program_3dlut(
+		struct mpc *mpc,
+		const struct tetrahedral_params *params,
+		int mpcc_id)
+{
+	enum dc_lut_mode mode;
+	bool is_17x17x17;
+	bool is_12bits_color_channel;
+	const struct dc_rgb *lut0;
+	const struct dc_rgb *lut1;
+	const struct dc_rgb *lut2;
+	const struct dc_rgb *lut3;
+	int lut_size0;
+	int lut_size;
+
+	if (params == NULL) {
+		mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
+		return false;
+	}
+	mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
+
+	mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
+
+	if (mode == LUT_BYPASS || mode == LUT_RAM_B)
+		mode = LUT_RAM_A;
+	else
+		mode = LUT_RAM_B;
+
+	is_17x17x17 = !params->use_tetrahedral_9;
+	is_12bits_color_channel = params->use_12bits;
+	if (is_17x17x17) {
+		lut0 = params->tetrahedral_17.lut0;
+		lut1 = params->tetrahedral_17.lut1;
+		lut2 = params->tetrahedral_17.lut2;
+		lut3 = params->tetrahedral_17.lut3;
+		lut_size0 = sizeof(params->tetrahedral_17.lut0)/
+					sizeof(params->tetrahedral_17.lut0[0]);
+		lut_size  = sizeof(params->tetrahedral_17.lut1)/
+					sizeof(params->tetrahedral_17.lut1[0]);
+	} else {
+		lut0 = params->tetrahedral_9.lut0;
+		lut1 = params->tetrahedral_9.lut1;
+		lut2 = params->tetrahedral_9.lut2;
+		lut3 = params->tetrahedral_9.lut3;
+		lut_size0 = sizeof(params->tetrahedral_9.lut0)/
+				sizeof(params->tetrahedral_9.lut0[0]);
+		lut_size  = sizeof(params->tetrahedral_9.lut1)/
+				sizeof(params->tetrahedral_9.lut1[0]);
+		}
+
+	mpc32_select_3dlut_ram(mpc, mode,
+				is_12bits_color_channel, mpcc_id);
+	mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
+
+	mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
+	if (is_12bits_color_channel)
+		mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
+	else
+		mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
+
+	mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
+					is_17x17x17, mpcc_id);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
+
+	return true;
+}
+
+const struct mpc_funcs dcn32_mpc_funcs = {
+	.read_mpcc_state = mpc1_read_mpcc_state,
+	.insert_plane = mpc1_insert_plane,
+	.remove_mpcc = mpc1_remove_mpcc,
+	.mpc_init = mpc32_mpc_init,
+	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
+	.update_blending = mpc2_update_blending,
+	.cursor_lock = mpc1_cursor_lock,
+	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
+	.wait_for_idle = mpc2_assert_idle_mpcc,
+	.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
+	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
+	.set_denorm =  mpc3_set_denorm,
+	.set_denorm_clamp = mpc3_set_denorm_clamp,
+	.set_output_csc = mpc3_set_output_csc,
+	.set_ocsc_default = mpc3_set_ocsc_default,
+	.set_output_gamma = mpc3_set_output_gamma,
+	.insert_plane_to_secondary = NULL,
+	.remove_mpcc_from_secondary =  NULL,
+	.set_dwb_mux = mpc3_set_dwb_mux,
+	.disable_dwb_mux = mpc3_disable_dwb_mux,
+	.is_dwb_idle = mpc3_is_dwb_idle,
+	.set_out_rate_control = mpc3_set_out_rate_control,
+	.set_gamut_remap = mpc3_set_gamut_remap,
+	.program_shaper = mpc32_program_shaper,
+	.program_3dlut = mpc32_program_3dlut,
+	.acquire_rmu = NULL,
+	.release_rmu = NULL,
+	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
+};
+
+
+void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
+	struct dc_context *ctx,
+	const struct dcn30_mpc_registers *mpc_regs,
+	const struct dcn30_mpc_shift *mpc_shift,
+	const struct dcn30_mpc_mask *mpc_mask,
+	int num_mpcc,
+	int num_rmu)
+{
+	int i;
+
+	mpc30->base.ctx = ctx;
+
+	mpc30->base.funcs = &dcn32_mpc_funcs;
+
+	mpc30->mpc_regs = mpc_regs;
+	mpc30->mpc_shift = mpc_shift;
+	mpc30->mpc_mask = mpc_mask;
+
+	mpc30->mpcc_in_use_mask = 0;
+	mpc30->num_mpcc = num_mpcc;
+	mpc30->num_rmu = num_rmu;
+
+	for (i = 0; i < MAX_MPCC; i++)
+		mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
new file mode 100644
index 000000000000..d4be3c89ec7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h
@@ -0,0 +1,213 @@
+/* Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MPCC_DCN32_H__
+#define __DC_MPCC_DCN32_H__
+
+#include "dcn20/dcn20_mpc.h"
+#include "dcn30/dcn30_mpc.h"
+
+#define MPC_MCM_REG_LIST_DCN32(inst) \
+	SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst), \
+	SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\
+	SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst)
+
+
+#define MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
+	SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
+	SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
+	SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
+	SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
+	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
+	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
+	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
+	SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
+	SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
+	SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
+	SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\
+	SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
+
+
+void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
+	struct dc_context *ctx,
+	const struct dcn30_mpc_registers *mpc_regs,
+	const struct dcn30_mpc_shift *mpc_shift,
+	const struct dcn30_mpc_mask *mpc_mask,
+	int num_mpcc,
+	int num_rmu);
+
+#endif		//__DC_MPCC_DCN32_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
new file mode 100644
index 000000000000..88275ea4193c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn32_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+	optc1->tg_regs->reg
+
+#define CTX \
+	optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+		struct dc_crtc_timing *timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	uint32_t memory_mask = 0;
+	int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+	int mpcc_hactive = h_active / opp_cnt;
+	/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */
+	int odm_mem_count = (h_active + 2047) / 2048;
+
+	/*
+	 * display <= 4k : 2 memories + 2 pipes
+	 * 4k < display <= 8k : 4 memories + 2 pipes
+	 * 8k < display <= 12k : 6 memories + 4 pipes
+	 */
+	if (opp_cnt == 4) {
+		if (odm_mem_count <= 2)
+			memory_mask = 0x3;
+		else if (odm_mem_count <= 4)
+			memory_mask = 0xf;
+		else
+			memory_mask = 0x3f;
+	} else {
+		if (odm_mem_count <= 2)
+			memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+		else if (odm_mem_count <= 4)
+			memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+		else
+			memory_mask = 0x77;
+	}
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+		OPTC_MEM_SEL, memory_mask);
+
+	if (opp_cnt == 2) {
+		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 1,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1]);
+	} else if (opp_cnt == 4) {
+		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 3,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1],
+				OPTC_SEG2_SRC_SEL, opp_id[2],
+				OPTC_SEG3_SRC_SEL, opp_id[3]);
+	}
+
+	REG_UPDATE(OPTC_WIDTH_CONTROL,
+			OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	optc1->opp_count = opp_cnt;
+}
+
+static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
+}
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool optc32_enable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+			OPTC_SEG0_SRC_SEL, optc->inst);
+
+	/* VTG enable first is for HW workaround */
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 1);
+
+	REG_SEQ_START();
+
+	/* Enable CRTC */
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 2,
+			OTG_MASTER_EN, 1);
+
+	REG_SEQ_SUBMIT();
+	REG_SEQ_WAIT_DONE();
+
+	return true;
+}
+
+/* disable_crtc */
+static bool optc32_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* disable otg request until end of the first line
+	 * in the vertical blank region
+	 */
+	REG_UPDATE(OTG_CONTROL,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* Disable immediately. */
+	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
+}
+
+static void optc32_set_odm_bypass(struct timing_generator *optc,
+		const struct dc_crtc_timing *dc_crtc_timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+			OPTC_NUM_OF_INPUT_SEGMENT, 0,
+			OPTC_SEG0_SRC_SEL, optc->inst,
+			OPTC_SEG1_SRC_SEL, 0xf,
+			OPTC_SEG2_SRC_SEL, 0xf,
+			OPTC_SEG3_SRC_SEL, 0xf
+			);
+
+	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE, h_div);
+
+	REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, 0);
+	optc1->opp_count = 1;
+}
+
+
+static struct timing_generator_funcs dcn32_tg_funcs = {
+		.validate_timing = optc1_validate_timing,
+		.program_timing = optc1_program_timing,
+		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+		.program_global_sync = optc1_program_global_sync,
+		.enable_crtc = optc32_enable_crtc,
+		.disable_crtc = optc32_disable_crtc,
+		.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.is_counter_moving = optc1_is_counter_moving,
+		.get_position = optc1_get_position,
+		.get_frame_count = optc1_get_vblank_counter,
+		.get_scanoutpos = optc1_get_crtc_scanoutpos,
+		.get_otg_active_size = optc1_get_otg_active_size,
+		.set_early_control = optc1_set_early_control,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.wait_for_state = optc1_wait_for_state,
+		.set_blank_color = optc3_program_blank_color,
+		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+		.triplebuffer_lock = optc3_triplebuffer_lock,
+		.triplebuffer_unlock = optc2_triplebuffer_unlock,
+		.enable_reset_trigger = optc1_enable_reset_trigger,
+		.enable_crtc_reset = optc1_enable_crtc_reset,
+		.disable_reset_trigger = optc1_disable_reset_trigger,
+		.lock = optc3_lock,
+		.unlock = optc1_unlock,
+		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+		.enable_optc_clock = optc1_enable_optc_clock,
+		.set_vrr_m_const = optc3_set_vrr_m_const,
+		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
+		.set_vtotal_min_max = optc1_set_vtotal_min_max,
+		.set_static_screen_control = optc1_set_static_screen_control,
+		.program_stereo = optc1_program_stereo,
+		.is_stereo_left_eye = optc1_is_stereo_left_eye,
+		.tg_init = optc3_tg_init,
+		.is_tg_enabled = optc1_is_tg_enabled,
+		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+		.clear_optc_underflow = optc1_clear_optc_underflow,
+		.setup_global_swap_lock = NULL,
+		.get_crc = optc1_get_crc,
+		.configure_crc = optc1_configure_crc,
+		.set_dsc_config = optc3_set_dsc_config,
+		.get_dsc_status = optc2_get_dsc_status,
+		.set_dwb_source = NULL,
+		.set_odm_bypass = optc32_set_odm_bypass,
+		.set_odm_combine = optc32_set_odm_combine,
+		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
+		.get_optc_source = optc2_get_optc_source,
+		.set_out_mux = optc3_set_out_mux,
+		.set_drr_trigger_window = optc3_set_drr_trigger_window,
+		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+		.set_gsl = optc2_set_gsl,
+		.set_gsl_source_select = optc2_set_gsl_source_select,
+		.set_vtg_params = optc1_set_vtg_params,
+		.program_manual_trigger = optc2_program_manual_trigger,
+		.setup_manual_trigger = optc2_setup_manual_trigger,
+		.get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn32_timing_generator_init(struct optc *optc1)
+{
+	optc1->base.funcs = &dcn32_tg_funcs;
+
+	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+	optc1->min_h_blank = 32;
+	optc1->min_v_blank = 3;
+	optc1->min_v_blank_interlace = 5;
+	optc1->min_h_sync_width = 4;
+	optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
new file mode 100644
index 000000000000..5e57c39235fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN32_H__
+#define __DC_OPTC_DCN32_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_2(inst) \
+	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+	SRI(OTG_VREADY_PARAM, OTG, inst),\
+	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+	SRI(OTG_H_TOTAL, OTG, inst),\
+	SRI(OTG_H_BLANK_START_END, OTG, inst),\
+	SRI(OTG_H_SYNC_A, OTG, inst),\
+	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+	SRI(OTG_V_TOTAL, OTG, inst),\
+	SRI(OTG_V_BLANK_START_END, OTG, inst),\
+	SRI(OTG_V_SYNC_A, OTG, inst),\
+	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_CONTROL, OTG, inst),\
+	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_STATUS, OTG, inst),\
+	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	SRI(OTG_TRIGA_CNTL, OTG, inst),\
+	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+	SRI(OTG_STATUS, OTG, inst),\
+	SRI(OTG_STATUS_POSITION, OTG, inst),\
+	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+	SRI(OTG_M_CONST_DTO0, OTG, inst),\
+	SRI(OTG_M_CONST_DTO1, OTG, inst),\
+	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+	SRI(CONTROL, VTG, inst),\
+	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+	SRI(OTG_GSL_CONTROL, OTG, inst),\
+	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+	SRI(OTG_CRC0_DATA_B, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SR(GSL_SOURCE_SELECT),\
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+	SRI(OTG_DSC_START_POSITION, OTG, inst),\
+	SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+	SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
+
+void dcn32_timing_generator_init(struct optc *optc1);
+
+#endif /* __DC_OPTC_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
new file mode 100644
index 000000000000..1ea6d258a20d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -0,0 +1,4002 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn32_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn32_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn32/dcn32_hubbub.h"
+#include "dcn32/dcn32_mpc.h"
+#include "dcn32_hubp.h"
+#include "irq/dcn32/irq_service_dcn32.h"
+#include "dcn32/dcn32_dpp.h"
+#include "dcn32/dcn32_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32/dcn32_dio_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32/dcn32_hpo_dp_link_encoder.h"
+#include "dc_link_dp.h"
+#include "dcn31/dcn31_apg.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32/dcn32_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dml/display_mode_vba.h"
+#include "dcn32/dcn32_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dc_link_ddc.h"
+#include "dcn31/dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn32/dcn32_mmhubbub.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+#include "nbio/nbio_4_3_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+
+#define MAX_INSTANCE                                        6
+#define MAX_SEGMENT                                         6
+
+struct IP_BASE_INSTANCE {
+	unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE {
+	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } } } };
+
+#define DC_LOGGER_INIT(logger)
+
+#define DCN3_2_DEFAULT_DET_SIZE 256
+#define DCN3_2_MAX_DET_SIZE 1152
+#define DCN3_2_MIN_DET_SIZE 128
+#define DCN3_2_MIN_COMPBUF_SIZE_KB 128
+
+struct _vcs_dpi_ip_params_st dcn3_2_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 0,
+	.rob_buffer_size_kbytes = 128,
+	.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1280,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 22,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
+	.min_pixel_chunk_size_bytes = 1024,
+	.dcc_meta_buffer_size_bytes = 6272,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 4,
+	.maximum_dsc_bits_per_component = 12,
+	.maximum_pixels_per_line_per_dsc_unit = 6016,
+	.dsc422_native_support = true,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 57,
+	.line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
+	.max_line_buffer_lines = 32,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 47,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 28,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 125,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+	.max_num_dp2p0_outputs = 2,
+	.max_num_dp2p0_streams = 4,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
+	.clock_limits = {
+		{
+			.state = 0,
+			.dcfclk_mhz = 1564.0,
+			.fabricclk_mhz = 400.0,
+			.dispclk_mhz = 2150.0,
+			.dppclk_mhz = 2150.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.phyclk_d32_mhz = 625.0,
+			.socclk_mhz = 1200.0,
+			.dscclk_mhz = 716.667,
+			.dram_speed_mts = 1600.0,
+			.dtbclk_mhz = 1564.0,
+		},
+	},
+	.num_states = 1,
+	.sr_exit_time_us = 5.20,
+	.sr_enter_plus_exit_time_us = 9.60,
+	.sr_exit_z8_time_us = 285.0,
+	.sr_enter_plus_exit_z8_time_us = 320,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 263,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.fclk_change_latency_us = 20,
+	.usr_retraining_latency_us = 2,
+	.smn_latency_us = 2,
+	.mall_allocated_for_dcn_mbytes = 64,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 100.0,
+	.pct_ideal_fabric_bw_after_urgent = 67.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,
+	.max_avg_sdp_bw_use_normal_percent = 80.0,
+	.max_avg_fabric_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
+	.max_avg_dram_bw_use_normal_percent = 15.0,
+	.num_chans = 8,
+	.dram_channel_width_bytes = 2,
+	.fabric_datapath_to_dcn_data_return_bytes = 64,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.dram_clock_change_latency_us = 400,
+	.dispclk_dppclk_vco_speed_mhz = 4300.0,
+	.do_urgent_latency_adjustment = true,
+	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+enum dcn32_clk_src_array_id {
+	DCN32_CLK_SRC_PLL0,
+	DCN32_CLK_SRC_PLL1,
+	DCN32_CLK_SRC_PLL2,
+	DCN32_CLK_SRC_PLL3,
+	DCN32_CLK_SRC_PLL4,
+	DCN32_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX0_ ## reg_name
+
+#define CTX ctx
+#define REG(reg_name) \
+	(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN32_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define apg_regs(id)\
+[id] = {\
+	APG_DCN31_REG_LIST(id)\
+}
+
+static const struct dcn31_apg_registers apg_regs[] = {
+	apg_regs(0),
+	apg_regs(1),
+	apg_regs(2),
+	apg_regs(3)
+};
+
+static const struct dcn31_apg_shift apg_shift = {
+	DCN31_APG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_apg_mask apg_mask = {
+		DCN31_APG_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN32_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	/*DPCS_DCN31_REG_LIST(id),*/ \
+}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+
+	//DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define hpo_dp_stream_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
+}
+
+static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
+	hpo_dp_stream_encoder_reg_list(0),
+	hpo_dp_stream_encoder_reg_list(1),
+	hpo_dp_stream_encoder_reg_list(2),
+	hpo_dp_stream_encoder_reg_list(3),
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
+};
+
+
+#define hpo_dp_link_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
+	/*DCN3_1_RDPCSTX_REG_LIST(0),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(1),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(2),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(3),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(4)*/\
+}
+
+static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
+	hpo_dp_link_encoder_reg_list(0),
+	hpo_dp_link_encoder_reg_list(1),
+};
+
+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30_COMMON(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
+};
+
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN32(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2),
+	dsc_regsDCN20(3)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_MCM_REG_LIST_DCN32(0),
+		MPC_MCM_REG_LIST_DCN32(1),
+		MPC_MCM_REG_LIST_DCN32(2),
+		MPC_MCM_REG_LIST_DCN32(3),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
+
+//#ifdef DIAGS_BUILD
+//static struct dcn_optc_registers optc_regs[] = {
+//#else
+static const struct dcn_optc_registers optc_regs[] = {
+//#endif
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN32(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN32(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN32(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN32(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN32()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN32_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN32_REG_LIST()
+};
+
+#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN32_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn32 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_hpo_dp_stream_encoder = 4,
+	.num_hpo_dp_link_encoder = 2,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 4,
+	.num_dsc = 4,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = true,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.disable_idle_power_optimizations = true,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = true,
+		}
+	},
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_dsc_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static struct dce_aux *dcn32_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn32_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static struct clock_source *dcn32_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub2)
+		return NULL;
+
+	hubbub32_construct(hubbub2, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			ctx->dc->dml.ip.det_buffer_size_kbytes,
+			ctx->dc->dml.ip.pixel_chunk_size_kbytes,
+			ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub2->base;
+}
+
+static struct hubp *dcn32_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp32_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static void dcn32_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN30_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn32_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp3 =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp3)
+		return NULL;
+
+	if (dpp32_construct(dpp3, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp3->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp3);
+	return NULL;
+}
+
+static struct mpc *dcn32_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn32_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct output_pixel_processor *dcn32_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp2 =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp2) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp2, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp2->base;
+}
+
+
+static struct timing_generator *dcn32_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn32_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn32_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn32_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dcn31_panel_cntl *panel_cntl =
+		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dcn31_panel_cntl_construct(panel_cntl, init_data);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn32_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn32_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn32_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct apg *dcn31_apg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
+
+	if (!apg31)
+		return NULL;
+
+	apg31_construct(apg31, ctx, inst,
+			&apg_regs[inst],
+			&apg_shift,
+			&apg_mask);
+
+	return &apg31->base;
+}
+
+static struct stream_encoder *dcn32_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn32_vpg_create(ctx, vpg_inst);
+	afmt = dcn32_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt) {
+		kfree(enc1);
+		kfree(vpg);
+		kfree(afmt);
+		return NULL;
+	}
+
+	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
+	struct vpg *vpg;
+	struct apg *apg;
+	uint32_t hpo_dp_inst;
+	uint32_t vpg_inst;
+	uint32_t apg_inst;
+
+	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
+
+	/* Mapping of VPG register blocks to HPO DP block instance:
+	 * VPG[6] -> HPO_DP[0]
+	 * VPG[7] -> HPO_DP[1]
+	 * VPG[8] -> HPO_DP[2]
+	 * VPG[9] -> HPO_DP[3]
+	 */
+	vpg_inst = hpo_dp_inst + 6;
+
+	/* Mapping of APG register blocks to HPO DP block instance:
+	 * APG[0] -> HPO_DP[0]
+	 * APG[1] -> HPO_DP[1]
+	 * APG[2] -> HPO_DP[2]
+	 * APG[3] -> HPO_DP[3]
+	 */
+	apg_inst = hpo_dp_inst;
+
+	/* allocate HPO stream encoder and create VPG sub-block */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
+	vpg = dcn32_vpg_create(ctx, vpg_inst);
+	apg = dcn31_apg_create(ctx, apg_inst);
+
+	if (!hpo_dp_enc31 || !vpg || !apg) {
+		kfree(hpo_dp_enc31);
+		kfree(vpg);
+		kfree(apg);
+		return NULL;
+	}
+
+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
+					hpo_dp_inst, eng_id, vpg, apg,
+					&hpo_dp_stream_enc_regs[hpo_dp_inst],
+					&hpo_dp_se_shift, &hpo_dp_se_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
+	uint8_t inst,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
+
+	/* allocate HPO link encoder */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
+
+	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
+					&hpo_dp_link_enc_regs[inst],
+					&hpo_dp_le_shift, &hpo_dp_le_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct dce_hwseq *dcn32_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn32_create_audio,
+	.create_stream_encoder = dcn32_stream_encoder_create,
+	.create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn32_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn32_hwseq_create,
+};
+
+static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
+		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
+			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
+				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
+				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
+				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
+			}
+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
+			pool->base.hpo_dp_stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
+		if (pool->base.hpo_dp_link_enc[i] != NULL) {
+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
+			pool->base.hpo_dp_link_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn32_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.oem_device != NULL)
+		dal_ddc_service_destroy(&pool->base.oem_device);
+}
+
+
+static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn32_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn32_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+
+	dsc->max_image_width = 6016;
+
+	return &dsc->base;
+}
+
+static void dcn32_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
+
+	dcn32_resource_destruct(dcn32_pool);
+	kfree(dcn32_pool);
+	*pool = NULL;
+}
+
+bool dcn32_acquire_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		int mpcc_id,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper)
+{
+	bool ret = false;
+	union dc_3dlut_state *state;
+
+	ASSERT(*lut == NULL && *shaper == NULL);
+	*lut = NULL;
+	*shaper = NULL;
+
+	if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
+		*lut = pool->mpc_lut[mpcc_id];
+		*shaper = pool->mpc_shaper[mpcc_id];
+		state = &pool->mpc_lut[mpcc_id]->state;
+		res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
+		ret = true;
+	}
+	return ret;
+}
+
+bool dcn32_release_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper)
+{
+	int i;
+	bool ret = false;
+
+	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+		if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
+			res_ctx->is_mpc_3dlut_acquired[i] = false;
+			pool->mpc_lut[i]->state.raw = 0;
+			*lut = NULL;
+			*shaper = NULL;
+			ret = true;
+			break;
+		}
+	}
+	return ret;
+}
+
+/**
+ ********************************************************************************************
+ * dcn32_get_num_free_pipes: Calculate number of free pipes
+ *
+ * This function assumes that a "used" pipe is a pipe that has
+ * both a stream and a plane assigned to it.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: Number of free pipes available in the context
+ *
+ ********************************************************************************************
+ */
+static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
+{
+	unsigned int i;
+	unsigned int free_pipes = 0;
+	unsigned int num_pipes = 0;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe) {
+			while (pipe) {
+				num_pipes++;
+				pipe = pipe->bottom_pipe;
+			}
+		}
+	}
+
+	free_pipes = dc->res_pool->pipe_count - num_pipes;
+	return free_pipes;
+}
+
+/**
+ ********************************************************************************************
+ * dcn32_assign_subvp_pipe: Function to decide which pipe will use Sub-VP.
+ *
+ * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
+ * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
+ * we are forcing SubVP P-State switching on the current config.
+ *
+ * The number of pipes used for the chosen surface must be less than or equal to the
+ * number of free pipes available.
+ *
+ * In general we choose surfaces that have ActiveDRAMClockChangeLatencyMargin <= 0 first,
+ * then among those surfaces we choose the one with the smallest VBLANK time. We only consider
+ * surfaces with ActiveDRAMClockChangeLatencyMargin > 0 if we are forcing a Sub-VP config.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [out] index: dc pipe index for the pipe chosen to have phantom pipes assigned
+ *
+ * @return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
+ *
+ ********************************************************************************************
+ */
+
+static bool dcn32_assign_subvp_pipe(struct dc *dc,
+		struct dc_state *context,
+		unsigned int *index)
+{
+	unsigned int i, pipe_idx;
+	unsigned int min_vblank_us = INT_MAX;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	bool valid_assignment_found = false;
+	unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		unsigned int num_pipes = 0;
+
+		if (!pipe->stream)
+			continue;
+
+		if (pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			while (pipe) {
+				num_pipes++;
+				pipe = pipe->bottom_pipe;
+			}
+
+			pipe = &context->res_ctx.pipe_ctx[i];
+			if (num_pipes <= free_pipes) {
+				struct dc_stream_state *stream = pipe->stream;
+				unsigned int vblank_us = ((stream->timing.v_total - stream->timing.v_addressable) *
+							stream->timing.h_total /
+							(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
+				if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] <= 0 &&
+						vblank_us < min_vblank_us) {
+					*index = i;
+					min_vblank_us = vblank_us;
+					valid_assignment_found = true;
+				} else if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
+						dc->debug.force_subvp_mclk_switch && !valid_assignment_found) {
+					// Handle case for forcing Sub-VP config. In this case we can assign
+					// phantom pipes to a surface that has active margin > 0.
+					*index = i;
+					valid_assignment_found = true;
+				}
+			}
+		}
+		pipe_idx++;
+	}
+	return valid_assignment_found;
+}
+
+/**
+ * ***************************************************************************************
+ * dcn32_enough_pipes_for_subvp: Function to check if there are "enough" pipes for SubVP.
+ *
+ * This function returns true if there are enough free pipes
+ * to create the required phantom pipes for any given stream
+ * (that does not already have phantom pipe assigned).
+ *
+ * e.g. For a 2 stream config where the first stream uses one
+ * pipe and the second stream uses 2 pipes (i.e. pipe split),
+ * this function will return true because there is 1 remaining
+ * pipe which can be used as the phantom pipe for the non pipe
+ * split pipe.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: True if there are enough free pipes to assign phantom pipes to at least one
+ *          stream that does not already have phantom pipes assigned. Otherwise false.
+ *
+ * ***************************************************************************************
+ */
+static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
+{
+	unsigned int i, split_cnt, free_pipes;
+	unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
+	bool subvp_possible = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		// Find the minimum pipe split count for non SubVP pipes
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			split_cnt = 0;
+			while (pipe) {
+				split_cnt++;
+				pipe = pipe->bottom_pipe;
+			}
+
+			if (split_cnt < min_pipe_split)
+				min_pipe_split = split_cnt;
+		}
+	}
+
+	free_pipes = dcn32_get_num_free_pipes(dc, context);
+
+	// SubVP only possible if at least one pipe is being used (i.e. free_pipes
+	// should not equal to the pipe_count)
+	if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
+		subvp_possible = true;
+
+	return subvp_possible;
+}
+
+static void dcn32_enable_phantom_plane(struct dc *dc,
+		struct dc_state *context,
+		struct dc_stream_state *phantom_stream,
+		unsigned int dc_pipe_idx)
+{
+	struct dc_plane_state *phantom_plane = NULL;
+	struct dc_plane_state *prev_phantom_plane = NULL;
+	struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
+
+	while (curr_pipe) {
+		if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
+			phantom_plane = prev_phantom_plane;
+		else
+			phantom_plane = dc_create_plane_state(dc);
+
+		memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
+		memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
+				sizeof(phantom_plane->scaling_quality));
+		memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
+		memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
+		memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
+		memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
+				sizeof(phantom_plane->plane_size));
+		memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
+				sizeof(phantom_plane->tiling_info));
+		memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
+		phantom_plane->format = curr_pipe->plane_state->format;
+		phantom_plane->rotation = curr_pipe->plane_state->rotation;
+		phantom_plane->visible = curr_pipe->plane_state->visible;
+
+		/* Shadow pipe has small viewport. */
+		phantom_plane->clip_rect.y = 0;
+		phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
+
+		dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);
+
+		curr_pipe = curr_pipe->bottom_pipe;
+		prev_phantom_plane = phantom_plane;
+	}
+}
+
+/**
+ * ***************************************************************************************
+ * dcn32_set_phantom_stream_timing: Set timing params for the phantom stream
+ *
+ * Set timing params of the phantom stream based on calculated output from DML.
+ * This function first gets the DML pipe index using the DC pipe index, then
+ * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
+ * lines required for SubVP MCLK switching and assigns to the phantom stream
+ * accordingly.
+ *
+ * - The number of SubVP lines calculated in DML does not take into account
+ * FW processing delays and required pstate allow width, so we must include
+ * that separately.
+ *
+ * - Set phantom backporch = vstartup of main pipe
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] ref_pipe: Main pipe for the phantom stream
+ * @param [in] pipes: DML pipe params
+ * @param [in] pipe_cnt: number of DML pipes
+ * @param [in] dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
+ *
+ * @return: void
+ *
+ * ***************************************************************************************
+ */
+static void dcn32_set_phantom_stream_timing(struct dc *dc,
+		struct dc_state *context,
+		struct pipe_ctx *ref_pipe,
+		struct dc_stream_state *phantom_stream,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int dc_pipe_idx)
+{
+	unsigned int i, pipe_idx;
+	struct pipe_ctx *pipe;
+	uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
+	unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
+	unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
+
+	// Find DML pipe index (pipe_idx) using dc_pipe_idx
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (i == dc_pipe_idx)
+			break;
+
+		pipe_idx++;
+	}
+
+	// Calculate lines required for pstate allow width and FW processing delays
+	pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
+			dc->caps.subvp_pstate_allow_width_us) / 1000000) *
+			(ref_pipe->stream->timing.pix_clk_100hz * 100) /
+			(double)ref_pipe->stream->timing.h_total;
+
+	// Update clks_cfg for calling into recalculate
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = socclk;
+
+	// DML calculation for MALL region doesn't take into account FW delay
+	// and required pstate allow width for multi-display cases
+	phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
+				pstate_width_fw_delay_lines;
+
+	// For backporch of phantom pipe, use vstartup of the main pipe
+	phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+	phantom_stream->dst.y = 0;
+	phantom_stream->dst.height = phantom_vactive;
+	phantom_stream->src.y = 0;
+	phantom_stream->src.height = phantom_vactive;
+
+	phantom_stream->timing.v_addressable = phantom_vactive;
+	phantom_stream->timing.v_front_porch = 1;
+	phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
+						phantom_stream->timing.v_front_porch +
+						phantom_stream->timing.v_sync_width +
+						phantom_bp;
+}
+
+static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int dc_pipe_idx)
+{
+	struct dc_stream_state *phantom_stream = NULL;
+	struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
+
+	phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink);
+	phantom_stream->signal = SIGNAL_TYPE_VIRTUAL;
+	phantom_stream->dpms_off = true;
+	phantom_stream->mall_stream_config.type = SUBVP_PHANTOM;
+	phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream;
+	ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN;
+	ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream;
+
+	/* stream has limited viewport and small timing */
+	memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
+	memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
+	memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
+	dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
+
+	dc_add_stream_to_ctx(dc, context, phantom_stream);
+	return phantom_stream;
+}
+
+void dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	bool removed_pipe = false;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		// build scaling params for phantom pipes
+		if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			dc_rem_all_planes_for_stream(dc, pipe->stream, context);
+			dc_remove_stream_from_ctx(dc, context, pipe->stream);
+			removed_pipe = true;
+		}
+
+		// Clear all phantom stream info
+		if (pipe->stream) {
+			pipe->stream->mall_stream_config.type = SUBVP_NONE;
+			pipe->stream->mall_stream_config.paired_stream = NULL;
+		}
+	}
+	if (removed_pipe)
+		dc->hwss.apply_ctx_to_hw(dc, context);
+}
+
+/* TODO: Input to this function should indicate which pipe indexes (or streams)
+ * require a phantom pipe / stream
+ */
+void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int index)
+{
+	struct dc_stream_state *phantom_stream = NULL;
+	unsigned int i;
+
+	// The index of the DC pipe passed into this function is guarenteed to
+	// be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
+	// already have phantom pipe assigned, etc.) by previous checks.
+	phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
+	dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		// Build scaling params for phantom pipes which were newly added.
+		// We determine which phantom pipes were added by comparing with
+		// the phantom stream.
+		if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
+				pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			pipe->stream->use_dynamic_meta = false;
+			pipe->plane_state->flip_immediate = false;
+			if (!resource_build_scaling_params(pipe)) {
+				// Log / remove phantom pipes since failed to build scaling params
+			}
+		}
+	}
+}
+
+static bool dcn32_split_stream_for_mpc_or_odm(
+		const struct dc *dc,
+		struct resource_context *res_ctx,
+		struct pipe_ctx *pri_pipe,
+		struct pipe_ctx *sec_pipe,
+		bool odm)
+{
+	int pipe_idx = sec_pipe->pipe_idx;
+	const struct resource_pool *pool = dc->res_pool;
+
+	if (pri_pipe->plane_state) {
+		/* ODM + window MPO, where MPO window is on left half only */
+		if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
+				pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
+			return true;
+
+		/* ODM + window MPO, where MPO window is on right half only */
+		if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
+			return true;
+	}
+
+	*sec_pipe = *pri_pipe;
+
+	sec_pipe->pipe_idx = pipe_idx;
+	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
+	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
+	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
+	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
+	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
+	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+	sec_pipe->stream_res.dsc = NULL;
+	if (odm) {
+		if (pri_pipe->next_odm_pipe) {
+			ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
+			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
+			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
+		}
+		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
+			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
+			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
+		}
+		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
+			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
+			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
+		}
+		pri_pipe->next_odm_pipe = sec_pipe;
+		sec_pipe->prev_odm_pipe = pri_pipe;
+		ASSERT(sec_pipe->top_pipe == NULL);
+
+		if (!sec_pipe->top_pipe)
+			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
+		else
+			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
+		if (sec_pipe->stream->timing.flags.DSC == 1) {
+			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
+			ASSERT(sec_pipe->stream_res.dsc);
+			if (sec_pipe->stream_res.dsc == NULL)
+				return false;
+		}
+	} else {
+		if (pri_pipe->bottom_pipe) {
+			ASSERT(pri_pipe->bottom_pipe != sec_pipe);
+			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
+			sec_pipe->bottom_pipe->top_pipe = sec_pipe;
+		}
+		pri_pipe->bottom_pipe = sec_pipe;
+		sec_pipe->top_pipe = pri_pipe;
+
+		ASSERT(pri_pipe->plane_state);
+	}
+
+	return true;
+}
+
+static struct pipe_ctx *dcn32_find_split_pipe(
+		struct dc *dc,
+		struct dc_state *context,
+		int old_index)
+{
+	struct pipe_ctx *pipe = NULL;
+	int i;
+
+	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
+		pipe = &context->res_ctx.pipe_ctx[old_index];
+		pipe->pipe_idx = old_index;
+	}
+
+	if (!pipe)
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
+					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
+				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+					pipe = &context->res_ctx.pipe_ctx[i];
+					pipe->pipe_idx = i;
+					break;
+				}
+			}
+		}
+
+	/*
+	 * May need to fix pipes getting tossed from 1 opp to another on flip
+	 * Add for debugging transient underflow during topology updates:
+	 * ASSERT(pipe);
+	 */
+	if (!pipe)
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+				pipe = &context->res_ctx.pipe_ctx[i];
+				pipe->pipe_idx = i;
+				break;
+			}
+		}
+
+	return pipe;
+}
+
+
+/**
+ * ***************************************************************************************
+ * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
+ *
+ * High level algorithm:
+ * 1. Find longest microschedule length (in us) between the two SubVP pipes
+ * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
+ * pipes still allows for the maximum microschedule to fit in the active
+ * region for both pipes.
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: bool - True if the SubVP + SubVP config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
+{
+	struct pipe_ctx *subvp_pipes[2];
+	struct dc_stream_state *phantom = NULL;
+	uint32_t microschedule_lines = 0;
+	uint32_t index = 0;
+	uint32_t i;
+	uint32_t max_microschedule_us = 0;
+	int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		uint32_t time_us = 0;
+
+		/* Loop to calculate the maximum microschedule time between the two SubVP pipes,
+		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
+		 */
+		if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			phantom = pipe->stream->mall_stream_config.paired_stream;
+			microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
+					phantom->timing.v_addressable;
+
+			// Round up when calculating microschedule time
+			time_us = ((microschedule_lines * phantom->timing.h_total +
+					phantom->timing.pix_clk_100hz * 100 - 1) /
+					(double)(phantom->timing.pix_clk_100hz * 100)) * 1000000 +
+						dc->caps.subvp_prefetch_end_to_mall_start_us +
+						dc->caps.subvp_fw_processing_delay_us;
+			if (time_us > max_microschedule_us)
+				max_microschedule_us = time_us;
+
+			subvp_pipes[index] = pipe;
+			index++;
+
+			// Maximum 2 SubVP pipes
+			if (index == 2)
+				break;
+		}
+	}
+	vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
+				(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
+			subvp_pipes[0]->stream->timing.h_total) /
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+	vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
+			subvp_pipes[1]->stream->timing.h_total) /
+			(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+
+	if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
+			(vactive2_us - vblank1_us) / 2 > max_microschedule_us)
+		return true;
+
+	return false;
+}
+
+/**
+ * ***************************************************************************************
+ * subvp_drr_schedulable: Determine if SubVP + DRR config is schedulable
+ *
+ * High level algorithm:
+ * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
+ * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
+ * (the margin is equal to the MALL region + DRR margin (500us))
+ * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
+ * then report the configuration as supported
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] drr_pipe: DRR pipe_ctx for the SubVP + DRR config
+ *
+ * @return: bool - True if the SubVP + DRR config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
+{
+	bool schedulable = false;
+	uint32_t i;
+	struct pipe_ctx *pipe = NULL;
+	struct dc_crtc_timing *main_timing = NULL;
+	struct dc_crtc_timing *phantom_timing = NULL;
+	struct dc_crtc_timing *drr_timing = NULL;
+	int16_t prefetch_us = 0;
+	int16_t mall_region_us = 0;
+	int16_t drr_frame_us = 0;	// nominal frame time
+	int16_t subvp_active_us = 0;
+	int16_t stretched_drr_us = 0;
+	int16_t drr_stretched_vblank_us = 0;
+	int16_t max_vblank_mallregion = 0;
+
+	// Find SubVP pipe
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		// We check for master pipe, but it shouldn't matter since we only need
+		// the pipe for timing info (stream should be same for any pipe splits)
+		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+
+		// Find the SubVP pipe
+		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			break;
+	}
+
+	main_timing = &pipe->stream->timing;
+	phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
+	drr_timing = &drr_pipe->stream->timing;
+	prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
+			dc->caps.subvp_prefetch_end_to_mall_start_us;
+	subvp_active_us = main_timing->v_addressable * main_timing->h_total /
+			(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+	drr_frame_us = drr_timing->v_total * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
+	// P-State allow width and FW delays already included phantom_timing->v_addressable
+	mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
+	stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
+	drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
+	max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
+
+	/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
+	 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
+	 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
+	 * and the max of (VBLANK blanking time, MALL region)).
+	 */
+	if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
+			subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
+		schedulable = true;
+
+	return schedulable;
+}
+
+/**
+ * ***************************************************************************************
+ * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
+ *
+ * High level algorithm:
+ * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
+ * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
+ * then report the configuration as supported
+ * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ *
+ * @return: bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
+ *
+ * ***************************************************************************************
+ */
+static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
+{
+	struct pipe_ctx *pipe = NULL;
+	struct pipe_ctx *subvp_pipe = NULL;
+	bool found = false;
+	bool schedulable = false;
+	uint32_t i = 0;
+	uint8_t vblank_index = 0;
+	int16_t prefetch_us = 0;
+	int16_t mall_region_us = 0;
+	int16_t vblank_frame_us = 0;
+	int16_t subvp_active_us = 0;
+	int16_t vblank_blank_us = 0;
+	int16_t max_vblank_mallregion = 0;
+	struct dc_crtc_timing *main_timing = NULL;
+	struct dc_crtc_timing *phantom_timing = NULL;
+	struct dc_crtc_timing *vblank_timing = NULL;
+
+	/* For SubVP + VBLANK/DRR cases, we assume there can only be
+	 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
+	 * is supported, it is either a single VBLANK case or two VBLANK
+	 * displays which are synchronized (in which case they have identical
+	 * timings).
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		pipe = &context->res_ctx.pipe_ctx[i];
+
+		// We check for master pipe, but it shouldn't matter since we only need
+		// the pipe for timing info (stream should be same for any pipe splits)
+		if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+
+		if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+			// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
+			vblank_index = i;
+			found = true;
+		}
+
+		if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			subvp_pipe = pipe;
+	}
+	// Use ignore_msa_timing_param flag to identify as DRR
+	if (found && pipe->stream->ignore_msa_timing_param) {
+		// SUBVP + DRR case
+		schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]);
+	} else if (found) {
+		main_timing = &subvp_pipe->stream->timing;
+		phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
+		vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
+		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
+		// Also include the prefetch end to mallstart delay time
+		prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
+				dc->caps.subvp_prefetch_end_to_mall_start_us;
+		// P-State allow width and FW delays already included phantom_timing->v_addressable
+		mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
+				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
+		vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
+		vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
+		subvp_active_us = main_timing->v_addressable * main_timing->h_total /
+				(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+		max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
+
+		// Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
+		// and the max of (VBLANK blanking time, MALL region)
+		// TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
+		if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
+			schedulable = true;
+	}
+	return schedulable;
+}
+
+/**
+ * ********************************************************************************************
+ * subvp_validate_static_schedulability: Check which SubVP case is calculated and handle
+ * static analysis based on the case.
+ *
+ * Three cases:
+ * 1. SubVP + SubVP
+ * 2. SubVP + VBLANK (DRR checked internally)
+ * 3. SubVP + VACTIVE (currently unsupported)
+ *
+ * @param [in] dc: current dc state
+ * @param [in] context: new dc state
+ * @param [in] vlevel: Voltage level calculated by DML
+ *
+ * @return: bool - True if statically schedulable, false otherwise
+ *
+ * ********************************************************************************************
+ */
+static bool subvp_validate_static_schedulability(struct dc *dc,
+				struct dc_state *context,
+				int vlevel)
+{
+	bool schedulable = true;	// true by default for single display case
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	uint32_t i, pipe_idx;
+	uint8_t subvp_count = 0;
+	uint8_t vactive_count = 0;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe->stream)
+			continue;
+
+		if (pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			subvp_count++;
+
+		// Count how many planes are capable of VACTIVE switching (SubVP + VACTIVE unsupported)
+		if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0) {
+			vactive_count++;
+		}
+		pipe_idx++;
+	}
+
+	if (subvp_count == 2) {
+		// Static schedulability check for SubVP + SubVP case
+		schedulable = subvp_subvp_schedulable(dc, context);
+	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
+		// Static schedulability check for SubVP + VBLANK case. Also handle the case where
+		// DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
+		if (vactive_count > 0)
+			schedulable = false;
+		else
+			schedulable = subvp_vblank_schedulable(dc, context);
+	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp) {
+		// SubVP + VACTIVE currently unsupported
+		schedulable = false;
+	}
+	return schedulable;
+}
+
+static void dcn32_full_validate_bw_helper(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *vlevel,
+		int *split,
+		bool *merge,
+		int *pipe_cnt)
+{
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+	unsigned int dc_pipe_idx = 0;
+	bool found_supported_config = false;
+	struct pipe_ctx *pipe = NULL;
+	uint32_t non_subvp_pipes = 0;
+	bool drr_pipe_found = false;
+	uint32_t drr_pipe_index = 0;
+	uint32_t i = 0;
+
+	/*
+	 * DML favors voltage over p-state, but we're more interested in
+	 * supporting p-state over voltage. We can't support p-state in
+	 * prefetch mode > 0 so try capping the prefetch mode to start.
+	 */
+	context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
+			dm_prefetch_support_uclk_fclk_and_stutter;
+	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
+	/* This may adjust vlevel and maxMpcComb */
+	if (*vlevel < context->bw_ctx.dml.soc.num_states)
+		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+
+	/* Conditions for setting up phantom pipes for SubVP:
+	 * 1. Not force disable SubVP
+	 * 2. Full update (i.e. !fast_validate)
+	 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
+	 * 4. Display configuration passes validation
+	 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
+	 */
+	if (!dc->debug.force_disable_subvp &&
+			(*vlevel == context->bw_ctx.dml.soc.num_states ||
+			vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
+			dc->debug.force_subvp_mclk_switch)) {
+
+		while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
+				dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
+
+			dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
+
+			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
+			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
+
+			if (*vlevel < context->bw_ctx.dml.soc.num_states &&
+					vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
+					&& subvp_validate_static_schedulability(dc, context, *vlevel)) {
+				found_supported_config = true;
+			} else if (*vlevel < context->bw_ctx.dml.soc.num_states &&
+					vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+				/* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles
+				 * the case for SubVP + DRR, where the DRR display does not support MCLK switch
+				 * at it's native refresh rate / timing.
+				 */
+				for (i = 0; i < dc->res_pool->pipe_count; i++) {
+					pipe = &context->res_ctx.pipe_ctx[i];
+					if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
+							pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+						non_subvp_pipes++;
+						// Use ignore_msa_timing_param flag to identify as DRR
+						if (pipe->stream->ignore_msa_timing_param) {
+							drr_pipe_found = true;
+							drr_pipe_index = i;
+						}
+					}
+				}
+				// If there is only 1 remaining non SubVP pipe that is DRR, check static
+				// schedulability for SubVP + DRR.
+				if (non_subvp_pipes == 1 && drr_pipe_found) {
+					found_supported_config = subvp_drr_schedulable(dc,
+							context, &context->res_ctx.pipe_ctx[drr_pipe_index]);
+				}
+			}
+		}
+
+		// If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
+		// remove phantom pipes and repopulate dml pipes
+		if (!found_supported_config) {
+			dc->res_pool->funcs->remove_phantom_pipes(dc, context);
+			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
+		} else {
+			// only call dcn20_validate_apply_pipe_split_flags if we found a supported config
+			memset(split, 0, MAX_PIPES * sizeof(int));
+			memset(merge, 0, MAX_PIPES * sizeof(bool));
+			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+
+			// If found a supported SubVP config, phantom pipes were added to the context.
+			// Program timing for the phantom pipes.
+			dc->hwss.apply_ctx_to_hw(dc, context);
+		}
+	}
+}
+
+static bool dcn32_internal_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *vlevel_out,
+		bool fast_validate)
+{
+	bool out = false;
+	bool repopulate_pipes = false;
+	int split[MAX_PIPES] = { 0 };
+	bool merge[MAX_PIPES] = { false };
+	bool newly_split[MAX_PIPES] = { false };
+	int pipe_cnt, i, pipe_idx, vlevel;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+
+	ASSERT(pipes);
+	if (!pipes)
+		return false;
+
+	// For each full update, remove all existing phantom pipes first
+	dc->res_pool->funcs->remove_phantom_pipes(dc, context);
+
+	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+
+	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
+
+	if (!pipe_cnt) {
+		out = true;
+		goto validate_out;
+	}
+
+	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
+
+	if (!fast_validate) {
+		dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
+	}
+
+	if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
+			vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
+		/*
+		 * If mode is unsupported or there's still no p-state support then
+		 * fall back to favoring voltage.
+		 *
+		 * We don't actually support prefetch mode 2, so require that we
+		 * at least support prefetch mode 1.
+		 */
+		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
+				dm_prefetch_support_stutter;
+
+		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+		if (vlevel < context->bw_ctx.dml.soc.num_states) {
+			memset(split, 0, MAX_PIPES * sizeof(int));
+			memset(merge, 0, MAX_PIPES * sizeof(bool));
+			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+		}
+	}
+
+	dml_log_mode_support_params(&context->bw_ctx.dml);
+
+	if (vlevel == context->bw_ctx.dml.soc.num_states)
+		goto validate_fail;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
+
+		if (!pipe->stream)
+			continue;
+
+		/* We only support full screen mpo with ODM */
+		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
+				&& pipe->plane_state && mpo_pipe
+				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
+						&pipe->plane_res.scl_data.recout,
+						sizeof(struct rect)) != 0) {
+			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
+			goto validate_fail;
+		}
+		pipe_idx++;
+	}
+
+	/* merge pipes if necessary */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		/*skip pipes that don't need merging*/
+		if (!merge[i])
+			continue;
+
+		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
+		if (pipe->prev_odm_pipe) {
+			/*split off odm pipe*/
+			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
+			if (pipe->next_odm_pipe)
+				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
+
+			pipe->bottom_pipe = NULL;
+			pipe->next_odm_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			pipe->top_pipe = NULL;
+			pipe->prev_odm_pipe = NULL;
+			if (pipe->stream_res.dsc)
+				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			repopulate_pipes = true;
+		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
+			struct pipe_ctx *top_pipe = pipe->top_pipe;
+			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
+
+			top_pipe->bottom_pipe = bottom_pipe;
+			if (bottom_pipe)
+				bottom_pipe->top_pipe = top_pipe;
+
+			pipe->top_pipe = NULL;
+			pipe->bottom_pipe = NULL;
+			pipe->plane_state = NULL;
+			pipe->stream = NULL;
+			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+			repopulate_pipes = true;
+		} else
+			ASSERT(0); /* Should never try to merge master pipe */
+
+	}
+
+	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *hsplit_pipe = NULL;
+		bool odm;
+		int old_index = -1;
+
+		if (!pipe->stream || newly_split[i])
+			continue;
+
+		pipe_idx++;
+		odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
+
+		if (!pipe->plane_state && !odm)
+			continue;
+
+		if (split[i]) {
+			if (odm) {
+				if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
+					old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+				else if (old_pipe->next_odm_pipe)
+					old_index = old_pipe->next_odm_pipe->pipe_idx;
+			} else {
+				if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+					old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+				else if (old_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+					old_index = old_pipe->bottom_pipe->pipe_idx;
+			}
+			hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(hsplit_pipe);
+			if (!hsplit_pipe)
+				goto validate_fail;
+
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					pipe, hsplit_pipe, odm))
+				goto validate_fail;
+
+			newly_split[hsplit_pipe->pipe_idx] = true;
+			repopulate_pipes = true;
+		}
+		if (split[i] == 4) {
+			struct pipe_ctx *pipe_4to1;
+
+			if (odm && old_pipe->next_odm_pipe)
+				old_index = old_pipe->next_odm_pipe->pipe_idx;
+			else if (!odm && old_pipe->bottom_pipe &&
+						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+				old_index = old_pipe->bottom_pipe->pipe_idx;
+			else
+				old_index = -1;
+			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(pipe_4to1);
+			if (!pipe_4to1)
+				goto validate_fail;
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					pipe, pipe_4to1, odm))
+				goto validate_fail;
+			newly_split[pipe_4to1->pipe_idx] = true;
+
+			if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
+					&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
+				old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+			else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
+					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+				old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+			else
+				old_index = -1;
+			pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+			ASSERT(pipe_4to1);
+			if (!pipe_4to1)
+				goto validate_fail;
+			if (!dcn32_split_stream_for_mpc_or_odm(
+					dc, &context->res_ctx,
+					hsplit_pipe, pipe_4to1, odm))
+				goto validate_fail;
+			newly_split[pipe_4to1->pipe_idx] = true;
+		}
+		if (odm)
+			dcn20_build_mapped_resource(dc, context, pipe->stream);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->plane_state) {
+			if (!resource_build_scaling_params(pipe))
+				goto validate_fail;
+		}
+	}
+
+	/* Actual dsc count per stream dsc validation*/
+	if (!dcn20_validate_dsc(dc, context)) {
+		vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
+		goto validate_fail;
+	}
+
+	if (repopulate_pipes)
+		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
+	*vlevel_out = vlevel;
+	*pipe_cnt_out = pipe_cnt;
+
+	out = true;
+	goto validate_out;
+
+validate_fail:
+	out = false;
+
+validate_out:
+	return out;
+}
+
+bool dcn32_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		bool fast_validate)
+{
+	bool out = false;
+
+	BW_VAL_TRACE_SETUP();
+
+	int vlevel = 0;
+	int pipe_cnt = 0;
+	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	BW_VAL_TRACE_COUNT();
+
+    DC_FP_START();
+	out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
+    DC_FP_END();
+
+	if (pipe_cnt == 0)
+		goto validate_out;
+
+	if (!out)
+		goto validate_fail;
+
+	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
+
+	if (fast_validate) {
+		BW_VAL_TRACE_SKIP(fast);
+		goto validate_out;
+	}
+
+	dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
+
+	BW_VAL_TRACE_END_WATERMARKS();
+
+	goto validate_out;
+
+validate_fail:
+	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
+		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
+
+	BW_VAL_TRACE_SKIP(fail);
+	out = false;
+
+validate_out:
+	kfree(pipes);
+
+	BW_VAL_TRACE_FINISH();
+
+	return out;
+}
+
+
+static bool is_dual_plane(enum surface_pixel_format format)
+{
+	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
+}
+
+int dcn32_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate)
+{
+	int i, pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe;
+
+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_crtc_timing *timing;
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+		pipe = &res_ctx->pipe_ctx[i];
+		timing = &pipe->stream->timing;
+
+		pipes[pipe_cnt].pipe.src.gpuvm = true;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
+		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
+		pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
+		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
+		pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
+
+		switch (pipe->stream->mall_stream_config.type) {
+		case SUBVP_MAIN:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
+			break;
+		case SUBVP_PHANTOM:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
+			pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_enable;
+			break;
+		case SUBVP_NONE:
+			pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
+			pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
+			break;
+		default:
+			break;
+		}
+
+		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+		if (pipes[pipe_cnt].dout.dsc_enable) {
+			switch (timing->display_color_depth) {
+			case COLOR_DEPTH_888:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
+				break;
+			case COLOR_DEPTH_101010:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
+				break;
+			case COLOR_DEPTH_121212:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
+				break;
+			default:
+				ASSERT(0);
+				break;
+			}
+		}
+		pipe_cnt++;
+	}
+
+	switch (pipe_cnt) {
+	case 1:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE;
+		if (pipe->plane_state && !dc->debug.disable_z9_mpc) {
+			if (!is_dual_plane(pipe->plane_state->format)) {
+				context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE;
+				pipes[0].pipe.src.unbounded_req_mode = true;
+				if (pipe->plane_state->src_rect.width >= 5120 &&
+					pipe->plane_state->src_rect.height >= 2880)
+					context->bw_ctx.dml.ip.det_buffer_size_kbytes = 320; // 5K or higher
+			}
+		}
+		break;
+	case 2:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 2; // 576 KB (9 segments)
+		break;
+	case 3:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_MAX_DET_SIZE / 3; // 384 KB (6 segments)
+		break;
+	case 4:
+	default:
+		context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE; // 256 KB (4 segments)
+		break;
+	}
+
+	return pipe_cnt;
+}
+
+void dcn32_calculate_wm_and_dlg_fp(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	int i, pipe_idx, vlevel_temp = 0;
+
+	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
+	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
+	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
+			dm_dram_clock_change_unsupported;
+
+	/* Set B:
+	 * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
+	 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
+	 * calculations to cover bootup clocks.
+	 * DCFCLK: soc.clock_limits[2] when available
+	 * UCLK: soc.clock_limits[2] when available
+	 */
+	if (dcn3_2_soc.num_states > 2) {
+		vlevel_temp = 2;
+		dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
+	} else
+		dcfclk = 615; //DCFCLK Vmin_lv
+
+	pipes[0].clks_cfg.voltage = vlevel_temp;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set D:
+	 * All clocks min.
+	 * DCFCLK: Min, as reported by PM FW when available
+	 * UCLK  : Min, as reported by PM FW when available
+	 * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
+	 */
+
+	if (dcn3_2_soc.num_states > 2) {
+		vlevel_temp = 0;
+		dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
+	} else
+		dcfclk = 615; //DCFCLK Vmin_lv
+
+	pipes[0].clks_cfg.voltage = vlevel_temp;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set C, for Dummy P-State:
+	 * All clocks min.
+	 * DCFCLK: Min, as reported by PM FW, when available
+	 * UCLK  : Min,  as reported by PM FW, when available
+	 * pstate latency as per UCLK state dummy pstate latency
+	 */
+
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
+		unsigned int min_dram_speed_mts_margin = 160;
+
+		if ((!pstate_en))
+			min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
+
+		/* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
+		for (i = 3; i > 0; i--)
+			if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
+				break;
+
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
+		context->bw_ctx.dml.soc.dummy_pstate_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
+		/* The only difference between A and C is p-state latency, if p-state is not supported
+		 * with full p-state latency we want to calculate DLG based on dummy p-state latency,
+		 * Set A p-state watermark set to 0 on DCN32, when p-state unsupported, for now keep as DCN32.
+		 */
+		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
+	} else {
+		/* Set A:
+		 * All clocks min.
+		 * DCFCLK: Min, as reported by PM FW, when available
+		 * UCLK: Min, as reported by PM FW, when available
+		 */
+		dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+		context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	}
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
+		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		if (dc->config.forced_clocks) {
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+		}
+		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
+		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+
+		pipe_idx++;
+	}
+
+	context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
+
+	dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
+
+	if (!pstate_en)
+		/* Restore full p-state latency */
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+				dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+
+static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+		unsigned int *optimal_dcfclk,
+		unsigned int *optimal_fclk)
+{
+	double bw_from_dram, bw_from_dram1, bw_from_dram2;
+
+	bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
+		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
+	bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
+		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
+
+	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
+
+	if (optimal_fclk)
+		*optimal_fclk = bw_from_dram /
+		(dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
+
+	if (optimal_dcfclk)
+		*optimal_dcfclk =  bw_from_dram /
+		(dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
+}
+
+void dcn32_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+    DC_FP_START();
+    dcn32_calculate_wm_and_dlg_fp(
+		dc, context,
+		pipes,
+		pipe_cnt,
+		vlevel);
+    DC_FP_END();
+}
+
+static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+		if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
+			return true;
+	}
+	return false;
+}
+
+void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes,
+		int pipe_cnt, int vlevel)
+{
+	int i, pipe_idx;
+	bool usr_retraining_support = false;
+
+	/* Writeback MCIF_WB arbitration parameters */
+	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
+
+	context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
+	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
+	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
+	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
+	context->bw_ctx.bw.dcn.clk.p_state_change_support =
+			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
+					!= dm_dram_clock_change_unsupported;
+
+	/*
+	 * TODO: needs FAMS
+	 * Pstate change might not be supported by hardware, but it might be
+	 * possible with firmware driven vertical blank stretching.
+	 */
+	// context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
+	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
+	context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
+	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
+		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
+	else
+		context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
+
+	usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+	ASSERT(usr_retraining_support);
+
+	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
+		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
+				pipe_idx);
+		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
+			context->res_ctx.pipe_ctx[i].unbounded_req = false;
+		} else {
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb =
+					context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+		}
+		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+		pipe_idx++;
+	}
+	/*save a original dppclock copy*/
+	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
+	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
+	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
+			* 1000;
+	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
+			* 1000;
+
+	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
+			- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
+				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
+				pipe_cnt, pipe_idx);
+
+		context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
+				&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		pipe_idx++;
+	}
+}
+
+/* dcn32_update_bw_bounding_box
+ * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
+ * with actual values as per dGPU SKU:
+ * -with passed few options from dc->config
+ * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
+ * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
+ * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
+ * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
+ * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
+ *  clocks (which might differ for certain dGPU SKU of the same ASIC)
+ */
+static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+
+		/* Overrides from dc->config options */
+		dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+
+		/* Override from passed dc->bb_overrides if available*/
+		if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+				&& dc->bb_overrides.sr_exit_time_ns) {
+			dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
+				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
+				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+			dcn3_2_soc.sr_enter_plus_exit_time_us =
+				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
+			&& dc->bb_overrides.urgent_latency_ns) {
+			dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
+				!= dc->bb_overrides.dram_clock_change_latency_ns
+				&& dc->bb_overrides.dram_clock_change_latency_ns) {
+			dcn3_2_soc.dram_clock_change_latency_us =
+				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
+				!= dc->bb_overrides.dummy_clock_change_latency_ns
+				&& dc->bb_overrides.dummy_clock_change_latency_ns) {
+			dcn3_2_soc.dummy_pstate_latency_us =
+				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
+		}
+
+		/* Override from VBIOS if VBIOS bb_info available */
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+			struct bp_soc_bb_info bb_info = {0};
+
+			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+				if (bb_info.dram_clock_change_latency_100ns > 0)
+					dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
+			}
+		}
+
+		/* Override from VBIOS for num_chan */
+		if (dc->ctx->dc_bios->vram_info.num_chans)
+			dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
+
+		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
+			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
+
+	}
+
+	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
+	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
+	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
+		unsigned int i = 0, j = 0, num_states = 0;
+
+		unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
+		unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
+
+		unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
+		unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
+		unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+		}
+		if (!max_dcfclk_mhz)
+			max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
+		if (!max_dispclk_mhz)
+			max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
+		if (!max_dppclk_mhz)
+			max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
+		if (!max_phyclk_mhz)
+			max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
+
+		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
+			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
+			num_dcfclk_sta_targets++;
+		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
+			for (i = 0; i < num_dcfclk_sta_targets; i++) {
+				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+					dcfclk_sta_targets[i] = max_dcfclk_mhz;
+					break;
+				}
+			}
+			// Update size of array since we "removed" duplicates
+			num_dcfclk_sta_targets = i + 1;
+		}
+
+		num_uclk_states = bw_params->clk_table.num_entries;
+
+		// Calculate optimal dcfclk for each uclk
+		for (i = 0; i < num_uclk_states; i++) {
+			dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
+					&optimal_dcfclk_for_uclk[i], NULL);
+			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
+				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
+			}
+		}
+
+		// Calculate optimal uclk for each dcfclk sta target
+		for (i = 0; i < num_dcfclk_sta_targets; i++) {
+			for (j = 0; j < num_uclk_states; j++) {
+				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
+					optimal_uclk_for_dcfclk_sta_targets[i] =
+							bw_params->clk_table.entries[j].memclk_mhz * 16;
+					break;
+				}
+			}
+		}
+
+		i = 0;
+		j = 0;
+		// create the final dcfclk and uclk table
+		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
+			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+			} else {
+				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+				} else {
+					j = num_uclk_states;
+				}
+			}
+		}
+
+		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
+			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+		}
+
+		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
+				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+		}
+
+		dcn3_2_soc.num_states = num_states;
+		for (i = 0; i < dcn3_2_soc.num_states; i++) {
+			dcn3_2_soc.clock_limits[i].state = i;
+			dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
+			dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
+
+			/* Fill all states with max values of all these clocks */
+			dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+			dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
+			dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
+			dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
+
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (i > 0) {
+				if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
+					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
+				} else {
+					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+				}
+			} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
+				dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+			}
+
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
+
+			if (!dram_speed_mts[i] && i > 0)
+				dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
+			else
+				dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
+			/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
+			/* PHYCLK_D18, PHYCLK_D32 */
+			dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
+			dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
+		}
+
+		/* Re-init DML with updated bb */
+		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+		if (dc->current_state)
+			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+	}
+}
+
+static struct resource_funcs dcn32_res_pool_funcs = {
+	.destroy = dcn32_destroy_resource_pool,
+	.link_enc_create = dcn32_link_encoder_create,
+	.link_enc_create_minimal = NULL,
+	.panel_cntl_create = dcn32_panel_cntl_create,
+	.validate_bandwidth = dcn32_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
+	.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn32_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
+	.add_phantom_pipes = dcn32_add_phantom_pipes,
+	.remove_phantom_pipes = dcn32_remove_phantom_pipes,
+};
+
+
+static bool dcn32_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn32_resource_pool *pool)
+{
+	int i, j;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
+	uint32_t pipe_fuses = 0;
+	uint32_t num_pipes  = 4;
+
+    DC_FP_START();
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn32;
+	/* max number of pipes for ASIC before checking for pipe fuses */
+	num_pipes  = pool->base.res_cap->num_timing_generator;
+	pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
+		if (pipe_fuses & 1 << i)
+			num_pipes--;
+
+	if (pipe_fuses & 1)
+		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
+
+	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
+		ASSERT(0); //Entire DCN is harvested!
+
+	/* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
+	 * value will be changed, update max_num_dpp and max_num_otg for dml.
+	 */
+	dcn3_2_ip.max_num_dpp = num_pipes;
+	dcn3_2_ip.max_num_otg = num_pipes;
+
+	pool->base.funcs = &dcn32_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.timing_generator_count = num_pipes;
+	pool->base.pipe_count = num_pipes;
+	pool->base.mpcc_count = num_pipes;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+	dc->caps.mall_size_per_mem_channel = 0;
+	dc->caps.mall_size_total = 0;
+	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
+
+	dc->caps.cache_line_size = 64;
+	dc->caps.cache_num_ways = 16;
+	dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
+	dc->caps.subvp_fw_processing_delay_us = 15;
+	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
+	dc->caps.subvp_pstate_allow_width_us = 20;
+	dc->caps.subvp_vertical_int_margin_us = 30;
+
+	dc->caps.max_slave_planes = 2;
+	dc->caps.max_slave_yuv_planes = 2;
+	dc->caps.max_slave_rgb_planes = 2;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.dp_hpo = true;
+	dc->caps.edp_dsc_support = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
+	// no OGAM ROM on DCN2 and later ASICs
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	/* Use pipe context based otg sync logic */
+	dc->config.use_pipe_ctx_sync_logic = true;
+
+	/* read VBIOS LTTPR caps */
+	{
+		if (ctx->dc_bios->funcs->get_lttpr_caps) {
+			enum bp_result bp_query_result;
+			uint8_t is_vbios_lttpr_enable = 0;
+
+			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
+			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
+		}
+
+		/* interop bit is implicit */
+		{
+			dc->caps.vbios_lttpr_aware = true;
+		}
+	}
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn32_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* DML */
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
+
+	/* IRQ Service */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn32_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs, TGs, ABMs */
+	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if (pipe_fuses & 1 << i)
+			continue;
+
+		/* HUBPs */
+		pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
+		if (pool->base.hubps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		/* DPPs */
+		pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
+		if (pool->base.dpps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+
+		/* OPPs */
+		pool->base.opps[j] = dcn32_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+
+		/* TGs */
+		pool->base.timing_generators[j] = dcn32_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+
+		/* ABMs */
+		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[j] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+
+		/* index for resource pool arrays for next valid pipe */
+		j++;
+	}
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* MPCCs */
+	pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	/* DSCs */
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB */
+	if (!dcn32_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	/* MMHUBBUB */
+	if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer init functions and Plane caps */
+	dcn32_hw_sequencer_init_functions(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->base.oem_device = NULL;
+	}
+
+    DC_FP_END();
+
+	return true;
+
+create_fail:
+
+    DC_FP_END();
+
+	dcn32_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn32_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn32_resource_pool *pool =
+		kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
new file mode 100644
index 000000000000..10b58f1c724a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN32_RESOURCE_H_
+#define _DCN32_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN32_RES_POOL(pool)\
+	container_of(pool, struct dcn32_resource_pool, base)
+
+struct dcn32_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn32_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+void dcn32_calculate_dlg_params(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+
+struct panel_cntl *dcn32_panel_cntl_create(
+		const struct panel_cntl_init_data *init_data);
+
+bool dcn32_acquire_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		int mpcc_id,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+bool dcn32_release_post_bldn_3dlut(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		struct dc_3dlut **lut,
+		struct dc_transfer_func **shaper);
+
+void dcn32_remove_phantom_pipes(struct dc *dc,
+		struct dc_state *context);
+
+void dcn32_add_phantom_pipes(struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		unsigned int pipe_cnt,
+		unsigned int index);
+
+bool dcn32_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		bool fast_validate);
+
+int dcn32_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate);
+
+void dcn32_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel);
+
+#endif /* _DCN32_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
new file mode 100644
index 000000000000..e554fd6c16f2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile
@@ -0,0 +1,42 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn321.
+
+DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn321/dcn321_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN321)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
new file mode 100644
index 000000000000..49682a31ecbd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn321_dio_link_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+static const struct link_encoder_funcs dcn321_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc32_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn32_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn10_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+	.set_dig_output_mode = enc32_set_dig_output_mode,
+};
+
+void dcn321_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_connector_speed_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn321_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	if (enc10->base.connector.id == CONNECTOR_ID_USBC)
+		enc10->base.features.flags.bits.DP_IS_USB_C = 1;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	if (bp_funcs->get_connector_speed_cap_info)
+		result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.connector, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
+		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
+		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
+		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h
new file mode 100644
index 000000000000..2205f39b0a24
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN321_H__
+#define __DC_LINK_ENCODER__DCN321_H__
+
+#include "dcn32/dcn32_dio_link_encoder.h"
+
+void dcn321_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+
+#endif /* __DC_LINK_ENCODER__DCN321_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
new file mode 100644
index 000000000000..48af91affb0c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -0,0 +1,2335 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn32/dcn32_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn32/dcn32_resource.h"
+#include "dcn321_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn32/dcn32_hubbub.h"
+#include "dcn32/dcn32_mpc.h"
+#include "dcn32/dcn32_hubp.h"
+#include "irq/dcn32/irq_service_dcn32.h"
+#include "dcn32/dcn32_dpp.h"
+#include "dcn32/dcn32_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn32/dcn32_dio_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
+#include "dcn31/dcn31_hpo_dp_link_encoder.h"
+#include "dcn32/dcn32_hpo_dp_link_encoder.h"
+#include "dc_link_dp.h"
+#include "dcn31/dcn31_apg.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dcn32/dcn32_dio_link_encoder.h"
+#include "dcn321_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dml/display_mode_vba.h"
+#include "dcn32/dcn32_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dc_link_ddc.h"
+#include "dcn31/dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn32/dcn32_mmhubbub.h"
+
+#include "dcn/dcn_3_2_1_offset.h"
+#include "dcn/dcn_3_2_1_sh_mask.h"
+#include "nbio/nbio_4_3_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+
+#define MAX_INSTANCE                                        8
+#define MAX_SEGMENT                                         6
+
+struct IP_BASE_INSTANCE {
+	unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE {
+	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } },
+					{ { 0, 0, 0, 0, 0, 0 } } } };
+
+#define DC_LOGGER_INIT(logger)
+#define fixed16_to_double(x) (((double)x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+#define DCN3_2_DEFAULT_DET_SIZE 256
+
+struct _vcs_dpi_ip_params_st dcn3_21_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 0,
+	.rob_buffer_size_kbytes = 128,
+	.det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1280,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 22,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.alpha_pixel_chunk_size_kbytes = 4, // not appearing in spreadsheet, match c code from hw team
+	.min_pixel_chunk_size_bytes = 1024,
+	.dcc_meta_buffer_size_bytes = 6272,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 4,
+	.maximum_dsc_bits_per_component = 12,
+	.maximum_pixels_per_line_per_dsc_unit = 6016,
+	.dsc422_native_support = true,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 57,
+	.line_buffer_size_bits = 1171920, //DPP doc, DCN3_2_DisplayMode_73.xlsm still shows as 986880 bits with 48 bpp
+	.max_line_buffer_lines = 32,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 47,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 28,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 125,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+	.max_num_dp2p0_outputs = 2,
+	.max_num_dp2p0_streams = 4,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
+	.clock_limits = {
+		{
+			.state = 0,
+			.dcfclk_mhz = 1564.0,
+			.fabricclk_mhz = 400.0,
+			.dispclk_mhz = 2150.0,
+			.dppclk_mhz = 2150.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.phyclk_d32_mhz = 625.0,
+			.socclk_mhz = 1200.0,
+			.dscclk_mhz = 716.667,
+			.dram_speed_mts = 1600.0,
+			.dtbclk_mhz = 1564.0,
+		},
+	},
+	.num_states = 1,
+	.sr_exit_time_us = 5.20,
+	.sr_enter_plus_exit_time_us = 9.60,
+	.sr_exit_z8_time_us = 285.0,
+	.sr_enter_plus_exit_z8_time_us = 320,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 263,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.fclk_change_latency_us = 20,
+	.usr_retraining_latency_us = 2,
+	.smn_latency_us = 2,
+	.mall_allocated_for_dcn_mbytes = 64,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 100.0,
+	.pct_ideal_fabric_bw_after_urgent = 67.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
+	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,
+	.max_avg_sdp_bw_use_normal_percent = 80.0,
+	.max_avg_fabric_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_strobe_percent = 50.0,
+	.max_avg_dram_bw_use_normal_percent = 15.0,
+	.num_chans = 8,
+	.dram_channel_width_bytes = 2,
+	.fabric_datapath_to_dcn_data_return_bytes = 64,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.dram_clock_change_latency_us = 400,
+	.dispclk_dppclk_vco_speed_mhz = 4300.0,
+	.do_urgent_latency_adjustment = true,
+	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+enum dcn321_clk_src_array_id {
+	DCN321_CLK_SRC_PLL0,
+	DCN321_CLK_SRC_PLL1,
+	DCN321_CLK_SRC_PLL2,
+	DCN321_CLK_SRC_PLL3,
+	DCN321_CLK_SRC_PLL4,
+	DCN321_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX0_ ## reg_name
+
+#define CTX ctx
+#define REG(reg_name) \
+	(DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN32_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define apg_regs(id)\
+[id] = {\
+	APG_DCN31_REG_LIST(id)\
+}
+
+static const struct dcn31_apg_registers apg_regs[] = {
+	apg_regs(0),
+	apg_regs(1),
+	apg_regs(2),
+	apg_regs(3)
+};
+
+static const struct dcn31_apg_shift apg_shift = {
+	DCN31_APG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_apg_mask apg_mask = {
+		DCN31_APG_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN32_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	/*DPCS_DCN31_REG_LIST(id),*/ \
+}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+//	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+//	DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define hpo_dp_stream_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
+}
+
+static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
+	hpo_dp_stream_encoder_reg_list(0),
+	hpo_dp_stream_encoder_reg_list(1),
+	hpo_dp_stream_encoder_reg_list(2),
+	hpo_dp_stream_encoder_reg_list(3),
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
+};
+
+
+#define hpo_dp_link_encoder_reg_list(id)\
+[id] = {\
+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
+	/*DCN3_1_RDPCSTX_REG_LIST(0),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(1),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(2),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(3),*/\
+	/*DCN3_1_RDPCSTX_REG_LIST(4)*/\
+}
+
+static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
+	hpo_dp_link_encoder_reg_list(0),
+	hpo_dp_link_encoder_reg_list(1),
+};
+
+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30_COMMON(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
+};
+
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN32(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2),
+	dsc_regsDCN20(3)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_MCM_REG_LIST_DCN32(0),
+		MPC_MCM_REG_LIST_DCN32(1),
+		MPC_MCM_REG_LIST_DCN32(2),
+		MPC_MCM_REG_LIST_DCN32(3),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
+
+static const struct dcn_optc_registers optc_regs[] = {
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN32(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN32(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN32(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN32(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN32()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN32(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN32(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN32_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN32_REG_LIST()
+};
+
+#define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN32_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn321 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_hpo_dp_stream_encoder = 4,
+	.num_hpo_dp_link_encoder = 2,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 4,
+	.num_dsc = 4,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = true,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = true,
+		}
+	},
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_dsc_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true,
+	.force_disable_subvp = true
+};
+
+
+static struct dce_aux *dcn321_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn321_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static struct clock_source *dcn321_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub2)
+		return NULL;
+
+	hubbub32_construct(hubbub2, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			ctx->dc->dml.ip.det_buffer_size_kbytes,
+			ctx->dc->dml.ip.pixel_chunk_size_kbytes,
+			ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub2->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub2->base;
+}
+
+static struct hubp *dcn321_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp32_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static void dcn321_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN30_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn321_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp3 =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp3)
+		return NULL;
+
+	if (dpp32_construct(dpp3, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp3->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp3);
+	return NULL;
+}
+
+static struct mpc *dcn321_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn32_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct output_pixel_processor *dcn321_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp2 =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp2) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp2, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp2->base;
+}
+
+
+static struct timing_generator *dcn321_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn32_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn321_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn321_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn321_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn321_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn321_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct apg *dcn321_apg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
+
+	if (!apg31)
+		return NULL;
+
+	apg31_construct(apg31, ctx, inst,
+			&apg_regs[inst],
+			&apg_shift,
+			&apg_mask);
+
+	return &apg31->base;
+}
+
+static struct stream_encoder *dcn321_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn321_vpg_create(ctx, vpg_inst);
+	afmt = dcn321_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt) {
+		kfree(enc1);
+		kfree(vpg);
+		kfree(afmt);
+		return NULL;
+	}
+
+	dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
+	struct vpg *vpg;
+	struct apg *apg;
+	uint32_t hpo_dp_inst;
+	uint32_t vpg_inst;
+	uint32_t apg_inst;
+
+	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
+
+	/* Mapping of VPG register blocks to HPO DP block instance:
+	 * VPG[6] -> HPO_DP[0]
+	 * VPG[7] -> HPO_DP[1]
+	 * VPG[8] -> HPO_DP[2]
+	 * VPG[9] -> HPO_DP[3]
+	 */
+	vpg_inst = hpo_dp_inst + 6;
+
+	/* Mapping of APG register blocks to HPO DP block instance:
+	 * APG[0] -> HPO_DP[0]
+	 * APG[1] -> HPO_DP[1]
+	 * APG[2] -> HPO_DP[2]
+	 * APG[3] -> HPO_DP[3]
+	 */
+	apg_inst = hpo_dp_inst;
+
+	/* allocate HPO stream encoder and create VPG sub-block */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
+	vpg = dcn321_vpg_create(ctx, vpg_inst);
+	apg = dcn321_apg_create(ctx, apg_inst);
+
+	if (!hpo_dp_enc31 || !vpg || !apg) {
+		kfree(hpo_dp_enc31);
+		kfree(vpg);
+		kfree(apg);
+		return NULL;
+	}
+
+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
+					hpo_dp_inst, eng_id, vpg, apg,
+					&hpo_dp_stream_enc_regs[hpo_dp_inst],
+					&hpo_dp_se_shift, &hpo_dp_se_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
+	uint8_t inst,
+	struct dc_context *ctx)
+{
+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
+
+	/* allocate HPO link encoder */
+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
+
+	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
+					&hpo_dp_link_enc_regs[inst],
+					&hpo_dp_le_shift, &hpo_dp_le_mask);
+
+	return &hpo_dp_enc31->base;
+}
+
+static struct dce_hwseq *dcn321_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn321_create_audio,
+	.create_stream_encoder = dcn321_stream_encoder_create,
+	.create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn321_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
+	.create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
+	.create_hwseq = dcn321_hwseq_create,
+};
+
+static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
+		if (pool->base.hpo_dp_stream_enc[i] != NULL) {
+			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
+				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
+				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
+				pool->base.hpo_dp_stream_enc[i]->apg = NULL;
+			}
+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
+			pool->base.hpo_dp_stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
+		if (pool->base.hpo_dp_link_enc[i] != NULL) {
+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
+			pool->base.hpo_dp_link_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn321_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL)
+			dal_irq_service_destroy(&pool->base.irqs);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.oem_device != NULL)
+		dal_ddc_service_destroy(&pool->base.oem_device);
+}
+
+
+static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn32_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn321_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+
+	dsc->max_image_width = 6016;
+
+	return &dsc->base;
+}
+
+static void dcn321_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
+
+	dcn321_resource_destruct(dcn321_pool);
+	kfree(dcn321_pool);
+	*pool = NULL;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+
+static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+		unsigned int *optimal_dcfclk,
+		unsigned int *optimal_fclk)
+{
+	double bw_from_dram, bw_from_dram1, bw_from_dram2;
+
+	bw_from_dram1 = uclk_mts * dcn3_21_soc.num_chans *
+		dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100);
+	bw_from_dram2 = uclk_mts * dcn3_21_soc.num_chans *
+		dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100);
+
+	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
+
+	if (optimal_fclk)
+		*optimal_fclk = bw_from_dram /
+		(dcn3_21_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
+
+	if (optimal_dcfclk)
+		*optimal_dcfclk =  bw_from_dram /
+		(dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
+}
+
+/* dcn321_update_bw_bounding_box
+ * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
+ * with actual values as per dGPU SKU:
+ * -with passed few options from dc->config
+ * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)
+ * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes
+ * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU
+ * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)
+ * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different
+ *  clocks (which might differ for certain dGPU SKU of the same ASIC)
+ */
+static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		/* Overrides from dc->config options */
+		dcn3_21_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+
+		/* Override from passed dc->bb_overrides if available*/
+		if ((int)(dcn3_21_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+				&& dc->bb_overrides.sr_exit_time_ns) {
+			dcn3_21_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.sr_enter_plus_exit_time_us * 1000)
+				!= dc->bb_overrides.sr_enter_plus_exit_time_ns
+				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+			dcn3_21_soc.sr_enter_plus_exit_time_us =
+				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
+			&& dc->bb_overrides.urgent_latency_ns) {
+			dcn3_21_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000)
+				!= dc->bb_overrides.dram_clock_change_latency_ns
+				&& dc->bb_overrides.dram_clock_change_latency_ns) {
+			dcn3_21_soc.dram_clock_change_latency_us =
+				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
+		}
+
+		if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000)
+				!= dc->bb_overrides.dummy_clock_change_latency_ns
+				&& dc->bb_overrides.dummy_clock_change_latency_ns) {
+			dcn3_21_soc.dummy_pstate_latency_us =
+				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
+		}
+
+		/* Override from VBIOS if VBIOS bb_info available */
+		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+			struct bp_soc_bb_info bb_info = {0};
+
+			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+				if (bb_info.dram_clock_change_latency_100ns > 0)
+					dcn3_21_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
+
+			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+				dcn3_21_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+			if (bb_info.dram_sr_exit_latency_100ns > 0)
+				dcn3_21_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
+			}
+		}
+
+		/* Override from VBIOS for num_chan */
+		if (dc->ctx->dc_bios->vram_info.num_chans)
+			dcn3_21_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
+
+		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
+			dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
+
+	}
+
+	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
+	dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
+	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
+		unsigned int i = 0, j = 0, num_states = 0;
+
+		unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
+		unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
+		unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
+
+		unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
+		unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
+		unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+		}
+		if (!max_dcfclk_mhz)
+			max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
+		if (!max_dispclk_mhz)
+			max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
+		if (!max_dppclk_mhz)
+			max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
+		if (!max_phyclk_mhz)
+			max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
+
+		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
+			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
+			num_dcfclk_sta_targets++;
+		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
+			for (i = 0; i < num_dcfclk_sta_targets; i++) {
+				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+					dcfclk_sta_targets[i] = max_dcfclk_mhz;
+					break;
+				}
+			}
+			// Update size of array since we "removed" duplicates
+			num_dcfclk_sta_targets = i + 1;
+		}
+
+		num_uclk_states = bw_params->clk_table.num_entries;
+
+		// Calculate optimal dcfclk for each uclk
+		for (i = 0; i < num_uclk_states; i++) {
+			dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
+					&optimal_dcfclk_for_uclk[i], NULL);
+			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
+				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
+			}
+		}
+
+		// Calculate optimal uclk for each dcfclk sta target
+		for (i = 0; i < num_dcfclk_sta_targets; i++) {
+			for (j = 0; j < num_uclk_states; j++) {
+				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
+					optimal_uclk_for_dcfclk_sta_targets[i] =
+							bw_params->clk_table.entries[j].memclk_mhz * 16;
+					break;
+				}
+			}
+		}
+
+		i = 0;
+		j = 0;
+		// create the final dcfclk and uclk table
+		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
+			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
+				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+			} else {
+				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+				} else {
+					j = num_uclk_states;
+				}
+			}
+		}
+
+		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
+			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
+			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
+		}
+
+		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
+				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
+			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
+			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
+		}
+
+		dcn3_21_soc.num_states = num_states;
+		for (i = 0; i < dcn3_21_soc.num_states; i++) {
+			dcn3_21_soc.clock_limits[i].state = i;
+			dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
+			dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
+
+			/* Fill all states with max values of all these clocks */
+			dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+			dcn3_21_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
+			dcn3_21_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
+			dcn3_21_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
+
+			/* Populate from bw_params for DTBCLK, SOCCLK */
+			if (i > 0) {
+				if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
+					dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
+				} else {
+					dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
+				}
+			} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
+				dcn3_21_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
+			}
+
+			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
+				dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
+			else
+				dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
+
+			if (!dram_speed_mts[i] && i > 0)
+				dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
+			else
+				dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
+
+			/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
+			/* PHYCLK_D18, PHYCLK_D32 */
+			dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
+			dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
+		}
+
+		/* Re-init DML with updated bb */
+		dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+		if (dc->current_state)
+			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+	}
+}
+
+static struct resource_funcs dcn321_res_pool_funcs = {
+	.destroy = dcn321_destroy_resource_pool,
+	.link_enc_create = dcn321_link_encoder_create,
+	.link_enc_create_minimal = NULL,
+	.panel_cntl_create = dcn32_panel_cntl_create,
+	.validate_bandwidth = dcn32_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
+	.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn321_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
+	.add_phantom_pipes = dcn32_add_phantom_pipes,
+	.remove_phantom_pipes = dcn32_remove_phantom_pipes,
+};
+
+
+static bool dcn321_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn321_resource_pool *pool)
+{
+	int i, j;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data = {0};
+	uint32_t pipe_fuses = 0;
+	uint32_t num_pipes  = 4;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn321;
+	/* max number of pipes for ASIC before checking for pipe fuses */
+	num_pipes  = pool->base.res_cap->num_timing_generator;
+	pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
+		if (pipe_fuses & 1 << i)
+			num_pipes--;
+
+	if (pipe_fuses & 1)
+		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
+
+	if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
+		ASSERT(0); //Entire DCN is harvested!
+
+	/* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
+	 * value will be changed, update max_num_dpp and max_num_otg for dml.
+	 */
+	dcn3_21_ip.max_num_dpp = num_pipes;
+	dcn3_21_ip.max_num_otg = num_pipes;
+
+	pool->base.funcs = &dcn321_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.timing_generator_count = num_pipes;
+	pool->base.pipe_count = num_pipes;
+	pool->base.mpcc_count = num_pipes;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+	dc->caps.mall_size_per_mem_channel = 0;
+	dc->caps.mall_size_total = 0;
+	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
+	dc->caps.cache_line_size = 64;
+	dc->caps.cache_num_ways = 16;
+	dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
+	dc->caps.subvp_fw_processing_delay_us = 15;
+	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
+	dc->caps.subvp_pstate_allow_width_us = 20;
+
+	dc->caps.max_slave_planes = 1;
+	dc->caps.max_slave_yuv_planes = 1;
+	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.dp_hpo = true;
+	dc->caps.edp_dsc_support = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 0; //3DLUT removed from DPP
+	dc->caps.color.dpp.ogam_ram = 0;  //Blnd Gam also removed
+	// no OGAM ROM on DCN2 and later ASICs
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	/* read VBIOS LTTPR caps */
+	{
+		if (ctx->dc_bios->funcs->get_lttpr_caps) {
+			enum bp_result bp_query_result;
+			uint8_t is_vbios_lttpr_enable = 0;
+
+			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
+			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
+		}
+
+		/* interop bit is implicit */
+		{
+			dc->caps.vbios_lttpr_aware = true;
+		}
+	}
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn321_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* DML */
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
+
+	/* IRQ Service */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn321_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs, TGs, ABMs */
+	for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if (pipe_fuses & 1 << i)
+			continue;
+
+		pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
+		if (pool->base.hubps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
+		if (pool->base.dpps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+
+		pool->base.opps[j] = dcn321_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+
+		pool->base.timing_generators[j] = dcn321_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+
+		pool->base.multiple_abms[j] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[j] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+
+		/* index for resource pool arrays for next valid pipe */
+		j++;
+	}
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* MPCCs */
+	pool->base.mpc = dcn321_mpc_create(ctx,  pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	/* DSCs */
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB */
+	if (!dcn321_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	/* MMHUBBUB */
+	if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer init functions and Plane caps */
+	dcn32_hw_sequencer_init_functions(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->base.oem_device = NULL;
+	}
+
+	return true;
+
+create_fail:
+
+	dcn321_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn321_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn321_resource_pool *pool =
+		kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h
new file mode 100644
index 000000000000..2732085a0e88
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN321_RESOURCE_H_
+#define _DCN321_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN321_RES_POOL(pool)\
+	container_of(pool, struct dcn321_resource_pool, base)
+
+struct dcn321_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn321_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN321_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index a64b88ca01a9..c48688cdd7f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags)
@@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o  := $(dml_rcflags)
@@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
 DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
 DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
+DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o
 DML += dcn31/dcn31_fpu.o
 DML += dcn301/dcn301_fpu.o
 DML += dcn302/dcn302_fpu.o
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
index 2a1983324629..74e86732e301 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
@@ -29,7 +29,7 @@
 #define DC__PRESENT 1
 #define DC__PRESENT__1 1
 #define DC__NUM_DPP 4
-#define DC__VOLTAGE_STATES 9
+#define DC__VOLTAGE_STATES 20
 #define DC__NUM_DPP__4 1
 #define DC__NUM_DPP__0_PRESENT 1
 #define DC__NUM_DPP__1_PRESENT 1
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index f79dd40f8d81..e247b2270b1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -811,9 +811,14 @@ void dcn20_calculate_dlg_params(
 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-		context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
-		context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
-
+		if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
+			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
+			context->res_ctx.pipe_ctx[i].unbounded_req = false;
+		} else {
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+		}
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@@ -1013,6 +1018,8 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
 		pipes[pipe_cnt].dout.dp_lanes = 4;
+		if (res_ctx->pipe_ctx[i].stream->link)
+			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
 		pipes[pipe_cnt].dout.is_virtual = 0;
 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
@@ -1070,6 +1077,7 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].dout.is_virtual = 1;
 			pipes[pipe_cnt].dout.output_type = dm_dp;
 			pipes[pipe_cnt].dout.dp_lanes = 4;
+			pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2;
 		}
 
 		switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
@@ -1138,7 +1146,8 @@ int dcn20_populate_dml_pipes_from_context(
 		 * bw calculations due to cursor on/off
 		 */
 		if (res_ctx->pipe_ctx[i].plane_state &&
-				res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+				(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||
+				 res_ctx->pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM))
 			pipes[pipe_cnt].pipe.src.num_cursors = 0;
 		else
 			pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
@@ -1149,6 +1158,7 @@ int dcn20_populate_dml_pipes_from_context(
 		if (!res_ctx->pipe_ctx[i].plane_state) {
 			pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
 			pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
+			pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
 			pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
 			pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
 			pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
@@ -1201,8 +1211,26 @@ int dcn20_populate_dml_pipes_from_context(
 
 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
+			switch (pln->rotation) {
+			case ROTATION_ANGLE_0:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_0;
+				break;
+			case ROTATION_ANGLE_90:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_90;
+				break;
+			case ROTATION_ANGLE_180:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_180;
+				break;
+			case ROTATION_ANGLE_270:
+				pipes[pipe_cnt].pipe.src.source_rotation = dm_rotation_270;
+				break;
+			default:
+				break;
+			}
 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
 			pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
+			pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x;
+			pipes[pipe_cnt].pipe.src.viewport_x_c = scl->viewport_c.x;
 			pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
@@ -1428,21 +1456,20 @@ void dcn20_calculate_wm(
 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
 {
-	struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
-	int i;
 	int num_calculated_states = 0;
 	int min_dcfclk = 0;
+	int i;
 
 	dc_assert_fp_enabled();
 
 	if (num_states == 0)
 		return;
 
-	memset(calculated_states, 0, sizeof(calculated_states));
+	memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
 
-	if (dc->bb_overrides.min_dcfclk_mhz > 0)
+	if (dc->bb_overrides.min_dcfclk_mhz > 0) {
 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
-	else {
+	} else {
 		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
 			min_dcfclk = 310;
 		else
@@ -1453,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 
 	for (i = 0; i < num_states; i++) {
 		int min_fclk_required_by_uclk;
-		calculated_states[i].state = i;
-		calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
+		bb->clock_limits[i].state = i;
+		bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
 
 		// FCLK:UCLK ratio is 1.08
 		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
 			1000000);
 
-		calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
+		bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
 				min_dcfclk : min_fclk_required_by_uclk;
 
-		calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
-				max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+		bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+				max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-		calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
-				max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+		bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+				max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-		calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
-		calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
-		calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
+		bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
+		bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
+		bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
 
-		calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
+		bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
 
 		num_calculated_states++;
 	}
 
-	calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
-	calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
-	calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
+	bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
 
-	memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
 	bb->num_states = num_calculated_states;
 
 	// Duplicate the last state, DML always an extra state identical to max state to work
@@ -1978,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 {
 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl = 0, k = 0;
 	int j;
 
@@ -1990,9 +2015,8 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 
 	ASSERT(clk_table->num_entries);
 	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
-	for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
-		clock_limits[i] = dcn2_1_soc.clock_limits[i];
-	}
+	memcpy(&dcn2_1_soc._clock_tmp, &dcn2_1_soc.clock_limits,
+	       sizeof(dcn2_1_soc.clock_limits));
 
 	for (i = 0; i < clk_table->num_entries; i++) {
 		/* loop backwards*/
@@ -2007,24 +2031,26 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 		if (i == 1)
 			k++;
 
-		clock_limits[k].state = k;
-		clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-		clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-		clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
-		clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+		dcn2_1_soc._clock_tmp[k].state = k;
+		dcn2_1_soc._clock_tmp[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+		dcn2_1_soc._clock_tmp[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+		dcn2_1_soc._clock_tmp[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
 
-		clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-		clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-		clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-		clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-		clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-		clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-		clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+		dcn2_1_soc._clock_tmp[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+		dcn2_1_soc._clock_tmp[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+		dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+		dcn2_1_soc._clock_tmp[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 
 		k++;
 	}
-	for (i = 0; i < clk_table->num_entries + 1; i++)
-		dcn2_1_soc.clock_limits[i] = clock_limits[i];
+
+	memcpy(&dcn2_1_soc.clock_limits, &dcn2_1_soc._clock_tmp,
+	       sizeof(dcn2_1_soc.clock_limits));
+
 	if (clk_table->num_entries) {
 		dcn2_1_soc.num_states = clk_table->num_entries + 1;
 		/* fill in min DF PState */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index f47d82da115c..fb4aa4c800bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -438,8 +438,8 @@ static void UseMinimumDCFCLK(
 		int dpte_group_bytes[],
 		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
 		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
-		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
-		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
 		int BytePerPixelY[],
 		int BytePerPixelC[],
 		int HTotal[],
@@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK(
 		int dpte_group_bytes[],
 		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
 		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
-		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
-		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
 		int BytePerPixelY[],
 		int BytePerPixelC[],
 		int HTotal[],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 0a7a33864973..e4863f0bf0f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -249,12 +249,14 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 {
 	struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int j;
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_01_soc._clock_tmp, &dcn3_01_soc.clock_limits,
+	       sizeof(dcn3_01_soc.clock_limits));
+
 	/* Default clock levels are used for diags, which may lead to overclocking. */
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 		dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
@@ -271,32 +273,32 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				}
 			}
 
-			clock_limits[i].state = i;
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
-
-			clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-			clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_01_soc._clock_tmp[i].state = i;
+			dcn3_01_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_01_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_01_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+
+			dcn3_01_soc._clock_tmp[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_01_soc._clock_tmp[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_01_soc._clock_tmp[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_01_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_01_soc._clock_tmp[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
 
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_01_soc.clock_limits[i] = clock_limits[i];
-
 		if (clk_table->num_entries) {
 			dcn3_01_soc.num_states = clk_table->num_entries;
 			/* duplicate last level */
-			dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
-			dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
+			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
+			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
 		}
 	}
 
+	memcpy(&dcn3_01_soc.clock_limits, &dcn3_01_soc._clock_tmp,
+	       sizeof(dcn3_01_soc.clock_limits));
+
 	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 54db2eca9e6b..7be3476989ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -201,7 +201,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
 	.hostvm_max_page_table_levels = 2,
 	.rob_buffer_size_kbytes = 64,
 	.det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
-	.min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB,
+	.min_comp_buffer_size_kbytes = 64,
 	.config_return_buffer_size_in_kbytes = 1024,
 	.compressed_buffer_segment_size_in_kbytes = 64,
 	.meta_fifo_size_in_kentries = 32,
@@ -297,6 +297,7 @@ struct _vcs_dpi_ip_params_st dcn3_16_ip = {
 	.hostvm_max_page_table_levels = 2,
 	.rob_buffer_size_kbytes = 64,
 	.det_buffer_size_kbytes = DCN3_16_DEFAULT_DET_SIZE,
+	.min_comp_buffer_size_kbytes = 64,
 	.config_return_buffer_size_in_kbytes = 1024,
 	.compressed_buffer_segment_size_in_kbytes = 64,
 	.meta_fifo_size_in_kentries = 32,
@@ -574,12 +575,14 @@ void dcn31_calculate_wm_and_dlg_fp(
 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int j;
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits,
+	       sizeof(dcn3_1_soc.clock_limits));
+
 	// Default clock levels are used for diags, which may lead to overclocking.
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 		int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
@@ -607,34 +610,35 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 				}
 			}
 
-			clock_limits[i].state = i;
+			dcn3_1_soc._clock_tmp[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_1_soc.clock_limits[i] = clock_limits[i];
 		if (clk_table->num_entries) {
 			dcn3_1_soc.num_states = clk_table->num_entries;
 		}
 	}
 
+	memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp,
+	       sizeof(dcn3_1_soc.clock_limits));
+
 	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
 
@@ -701,13 +705,15 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
-	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
 	unsigned int i, closest_clk_lvl;
 	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
 	int j;
 
 	dc_assert_fp_enabled();
 
+	memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits,
+	       sizeof(dcn3_16_soc.clock_limits));
+
 	// Default clock levels are used for diags, which may lead to overclocking.
 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 
@@ -739,39 +745,40 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 				closest_clk_lvl = dcn3_16_soc.num_states - 1;
 			}
 
-			clock_limits[i].state = i;
+			dcn3_16_soc._clock_tmp[i].state = i;
 
 			/* Clocks dependent on voltage level. */
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 			if (clk_table->num_entries == 1 &&
-				clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
+			    dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
 				/*SMU fix not released yet*/
-				clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
+				dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
 			}
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+			dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
 
 			/* Clocks independent of voltage level. */
-			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+			dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
 
-			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+			dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
 				dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
 
-			clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
 		}
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn3_16_soc.clock_limits[i] = clock_limits[i];
 		if (clk_table->num_entries) {
 			dcn3_16_soc.num_states = clk_table->num_entries;
 		}
 	}
 
+	memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp,
+	       sizeof(dcn3_16_soc.clock_limits));
+
 	if (max_dispclk_mhz) {
 		dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
 		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index e4b9fd31223c..448fbbcdf88a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				v->ImmediateFlipSupported)) ? true : false;
 #ifdef __DML_VBA_DEBUG__
 		dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
-		dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required);
 		dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
 		dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
 		dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
index 53d760e169e6..dd570689c095 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -1055,7 +1055,6 @@ static void dml_rq_dlg_get_dlg_params(
 
 	float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
 	float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
-	int blank_lines;
 
 	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
 	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
@@ -1079,20 +1078,9 @@ static void dml_rq_dlg_get_dlg_params(
 	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
 
 	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
-
 	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
-	blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1);
-	if (blank_lines < 0)
-		blank_lines = 0;
-	if (blank_lines != 0) {
-		disp_dlg_regs->optimized_min_dst_y_next_start_us =
-			((unsigned int) blank_lines * dst->hactive) / (unsigned int) dst->pixel_rate_mhz;
-		disp_dlg_regs->optimized_min_dst_y_next_start =
-			(unsigned int)(((double) (dlg_vblank_start + blank_lines)) * dml_pow(2, 2));
-	} else {
-		// use unoptimized value
-		disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
-	}
+	disp_dlg_regs->optimized_min_dst_y_next_start_us = 0;
+	disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
 	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
 
 	dml_print("DML_DLG: %s: min_ttu_vblank (us)         = %3.2f\n", __func__, min_ttu_vblank);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
new file mode 100644
index 000000000000..7f144adb1e36
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -0,0 +1,3824 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc.h"
+#include "dc_link.h"
+#include "../display_mode_lib.h"
+#include "display_mode_vba_32.h"
+#include "../dml_inline_defs.h"
+#include "display_mode_vba_util_32.h"
+
+static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
+
+void dml32_recalculate(struct display_mode_lib *mode_lib);
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+		struct display_mode_lib *mode_lib);
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+
+void dml32_recalculate(struct display_mode_lib *mode_lib)
+{
+	ModeSupportAndSystemConfiguration(mode_lib);
+
+	dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte,
+			mode_lib->vba.ROBBufferSizeInKByte,
+			DC__NUM_DPP,
+			false, //mode_lib->vba.override_setting.nomDETInKByteOverrideEnable,
+			0, //mode_lib->vba.override_setting.nomDETInKByteOverrideValue,
+
+			/* Output */
+			&mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte,
+			&mode_lib->vba.MinCompressedBufferSizeInKByte);
+
+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__);
+#endif
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
+}
+
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+		struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int j, k;
+	bool ImmediateFlipRequirementFinal;
+	int iteration;
+	double MaxTotalRDBandwidth;
+	unsigned int NextPrefetchMode;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- START ---\n", __func__);
+	dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba.PrefetchMode);
+	dml_print("DML::%s: mode_lib->vba.ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport);
+	dml_print("DML::%s: mode_lib->vba.VoltageLevel = %d\n", __func__, mode_lib->vba.VoltageLevel);
+#endif
+
+	v->WritebackDISPCLK = 0.0;
+	v->GlobalDPPCLK = 0.0;
+
+	// DISPCLK and DPPCLK Calculation
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.WritebackEnable[k]) {
+			v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
+					dml32_CalculateWriteBackDISPCLK(
+							mode_lib->vba.WritebackPixelFormat[k],
+							mode_lib->vba.PixelClock[k], mode_lib->vba.WritebackHRatio[k],
+							mode_lib->vba.WritebackVRatio[k],
+							mode_lib->vba.WritebackHTaps[k],
+							mode_lib->vba.WritebackVTaps[k],
+							mode_lib->vba.WritebackSourceWidth[k],
+							mode_lib->vba.WritebackDestinationWidth[k],
+							mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize,
+							mode_lib->vba.DISPCLKDPPCLKVCOSpeed));
+		}
+	}
+
+	v->DISPCLK_calculated = v->WritebackDISPCLK;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated,
+					dml32_CalculateRequiredDispclk(
+							mode_lib->vba.ODMCombineEnabled[k],
+							mode_lib->vba.PixelClock[k],
+							mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+							mode_lib->vba.DISPCLKRampingMargin,
+							mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+							mode_lib->vba.MaxDppclk[v->soc.num_states - 1]));
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k],
+				mode_lib->vba.HRatioChroma[k],
+				mode_lib->vba.VRatio[k],
+				mode_lib->vba.VRatioChroma[k],
+				mode_lib->vba.MaxDCHUBToPSCLThroughput,
+				mode_lib->vba.MaxPSCLToLBThroughput,
+				mode_lib->vba.PixelClock[k],
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.htaps[k],
+				mode_lib->vba.HTAPsChroma[k],
+				mode_lib->vba.vtaps[k],
+				mode_lib->vba.VTAPsChroma[k],
+
+				/* Output */
+				&v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k],
+				&v->DPPCLKUsingSingleDPP[k]);
+	}
+
+	dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces, mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed, v->DPPCLKUsingSingleDPP, mode_lib->vba.DPPPerPlane,
+			/* Output */
+			&v->GlobalDPPCLK, v->DPPCLK);
+
+	for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
+		v->DPPCLK_calculated[k] = v->DPPCLK[k];
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateBytePerPixelAndBlockSizes(
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.SurfaceTiling[k],
+
+				/* Output */
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelDETY[k],
+				&v->BytePerPixelDETC[k],
+				&v->BlockHeight256BytesY[k],
+				&v->BlockHeight256BytesC[k],
+				&v->BlockWidth256BytesY[k],
+				&v->BlockWidth256BytesC[k],
+				&v->BlockHeightY[k],
+				&v->BlockHeightC[k],
+				&v->BlockWidthY[k],
+				&v->BlockWidthC[k]);
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: %d\n", __func__, __LINE__);
+#endif
+	dml32_CalculateSwathWidth(
+			false,  // ForceSingleDPP
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.SourcePixelFormat,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.ODMCombineEnabled,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BlockHeight256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesY,
+			v->BlockWidth256BytesC,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.HActive,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.DPPPerPlane,
+
+			/* Output */
+			v->SwathWidthSingleDPPY, v->SwathWidthSingleDPPC, v->SwathWidthY, v->SwathWidthC,
+			v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_integer_array[0], // Integer             MaximumSwathHeightY[]
+			v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_integer_array[1], // Integer             MaximumSwathHeightC[]
+			v->swath_width_luma_ub, v->swath_width_chroma_ub);
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+		v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
+				* mode_lib->vba.VRatioChroma[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: ReadBandwidthSurfaceLuma[%i] = %fBps\n",
+				__func__, k, v->ReadBandwidthSurfaceLuma[k]);
+		dml_print("DML::%s: ReadBandwidthSurfaceChroma[%i] = %fBps\n",
+				__func__, k, v->ReadBandwidthSurfaceChroma[k]);
+#endif
+	}
+
+	{
+		// VBA_DELTA
+		// Calculate DET size, swath height
+		dml32_CalculateSwathAndDETConfiguration(
+				mode_lib->vba.DETSizeOverride,
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.ConfigReturnBufferSizeInKByte,
+				mode_lib->vba.MaxTotalDETInKByte,
+				mode_lib->vba.MinCompressedBufferSizeInKByte,
+				false, /* ForceSingleDPP */
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.nomDETInKByte,
+				mode_lib->vba.UseUnboundedRequesting,
+				mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_output_encoder_array, /* output_encoder_class Output[] */
+				v->ReadBandwidthSurfaceLuma,
+				v->ReadBandwidthSurfaceChroma,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_single_array[0], /* Single MaximumSwathWidthLuma[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_single_array[1], /* Single MaximumSwathWidthChroma[] */
+				mode_lib->vba.SourceRotation,
+				mode_lib->vba.ViewportStationary,
+				mode_lib->vba.SourcePixelFormat,
+				mode_lib->vba.SurfaceTiling,
+				mode_lib->vba.ViewportWidth,
+				mode_lib->vba.ViewportHeight,
+				mode_lib->vba.ViewportXStartY,
+				mode_lib->vba.ViewportYStartY,
+				mode_lib->vba.ViewportXStartC,
+				mode_lib->vba.ViewportYStartC,
+				mode_lib->vba.SurfaceWidthY,
+				mode_lib->vba.SurfaceWidthC,
+				mode_lib->vba.SurfaceHeightY,
+				mode_lib->vba.SurfaceHeightC,
+				v->BlockHeight256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidth256BytesY,
+				v->BlockWidth256BytesC,
+				mode_lib->vba.ODMCombineEnabled,
+				mode_lib->vba.BlendingAndTiming,
+				v->BytePerPixelY,
+				v->BytePerPixelC,
+				v->BytePerPixelDETY,
+				v->BytePerPixelDETC,
+				mode_lib->vba.HActive,
+				mode_lib->vba.HRatio,
+				mode_lib->vba.HRatioChroma,
+				mode_lib->vba.DPPPerPlane,
+
+				/* Output */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_long_array[0], /* Long swath_width_luma_ub[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_long_array[1], /* Long swath_width_chroma_ub[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_double_array[0], /* Long SwathWidth[] */
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_double_array[1], /* Long SwathWidthChroma[] */
+				mode_lib->vba.SwathHeightY,
+				mode_lib->vba.SwathHeightC,
+				mode_lib->vba.DETBufferSizeInKByte,
+				mode_lib->vba.DETBufferSizeY,
+				mode_lib->vba.DETBufferSizeC,
+				&v->UnboundedRequestEnabled,
+				&v->CompressedBufferSizeInkByte,
+				v->dummy_vars
+					.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					.dummy_boolean_array, /* bool ViewportSizeSupportPerSurface[] */
+				&v->dummy_vars
+					 .DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+					 .dummy_boolean); /* bool *ViewportSizeSupport */
+	}
+
+	// DCFCLK Deep Sleep
+	dml32_CalculateDCFCLKDeepSleep(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			mode_lib->vba.DPPCLK,
+			v->ReadBandwidthSurfaceLuma,
+			v->ReadBandwidthSurfaceChroma,
+			mode_lib->vba.ReturnBusWidth,
+
+			/* Output */
+			&v->DCFCLKDeepSleep);
+
+	// DSCCLK
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
+			v->DSCCLK_calculated[k] = 0.0;
+		} else {
+			if (mode_lib->vba.OutputFormat[k] == dm_420)
+				mode_lib->vba.DSCFormatFactor = 2;
+			else if (mode_lib->vba.OutputFormat[k] == dm_444)
+				mode_lib->vba.DSCFormatFactor = 1;
+			else if (mode_lib->vba.OutputFormat[k] == dm_n422)
+				mode_lib->vba.DSCFormatFactor = 2;
+			else
+				mode_lib->vba.DSCFormatFactor = 1;
+			if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else
+				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
+						/ mode_lib->vba.DSCFormatFactor
+						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		}
+	}
+
+	// DSC Delay
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k],
+				mode_lib->vba.ODMCombineEnabled[k], mode_lib->vba.DSCInputBitPerComponent[k],
+				mode_lib->vba.OutputBpp[k], mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],
+				mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],
+				mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],
+				mode_lib->vba.PixelClockBackEnd[k]);
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) // NumberOfSurfaces
+			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j])
+				v->DSCDelay[k] = v->DSCDelay[j];
+
+	//Immediate Flip
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
+				&& (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required);
+	}
+
+	// Prefetch
+	dml32_CalculateSurfaceSizeInMall(
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.MALLAllocatedForDCNFinal,
+				mode_lib->vba.UseMALLForStaticScreen,
+				mode_lib->vba.DCCEnable,
+				mode_lib->vba.ViewportStationary,
+				mode_lib->vba.ViewportXStartY,
+				mode_lib->vba.ViewportYStartY,
+				mode_lib->vba.ViewportXStartC,
+				mode_lib->vba.ViewportYStartC,
+				mode_lib->vba.ViewportWidth,
+				mode_lib->vba.ViewportHeight,
+				v->BytePerPixelY,
+				mode_lib->vba.ViewportWidthChroma,
+				mode_lib->vba.ViewportHeightChroma,
+				v->BytePerPixelC,
+				mode_lib->vba.SurfaceWidthY,
+				mode_lib->vba.SurfaceWidthC,
+				mode_lib->vba.SurfaceHeightY,
+				mode_lib->vba.SurfaceHeightC,
+				v->BlockWidth256BytesY,
+				v->BlockWidth256BytesC,
+				v->BlockHeight256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidthY,
+				v->BlockWidthC,
+				v->BlockHeightY,
+				v->BlockHeightC,
+
+				/* Output */
+				v->SurfaceSizeInMALL,
+				&v->dummy_vars.
+				DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.dummy_boolean2); /* Boolean *ExceededMALLSize */
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k];
+		v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k];
+	}
+
+	{
+
+		dml32_CalculateVMRowAndSwath(
+				mode_lib->vba.NumberOfActiveSurfaces,
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters,
+				v->SurfaceSizeInMALL,
+				mode_lib->vba.PTEBufferSizeInRequestsLuma,
+				mode_lib->vba.PTEBufferSizeInRequestsChroma,
+				mode_lib->vba.DCCMetaBufferSizeBytes,
+				mode_lib->vba.UseMALLForStaticScreen,
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.MALLAllocatedForDCNFinal,
+				v->SwathWidthY,
+				v->SwathWidthC,
+				mode_lib->vba.GPUVMEnable,
+				mode_lib->vba.HostVMEnable,
+				mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+				mode_lib->vba.GPUVMMaxPageTableLevels,
+				mode_lib->vba.GPUVMMinPageSizeKBytes,
+				mode_lib->vba.HostVMMinPageSize,
+
+				/* Output */
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0],  // Boolean PTEBufferSizeNotExceeded[]
+				v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[1],  // Boolean DCCMetaBufferSizeNotExceeded[]
+				v->dpte_row_width_luma_ub,
+				v->dpte_row_width_chroma_ub,
+				v->dpte_row_height,
+				v->dpte_row_height_chroma,
+				v->dpte_row_height_linear,
+				v->dpte_row_height_linear_chroma,
+				v->meta_req_width,
+				v->meta_req_width_chroma,
+				v->meta_req_height,
+				v->meta_req_height_chroma,
+				v->meta_row_width,
+				v->meta_row_width_chroma,
+				v->meta_row_height,
+				v->meta_row_height_chroma,
+				v->vm_group_bytes,
+				v->dpte_group_bytes,
+				v->PixelPTEReqWidthY,
+				v->PixelPTEReqHeightY,
+				v->PTERequestSizeY,
+				v->PixelPTEReqWidthC,
+				v->PixelPTEReqHeightC,
+				v->PTERequestSizeC,
+				v->dpde0_bytes_per_frame_ub_l,
+				v->meta_pte_bytes_per_frame_ub_l,
+				v->dpde0_bytes_per_frame_ub_c,
+				v->meta_pte_bytes_per_frame_ub_c,
+				v->PrefetchSourceLinesY,
+				v->PrefetchSourceLinesC,
+				v->VInitPreFillY, v->VInitPreFillC,
+				v->MaxNumSwathY,
+				v->MaxNumSwathC,
+				v->meta_row_bw,
+				v->dpte_row_bw,
+				v->PixelPTEBytesPerRow,
+				v->PDEAndMetaPTEBytesFrame,
+				v->MetaRowByte,
+				v->Use_One_Row_For_Frame,
+				v->Use_One_Row_For_Frame_Flip,
+				v->UsesMALLForStaticScreen,
+				v->PTE_BUFFER_MODE,
+				v->BIGK_FRAGMENT_SIZE);
+	}
+
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels
+			* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only(
+			&mode_lib->vba.soc,
+			mode_lib->vba.VoltageLevel,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.FabricClock,
+			mode_lib->vba.DRAMSpeed);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: mode_lib->vba.ReturnBusWidth = %f\n", __func__, mode_lib->vba.ReturnBusWidth);
+	dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK);
+	dml_print("DML::%s: mode_lib->vba.FabricClock = %f\n", __func__, mode_lib->vba.FabricClock);
+	dml_print("DML::%s: mode_lib->vba.FabricDatapathToDCNDataReturn = %f\n", __func__,
+			mode_lib->vba.FabricDatapathToDCNDataReturn);
+	dml_print("DML::%s: mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency = %f\n",
+			__func__, mode_lib->vba.PercentOfIdealSDPPortBWReceivedAfterUrgLatency);
+	dml_print("DML::%s: mode_lib->vba.DRAMSpeed = %f\n", __func__, mode_lib->vba.DRAMSpeed);
+	dml_print("DML::%s: mode_lib->vba.NumberOfChannels = %f\n", __func__, mode_lib->vba.NumberOfChannels);
+	dml_print("DML::%s: mode_lib->vba.DRAMChannelWidth = %f\n", __func__, mode_lib->vba.DRAMChannelWidth);
+	dml_print("DML::%s: mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n",
+			__func__, mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, mode_lib->vba.ReturnBW);
+#endif
+
+	v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor = 1.0;
+
+	if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable)
+		v->dummy_vars
+			.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+			.HostVMInefficiencyFactor =
+			mode_lib->vba.ReturnBW / v->dummy_vars
+				.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+				.VMDataOnlyReturnBW;
+
+	mode_lib->vba.TotalDCCActiveDPP = 0;
+	mode_lib->vba.TotalActiveDPP = 0;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k];
+		if (mode_lib->vba.DCCEnable[k])
+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
+					+ mode_lib->vba.DPPPerPlane[k];
+	}
+
+	v->UrgentExtraLatency = dml32_CalculateExtraLatency(
+			mode_lib->vba.RoundTripPingLatencyCycles,
+			v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.TotalActiveDPP,
+			mode_lib->vba.PixelChunkSizeInKByte,
+			mode_lib->vba.TotalDCCActiveDPP,
+			mode_lib->vba.MetaChunkSize,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.HostVMEnable,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.DPPPerPlane,
+			v->dpte_group_bytes,
+			v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+			mode_lib->vba.HostVMMinPageSize,
+			mode_lib->vba.HostVMMaxNonCachedPageTableLevels);
+
+	mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			if (mode_lib->vba.WritebackEnable[k] == true) {
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency
+						+ dml32_CalculateWriteBackDelay(
+								mode_lib->vba.WritebackPixelFormat[k],
+								mode_lib->vba.WritebackHRatio[k],
+								mode_lib->vba.WritebackVRatio[k],
+								mode_lib->vba.WritebackVTaps[k],
+								mode_lib->vba.WritebackDestinationWidth[k],
+								mode_lib->vba.WritebackDestinationHeight[k],
+								mode_lib->vba.WritebackSourceHeight[k],
+								mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK;
+			} else
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
+			for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+				if (mode_lib->vba.BlendingAndTiming[j] == k &&
+					mode_lib->vba.WritebackEnable[j] == true) {
+					v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
+						dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
+						mode_lib->vba.WritebackLatency +
+						dml32_CalculateWriteBackDelay(
+								mode_lib->vba.WritebackPixelFormat[j],
+								mode_lib->vba.WritebackHRatio[j],
+								mode_lib->vba.WritebackVRatio[j],
+								mode_lib->vba.WritebackVTaps[j],
+								mode_lib->vba.WritebackDestinationWidth[j],
+								mode_lib->vba.WritebackDestinationHeight[j],
+								mode_lib->vba.WritebackSourceHeight[j],
+								mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK);
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j)
+			if (mode_lib->vba.BlendingAndTiming[k] == j)
+				v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
+						v->WritebackDelay[mode_lib->vba.VoltageLevel][j];
+
+	v->UrgentLatency = dml32_CalculateUrgentLatency(mode_lib->vba.UrgentLatencyPixelDataOnly,
+			mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
+			mode_lib->vba.UrgentLatencyVMDataOnly,
+			mode_lib->vba.DoUrgentLatencyAdjustment,
+			mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent,
+			mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference,
+			mode_lib->vba.FabricClock);
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
+				v->swath_width_luma_ub[k],
+				v->swath_width_chroma_ub[k],
+				mode_lib->vba.SwathHeightY[k],
+				mode_lib->vba.SwathHeightC[k],
+				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+				v->UrgentLatency,
+				mode_lib->vba.CursorBufferSize,
+				mode_lib->vba.CursorWidth[k][0],
+				mode_lib->vba.CursorBPP[k][0],
+				mode_lib->vba.VRatio[k],
+				mode_lib->vba.VRatioChroma[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				mode_lib->vba.DETBufferSizeY[k],
+				mode_lib->vba.DETBufferSizeC[k],
+
+				/* output */
+				&v->UrgBurstFactorCursor[k],
+				&v->UrgBurstFactorLuma[k],
+				&v->UrgBurstFactorChroma[k],
+				&v->NoUrgentLatencyHiding[k]);
+
+		v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
+				!mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ?
+				dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) :
+				mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0,
+				dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
+
+	// Clamp to max OTG vstartup register limit
+	if (v->MaxVStartupLines[k] > 1023)
+		v->MaxVStartupLines[k] = 1023;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, mode_lib->vba.VoltageLevel);
+		dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__,
+				k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]);
+#endif
+	}
+
+	v->MaximumMaxVStartupLines = 0;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
+
+	ImmediateFlipRequirementFinal = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		ImmediateFlipRequirementFinal = ImmediateFlipRequirementFinal
+				|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ImmediateFlipRequirementFinal = %d\n", __func__, ImmediateFlipRequirementFinal);
+#endif
+	// ModeProgramming will not repeat the schedule calculation using different prefetch mode,
+	//it is just calcualated once with given prefetch mode
+	dml32_CalculateMinAndMaxPrefetchMode(
+			mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal,
+			&mode_lib->vba.MinPrefetchMode,
+			&mode_lib->vba.MaxPrefetchMode);
+
+	v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
+
+	iteration = 0;
+	MaxTotalRDBandwidth = 0;
+	NextPrefetchMode = mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
+
+	do {
+		double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+		bool DestinationLineTimesForPrefetchLessThan2 = false;
+		bool VRatioPrefetchMoreThanMax = false;
+		double dummy_unit_vector[DC__NUM_DPP__MAX];
+
+		MaxTotalRDBandwidth = 0;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, mode_lib->vba.VStartupLines);
+#endif
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			/* NOTE PerfetchMode variable is invalid in DAL as per the input received.
+			 * Hence the direction is to use PrefetchModePerState.
+			 */
+			double TWait = dml32_CalculateTWait(
+					mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
+					mode_lib->vba.UsesMALLForPStateChange[k],
+					mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+					mode_lib->vba.DRRDisplay[k],
+					mode_lib->vba.DRAMClockChangeLatency,
+					mode_lib->vba.FCLKChangeLatency, v->UrgentLatency,
+					mode_lib->vba.SREnterPlusExitTime);
+
+			DmlPipe myPipe;
+
+			myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
+			myPipe.Dispclk = mode_lib->vba.DISPCLK;
+			myPipe.PixelClock = mode_lib->vba.PixelClock[k];
+			myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
+			myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
+			myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
+			myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
+			myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+			myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+			myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+			myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+			myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
+			myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
+			myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
+			myPipe.HTotal = mode_lib->vba.HTotal[k];
+			myPipe.HActive = mode_lib->vba.HActive[k];
+			myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
+			myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k];
+			myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+			myPipe.BytePerPixelY = v->BytePerPixelY[k];
+			myPipe.BytePerPixelC = v->BytePerPixelC[k];
+			myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+			v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+					&myPipe, v->DSCDelay[k],
+					mode_lib->vba.DPPCLKDelaySubtotal + mode_lib->vba.DPPCLKDelayCNVCFormater,
+					mode_lib->vba.DPPCLKDelaySCL,
+					mode_lib->vba.DPPCLKDelaySCLLBOnly,
+					mode_lib->vba.DPPCLKDelayCNVCCursor,
+					mode_lib->vba.DISPCLKDelaySubtotal,
+					(unsigned int) (v->SwathWidthY[k] / mode_lib->vba.HRatio[k]),
+					mode_lib->vba.OutputFormat[k],
+					mode_lib->vba.MaxInterDCNTileRepeaters,
+					dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
+					v->MaxVStartupLines[k],
+					mode_lib->vba.GPUVMMaxPageTableLevels,
+					mode_lib->vba.GPUVMEnable,
+					mode_lib->vba.HostVMEnable,
+					mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+					mode_lib->vba.HostVMMinPageSize,
+					mode_lib->vba.DynamicMetadataEnable[k],
+					mode_lib->vba.DynamicMetadataVMEnabled,
+					mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
+					mode_lib->vba.DynamicMetadataTransmittedBytes[k],
+					v->UrgentLatency,
+					v->UrgentExtraLatency,
+					mode_lib->vba.TCalc,
+					v->PDEAndMetaPTEBytesFrame[k],
+					v->MetaRowByte[k],
+					v->PixelPTEBytesPerRow[k],
+					v->PrefetchSourceLinesY[k],
+					v->SwathWidthY[k],
+					v->VInitPreFillY[k],
+					v->MaxNumSwathY[k],
+					v->PrefetchSourceLinesC[k],
+					v->SwathWidthC[k],
+					v->VInitPreFillC[k],
+					v->MaxNumSwathC[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					mode_lib->vba.SwathHeightY[k],
+					mode_lib->vba.SwathHeightC[k],
+					TWait,
+					/* Output */
+					&v->DSTXAfterScaler[k],
+					&v->DSTYAfterScaler[k],
+					&v->DestinationLinesForPrefetch[k],
+					&v->PrefetchBandwidth[k],
+					&v->DestinationLinesToRequestVMInVBlank[k],
+					&v->DestinationLinesToRequestRowInVBlank[k],
+					&v->VRatioPrefetchY[k],
+					&v->VRatioPrefetchC[k],
+					&v->RequiredPrefetchPixDataBWLuma[k],
+					&v->RequiredPrefetchPixDataBWChroma[k],
+					&v->NotEnoughTimeForDynamicMetadata[k],
+					&v->Tno_bw[k], &v->prefetch_vmrow_bw[k],
+					&v->Tdmdl_vm[k],
+					&v->Tdmdl[k],
+					&v->TSetup[k],
+					&v->VUpdateOffsetPix[k],
+					&v->VUpdateWidthPix[k],
+					&v->VReadyOffsetPix[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Prefetch calculation errResult=%0d\n",
+					__func__, k, mode_lib->vba.ErrorResult[k]);
+#endif
+			v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					mode_lib->vba.SwathHeightY[k],
+					mode_lib->vba.SwathHeightC[k],
+					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+					v->UrgentLatency,
+					mode_lib->vba.CursorBufferSize,
+					mode_lib->vba.CursorWidth[k][0],
+					mode_lib->vba.CursorBPP[k][0],
+					v->VRatioPrefetchY[k],
+					v->VRatioPrefetchC[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					mode_lib->vba.DETBufferSizeY[k],
+					mode_lib->vba.DETBufferSizeC[k],
+					/* Output */
+					&v->UrgBurstFactorCursorPre[k],
+					&v->UrgBurstFactorLumaPre[k],
+					&v->UrgBurstFactorChromaPre[k],
+					&v->NoUrgentLatencyHidingPre[k]);
+
+			v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
+					8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d DPPPerSurface=%d\n", __func__, k, mode_lib->vba.DPPPerPlane[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k,
+					v->UrgBurstFactorLumaPre[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k,
+					v->UrgBurstFactorChromaPre[k]);
+
+			dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
+			dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, mode_lib->vba.VRatio[k]);
+
+			dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthSurfaceLuma=%f\n", __func__, k,
+					v->ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthSurfaceChroma=%f\n", __func__, k,
+					v->ReadBandwidthSurfaceChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
+			dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
+			dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k,
+					v->RequiredPrefetchPixDataBWLuma[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k,
+					v->RequiredPrefetchPixDataBWChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
+			dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k,
+					MaxTotalRDBandwidthNoUrgentBurst);
+#endif
+			if (v->DestinationLinesForPrefetch[k] < 2)
+				DestinationLineTimesForPrefetchLessThan2 = true;
+
+			if (v->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__
+					|| v->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__)
+				VRatioPrefetchMoreThanMax = true;
+
+			//bool DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = false;
+			//bool DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = false;
+			//if (v->DestinationLinesToRequestVMInVBlank[k] >= 32) {
+			//    DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = true;
+			//}
+
+			//if (v->DestinationLinesToRequestRowInVBlank[k] >= 16) {
+			//    DestinationLinesToRequestRowInVBlankEqualOrMoreThan16 = true;
+			//}
+		}
+
+		v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f\n",
+				__func__, MaxTotalRDBandwidthNoUrgentBurst);
+		dml_print("DML::%s: ReturnBW=%f\n", __func__, mode_lib->vba.ReturnBW);
+		dml_print("DML::%s: FractionOfUrgentBandwidth=%f\n",
+				__func__, mode_lib->vba.FractionOfUrgentBandwidth);
+#endif
+
+		{
+			double dummy_single[1];
+
+			dml32_CalculatePrefetchBandwithSupport(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->NoUrgentLatencyHidingPre,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->meta_row_bw,
+					v->dpte_row_bw,
+					v->cursor_bw_pre,
+					v->prefetch_vmrow_bw,
+					mode_lib->vba.DPPPerPlane,
+					v->UrgBurstFactorLuma,
+					v->UrgBurstFactorChroma,
+					v->UrgBurstFactorCursor,
+					v->UrgBurstFactorLumaPre,
+					v->UrgBurstFactorChromaPre,
+					v->UrgBurstFactorCursorPre,
+
+					/* output */
+					&MaxTotalRDBandwidth,
+					&dummy_single[0],
+					&v->PrefetchModeSupported);
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+			dummy_unit_vector[k] = 1.0;
+
+		{
+			double  dummy_single[1];
+			bool dummy_boolean[1];
+			dml32_CalculatePrefetchBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->NoUrgentLatencyHidingPre,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->meta_row_bw,
+					v->dpte_row_bw,
+					v->cursor_bw_pre,
+					v->prefetch_vmrow_bw,
+					mode_lib->vba.DPPPerPlane,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+					dummy_unit_vector,
+
+					/* output */
+					&dummy_single[0],
+					&v->FractionOfUrgentBandwidth,
+					&dummy_boolean[0]);
+		}
+
+		if (VRatioPrefetchMoreThanMax != false || DestinationLineTimesForPrefetchLessThan2 != false) {
+			v->PrefetchModeSupported = false;
+		}
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {
+				v->PrefetchModeSupported = false;
+			}
+		}
+
+		if (v->PrefetchModeSupported == true && mode_lib->vba.ImmediateFlipSupport == true) {
+			mode_lib->vba.BandwidthAvailableForImmediateFlip = dml32_CalculateBandwidthAvailableForImmediateFlip(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBW,
+					v->ReadBandwidthSurfaceLuma,
+					v->ReadBandwidthSurfaceChroma,
+					v->RequiredPrefetchPixDataBWLuma,
+					v->RequiredPrefetchPixDataBWChroma,
+					v->cursor_bw,
+					v->cursor_bw_pre,
+					mode_lib->vba.DPPPerPlane,
+					v->UrgBurstFactorLuma,
+					v->UrgBurstFactorChroma,
+					v->UrgBurstFactorCursor,
+					v->UrgBurstFactorLumaPre,
+					v->UrgBurstFactorChromaPre,
+					v->UrgBurstFactorCursorPre);
+
+			mode_lib->vba.TotImmediateFlipBytes = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
+					mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes
+							+ mode_lib->vba.DPPPerPlane[k]
+									* (v->PDEAndMetaPTEBytesFrame[k]
+											+ v->MetaRowByte[k]);
+					if (v->use_one_row_for_frame_flip[k][0][0]) {
+						mode_lib->vba.TotImmediateFlipBytes =
+								mode_lib->vba.TotImmediateFlipBytes
+										+ 2 * v->PixelPTEBytesPerRow[k];
+					} else {
+						mode_lib->vba.TotImmediateFlipBytes =
+								mode_lib->vba.TotImmediateFlipBytes
+										+ v->PixelPTEBytesPerRow[k];
+					}
+				}
+			}
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				dml32_CalculateFlipSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
+						v->UrgentExtraLatency,
+						v->UrgentLatency,
+						mode_lib->vba.GPUVMMaxPageTableLevels,
+						mode_lib->vba.HostVMEnable,
+						mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+						mode_lib->vba.GPUVMEnable,
+						mode_lib->vba.HostVMMinPageSize,
+						v->PDEAndMetaPTEBytesFrame[k],
+						v->MetaRowByte[k],
+						v->PixelPTEBytesPerRow[k],
+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
+						mode_lib->vba.TotImmediateFlipBytes,
+						mode_lib->vba.SourcePixelFormat[k],
+						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+						mode_lib->vba.VRatio[k],
+						mode_lib->vba.VRatioChroma[k],
+						v->Tno_bw[k],
+						mode_lib->vba.DCCEnable[k],
+						v->dpte_row_height[k],
+						v->meta_row_height[k],
+						v->dpte_row_height_chroma[k],
+						v->meta_row_height_chroma[k],
+						v->Use_One_Row_For_Frame_Flip[k],
+
+						/* Output */
+						&v->DestinationLinesToRequestVMInImmediateFlip[k],
+						&v->DestinationLinesToRequestRowInImmediateFlip[k],
+						&v->final_flip_bw[k],
+						&v->ImmediateFlipSupportedForPipe[k]);
+			}
+
+			{
+				double  dummy_single[2];
+				bool dummy_boolean[1];
+				dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.ReturnBW,
+						mode_lib->vba.ImmediateFlipRequirement,
+						v->final_flip_bw,
+						v->ReadBandwidthSurfaceLuma,
+						v->ReadBandwidthSurfaceChroma,
+						v->RequiredPrefetchPixDataBWLuma,
+						v->RequiredPrefetchPixDataBWChroma,
+						v->cursor_bw,
+						v->meta_row_bw,
+						v->dpte_row_bw,
+						v->cursor_bw_pre,
+						v->prefetch_vmrow_bw,
+						mode_lib->vba.DPPPerPlane,
+						v->UrgBurstFactorLuma,
+						v->UrgBurstFactorChroma,
+						v->UrgBurstFactorCursor,
+						v->UrgBurstFactorLumaPre,
+						v->UrgBurstFactorChromaPre,
+						v->UrgBurstFactorCursorPre,
+
+						/* output */
+						&v->total_dcn_read_bw_with_flip,    // Single  *TotalBandwidth
+						&dummy_single[0],                        // Single  *FractionOfUrgentBandwidth
+						&v->ImmediateFlipSupported);        // Boolean *ImmediateFlipBandwidthSupport
+
+				dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.ReturnBW,
+						mode_lib->vba.ImmediateFlipRequirement,
+						v->final_flip_bw,
+						v->ReadBandwidthSurfaceLuma,
+						v->ReadBandwidthSurfaceChroma,
+						v->RequiredPrefetchPixDataBWLuma,
+						v->RequiredPrefetchPixDataBWChroma,
+						v->cursor_bw,
+						v->meta_row_bw,
+						v->dpte_row_bw,
+						v->cursor_bw_pre,
+						v->prefetch_vmrow_bw,
+						mode_lib->vba.DPPPerPlane,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+						dummy_unit_vector,
+
+						/* output */
+						&dummy_single[1],                                // Single  *TotalBandwidth
+						&v->FractionOfUrgentBandwidthImmediateFlip, // Single  *FractionOfUrgentBandwidth
+						&dummy_boolean[0]);                              // Boolean *ImmediateFlipBandwidthSupport
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
+					v->ImmediateFlipSupported = false;
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k);
+#endif
+				}
+			}
+		} else {
+			v->ImmediateFlipSupported = false;
+		}
+
+		/* consider flip support is okay if the flip bw is ok or (when user does't require a iflip and there is no host vm) */
+		v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true &&
+				((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable && !ImmediateFlipRequirementFinal) ||
+						v->ImmediateFlipSupported)) ? true : false;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: PrefetchModeSupported = %d\n", __func__, locals->PrefetchModeSupported);
+		for (uint k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+			dml_print("DML::%s: ImmediateFlipRequirement[%d] = %d\n", __func__, k,  mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipSupported = %d\n", __func__, locals->ImmediateFlipSupported);
+		dml_print("DML::%s: ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateFlipSupport);
+		dml_print("DML::%s: HostVMEnable = %d\n", __func__, mode_lib->vba.HostVMEnable);
+		dml_print("DML::%s: PrefetchAndImmediateFlipSupported = %d\n", __func__, locals->PrefetchAndImmediateFlipSupported);
+		dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup=%d\n", __func__, locals->VStartupLines, locals->MaximumMaxVStartupLines);
+#endif
+
+		v->VStartupLines = v->VStartupLines + 1;
+
+		if (v->VStartupLines > v->MaximumMaxVStartupLines) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Vstartup exceeds max vstartup, exiting loop\n", __func__);
+#endif
+			break; // VBA_DELTA: Implementation divergence! Gabe is *still* iterating across prefetch modes which we don't care to do
+		}
+		iteration++;
+		if (iteration > 2500) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: too many errors, exit now\n", __func__);
+			assert(0);
+#endif
+		}
+	} while (!(v->PrefetchAndImmediateFlipSupported || NextPrefetchMode > mode_lib->vba.MaxPrefetchMode));
+
+
+	if (v->VStartupLines <= v->MaximumMaxVStartupLines) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Good, Prefetch and flip scheduling found solution at VStartupLines=%d\n", __func__, locals->VStartupLines-1);
+#endif
+	}
+
+
+	//Watermarks and NB P-State/DRAM Clock Change Support
+	{
+		SOCParametersList mmSOCParameters;
+		enum clock_change_support dummy_dramchange_support;
+		enum dm_fclock_change_support dummy_fclkchange_support;
+		bool dummy_USRRetrainingSupport;
+
+		mmSOCParameters.UrgentLatency = v->UrgentLatency;
+		mmSOCParameters.ExtraLatency = v->UrgentExtraLatency;
+		mmSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
+		mmSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
+		mmSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
+		mmSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
+		mmSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
+		mmSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
+		mmSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
+		mmSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
+		mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
+
+		dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+			mode_lib->vba.USRRetrainingRequiredFinal,
+			mode_lib->vba.UsesMALLForPStateChange,
+			mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.MaxLineBufferLines,
+			mode_lib->vba.LineBufferSizeFinal,
+			mode_lib->vba.WritebackInterfaceBufferSize,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.SynchronizeTimingsFinal,
+			mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+			mode_lib->vba.DRRDisplay,
+			v->dpte_group_bytes,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			mmSOCParameters,
+			mode_lib->vba.WritebackChunkSize,
+			mode_lib->vba.SOCCLK,
+			v->DCFCLKDeepSleep,
+			mode_lib->vba.DETBufferSizeY,
+			mode_lib->vba.DETBufferSizeC,
+			mode_lib->vba.SwathHeightY,
+			mode_lib->vba.SwathHeightC,
+			mode_lib->vba.LBBitPerPixel,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.vtaps,
+			mode_lib->vba.VTAPsChroma,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			mode_lib->vba.HTotal,
+			mode_lib->vba.VTotal,
+			mode_lib->vba.VActive,
+			mode_lib->vba.PixelClock,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.DPPPerPlane,
+			v->BytePerPixelDETY,
+			v->BytePerPixelDETC,
+			v->DSTXAfterScaler,
+			v->DSTYAfterScaler,
+			mode_lib->vba.WritebackEnable,
+			mode_lib->vba.WritebackPixelFormat,
+			mode_lib->vba.WritebackDestinationWidth,
+			mode_lib->vba.WritebackDestinationHeight,
+			mode_lib->vba.WritebackSourceHeight,
+			v->UnboundedRequestEnabled,
+			v->CompressedBufferSizeInkByte,
+
+			/* Output */
+			&v->Watermark,
+			&dummy_dramchange_support,
+			v->MaxActiveDRAMClockChangeLatencySupported,
+			v->SubViewportLinesNeededInMALL,
+			&dummy_fclkchange_support,
+			&v->MinActiveFCLKChangeLatencySupported,
+			&dummy_USRRetrainingSupport,
+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+
+		/* DCN32 has a new struct Watermarks (typedef) which is used to store
+		 * calculated WM values. Copy over values from struct to vba varaibles
+		 * to ensure that the DCN32 getters return the correct value.
+		 */
+		v->UrgentWatermark = v->Watermark.UrgentWatermark;
+		v->WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark;
+		v->DRAMClockChangeWatermark = v->Watermark.DRAMClockChangeWatermark;
+		v->WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark;
+		v->StutterExitWatermark = v->Watermark.StutterExitWatermark;
+		v->StutterEnterPlusExitWatermark = v->Watermark.StutterEnterPlusExitWatermark;
+		v->Z8StutterExitWatermark = v->Watermark.Z8StutterExitWatermark;
+		v->Z8StutterEnterPlusExitWatermark = v->Watermark.Z8StutterEnterPlusExitWatermark;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.WritebackEnable[k] == true) {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
+						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
+								- v->Watermark.WritebackDRAMClockChangeWatermark);
+				v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
+						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
+								- v->Watermark.WritebackFCLKChangeWatermark);
+			} else {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
+				v->WritebackAllowFCLKChangeEndPosition[k] = 0;
+			}
+		}
+	}
+
+	//Display Pipeline Delivery Time in Prefetch, Groups
+	dml32_CalculatePixelDeliveryTimes(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->VRatioPrefetchY,
+			v->VRatioPrefetchC,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub,
+			mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			mode_lib->vba.PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			mode_lib->vba.DPPCLK,
+			v->BytePerPixelC,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.NumberOfCursors,
+			mode_lib->vba.CursorWidth,
+			mode_lib->vba.CursorBPP,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlockHeight256BytesC,
+
+			/* Output */
+			v->DisplayPipeLineDeliveryTimeLuma,
+			v->DisplayPipeLineDeliveryTimeChroma,
+			v->DisplayPipeLineDeliveryTimeLumaPrefetch,
+			v->DisplayPipeLineDeliveryTimeChromaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeLuma,
+			v->DisplayPipeRequestDeliveryTimeChroma,
+			v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
+			v->CursorRequestDeliveryTime,
+			v->CursorRequestDeliveryTimePrefetch);
+
+	dml32_CalculateMetaAndPTETimes(v->Use_One_Row_For_Frame,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.MetaChunkSize,
+			mode_lib->vba.MinMetaChunkSizeBytes,
+			mode_lib->vba.HTotal,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.VRatioChroma,
+			v->DestinationLinesToRequestRowInVBlank,
+			v->DestinationLinesToRequestRowInImmediateFlip,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.PixelClock,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			mode_lib->vba.SourceRotation,
+			v->dpte_row_height,
+			v->dpte_row_height_chroma,
+			v->meta_row_width,
+			v->meta_row_width_chroma,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			v->meta_req_width,
+			v->meta_req_width_chroma,
+			v->meta_req_height,
+			v->meta_req_height_chroma,
+			v->dpte_group_bytes,
+			v->PTERequestSizeY,
+			v->PTERequestSizeC,
+			v->PixelPTEReqWidthY,
+			v->PixelPTEReqHeightY,
+			v->PixelPTEReqWidthC,
+			v->PixelPTEReqHeightC,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+
+			/* Output */
+			v->DST_Y_PER_PTE_ROW_NOM_L,
+			v->DST_Y_PER_PTE_ROW_NOM_C,
+			v->DST_Y_PER_META_ROW_NOM_L,
+			v->DST_Y_PER_META_ROW_NOM_C,
+			v->TimePerMetaChunkNominal,
+			v->TimePerChromaMetaChunkNominal,
+			v->TimePerMetaChunkVBlank,
+			v->TimePerChromaMetaChunkVBlank,
+			v->TimePerMetaChunkFlip,
+			v->TimePerChromaMetaChunkFlip,
+			v->time_per_pte_group_nom_luma,
+			v->time_per_pte_group_vblank_luma,
+			v->time_per_pte_group_flip_luma,
+			v->time_per_pte_group_nom_chroma,
+			v->time_per_pte_group_vblank_chroma,
+			v->time_per_pte_group_flip_chroma);
+
+	dml32_CalculateVMGroupAndRequestTimes(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.GPUVMEnable,
+			mode_lib->vba.GPUVMMaxPageTableLevels,
+			mode_lib->vba.HTotal,
+			v->BytePerPixelC,
+			v->DestinationLinesToRequestVMInVBlank,
+			v->DestinationLinesToRequestVMInImmediateFlip,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.PixelClock,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->vm_group_bytes,
+			v->dpde0_bytes_per_frame_ub_l,
+			v->dpde0_bytes_per_frame_ub_c,
+			v->meta_pte_bytes_per_frame_ub_l,
+			v->meta_pte_bytes_per_frame_ub_c,
+
+			/* Output */
+			v->TimePerVMGroupVBlank,
+			v->TimePerVMGroupFlip,
+			v->TimePerVMRequestVBlank,
+			v->TimePerVMRequestFlip);
+
+	// Min TTUVBlank
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
+			v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,
+					v->Watermark.FCLKChangeWatermark, v->Watermark.StutterEnterPlusExitWatermark,
+					v->Watermark.UrgentWatermark);
+		} else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
+				== 1) {
+			v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
+					v->Watermark.StutterEnterPlusExitWatermark, v->Watermark.UrgentWatermark);
+		} else if (mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
+				== 2) {
+			v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
+					v->Watermark.UrgentWatermark);
+		} else {
+			v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark;
+		}
+		if (!mode_lib->vba.DynamicMetadataEnable[k])
+			v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k];
+	}
+
+	// DCC Configuration
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Calculate DCC configuration for surface k=%d\n", __func__, k);
+#endif
+		dml32_CalculateDCCConfiguration(
+				mode_lib->vba.DCCEnable[k],
+				mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal,
+				mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceWidthY[k],
+				mode_lib->vba.SurfaceWidthC[k],
+				mode_lib->vba.SurfaceHeightY[k],
+				mode_lib->vba.SurfaceHeightC[k],
+				mode_lib->vba.nomDETInKByte,
+				v->BlockHeight256BytesY[k],
+				v->BlockHeight256BytesC[k],
+				mode_lib->vba.SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->BytePerPixelC[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				(enum dm_rotation_angle) mode_lib->vba.SourceScan[k],
+				/* Output */
+				&v->DCCYMaxUncompressedBlock[k],
+				&v->DCCCMaxUncompressedBlock[k],
+				&v->DCCYMaxCompressedBlock[k],
+				&v->DCCCMaxCompressedBlock[k],
+				&v->DCCYIndependentBlock[k],
+				&v->DCCCIndependentBlock[k]);
+	}
+
+	// VStartup Adjustment
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		bool isInterlaceTiming;
+		double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k]
+				/ mode_lib->vba.PixelClock[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k,
+				v->MinTTUVBlank[k]);
+#endif
+
+		v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
+		dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
+		if (mode_lib->vba.DynamicMetadataEnable[k] && mode_lib->vba.DynamicMetadataVMEnabled)
+			v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
+
+		isInterlaceTiming = (mode_lib->vba.Interlace[k] &&
+				!mode_lib->vba.ProgressiveToInterlaceUnitInOPP);
+
+		v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] -
+						mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) :
+						mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k])
+						+ dml_max(1.0,
+						dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
+						/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0))
+						+ dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k]
+						/ mode_lib->vba.PixelClock[k]), 1.0) / 4.0;
+
+		v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
+
+		if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k])
+			/ mode_lib->vba.HTotal[k]) <= (isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k]
+			- mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
+			(int) (mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
+		       - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
+		} else {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
+		dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
+		dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
+		dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, mode_lib->vba.HTotal[k]);
+		dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, mode_lib->vba.VTotal[k]);
+		dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, mode_lib->vba.VActive[k]);
+		dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, mode_lib->vba.VFrontPorch[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]);
+		dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
+		dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k,
+				v->VREADY_AT_OR_AFTER_VSYNC[k]);
+#endif
+	}
+
+	{
+		//Maximum Bandwidth Used
+		double TotalWRBandwidth = 0;
+		double WRBandwidth = 0;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.WritebackEnable[k] == true
+					&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
+				WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
+						* mode_lib->vba.WritebackDestinationHeight[k]
+						/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
+								/ mode_lib->vba.PixelClock[k]) * 4;
+			} else if (mode_lib->vba.WritebackEnable[k] == true) {
+				WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
+						* mode_lib->vba.WritebackDestinationHeight[k]
+						/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
+								/ mode_lib->vba.PixelClock[k]) * 8;
+			}
+			TotalWRBandwidth = TotalWRBandwidth + WRBandwidth;
+		}
+
+		v->TotalDataReadBandwidth = 0;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k]
+					+ v->ReadBandwidthSurfaceChroma[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d, TotalDataReadBandwidth = %f\n",
+					__func__, k, v->TotalDataReadBandwidth);
+			dml_print("DML::%s: k=%d, ReadBandwidthSurfaceLuma = %f\n",
+					__func__, k, v->ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%d, ReadBandwidthSurfaceChroma = %f\n",
+					__func__, k, v->ReadBandwidthSurfaceChroma[k]);
+#endif
+		}
+	}
+
+	// Stutter Efficiency
+	dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
+			mode_lib->vba.UsesMALLForPStateChange,
+			v->UnboundedRequestEnabled,
+			mode_lib->vba.MetaFIFOSizeInKEntries,
+			mode_lib->vba.ZeroSizeBufferEntries,
+			mode_lib->vba.PixelChunkSizeInKByte,
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.ROBBufferSizeInKByte,
+			v->TotalDataReadBandwidth,
+			mode_lib->vba.DCFCLK,
+			mode_lib->vba.ReturnBW,
+			mode_lib->vba.CompbufReservedSpace64B,
+			mode_lib->vba.CompbufReservedSpaceZs,
+			mode_lib->vba.SRExitTime,
+			mode_lib->vba.SRExitZ8Time,
+			mode_lib->vba.SynchronizeTimingsFinal,
+			mode_lib->vba.BlendingAndTiming,
+			v->Watermark.StutterEnterPlusExitWatermark,
+			v->Watermark.Z8StutterEnterPlusExitWatermark,
+			mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+			mode_lib->vba.Interlace,
+			v->MinTTUVBlank, mode_lib->vba.DPPPerPlane,
+			mode_lib->vba.DETBufferSizeY,
+			v->BytePerPixelY,
+			v->BytePerPixelDETY,
+			v->SwathWidthY,
+			mode_lib->vba.SwathHeightY,
+			mode_lib->vba.SwathHeightC,
+			mode_lib->vba.DCCRateLuma,
+			mode_lib->vba.DCCRateChroma,
+			mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma,
+			mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma,
+			mode_lib->vba.HTotal, mode_lib->vba.VTotal,
+			mode_lib->vba.PixelClock,
+			mode_lib->vba.VRatio,
+			mode_lib->vba.SourceRotation,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesC,
+			v->DCCYMaxUncompressedBlock,
+			v->DCCCMaxUncompressedBlock,
+			mode_lib->vba.VActive,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.WritebackEnable,
+			v->ReadBandwidthSurfaceLuma,
+			v->ReadBandwidthSurfaceChroma,
+			v->meta_row_bw,
+			v->dpte_row_bw,
+			/* Output */
+			&v->StutterEfficiencyNotIncludingVBlank,
+			&v->StutterEfficiency,
+			&v->NumberOfStutterBurstsPerFrame,
+			&v->Z8StutterEfficiencyNotIncludingVBlank,
+			&v->Z8StutterEfficiency,
+			&v->Z8NumberOfStutterBurstsPerFrame,
+			&v->StutterPeriod,
+			&v->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	{
+		double dummy_single[2];
+		unsigned int dummy_integer[1];
+		bool dummy_boolean[1];
+
+		// Calculate z8 stutter eff assuming 0 reserved space
+		dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
+				mode_lib->vba.UsesMALLForPStateChange,
+				v->UnboundedRequestEnabled,
+				mode_lib->vba.MetaFIFOSizeInKEntries,
+				mode_lib->vba.ZeroSizeBufferEntries,
+				mode_lib->vba.PixelChunkSizeInKByte,
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.ROBBufferSizeInKByte,
+				v->TotalDataReadBandwidth,
+				mode_lib->vba.DCFCLK,
+				mode_lib->vba.ReturnBW,
+				0, //mode_lib->vba.CompbufReservedSpace64B,
+				0, //mode_lib->vba.CompbufReservedSpaceZs,
+				mode_lib->vba.SRExitTime,
+				mode_lib->vba.SRExitZ8Time,
+				mode_lib->vba.SynchronizeTimingsFinal,
+				mode_lib->vba.BlendingAndTiming,
+				v->Watermark.StutterEnterPlusExitWatermark,
+				v->Watermark.Z8StutterEnterPlusExitWatermark,
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+				mode_lib->vba.Interlace,
+				v->MinTTUVBlank,
+				mode_lib->vba.DPPPerPlane,
+				mode_lib->vba.DETBufferSizeY,
+				v->BytePerPixelY, v->BytePerPixelDETY,
+				v->SwathWidthY, mode_lib->vba.SwathHeightY,
+				mode_lib->vba.SwathHeightC,
+				mode_lib->vba.DCCRateLuma,
+				mode_lib->vba.DCCRateChroma,
+				mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma,
+				mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma,
+				mode_lib->vba.HTotal,
+				mode_lib->vba.VTotal,
+				mode_lib->vba.PixelClock,
+				mode_lib->vba.VRatio,
+				mode_lib->vba.SourceRotation,
+				v->BlockHeight256BytesY,
+				v->BlockWidth256BytesY,
+				v->BlockHeight256BytesC,
+				v->BlockWidth256BytesC,
+				v->DCCYMaxUncompressedBlock,
+				v->DCCCMaxUncompressedBlock,
+				mode_lib->vba.VActive,
+				mode_lib->vba.DCCEnable,
+				mode_lib->vba.WritebackEnable,
+				v->ReadBandwidthSurfaceLuma,
+				v->ReadBandwidthSurfaceChroma,
+				v->meta_row_bw, v->dpte_row_bw,
+
+				/* Output */
+				&dummy_single[0],
+				&dummy_single[1],
+				&dummy_integer[0],
+				&v->Z8StutterEfficiencyNotIncludingVBlankBestCase,
+				&v->Z8StutterEfficiencyBestCase,
+				&v->Z8NumberOfStutterBurstsPerFrameBestCase,
+				&v->StutterPeriodBestCase,
+				&dummy_boolean[0]);
+	}
+#else
+	v->Z8StutterEfficiencyNotIncludingVBlankBestCase = v->Z8StutterEfficiencyNotIncludingVBlank;
+	v->Z8StutterEfficiencyBestCase = v->Z8StutterEfficiency;
+	v->Z8NumberOfStutterBurstsPerFrameBestCase = v->Z8NumberOfStutterBurstsPerFrame;
+	v->StutterPeriodBestCase = v->StutterPeriod;
+#endif
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- END ---\n", __func__);
+#endif
+}
+
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
+{
+	unsigned int dummy_integer[4];
+	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
+	bool MPCCombineMethodAsPossible;
+	enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
+	unsigned int TotalNumberOfActiveOTG;
+	unsigned int TotalNumberOfActiveHDMIFRL;
+	unsigned int TotalNumberOfActiveDP2p0;
+	unsigned int TotalNumberOfActiveDP2p0Outputs;
+	unsigned int TotalDSCUnitsRequired;
+	unsigned int m;
+	unsigned int ReorderingBytes;
+	bool FullFrameMALLPStateMethod;
+	bool SubViewportMALLPStateMethod;
+	bool PhantomPipeMALLPStateMethod;
+	unsigned int MaximumMPCCombine;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: called\n", __func__);
+#endif
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	int i, j;
+	unsigned int k;
+
+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
+
+	/*Scale Ratio, taps Support Check*/
+
+	mode_lib->vba.ScaleRatioAndTapsSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.ScalerEnabled[k] == false
+				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha)
+						|| mode_lib->vba.HRatio[k] != 1.0 || mode_lib->vba.htaps[k] != 1.0
+						|| mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) {
+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
+		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0
+				|| mode_lib->vba.htaps[k] > 8.0
+				|| (mode_lib->vba.htaps[k] > 1.0 && (mode_lib->vba.htaps[k] % 2) == 1)
+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
+				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
+						&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+						&& (mode_lib->vba.VTAPsChroma[k] < 1
+								|| mode_lib->vba.VTAPsChroma[k] > 8
+								|| mode_lib->vba.HTAPsChroma[k] < 1
+								|| mode_lib->vba.HTAPsChroma[k] > 8
+								|| (mode_lib->vba.HTAPsChroma[k] > 1
+										&& mode_lib->vba.HTAPsChroma[k] % 2
+												== 1)
+								|| mode_lib->vba.HRatioChroma[k]
+										> mode_lib->vba.MaxHSCLRatio
+								|| mode_lib->vba.VRatioChroma[k]
+										> mode_lib->vba.MaxVSCLRatio
+								|| mode_lib->vba.HRatioChroma[k]
+										> mode_lib->vba.HTAPsChroma[k]
+								|| mode_lib->vba.VRatioChroma[k]
+										> mode_lib->vba.VTAPsChroma[k]))) {
+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
+		}
+	}
+
+	/*Source Format, Pixel Format and Scan Support Check*/
+	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
+			&& (!(!IsVertical((enum dm_rotation_angle) mode_lib->vba.SourceScan[k]))
+				|| mode_lib->vba.DCCEnable[k] == true)) {
+			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
+		}
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		dml32_CalculateBytePerPixelAndBlockSizes(
+				mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.SurfaceTiling[k],
+
+				/* Output */
+				&mode_lib->vba.BytePerPixelY[k],
+				&mode_lib->vba.BytePerPixelC[k],
+				&mode_lib->vba.BytePerPixelInDETY[k],
+				&mode_lib->vba.BytePerPixelInDETC[k],
+				&mode_lib->vba.Read256BlockHeightY[k],
+				&mode_lib->vba.Read256BlockHeightC[k],
+				&mode_lib->vba.Read256BlockWidthY[k],
+				&mode_lib->vba.Read256BlockWidthC[k],
+				&mode_lib->vba.MicroTileHeightY[k],
+				&mode_lib->vba.MicroTileHeightC[k],
+				&mode_lib->vba.MicroTileWidthY[k],
+				&mode_lib->vba.MicroTileWidthC[k]);
+	}
+
+	/*Bandwidth Support Check*/
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
+			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
+			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
+		} else {
+			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
+			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
+		}
+	}
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+		v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]
+				/ 2.0;
+	}
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) {
+			v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
+					* mode_lib->vba.WritebackDestinationHeight[k]
+					/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
+							/ mode_lib->vba.PixelClock[k]) * 8.0;
+		} else if (mode_lib->vba.WritebackEnable[k] == true) {
+			v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
+					* mode_lib->vba.WritebackDestinationHeight[k]
+					/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
+							/ mode_lib->vba.PixelClock[k]) * 4.0;
+		} else {
+			v->WriteBandwidth[k] = 0.0;
+		}
+	}
+
+	/*Writeback Latency support check*/
+
+	mode_lib->vba.WritebackLatencySupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true
+				&& (v->WriteBandwidth[k]
+						> mode_lib->vba.WritebackInterfaceBufferSize * 1024
+								/ mode_lib->vba.WritebackLatency)) {
+			mode_lib->vba.WritebackLatencySupport = false;
+		}
+	}
+
+	/*Writeback Mode Support Check*/
+	mode_lib->vba.EnoughWritebackUnits = true;
+	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true)
+			mode_lib->vba.TotalNumberOfActiveWriteback = mode_lib->vba.TotalNumberOfActiveWriteback + 1;
+	}
+
+	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback)
+		mode_lib->vba.EnoughWritebackUnits = false;
+
+	/*Writeback Scale Ratio and Taps Support Check*/
+	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.WritebackEnable[k] == true) {
+			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
+					|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackMaxVSCLRatio
+					|| mode_lib->vba.WritebackHRatio[k] < mode_lib->vba.WritebackMinHSCLRatio
+					|| mode_lib->vba.WritebackVRatio[k] < mode_lib->vba.WritebackMinVSCLRatio
+					|| mode_lib->vba.WritebackHTaps[k] > mode_lib->vba.WritebackMaxHSCLTaps
+					|| mode_lib->vba.WritebackVTaps[k] > mode_lib->vba.WritebackMaxVSCLTaps
+					|| mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackHTaps[k]
+					|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackVTaps[k]
+					|| (mode_lib->vba.WritebackHTaps[k] > 2.0
+							&& ((mode_lib->vba.WritebackHTaps[k] % 2) == 1))) {
+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
+			}
+			if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1)
+					* 57 > mode_lib->vba.WritebackLineBufferSize) {
+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
+			}
+		}
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], mode_lib->vba.HRatioChroma[k],
+				mode_lib->vba.VRatio[k], mode_lib->vba.VRatioChroma[k],
+				mode_lib->vba.MaxDCHUBToPSCLThroughput, mode_lib->vba.MaxPSCLToLBThroughput,
+				mode_lib->vba.PixelClock[k], mode_lib->vba.SourcePixelFormat[k],
+				mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k],
+				mode_lib->vba.VTAPsChroma[k],
+				/* Output */
+				&mode_lib->vba.PSCL_FACTOR[k], &mode_lib->vba.PSCL_FACTOR_CHROMA[k],
+				&mode_lib->vba.MinDPPCLKUsingSingleDPP[k]);
+	}
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+
+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 8192;
+		} else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 7680;
+		} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 4320;
+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3840;
+		} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 &&
+				mode_lib->vba.DCCEnable[k] == true) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3072;
+		} else {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 6144;
+		}
+
+		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10
+				|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12) {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0;
+		} else {
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma;
+		}
+		v->MaximumSwathWidthInLineBufferLuma = mode_lib->vba.LineBufferSizeFinal
+				* dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
+				/ (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->MaximumSwathWidthInLineBufferChroma = 0;
+		} else {
+			v->MaximumSwathWidthInLineBufferChroma = mode_lib->vba.LineBufferSizeFinal
+					* dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
+					/ (mode_lib->vba.VTAPsChroma[k]
+							+ dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
+									0.0));
+		}
+		v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
+				v->MaximumSwathWidthInLineBufferLuma);
+		v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
+				v->MaximumSwathWidthInLineBufferChroma);
+	}
+
+	/*Number Of DSC Slices*/
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			if (mode_lib->vba.PixelClockBackEnd[k] > 4800) {
+				mode_lib->vba.NumberOfDSCSlices[k] = dml_ceil(mode_lib->vba.PixelClockBackEnd[k] / 600,
+						4);
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 2400) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 8;
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1200) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 4;
+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340) {
+				mode_lib->vba.NumberOfDSCSlices[k] = 2;
+			} else {
+				mode_lib->vba.NumberOfDSCSlices[k] = 1;
+			}
+		} else {
+			mode_lib->vba.NumberOfDSCSlices[k] = 0;
+		}
+	}
+
+	dml32_CalculateSwathAndDETConfiguration(
+			mode_lib->vba.DETSizeOverride,
+			mode_lib->vba.UsesMALLForPStateChange,
+			mode_lib->vba.ConfigReturnBufferSizeInKByte,
+			mode_lib->vba.MaxTotalDETInKByte,
+			mode_lib->vba.MinCompressedBufferSizeInKByte,
+			1, /* ForceSingleDPP */
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.nomDETInKByte,
+			mode_lib->vba.UseUnboundedRequesting,
+			mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+			mode_lib->vba.Output,
+			mode_lib->vba.ReadBandwidthLuma,
+			mode_lib->vba.ReadBandwidthChroma,
+			mode_lib->vba.MaximumSwathWidthLuma,
+			mode_lib->vba.MaximumSwathWidthChroma,
+			mode_lib->vba.SourceRotation,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.SourcePixelFormat,
+			mode_lib->vba.SurfaceTiling,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.Read256BlockHeightY,
+			mode_lib->vba.Read256BlockHeightC,
+			mode_lib->vba.Read256BlockWidthY,
+			mode_lib->vba.Read256BlockWidthC,
+			dummy_odm_mode,
+			mode_lib->vba.BlendingAndTiming,
+			mode_lib->vba.BytePerPixelY,
+			mode_lib->vba.BytePerPixelC,
+			mode_lib->vba.BytePerPixelInDETY,
+			mode_lib->vba.BytePerPixelInDETC,
+			mode_lib->vba.HActive,
+			mode_lib->vba.HRatio,
+			mode_lib->vba.HRatioChroma,
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0], /*  Integer DPPPerSurface[] */
+
+			/* Output */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1], /* Long            swath_width_luma_ub[] */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2], /* Long            swath_width_chroma_ub[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[0], /* Long            SwathWidth[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[1], /* Long            SwathWidthChroma[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3], /* Integer         SwathHeightY[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4], /* Integer         SwathHeightC[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long            DETBufferSizeInKByte[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long            DETBufferSizeY[]  */
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long            DETBufferSizeC[]  */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0][0], /* bool           *UnboundedRequestEnabled  */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0][0], /* Long           *CompressedBufferSizeInkByte  */
+			mode_lib->vba.SingleDPPViewportSizeSupportPerSurface,/* bool ViewportSizeSupportPerSurface[] */
+			&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1][0]); /* bool           *ViewportSizeSupport */
+
+	MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
+	MPCCombineMethodAsPossible = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_reduce_voltage_and_clocks)
+			MPCCombineMethodAsNeededForPStateChangeAndVoltage = true;
+		if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_always_when_possible)
+			MPCCombineMethodAsPossible = true;
+	}
+	mode_lib->vba.MPCCombineMethodIncompatible = MPCCombineMethodAsNeededForPStateChangeAndVoltage
+			&& MPCCombineMethodAsPossible;
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			bool NoChroma;
+			mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;
+			mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+
+				bool TotalAvailablePipesSupportNoDSC;
+				unsigned int NumberOfDPPNoDSC;
+				enum odm_combine_mode ODMModeNoDSC = dm_odm_combine_mode_disabled;
+				double RequiredDISPCLKPerSurfaceNoDSC;
+				bool TotalAvailablePipesSupportDSC;
+				unsigned int NumberOfDPPDSC;
+				enum odm_combine_mode ODMModeDSC = dm_odm_combine_mode_disabled;
+				double RequiredDISPCLKPerSurfaceDSC;
+
+				dml32_CalculateODMMode(
+						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.Output[k],
+						mode_lib->vba.ODMUse[k],
+						mode_lib->vba.MaxDispclk[i],
+						mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
+						false,
+						mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+						mode_lib->vba.MaxNumDPP,
+						mode_lib->vba.PixelClock[k],
+						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+						mode_lib->vba.DISPCLKRampingMargin,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
+						/* Output */
+						&TotalAvailablePipesSupportNoDSC,
+						&NumberOfDPPNoDSC,
+						&ODMModeNoDSC,
+						&RequiredDISPCLKPerSurfaceNoDSC);
+
+				dml32_CalculateODMMode(
+						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.Output[k],
+						mode_lib->vba.ODMUse[k],
+						mode_lib->vba.MaxDispclk[i],
+						mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
+						true,
+						mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+						mode_lib->vba.MaxNumDPP,
+						mode_lib->vba.PixelClock[k],
+						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+						mode_lib->vba.DISPCLKRampingMargin,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
+						/* Output */
+						&TotalAvailablePipesSupportDSC,
+						&NumberOfDPPDSC,
+						&ODMModeDSC,
+						&RequiredDISPCLKPerSurfaceDSC);
+
+				dml32_CalculateOutputLink(
+						mode_lib->vba.PHYCLKPerState[i],
+						mode_lib->vba.PHYCLKD18PerState[i],
+						mode_lib->vba.PHYCLKD32PerState[i],
+						mode_lib->vba.Downspreading,
+						(mode_lib->vba.BlendingAndTiming[k] == k),
+						mode_lib->vba.Output[k],
+						mode_lib->vba.OutputFormat[k],
+						mode_lib->vba.HTotal[k],
+						mode_lib->vba.HActive[k],
+						mode_lib->vba.PixelClockBackEnd[k],
+						mode_lib->vba.ForcedOutputLinkBPP[k],
+						mode_lib->vba.DSCInputBitPerComponent[k],
+						mode_lib->vba.NumberOfDSCSlices[k],
+						mode_lib->vba.AudioSampleRate[k],
+						mode_lib->vba.AudioSampleLayout[k],
+						ODMModeNoDSC,
+						ODMModeDSC,
+						mode_lib->vba.DSCEnable[k],
+						mode_lib->vba.OutputLinkDPLanes[k],
+						mode_lib->vba.OutputLinkDPRate[k],
+
+						/* Output */
+						&mode_lib->vba.RequiresDSC[i][k],
+						&mode_lib->vba.RequiresFEC[i][k],
+						&mode_lib->vba.OutputBppPerState[i][k],
+						&mode_lib->vba.OutputTypePerState[i][k],
+						&mode_lib->vba.OutputRatePerState[i][k],
+						&mode_lib->vba.RequiredSlots[i][k]);
+
+				if (mode_lib->vba.RequiresDSC[i][k] == false) {
+					mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeNoDSC;
+					mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
+							RequiredDISPCLKPerSurfaceNoDSC;
+					if (!TotalAvailablePipesSupportNoDSC)
+						mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPNoDSC;
+				} else {
+					mode_lib->vba.ODMCombineEnablePerState[i][k] = ODMModeDSC;
+					mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
+							RequiredDISPCLKPerSurfaceDSC;
+					if (!TotalAvailablePipesSupportDSC)
+						mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + NumberOfDPPDSC;
+				}
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 4;
+				} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 2;
+				} else if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_never) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+				} else if (dml32_RoundToDFSGranularity(
+						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
+								* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
+												/ 100), 1,
+						mode_lib->vba.DISPCLKDPPCLKVCOSpeed) <= mode_lib->vba.MaxDppclk[i] &&
+				mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+				} else if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP) {
+					mode_lib->vba.MPCCombine[i][j][k] = true;
+					mode_lib->vba.NoOfDPP[i][j][k] = 2;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1;
+				} else {
+					mode_lib->vba.MPCCombine[i][j][k] = false;
+					mode_lib->vba.NoOfDPP[i][j][k] = 1;
+					mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+				}
+			}
+
+			mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] = 0;
+			NoChroma = true;
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.NoOfDPP[i][j][k] == 1)
+					mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] =
+							mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] + 1;
+				if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_420_10
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12
+						|| mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
+					NoChroma = false;
+				}
+			}
+
+			if (j == 1 && !dml32_UnboundedRequest(mode_lib->vba.UseUnboundedRequesting,
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j], NoChroma,
+							mode_lib->vba.Output[0])) {
+				while (!(mode_lib->vba.TotalNumberOfActiveDPP[i][j] >= mode_lib->vba.MaxNumDPP
+						|| mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] == 0)) {
+					double BWOfNonCombinedSurfaceOfMaximumBandwidth = 0;
+					unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth = 0;
+
+					for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+						if (mode_lib->vba.MPCCombineUse[k]
+							!= dm_mpc_never &&
+							mode_lib->vba.MPCCombineUse[k] != dm_mpc_reduce_voltage &&
+							mode_lib->vba.ReadBandwidthLuma[k] +
+							mode_lib->vba.ReadBandwidthChroma[k] >
+							BWOfNonCombinedSurfaceOfMaximumBandwidth &&
+							(mode_lib->vba.ODMCombineEnablePerState[i][k] !=
+							dm_odm_combine_mode_2to1 &&
+							mode_lib->vba.ODMCombineEnablePerState[i][k] !=
+							dm_odm_combine_mode_4to1) &&
+								mode_lib->vba.MPCCombine[i][j][k] == false) {
+							BWOfNonCombinedSurfaceOfMaximumBandwidth =
+								mode_lib->vba.ReadBandwidthLuma[k]
+								+ mode_lib->vba.ReadBandwidthChroma[k];
+							NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
+						}
+					}
+					mode_lib->vba.MPCCombine[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] =
+							true;
+					mode_lib->vba.NoOfDPP[i][j][NumberOfNonCombinedSurfaceOfMaximumBandwidth] = 2;
+					mode_lib->vba.TotalNumberOfActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfActiveDPP[i][j] + 1;
+					mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] =
+							mode_lib->vba.TotalNumberOfSingleDPPSurfaces[i][j] - 1;
+				}
+			}
+
+			//DISPCLK/DPPCLK
+			mode_lib->vba.WritebackRequiredDISPCLK = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.WritebackEnable[k]) {
+					mode_lib->vba.WritebackRequiredDISPCLK = dml_max(
+							mode_lib->vba.WritebackRequiredDISPCLK,
+							dml32_CalculateWriteBackDISPCLK(
+									mode_lib->vba.WritebackPixelFormat[k],
+									mode_lib->vba.PixelClock[k],
+									mode_lib->vba.WritebackHRatio[k],
+									mode_lib->vba.WritebackVRatio[k],
+									mode_lib->vba.WritebackHTaps[k],
+									mode_lib->vba.WritebackVTaps[k],
+									mode_lib->vba.WritebackSourceWidth[k],
+									mode_lib->vba.WritebackDestinationWidth[k],
+									mode_lib->vba.HTotal[k],
+									mode_lib->vba.WritebackLineBufferSize,
+									mode_lib->vba.DISPCLKDPPCLKVCOSpeed));
+				}
+			}
+
+			mode_lib->vba.RequiredDISPCLK[i][j] = mode_lib->vba.WritebackRequiredDISPCLK;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.RequiredDISPCLK[i][j] = dml_max(mode_lib->vba.RequiredDISPCLK[i][j],
+						mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k]);
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+
+			dml32_CalculateDPPCLK(mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
+					mode_lib->vba.DISPCLKDPPCLKVCOSpeed, mode_lib->vba.MinDPPCLKUsingSingleDPP,
+					mode_lib->vba.NoOfDPPThisState,
+					/* Output */
+					&mode_lib->vba.GlobalDPPCLK, mode_lib->vba.RequiredDPPCLKThisState);
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+				mode_lib->vba.RequiredDPPCLK[i][j][k] = mode_lib->vba.RequiredDPPCLKThisState[k];
+
+			mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] = !((mode_lib->vba.RequiredDISPCLK[i][j]
+					> mode_lib->vba.MaxDispclk[i])
+					|| (mode_lib->vba.GlobalDPPCLK > mode_lib->vba.MaxDppclk[i]));
+
+			if (mode_lib->vba.TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP)
+				mode_lib->vba.TotalAvailablePipesSupport[i][j] = false;
+		} // j
+	} // i (VOLTAGE_STATE)
+
+	/* Total Available OTG, HDMIFRL, DP Support Check */
+	TotalNumberOfActiveOTG = 0;
+	TotalNumberOfActiveHDMIFRL = 0;
+	TotalNumberOfActiveDP2p0 = 0;
+	TotalNumberOfActiveDP2p0Outputs = 0;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+			if (mode_lib->vba.Output[k] == dm_dp2p0) {
+				TotalNumberOfActiveDP2p0 = TotalNumberOfActiveDP2p0 + 1;
+				if (mode_lib->vba.OutputMultistreamId[k]
+						== k || mode_lib->vba.OutputMultistreamEn[k] == false) {
+					TotalNumberOfActiveDP2p0Outputs = TotalNumberOfActiveDP2p0Outputs + 1;
+				}
+			}
+		}
+	}
+
+	mode_lib->vba.NumberOfOTGSupport = (TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG);
+	mode_lib->vba.NumberOfHDMIFRLSupport = (TotalNumberOfActiveHDMIFRL <= mode_lib->vba.MaxNumHDMIFRLOutputs);
+	mode_lib->vba.NumberOfDP2p0Support = (TotalNumberOfActiveDP2p0 <= mode_lib->vba.MaxNumDP2p0Streams
+			&& TotalNumberOfActiveDP2p0Outputs <= mode_lib->vba.MaxNumDP2p0Outputs);
+
+	/* Display IO and DSC Support Check */
+	mode_lib->vba.NonsupportedDSCInputBPC = false;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0
+				|| mode_lib->vba.DSCInputBitPerComponent[k] >
+				mode_lib->vba.MaximumDSCBitsPerComponent)) {
+			mode_lib->vba.NonsupportedDSCInputBPC = true;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		unsigned int TotalSlots;
+
+		mode_lib->vba.ExceededMultistreamSlots[i] = false;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
+				TotalSlots = mode_lib->vba.RequiredSlots[i][k];
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamId[j] == k)
+						TotalSlots = TotalSlots + mode_lib->vba.RequiredSlots[i][j];
+				}
+				if (mode_lib->vba.Output[k] == dm_dp && TotalSlots > 63)
+					mode_lib->vba.ExceededMultistreamSlots[i] = true;
+				if (mode_lib->vba.Output[k] == dm_dp2p0 && TotalSlots > 64)
+					mode_lib->vba.ExceededMultistreamSlots[i] = true;
+			}
+		}
+		mode_lib->vba.LinkCapacitySupport[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+							|| mode_lib->vba.Output[k] == dm_edp
+							|| mode_lib->vba.Output[k] == dm_hdmi)
+					&& mode_lib->vba.OutputBppPerState[i][k] == 0) {
+				mode_lib->vba.LinkCapacitySupport[i] = false;
+			}
+		}
+	}
+
+	mode_lib->vba.P2IWith420 = false;
+	mode_lib->vba.DSCOnlyIfNecessaryWithBPP = false;
+	mode_lib->vba.DSC422NativeNotSupported = false;
+	mode_lib->vba.LinkRateDoesNotMatchDPVersion = false;
+	mode_lib->vba.LinkRateForMultistreamNotIndicated = false;
+	mode_lib->vba.BPPForMultistreamNotIndicated = false;
+	mode_lib->vba.MultistreamWithHDMIOreDP = false;
+	mode_lib->vba.MSOOrODMSplitWithNonDPLink = false;
+	mode_lib->vba.NotEnoughLanesForMSO = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k
+				&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+						|| mode_lib->vba.Output[k] == dm_edp
+						|| mode_lib->vba.Output[k] == dm_hdmi)) {
+			if (mode_lib->vba.OutputFormat[k]
+					== dm_420 && mode_lib->vba.Interlace[k] == 1 &&
+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)
+				mode_lib->vba.P2IWith420 = true;
+
+			if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0)
+				mode_lib->vba.DSCOnlyIfNecessaryWithBPP = true;
+			if ((mode_lib->vba.DSCEnable[k] || mode_lib->vba.DSCEnable[k])
+					&& mode_lib->vba.OutputFormat[k] == dm_n422
+					&& !mode_lib->vba.DSC422NativeSupport)
+				mode_lib->vba.DSC422NativeNotSupported = true;
+
+			if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr
+					|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2
+					|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3)
+					&& mode_lib->vba.Output[k] != dm_dp && mode_lib->vba.Output[k] != dm_edp)
+					|| ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10
+							|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5
+							|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20)
+							&& mode_lib->vba.Output[k] != dm_dp2p0))
+				mode_lib->vba.LinkRateDoesNotMatchDPVersion = true;
+
+			if (mode_lib->vba.OutputMultistreamEn[k] == true) {
+				if (mode_lib->vba.OutputMultistreamId[k] == k
+					&& mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na)
+					mode_lib->vba.LinkRateForMultistreamNotIndicated = true;
+				if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
+					mode_lib->vba.BPPForMultistreamNotIndicated = true;
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamId[k] == j && mode_lib->vba.OutputMultistreamEn[k]
+						&& mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
+						mode_lib->vba.BPPForMultistreamNotIndicated = true;
+				}
+			}
+
+			if ((mode_lib->vba.Output[k] == dm_edp || mode_lib->vba.Output[k] == dm_hdmi)) {
+				if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.OutputMultistreamEn[k])
+					mode_lib->vba.MultistreamWithHDMIOreDP = true;
+
+				for (j = 0; j < mode_lib->vba.NumberOfActiveSurfaces; ++j) {
+					if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j)
+						mode_lib->vba.MultistreamWithHDMIOreDP = true;
+				}
+			}
+
+			if (mode_lib->vba.Output[k] != dm_dp
+					&& (mode_lib->vba.ODMUse[k] == dm_odm_split_policy_1to2
+							|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
+							|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4))
+				mode_lib->vba.MSOOrODMSplitWithNonDPLink = true;
+
+			if ((mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
+					&& mode_lib->vba.OutputLinkDPLanes[k] < 2)
+					|| (mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4
+							&& mode_lib->vba.OutputLinkDPLanes[k] < 4))
+				mode_lib->vba.NotEnoughLanesForMSO = true;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& dml32_RequiredDTBCLK(mode_lib->vba.RequiresDSC[i][k],
+							mode_lib->vba.PixelClockBackEnd[k],
+							mode_lib->vba.OutputFormat[k],
+							mode_lib->vba.OutputBppPerState[i][k],
+							mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.HTotal[k],
+							mode_lib->vba.HActive[k], mode_lib->vba.AudioSampleRate[k],
+							mode_lib->vba.AudioSampleLayout[k])
+							> mode_lib->vba.DTBCLKPerState[i]) {
+				mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = true;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;
+		mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1
+					&& mode_lib->vba.Output[k] == dm_hdmi) {
+				mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = false;
+			}
+			if (mode_lib->vba.BlendingAndTiming[k] == k
+					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+					&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_edp
+							|| mode_lib->vba.Output[k] == dm_hdmi)) {
+				mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = false;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
+		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
+				if (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
+						|| mode_lib->vba.Output[k] == dm_edp) {
+					if (mode_lib->vba.OutputFormat[k] == dm_420) {
+						mode_lib->vba.DSCFormatFactor = 2;
+					} else if (mode_lib->vba.OutputFormat[k] == dm_444) {
+						mode_lib->vba.DSCFormatFactor = 1;
+					} else if (mode_lib->vba.OutputFormat[k] == dm_n422) {
+						mode_lib->vba.DSCFormatFactor = 2;
+					} else {
+						mode_lib->vba.DSCFormatFactor = 1;
+					}
+					if (mode_lib->vba.RequiresDSC[i][k] == true) {
+						if (mode_lib->vba.ODMCombineEnablePerState[i][k]
+								== dm_odm_combine_mode_4to1) {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						} else if (mode_lib->vba.ODMCombineEnablePerState[i][k]
+								== dm_odm_combine_mode_2to1) {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						} else {
+							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = true;
+						}
+					}
+				}
+			}
+		}
+	}
+
+	/* Check DSC Unit and Slices Support */
+	TotalDSCUnitsRequired = 0;
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		mode_lib->vba.NotEnoughDSCUnits[i] = false;
+		mode_lib->vba.NotEnoughDSCSlices[i] = false;
+		TotalDSCUnitsRequired = 0;
+		mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = true;
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			if (mode_lib->vba.RequiresDSC[i][k] == true) {
+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					if (mode_lib->vba.HActive[k]
+							> 4 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 4;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 16)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					if (mode_lib->vba.HActive[k]
+							> 2 * mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 2;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 8)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				} else {
+					if (mode_lib->vba.HActive[k] > mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
+						mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i] = false;
+					TotalDSCUnitsRequired = TotalDSCUnitsRequired + 1;
+					if (mode_lib->vba.NumberOfDSCSlices[k] > 4)
+						mode_lib->vba.NotEnoughDSCSlices[i] = true;
+				}
+			}
+		}
+		if (TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC)
+			mode_lib->vba.NotEnoughDSCUnits[i] = true;
+	}
+
+	/*DSC Delay per state*/
+	for (i = 0; i < v->soc.num_states; ++i) {
+		unsigned int m;
+
+		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+			mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
+					mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
+					mode_lib->vba.DSCInputBitPerComponent[k],
+					mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],
+					mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],
+					mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],
+					mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k]);
+		}
+
+		m = 0;
+
+		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+			for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+				for (j = 0; j <= mode_lib->vba.NumberOfActiveSurfaces - 1; j++) {
+					if (mode_lib->vba.BlendingAndTiming[k] == m &&
+							mode_lib->vba.RequiresDSC[i][m] == true) {
+						mode_lib->vba.DSCDelayPerState[i][k] =
+							mode_lib->vba.DSCDelayPerState[i][m];
+					}
+				}
+			}
+		}
+	}
+
+	//Calculate Swath, DET Configuration, DCFCLKDeepSleep
+	//
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+				mode_lib->vba.ODMCombineEnableThisState[k] =
+						mode_lib->vba.ODMCombineEnablePerState[i][k];
+			}
+
+			dml32_CalculateSwathAndDETConfiguration(
+					mode_lib->vba.DETSizeOverride,
+					mode_lib->vba.UsesMALLForPStateChange,
+					mode_lib->vba.ConfigReturnBufferSizeInKByte,
+					mode_lib->vba.MaxTotalDETInKByte,
+					mode_lib->vba.MinCompressedBufferSizeInKByte,
+					false, /* ForceSingleDPP */
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.nomDETInKByte,
+					mode_lib->vba.UseUnboundedRequesting,
+					mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal,
+					mode_lib->vba.Output,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.MaximumSwathWidthLuma,
+					mode_lib->vba.MaximumSwathWidthChroma,
+					mode_lib->vba.SourceRotation,
+					mode_lib->vba.ViewportStationary,
+					mode_lib->vba.SourcePixelFormat,
+					mode_lib->vba.SurfaceTiling,
+					mode_lib->vba.ViewportWidth,
+					mode_lib->vba.ViewportHeight,
+					mode_lib->vba.ViewportXStartY,
+					mode_lib->vba.ViewportYStartY,
+					mode_lib->vba.ViewportXStartC,
+					mode_lib->vba.ViewportYStartC,
+					mode_lib->vba.SurfaceWidthY,
+					mode_lib->vba.SurfaceWidthC,
+					mode_lib->vba.SurfaceHeightY,
+					mode_lib->vba.SurfaceHeightC,
+					mode_lib->vba.Read256BlockHeightY,
+					mode_lib->vba.Read256BlockHeightC,
+					mode_lib->vba.Read256BlockWidthY,
+					mode_lib->vba.Read256BlockWidthC,
+					mode_lib->vba.ODMCombineEnableThisState,
+					mode_lib->vba.BlendingAndTiming,
+					mode_lib->vba.BytePerPixelY,
+					mode_lib->vba.BytePerPixelC,
+					mode_lib->vba.BytePerPixelInDETY,
+					mode_lib->vba.BytePerPixelInDETC,
+					mode_lib->vba.HActive,
+					mode_lib->vba.HRatio,
+					mode_lib->vba.HRatioChroma,
+					mode_lib->vba.NoOfDPPThisState,
+					/* Output */
+					mode_lib->vba.swath_width_luma_ub_this_state,
+					mode_lib->vba.swath_width_chroma_ub_this_state,
+					mode_lib->vba.SwathWidthYThisState,
+					mode_lib->vba.SwathWidthCThisState,
+					mode_lib->vba.SwathHeightYThisState,
+					mode_lib->vba.SwathHeightCThisState,
+					mode_lib->vba.DETBufferSizeInKByteThisState,
+					mode_lib->vba.DETBufferSizeYThisState,
+					mode_lib->vba.DETBufferSizeCThisState,
+					&mode_lib->vba.UnboundedRequestEnabledThisState,
+					&mode_lib->vba.CompressedBufferSizeInkByteThisState,
+					v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0],
+					&mode_lib->vba.ViewportSizeSupport[i][j]);
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.swath_width_luma_ub_all_states[i][j][k] =
+						mode_lib->vba.swath_width_luma_ub_this_state[k];
+				mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] =
+						mode_lib->vba.swath_width_chroma_ub_this_state[k];
+				mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k];
+				mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k];
+				mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k];
+				mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k];
+				mode_lib->vba.UnboundedRequestEnabledAllStates[i][j] =
+						mode_lib->vba.UnboundedRequestEnabledThisState;
+				mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j] =
+						mode_lib->vba.CompressedBufferSizeInkByteThisState;
+				mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeInKByteThisState[k];
+				mode_lib->vba.DETBufferSizeYAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeYThisState[k];
+				mode_lib->vba.DETBufferSizeCAllStates[i][j][k] =
+						mode_lib->vba.DETBufferSizeCThisState[k];
+			}
+		}
+	}
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0]
+				* mode_lib->vba.CursorBPP[k][0] / 8.0
+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
+	}
+
+	dml32_CalculateSurfaceSizeInMall(
+			mode_lib->vba.NumberOfActiveSurfaces,
+			mode_lib->vba.MALLAllocatedForDCNFinal,
+			mode_lib->vba.UseMALLForStaticScreen,
+			mode_lib->vba.DCCEnable,
+			mode_lib->vba.ViewportStationary,
+			mode_lib->vba.ViewportXStartY,
+			mode_lib->vba.ViewportYStartY,
+			mode_lib->vba.ViewportXStartC,
+			mode_lib->vba.ViewportYStartC,
+			mode_lib->vba.ViewportWidth,
+			mode_lib->vba.ViewportHeight,
+			mode_lib->vba.BytePerPixelY,
+			mode_lib->vba.ViewportWidthChroma,
+			mode_lib->vba.ViewportHeightChroma,
+			mode_lib->vba.BytePerPixelC,
+			mode_lib->vba.SurfaceWidthY,
+			mode_lib->vba.SurfaceWidthC,
+			mode_lib->vba.SurfaceHeightY,
+			mode_lib->vba.SurfaceHeightC,
+			mode_lib->vba.Read256BlockWidthY,
+			mode_lib->vba.Read256BlockWidthC,
+			mode_lib->vba.Read256BlockHeightY,
+			mode_lib->vba.Read256BlockHeightC,
+			mode_lib->vba.MicroTileWidthY,
+			mode_lib->vba.MicroTileWidthC,
+			mode_lib->vba.MicroTileHeightY,
+			mode_lib->vba.MicroTileHeightC,
+
+			/* Output */
+			mode_lib->vba.SurfaceSizeInMALL,
+			&mode_lib->vba.ExceededMALLSize);
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				mode_lib->vba.swath_width_luma_ub_this_state[k] =
+						mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
+				mode_lib->vba.swath_width_chroma_ub_this_state[k] =
+						mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
+				mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
+				mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
+				mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
+				mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeInKByteThisState[k] =
+						mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeYThisState[k] =
+						mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeCThisState[k] =
+						mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
+				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+			}
+
+			mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] = 0;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.DCCEnable[k] == true) {
+					mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j] =
+							mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j]
+									+ mode_lib->vba.NoOfDPP[i][j][k];
+				}
+			}
+
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP =
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k];
+			}
+
+			{
+				dml32_CalculateVMRowAndSwath(
+						mode_lib->vba.NumberOfActiveSurfaces,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters,
+						mode_lib->vba.SurfaceSizeInMALL,
+						mode_lib->vba.PTEBufferSizeInRequestsLuma,
+						mode_lib->vba.PTEBufferSizeInRequestsChroma,
+						mode_lib->vba.DCCMetaBufferSizeBytes,
+						mode_lib->vba.UseMALLForStaticScreen,
+						mode_lib->vba.UsesMALLForPStateChange,
+						mode_lib->vba.MALLAllocatedForDCNFinal,
+						mode_lib->vba.SwathWidthYThisState,
+						mode_lib->vba.SwathWidthCThisState,
+						mode_lib->vba.GPUVMEnable,
+						mode_lib->vba.HostVMEnable,
+						mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+						mode_lib->vba.GPUVMMaxPageTableLevels,
+						mode_lib->vba.GPUVMMinPageSizeKBytes,
+						mode_lib->vba.HostVMMinPageSize,
+
+						/* Output */
+						mode_lib->vba.PTEBufferSizeNotExceededPerState,
+						mode_lib->vba.DCCMetaBufferSizeNotExceededPerState,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1],
+						mode_lib->vba.dpte_row_height,
+						mode_lib->vba.dpte_row_height_chroma,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[8],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[9],
+						mode_lib->vba.meta_row_height,
+						mode_lib->vba.meta_row_height_chroma,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[10],
+						mode_lib->vba.dpte_group_bytes,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[11],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[12],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[13],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[14],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[15],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[16],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[17],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[18],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[19],
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[20],
+						mode_lib->vba.PrefetchLinesYThisState,
+						mode_lib->vba.PrefetchLinesCThisState,
+						mode_lib->vba.PrefillY,
+						mode_lib->vba.PrefillC,
+						mode_lib->vba.MaxNumSwY,
+						mode_lib->vba.MaxNumSwC,
+						mode_lib->vba.meta_row_bandwidth_this_state,
+						mode_lib->vba.dpte_row_bandwidth_this_state,
+						mode_lib->vba.DPTEBytesPerRowThisState,
+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState,
+						mode_lib->vba.MetaRowBytesThisState,
+						mode_lib->vba.use_one_row_for_frame_this_state,
+						mode_lib->vba.use_one_row_for_frame_flip_this_state,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[]
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[]
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[]
+			}
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.PrefetchLinesY[i][j][k] = mode_lib->vba.PrefetchLinesYThisState[k];
+				mode_lib->vba.PrefetchLinesC[i][j][k] = mode_lib->vba.PrefetchLinesCThisState[k];
+				mode_lib->vba.meta_row_bandwidth[i][j][k] =
+						mode_lib->vba.meta_row_bandwidth_this_state[k];
+				mode_lib->vba.dpte_row_bandwidth[i][j][k] =
+						mode_lib->vba.dpte_row_bandwidth_this_state[k];
+				mode_lib->vba.DPTEBytesPerRow[i][j][k] = mode_lib->vba.DPTEBytesPerRowThisState[k];
+				mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] =
+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState[k];
+				mode_lib->vba.MetaRowBytes[i][j][k] = mode_lib->vba.MetaRowBytesThisState[k];
+				mode_lib->vba.use_one_row_for_frame[i][j][k] =
+						mode_lib->vba.use_one_row_for_frame_this_state[k];
+				mode_lib->vba.use_one_row_for_frame_flip[i][j][k] =
+						mode_lib->vba.use_one_row_for_frame_flip_this_state[k];
+			}
+
+			mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false)
+					mode_lib->vba.PTEBufferSizeNotExceeded[i][j] = false;
+			}
+
+			mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false)
+					mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] = false;
+			}
+
+			mode_lib->vba.UrgLatency[i] = dml32_CalculateUrgentLatency(
+					mode_lib->vba.UrgentLatencyPixelDataOnly,
+					mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
+					mode_lib->vba.UrgentLatencyVMDataOnly, mode_lib->vba.DoUrgentLatencyAdjustment,
+					mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent,
+					mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference,
+					mode_lib->vba.FabricClockPerState[i]);
+
+			//bool   NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				dml32_CalculateUrgentBurstFactor(
+						mode_lib->vba.UsesMALLForPStateChange[k],
+						mode_lib->vba.swath_width_luma_ub_this_state[k],
+						mode_lib->vba.swath_width_chroma_ub_this_state[k],
+						mode_lib->vba.SwathHeightYThisState[k],
+						mode_lib->vba.SwathHeightCThisState[k],
+						(double) mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+						mode_lib->vba.UrgLatency[i],
+						mode_lib->vba.CursorBufferSize,
+						mode_lib->vba.CursorWidth[k][0],
+						mode_lib->vba.CursorBPP[k][0],
+						mode_lib->vba.VRatio[k],
+						mode_lib->vba.VRatioChroma[k],
+						mode_lib->vba.BytePerPixelInDETY[k],
+						mode_lib->vba.BytePerPixelInDETC[k],
+						mode_lib->vba.DETBufferSizeYThisState[k],
+						mode_lib->vba.DETBufferSizeCThisState[k],
+						/* Output */
+						&mode_lib->vba.UrgentBurstFactorCursor[k],
+						&mode_lib->vba.UrgentBurstFactorLuma[k],
+						&mode_lib->vba.UrgentBurstFactorChroma[k],
+						&mode_lib->vba.NoUrgentLatencyHiding[k]);
+			}
+
+			dml32_CalculateDCFCLKDeepSleep(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.BytePerPixelY,
+					mode_lib->vba.BytePerPixelC,
+					mode_lib->vba.VRatio,
+					mode_lib->vba.VRatioChroma,
+					mode_lib->vba.SwathWidthYThisState,
+					mode_lib->vba.SwathWidthCThisState,
+					mode_lib->vba.NoOfDPPThisState,
+					mode_lib->vba.HRatio,
+					mode_lib->vba.HRatioChroma,
+					mode_lib->vba.PixelClock,
+					mode_lib->vba.PSCL_FACTOR,
+					mode_lib->vba.PSCL_FACTOR_CHROMA,
+					mode_lib->vba.RequiredDPPCLKThisState,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.ReturnBusWidth,
+
+					/* Output */
+					&mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j]);
+		}
+	}
+
+	m = 0;
+
+	//Calculate Return BW
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				if (mode_lib->vba.BlendingAndTiming[k] == k) {
+					if (mode_lib->vba.WritebackEnable[k] == true) {
+						mode_lib->vba.WritebackDelayTime[k] =
+							mode_lib->vba.WritebackLatency
+						+ dml32_CalculateWriteBackDelay(
+							mode_lib->vba.WritebackPixelFormat[k],
+							mode_lib->vba.WritebackHRatio[k],
+							mode_lib->vba.WritebackVRatio[k],
+							mode_lib->vba.WritebackVTaps[k],
+							mode_lib->vba.WritebackDestinationWidth[k],
+							mode_lib->vba.WritebackDestinationHeight[k],
+							mode_lib->vba.WritebackSourceHeight[k],
+							mode_lib->vba.HTotal[k])
+							/ mode_lib->vba.RequiredDISPCLK[i][j];
+					} else {
+						mode_lib->vba.WritebackDelayTime[k] = 0.0;
+					}
+					for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+						if (mode_lib->vba.BlendingAndTiming[m]
+								== k && mode_lib->vba.WritebackEnable[m] == true) {
+							mode_lib->vba.WritebackDelayTime[k] =
+								dml_max(mode_lib->vba.WritebackDelayTime[k],
+									mode_lib->vba.WritebackLatency
+								+ dml32_CalculateWriteBackDelay(
+									mode_lib->vba.WritebackPixelFormat[m],
+									mode_lib->vba.WritebackHRatio[m],
+									mode_lib->vba.WritebackVRatio[m],
+									mode_lib->vba.WritebackVTaps[m],
+									mode_lib->vba.WritebackDestinationWidth[m],
+									mode_lib->vba.WritebackDestinationHeight[m],
+									mode_lib->vba.WritebackSourceHeight[m],
+									mode_lib->vba.HTotal[m]) /
+									mode_lib->vba.RequiredDISPCLK[i][j]);
+						}
+					}
+				}
+			}
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				for (m = 0; m <= mode_lib->vba.NumberOfActiveSurfaces - 1; m++) {
+					if (mode_lib->vba.BlendingAndTiming[k] == m) {
+						mode_lib->vba.WritebackDelayTime[k] =
+								mode_lib->vba.WritebackDelayTime[m];
+					}
+				}
+			}
+			mode_lib->vba.MaxMaxVStartup[i][j] = 0;
+			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+				mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] &&
+								!mode_lib->vba.ProgressiveToInterlaceUnitInOPP) ?
+								dml_floor((mode_lib->vba.VTotal[k] -
+									mode_lib->vba.VActive[k]) / 2.0, 1.0) :
+								mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k])
+								- dml_max(1.0, dml_ceil(1.0 *
+									mode_lib->vba.WritebackDelayTime[k] /
+									(mode_lib->vba.HTotal[k] /
+									mode_lib->vba.PixelClock[k]), 1.0));
+
+				// Clamp to max OTG vstartup register limit
+				if (mode_lib->vba.MaximumVStartup[i][j][k] > 1023)
+					mode_lib->vba.MaximumVStartup[i][j][k] = 1023;
+
+				mode_lib->vba.MaxMaxVStartup[i][j] = dml_max(mode_lib->vba.MaxMaxVStartup[i][j],
+						mode_lib->vba.MaximumVStartup[i][j][k]);
+			}
+		}
+	}
+
+	ReorderingBytes = mode_lib->vba.NumberOfChannels
+			* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	dml32_CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal,
+			&mode_lib->vba.MinPrefetchMode,
+			&mode_lib->vba.MaxPrefetchMode);
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j)
+			mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];
+	}
+
+	/* Immediate Flip and MALL parameters */
+	mode_lib->vba.ImmediateFlipRequiredFinal = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipRequiredFinal = mode_lib->vba.ImmediateFlipRequiredFinal
+				|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
+	}
+
+	mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified =
+				mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+						|| ((mode_lib->vba.ImmediateFlipRequirement[k]
+								!= dm_immediate_flip_required)
+								&& (mode_lib->vba.ImmediateFlipRequirement[k]
+										!= dm_immediate_flip_not_required));
+	}
+	mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified =
+			mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+					&& mode_lib->vba.ImmediateFlipRequiredFinal;
+
+	mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe =
+			mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe ||
+			((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] !=
+					dm_immediate_flip_not_required) &&
+			(mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame ||
+			mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe));
+	}
+
+	mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen =
+			mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
+			|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable
+			|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
+			&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe))
+			|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_disable
+			|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
+			&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame));
+	}
+
+	FullFrameMALLPStateMethod = false;
+	SubViewportMALLPStateMethod = false;
+	PhantomPipeMALLPStateMethod = false;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
+			FullFrameMALLPStateMethod = true;
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
+			SubViewportMALLPStateMethod = true;
+		if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
+			PhantomPipeMALLPStateMethod = true;
+	}
+	mode_lib->vba.InvalidCombinationOfMALLUseForPState = (SubViewportMALLPStateMethod
+			!= PhantomPipeMALLPStateMethod) || (SubViewportMALLPStateMethod && FullFrameMALLPStateMethod);
+
+	if (mode_lib->vba.UseMinimumRequiredDCFCLK == true) {
+		dml32_UseMinimumDCFCLK(
+				mode_lib->vba.UsesMALLForPStateChange,
+				mode_lib->vba.DRRDisplay,
+				mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+				mode_lib->vba.MaxInterDCNTileRepeaters,
+				mode_lib->vba.MaxPrefetchMode,
+				mode_lib->vba.DRAMClockChangeLatency,
+				mode_lib->vba.FCLKChangeLatency,
+				mode_lib->vba.SREnterPlusExitTime,
+				mode_lib->vba.ReturnBusWidth,
+				mode_lib->vba.RoundTripPingLatencyCycles,
+				ReorderingBytes,
+				mode_lib->vba.PixelChunkSizeInKByte,
+				mode_lib->vba.MetaChunkSize,
+				mode_lib->vba.GPUVMEnable,
+				mode_lib->vba.GPUVMMaxPageTableLevels,
+				mode_lib->vba.HostVMEnable,
+				mode_lib->vba.NumberOfActiveSurfaces,
+				mode_lib->vba.HostVMMinPageSize,
+				mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+				mode_lib->vba.DynamicMetadataVMEnabled,
+				mode_lib->vba.ImmediateFlipRequiredFinal,
+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
+				mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+				mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+				mode_lib->vba.VTotal,
+				mode_lib->vba.VActive,
+				mode_lib->vba.DynamicMetadataTransmittedBytes,
+				mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired,
+				mode_lib->vba.Interlace,
+				mode_lib->vba.RequiredDPPCLK,
+				mode_lib->vba.RequiredDISPCLK,
+				mode_lib->vba.UrgLatency,
+				mode_lib->vba.NoOfDPP,
+				mode_lib->vba.ProjectedDCFCLKDeepSleep,
+				mode_lib->vba.MaximumVStartup,
+				mode_lib->vba.TotalNumberOfActiveDPP,
+				mode_lib->vba.TotalNumberOfDCCActiveDPP,
+				mode_lib->vba.dpte_group_bytes,
+				mode_lib->vba.PrefetchLinesY,
+				mode_lib->vba.PrefetchLinesC,
+				mode_lib->vba.swath_width_luma_ub_all_states,
+				mode_lib->vba.swath_width_chroma_ub_all_states,
+				mode_lib->vba.BytePerPixelY,
+				mode_lib->vba.BytePerPixelC,
+				mode_lib->vba.HTotal,
+				mode_lib->vba.PixelClock,
+				mode_lib->vba.PDEAndMetaPTEBytesPerFrame,
+				mode_lib->vba.DPTEBytesPerRow,
+				mode_lib->vba.MetaRowBytes,
+				mode_lib->vba.DynamicMetadataEnable,
+				mode_lib->vba.ReadBandwidthLuma,
+				mode_lib->vba.ReadBandwidthChroma,
+				mode_lib->vba.DCFCLKPerState,
+
+				/* Output */
+				mode_lib->vba.DCFCLKState);
+	} // UseMinimumRequiredDCFCLK == true
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,
+					mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],
+					mode_lib->vba.FabricClockPerState[i], mode_lib->vba.DRAMSpeedPerState[i]);
+		}
+	}
+
+	//Re-ordering Buffer Support Check
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024
+					/ mode_lib->vba.ReturnBWPerState[i][j]
+					> (mode_lib->vba.RoundTripPingLatencyCycles + 32)
+							/ mode_lib->vba.DCFCLKState[i][j]
+							+ ReorderingBytes / mode_lib->vba.ReturnBWPerState[i][j]) {
+				mode_lib->vba.ROBSupport[i][j] = true;
+			} else {
+				mode_lib->vba.ROBSupport[i][j] = false;
+			}
+		}
+	}
+
+	//Vertical Active BW support check
+	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth = 0;
+
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+		v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k]
+				+ mode_lib->vba.ReadBandwidthChroma[k];
+	}
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =
+				dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]
+					* mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
+					mode_lib->vba.FabricClockPerState[i]
+					* mode_lib->vba.FabricDatapathToDCNDataReturn
+					* mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation / 100,
+					mode_lib->vba.DRAMSpeedPerState[i]
+					* mode_lib->vba.NumberOfChannels
+					* mode_lib->vba.DRAMChannelWidth
+					* (i < 2 ? mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE : mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation) / 100);
+
+			if (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth
+					<= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
+				mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = true;
+			} else {
+				mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] = false;
+			}
+		}
+	}
+
+	/* Prefetch Check */
+
+	for (i = 0; i < (int) v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double VMDataOnlyReturnBWPerState;
+			double HostVMInefficiencyFactor;
+			unsigned int NextPrefetchModeState;
+
+			mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
+				mode_lib->vba.swath_width_luma_ub_this_state[k] =
+						mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
+				mode_lib->vba.swath_width_chroma_ub_this_state[k] =
+						mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
+				mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
+				mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
+				mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
+				mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
+				mode_lib->vba.UnboundedRequestEnabledThisState =
+						mode_lib->vba.UnboundedRequestEnabledAllStates[i][j];
+				mode_lib->vba.CompressedBufferSizeInkByteThisState =
+						mode_lib->vba.CompressedBufferSizeInkByteAllStates[i][j];
+				mode_lib->vba.DETBufferSizeInKByteThisState[k] =
+						mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeYThisState[k] =
+						mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
+				mode_lib->vba.DETBufferSizeCThisState[k] =
+						mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
+			}
+
+			mode_lib->vba.VActiveBandwithSupport[i][j] = dml32_CalculateVActiveBandwithSupport(
+					mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.ReturnBWPerState[i][j],
+					mode_lib->vba.NoUrgentLatencyHiding,
+					mode_lib->vba.ReadBandwidthLuma,
+					mode_lib->vba.ReadBandwidthChroma,
+					mode_lib->vba.cursor_bw,
+					mode_lib->vba.meta_row_bandwidth_this_state,
+					mode_lib->vba.dpte_row_bandwidth_this_state,
+					mode_lib->vba.NoOfDPPThisState,
+					mode_lib->vba.UrgentBurstFactorLuma,
+					mode_lib->vba.UrgentBurstFactorChroma,
+					mode_lib->vba.UrgentBurstFactorCursor);
+
+			VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i,
+					mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i],
+					mode_lib->vba.DRAMSpeedPerState[i]);
+			HostVMInefficiencyFactor = 1;
+
+			if (mode_lib->vba.GPUVMEnable && mode_lib->vba.HostVMEnable)
+				HostVMInefficiencyFactor = mode_lib->vba.ReturnBWPerState[i][j]
+						/ VMDataOnlyReturnBWPerState;
+
+			mode_lib->vba.ExtraLatency = dml32_CalculateExtraLatency(
+					mode_lib->vba.RoundTripPingLatencyCycles, ReorderingBytes,
+					mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.TotalNumberOfActiveDPP[i][j],
+					mode_lib->vba.PixelChunkSizeInKByte,
+					mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j], mode_lib->vba.MetaChunkSize,
+					mode_lib->vba.ReturnBWPerState[i][j], mode_lib->vba.GPUVMEnable,
+					mode_lib->vba.HostVMEnable, mode_lib->vba.NumberOfActiveSurfaces,
+					mode_lib->vba.NoOfDPPThisState, mode_lib->vba.dpte_group_bytes,
+					HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize,
+					mode_lib->vba.HostVMMaxNonCachedPageTableLevels);
+
+			NextPrefetchModeState = mode_lib->vba.MinPrefetchMode;
+
+			mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j];
+
+			do {
+				mode_lib->vba.PrefetchModePerState[i][j] = NextPrefetchModeState;
+				mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup;
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					DmlPipe myPipe;
+
+					mode_lib->vba.TWait = dml32_CalculateTWait(
+							mode_lib->vba.PrefetchModePerState[i][j],
+							mode_lib->vba.UsesMALLForPStateChange[k],
+							mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+							mode_lib->vba.DRRDisplay[k],
+							mode_lib->vba.DRAMClockChangeLatency,
+							mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.SREnterPlusExitTime);
+
+					myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
+					myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j];
+					myPipe.PixelClock = mode_lib->vba.PixelClock[k];
+					myPipe.DCFClkDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];
+					myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
+					myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
+					myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
+					myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
+					myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
+					myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
+					myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
+					myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
+					myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
+					myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
+					myPipe.HTotal = mode_lib->vba.HTotal[k];
+					myPipe.HActive = mode_lib->vba.HActive[k];
+					myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
+					myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k];
+					myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
+					myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
+					myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
+					myPipe.ProgressiveToInterlaceUnitInOPP =
+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
+
+					mode_lib->vba.NoTimeForPrefetch[i][j][k] =
+						dml32_CalculatePrefetchSchedule(
+							HostVMInefficiencyFactor,
+							&myPipe,
+							mode_lib->vba.DSCDelayPerState[i][k],
+							mode_lib->vba.DPPCLKDelaySubtotal +
+								mode_lib->vba.DPPCLKDelayCNVCFormater,
+							mode_lib->vba.DPPCLKDelaySCL,
+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
+							mode_lib->vba.DPPCLKDelayCNVCCursor,
+							mode_lib->vba.DISPCLKDelaySubtotal,
+							mode_lib->vba.SwathWidthYThisState[k] /
+								mode_lib->vba.HRatio[k],
+							mode_lib->vba.OutputFormat[k],
+							mode_lib->vba.MaxInterDCNTileRepeaters,
+							dml_min(mode_lib->vba.MaxVStartup,
+									mode_lib->vba.MaximumVStartup[i][j][k]),
+							mode_lib->vba.MaximumVStartup[i][j][k],
+							mode_lib->vba.GPUVMMaxPageTableLevels,
+							mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable,
+							mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+							mode_lib->vba.HostVMMinPageSize,
+							mode_lib->vba.DynamicMetadataEnable[k],
+							mode_lib->vba.DynamicMetadataVMEnabled,
+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
+							mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.ExtraLatency,
+							mode_lib->vba.TimeCalc,
+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
+							mode_lib->vba.MetaRowBytes[i][j][k],
+							mode_lib->vba.DPTEBytesPerRow[i][j][k],
+							mode_lib->vba.PrefetchLinesY[i][j][k],
+							mode_lib->vba.SwathWidthYThisState[k],
+							mode_lib->vba.PrefillY[k],
+							mode_lib->vba.MaxNumSwY[k],
+							mode_lib->vba.PrefetchLinesC[i][j][k],
+							mode_lib->vba.SwathWidthCThisState[k],
+							mode_lib->vba.PrefillC[k],
+							mode_lib->vba.MaxNumSwC[k],
+							mode_lib->vba.swath_width_luma_ub_this_state[k],
+							mode_lib->vba.swath_width_chroma_ub_this_state[k],
+							mode_lib->vba.SwathHeightYThisState[k],
+							mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait,
+
+							/* Output */
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
+							&mode_lib->vba.LineTimesForPrefetch[k],
+							&mode_lib->vba.PrefetchBW[k],
+							&mode_lib->vba.LinesForMetaPTE[k],
+							&mode_lib->vba.LinesForMetaAndDPTERow[k],
+							&mode_lib->vba.VRatioPreY[i][j][k],
+							&mode_lib->vba.VRatioPreC[i][j][k],
+							&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0][k],
+							&mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0][k],
+							&mode_lib->vba.NoTimeForDynamicMetadata[i][j][k],
+							&mode_lib->vba.Tno_bw[k],
+							&mode_lib->vba.prefetch_vmrow_bw[k],
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0],         // double *Tdmdl_vm
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1],         // double *Tdmdl
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2],         // double *TSetup
+							&dummy_integer[0],         							    // unsigned int   *VUpdateOffsetPix
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3],         // unsigned int   *VUpdateWidthPix
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]);        // unsigned int   *VReadyOffsetPix
+				}
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					dml32_CalculateUrgentBurstFactor(
+							mode_lib->vba.UsesMALLForPStateChange[k],
+							mode_lib->vba.swath_width_luma_ub_this_state[k],
+							mode_lib->vba.swath_width_chroma_ub_this_state[k],
+							mode_lib->vba.SwathHeightYThisState[k],
+							mode_lib->vba.SwathHeightCThisState[k],
+							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
+							mode_lib->vba.UrgLatency[i], mode_lib->vba.CursorBufferSize,
+							mode_lib->vba.CursorWidth[k][0], mode_lib->vba.CursorBPP[k][0],
+							mode_lib->vba.VRatioPreY[i][j][k],
+							mode_lib->vba.VRatioPreC[i][j][k],
+							mode_lib->vba.BytePerPixelInDETY[k],
+							mode_lib->vba.BytePerPixelInDETC[k],
+							mode_lib->vba.DETBufferSizeYThisState[k],
+							mode_lib->vba.DETBufferSizeCThisState[k],
+							/* Output */
+							&mode_lib->vba.UrgentBurstFactorCursorPre[k],
+							&mode_lib->vba.UrgentBurstFactorLumaPre[k],
+							&mode_lib->vba.UrgentBurstFactorChroma[k],
+							&mode_lib->vba.NotUrgentLatencyHidingPre[k]);
+				}
+
+				{
+					dml32_CalculatePrefetchBandwithSupport(
+							mode_lib->vba.NumberOfActiveSurfaces,
+							mode_lib->vba.ReturnBWPerState[i][j],
+							mode_lib->vba.NotUrgentLatencyHidingPre,
+							mode_lib->vba.ReadBandwidthLuma,
+							mode_lib->vba.ReadBandwidthChroma,
+							mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+							mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+							mode_lib->vba.cursor_bw,
+							mode_lib->vba.meta_row_bandwidth_this_state,
+							mode_lib->vba.dpte_row_bandwidth_this_state,
+							mode_lib->vba.cursor_bw_pre,
+							mode_lib->vba.prefetch_vmrow_bw,
+							mode_lib->vba.NoOfDPPThisState,
+							mode_lib->vba.UrgentBurstFactorLuma,
+							mode_lib->vba.UrgentBurstFactorChroma,
+							mode_lib->vba.UrgentBurstFactorCursor,
+							mode_lib->vba.UrgentBurstFactorLumaPre,
+							mode_lib->vba.UrgentBurstFactorChromaPre,
+							mode_lib->vba.UrgentBurstFactorCursorPre,
+
+							/* output */
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0],   // Single  *PrefetchBandwidth
+							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1],   // Single  *FractionOfUrgentBandwidth
+							&mode_lib->vba.PrefetchSupported[i][j]);
+				}
+
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					if (mode_lib->vba.LineTimesForPrefetch[k]
+							< 2.0 || mode_lib->vba.LinesForMetaPTE[k] >= 32.0
+							|| mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0
+							|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
+						mode_lib->vba.PrefetchSupported[i][j] = false;
+					}
+				}
+
+				mode_lib->vba.DynamicMetadataSupported[i][j] = true;
+				for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+					if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true)
+						mode_lib->vba.DynamicMetadataSupported[i][j] = false;
+				}
+
+				mode_lib->vba.VRatioInPrefetchSupported[i][j] = true;
+				for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+					if (mode_lib->vba.VRatioPreY[i][j][k] > __DML_MAX_VRATIO_PRE__
+							|| mode_lib->vba.VRatioPreC[i][j][k] > __DML_MAX_VRATIO_PRE__
+							|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
+						mode_lib->vba.VRatioInPrefetchSupported[i][j] = false;
+					}
+				}
+				mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
+				for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+					if (mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16
+							|| mode_lib->vba.LinesForMetaPTE[k] >= 32) {
+						mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;
+					}
+				}
+
+				if (mode_lib->vba.PrefetchSupported[i][j] == true
+						&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {
+					mode_lib->vba.BandwidthAvailableForImmediateFlip =
+							dml32_CalculateBandwidthAvailableForImmediateFlip(
+							mode_lib->vba.NumberOfActiveSurfaces,
+							mode_lib->vba.ReturnBWPerState[i][j],
+							mode_lib->vba.ReadBandwidthLuma,
+							mode_lib->vba.ReadBandwidthChroma,
+							mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+							mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+							mode_lib->vba.cursor_bw,
+							mode_lib->vba.cursor_bw_pre,
+							mode_lib->vba.NoOfDPPThisState,
+							mode_lib->vba.UrgentBurstFactorLuma,
+							mode_lib->vba.UrgentBurstFactorChroma,
+							mode_lib->vba.UrgentBurstFactorCursor,
+							mode_lib->vba.UrgentBurstFactorLumaPre,
+							mode_lib->vba.UrgentBurstFactorChromaPre,
+							mode_lib->vba.UrgentBurstFactorCursorPre);
+
+					mode_lib->vba.TotImmediateFlipBytes = 0.0;
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						if (!(mode_lib->vba.ImmediateFlipRequirement[k] ==
+								dm_immediate_flip_not_required)) {
+							mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes
+								+ mode_lib->vba.NoOfDPP[i][j][k]
+								* mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k]
+								+ mode_lib->vba.MetaRowBytes[i][j][k];
+							if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) {
+								mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes + 2
+								* mode_lib->vba.DPTEBytesPerRow[i][j][k];
+							} else {
+								mode_lib->vba.TotImmediateFlipBytes =
+									mode_lib->vba.TotImmediateFlipBytes
+								+ mode_lib->vba.DPTEBytesPerRow[i][j][k];
+							}
+						}
+					}
+
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						dml32_CalculateFlipSchedule(HostVMInefficiencyFactor,
+							mode_lib->vba.ExtraLatency,
+							mode_lib->vba.UrgLatency[i],
+							mode_lib->vba.GPUVMMaxPageTableLevels,
+							mode_lib->vba.HostVMEnable,
+							mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
+							mode_lib->vba.GPUVMEnable,
+							mode_lib->vba.HostVMMinPageSize,
+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
+							mode_lib->vba.MetaRowBytes[i][j][k],
+							mode_lib->vba.DPTEBytesPerRow[i][j][k],
+							mode_lib->vba.BandwidthAvailableForImmediateFlip,
+							mode_lib->vba.TotImmediateFlipBytes,
+							mode_lib->vba.SourcePixelFormat[k],
+							(mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]),
+							mode_lib->vba.VRatio[k],
+							mode_lib->vba.VRatioChroma[k],
+							mode_lib->vba.Tno_bw[k],
+								mode_lib->vba.DCCEnable[k],
+							mode_lib->vba.dpte_row_height[k],
+							mode_lib->vba.meta_row_height[k],
+							mode_lib->vba.dpte_row_height_chroma[k],
+							mode_lib->vba.meta_row_height_chroma[k],
+							mode_lib->vba.use_one_row_for_frame_flip[i][j][k], // 24
+
+							/* Output */
+							&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
+							&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
+							&mode_lib->vba.final_flip_bw[k],
+							&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
+					}
+
+					{
+						dml32_CalculateImmediateFlipBandwithSupport(mode_lib->vba.NumberOfActiveSurfaces,
+								mode_lib->vba.ReturnBWPerState[i][j],
+								mode_lib->vba.ImmediateFlipRequirement,
+								mode_lib->vba.final_flip_bw,
+								mode_lib->vba.ReadBandwidthLuma,
+								mode_lib->vba.ReadBandwidthChroma,
+								mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0],
+								mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0],
+								mode_lib->vba.cursor_bw,
+								mode_lib->vba.meta_row_bandwidth_this_state,
+								mode_lib->vba.dpte_row_bandwidth_this_state,
+								mode_lib->vba.cursor_bw_pre,
+								mode_lib->vba.prefetch_vmrow_bw,
+								mode_lib->vba.DPPPerPlane,
+								mode_lib->vba.UrgentBurstFactorLuma,
+								mode_lib->vba.UrgentBurstFactorChroma,
+								mode_lib->vba.UrgentBurstFactorCursor,
+								mode_lib->vba.UrgentBurstFactorLumaPre,
+								mode_lib->vba.UrgentBurstFactorChromaPre,
+								mode_lib->vba.UrgentBurstFactorCursorPre,
+
+								/* output */
+								&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], //  Single  *TotalBandwidth
+								&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], //  Single  *FractionOfUrgentBandwidth
+								&mode_lib->vba.ImmediateFlipSupportedForState[i][j]); // Boolean *ImmediateFlipBandwidthSupport
+					}
+
+					for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+						if (!(mode_lib->vba.ImmediateFlipRequirement[k]
+								== dm_immediate_flip_not_required)
+								&& (mode_lib->vba.ImmediateFlipSupportedForPipe[k]
+										== false))
+							mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
+					}
+				} else { // if prefetch not support, assume iflip not supported
+					mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
+				}
+
+				if (mode_lib->vba.MaxVStartup <= __DML_VBA_MIN_VSTARTUP__
+						|| mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup[i][j];
+					NextPrefetchModeState = NextPrefetchModeState + 1;
+				} else {
+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1;
+				}
+			} while (!((mode_lib->vba.PrefetchSupported[i][j] == true
+					&& mode_lib->vba.DynamicMetadataSupported[i][j] == true
+					&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true &&
+					// consider flip support is okay if when there is no hostvm and the
+					// user does't require a iflip OR the flip bw is ok
+					// If there is hostvm, DCN needs to support iflip for invalidation
+					((mode_lib->vba.HostVMEnable == false
+							&& !mode_lib->vba.ImmediateFlipRequiredFinal)
+							|| mode_lib->vba.ImmediateFlipSupportedForState[i][j] == true))
+					|| (mode_lib->vba.NextMaxVStartup == mode_lib->vba.MaxMaxVStartup[i][j]
+							&& NextPrefetchModeState > mode_lib->vba.MaxPrefetchMode)));
+
+			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
+				mode_lib->vba.use_one_row_for_frame_this_state[k] =
+						mode_lib->vba.use_one_row_for_frame[i][j][k];
+			}
+
+
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.UrgentLatency = mode_lib->vba.UrgLatency[i];
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.ExtraLatency = mode_lib->vba.ExtraLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
+			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
+
+			{
+				dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+						mode_lib->vba.USRRetrainingRequiredFinal,
+						mode_lib->vba.UsesMALLForPStateChange,
+						mode_lib->vba.PrefetchModePerState[i][j],
+						mode_lib->vba.NumberOfActiveSurfaces,
+						mode_lib->vba.MaxLineBufferLines,
+						mode_lib->vba.LineBufferSizeFinal,
+						mode_lib->vba.WritebackInterfaceBufferSize,
+						mode_lib->vba.DCFCLKState[i][j],
+						mode_lib->vba.ReturnBWPerState[i][j],
+						mode_lib->vba.SynchronizeTimingsFinal,
+						mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+						mode_lib->vba.DRRDisplay,
+						mode_lib->vba.dpte_group_bytes,
+						mode_lib->vba.meta_row_height,
+						mode_lib->vba.meta_row_height_chroma,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters,
+						mode_lib->vba.WritebackChunkSize,
+						mode_lib->vba.SOCCLKPerState[i],
+						mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j],
+						mode_lib->vba.DETBufferSizeYThisState,
+						mode_lib->vba.DETBufferSizeCThisState,
+						mode_lib->vba.SwathHeightYThisState,
+						mode_lib->vba.SwathHeightCThisState,
+						mode_lib->vba.LBBitPerPixel,
+						mode_lib->vba.SwathWidthYThisState, // 24
+						mode_lib->vba.SwathWidthCThisState,
+						mode_lib->vba.HRatio,
+						mode_lib->vba.HRatioChroma,
+						mode_lib->vba.vtaps,
+						mode_lib->vba.VTAPsChroma,
+						mode_lib->vba.VRatio,
+						mode_lib->vba.VRatioChroma,
+						mode_lib->vba.HTotal,
+						mode_lib->vba.VTotal,
+						mode_lib->vba.VActive,
+						mode_lib->vba.PixelClock,
+						mode_lib->vba.BlendingAndTiming,
+						mode_lib->vba.NoOfDPPThisState,
+						mode_lib->vba.BytePerPixelInDETY,
+						mode_lib->vba.BytePerPixelInDETC,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler,
+						v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler,
+						mode_lib->vba.WritebackEnable,
+						mode_lib->vba.WritebackPixelFormat,
+						mode_lib->vba.WritebackDestinationWidth,
+						mode_lib->vba.WritebackDestinationHeight,
+						mode_lib->vba.WritebackSourceHeight,
+						mode_lib->vba.UnboundedRequestEnabledThisState,
+						mode_lib->vba.CompressedBufferSizeInkByteThisState,
+
+						/* Output */
+						&mode_lib->vba.Watermark, // Store the values in vba
+						&mode_lib->vba.DRAMClockChangeSupport[i][j],
+						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported
+						&dummy_integer[0], // Long SubViewportLinesNeededInMALL[]
+						&mode_lib->vba.FCLKChangeSupport[i][j],
+						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported
+						&mode_lib->vba.USRRetrainingSupport[i][j],
+						mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+			}
+		}
+	} // End of Prefetch Check
+
+	/*Cursor Support Check*/
+	mode_lib->vba.CursorSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
+			if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false)
+				mode_lib->vba.CursorSupport = false;
+		}
+	}
+
+	/*Valid Pitch Check*/
+	mode_lib->vba.PitchSupport = true;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		mode_lib->vba.AlignedYPitch[k] = dml_ceil(
+				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]),
+				mode_lib->vba.MacroTileWidthY[k]);
+		if (mode_lib->vba.DCCEnable[k] == true) {
+			mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil(
+					dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]),
+					64.0 * mode_lib->vba.Read256BlockWidthY[k]);
+		} else {
+			mode_lib->vba.AlignedDCCMetaPitchY[k] = mode_lib->vba.DCCMetaPitchY[k];
+		}
+		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 && mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
+			mode_lib->vba.AlignedCPitch[k] = dml_ceil(
+					dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]),
+					mode_lib->vba.MacroTileWidthC[k]);
+			if (mode_lib->vba.DCCEnable[k] == true) {
+				mode_lib->vba.AlignedDCCMetaPitchC[k] = dml_ceil(
+						dml_max(mode_lib->vba.DCCMetaPitchC[k],
+								mode_lib->vba.SurfaceWidthC[k]),
+						64.0 * mode_lib->vba.Read256BlockWidthC[k]);
+			} else {
+				mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
+			}
+		} else {
+			mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k];
+			mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
+		}
+		if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k]
+				|| mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k]
+				|| mode_lib->vba.AlignedDCCMetaPitchY[k] > mode_lib->vba.DCCMetaPitchY[k]
+				|| mode_lib->vba.AlignedDCCMetaPitchC[k] > mode_lib->vba.DCCMetaPitchC[k]) {
+			mode_lib->vba.PitchSupport = false;
+		}
+	}
+
+	mode_lib->vba.ViewportExceedsSurface = false;
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.ViewportWidth[k] > mode_lib->vba.SurfaceWidthY[k]
+				|| mode_lib->vba.ViewportHeight[k] > mode_lib->vba.SurfaceHeightY[k]) {
+			mode_lib->vba.ViewportExceedsSurface = true;
+			if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8
+					&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe) {
+				if (mode_lib->vba.ViewportWidthChroma[k] > mode_lib->vba.SurfaceWidthC[k]
+						|| mode_lib->vba.ViewportHeightChroma[k]
+								> mode_lib->vba.SurfaceHeightC[k]) {
+					mode_lib->vba.ViewportExceedsSurface = true;
+				}
+			}
+		}
+	}
+
+	/*Mode Support, Voltage State and SOC Configuration*/
+	for (i = v->soc.num_states - 1; i >= 0; i--) {
+		for (j = 0; j < 2; j++) {
+			if (mode_lib->vba.ScaleRatioAndTapsSupport == true
+				&& mode_lib->vba.SourceFormatPixelAndScanSupport == true
+				&& mode_lib->vba.ViewportSizeSupport[i][j] == true
+				&& !mode_lib->vba.LinkRateDoesNotMatchDPVersion
+				&& !mode_lib->vba.LinkRateForMultistreamNotIndicated
+				&& !mode_lib->vba.BPPForMultistreamNotIndicated
+				&& !mode_lib->vba.MultistreamWithHDMIOreDP
+				&& !mode_lib->vba.ExceededMultistreamSlots[i]
+				&& !mode_lib->vba.MSOOrODMSplitWithNonDPLink
+				&& !mode_lib->vba.NotEnoughLanesForMSO
+				&& mode_lib->vba.LinkCapacitySupport[i] == true && !mode_lib->vba.P2IWith420
+				&& !mode_lib->vba.DSCOnlyIfNecessaryWithBPP
+				&& !mode_lib->vba.DSC422NativeNotSupported
+				&& !mode_lib->vba.MPCCombineMethodIncompatible
+				&& mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true
+				&& mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true
+				&& mode_lib->vba.NotEnoughDSCUnits[i] == false
+				&& !mode_lib->vba.NotEnoughDSCSlices[i]
+				&& !mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe
+				&& !mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
+				&& mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
+				&& mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i]
+				&& mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false
+				&& !mode_lib->vba.InvalidCombinationOfMALLUseForPState
+				&& !mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+				&& mode_lib->vba.ROBSupport[i][j] == true
+				&& mode_lib->vba.DISPCLK_DPPCLK_Support[i][j] == true
+				&& mode_lib->vba.TotalAvailablePipesSupport[i][j] == true
+				&& mode_lib->vba.NumberOfOTGSupport == true
+				&& mode_lib->vba.NumberOfHDMIFRLSupport == true
+				&& mode_lib->vba.EnoughWritebackUnits == true
+				&& mode_lib->vba.WritebackLatencySupport == true
+				&& mode_lib->vba.WritebackScaleRatioAndTapsSupport == true
+				&& mode_lib->vba.CursorSupport == true && mode_lib->vba.PitchSupport == true
+				&& mode_lib->vba.ViewportExceedsSurface == false
+				&& mode_lib->vba.PrefetchSupported[i][j] == true
+				&& mode_lib->vba.VActiveBandwithSupport[i][j] == true
+				&& mode_lib->vba.DynamicMetadataSupported[i][j] == true
+				&& mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] == true
+				&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true
+				&& mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true
+				&& mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true
+				&& mode_lib->vba.NonsupportedDSCInputBPC == false
+				&& !mode_lib->vba.ExceededMALLSize
+				&& ((mode_lib->vba.HostVMEnable == false
+				&& !mode_lib->vba.ImmediateFlipRequiredFinal)
+				|| mode_lib->vba.ImmediateFlipSupportedForState[i][j])
+				&& (!mode_lib->vba.DRAMClockChangeRequirementFinal
+				|| i == v->soc.num_states - 1
+				|| mode_lib->vba.DRAMClockChangeSupport[i][j] != dm_dram_clock_change_unsupported)
+				&& (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1
+				|| mode_lib->vba.FCLKChangeSupport[i][j] != dm_fclock_change_unsupported)
+				&& (!mode_lib->vba.USRRetrainingRequiredFinal
+				|| mode_lib->vba.USRRetrainingSupport[i][j])) {
+				mode_lib->vba.ModeSupport[i][j] = true;
+			} else {
+				mode_lib->vba.ModeSupport[i][j] = false;
+			}
+		}
+	}
+
+	MaximumMPCCombine = 0;
+
+	for (i = v->soc.num_states; i >= 0; i--) {
+		if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true ||
+				mode_lib->vba.ModeSupport[i][1] == true) {
+			mode_lib->vba.VoltageLevel = i;
+			mode_lib->vba.ModeIsSupported = mode_lib->vba.ModeSupport[i][0] == true
+					|| mode_lib->vba.ModeSupport[i][1] == true;
+
+			if ((mode_lib->vba.ModeSupport[i][0] == false && mode_lib->vba.ModeSupport[i][1] == true)
+				|| MPCCombineMethodAsPossible
+				|| (MPCCombineMethodAsNeededForPStateChangeAndVoltage
+				&& mode_lib->vba.DRAMClockChangeRequirementFinal
+				&& (((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vactive_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vactive_w_mall_sub_vp)
+				&& !(mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_vactive
+				|| mode_lib->vba.DRAMClockChangeSupport[i][0] ==
+						dm_dram_clock_change_vactive_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][0] ==
+						dm_dram_clock_change_vactive_w_mall_sub_vp))
+				|| ((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vblank_w_mall_full_frame
+				|| mode_lib->vba.DRAMClockChangeSupport[i][1] ==
+						dm_dram_clock_change_vblank_w_mall_sub_vp)
+				&& mode_lib->vba.DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported)))
+				|| (MPCCombineMethodAsNeededForPStateChangeAndVoltage &&
+				mode_lib->vba.FCLKChangeRequirementFinal
+				&& ((mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vactive
+				&& mode_lib->vba.FCLKChangeSupport[i][0] != dm_fclock_change_vactive)
+				|| (mode_lib->vba.FCLKChangeSupport[i][1] == dm_fclock_change_vblank
+				&& mode_lib->vba.FCLKChangeSupport[i][0] == dm_fclock_change_unsupported)))) {
+				MaximumMPCCombine = 1;
+			} else {
+				MaximumMPCCombine = 0;
+			}
+		}
+	}
+
+	mode_lib->vba.ImmediateFlipSupport =
+			mode_lib->vba.ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.UnboundedRequestEnabled =
+			mode_lib->vba.UnboundedRequestEnabledAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.CompressedBufferSizeInkByte =
+			mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; // Not used, informational
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		mode_lib->vba.MPCCombineEnable[k] =
+				mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.SwathHeightY[k] =
+				mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.SwathHeightC[k] =
+				mode_lib->vba.SwathHeightCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeInKByte[k] =
+			mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeY[k] =
+				mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.DETBufferSizeC[k] =
+				mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
+		mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k];
+	}
+
+	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.DISPCLK = mode_lib->vba.RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+	mode_lib->vba.maxMpcComb = MaximumMPCCombine;
+
+	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
+			mode_lib->vba.ODMCombineEnabled[k] =
+					mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
+		} else {
+			mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
+		}
+
+		mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
+		mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
+	}
+
+	mode_lib->vba.UrgentWatermark = mode_lib->vba.Watermark.UrgentWatermark;
+	mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.Watermark.StutterEnterPlusExitWatermark;
+	mode_lib->vba.StutterExitWatermark = mode_lib->vba.Watermark.StutterExitWatermark;
+	mode_lib->vba.WritebackDRAMClockChangeWatermark = mode_lib->vba.Watermark.WritebackDRAMClockChangeWatermark;
+	mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.Watermark.DRAMClockChangeWatermark;
+	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgLatency[mode_lib->vba.VoltageLevel];
+	mode_lib->vba.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
+
+	/* VBA has Error type to Error Msg output here, but not necessary for DML-C */
+} // ModeSupportAndSystemConfigurationFull
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
new file mode 100644
index 000000000000..c62e0991358b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML32_DISPLAY_MODE_VBA_H__
+#define __DML32_DISPLAY_MODE_VBA_H__
+
+#include "../display_mode_enums.h"
+
+// To enable a lot of debug msg
+//#define __DML_VBA_DEBUG__
+// For DML-C changes that hasn't been propagated to VBA yet
+//#define __DML_VBA_ALLOW_DELTA__
+
+// Move these to ip parameters/constant
+// At which vstartup the DML start to try if the mode can be supported
+#define __DML_VBA_MIN_VSTARTUP__    9
+
+// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
+#define __DML_ARB_TO_RET_DELAY__    7 + 95
+
+// fudge factor for min dcfclk calclation
+#define __DML_MIN_DCFCLK_FACTOR__   1.15
+
+// Prefetch schedule max vratio
+#define __DML_MAX_VRATIO_PRE__ 4.0
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+
+struct display_mode_lib;
+
+void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+void dml32_recalculate(struct display_mode_lib *mode_lib);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
new file mode 100644
index 000000000000..07f3a85f8edf
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -0,0 +1,6253 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "display_mode_vba_util_32.h"
+#include "../dml_inline_defs.h"
+#include "display_mode_vba_32.h"
+#include "../display_mode_lib.h"
+
+unsigned int dml32_dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output)
+{
+	// valid bpc         = source bits per component in the set of {8, 10, 12}
+	// valid bpp         = increments of 1/16 of a bit
+	//                    min = 6/7/8 in N420/N422/444, respectively
+	//                    max = such that compression is 1:1
+	//valid sliceWidth  = number of pixels per slice line,
+	//	must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
+
+	// fixed value
+	unsigned int rcModelSize = 8192;
+
+	// N422/N420 operate at 2 pixels per clock
+	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, L,
+	Delay, pixels;
+
+	if (pixelFormat == dm_420)
+		pixelsPerClock = 2;
+	else if (pixelFormat == dm_n422)
+		pixelsPerClock = 2;
+	// #all other modes operate at 1 pixel per clock
+	else
+		pixelsPerClock = 1;
+
+	//initial transmit delay as per PPS
+	initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock);
+
+	//compute ssm delay
+	if (bpc == 8)
+		D = 81;
+	else if (bpc == 10)
+		D = 89;
+	else
+		D = 113;
+
+	//divide by pixel per cycle to compute slice width as seen by DSC
+	w = sliceWidth / pixelsPerClock;
+
+	//422 mode has an additional cycle of delay
+	if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
+		s = 0;
+	else
+		s = 1;
+
+	//main calculation for the dscce
+	ix = initalXmitDelay + 45;
+	wx = (w + 2) / 3;
+	p = 3 * wx - w;
+	l0 = ix / w;
+	a = ix + p * l0;
+	ax = (a + 2) / 3 + D + 6 + 1;
+	L = (ax + wx - 1) / wx;
+	if ((ix % w) == 0 && p != 0)
+		lstall = 1;
+	else
+		lstall = 0;
+	Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22;
+
+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
+	pixels = Delay * 3 * pixelsPerClock;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: bpc: %d\n", __func__, bpc);
+	dml_print("DML::%s: BPP: %f\n", __func__, BPP);
+	dml_print("DML::%s: sliceWidth: %d\n", __func__, sliceWidth);
+	dml_print("DML::%s: numSlices: %d\n", __func__, numSlices);
+	dml_print("DML::%s: pixelFormat: %d\n", __func__, pixelFormat);
+	dml_print("DML::%s: Output: %d\n", __func__, Output);
+	dml_print("DML::%s: pixels: %d\n", __func__, pixels);
+#endif
+
+	return pixels;
+}
+
+unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output)
+{
+	unsigned int Delay = 0;
+
+	if (pixelFormat == dm_420) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 2;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 13;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 3;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else if (pixelFormat == dm_n422 || (pixelFormat != dm_444)) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 1;
+		//   dscc - input deserializer
+		Delay = Delay + 5;
+		//  dscc - input cdc fifo
+		Delay = Delay + 25;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 10;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   sft
+		Delay = Delay + 1;
+	}
+
+	return Delay;
+}
+
+
+bool IsVertical(enum dm_rotation_angle Scan)
+{
+	bool is_vert = false;
+
+	if (Scan == dm_rotation_90 || Scan == dm_rotation_90m || Scan == dm_rotation_270 || Scan == dm_rotation_270m)
+		is_vert = true;
+	else
+		is_vert = false;
+	return is_vert;
+}
+
+void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingSingleDPP)
+{
+	double DPPCLKUsingSingleDPPLuma;
+	double DPPCLKUsingSingleDPPChroma;
+
+	if (HRatio > 1) {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio /
+				dml_ceil((double) HTaps / 6.0, 1.0));
+	} else {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+	}
+
+	DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
+			*PSCL_THROUGHPUT, 1);
+
+	if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingSingleDPPLuma < 2 * PixelClock)
+		DPPCLKUsingSingleDPPLuma = 2 * PixelClock;
+
+	if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 &&
+			SourcePixelFormat != dm_rgbe_alpha)) {
+		*PSCL_THROUGHPUT_CHROMA = 0;
+		*DPPCLKUsingSingleDPP = DPPCLKUsingSingleDPPLuma;
+	} else {
+		if (HRatioChroma > 1) {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput *
+					HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0));
+		} else {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+		}
+		DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
+				HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1);
+		if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingSingleDPPChroma < 2 * PixelClock)
+			DPPCLKUsingSingleDPPChroma = 2 * PixelClock;
+		*DPPCLKUsingSingleDPP = dml_max(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma);
+	}
+}
+
+void dml32_CalculateBytePerPixelAndBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+
+		/* Output */
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double  *BytePerPixelDETY,
+		double  *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC,
+		unsigned int *MacroTileHeightY,
+		unsigned int *MacroTileHeightC,
+		unsigned int *MacroTileWidthY,
+		unsigned int *MacroTileWidthC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: SourcePixelFormat = %d\n", __func__, SourcePixelFormat);
+	dml_print("DML::%s: BytePerPixelDETY = %f\n", __func__, *BytePerPixelDETY);
+	dml_print("DML::%s: BytePerPixelDETC = %f\n", __func__, *BytePerPixelDETC);
+	dml_print("DML::%s: BytePerPixelY    = %d\n", __func__, *BytePerPixelY);
+	dml_print("DML::%s: BytePerPixelC    = %d\n", __func__, *BytePerPixelC);
+#endif
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32
+			|| SourcePixelFormat == dm_444_16
+			|| SourcePixelFormat == dm_444_8
+			|| SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8
+			|| SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear)
+			*BlockHeight256BytesY = 1;
+		else if (SourcePixelFormat == dm_444_64)
+			*BlockHeight256BytesY = 4;
+		else if (SourcePixelFormat == dm_444_8)
+			*BlockHeight256BytesY = 16;
+		else
+			*BlockHeight256BytesY = 8;
+
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: BlockWidth256BytesY  = %d\n", __func__, *BlockWidth256BytesY);
+	dml_print("DML::%s: BlockHeight256BytesY = %d\n", __func__, *BlockHeight256BytesY);
+	dml_print("DML::%s: BlockWidth256BytesC  = %d\n", __func__, *BlockWidth256BytesC);
+	dml_print("DML::%s: BlockHeight256BytesC = %d\n", __func__, *BlockHeight256BytesC);
+#endif
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*MacroTileHeightY = *BlockHeight256BytesY;
+		*MacroTileWidthY = 256 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 256 / *BytePerPixelC / *MacroTileHeightC;
+	} else if (SurfaceTiling == dm_sw_64kb_d || SurfaceTiling == dm_sw_64kb_d_t ||
+			SurfaceTiling == dm_sw_64kb_d_x || SurfaceTiling == dm_sw_64kb_r_x) {
+		*MacroTileHeightY = 16 * *BlockHeight256BytesY;
+		*MacroTileWidthY = 65536 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = 16 * *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 65536 / *BytePerPixelC / *MacroTileHeightC;
+	} else {
+		*MacroTileHeightY = 32 * *BlockHeight256BytesY;
+		*MacroTileWidthY = 65536 * 4 / *BytePerPixelY / *MacroTileHeightY;
+		*MacroTileHeightC = 32 * *BlockHeight256BytesC;
+		if (*MacroTileHeightC == 0)
+			*MacroTileWidthC = 0;
+		else
+			*MacroTileWidthC = 65536 * 4 / *BytePerPixelC / *MacroTileHeightC;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MacroTileWidthY  = %d\n", __func__, *MacroTileWidthY);
+	dml_print("DML::%s: MacroTileHeightY = %d\n", __func__, *MacroTileHeightY);
+	dml_print("DML::%s: MacroTileWidthC  = %d\n", __func__, *MacroTileWidthC);
+	dml_print("DML::%s: MacroTileHeightC = %d\n", __func__, *MacroTileHeightC);
+#endif
+} // CalculateBytePerPixelAndBlockSizes
+
+void dml32_CalculatedoublePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingdoubleDPP)
+{
+	double DPPCLKUsingdoubleDPPLuma;
+	double DPPCLKUsingdoubleDPPChroma;
+
+	if (HRatio > 1) {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio /
+				dml_ceil((double) HTaps / 6.0, 1.0));
+	} else {
+		*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+	}
+
+	DPPCLKUsingdoubleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
+			*PSCL_THROUGHPUT, 1);
+
+	if ((HTaps > 6 || VTaps > 6) && DPPCLKUsingdoubleDPPLuma < 2 * PixelClock)
+		DPPCLKUsingdoubleDPPLuma = 2 * PixelClock;
+
+	if ((SourcePixelFormat != dm_420_8 && SourcePixelFormat != dm_420_10 && SourcePixelFormat != dm_420_12 &&
+			SourcePixelFormat != dm_rgbe_alpha)) {
+		*PSCL_THROUGHPUT_CHROMA = 0;
+		*DPPCLKUsingdoubleDPP = DPPCLKUsingdoubleDPPLuma;
+	} else {
+		if (HRatioChroma > 1) {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput *
+					HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0));
+		} else {
+			*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
+		}
+		DPPCLKUsingdoubleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
+				HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1);
+		if ((HTapsChroma > 6 || VTapsChroma > 6) && DPPCLKUsingdoubleDPPChroma < 2 * PixelClock)
+			DPPCLKUsingdoubleDPPChroma = 2 * PixelClock;
+		*DPPCLKUsingdoubleDPP = dml_max(DPPCLKUsingdoubleDPPLuma, DPPCLKUsingdoubleDPPChroma);
+	}
+}
+
+void dml32_CalculateSwathAndDETConfiguration(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		double ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int nomDETInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class Output[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum dm_rotation_angle SourceRotation[],
+		bool ViewportStationary[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BlendingAndTiming[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		unsigned int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool *UnboundedRequestEnabled,
+		unsigned int *CompressedBufferSizeInkByte,
+		bool ViewportSizeSupportPerSurface[],
+		bool *ViewportSizeSupport)
+{
+	unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+	unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX];
+	unsigned int RoundedUpSwathSizeBytesY;
+	unsigned int RoundedUpSwathSizeBytesC;
+	double SwathWidthdoubleDPP[DC__NUM_DPP__MAX];
+	double SwathWidthdoubleDPPChroma[DC__NUM_DPP__MAX];
+	unsigned int k;
+	unsigned int TotalActiveDPP = 0;
+	bool NoChromaSurfaces = true;
+	unsigned int DETBufferSizeInKByteForSwathCalculation;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+#endif
+	dml32_CalculateSwathWidth(ForceSingleDPP,
+			NumberOfActiveSurfaces,
+			SourcePixelFormat,
+			SourceRotation,
+			ViewportStationary,
+			ViewportWidth,
+			ViewportHeight,
+			ViewportXStart,
+			ViewportYStart,
+			ViewportXStartC,
+			ViewportYStartC,
+			SurfaceWidthY,
+			SurfaceWidthC,
+			SurfaceHeightY,
+			SurfaceHeightC,
+			ODMMode,
+			BytePerPixY,
+			BytePerPixC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			BlendingAndTiming,
+			HActive,
+			HRatio,
+			DPPPerSurface,
+
+			/* Output */
+			SwathWidthdoubleDPP,
+			SwathWidthdoubleDPPChroma,
+			SwathWidth,
+			SwathWidthChroma,
+			MaximumSwathHeightY,
+			MaximumSwathHeightC,
+			swath_width_luma_ub,
+			swath_width_chroma_ub);
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
+		RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+		dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%0d BytePerPixDETY = %f\n", __func__, k, BytePerPixDETY[k]);
+		dml_print("DML::%s: k=%0d MaximumSwathHeightY = %d\n", __func__, k, MaximumSwathHeightY[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
+				RoundedUpMaxSwathSizeBytesY[k]);
+		dml_print("DML::%s: k=%0d swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%0d BytePerPixDETC = %f\n", __func__, k, BytePerPixDETC[k]);
+		dml_print("DML::%s: k=%0d MaximumSwathHeightC = %d\n", __func__, k, MaximumSwathHeightC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
+				RoundedUpMaxSwathSizeBytesC[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256);
+			RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256);
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		TotalActiveDPP = TotalActiveDPP + (ForceSingleDPP ? 1 : DPPPerSurface[k]);
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+				SourcePixelFormat[k] == dm_420_12 || SourcePixelFormat[k] == dm_rgbe_alpha) {
+			NoChromaSurfaces = false;
+		}
+	}
+
+	*UnboundedRequestEnabled = dml32_UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP,
+			NoChromaSurfaces, Output[0]);
+
+	dml32_CalculateDETBufferSize(DETSizeOverride,
+			UseMALLForPStateChange,
+			ForceSingleDPP,
+			NumberOfActiveSurfaces,
+			*UnboundedRequestEnabled,
+			nomDETInKByte,
+			MaxTotalDETInKByte,
+			ConfigReturnBufferSizeInKByte,
+			MinCompressedBufferSizeInKByte,
+			CompressedBufferSegmentSizeInkByteFinal,
+			SourcePixelFormat,
+			ReadBandwidthLuma,
+			ReadBandwidthChroma,
+			RoundedUpMaxSwathSizeBytesY,
+			RoundedUpMaxSwathSizeBytesC,
+			DPPPerSurface,
+
+			/* Output */
+			DETBufferSizeInKByte,    // per hubp pipe
+			CompressedBufferSizeInkByte);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+#endif
+
+	*ViewportSizeSupport = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		DETBufferSizeInKByteForSwathCalculation = (UseMALLForPStateChange[k] ==
+				dm_use_mall_pstate_change_phantom_pipe ? 1024 : DETBufferSizeInKByte[k]);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DETBufferSizeInKByteForSwathCalculation = %d\n", __func__, k,
+				DETBufferSizeInKByteForSwathCalculation);
+#endif
+
+		if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
+		} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
+				RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
+		} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
+				RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <=
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
+		} else {
+			SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
+			SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
+		}
+
+		if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 >
+				DETBufferSizeInKByteForSwathCalculation * 1024 / 2)
+				|| SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 &&
+						SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
+			*ViewportSizeSupport = false;
+			ViewportSizeSupportPerSurface[k] = false;
+		} else {
+			ViewportSizeSupportPerSurface[k] = true;
+		}
+
+		if (SwathHeightC[k] == 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d All DET for plane0\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024;
+			DETBufferSizeC[k] = 0;
+		} else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Half DET for plane0, half for plane1\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024 / 2;
+			DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 / 2;
+		} else {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
+#endif
+			DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024);
+			DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
+		dml_print("DML::%s: k=%0d SwathHeightC = %d\n", __func__, k, SwathHeightC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__,
+				k, RoundedUpMaxSwathSizeBytesY[k]);
+		dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__,
+				k, RoundedUpMaxSwathSizeBytesC[k]);
+		dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesY = %d\n", __func__, k, RoundedUpSwathSizeBytesY);
+		dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesC = %d\n", __func__, k, RoundedUpSwathSizeBytesC);
+		dml_print("DML::%s: k=%0d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+		dml_print("DML::%s: k=%0d DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
+		dml_print("DML::%s: k=%0d DETBufferSizeC = %d\n", __func__, k, DETBufferSizeC[k]);
+		dml_print("DML::%s: k=%0d ViewportSizeSupportPerSurface = %d\n", __func__, k,
+				ViewportSizeSupportPerSurface[k]);
+#endif
+
+	}
+} // CalculateSwathAndDETConfiguration
+
+void dml32_CalculateSwathWidth(
+		bool				ForceSingleDPP,
+		unsigned int			NumberOfActiveSurfaces,
+		enum source_format_class	SourcePixelFormat[],
+		enum dm_rotation_angle		SourceRotation[],
+		bool				ViewportStationary[],
+		unsigned int			ViewportWidth[],
+		unsigned int			ViewportHeight[],
+		unsigned int			ViewportXStart[],
+		unsigned int			ViewportYStart[],
+		unsigned int			ViewportXStartC[],
+		unsigned int			ViewportYStartC[],
+		unsigned int			SurfaceWidthY[],
+		unsigned int			SurfaceWidthC[],
+		unsigned int			SurfaceHeightY[],
+		unsigned int			SurfaceHeightC[],
+		enum odm_combine_mode		ODMMode[],
+		unsigned int			BytePerPixY[],
+		unsigned int			BytePerPixC[],
+		unsigned int			Read256BytesBlockHeightY[],
+		unsigned int			Read256BytesBlockHeightC[],
+		unsigned int			Read256BytesBlockWidthY[],
+		unsigned int			Read256BytesBlockWidthC[],
+		unsigned int			BlendingAndTiming[],
+		unsigned int			HActive[],
+		double				HRatio[],
+		unsigned int			DPPPerSurface[],
+
+		/* Output */
+		double				SwathWidthdoubleDPPY[],
+		double				SwathWidthdoubleDPPC[],
+		double				SwathWidthY[], // per-pipe
+		double				SwathWidthC[], // per-pipe
+		unsigned int			MaximumSwathHeightY[],
+		unsigned int			MaximumSwathHeightC[],
+		unsigned int			swath_width_luma_ub[], // per-pipe
+		unsigned int			swath_width_chroma_ub[]) // per-pipe
+{
+	unsigned int k, j;
+	enum odm_combine_mode MainSurfaceODMMode;
+
+    unsigned int surface_width_ub_l;
+    unsigned int surface_height_ub_l;
+    unsigned int surface_width_ub_c;
+    unsigned int surface_height_ub_c;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!IsVertical(SourceRotation[k]))
+			SwathWidthdoubleDPPY[k] = ViewportWidth[k];
+		else
+			SwathWidthdoubleDPPY[k] = ViewportHeight[k];
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
+		dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
+#endif
+
+		MainSurfaceODMMode = ODMMode[k];
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			if (BlendingAndTiming[k] == j)
+				MainSurfaceODMMode = ODMMode[j];
+		}
+
+		if (ForceSingleDPP) {
+			SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+		} else {
+			if (MainSurfaceODMMode == dm_odm_combine_mode_4to1) {
+				SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
+						dml_round(HActive[k] / 4.0 * HRatio[k]));
+			} else if (MainSurfaceODMMode == dm_odm_combine_mode_2to1) {
+				SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
+						dml_round(HActive[k] / 2.0 * HRatio[k]));
+			} else if (DPPPerSurface[k] == 2) {
+				SwathWidthY[k] = SwathWidthdoubleDPPY[k] / 2;
+			} else {
+				SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+			}
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d HActive=%d\n", __func__, k, HActive[k]);
+		dml_print("DML::%s: k=%d HRatio=%f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d MainSurfaceODMMode=%d\n", __func__, k, MainSurfaceODMMode);
+		dml_print("DML::%s: k=%d SwathWidthdoubleDPPY=%d\n", __func__, k, SwathWidthdoubleDPPY[k]);
+		dml_print("DML::%s: k=%d SwathWidthY=%d\n", __func__, k, SwathWidthY[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+				SourcePixelFormat[k] == dm_420_12) {
+			SwathWidthC[k] = SwathWidthY[k] / 2;
+			SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k] / 2;
+		} else {
+			SwathWidthC[k] = SwathWidthY[k];
+			SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k];
+		}
+
+		if (ForceSingleDPP == true) {
+			SwathWidthY[k] = SwathWidthdoubleDPPY[k];
+			SwathWidthC[k] = SwathWidthdoubleDPPC[k];
+		}
+
+		surface_width_ub_l  = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
+		surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
+		surface_width_ub_c  = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
+		surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
+		dml_print("DML::%s: k=%d surface_height_ub_l=%0d\n", __func__, k, surface_height_ub_l);
+		dml_print("DML::%s: k=%d surface_width_ub_c=%0d\n", __func__, k, surface_width_ub_c);
+		dml_print("DML::%s: k=%d surface_height_ub_c=%0d\n", __func__, k, surface_height_ub_c);
+		dml_print("DML::%s: k=%d Read256BytesBlockWidthY=%0d\n", __func__, k, Read256BytesBlockWidthY[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockHeightY=%0d\n", __func__, k, Read256BytesBlockHeightY[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockWidthC=%0d\n", __func__, k, Read256BytesBlockWidthC[k]);
+		dml_print("DML::%s: k=%d Read256BytesBlockHeightC=%0d\n", __func__, k, Read256BytesBlockHeightC[k]);
+		dml_print("DML::%s: k=%d ViewportStationary=%0d\n", __func__, k, ViewportStationary[k]);
+		dml_print("DML::%s: k=%d DPPPerSurface=%0d\n", __func__, k, DPPPerSurface[k]);
+#endif
+
+		if (!IsVertical(SourceRotation[k])) {
+			MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
+			if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+				swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
+						dml_floor(ViewportXStart[k] +
+								SwathWidthY[k] +
+								Read256BytesBlockWidthY[k] - 1,
+								Read256BytesBlockWidthY[k]) -
+								dml_floor(ViewportXStart[k],
+								Read256BytesBlockWidthY[k]));
+			} else {
+				swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
+						dml_ceil(SwathWidthY[k] - 1,
+								Read256BytesBlockWidthY[k]) +
+								Read256BytesBlockWidthY[k]);
+			}
+			if (BytePerPixC[k] > 0) {
+				if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+					swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
+							dml_floor(ViewportXStartC[k] + SwathWidthC[k] +
+									Read256BytesBlockWidthC[k] - 1,
+									Read256BytesBlockWidthC[k]) -
+									dml_floor(ViewportXStartC[k],
+									Read256BytesBlockWidthC[k]));
+				} else {
+					swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
+							dml_ceil(SwathWidthC[k] - 1,
+								Read256BytesBlockWidthC[k]) +
+								Read256BytesBlockWidthC[k]);
+				}
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		} else {
+			MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
+
+			if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+				swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] +
+						SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1,
+						Read256BytesBlockHeightY[k]) -
+						dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k]));
+			} else {
+				swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1,
+						Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
+			}
+			if (BytePerPixC[k] > 0) {
+				if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
+					swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
+							dml_floor(ViewportYStartC[k] + SwathWidthC[k] +
+									Read256BytesBlockHeightC[k] - 1,
+									Read256BytesBlockHeightC[k]) -
+									dml_floor(ViewportYStartC[k],
+											Read256BytesBlockHeightC[k]));
+				} else {
+					swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
+							dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) +
+							Read256BytesBlockHeightC[k]);
+				}
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d swath_width_luma_ub=%0d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d swath_width_chroma_ub=%0d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d MaximumSwathHeightY=%0d\n", __func__, k, MaximumSwathHeightY[k]);
+		dml_print("DML::%s: k=%d MaximumSwathHeightC=%0d\n", __func__, k, MaximumSwathHeightC[k]);
+#endif
+
+	}
+} // CalculateSwathWidth
+
+bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int TotalNumberOfActiveDPP,
+		bool NoChroma,
+		enum output_encoder_class Output)
+{
+	bool ret_val = false;
+
+	ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable &&
+			TotalNumberOfActiveDPP == 1 && NoChroma);
+	if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp)
+		ret_val = false;
+	return ret_val;
+}
+
+void dml32_CalculateDETBufferSize(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		bool UnboundedRequestEnabled,
+		unsigned int nomDETInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum source_format_class SourcePixelFormat[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int RoundedUpMaxSwathSizeBytesY[],
+		unsigned int RoundedUpMaxSwathSizeBytesC[],
+		unsigned int DPPPerSurface[],
+		/* Output */
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int *CompressedBufferSizeInkByte)
+{
+	unsigned int DETBufferSizePoolInKByte;
+	unsigned int NextDETBufferPieceInKByte;
+	bool DETPieceAssignedToThisSurfaceAlready[DC__NUM_DPP__MAX];
+	bool NextPotentialSurfaceToAssignDETPieceFound;
+	unsigned int NextSurfaceToAssignDETPiece;
+	double TotalBandwidth;
+	double BandwidthOfSurfacesNotAssignedDETPiece;
+	unsigned int max_minDET;
+	unsigned int minDET;
+	unsigned int minDET_pipe;
+	unsigned int j, k;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ForceSingleDPP = %d\n", __func__, ForceSingleDPP);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled);
+	dml_print("DML::%s: MaxTotalDETInKByte = %d\n", __func__, MaxTotalDETInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: MinCompressedBufferSizeInKByte = %d\n", __func__, MinCompressedBufferSizeInKByte);
+	dml_print("DML::%s: CompressedBufferSegmentSizeInkByteFinal = %d\n", __func__,
+			CompressedBufferSegmentSizeInkByteFinal);
+#endif
+
+	// Note: Will use default det size if that fits 2 swaths
+	if (UnboundedRequestEnabled) {
+		if (DETSizeOverride[0] > 0) {
+			DETBufferSizeInKByte[0] = DETSizeOverride[0];
+		} else {
+			DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 *
+					((double) RoundedUpMaxSwathSizeBytesY[0] +
+							(double) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, 64.0));
+		}
+		*CompressedBufferSizeInkByte = ConfigReturnBufferSizeInKByte - DETBufferSizeInKByte[0];
+	} else {
+		DETBufferSizePoolInKByte = MaxTotalDETInKByte;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			DETBufferSizeInKByte[k] = nomDETInKByte;
+			if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
+					SourcePixelFormat[k] == dm_420_12) {
+				max_minDET = nomDETInKByte - 64;
+			} else {
+				max_minDET = nomDETInKByte;
+			}
+			minDET = 128;
+			minDET_pipe = 0;
+
+			// add DET resource until can hold 2 full swaths
+			while (minDET <= max_minDET && minDET_pipe == 0) {
+				if (2.0 * ((double) RoundedUpMaxSwathSizeBytesY[k] +
+						(double) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
+					minDET_pipe = minDET;
+				minDET = minDET + 64;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d minDET        = %d\n", __func__, k, minDET);
+			dml_print("DML::%s: k=%0d max_minDET    = %d\n", __func__, k, max_minDET);
+			dml_print("DML::%s: k=%0d minDET_pipe   = %d\n", __func__, k, minDET_pipe);
+			dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
+					RoundedUpMaxSwathSizeBytesY[k]);
+			dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
+					RoundedUpMaxSwathSizeBytesC[k]);
+#endif
+
+			if (minDET_pipe == 0) {
+				minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] +
+						(double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64));
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d minDET_pipe = %d (assume each plane take half DET)\n",
+						__func__, k, minDET_pipe);
+#endif
+			}
+
+			if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
+				DETBufferSizeInKByte[k] = 0;
+			} else if (DETSizeOverride[k] > 0) {
+				DETBufferSizeInKByte[k] = DETSizeOverride[k];
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte -
+						(ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
+			} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
+				DETBufferSizeInKByte[k] = minDET_pipe;
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte -
+						(ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+			dml_print("DML::%s: k=%d DETSizeOverride = %d\n", __func__, k, DETSizeOverride[k]);
+			dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+			dml_print("DML::%s: DETBufferSizePoolInKByte = %d\n", __func__, DETBufferSizePoolInKByte);
+#endif
+		}
+
+		TotalBandwidth = 0;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)
+				TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: --- Before bandwidth adjustment ---\n", __func__);
+		for (uint k = 0; k < NumberOfActiveSurfaces; ++k)
+			dml_print("DML::%s: k=%d DETBufferSizeInKByte   = %d\n", __func__, k, DETBufferSizeInKByte[k]);
+		dml_print("DML::%s: --- DET allocation with bandwidth ---\n", __func__);
+		dml_print("DML::%s: TotalBandwidth = %f\n", __func__, TotalBandwidth);
+#endif
+		BandwidthOfSurfacesNotAssignedDETPiece = TotalBandwidth;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+			if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
+				DETPieceAssignedToThisSurfaceAlready[k] = true;
+			} else if (DETSizeOverride[k] > 0 || (((double) (ForceSingleDPP ? 1 : DPPPerSurface[k]) *
+					(double) DETBufferSizeInKByte[k] / (double) MaxTotalDETInKByte) >=
+					((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
+				DETPieceAssignedToThisSurfaceAlready[k] = true;
+				BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece -
+						ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
+			} else {
+				DETPieceAssignedToThisSurfaceAlready[k] = false;
+			}
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d DETPieceAssignedToThisSurfaceAlready = %d\n", __func__, k,
+					DETPieceAssignedToThisSurfaceAlready[k]);
+			dml_print("DML::%s: k=%d BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k,
+					BandwidthOfSurfacesNotAssignedDETPiece);
+#endif
+		}
+
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			NextPotentialSurfaceToAssignDETPieceFound = false;
+			NextSurfaceToAssignDETPiece = 0;
+
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[k] = %f\n", __func__, j, k,
+						ReadBandwidthLuma[k]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[k] = %f\n", __func__, j, k,
+						ReadBandwidthChroma[k]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[Next] = %f\n", __func__, j, k,
+						ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[Next] = %f\n", __func__, j, k,
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%d k=%d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, k,
+						NextSurfaceToAssignDETPiece);
+#endif
+				if (!DETPieceAssignedToThisSurfaceAlready[k] &&
+						(!NextPotentialSurfaceToAssignDETPieceFound ||
+						ReadBandwidthLuma[k] + ReadBandwidthChroma[k] <
+						ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece])) {
+					NextSurfaceToAssignDETPiece = k;
+					NextPotentialSurfaceToAssignDETPieceFound = true;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%d k=%d, DETPieceAssignedToThisSurfaceAlready = %d\n",
+						__func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
+				dml_print("DML::%s: j=%d k=%d, NextPotentialSurfaceToAssignDETPieceFound = %d\n",
+						__func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
+#endif
+			}
+
+			if (NextPotentialSurfaceToAssignDETPieceFound) {
+				// Note: To show the banker's rounding behavior in VBA and also the fact
+				// that the DET buffer size varies due to precision issue
+				//
+				//double tmp1 =  ((double) DETBufferSizePoolInKByte *
+				// (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+				// ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+				// BandwidthOfSurfacesNotAssignedDETPiece /
+				// ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+				//double tmp2 =  dml_round((double) DETBufferSizePoolInKByte *
+				// (ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+				// ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+				 //BandwidthOfSurfacesNotAssignedDETPiece /
+				// ((ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+				//
+				//dml_print("DML::%s: j=%d, tmp1 = %f\n", __func__, j, tmp1);
+				//dml_print("DML::%s: j=%d, tmp2 = %f\n", __func__, j, tmp2);
+
+				NextDETBufferPieceInKByte = dml_min(
+					dml_round((double) DETBufferSizePoolInKByte *
+						(ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+						ReadBandwidthChroma[NextSurfaceToAssignDETPiece]) /
+						BandwidthOfSurfacesNotAssignedDETPiece /
+						((ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0)) *
+						(ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0,
+						dml_floor((double) DETBufferSizePoolInKByte,
+						(ForceSingleDPP ? 1 :
+								DPPPerSurface[NextSurfaceToAssignDETPiece]) * 64.0));
+
+				// Above calculation can assign the entire DET buffer allocation to a single pipe.
+				// We should limit the per-pipe DET size to the nominal / max per pipe.
+				if (NextDETBufferPieceInKByte > nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
+					if (DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] <
+							nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
+						NextDETBufferPieceInKByte = nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k]) -
+								DETBufferSizeInKByte[NextSurfaceToAssignDETPiece];
+					} else {
+						// Case where DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]
+						// already has the max per-pipe value
+						NextDETBufferPieceInKByte = 0;
+					}
+				}
+
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: j=%0d, DETBufferSizePoolInKByte = %d\n", __func__, j,
+					DETBufferSizePoolInKByte);
+				dml_print("DML::%s: j=%0d, NextSurfaceToAssignDETPiece = %d\n", __func__, j,
+					NextSurfaceToAssignDETPiece);
+				dml_print("DML::%s: j=%0d, ReadBandwidthLuma[%0d] = %f\n", __func__, j,
+					NextSurfaceToAssignDETPiece, ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%0d, ReadBandwidthChroma[%0d] = %f\n", __func__, j,
+					NextSurfaceToAssignDETPiece, ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+				dml_print("DML::%s: j=%0d, BandwidthOfSurfacesNotAssignedDETPiece = %f\n",
+					__func__, j, BandwidthOfSurfacesNotAssignedDETPiece);
+				dml_print("DML::%s: j=%0d, NextDETBufferPieceInKByte = %d\n", __func__, j,
+					NextDETBufferPieceInKByte);
+				dml_print("DML::%s: j=%0d, DETBufferSizeInKByte[%0d] increases from %0d ",
+					__func__, j, NextSurfaceToAssignDETPiece,
+					DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]);
+#endif
+
+				DETBufferSizeInKByte[NextSurfaceToAssignDETPiece] =
+						DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]
+						+ NextDETBufferPieceInKByte
+						/ (ForceSingleDPP ? 1 : DPPPerSurface[NextSurfaceToAssignDETPiece]);
+#ifdef __DML_VBA_DEBUG__
+				dml_print("to %0d\n", DETBufferSizeInKByte[NextSurfaceToAssignDETPiece]);
+#endif
+
+				DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - NextDETBufferPieceInKByte;
+				DETPieceAssignedToThisSurfaceAlready[NextSurfaceToAssignDETPiece] = true;
+				BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece -
+						(ReadBandwidthLuma[NextSurfaceToAssignDETPiece] +
+								ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
+			}
+		}
+		*CompressedBufferSizeInkByte = MinCompressedBufferSizeInKByte;
+	}
+	*CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: --- After bandwidth adjustment ---\n", __func__);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+	for (uint k = 0; k < NumberOfActiveSurfaces; ++k) {
+		dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d (TotalReadBandWidth=%f)\n",
+				__func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
+	}
+#endif
+} // CalculateDETBufferSize
+
+void dml32_CalculateODMMode(
+		unsigned int MaximumPixelsPerLinePerDSCUnit,
+		unsigned int HActive,
+		enum output_encoder_class Output,
+		enum odm_combine_policy ODMUse,
+		double StateDispclk,
+		double MaxDispclk,
+		bool DSCEnable,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int MaxNumDPP,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+
+		/* Output */
+		bool *TotalAvailablePipesSupport,
+		unsigned int *NumberOfDPP,
+		enum odm_combine_mode *ODMMode,
+		double *RequiredDISPCLKPerSurface)
+{
+
+	double SurfaceRequiredDISPCLKWithoutODMCombine;
+	double SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
+	double SurfaceRequiredDISPCLKWithODMCombineFourToOne;
+
+	SurfaceRequiredDISPCLKWithoutODMCombine = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_disabled,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	SurfaceRequiredDISPCLKWithODMCombineTwoToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_2to1,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	SurfaceRequiredDISPCLKWithODMCombineFourToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_4to1,
+			PixelClock, DISPCLKDPPCLKDSCCLKDownSpreading, DISPCLKRampingMargin, DISPCLKDPPCLKVCOSpeed,
+			MaxDispclk);
+	*TotalAvailablePipesSupport = true;
+	*ODMMode = dm_odm_combine_mode_disabled; // initialize as disable
+
+	if (ODMUse == dm_odm_combine_policy_none)
+		*ODMMode = dm_odm_combine_mode_disabled;
+
+	*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithoutODMCombine;
+	*NumberOfDPP = 0;
+
+	// FIXME check ODMUse == "" condition does it mean bypass or Gabriel means something like don't care??
+	// (ODMUse == "" || ODMUse == "CombineAsNeeded")
+
+	if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) && (ODMUse == dm_odm_combine_policy_4to1 ||
+			((SurfaceRequiredDISPCLKWithODMCombineTwoToOne > StateDispclk ||
+					(DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)))))) {
+		if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) {
+			*ODMMode = dm_odm_combine_mode_4to1;
+			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;
+			*NumberOfDPP = 4;
+		} else {
+			*TotalAvailablePipesSupport = false;
+		}
+	} else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 ||
+			(((SurfaceRequiredDISPCLKWithoutODMCombine > StateDispclk &&
+					SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) ||
+					(DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)))))) {
+		if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) {
+			*ODMMode = dm_odm_combine_mode_2to1;
+			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
+			*NumberOfDPP = 2;
+		} else {
+			*TotalAvailablePipesSupport = false;
+		}
+	} else {
+		if (TotalNumberOfActiveDPP + 1 <= MaxNumDPP)
+			*NumberOfDPP = 1;
+		else
+			*TotalAvailablePipesSupport = false;
+	}
+}
+
+double dml32_CalculateRequiredDispclk(
+		enum odm_combine_mode ODMMode,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+		double MaxDispclk)
+{
+	double RequiredDispclk = 0.;
+	double PixelClockAfterODM;
+	double DISPCLKWithRampingRoundedToDFSGranularity;
+	double DISPCLKWithoutRampingRoundedToDFSGranularity;
+	double MaxDispclkRoundedDownToDFSGranularity;
+
+	if (ODMMode == dm_odm_combine_mode_4to1)
+		PixelClockAfterODM = PixelClock / 4;
+	else if (ODMMode == dm_odm_combine_mode_2to1)
+		PixelClockAfterODM = PixelClock / 2;
+	else
+		PixelClockAfterODM = PixelClock;
+
+
+	DISPCLKWithRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(
+			PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+					* (1 + DISPCLKRampingMargin / 100), 1, DISPCLKDPPCLKVCOSpeed);
+
+	DISPCLKWithoutRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(
+			PixelClockAfterODM * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100), 1, DISPCLKDPPCLKVCOSpeed);
+
+	MaxDispclkRoundedDownToDFSGranularity = dml32_RoundToDFSGranularity(MaxDispclk, 0, DISPCLKDPPCLKVCOSpeed);
+
+	if (DISPCLKWithoutRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity)
+		RequiredDispclk = DISPCLKWithoutRampingRoundedToDFSGranularity;
+	else if (DISPCLKWithRampingRoundedToDFSGranularity > MaxDispclkRoundedDownToDFSGranularity)
+		RequiredDispclk = MaxDispclkRoundedDownToDFSGranularity;
+	else
+		RequiredDispclk = DISPCLKWithRampingRoundedToDFSGranularity;
+
+	return RequiredDispclk;
+}
+
+double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed)
+{
+	if (Clock <= 0.0)
+		return 0.0;
+
+	if (round_up)
+		return VCOSpeed * 4.0 / dml_floor(VCOSpeed * 4.0 / Clock, 1.0);
+	else
+		return VCOSpeed * 4.0 / dml_ceil(VCOSpeed * 4.0 / Clock, 1.0);
+}
+
+void dml32_CalculateOutputLink(
+		double PHYCLKPerState,
+		double PHYCLKD18PerState,
+		double PHYCLKD32PerState,
+		double Downspreading,
+		bool IsMainSurfaceUsingTheIndicatedTiming,
+		enum output_encoder_class Output,
+		enum output_format_class OutputFormat,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClockBackEnd,
+		double ForcedOutputLinkBPP,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int NumberOfDSCSlices,
+		double AudioSampleRate,
+		unsigned int AudioSampleLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		bool DSCEnable,
+		unsigned int OutputLinkDPLanes,
+		enum dm_output_link_dp_rate OutputLinkDPRate,
+
+		/* Output */
+		bool *RequiresDSC,
+		double *RequiresFEC,
+		double  *OutBpp,
+		enum dm_output_type *OutputType,
+		enum dm_output_rate *OutputRate,
+		unsigned int *RequiredSlots)
+{
+	bool LinkDSCEnable;
+	unsigned int dummy;
+	*RequiresDSC = false;
+	*RequiresFEC = false;
+	*OutBpp = 0;
+	*OutputType = dm_output_type_unknown;
+	*OutputRate = dm_output_rate_unknown;
+
+	if (IsMainSurfaceUsingTheIndicatedTiming) {
+		if (Output == dm_hdmi) {
+			*RequiresDSC = false;
+			*RequiresFEC = false;
+			*OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive,
+					PixelClockBackEnd, ForcedOutputLinkBPP, false, Output, OutputFormat,
+					DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+					ODMModeNoDSC, ODMModeDSC, &dummy);
+			//OutputTypeAndRate = "HDMI";
+			*OutputType = dm_output_type_hdmi;
+
+		} else if (Output == dm_dp || Output == dm_dp2p0 || Output == dm_edp) {
+			if (DSCEnable == true) {
+				*RequiresDSC = true;
+				LinkDSCEnable = true;
+				if (Output == dm_dp || Output == dm_dp2p0)
+					*RequiresFEC = true;
+				else
+					*RequiresFEC = false;
+			} else {
+				*RequiresDSC = false;
+				LinkDSCEnable = false;
+				if (Output == dm_dp2p0)
+					*RequiresFEC = true;
+				else
+					*RequiresFEC = false;
+			}
+			if (Output == dm_dp2p0) {
+				*OutBpp = 0;
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr10) &&
+						PHYCLKD32PerState >= 10000 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR10";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr10;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr13p5) &&
+						*OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+
+					if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR13p5";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr13p5;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr20) &&
+						*OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 20000,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " UHBR20";
+					*OutputType = dm_output_type_dp2p0;
+					*OutputRate = dm_output_rate_dp_rate_uhbr20;
+				}
+			} else {
+				*OutBpp = 0;
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr) &&
+						PHYCLKPerState >= 270) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 2700,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr2) &&
+						*OutBpp == 0 && PHYCLKPerState >= 540) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,
+							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,
+							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+
+					if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == true &&
+							ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 5400,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR2";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr2;
+				}
+				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) {
+					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100,
+							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+							ForcedOutputLinkBPP, LinkDSCEnable, Output,
+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices,
+							AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC,
+							RequiredSlots);
+
+					if (*OutBpp == 0 && DSCEnable == true && ForcedOutputLinkBPP == 0) {
+						*RequiresDSC = true;
+						LinkDSCEnable = true;
+						if (Output == dm_dp)
+							*RequiresFEC = true;
+
+						*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 8100,
+								OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,
+								ForcedOutputLinkBPP, LinkDSCEnable, Output,
+								OutputFormat, DSCInputBitPerComponent,
+								NumberOfDSCSlices, AudioSampleRate, AudioSampleLayout,
+								ODMModeNoDSC, ODMModeDSC, RequiredSlots);
+					}
+					//OutputTypeAndRate = Output & " HBR3";
+					*OutputType = (Output == dm_dp) ? dm_output_type_dp : dm_output_type_edp;
+					*OutputRate = dm_output_rate_dp_rate_hbr3;
+				}
+			}
+		}
+	}
+}
+
+void dml32_CalculateDPPCLK(
+		unsigned int NumberOfActiveSurfaces,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKDPPCLKVCOSpeed,
+		double DPPCLKUsingSingleDPP[],
+		unsigned int DPPPerSurface[],
+
+		/* output */
+		double *GlobalDPPCLK,
+		double Dppclk[])
+{
+	unsigned int k;
+	*GlobalDPPCLK = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
+	}
+	*GlobalDPPCLK = dml32_RoundToDFSGranularity(*GlobalDPPCLK, 1, DISPCLKDPPCLKVCOSpeed);
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		Dppclk[k] = *GlobalDPPCLK / 255 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
+}
+
+double dml32_TruncToValidBPP(
+		double LinkBitRate,
+		unsigned int Lanes,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int DSCSlices,
+		unsigned int AudioRate,
+		unsigned int AudioLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		/* Output */
+		unsigned int *RequiredSlots)
+{
+	double    MaxLinkBPP;
+	unsigned int   MinDSCBPP;
+	double    MaxDSCBPP;
+	unsigned int   NonDSCBPP0;
+	unsigned int   NonDSCBPP1;
+	unsigned int   NonDSCBPP2;
+	unsigned int   NonDSCBPP3;
+
+	if (Format == dm_420) {
+		NonDSCBPP0 = 12;
+		NonDSCBPP1 = 15;
+		NonDSCBPP2 = 18;
+		MinDSCBPP = 6;
+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
+	} else if (Format == dm_444) {
+		NonDSCBPP0 = 18;
+		NonDSCBPP1 = 24;
+		NonDSCBPP2 = 30;
+		NonDSCBPP3 = 36;
+		MinDSCBPP = 8;
+		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
+	} else {
+		if (Output == dm_hdmi) {
+			NonDSCBPP0 = 24;
+			NonDSCBPP1 = 24;
+			NonDSCBPP2 = 24;
+		} else {
+			NonDSCBPP0 = 16;
+			NonDSCBPP1 = 20;
+			NonDSCBPP2 = 24;
+		}
+		if (Format == dm_n422) {
+			MinDSCBPP = 7;
+			MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
+		} else {
+			MinDSCBPP = 8;
+			MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0;
+		}
+	}
+	if (Output == dm_dp2p0) {
+		MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128 / 132 * 383 / 384 * 65536 / 65540;
+	} else if (DSCEnable && Output == dm_dp) {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100);
+	} else {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
+	}
+
+	if (DSCEnable) {
+		if (ODMModeDSC == dm_odm_combine_mode_4to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 16);
+		else if (ODMModeDSC == dm_odm_combine_mode_2to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 32);
+		else if (ODMModeDSC == dm_odm_split_mode_1to2)
+			MaxLinkBPP = 2 * MaxLinkBPP;
+	} else {
+		if (ODMModeNoDSC == dm_odm_combine_mode_4to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 16);
+		else if (ODMModeNoDSC == dm_odm_combine_mode_2to1)
+			MaxLinkBPP = dml_min(MaxLinkBPP, 32);
+		else if (ODMModeNoDSC == dm_odm_split_mode_1to2)
+			MaxLinkBPP = 2 * MaxLinkBPP;
+	}
+
+	if (DesiredBPP == 0) {
+		if (DSCEnable) {
+			if (MaxLinkBPP < MinDSCBPP)
+				return BPP_INVALID;
+			else if (MaxLinkBPP >= MaxDSCBPP)
+				return MaxDSCBPP;
+			else
+				return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
+		} else {
+			if (MaxLinkBPP >= NonDSCBPP3)
+				return NonDSCBPP3;
+			else if (MaxLinkBPP >= NonDSCBPP2)
+				return NonDSCBPP2;
+			else if (MaxLinkBPP >= NonDSCBPP1)
+				return NonDSCBPP1;
+			else if (MaxLinkBPP >= NonDSCBPP0)
+				return 16.0;
+			else
+				return BPP_INVALID;
+		}
+	} else {
+		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 ||
+				DesiredBPP == NonDSCBPP0 || DesiredBPP == NonDSCBPP3)) ||
+				(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP)))
+			return BPP_INVALID;
+		else
+			return DesiredBPP;
+	}
+
+	*RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1);
+
+	return BPP_INVALID;
+} // TruncToValidBPP
+
+double dml32_RequiredDTBCLK(
+		bool              DSCEnable,
+		double               PixelClock,
+		enum output_format_class  OutputFormat,
+		double               OutputBpp,
+		unsigned int              DSCSlices,
+		unsigned int                 HTotal,
+		unsigned int                 HActive,
+		unsigned int              AudioRate,
+		unsigned int              AudioLayout)
+{
+	double PixelWordRate = PixelClock /  (OutputFormat == dm_444 ? 1 : 2);
+	double HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp *
+			dml_ceil(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1);
+	double HCBlank = 64 + 32 *
+			dml_ceil(AudioRate *  (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1);
+	double AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal;
+	double HActiveTribyteRate = PixelWordRate * HCActive / HActive;
+
+	if (DSCEnable != true)
+		return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);
+
+	return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;
+}
+
+unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
+		enum odm_combine_mode ODMMode,
+		unsigned int DSCInputBitPerComponent,
+		double OutputBpp,
+		unsigned int HActive,
+		unsigned int HTotal,
+		unsigned int NumberOfDSCSlices,
+		enum output_format_class  OutputFormat,
+		enum output_encoder_class Output,
+		double PixelClock,
+		double PixelClockBackEnd)
+{
+	unsigned int DSCDelayRequirement_val;
+
+	if (DSCEnabled == true && OutputBpp != 0) {
+		if (ODMMode == dm_odm_combine_mode_4to1) {
+			DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 4,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output));
+		} else if (ODMMode == dm_odm_combine_mode_2to1) {
+			DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices / 2,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output));
+		} else {
+			DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp,
+					dml_ceil(HActive / NumberOfDSCSlices, 1), NumberOfDSCSlices,
+					OutputFormat, Output) + dml32_dscComputeDelay(OutputFormat, Output);
+		}
+
+		DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) *
+				dml_ceil(DSCDelayRequirement_val / HActive, 1);
+
+		DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd;
+
+	} else {
+		DSCDelayRequirement_val = 0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSCEnabled              = %d\n", __func__, DSCEnabled);
+	dml_print("DML::%s: OutputBpp               = %f\n", __func__, OutputBpp);
+	dml_print("DML::%s: HActive                 = %d\n", __func__, HActive);
+	dml_print("DML::%s: OutputFormat            = %d\n", __func__, OutputFormat);
+	dml_print("DML::%s: DSCInputBitPerComponent = %d\n", __func__, DSCInputBitPerComponent);
+	dml_print("DML::%s: NumberOfDSCSlices       = %d\n", __func__, NumberOfDSCSlices);
+	dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val);
+#endif
+
+	return DSCDelayRequirement_val;
+}
+
+void dml32_CalculateSurfaceSizeInMall(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCN,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		bool DCCEnable[],
+		bool ViewportStationary[],
+		unsigned int ViewportXStartY[],
+		unsigned int ViewportYStartY[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int ViewportWidthY[],
+		unsigned int ViewportHeightY[],
+		unsigned int BytesPerPixelY[],
+		unsigned int ViewportWidthC[],
+		unsigned int ViewportHeightC[],
+		unsigned int BytesPerPixelC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int ReadBlockWidthY[],
+		unsigned int ReadBlockWidthC[],
+		unsigned int ReadBlockHeightY[],
+		unsigned int ReadBlockHeightC[],
+
+		/* Output */
+		unsigned int    SurfaceSizeInMALL[],
+		bool *ExceededMALLSize)
+{
+	unsigned int TotalSurfaceSizeInMALL  = 0;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (ViewportStationary[k]) {
+			SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]),
+					dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1,
+						ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k],
+						ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k],
+						ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
+						ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
+						dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k];
+
+			if (ReadBlockWidthC[k] > 0) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]),
+							dml_floor(ViewportXStartC[k] + ViewportWidthC[k] +
+							ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
+							dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
+							dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]),
+							dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
+							ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
+							dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) *
+							BytesPerPixelC[k];
+			}
+			if (DCCEnable[k] == true) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]),
+							dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 *
+							Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k])
+							- dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k]))
+							* dml_min(dml_ceil(SurfaceHeightY[k], 8 *
+							Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
+							ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 *
+							Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8
+							* Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256;
+				if (Read256BytesBlockWidthC[k] > 0) {
+					SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+							dml_min(dml_ceil(SurfaceWidthC[k], 8 *
+								Read256BytesBlockWidthC[k]),
+								dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8
+								* Read256BytesBlockWidthC[k] - 1, 8 *
+								Read256BytesBlockWidthC[k]) -
+								dml_floor(ViewportXStartC[k], 8 *
+								Read256BytesBlockWidthC[k])) *
+								dml_min(dml_ceil(SurfaceHeightC[k], 8 *
+								Read256BytesBlockHeightC[k]),
+								dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
+								8 * Read256BytesBlockHeightC[k] - 1, 8 *
+								Read256BytesBlockHeightC[k]) -
+								dml_floor(ViewportYStartC[k], 8 *
+								Read256BytesBlockHeightC[k])) *
+								BytesPerPixelC[k] / 256;
+				}
+			}
+		} else {
+			SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] +
+					ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
+					dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] +
+							ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) *
+							BytesPerPixelY[k];
+			if (ReadBlockWidthC[k] > 0) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] +
+								ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
+						dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] +
+								ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) *
+								BytesPerPixelC[k];
+			}
+			if (DCCEnable[k] == true) {
+				SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+						dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 *
+								Read256BytesBlockWidthY[k] - 1), 8 *
+								Read256BytesBlockWidthY[k]) *
+						dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 *
+								Read256BytesBlockHeightY[k] - 1), 8 *
+								Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256;
+
+				if (Read256BytesBlockWidthC[k] > 0) {
+					SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
+							dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 *
+									Read256BytesBlockWidthC[k] - 1), 8 *
+									Read256BytesBlockWidthC[k]) *
+							dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 *
+									Read256BytesBlockHeightC[k] - 1), 8 *
+									Read256BytesBlockHeightC[k]) *
+									BytesPerPixelC[k] / 256;
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable)
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
+	}
+	*ExceededMALLSize =  (TotalSurfaceSizeInMALL <= MALLAllocatedForDCN * 1024 * 1024 ? false : true);
+} // CalculateSurfaceSizeInMall
+
+void dml32_CalculateVMRowAndSwath(
+		unsigned int NumberOfActiveSurfaces,
+		DmlPipe myPipe[],
+		unsigned int SurfaceSizeInMALL[],
+		unsigned int PTEBufferSizeInRequestsLuma,
+		unsigned int PTEBufferSizeInRequestsChroma,
+		unsigned int DCCMetaBufferSizeBytes,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int MALLAllocatedForDCN,
+		double SwathWidthY[],
+		double SwathWidthC[],
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes[],
+		unsigned int HostVMMinPageSize,
+
+		/* Output */
+		bool PTEBufferSizeNotExceeded[],
+		bool DCCMetaBufferSizeNotExceeded[],
+		unsigned int dpte_row_width_luma_ub[],
+		unsigned int dpte_row_width_chroma_ub[],
+		unsigned int dpte_row_height_luma[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int dpte_row_height_linear_luma[],     // VBA_DELTA
+		unsigned int dpte_row_height_linear_chroma[],   // VBA_DELTA
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int vm_group_bytes[],
+		unsigned int dpte_group_bytes[],
+		unsigned int PixelPTEReqWidthY[],
+		unsigned int PixelPTEReqHeightY[],
+		unsigned int PTERequestSizeY[],
+		unsigned int PixelPTEReqWidthC[],
+		unsigned int PixelPTEReqHeightC[],
+		unsigned int PTERequestSizeC[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int meta_pte_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		unsigned int meta_pte_bytes_per_frame_ub_c[],
+		double PrefetchSourceLinesY[],
+		double PrefetchSourceLinesC[],
+		double VInitPreFillY[],
+		double VInitPreFillC[],
+		unsigned int MaxNumSwathY[],
+		unsigned int MaxNumSwathC[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double PixelPTEBytesPerRow[],
+		double PDEAndMetaPTEBytesFrame[],
+		double MetaRowByte[],
+		bool use_one_row_for_frame[],
+		bool use_one_row_for_frame_flip[],
+		bool UsesMALLForStaticScreen[],
+		bool PTE_BUFFER_MODE[],
+		unsigned int BIGK_FRAGMENT_SIZE[])
+{
+	unsigned int k;
+	unsigned int PTEBufferSizeInRequestsForLuma[DC__NUM_DPP__MAX];
+	unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];
+	unsigned int PDEAndMetaPTEBytesFrameY;
+	unsigned int PDEAndMetaPTEBytesFrameC;
+	unsigned int MetaRowByteY[DC__NUM_DPP__MAX];
+	unsigned int MetaRowByteC[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_width_luma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_luma_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_chroma_one_row_per_frame[DC__NUM_DPP__MAX];
+	bool one_row_per_frame_fits_in_buffer[DC__NUM_DPP__MAX];
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (HostVMEnable == true) {
+			vm_group_bytes[k] = 512;
+			dpte_group_bytes[k] = 512;
+		} else if (GPUVMEnable == true) {
+			vm_group_bytes[k] = 2048;
+			if (GPUVMMinPageSizeKBytes[k] >= 64 && IsVertical(myPipe[k].SourceRotation))
+				dpte_group_bytes[k] = 512;
+			else
+				dpte_group_bytes[k] = 2048;
+		} else {
+			vm_group_bytes[k] = 0;
+			dpte_group_bytes[k] = 0;
+		}
+
+		if (myPipe[k].SourcePixelFormat == dm_420_8 || myPipe[k].SourcePixelFormat == dm_420_10 ||
+				myPipe[k].SourcePixelFormat == dm_420_12 ||
+				myPipe[k].SourcePixelFormat == dm_rgbe_alpha) {
+			if ((myPipe[k].SourcePixelFormat == dm_420_10 || myPipe[k].SourcePixelFormat == dm_420_12) &&
+					!IsVertical(myPipe[k].SourceRotation)) {
+				PTEBufferSizeInRequestsForLuma[k] =
+						(PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma) / 2;
+				PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsForLuma[k];
+			} else {
+				PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma;
+				PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsChroma;
+			}
+
+			PDEAndMetaPTEBytesFrameC = dml32_CalculateVMAndRowBytes(
+					myPipe[k].ViewportStationary,
+					myPipe[k].DCCEnable,
+					myPipe[k].DPPPerSurface,
+					myPipe[k].BlockHeight256BytesC,
+					myPipe[k].BlockWidth256BytesC,
+					myPipe[k].SourcePixelFormat,
+					myPipe[k].SurfaceTiling,
+					myPipe[k].BytePerPixelC,
+					myPipe[k].SourceRotation,
+					SwathWidthC[k],
+					myPipe[k].ViewportHeightChroma,
+					myPipe[k].ViewportXStartC,
+					myPipe[k].ViewportYStartC,
+					GPUVMEnable,
+					HostVMEnable,
+					HostVMMaxNonCachedPageTableLevels,
+					GPUVMMaxPageTableLevels,
+					GPUVMMinPageSizeKBytes[k],
+					HostVMMinPageSize,
+					PTEBufferSizeInRequestsForChroma[k],
+					myPipe[k].PitchC,
+					myPipe[k].DCCMetaPitchC,
+					myPipe[k].BlockWidthC,
+					myPipe[k].BlockHeightC,
+
+					/* Output */
+					&MetaRowByteC[k],
+					&PixelPTEBytesPerRowC[k],
+					&dpte_row_width_chroma_ub[k],
+					&dpte_row_height_chroma[k],
+					&dpte_row_height_linear_chroma[k],
+					&PixelPTEBytesPerRowC_one_row_per_frame[k],
+					&dpte_row_width_chroma_ub_one_row_per_frame[k],
+					&dpte_row_height_chroma_one_row_per_frame[k],
+					&meta_req_width_chroma[k],
+					&meta_req_height_chroma[k],
+					&meta_row_width_chroma[k],
+					&meta_row_height_chroma[k],
+					&PixelPTEReqWidthC[k],
+					&PixelPTEReqHeightC[k],
+					&PTERequestSizeC[k],
+					&dpde0_bytes_per_frame_ub_c[k],
+					&meta_pte_bytes_per_frame_ub_c[k]);
+
+			PrefetchSourceLinesC[k] = dml32_CalculatePrefetchSourceLines(
+					myPipe[k].VRatioChroma,
+					myPipe[k].VTapsChroma,
+					myPipe[k].InterlaceEnable,
+					myPipe[k].ProgressiveToInterlaceUnitInOPP,
+					myPipe[k].SwathHeightC,
+					myPipe[k].SourceRotation,
+					myPipe[k].ViewportStationary,
+					SwathWidthC[k],
+					myPipe[k].ViewportHeightChroma,
+					myPipe[k].ViewportXStartC,
+					myPipe[k].ViewportYStartC,
+
+					/* Output */
+					&VInitPreFillC[k],
+					&MaxNumSwathC[k]);
+		} else {
+			PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma;
+			PTEBufferSizeInRequestsForChroma[k] = 0;
+			PixelPTEBytesPerRowC[k] = 0;
+			PDEAndMetaPTEBytesFrameC = 0;
+			MetaRowByteC[k] = 0;
+			MaxNumSwathC[k] = 0;
+			PrefetchSourceLinesC[k] = 0;
+			dpte_row_height_chroma_one_row_per_frame[k] = 0;
+			dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
+			PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
+		}
+
+		PDEAndMetaPTEBytesFrameY = dml32_CalculateVMAndRowBytes(
+				myPipe[k].ViewportStationary,
+				myPipe[k].DCCEnable,
+				myPipe[k].DPPPerSurface,
+				myPipe[k].BlockHeight256BytesY,
+				myPipe[k].BlockWidth256BytesY,
+				myPipe[k].SourcePixelFormat,
+				myPipe[k].SurfaceTiling,
+				myPipe[k].BytePerPixelY,
+				myPipe[k].SourceRotation,
+				SwathWidthY[k],
+				myPipe[k].ViewportHeight,
+				myPipe[k].ViewportXStart,
+				myPipe[k].ViewportYStart,
+				GPUVMEnable,
+				HostVMEnable,
+				HostVMMaxNonCachedPageTableLevels,
+				GPUVMMaxPageTableLevels,
+				GPUVMMinPageSizeKBytes[k],
+				HostVMMinPageSize,
+				PTEBufferSizeInRequestsForLuma[k],
+				myPipe[k].PitchY,
+				myPipe[k].DCCMetaPitchY,
+				myPipe[k].BlockWidthY,
+				myPipe[k].BlockHeightY,
+
+				/* Output */
+				&MetaRowByteY[k],
+				&PixelPTEBytesPerRowY[k],
+				&dpte_row_width_luma_ub[k],
+				&dpte_row_height_luma[k],
+				&dpte_row_height_linear_luma[k],
+				&PixelPTEBytesPerRowY_one_row_per_frame[k],
+				&dpte_row_width_luma_ub_one_row_per_frame[k],
+				&dpte_row_height_luma_one_row_per_frame[k],
+				&meta_req_width[k],
+				&meta_req_height[k],
+				&meta_row_width[k],
+				&meta_row_height[k],
+				&PixelPTEReqWidthY[k],
+				&PixelPTEReqHeightY[k],
+				&PTERequestSizeY[k],
+				&dpde0_bytes_per_frame_ub_l[k],
+				&meta_pte_bytes_per_frame_ub_l[k]);
+
+		PrefetchSourceLinesY[k] = dml32_CalculatePrefetchSourceLines(
+				myPipe[k].VRatio,
+				myPipe[k].VTaps,
+				myPipe[k].InterlaceEnable,
+				myPipe[k].ProgressiveToInterlaceUnitInOPP,
+				myPipe[k].SwathHeightY,
+				myPipe[k].SourceRotation,
+				myPipe[k].ViewportStationary,
+				SwathWidthY[k],
+				myPipe[k].ViewportHeight,
+				myPipe[k].ViewportXStart,
+				myPipe[k].ViewportYStart,
+
+				/* Output */
+				&VInitPreFillY[k],
+				&MaxNumSwathY[k]);
+
+		PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
+		MetaRowByte[k] = MetaRowByteY[k] + MetaRowByteC[k];
+
+		if (PixelPTEBytesPerRowY[k] <= 64 * PTEBufferSizeInRequestsForLuma[k] &&
+				PixelPTEBytesPerRowC[k] <= 64 * PTEBufferSizeInRequestsForChroma[k]) {
+			PTEBufferSizeNotExceeded[k] = true;
+		} else {
+			PTEBufferSizeNotExceeded[k] = false;
+		}
+
+		one_row_per_frame_fits_in_buffer[k] = (PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 *
+			PTEBufferSizeInRequestsForLuma[k] &&
+			PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * PTEBufferSizeInRequestsForChroma[k]);
+	}
+
+	dml32_CalculateMALLUseForStaticScreen(
+			NumberOfActiveSurfaces,
+			MALLAllocatedForDCN,
+			UseMALLForStaticScreen,   // mode
+			SurfaceSizeInMALL,
+			one_row_per_frame_fits_in_buffer,
+			/* Output */
+			UsesMALLForStaticScreen); // boolen
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		PTE_BUFFER_MODE[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
+				(GPUVMMinPageSizeKBytes[k] > 64);
+		BIGK_FRAGMENT_SIZE[k] = dml_log2(GPUVMMinPageSizeKBytes[k] * 1024) - 12;
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, SurfaceSizeInMALL = %d\n",  __func__, k, SurfaceSizeInMALL[k]);
+		dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n",  __func__, k, UsesMALLForStaticScreen[k]);
+#endif
+		use_one_row_for_frame[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
+				(GPUVMMinPageSizeKBytes[k] > 64 && IsVertical(myPipe[k].SourceRotation));
+
+		use_one_row_for_frame_flip[k] = use_one_row_for_frame[k] &&
+				!(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame);
+
+		if (use_one_row_for_frame[k]) {
+			dpte_row_height_luma[k] = dpte_row_height_luma_one_row_per_frame[k];
+			dpte_row_width_luma_ub[k] = dpte_row_width_luma_ub_one_row_per_frame[k];
+			PixelPTEBytesPerRowY[k] = PixelPTEBytesPerRowY_one_row_per_frame[k];
+			dpte_row_height_chroma[k] = dpte_row_height_chroma_one_row_per_frame[k];
+			dpte_row_width_chroma_ub[k] = dpte_row_width_chroma_ub_one_row_per_frame[k];
+			PixelPTEBytesPerRowC[k] = PixelPTEBytesPerRowC_one_row_per_frame[k];
+			PTEBufferSizeNotExceeded[k] = one_row_per_frame_fits_in_buffer[k];
+		}
+
+		if (MetaRowByte[k] <= DCCMetaBufferSizeBytes)
+			DCCMetaBufferSizeNotExceeded[k] = true;
+		else
+			DCCMetaBufferSizeNotExceeded[k] = false;
+
+		PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY[k] + PixelPTEBytesPerRowC[k];
+		if (use_one_row_for_frame[k])
+			PixelPTEBytesPerRow[k] = PixelPTEBytesPerRow[k] / 2;
+
+		dml32_CalculateRowBandwidth(
+				GPUVMEnable,
+				myPipe[k].SourcePixelFormat,
+				myPipe[k].VRatio,
+				myPipe[k].VRatioChroma,
+				myPipe[k].DCCEnable,
+				myPipe[k].HTotal / myPipe[k].PixelClock,
+				MetaRowByteY[k], MetaRowByteC[k],
+				meta_row_height[k],
+				meta_row_height_chroma[k],
+				PixelPTEBytesPerRowY[k],
+				PixelPTEBytesPerRowC[k],
+				dpte_row_height_luma[k],
+				dpte_row_height_chroma[k],
+
+				/* Output */
+				&meta_row_bw[k],
+				&dpte_row_bw[k]);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, use_one_row_for_frame        = %d\n",  __func__, k, use_one_row_for_frame[k]);
+		dml_print("DML::%s: k=%d, use_one_row_for_frame_flip   = %d\n",
+				__func__, k, use_one_row_for_frame_flip[k]);
+		dml_print("DML::%s: k=%d, UseMALLForPStateChange       = %d\n",
+				__func__, k, UseMALLForPStateChange[k]);
+		dml_print("DML::%s: k=%d, dpte_row_height_luma         = %d\n",  __func__, k, dpte_row_height_luma[k]);
+		dml_print("DML::%s: k=%d, dpte_row_width_luma_ub       = %d\n",
+				__func__, k, dpte_row_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRowY         = %d\n",  __func__, k, PixelPTEBytesPerRowY[k]);
+		dml_print("DML::%s: k=%d, dpte_row_height_chroma       = %d\n",
+				__func__, k, dpte_row_height_chroma[k]);
+		dml_print("DML::%s: k=%d, dpte_row_width_chroma_ub     = %d\n",
+				__func__, k, dpte_row_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRowC         = %d\n",  __func__, k, PixelPTEBytesPerRowC[k]);
+		dml_print("DML::%s: k=%d, PixelPTEBytesPerRow          = %d\n",  __func__, k, PixelPTEBytesPerRow[k]);
+		dml_print("DML::%s: k=%d, PTEBufferSizeNotExceeded     = %d\n",
+				__func__, k, PTEBufferSizeNotExceeded[k]);
+		dml_print("DML::%s: k=%d, PTE_BUFFER_MODE              = %d\n", __func__, k, PTE_BUFFER_MODE[k]);
+		dml_print("DML::%s: k=%d, BIGK_FRAGMENT_SIZE           = %d\n", __func__, k, BIGK_FRAGMENT_SIZE[k]);
+#endif
+	}
+} // CalculateVMRowAndSwath
+
+unsigned int dml32_CalculateVMAndRowBytes(
+		bool ViewportStationary,
+		bool DCCEnable,
+		unsigned int NumberOfDPPs,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum dm_rotation_angle SourceRotation,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int    ViewportXStart,
+		unsigned int    ViewportYStart,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int MacroTileWidth,
+		unsigned int MacroTileHeight,
+
+		/* Output */
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		unsigned int    *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *dpte_row_height_linear,
+		unsigned int    *PixelPTEBytesPerRow_one_row_per_frame,
+		unsigned int    *dpte_row_width_ub_one_row_per_frame,
+		unsigned int    *dpte_row_height_one_row_per_frame,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		unsigned int    *DPDE0BytesFrame,
+		unsigned int    *MetaPTEBytesFrame)
+{
+	unsigned int MPDEBytesFrame;
+	unsigned int DCCMetaSurfaceBytes;
+	unsigned int ExtraDPDEBytesFrame;
+	unsigned int PDEAndMetaPTEBytesFrame;
+	unsigned int HostVMDynamicLevels = 0;
+	unsigned int    MacroTileSizeBytes;
+	unsigned int    vp_height_meta_ub;
+	unsigned int    vp_height_dpte_ub;
+	unsigned int PixelPTEReqWidth_linear = 0; // VBA_DELTA. VBA doesn't calculate this
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048)
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576)
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		else
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+	}
+
+	*MetaRequestHeight = 8 * BlockHeight256Bytes;
+	*MetaRequestWidth = 8 * BlockWidth256Bytes;
+	if (SurfaceTiling == dm_sw_linear) {
+		*meta_row_height = 32;
+		*meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth)
+				- dml_floor(ViewportXStart, *MetaRequestWidth);
+	} else if (!IsVertical(SourceRotation)) {
+		*meta_row_height = *MetaRequestHeight;
+		if (ViewportStationary && NumberOfDPPs == 1) {
+			*meta_row_width = dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1,
+					*MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth);
+		} else {
+			*meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth;
+		}
+		*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
+	} else {
+		*meta_row_height = *MetaRequestWidth;
+		if (ViewportStationary && NumberOfDPPs == 1) {
+			*meta_row_width = dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1,
+					*MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight);
+		} else {
+			*meta_row_width = dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight;
+		}
+		*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
+	}
+
+	if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) {
+		vp_height_meta_ub = dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1,
+				64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes);
+	} else if (!IsVertical(SourceRotation)) {
+		vp_height_meta_ub = dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes;
+	} else {
+		vp_height_meta_ub = dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes;
+	}
+
+	DCCMetaSurfaceBytes = DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0;
+
+	if (GPUVMEnable == true) {
+		*MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) /
+				(8 * 4.0 * 1024), 1) + 1) * 64;
+		MPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 1);
+	} else {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+	}
+
+	if (DCCEnable != true) {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+		*MetaRowByte = 0;
+	}
+
+	MacroTileSizeBytes = MacroTileWidth * BytePerPixel * MacroTileHeight;
+
+	if (GPUVMEnable == true && GPUVMMaxPageTableLevels > 1) {
+		if (ViewportStationary && (NumberOfDPPs == 1 || !IsVertical(SourceRotation))) {
+			vp_height_dpte_ub = dml_floor(ViewportYStart + ViewportHeight +
+					MacroTileHeight - 1, MacroTileHeight) -
+					dml_floor(ViewportYStart, MacroTileHeight);
+		} else if (!IsVertical(SourceRotation)) {
+			vp_height_dpte_ub = dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight;
+		} else {
+			vp_height_dpte_ub = dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight;
+		}
+		*DPDE0BytesFrame = 64 * (dml_ceil((Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) /
+				(8 * 2097152), 1) + 1);
+		ExtraDPDEBytesFrame = 128 * (GPUVMMaxPageTableLevels - 2);
+	} else {
+		*DPDE0BytesFrame = 0;
+		ExtraDPDEBytesFrame = 0;
+		vp_height_dpte_ub = 0;
+	}
+
+	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable);
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: SwModeLinear = %d\n", __func__, SurfaceTiling == dm_sw_linear);
+	dml_print("DML::%s: BytePerPixel = %d\n", __func__, BytePerPixel);
+	dml_print("DML::%s: GPUVMMaxPageTableLevels = %d\n", __func__, GPUVMMaxPageTableLevels);
+	dml_print("DML::%s: BlockHeight256Bytes = %d\n", __func__, BlockHeight256Bytes);
+	dml_print("DML::%s: BlockWidth256Bytes = %d\n", __func__, BlockWidth256Bytes);
+	dml_print("DML::%s: MacroTileHeight = %d\n", __func__, MacroTileHeight);
+	dml_print("DML::%s: MacroTileWidth = %d\n", __func__, MacroTileWidth);
+	dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame);
+	dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame);
+	dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame);
+	dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: ViewportHeight = %d\n", __func__, ViewportHeight);
+	dml_print("DML::%s: SwathWidth = %d\n", __func__, SwathWidth);
+	dml_print("DML::%s: vp_height_dpte_ub = %d\n", __func__, vp_height_dpte_ub);
+#endif
+
+	if (HostVMEnable == true)
+		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels);
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*PixelPTEReqHeight = 1;
+		*PixelPTEReqWidth = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel;
+		PixelPTEReqWidth_linear = GPUVMMinPageSizeKBytes * 1024 * 8 / BytePerPixel;
+		*PTERequestSize = 64;
+	} else if (GPUVMMinPageSizeKBytes == 4) {
+		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
+		*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
+		*PTERequestSize = 128;
+	} else {
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 *  1024 * GPUVMMinPageSizeKBytes / (MacroTileHeight * BytePerPixel);
+		*PTERequestSize = 64;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d (after HostVM factor)\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: PixelPTEReqHeight = %d\n", __func__, *PixelPTEReqHeight);
+	dml_print("DML::%s: PixelPTEReqWidth = %d\n", __func__, *PixelPTEReqWidth);
+	dml_print("DML::%s: PixelPTEReqWidth_linear = %d\n", __func__, PixelPTEReqWidth_linear);
+	dml_print("DML::%s: PTERequestSize = %d\n", __func__, *PTERequestSize);
+	dml_print("DML::%s: Pitch = %d\n", __func__, Pitch);
+#endif
+
+	*dpte_row_height_one_row_per_frame = vp_height_dpte_ub;
+	*dpte_row_width_ub_one_row_per_frame = (dml_ceil(((double)Pitch * (double)*dpte_row_height_one_row_per_frame /
+			(double) *PixelPTEReqHeight - 1) / (double) *PixelPTEReqWidth, 1) + 1) *
+					(double) *PixelPTEReqWidth;
+	*PixelPTEBytesPerRow_one_row_per_frame = *dpte_row_width_ub_one_row_per_frame / *PixelPTEReqWidth *
+			*PTERequestSize;
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+				*PixelPTEReqWidth / Pitch), 1));
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: dpte_row_height = %d (1)\n", __func__,
+				PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch);
+		dml_print("DML::%s: dpte_row_height = %f (2)\n", __func__,
+				dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch));
+		dml_print("DML::%s: dpte_row_height = %f (3)\n", __func__,
+				dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
+		dml_print("DML::%s: dpte_row_height = %d (4)\n", __func__,
+				1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+						*PixelPTEReqWidth / Pitch), 1));
+		dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height);
+#endif
+		*dpte_row_width_ub = dml_ceil(((double) Pitch * (double) *dpte_row_height - 1),
+				(double) *PixelPTEReqWidth) + *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / (double)*PixelPTEReqWidth * (double)*PTERequestSize;
+
+		// VBA_DELTA, VBA doesn't have programming value for pte row height linear.
+		*dpte_row_height_linear = 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
+				PixelPTEReqWidth_linear / Pitch), 1);
+		if (*dpte_row_height_linear > 128)
+			*dpte_row_height_linear = 128;
+
+	} else if (!IsVertical(SourceRotation)) {
+		*dpte_row_height = *PixelPTEReqHeight;
+
+		if (GPUVMMinPageSizeKBytes > 64) {
+			*dpte_row_width_ub = (dml_ceil((Pitch * *dpte_row_height / *PixelPTEReqHeight - 1) /
+					*PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		} else if (ViewportStationary && (NumberOfDPPs == 1)) {
+			*dpte_row_width_ub = dml_floor(ViewportXStart + SwathWidth +
+					*PixelPTEReqWidth - 1, *PixelPTEReqWidth) -
+					dml_floor(ViewportXStart, *PixelPTEReqWidth);
+		} else {
+			*dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) *
+					*PixelPTEReqWidth;
+		}
+
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else {
+		*dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth);
+
+		if (ViewportStationary && (NumberOfDPPs == 1)) {
+			*dpte_row_width_ub = dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1,
+					*PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight);
+		} else {
+			*dpte_row_width_ub = (dml_ceil((SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1)
+					* *PixelPTEReqHeight;
+		}
+
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
+	}
+
+	if (GPUVMEnable != true)
+		*PixelPTEBytesPerRow = 0;
+	if (HostVMEnable == true)
+		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMMinPageSizeKBytes = %d\n", __func__, GPUVMMinPageSizeKBytes);
+	dml_print("DML::%s: dpte_row_height = %d\n", __func__, *dpte_row_height);
+	dml_print("DML::%s: dpte_row_height_linear = %d\n", __func__, *dpte_row_height_linear);
+	dml_print("DML::%s: dpte_row_width_ub = %d\n", __func__, *dpte_row_width_ub);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, *PixelPTEBytesPerRow);
+	dml_print("DML::%s: PTEBufferSizeInRequests = %d\n", __func__, PTEBufferSizeInRequests);
+	dml_print("DML::%s: dpte_row_height_one_row_per_frame = %d\n", __func__, *dpte_row_height_one_row_per_frame);
+	dml_print("DML::%s: dpte_row_width_ub_one_row_per_frame = %d\n",
+			__func__, *dpte_row_width_ub_one_row_per_frame);
+	dml_print("DML::%s: PixelPTEBytesPerRow_one_row_per_frame = %d\n",
+			__func__, *PixelPTEBytesPerRow_one_row_per_frame);
+	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n",
+			*MetaPTEBytesFrame);
+#endif
+
+	return PDEAndMetaPTEBytesFrame;
+} // CalculateVMAndRowBytes
+
+double dml32_CalculatePrefetchSourceLines(
+		double VRatio,
+		unsigned int VTaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		enum dm_rotation_angle SourceRotation,
+		bool ViewportStationary,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int ViewportXStart,
+		unsigned int ViewportYStart,
+
+		/* Output */
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath)
+{
+
+	unsigned int vp_start_rot;
+	unsigned int sw0_tmp;
+	unsigned int MaxPartialSwath;
+	double numLines;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VRatio = %f\n", __func__, VRatio);
+	dml_print("DML::%s: VTaps = %d\n", __func__, VTaps);
+	dml_print("DML::%s: ViewportXStart = %d\n", __func__, ViewportXStart);
+	dml_print("DML::%s: ViewportYStart = %d\n", __func__, ViewportYStart);
+	dml_print("DML::%s: ViewportStationary = %d\n", __func__, ViewportStationary);
+	dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight);
+#endif
+	if (ProgressiveToInterlaceUnitInOPP)
+		*VInitPreFill = dml_floor((VRatio + (double) VTaps + 1) / 2.0, 1);
+	else
+		*VInitPreFill = dml_floor((VRatio + (double) VTaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
+
+	if (ViewportStationary) {
+		if (SourceRotation == dm_rotation_180 || SourceRotation == dm_rotation_180m) {
+			vp_start_rot = SwathHeight -
+					(((unsigned int) (ViewportYStart + ViewportHeight - 1) % SwathHeight) + 1);
+		} else if (SourceRotation == dm_rotation_270 || SourceRotation == dm_rotation_90m) {
+			vp_start_rot = ViewportXStart;
+		} else if (SourceRotation == dm_rotation_90 || SourceRotation == dm_rotation_270m) {
+			vp_start_rot = SwathHeight -
+					(((unsigned int)(ViewportYStart + SwathWidth - 1) % SwathHeight) + 1);
+		} else {
+			vp_start_rot = ViewportYStart;
+		}
+		sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight);
+		if (sw0_tmp < *VInitPreFill)
+			*MaxNumSwath = dml_ceil((*VInitPreFill - sw0_tmp) / SwathHeight, 1) + 1;
+		else
+			*MaxNumSwath = 1;
+		MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight);
+	} else {
+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1;
+		if (*VInitPreFill > 1)
+			MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight);
+		else
+			MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight);
+	}
+	numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: vp_start_rot = %d\n", __func__, vp_start_rot);
+	dml_print("DML::%s: VInitPreFill = %d\n", __func__, *VInitPreFill);
+	dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath);
+	dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath);
+	dml_print("DML::%s: Prefetch source lines = %3.2f\n", __func__, numLines);
+#endif
+	return numLines;
+
+} // CalculatePrefetchSourceLines
+
+void dml32_CalculateMALLUseForStaticScreen(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCNFinal,
+		enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen,
+		unsigned int SurfaceSizeInMALL[],
+		bool one_row_per_frame_fits_in_buffer[],
+
+		/* output */
+		bool UsesMALLForStaticScreen[])
+{
+	unsigned int k;
+	unsigned int SurfaceToAddToMALL;
+	bool CanAddAnotherSurfaceToMALL;
+	unsigned int TotalSurfaceSizeInMALL;
+
+	TotalSurfaceSizeInMALL = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable);
+		if (UsesMALLForStaticScreen[k])
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n",  __func__, k, UsesMALLForStaticScreen[k]);
+		dml_print("DML::%s: k=%d, TotalSurfaceSizeInMALL = %d\n",  __func__, k, TotalSurfaceSizeInMALL);
+#endif
+	}
+
+	SurfaceToAddToMALL = 0;
+	CanAddAnotherSurfaceToMALL = true;
+	while (CanAddAnotherSurfaceToMALL) {
+		CanAddAnotherSurfaceToMALL = false;
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
+					!UsesMALLForStaticScreen[k] &&
+					UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable &&
+					one_row_per_frame_fits_in_buffer[k] &&
+					(!CanAddAnotherSurfaceToMALL ||
+					SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
+				CanAddAnotherSurfaceToMALL = true;
+				SurfaceToAddToMALL = k;
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%d, UseMALLForStaticScreen = %d (dis, en, optimize)\n",
+						__func__, k, UseMALLForStaticScreen[k]);
+#endif
+			}
+		}
+		if (CanAddAnotherSurfaceToMALL) {
+			UsesMALLForStaticScreen[SurfaceToAddToMALL] = true;
+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[SurfaceToAddToMALL];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: SurfaceToAddToMALL       = %d\n",  __func__, SurfaceToAddToMALL);
+			dml_print("DML::%s: TotalSurfaceSizeInMALL   = %d\n",  __func__, TotalSurfaceSizeInMALL);
+#endif
+
+		}
+	}
+}
+
+void dml32_CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		/* Output */
+		double *meta_row_bw,
+		double *dpte_row_bw)
+{
+	if (DCCEnable != true) {
+		*meta_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 ||
+			SourcePixelFormat == dm_rgbe_alpha) {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma *
+				MetaRowByteChroma / (meta_row_height_chroma * LineTime);
+	} else {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
+	}
+
+	if (GPUVMEnable != true) {
+		*dpte_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 ||
+			SourcePixelFormat == dm_rgbe_alpha) {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime) +
+				VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime);
+	} else {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
+	}
+}
+
+double dml32_CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool   DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock)
+{
+	double   ret;
+
+	ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
+	if (DoUrgentLatencyAdjustment == true) {
+		ret = ret + UrgentLatencyAdjustmentFabricClockComponent *
+				(UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1);
+	}
+	return ret;
+}
+
+void dml32_CalculateUrgentBurstFactor(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		unsigned int    swath_width_luma_ub,
+		unsigned int    swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double  LineTime,
+		double  UrgentLatency,
+		double  CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double  VRatio,
+		double  VRatioC,
+		double  BytePerPixelInDETY,
+		double  BytePerPixelInDETC,
+		unsigned int    DETBufferSizeY,
+		unsigned int    DETBufferSizeC,
+		/* Output */
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool   *NotEnoughUrgentLatencyHiding)
+{
+	double       LinesInDETLuma;
+	double       LinesInDETChroma;
+	unsigned int LinesInCursorBuffer;
+	double       CursorBufferSizeInTime;
+	double       DETBufferSizeInTimeLuma;
+	double       DETBufferSizeInTimeChroma;
+
+	*NotEnoughUrgentLatencyHiding = 0;
+
+	if (CursorWidth > 0) {
+		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 /
+				(CursorWidth * CursorBPP / 8.0)), 1.0);
+		if (VRatio > 0) {
+			CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
+			if (CursorBufferSizeInTime - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorCursor = 0;
+			} else {
+				*UrgentBurstFactorCursor = CursorBufferSizeInTime /
+						(CursorBufferSizeInTime - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorCursor = 1;
+		}
+	}
+
+	LinesInDETLuma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ? 1024*1024 :
+			DETBufferSizeY) / BytePerPixelInDETY / swath_width_luma_ub;
+
+	if (VRatio > 0) {
+		DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
+		if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
+			*NotEnoughUrgentLatencyHiding = 1;
+			*UrgentBurstFactorLuma = 0;
+		} else {
+			*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);
+		}
+	} else {
+		*UrgentBurstFactorLuma = 1;
+	}
+
+	if (BytePerPixelInDETC > 0) {
+		LinesInDETChroma = (UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe ?
+					1024 * 1024 : DETBufferSizeC) / BytePerPixelInDETC
+					/ swath_width_chroma_ub;
+
+		if (VRatio > 0) {
+			DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio;
+			if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorChroma = 0;
+			} else {
+				*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma
+						/ (DETBufferSizeInTimeChroma - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorChroma = 1;
+		}
+	}
+} // CalculateUrgentBurstFactor
+
+void dml32_CalculateDCFCLKDeepSleep(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerSurface[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double Dppclk[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int ReturnBusWidth,
+
+		/* Output */
+		double *DCFClkDeepSleep)
+{
+	unsigned int k;
+	double   DisplayPipeLineDeliveryTimeLuma;
+	double   DisplayPipeLineDeliveryTimeChroma;
+	double   DCFClkDeepSleepPerSurface[DC__NUM_DPP__MAX];
+	double ReadBandwidth = 0.0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k]
+					/ PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] *
+						DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k]
+						/ Dppclk[k];
+			}
+		}
+
+		if (BytePerPixelC[k] > 0) {
+			DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] *
+					BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
+					__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] /
+					32.0 / DisplayPipeLineDeliveryTimeChroma);
+		} else {
+			DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] /
+					64.0 / DisplayPipeLineDeliveryTimeLuma;
+		}
+		DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+
+	*DCFClkDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / (double) ReturnBusWidth);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: __DML_MIN_DCFCLK_FACTOR__ = %f\n", __func__, __DML_MIN_DCFCLK_FACTOR__);
+	dml_print("DML::%s: ReadBandwidth = %f\n", __func__, ReadBandwidth);
+	dml_print("DML::%s: ReturnBusWidth = %d\n", __func__, ReturnBusWidth);
+	dml_print("DML::%s: DCFClkDeepSleep = %f\n", __func__, *DCFClkDeepSleep);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k)
+		*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCFClkDeepSleep = %f (final)\n", __func__, *DCFClkDeepSleep);
+#endif
+} // CalculateDCFCLKDeepSleep
+
+double dml32_CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		unsigned int         WritebackDestinationWidth,
+		unsigned int         WritebackDestinationHeight,
+		unsigned int         WritebackSourceHeight,
+		unsigned int HTotal)
+{
+	double CalculateWriteBackDelay;
+	double Line_length;
+	double Output_lines_last_notclamped;
+	double WritebackVInit;
+
+	WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2;
+	Line_length = dml_max((double) WritebackDestinationWidth,
+			dml_ceil((double)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps);
+	Output_lines_last_notclamped = WritebackDestinationHeight - 1 -
+			dml_ceil(((double)WritebackSourceHeight -
+					(double) WritebackVInit) / (double)WritebackVRatio, 1.0);
+	if (Output_lines_last_notclamped < 0) {
+		CalculateWriteBackDelay = 0;
+	} else {
+		CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length +
+				(HTotal - WritebackDestinationWidth) + 80;
+	}
+	return CalculateWriteBackDelay;
+}
+
+void dml32_UseMinimumDCFCLK(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool DRRDisplay[],
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int MaxPrefetchMode,
+		double DRAMClockChangeLatencyFinal,
+		double FCLKChangeLatency,
+		double SREnterPlusExitTime,
+		unsigned int ReturnBusWidth,
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		bool ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealSDPPortBWReceivedAfterUrgLatency,
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		unsigned int DynamicMetadataTransmittedBytes[],
+		unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFClkDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		unsigned int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		/* Output */
+		double DCFCLKState[][2])
+{
+	unsigned int i, j, k;
+	unsigned int     dummy1;
+	double dummy2, dummy3;
+	double   NormalEfficiency;
+	double   TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+
+	NormalEfficiency = PercentOfIdealSDPPortBWReceivedAfterUrgLatency / 100.0;
+	for  (i = 0; i < DC__VOLTAGE_STATES; ++i) {
+		for  (j = 0; j <= 1; ++j) {
+			double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX];
+			double PrefetchPixelLinesTime[DC__NUM_DPP__MAX];
+			double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX];
+			double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX];
+			double MinimumTWait = 0.0;
+			double DPTEBandwidth;
+			double DCFCLKRequiredForAverageBandwidth;
+			unsigned int ExtraLatencyBytes;
+			double ExtraLatencyCycles;
+			double DCFCLKRequiredForPeakBandwidth;
+			unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
+			double MinimumTvmPlus2Tr0;
+
+			TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
+						+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k]
+								/ (15.75 * HTotal[k] / PixelClock[k]);
+			}
+
+			for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k)
+				NoOfDPPState[k] = NoOfDPP[i][j][k];
+
+			DPTEBandwidth = TotalMaxPrefetchFlipDPTERowBandwidth[i][j];
+			DCFCLKRequiredForAverageBandwidth = dml_max(ProjectedDCFClkDeepSleep[i][j], DPTEBandwidth / NormalEfficiency / ReturnBusWidth);
+
+			ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes(ReorderingBytes,
+					TotalNumberOfActiveDPP[i][j], PixelChunkSizeInKByte,
+					TotalNumberOfDCCActiveDPP[i][j], MetaChunkSize, GPUVMEnable, HostVMEnable,
+					NumberOfActiveSurfaces, NoOfDPPState, dpte_group_bytes, 1, HostVMMinPageSize,
+					HostVMMaxNonCachedPageTableLevels);
+			ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__
+					+ ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				double DCFCLKCyclesRequiredInPrefetch;
+				double PrefetchTime;
+
+				PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k]
+						* swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
+						+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k]
+								* BytePerPixelC[k]) / NormalEfficiency
+						/ ReturnBusWidth;
+				DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
+						+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency
+								/ NormalEfficiency / ReturnBusWidth
+								* (GPUVMMaxPageTableLevels > 2 ? 1 : 0)
+						+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency
+								/ ReturnBusWidth
+						+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth
+						+ PixelDCFCLKCyclesRequiredInPrefetch[k];
+				PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k])
+						* HTotal[k] / PixelClock[k];
+				DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true &&
+						DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
+						UrgLatency[i] * GPUVMMaxPageTableLevels *
+						(HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
+
+				MinimumTWait = dml32_CalculateTWait(MaxPrefetchMode,
+						UseMALLForPStateChange[k],
+						SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+						DRRDisplay[k],
+						DRAMClockChangeLatencyFinal,
+						FCLKChangeLatency,
+						UrgLatency[i],
+						SREnterPlusExitTime);
+
+				PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] -
+						MinimumTWait - UrgLatency[i] *
+						((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels :
+						GPUVMMaxPageTableLevels - 2) *  (HostVMEnable == true ?
+						HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) -
+						DynamicMetadataVMExtraLatency[k];
+
+				if (PrefetchTime > 0) {
+					double ExpectedVRatioPrefetch;
+
+					ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime *
+							PixelDCFCLKCyclesRequiredInPrefetch[k] /
+							DCFCLKCyclesRequiredInPrefetch);
+					DCFCLKRequiredForPeakBandwidthPerSurface[k] = NoOfDPPState[k] *
+							PixelDCFCLKCyclesRequiredInPrefetch[k] /
+							PrefetchPixelLinesTime[k] *
+							dml_max(1.0, ExpectedVRatioPrefetch) *
+							dml_max(1.0, ExpectedVRatioPrefetch / 4);
+					if (HostVMEnable == true || ImmediateFlipRequirement == true) {
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] =
+								DCFCLKRequiredForPeakBandwidthPerSurface[k] +
+								NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency /
+								NormalEfficiency / ReturnBusWidth;
+					}
+				} else {
+					DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
+				}
+				if (DynamicMetadataEnable[k] == true) {
+					double TSetupPipe;
+					double TdmbfPipe;
+					double TdmsksPipe;
+					double TdmecPipe;
+					double AllowedTimeForUrgentExtraLatency;
+
+					dml32_CalculateVUpdateAndDynamicMetadataParameters(
+							MaxInterDCNTileRepeaters,
+							RequiredDPPCLKPerSurface[i][j][k],
+							RequiredDISPCLK[i][j],
+							ProjectedDCFClkDeepSleep[i][j],
+							PixelClock[k],
+							HTotal[k],
+							VTotal[k] - VActive[k],
+							DynamicMetadataTransmittedBytes[k],
+							DynamicMetadataLinesBeforeActiveRequired[k],
+							Interlace[k],
+							ProgressiveToInterlaceUnitInOPP,
+
+							/* output */
+							&TSetupPipe,
+							&TdmbfPipe,
+							&TdmecPipe,
+							&TdmsksPipe,
+							&dummy1,
+							&dummy2,
+							&dummy3);
+					AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] /
+							PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe -
+							TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
+					if (AllowedTimeForUrgentExtraLatency > 0)
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] =
+								dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k],
+								ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
+					else
+						DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
+				}
+			}
+			DCFCLKRequiredForPeakBandwidth = 0;
+			for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) {
+				DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth +
+						DCFCLKRequiredForPeakBandwidthPerSurface[k];
+			}
+			MinimumTvmPlus2Tr0 = UrgLatency[i] * (GPUVMEnable == true ?
+					(HostVMEnable == true ? (GPUVMMaxPageTableLevels + 2) *
+					(HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 0);
+			for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+				double MaximumTvmPlus2Tr0PlusTsw;
+
+				MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] /
+						PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
+				if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
+					DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
+				} else {
+					DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth,
+							2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw -
+								MinimumTvmPlus2Tr0 -
+								PrefetchPixelLinesTime[k] / 4),
+							(2 * ExtraLatencyCycles +
+								PixelDCFCLKCyclesRequiredInPrefetch[k]) /
+								(MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
+				}
+			}
+			DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 *
+					dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
+		}
+	}
+}
+
+unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels)
+{
+	unsigned int k;
+	double   ret;
+	unsigned int  HostVMDynamicLevels;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048)
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576)
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		else
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+	} else {
+		HostVMDynamicLevels = 0;
+	}
+
+	ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte +
+			TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0;
+
+	if (GPUVMEnable == true) {
+		for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+			ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] *
+					(1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
+		}
+	}
+	return ret;
+}
+
+void dml32_CalculateVUpdateAndDynamicMetadataParameters(
+		unsigned int MaxInterDCNTileRepeaters,
+		double Dppclk,
+		double Dispclk,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		unsigned int HTotal,
+		unsigned int VBlank,
+		unsigned int DynamicMetadataTransmittedBytes,
+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+
+		/* output */
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		unsigned int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	double TotalRepeaterDelayTime;
+
+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / Dppclk + 3 / Dispclk);
+	*VUpdateWidthPix  =
+			dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0);
+	*VReadyOffsetPix  = dml_ceil(dml_max(150.0 / Dppclk,
+			TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0);
+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1.0);
+	*TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
+	*Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk;
+	*Tdmec = HTotal / PixelClock;
+
+	if (DynamicMetadataLinesBeforeActiveRequired == 0)
+		*Tdmsks = VBlank * HTotal / PixelClock / 2.0;
+	else
+		*Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock;
+
+	if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false)
+		*Tdmsks = *Tdmsks / 2;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix);
+	dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix);
+	dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix);
+
+	dml_print("DML::%s: DynamicMetadataLinesBeforeActiveRequired = %d\n",
+			__func__, DynamicMetadataLinesBeforeActiveRequired);
+	dml_print("DML::%s: VBlank = %d\n", __func__, VBlank);
+	dml_print("DML::%s: HTotal = %d\n", __func__, HTotal);
+	dml_print("DML::%s: PixelClock = %f\n", __func__, PixelClock);
+	dml_print("DML::%s: Tdmsks = %f\n", __func__, *Tdmsks);
+#endif
+}
+
+double dml32_CalculateTWait(
+		unsigned int PrefetchMode,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay,
+		double DRAMClockChangeLatency,
+		double FCLKChangeLatency,
+		double UrgentLatency,
+		double SREnterPlusExitTime)
+{
+	double TWait = 0.0;
+
+	if (PrefetchMode == 0 &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_full_frame) &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_sub_viewport) &&
+			!(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe) &&
+			!(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) {
+		TWait = dml_max3(DRAMClockChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
+	} else if (PrefetchMode <= 1 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) {
+		TWait = dml_max3(FCLKChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
+	} else if (PrefetchMode <= 2 && !(UseMALLForPStateChange == dm_use_mall_pstate_change_phantom_pipe)) {
+		TWait = dml_max(SREnterPlusExitTime, UrgentLatency);
+	} else {
+		TWait = UrgentLatency;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: PrefetchMode = %d\n", __func__, PrefetchMode);
+	dml_print("DML::%s: TWait = %f\n", __func__, TWait);
+#endif
+	return TWait;
+} // CalculateTWait
+
+// Function: get_return_bw_mbps
+// Megabyte per second
+double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const bool HostVMEnable,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed)
+{
+	double ReturnBW = 0.;
+	double IdealSDPPortBandwidth    = soc->return_bus_width_bytes /*mode_lib->vba.ReturnBusWidth*/ * DCFCLK;
+	double IdealFabricBandwidth     = FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes;
+	double IdealDRAMBandwidth       = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes;
+	double PixelDataOnlyReturnBW    = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
+			IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
+			IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe  :
+					soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100);
+	double PixelMixedWithVMDataReturnBW = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
+			IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
+			IdealDRAMBandwidth * (VoltageLevel < 2 ? soc->pct_ideal_dram_bw_after_urgent_strobe :
+					soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only) / 100);
+
+	if (HostVMEnable != true)
+		ReturnBW = PixelDataOnlyReturnBW;
+	else
+		ReturnBW = PixelMixedWithVMDataReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel);
+	dml_print("DML::%s: HostVMEnable = %d\n", __func__, HostVMEnable);
+	dml_print("DML::%s: DCFCLK       = %f\n", __func__, DCFCLK);
+	dml_print("DML::%s: FabricClock  = %f\n", __func__, FabricClock);
+	dml_print("DML::%s: DRAMSpeed    = %f\n", __func__, DRAMSpeed);
+	dml_print("DML::%s: IdealSDPPortBandwidth        = %f\n", __func__, IdealSDPPortBandwidth);
+	dml_print("DML::%s: IdealFabricBandwidth         = %f\n", __func__, IdealFabricBandwidth);
+	dml_print("DML::%s: IdealDRAMBandwidth           = %f\n", __func__, IdealDRAMBandwidth);
+	dml_print("DML::%s: PixelDataOnlyReturnBW        = %f\n", __func__, PixelDataOnlyReturnBW);
+	dml_print("DML::%s: PixelMixedWithVMDataReturnBW = %f\n", __func__, PixelMixedWithVMDataReturnBW);
+	dml_print("DML::%s: ReturnBW                     = %f MBps\n", __func__, ReturnBW);
+#endif
+	return ReturnBW;
+}
+
+// Function: get_return_bw_mbps_vm_only
+// Megabyte per second
+double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed)
+{
+	double VMDataOnlyReturnBW = dml_min3(
+			soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0,
+			FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes
+					* soc->pct_ideal_sdp_bw_after_urgent / 100.0,
+			DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes
+					* (VoltageLevel < 2 ?
+							soc->pct_ideal_dram_bw_after_urgent_strobe :
+							soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only) / 100.0);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VoltageLevel = %d\n", __func__, VoltageLevel);
+	dml_print("DML::%s: DCFCLK       = %f\n", __func__, DCFCLK);
+	dml_print("DML::%s: FabricClock  = %f\n", __func__, FabricClock);
+	dml_print("DML::%s: DRAMSpeed    = %f\n", __func__, DRAMSpeed);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+#endif
+	return VMDataOnlyReturnBW;
+}
+
+double dml32_CalculateExtraLatency(
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		double DCFCLK,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels)
+{
+	double ExtraLatencyBytes;
+	double ExtraLatency;
+
+	ExtraLatencyBytes = dml32_CalculateExtraLatencyBytes(
+			ReorderingBytes,
+			TotalNumberOfActiveDPP,
+			PixelChunkSizeInKByte,
+			TotalNumberOfDCCActiveDPP,
+			MetaChunkSize,
+			GPUVMEnable,
+			HostVMEnable,
+			NumberOfActiveSurfaces,
+			NumberOfDPP,
+			dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			HostVMMinPageSize,
+			HostVMMaxNonCachedPageTableLevels);
+
+	ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles);
+	dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);
+	dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes);
+	dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW);
+	dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency);
+#endif
+
+	return ExtraLatency;
+} // CalculateExtraLatency
+
+bool dml32_CalculatePrefetchSchedule(
+		double HostVMInefficiencyFactor,
+		DmlPipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		unsigned int VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		unsigned int VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		unsigned int swath_width_luma_ub,
+		unsigned int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		/* Output */
+		double   *DSTXAfterScaler,
+		double   *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool   *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		unsigned int   *VUpdateOffsetPix,
+		double   *VUpdateWidthPix,
+		double   *VReadyOffsetPix)
+{
+	bool MyError = false;
+	unsigned int DPPCycles, DISPCLKCycles;
+	double DSTTotalPixelsAfterScaler;
+	double LineTime;
+	double dst_y_prefetch_equ;
+	double prefetch_bw_oto;
+	double Tvm_oto;
+	double Tr0_oto;
+	double Tvm_oto_lines;
+	double Tr0_oto_lines;
+	double dst_y_prefetch_oto;
+	double TimeForFetchingMetaPTE = 0;
+	double TimeForFetchingRowInVBlank = 0;
+	double LinesToRequestPrefetchPixelData = 0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double  trip_to_mem;
+	double  Tvm_trips;
+	double  Tr0_trips;
+	double  Tvm_trips_rounded;
+	double  Tr0_trips_rounded;
+	double  Lsw_oto;
+	double  Tpre_rounded;
+	double  prefetch_bw_equ;
+	double  Tvm_equ;
+	double  Tr0_equ;
+	double  Tdmbf;
+	double  Tdmec;
+	double  Tdmsks;
+	double  prefetch_sw_bytes;
+	double  bytes_pp;
+	double  dep_bytes;
+	unsigned int max_vratio_pre = __DML_MAX_VRATIO_PRE__;
+	double  min_Lsw;
+	double  Tsw_est1 = 0;
+	double  Tsw_est3 = 0;
+
+	if (GPUVMEnable == true && HostVMEnable == true)
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	else
+		HostVMDynamicLevelsTrips = 0;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: GPUVMPageTableLevels = %d\n", __func__, GPUVMPageTableLevels);
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, myPipe->DCCEnable);
+	dml_print("DML::%s: HostVMEnable=%d HostVMInefficiencyFactor=%f\n",
+			__func__, HostVMEnable, HostVMInefficiencyFactor);
+#endif
+	dml32_CalculateVUpdateAndDynamicMetadataParameters(
+			MaxInterDCNTileRepeaters,
+			myPipe->Dppclk,
+			myPipe->Dispclk,
+			myPipe->DCFClkDeepSleep,
+			myPipe->PixelClock,
+			myPipe->HTotal,
+			myPipe->VBlank,
+			DynamicMetadataTransmittedBytes,
+			DynamicMetadataLinesBeforeActiveRequired,
+			myPipe->InterlaceEnable,
+			myPipe->ProgressiveToInterlaceUnitInOPP,
+			TSetup,
+
+			/* output */
+			&Tdmbf,
+			&Tdmec,
+			&Tdmsks,
+			VUpdateOffsetPix,
+			VUpdateWidthPix,
+			VReadyOffsetPix);
+
+	LineTime = myPipe->HTotal / myPipe->PixelClock;
+	trip_to_mem = UrgentLatency;
+	Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
+
+	if (DynamicMetadataVMEnabled == true)
+		*Tdmdl = TWait + Tvm_trips + trip_to_mem;
+	else
+		*Tdmdl = TWait + UrgentExtraLatency;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataEnable == false)
+		*Tdmdl = 0.0;
+#endif
+
+	if (DynamicMetadataEnable == true) {
+		if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
+			*NotEnoughTimeForDynamicMetadata = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);
+			dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n",
+					__func__, Tdmbf);
+			dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+			dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n",
+					__func__, Tdmsks);
+			dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n",
+					__func__, *Tdmdl);
+#endif
+		} else {
+			*NotEnoughTimeForDynamicMetadata = false;
+		}
+	} else {
+		*NotEnoughTimeForDynamicMetadata = false;
+	}
+
+	*Tdmdl_vm =  (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true &&
+			GPUVMEnable == true ? TWait + Tvm_trips : 0);
+
+	if (myPipe->ScalerEnabled)
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
+	else
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
+
+	DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
+
+	DISPCLKCycles = DISPCLKDelaySubtotal;
+
+	if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0)
+		return true;
+
+	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->Dppclk + DISPCLKCycles *
+			myPipe->PixelClock / myPipe->Dispclk + DSCDelay;
+
+	*DSTXAfterScaler = *DSTXAfterScaler + (myPipe->ODMMode != dm_odm_combine_mode_disabled ? 18 : 0)
+			+ (myPipe->DPPPerSurface - 1) * DPP_RECOUT_WIDTH
+			+ ((myPipe->ODMMode == dm_odm_split_mode_1to2 || myPipe->ODMMode == dm_odm_mode_mso_1to2) ?
+					myPipe->HActive / 2 : 0)
+			+ ((myPipe->ODMMode == dm_odm_mode_mso_1to4) ? myPipe->HActive * 3 / 4 : 0);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles);
+	dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock);
+	dml_print("DML::%s: Dppclk: %f\n", __func__, myPipe->Dppclk);
+	dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles);
+	dml_print("DML::%s: DISPCLK: %f\n", __func__,  myPipe->Dispclk);
+	dml_print("DML::%s: DSCDelay: %d\n", __func__,  DSCDelay);
+	dml_print("DML::%s: ODMMode: %d\n", __func__,  myPipe->ODMMode);
+	dml_print("DML::%s: DPP_RECOUT_WIDTH: %d\n", __func__, DPP_RECOUT_WIDTH);
+	dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__,  *DSTXAfterScaler);
+#endif
+
+	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
+		*DSTYAfterScaler = 1;
+	else
+		*DSTYAfterScaler = 0;
+
+	DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler;
+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__,  *DSTXAfterScaler);
+	dml_print("DML::%s: DSTYAfterScaler: %d (final)\n", __func__, *DSTYAfterScaler);
+#endif
+
+	MyError = false;
+
+	Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1);
+
+	if (GPUVMEnable == true) {
+		Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1.0) / 4.0 * LineTime;
+		Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime;
+		if (GPUVMPageTableLevels >= 3) {
+			*Tno_bw = UrgentExtraLatency + trip_to_mem *
+					(double) ((GPUVMPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1);
+		} else if (GPUVMPageTableLevels == 1 && myPipe->DCCEnable != true) {
+			Tr0_trips_rounded = dml_ceil(4.0 * UrgentExtraLatency / LineTime, 1.0) /
+					4.0 * LineTime; // VBA_ERROR
+			*Tno_bw = UrgentExtraLatency;
+		} else {
+			*Tno_bw = 0;
+		}
+	} else if (myPipe->DCCEnable == true) {
+		Tvm_trips_rounded = LineTime / 4.0;
+		Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime;
+		*Tno_bw = 0;
+	} else {
+		Tvm_trips_rounded = LineTime / 4.0;
+		Tr0_trips_rounded = LineTime / 2.0;
+		*Tno_bw = 0;
+	}
+	Tvm_trips_rounded = dml_max(Tvm_trips_rounded, LineTime / 4.0);
+	Tr0_trips_rounded = dml_max(Tr0_trips_rounded, LineTime / 4.0);
+
+	if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10
+			|| myPipe->SourcePixelFormat == dm_420_12) {
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4;
+	} else {
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC;
+	}
+
+	prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY
+			+ PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
+	prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerSurface,
+			prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
+
+	min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
+	min_Lsw = dml_max(min_Lsw, 1.0);
+	Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0;
+
+	if (GPUVMEnable == true) {
+		Tvm_oto = dml_max3(
+				Tvm_trips,
+				*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
+				LineTime / 4.0);
+	} else
+		Tvm_oto = LineTime / 4.0;
+
+	if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+		Tr0_oto = dml_max4(
+				Tr0_trips,
+				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
+				(LineTime - Tvm_oto)/2.0,
+				LineTime / 4.0);
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tr0_oto max0 = %f\n", __func__,
+				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto);
+		dml_print("DML::%s: Tr0_oto max1 = %f\n", __func__, Tr0_trips);
+		dml_print("DML::%s: Tr0_oto max2 = %f\n", __func__, LineTime - Tvm_oto);
+		dml_print("DML::%s: Tr0_oto max3 = %f\n", __func__, LineTime / 4);
+#endif
+	} else
+		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
+
+	Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
+	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
+	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;
+
+	dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime -
+			(*DSTYAfterScaler + (double) *DSTXAfterScaler / (double) myPipe->HTotal);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: HTotal = %d\n", __func__, myPipe->HTotal);
+	dml_print("DML::%s: min_Lsw = %f\n", __func__, min_Lsw);
+	dml_print("DML::%s: *Tno_bw = %f\n", __func__, *Tno_bw);
+	dml_print("DML::%s: UrgentExtraLatency = %f\n", __func__, UrgentExtraLatency);
+	dml_print("DML::%s: trip_to_mem = %f\n", __func__, trip_to_mem);
+	dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+	dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+	dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+	dml_print("DML::%s: BytePerPixelC = %d\n", __func__, myPipe->BytePerPixelC);
+	dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+	dml_print("DML::%s: swath_width_chroma_ub = %d\n", __func__, swath_width_chroma_ub);
+	dml_print("DML::%s: prefetch_sw_bytes = %f\n", __func__, prefetch_sw_bytes);
+	dml_print("DML::%s: bytes_pp = %f\n", __func__, bytes_pp);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+	dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+	dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+	dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips);
+	dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips);
+	dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto);
+	dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto);
+	dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto);
+	dml_print("DML::%s: Tvm_oto_lines = %f\n", __func__, Tvm_oto_lines);
+	dml_print("DML::%s: Tr0_oto_lines = %f\n", __func__, Tr0_oto_lines);
+	dml_print("DML::%s: Lsw_oto = %f\n", __func__, Lsw_oto);
+	dml_print("DML::%s: dst_y_prefetch_oto = %f\n", __func__, dst_y_prefetch_oto);
+	dml_print("DML::%s: dst_y_prefetch_equ = %f\n", __func__, dst_y_prefetch_equ);
+#endif
+
+	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
+	Tpre_rounded = dst_y_prefetch_equ * LineTime;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ);
+	dml_print("DML::%s: LineTime: %f\n", __func__, LineTime);
+	dml_print("DML::%s: VStartup: %d\n", __func__, VStartup);
+	dml_print("DML::%s: Tvstartup: %fus - time between vstartup and first pixel of active\n",
+			__func__, VStartup * LineTime);
+	dml_print("DML::%s: TSetup: %fus - time from vstartup to vready\n", __func__, *TSetup);
+	dml_print("DML::%s: TCalc: %fus - time for calculations in dchub starting at vready\n", __func__, TCalc);
+	dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf);
+	dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+	dml_print("DML::%s: Tdmdl_vm: %fus - time for vm stages of dmd\n", __func__, *Tdmdl_vm);
+	dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd\n", __func__, *Tdmdl);
+	dml_print("DML::%s: DSTYAfterScaler: %d lines - number of lines of pipeline and buffer delay after scaler\n",
+			__func__, *DSTYAfterScaler);
+#endif
+	dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor,
+			MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
+
+	if (prefetch_sw_bytes < dep_bytes)
+		prefetch_sw_bytes = 2 * dep_bytes;
+
+	*PrefetchBandwidth = 0;
+	*DestinationLinesToRequestVMInVBlank = 0;
+	*DestinationLinesToRequestRowInVBlank = 0;
+	*VRatioPrefetchY = 0;
+	*VRatioPrefetchC = 0;
+	*RequiredPrefetchPixDataBWLuma = 0;
+	if (dst_y_prefetch_equ > 1) {
+		double PrefetchBandwidth1;
+		double PrefetchBandwidth2;
+		double PrefetchBandwidth3;
+		double PrefetchBandwidth4;
+
+		if (Tpre_rounded - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
+					+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw);
+			Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1;
+		} else
+			PrefetchBandwidth1 = 0;
+
+		if (VStartup == MaxVStartup && (Tsw_est1 / LineTime < min_Lsw)
+				&& Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
+					+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw);
+		}
+
+		if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) /
+			(Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth2 = 0;
+
+		if (Tpre_rounded - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded);
+			Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3;
+		} else
+			PrefetchBandwidth3 = 0;
+
+
+		if (VStartup == MaxVStartup &&
+				(Tsw_est3 / LineTime < min_Lsw) && Tpre_rounded - min_Lsw * LineTime - 0.75 *
+				LineTime - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded);
+		}
+
+		if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0) {
+			PrefetchBandwidth4 = prefetch_sw_bytes /
+					(Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
+		} else {
+			PrefetchBandwidth4 = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded);
+		dml_print("DML::%s: Tno_bw: %f\n", __func__, *Tno_bw);
+		dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded);
+		dml_print("DML::%s: Tsw_est1: %f\n", __func__, Tsw_est1);
+		dml_print("DML::%s: Tsw_est3: %f\n", __func__, Tsw_est3);
+		dml_print("DML::%s: PrefetchBandwidth1: %f\n", __func__, PrefetchBandwidth1);
+		dml_print("DML::%s: PrefetchBandwidth2: %f\n", __func__, PrefetchBandwidth2);
+		dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3);
+		dml_print("DML::%s: PrefetchBandwidth4: %f\n", __func__, PrefetchBandwidth4);
+#endif
+		{
+			bool Case1OK;
+			bool Case2OK;
+			bool Case3OK;
+
+			if (PrefetchBandwidth1 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
+						>= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+								/ PrefetchBandwidth1 >= Tr0_trips_rounded) {
+					Case1OK = true;
+				} else {
+					Case1OK = false;
+				}
+			} else {
+				Case1OK = false;
+			}
+
+			if (PrefetchBandwidth2 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
+						>= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+						/ PrefetchBandwidth2 < Tr0_trips_rounded) {
+					Case2OK = true;
+				} else {
+					Case2OK = false;
+				}
+			} else {
+				Case2OK = false;
+			}
+
+			if (PrefetchBandwidth3 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 <
+						Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow *
+								HostVMInefficiencyFactor) / PrefetchBandwidth3 >=
+								Tr0_trips_rounded) {
+					Case3OK = true;
+				} else {
+					Case3OK = false;
+				}
+			} else {
+				Case3OK = false;
+			}
+
+			if (Case1OK)
+				prefetch_bw_equ = PrefetchBandwidth1;
+			else if (Case2OK)
+				prefetch_bw_equ = PrefetchBandwidth2;
+			else if (Case3OK)
+				prefetch_bw_equ = PrefetchBandwidth3;
+			else
+				prefetch_bw_equ = PrefetchBandwidth4;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK);
+			dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK);
+			dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK);
+			dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ);
+#endif
+
+			if (prefetch_bw_equ > 0) {
+				if (GPUVMEnable == true) {
+					Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame *
+							HostVMInefficiencyFactor / prefetch_bw_equ,
+							Tvm_trips, LineTime / 4);
+				} else {
+					Tvm_equ = LineTime / 4;
+				}
+
+				if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+					Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow *
+							HostVMInefficiencyFactor) / prefetch_bw_equ, Tr0_trips,
+							(LineTime - Tvm_equ) / 2, LineTime / 4);
+				} else {
+					Tr0_equ = (LineTime - Tvm_equ) / 2;
+				}
+			} else {
+				Tvm_equ = 0;
+				Tr0_equ = 0;
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__);
+#endif
+			}
+		}
+
+		if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
+			*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			TimeForFetchingMetaPTE = Tvm_oto;
+			TimeForFetchingRowInVBlank = Tr0_oto;
+			*PrefetchBandwidth = prefetch_bw_oto;
+		} else {
+			*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+			TimeForFetchingMetaPTE = Tvm_equ;
+			TimeForFetchingRowInVBlank = Tr0_equ;
+			*PrefetchBandwidth = prefetch_bw_equ;
+		}
+
+		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
+
+		*DestinationLinesToRequestRowInVBlank =
+				dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
+
+		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch -
+				*DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch);
+		dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n",
+				__func__, *DestinationLinesToRequestVMInVBlank);
+		dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank);
+		dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+		dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n",
+				__func__, *DestinationLinesToRequestRowInVBlank);
+		dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+		dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData);
+#endif
+
+		if (LinesToRequestPrefetchPixelData >= 1 && prefetch_bw_equ > 0) {
+			*VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+			dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY);
+			dml_print("DML::%s: VInitPreFillY = %d\n", __func__, VInitPreFillY);
+#endif
+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
+					*VRatioPrefetchY =
+							dml_max((double) PrefetchSourceLinesY /
+									LinesToRequestPrefetchPixelData,
+									(double) MaxNumSwathY * SwathHeightY /
+									(LinesToRequestPrefetchPixelData -
+									(VInitPreFillY - 3.0) / 2.0));
+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+				} else {
+					MyError = true;
+					*VRatioPrefetchY = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+				dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+				dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY);
+#endif
+			}
+
+			*VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+			dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC);
+			dml_print("DML::%s: VInitPreFillC = %d\n", __func__, VInitPreFillC);
+#endif
+			if ((SwathHeightC > 4)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
+					*VRatioPrefetchC =
+						dml_max(*VRatioPrefetchC,
+							(double) MaxNumSwathC * SwathHeightC /
+							(LinesToRequestPrefetchPixelData -
+							(VInitPreFillC - 3.0) / 2.0));
+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+				} else {
+					MyError = true;
+					*VRatioPrefetchC = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+				dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+				dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC);
+#endif
+			}
+
+			*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY
+					/ LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub
+					/ LineTime;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+			dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+			dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n",
+					__func__, *RequiredPrefetchPixDataBWLuma);
+#endif
+			*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC /
+					LinesToRequestPrefetchPixelData
+					* myPipe->BytePerPixelC
+					* swath_width_chroma_ub / LineTime;
+		} else {
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML:%s: MyErr set. LinesToRequestPrefetchPixelData: %f, should be > 0\n",
+					__func__, LinesToRequestPrefetchPixelData);
+#endif
+			*VRatioPrefetchY = 0;
+			*VRatioPrefetchC = 0;
+			*RequiredPrefetchPixDataBWLuma = 0;
+			*RequiredPrefetchPixDataBWChroma = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n",
+			(double)LinesToRequestPrefetchPixelData * LineTime +
+			2.0*TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE);
+		dml_print("DML:  Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE);
+		dml_print("DML: To: %fus - time for propagation from scaler to optc\n",
+			(*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime);
+		dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n");
+		dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime -
+			TimeForFetchingMetaPTE - 2*TimeForFetchingRowInVBlank - (*DSTYAfterScaler +
+			((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup);
+		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n",
+				PixelPTEBytesPerRow);
+#endif
+	} else {
+		MyError = true;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MyErr set, dst_y_prefetch_equ = %f (should be > 1)\n",
+				__func__, dst_y_prefetch_equ);
+#endif
+	}
+
+	{
+		double prefetch_vm_bw;
+		double prefetch_row_bw;
+
+		if (PDEAndMetaPTEBytesFrame == 0) {
+			prefetch_vm_bw = 0;
+		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+			dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+			dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n",
+					__func__, *DestinationLinesToRequestVMInVBlank);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor /
+					(*DestinationLinesToRequestVMInVBlank * LineTime);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw);
+#endif
+		} else {
+			prefetch_vm_bw = 0;
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MyErr set. DestinationLinesToRequestVMInVBlank=%f (should be > 0)\n",
+					__func__, *DestinationLinesToRequestVMInVBlank);
+#endif
+		}
+
+		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
+			prefetch_row_bw = 0;
+		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
+			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInVBlank * LineTime);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+			dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+			dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n",
+					__func__, *DestinationLinesToRequestRowInVBlank);
+			dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw);
+#endif
+		} else {
+			prefetch_row_bw = 0;
+			MyError = true;
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MyErr set. DestinationLinesToRequestRowInVBlank=%f (should be > 0)\n",
+					__func__, *DestinationLinesToRequestRowInVBlank);
+#endif
+		}
+
+		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
+	}
+
+	if (MyError) {
+		*PrefetchBandwidth = 0;
+		TimeForFetchingMetaPTE = 0;
+		TimeForFetchingRowInVBlank = 0;
+		*DestinationLinesToRequestVMInVBlank = 0;
+		*DestinationLinesToRequestRowInVBlank = 0;
+		*DestinationLinesForPrefetch = 0;
+		LinesToRequestPrefetchPixelData = 0;
+		*VRatioPrefetchY = 0;
+		*VRatioPrefetchC = 0;
+		*RequiredPrefetchPixDataBWLuma = 0;
+		*RequiredPrefetchPixDataBWChroma = 0;
+	}
+
+	return MyError;
+} // CalculatePrefetchSchedule
+
+void dml32_CalculateFlipSchedule(
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		bool    use_one_row_for_frame_flip,
+
+		/* Output */
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe)
+{
+	double min_row_time = 0.0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double TimeForFetchingMetaPTEImmediateFlip;
+	double TimeForFetchingRowInVBlankImmediateFlip;
+	double ImmediateFlipBW;
+
+	if (GPUVMEnable == true && HostVMEnable == true)
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	else
+		HostVMDynamicLevelsTrips = 0;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotImmediateFlipBytes = %d\n", __func__, TotImmediateFlipBytes);
+	dml_print("DML::%s: BandwidthAvailableForImmediateFlip = %f\n", __func__, BandwidthAvailableForImmediateFlip);
+#endif
+
+	if (TotImmediateFlipBytes > 0) {
+		if (use_one_row_for_frame_flip) {
+			ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + 2 * DPTEBytesPerRow) *
+					BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+		} else {
+			ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) *
+					BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+		}
+		if (GPUVMEnable == true) {
+			TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame *
+					HostVMInefficiencyFactor / ImmediateFlipBW,
+					UrgentExtraLatency + UrgentLatency *
+					(GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
+					LineTime / 4.0);
+		} else {
+			TimeForFetchingMetaPTEImmediateFlip = 0;
+		}
+		if ((GPUVMEnable == true || DCCEnable == true)) {
+			TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
+					(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
+					UrgentLatency * (HostVMDynamicLevelsTrips + 1), LineTime / 4.0);
+		} else {
+			TimeForFetchingRowInVBlankImmediateFlip = 0;
+		}
+
+		*DestinationLinesToRequestVMInImmediateFlip =
+				dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1.0) / 4.0;
+		*DestinationLinesToRequestRowInImmediateFlip =
+				dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1.0) / 4.0;
+
+		if (GPUVMEnable == true) {
+			*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor /
+					(*DestinationLinesToRequestVMInImmediateFlip * LineTime),
+					(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInImmediateFlip * LineTime));
+		} else if ((GPUVMEnable == true || DCCEnable == true)) {
+			*final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) /
+					(*DestinationLinesToRequestRowInImmediateFlip * LineTime);
+		} else {
+			*final_flip_bw = 0;
+		}
+	} else {
+		TimeForFetchingMetaPTEImmediateFlip = 0;
+		TimeForFetchingRowInVBlankImmediateFlip = 0;
+		*DestinationLinesToRequestVMInImmediateFlip = 0;
+		*DestinationLinesToRequestRowInImmediateFlip = 0;
+		*final_flip_bw = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dml_min(dpte_row_height *
+					LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = dml_min(meta_row_height *
+					LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
+		} else {
+			min_row_time = dml_min4(dpte_row_height * LineTime / VRatio, meta_row_height *
+					LineTime / VRatio, dpte_row_height_chroma * LineTime /
+					VRatioChroma, meta_row_height_chroma * LineTime / VRatioChroma);
+		}
+	} else {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dpte_row_height * LineTime / VRatio;
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = meta_row_height * LineTime / VRatio;
+		} else {
+			min_row_time =
+				dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
+		}
+	}
+
+	if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16
+			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip
+					> min_row_time) {
+		*ImmediateFlipSupportedForPipe = false;
+	} else {
+		*ImmediateFlipSupportedForPipe = true;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+	dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable);
+	dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n",
+			__func__, *DestinationLinesToRequestVMInImmediateFlip);
+	dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n",
+			__func__, *DestinationLinesToRequestRowInImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n",
+			__func__, TimeForFetchingRowInVBlankImmediateFlip);
+	dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time);
+	dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe);
+#endif
+} // CalculateFlipSchedule
+
+void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+		bool USRRetrainingRequiredFinal,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizeTimingsFinal,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay[],
+		unsigned int dpte_group_bytes[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		SOCParametersList mmSOCParameters,
+		unsigned int WritebackChunkSize,
+		double SOCCLK,
+		double DCFClkDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int VTaps[],
+		unsigned int VTapsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerSurface[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		unsigned int CompressedBufferSizeInkByte,
+
+		/* Output */
+		Watermarks *Watermark,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double MaxActiveDRAMClockChangeLatencySupported[],
+		unsigned int SubViewportLinesNeededInMALL[],
+		enum dm_fclock_change_support *FCLKChangeSupport,
+		double *MinActiveFCLKChangeLatencySupported,
+		bool *USRRetrainingSupport,
+		double ActiveDRAMClockChangeLatencyMargin[])
+{
+	unsigned int i, j, k;
+	unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0;
+	unsigned int DRAMClockChangeSupportNumber = 0;
+	unsigned int LastSurfaceWithoutMargin;
+	unsigned int DRAMClockChangeMethod = 0;
+	bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;
+	double MinActiveFCLKChangeMargin = 0.;
+	double SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = 0.;
+	double ActiveClockChangeLatencyHidingY;
+	double ActiveClockChangeLatencyHidingC;
+	double ActiveClockChangeLatencyHiding;
+    double EffectiveDETBufferSizeY;
+	double     ActiveFCLKChangeLatencyMargin[DC__NUM_DPP__MAX];
+	double     USRRetrainingLatencyMargin[DC__NUM_DPP__MAX];
+	double TotalPixelBW = 0.0;
+	bool    SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX];
+	double     EffectiveLBLatencyHidingY;
+	double     EffectiveLBLatencyHidingC;
+	double     LinesInDETY[DC__NUM_DPP__MAX];
+	double     LinesInDETC[DC__NUM_DPP__MAX];
+	unsigned int    LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
+	unsigned int    LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
+	double     FullDETBufferingTimeY;
+	double     FullDETBufferingTimeC;
+	double     WritebackDRAMClockChangeLatencyMargin;
+	double     WritebackFCLKChangeLatencyMargin;
+	double     WritebackLatencyHiding;
+	bool    SameTimingForFCLKChange;
+
+	unsigned int    TotalActiveWriteback = 0;
+	unsigned int LBLatencyHidingSourceLinesY[DC__NUM_DPP__MAX];
+	unsigned int LBLatencyHidingSourceLinesC[DC__NUM_DPP__MAX];
+
+	Watermark->UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency;
+	Watermark->USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency
+			+ mmSOCParameters.USRRetrainingLatency + mmSOCParameters.SMNLatency;
+	Watermark->DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + Watermark->UrgentWatermark;
+	Watermark->FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + Watermark->UrgentWatermark;
+	Watermark->StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency
+			+ 10 / DCFClkDeepSleep;
+	Watermark->Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time
+			+ mmSOCParameters.ExtraLatency + 10 / DCFClkDeepSleep;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UrgentLatency = %f\n", __func__, mmSOCParameters.UrgentLatency);
+	dml_print("DML::%s: ExtraLatency = %f\n", __func__, mmSOCParameters.ExtraLatency);
+	dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, mmSOCParameters.DRAMClockChangeLatency);
+	dml_print("DML::%s: UrgentWatermark = %f\n", __func__, Watermark->UrgentWatermark);
+	dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, Watermark->USRRetrainingWatermark);
+	dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, Watermark->DRAMClockChangeWatermark);
+	dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, Watermark->FCLKChangeWatermark);
+	dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, Watermark->StutterExitWatermark);
+	dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, Watermark->StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, Watermark->Z8StutterExitWatermark);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n",
+			__func__, Watermark->Z8StutterEnterPlusExitWatermark);
+#endif
+
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (WritebackEnable[k] == true)
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+	}
+
+	if (TotalActiveWriteback <= 1) {
+		Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency;
+	} else {
+		Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency
+				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackUrgentWatermark = Watermark->WritebackUrgentWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+	if (TotalActiveWriteback <= 1) {
+		Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
+				+ mmSOCParameters.WritebackLatency;
+		Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
+				+ mmSOCParameters.WritebackLatency;
+	} else {
+		Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
+				+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+		Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
+				+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024 / 32 / SOCCLK;
+	}
+
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackDRAMClockChangeWatermark = Watermark->WritebackDRAMClockChangeWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+	if (USRRetrainingRequiredFinal)
+		Watermark->WritebackFCLKChangeWatermark = Watermark->WritebackFCLKChangeWatermark
+				+ mmSOCParameters.USRRetrainingLatency;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: WritebackDRAMClockChangeWatermark = %f\n",
+			__func__, Watermark->WritebackDRAMClockChangeWatermark);
+	dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, Watermark->WritebackFCLKChangeWatermark);
+	dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, Watermark->WritebackUrgentWatermark);
+	dml_print("DML::%s: USRRetrainingRequiredFinal = %d\n", __func__, USRRetrainingRequiredFinal);
+	dml_print("DML::%s: USRRetrainingLatency = %f\n", __func__, mmSOCParameters.USRRetrainingLatency);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] +
+				SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) / (HTotal[k] / PixelClock[k]);
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+		LBLatencyHidingSourceLinesY[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (VTaps[k] - 1);
+		LBLatencyHidingSourceLinesC[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTapsChroma[k] - 1);
+
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MaxLineBufferLines = %d\n", __func__, k, MaxLineBufferLines);
+		dml_print("DML::%s: k=%d, LineBufferSize     = %d\n", __func__, k, LineBufferSize);
+		dml_print("DML::%s: k=%d, LBBitPerPixel      = %d\n", __func__, k, LBBitPerPixel[k]);
+		dml_print("DML::%s: k=%d, HRatio             = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d, VTaps              = %d\n", __func__, k, VTaps[k]);
+#endif
+
+		EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / VRatio[k] * (HTotal[k] / PixelClock[k]);
+		EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
+		EffectiveDETBufferSizeY = DETBufferSizeY[k];
+
+		if (UnboundedRequestEnabled) {
+			EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
+					+ CompressedBufferSizeInkByte * 1024
+							* (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k])
+							/ (HTotal[k] / PixelClock[k]) / TotalPixelBW;
+		}
+
+		LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
+		FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
+
+		ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
+				- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k];
+
+		if (NumberOfActiveSurfaces > 1) {
+			ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY
+					- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightY[k] * HTotal[k]
+							/ PixelClock[k] / VRatio[k];
+		}
+
+		if (BytePerPixelDETC[k] > 0) {
+			LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
+			LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]);
+			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k])
+					/ VRatioChroma[k];
+			ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
+					- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k]
+							/ PixelClock[k];
+			if (NumberOfActiveSurfaces > 1) {
+				ActiveClockChangeLatencyHidingC = ActiveClockChangeLatencyHidingC
+						- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightC[k] * HTotal[k]
+								/ PixelClock[k] / VRatioChroma[k];
+			}
+			ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY,
+					ActiveClockChangeLatencyHidingC);
+		} else {
+			ActiveClockChangeLatencyHiding = ActiveClockChangeLatencyHidingY;
+		}
+
+		ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
+				- Watermark->DRAMClockChangeWatermark;
+		ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
+				- Watermark->FCLKChangeWatermark;
+		USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->USRRetrainingWatermark;
+
+		if (WritebackEnable[k]) {
+			WritebackLatencyHiding = WritebackInterfaceBufferSize * 1024
+					/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k]
+							/ (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
+			if (WritebackPixelFormat[k] == dm_444_64)
+				WritebackLatencyHiding = WritebackLatencyHiding / 2;
+
+			WritebackDRAMClockChangeLatencyMargin = WritebackLatencyHiding
+					- Watermark->WritebackDRAMClockChangeWatermark;
+
+			WritebackFCLKChangeLatencyMargin = WritebackLatencyHiding
+					- Watermark->WritebackFCLKChangeWatermark;
+
+			ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
+					WritebackFCLKChangeLatencyMargin);
+			ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k],
+					WritebackDRAMClockChangeLatencyMargin);
+		}
+		MaxActiveDRAMClockChangeLatencySupported[k] =
+				(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
+						0 :
+						(ActiveDRAMClockChangeLatencyMargin[k]
+								+ mmSOCParameters.DRAMClockChangeLatency);
+	}
+
+	for (i = 0; i < NumberOfActiveSurfaces; ++i) {
+		for (j = 0; j < NumberOfActiveSurfaces; ++j) {
+			if (i == j ||
+					(BlendingAndTiming[i] == i && BlendingAndTiming[j] == i) ||
+					(BlendingAndTiming[j] == j && BlendingAndTiming[i] == j) ||
+					(BlendingAndTiming[i] == BlendingAndTiming[j] && BlendingAndTiming[i] != i) ||
+					(SynchronizeTimingsFinal && PixelClock[i] == PixelClock[j] &&
+					HTotal[i] == HTotal[j] && VTotal[i] == VTotal[j] &&
+					VActive[i] == VActive[j]) || (SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
+					(DRRDisplay[i] || DRRDisplay[j]))) {
+				SynchronizedSurfaces[i][j] = true;
+			} else {
+				SynchronizedSurfaces[i][j] = false;
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+				(!FoundFirstSurfaceWithMinActiveFCLKChangeMargin ||
+				ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) {
+			FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true;
+			MinActiveFCLKChangeMargin = ActiveFCLKChangeLatencyMargin[k];
+			SurfaceWithMinActiveFCLKChangeMargin = k;
+		}
+	}
+
+	*MinActiveFCLKChangeLatencySupported = MinActiveFCLKChangeMargin + mmSOCParameters.FCLKChangeLatency;
+
+	SameTimingForFCLKChange = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) {
+			if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+					(SameTimingForFCLKChange ||
+					ActiveFCLKChangeLatencyMargin[k] <
+					SecondMinActiveFCLKChangeMarginOneDisplayInVBLank)) {
+				SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = ActiveFCLKChangeLatencyMargin[k];
+			}
+			SameTimingForFCLKChange = false;
+		}
+	}
+
+	if (MinActiveFCLKChangeMargin > 0) {
+		*FCLKChangeSupport = dm_fclock_change_vactive;
+	} else if ((SameTimingForFCLKChange || SecondMinActiveFCLKChangeMarginOneDisplayInVBLank > 0) &&
+			(PrefetchMode <= 1)) {
+		*FCLKChangeSupport = dm_fclock_change_vblank;
+	} else {
+		*FCLKChangeSupport = dm_fclock_change_unsupported;
+	}
+
+	*USRRetrainingSupport = true;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
+				(USRRetrainingLatencyMargin[k] < 0)) {
+			*USRRetrainingSupport = false;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
+				UseMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
+				UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
+				ActiveDRAMClockChangeLatencyMargin[k] < 0) {
+			if (PrefetchMode > 0) {
+				DRAMClockChangeSupportNumber = 2;
+			} else if (DRAMClockChangeSupportNumber == 0) {
+				DRAMClockChangeSupportNumber = 1;
+				LastSurfaceWithoutMargin = k;
+			} else if (DRAMClockChangeSupportNumber == 1 &&
+					!SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) {
+				DRAMClockChangeSupportNumber = 2;
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
+			DRAMClockChangeMethod = 1;
+		else if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
+			DRAMClockChangeMethod = 2;
+	}
+
+	if (DRAMClockChangeMethod == 0) {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	} else if (DRAMClockChangeMethod == 1) {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_full_frame;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_full_frame;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	} else {
+		if (DRAMClockChangeSupportNumber == 0)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vactive_w_mall_sub_vp;
+		else if (DRAMClockChangeSupportNumber == 1)
+			*DRAMClockChangeSupport = dm_dram_clock_change_vblank_w_mall_sub_vp;
+		else
+			*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		unsigned int dst_y_pstate;
+		unsigned int src_y_pstate_l;
+		unsigned int src_y_pstate_c;
+		unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c;
+
+		dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (HTotal[k] / PixelClock[k]), 1);
+		src_y_pstate_l = dml_ceil(dst_y_pstate * VRatio[k], SwathHeightY[k]);
+		src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k];
+		sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + meta_row_height[k];
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: k=%d, DETBufferSizeY               = %d\n", __func__, k, DETBufferSizeY[k]);
+dml_print("DML::%s: k=%d, BytePerPixelDETY             = %f\n", __func__, k, BytePerPixelDETY[k]);
+dml_print("DML::%s: k=%d, SwathWidthY                  = %d\n", __func__, k, SwathWidthY[k]);
+dml_print("DML::%s: k=%d, SwathHeightY                 = %d\n", __func__, k, SwathHeightY[k]);
+dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY  = %d\n", __func__, k, LBLatencyHidingSourceLinesY[k]);
+dml_print("DML::%s: k=%d, dst_y_pstate      = %d\n", __func__, k, dst_y_pstate);
+dml_print("DML::%s: k=%d, src_y_pstate_l    = %d\n", __func__, k, src_y_pstate_l);
+dml_print("DML::%s: k=%d, src_y_ahead_l     = %d\n", __func__, k, src_y_ahead_l);
+dml_print("DML::%s: k=%d, meta_row_height   = %d\n", __func__, k, meta_row_height[k]);
+dml_print("DML::%s: k=%d, sub_vp_lines_l    = %d\n", __func__, k, sub_vp_lines_l);
+#endif
+		SubViewportLinesNeededInMALL[k] = sub_vp_lines_l;
+
+		if (BytePerPixelDETC[k] > 0) {
+			src_y_pstate_c = dml_ceil(dst_y_pstate * VRatioChroma[k], SwathHeightC[k]);
+			src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k];
+			sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + meta_row_height_chroma[k];
+			SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: k=%d, src_y_pstate_c            = %d\n", __func__, k, src_y_pstate_c);
+dml_print("DML::%s: k=%d, src_y_ahead_c             = %d\n", __func__, k, src_y_ahead_c);
+dml_print("DML::%s: k=%d, meta_row_height_chroma    = %d\n", __func__, k, meta_row_height_chroma[k]);
+dml_print("DML::%s: k=%d, sub_vp_lines_c            = %d\n", __func__, k, sub_vp_lines_c);
+#endif
+		}
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DRAMClockChangeSupport = %d\n", __func__, *DRAMClockChangeSupport);
+	dml_print("DML::%s: FCLKChangeSupport = %d\n", __func__, *FCLKChangeSupport);
+	dml_print("DML::%s: MinActiveFCLKChangeLatencySupported = %f\n",
+			__func__, *MinActiveFCLKChangeLatencySupported);
+	dml_print("DML::%s: USRRetrainingSupport = %d\n", __func__, *USRRetrainingSupport);
+#endif
+} // CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport
+
+double dml32_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		unsigned int   WritebackSourceWidth,
+		unsigned int   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize,
+		double DISPCLKDPPCLKVCOSpeed)
+{
+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
+
+	DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
+	DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
+	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth *
+			WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
+	return dml32_RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed);
+}
+
+void dml32_CalculateMinAndMaxPrefetchMode(
+		enum dm_prefetch_modes   AllowForPStateChangeOrStutterInVBlankFinal,
+		unsigned int             *MinPrefetchMode,
+		unsigned int             *MaxPrefetchMode)
+{
+	if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_none) {
+		*MinPrefetchMode = 3;
+		*MaxPrefetchMode = 3;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_stutter) {
+		*MinPrefetchMode = 2;
+		*MaxPrefetchMode = 2;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_fclk_and_stutter) {
+		*MinPrefetchMode = 1;
+		*MaxPrefetchMode = 1;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal == dm_prefetch_support_uclk_fclk_and_stutter) {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 0;
+	} else if (AllowForPStateChangeOrStutterInVBlankFinal ==
+			dm_prefetch_support_uclk_fclk_and_stutter_if_possible) {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 3;
+	} else {
+		*MinPrefetchMode = 0;
+		*MaxPrefetchMode = 3;
+	}
+} // CalculateMinAndMaxPrefetchMode
+
+void dml32_CalculatePixelDeliveryTimes(
+		unsigned int             NumberOfActiveSurfaces,
+		double              VRatio[],
+		double              VRatioChroma[],
+		double              VRatioPrefetchY[],
+		double              VRatioPrefetchC[],
+		unsigned int             swath_width_luma_ub[],
+		unsigned int             swath_width_chroma_ub[],
+		unsigned int             DPPPerSurface[],
+		double              HRatio[],
+		double              HRatioChroma[],
+		double              PixelClock[],
+		double              PSCL_THROUGHPUT[],
+		double              PSCL_THROUGHPUT_CHROMA[],
+		double              Dppclk[],
+		unsigned int             BytePerPixelC[],
+		enum dm_rotation_angle   SourceRotation[],
+		unsigned int             NumberOfCursors[],
+		unsigned int             CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int             CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int             BlockWidth256BytesY[],
+		unsigned int             BlockHeight256BytesY[],
+		unsigned int             BlockWidth256BytesC[],
+		unsigned int             BlockHeight256BytesC[],
+
+		/* Output */
+		double              DisplayPipeLineDeliveryTimeLuma[],
+		double              DisplayPipeLineDeliveryTimeChroma[],
+		double              DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeLuma[],
+		double              DisplayPipeRequestDeliveryTimeChroma[],
+		double              DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double              CursorRequestDeliveryTime[],
+		double              CursorRequestDeliveryTimePrefetch[])
+{
+	double   req_per_swath_ub;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
+		dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
+		dml_print("DML::%s: k=%d : swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
+		dml_print("DML::%s: k=%d : swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
+		dml_print("DML::%s: k=%d : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
+		dml_print("DML::%s: k=%d : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
+		dml_print("DML::%s: k=%d : DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
+		dml_print("DML::%s: k=%d : PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%d : Dppclk = %f\n", __func__, k, Dppclk[k]);
+#endif
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma[k] =
+					swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma[k] = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma[k] =
+					swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma[k] =
+					swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
+			}
+		}
+
+		if (VRatioPrefetchY[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
+					swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
+					swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (VRatioPrefetchC[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] *
+						DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
+						swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
+			}
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n",
+				__func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (!IsVertical(SourceRotation[k]))
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
+		else
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
+#endif
+
+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
+				DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (!IsVertical(SourceRotation[k]))
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
+			else
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
+#endif
+			DisplayPipeRequestDeliveryTimeChroma[k] =
+					DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
+					DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n",
+				__func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		unsigned int cursor_req_per_width;
+
+		cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] /
+				256.0 / 8.0, 1.0);
+		if (NumberOfCursors[k] > 0) {
+			if (VRatio[k] <= 1) {
+				CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
+						HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
+						PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
+			}
+			if (VRatioPrefetchY[k] <= 1) {
+				CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
+						HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
+						PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
+			}
+		} else {
+			CursorRequestDeliveryTime[k] = 0;
+			CursorRequestDeliveryTimePrefetch[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : NumberOfCursors = %d\n",
+				__func__, k, NumberOfCursors[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n",
+				__func__, k, CursorRequestDeliveryTime[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n",
+				__func__, k, CursorRequestDeliveryTimePrefetch[k]);
+#endif
+	}
+} // CalculatePixelDeliveryTimes
+
+void dml32_CalculateMetaAndPTETimes(
+		bool use_one_row_for_frame[],
+		unsigned int NumberOfActiveSurfaces,
+		bool GPUVMEnable,
+		unsigned int MetaChunkSize,
+		unsigned int MinMetaChunkSizeBytes,
+		unsigned int    HTotal[],
+		double  VRatio[],
+		double  VRatioChroma[],
+		double  DestinationLinesToRequestRowInVBlank[],
+		double  DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double  PixelClock[],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int dpte_row_height[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int dpte_group_bytes[],
+		unsigned int    PTERequestSizeY[],
+		unsigned int    PTERequestSizeC[],
+		unsigned int    PixelPTEReqWidthY[],
+		unsigned int    PixelPTEReqHeightY[],
+		unsigned int    PixelPTEReqWidthC[],
+		unsigned int    PixelPTEReqHeightC[],
+		unsigned int    dpte_row_width_luma_ub[],
+		unsigned int    dpte_row_width_chroma_ub[],
+
+		/* Output */
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[])
+{
+	unsigned int   meta_chunk_width;
+	unsigned int   min_meta_chunk_width;
+	unsigned int   meta_chunk_per_row_int;
+	unsigned int   meta_row_remainder;
+	unsigned int   meta_chunk_threshold;
+	unsigned int   meta_chunks_per_row_ub;
+	unsigned int   meta_chunk_width_chroma;
+	unsigned int   min_meta_chunk_width_chroma;
+	unsigned int   meta_chunk_per_row_int_chroma;
+	unsigned int   meta_row_remainder_chroma;
+	unsigned int   meta_chunk_threshold_chroma;
+	unsigned int   meta_chunks_per_row_ub_chroma;
+	unsigned int   dpte_group_width_luma;
+	unsigned int   dpte_groups_per_row_luma_ub;
+	unsigned int   dpte_group_width_chroma;
+	unsigned int   dpte_groups_per_row_chroma_ub;
+	unsigned int k;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0)
+			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
+		else
+			DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
+		DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0)
+			DST_Y_PER_META_ROW_NOM_C[k] = 0;
+		else
+			DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (DCCEnable[k] == true) {
+			meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
+			min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
+			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
+			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
+			if (!IsVertical(SourceRotation[k]))
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
+			else
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
+
+			if (meta_row_remainder <= meta_chunk_threshold)
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+			else
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+
+			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			if (BytePerPixelC[k] == 0) {
+				TimePerChromaMetaChunkNominal[k] = 0;
+				TimePerChromaMetaChunkVBlank[k] = 0;
+				TimePerChromaMetaChunkFlip[k] = 0;
+			} else {
+				meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] /
+						meta_row_height_chroma[k];
+				min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] /
+						meta_row_height_chroma[k];
+				meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] /
+						meta_chunk_width_chroma;
+				meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
+				if (!IsVertical(SourceRotation[k])) {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma -
+							meta_req_width_chroma[k];
+				} else {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma -
+							meta_req_height_chroma[k];
+				}
+				if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma)
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1;
+				else
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2;
+
+				TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+						HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+			}
+		} else {
+			TimePerMetaChunkNominal[k] = 0;
+			TimePerMetaChunkVBlank[k] = 0;
+			TimePerMetaChunkFlip[k] = 0;
+			TimePerChromaMetaChunkNominal[k] = 0;
+			TimePerChromaMetaChunkVBlank[k] = 0;
+			TimePerChromaMetaChunkFlip[k] = 0;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (GPUVMEnable == true) {
+			if (!IsVertical(SourceRotation[k])) {
+				dpte_group_width_luma = (double) dpte_group_bytes[k] /
+						(double) PTERequestSizeY[k] * PixelPTEReqWidthY[k];
+			} else {
+				dpte_group_width_luma = (double) dpte_group_bytes[k] /
+						(double) PTERequestSizeY[k] * PixelPTEReqHeightY[k];
+			}
+
+			if (use_one_row_for_frame[k]) {
+				dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
+						(double) dpte_group_width_luma / 2.0, 1.0);
+			} else {
+				dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
+						(double) dpte_group_width_luma, 1.0);
+			}
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d, use_one_row_for_frame        = %d\n",
+					__func__, k, use_one_row_for_frame[k]);
+			dml_print("DML::%s: k=%0d, dpte_group_bytes             = %d\n",
+					__func__, k, dpte_group_bytes[k]);
+			dml_print("DML::%s: k=%0d, PTERequestSizeY              = %d\n",
+					__func__, k, PTERequestSizeY[k]);
+			dml_print("DML::%s: k=%0d, PixelPTEReqWidthY            = %d\n",
+					__func__, k, PixelPTEReqWidthY[k]);
+			dml_print("DML::%s: k=%0d, PixelPTEReqHeightY           = %d\n",
+					__func__, k, PixelPTEReqHeightY[k]);
+			dml_print("DML::%s: k=%0d, dpte_row_width_luma_ub       = %d\n",
+					__func__, k, dpte_row_width_luma_ub[k]);
+			dml_print("DML::%s: k=%0d, dpte_group_width_luma        = %d\n",
+					__func__, k, dpte_group_width_luma);
+			dml_print("DML::%s: k=%0d, dpte_groups_per_row_luma_ub  = %d\n",
+					__func__, k, dpte_groups_per_row_luma_ub);
+#endif
+
+			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			if (BytePerPixelC[k] == 0) {
+				time_per_pte_group_nom_chroma[k] = 0;
+				time_per_pte_group_vblank_chroma[k] = 0;
+				time_per_pte_group_flip_chroma[k] = 0;
+			} else {
+				if (!IsVertical(SourceRotation[k])) {
+					dpte_group_width_chroma = (double) dpte_group_bytes[k] /
+							(double) PTERequestSizeC[k] * PixelPTEReqWidthC[k];
+				} else {
+					dpte_group_width_chroma = (double) dpte_group_bytes[k] /
+							(double) PTERequestSizeC[k] * PixelPTEReqHeightC[k];
+				}
+
+				if (use_one_row_for_frame[k]) {
+					dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
+							(double) dpte_group_width_chroma / 2.0, 1.0);
+				} else {
+					dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
+							(double) dpte_group_width_chroma, 1.0);
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, dpte_row_width_chroma_ub        = %d\n",
+						__func__, k, dpte_row_width_chroma_ub[k]);
+				dml_print("DML::%s: k=%0d, dpte_group_width_chroma        = %d\n",
+						__func__, k, dpte_group_width_chroma);
+				dml_print("DML::%s: k=%0d, dpte_groups_per_row_chroma_ub  = %d\n",
+						__func__, k, dpte_groups_per_row_chroma_ub);
+#endif
+				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
+						HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+			}
+		} else {
+			time_per_pte_group_nom_luma[k] = 0;
+			time_per_pte_group_vblank_luma[k] = 0;
+			time_per_pte_group_flip_luma[k] = 0;
+			time_per_pte_group_nom_chroma[k] = 0;
+			time_per_pte_group_vblank_chroma[k] = 0;
+			time_per_pte_group_flip_chroma[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInVBlank         = %f\n",
+				__func__, k, DestinationLinesToRequestRowInVBlank[k]);
+		dml_print("DML::%s: k=%0d, DestinationLinesToRequestRowInImmediateFlip  = %f\n",
+				__func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_L                      = %f\n",
+				__func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_PTE_ROW_NOM_C                      = %f\n",
+				__func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_L                     = %f\n",
+				__func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
+		dml_print("DML::%s: k=%0d, DST_Y_PER_META_ROW_NOM_C                     = %f\n",
+				__func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkNominal          = %f\n",
+				__func__, k, TimePerMetaChunkNominal[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkVBlank           = %f\n",
+				__func__, k, TimePerMetaChunkVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerMetaChunkFlip             = %f\n",
+				__func__, k, TimePerMetaChunkFlip[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkNominal    = %f\n",
+				__func__, k, TimePerChromaMetaChunkNominal[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkVBlank     = %f\n",
+				__func__, k, TimePerChromaMetaChunkVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerChromaMetaChunkFlip       = %f\n",
+				__func__, k, TimePerChromaMetaChunkFlip[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_nom_luma      = %f\n",
+				__func__, k, time_per_pte_group_nom_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_luma   = %f\n",
+				__func__, k, time_per_pte_group_vblank_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_flip_luma     = %f\n",
+				__func__, k, time_per_pte_group_flip_luma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_nom_chroma    = %f\n",
+				__func__, k, time_per_pte_group_nom_chroma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_vblank_chroma = %f\n",
+				__func__, k, time_per_pte_group_vblank_chroma[k]);
+		dml_print("DML::%s: k=%0d, time_per_pte_group_flip_chroma   = %f\n",
+				__func__, k, time_per_pte_group_flip_chroma[k]);
+#endif
+	}
+} // CalculateMetaAndPTETimes
+
+void dml32_CalculateVMGroupAndRequestTimes(
+		unsigned int     NumberOfActiveSurfaces,
+		bool     GPUVMEnable,
+		unsigned int     GPUVMMaxPageTableLevels,
+		unsigned int     HTotal[],
+		unsigned int     BytePerPixelC[],
+		double      DestinationLinesToRequestVMInVBlank[],
+		double      DestinationLinesToRequestVMInImmediateFlip[],
+		bool     DCCEnable[],
+		double      PixelClock[],
+		unsigned int        dpte_row_width_luma_ub[],
+		unsigned int        dpte_row_width_chroma_ub[],
+		unsigned int     vm_group_bytes[],
+		unsigned int     dpde0_bytes_per_frame_ub_l[],
+		unsigned int     dpde0_bytes_per_frame_ub_c[],
+		unsigned int        meta_pte_bytes_per_frame_ub_l[],
+		unsigned int        meta_pte_bytes_per_frame_ub_c[],
+
+		/* Output */
+		double      TimePerVMGroupVBlank[],
+		double      TimePerVMGroupFlip[],
+		double      TimePerVMRequestVBlank[],
+		double      TimePerVMRequestFlip[])
+{
+	unsigned int k;
+	unsigned int   num_group_per_lower_vm_stage;
+	unsigned int   num_req_per_lower_vm_stage;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, NumberOfActiveSurfaces);
+	dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
+#endif
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, DCCEnable = %d\n", __func__, k, DCCEnable[k]);
+		dml_print("DML::%s: k=%0d, vm_group_bytes = %d\n", __func__, k, vm_group_bytes[k]);
+		dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_l = %d\n",
+				__func__, k, dpde0_bytes_per_frame_ub_l[k]);
+		dml_print("DML::%s: k=%0d, dpde0_bytes_per_frame_ub_c = %d\n",
+				__func__, k, dpde0_bytes_per_frame_ub_c[k]);
+		dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_l = %d\n",
+				__func__, k, meta_pte_bytes_per_frame_ub_l[k]);
+		dml_print("DML::%s: k=%0d, meta_pte_bytes_per_frame_ub_c = %d\n",
+				__func__, k, meta_pte_bytes_per_frame_ub_c[k]);
+#endif
+
+		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_group_per_lower_vm_stage = dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0) +
+							dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+				} else {
+					num_group_per_lower_vm_stage = dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = dml_ceil(
+							(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1.0) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1.0);
+					} else {
+						num_group_per_lower_vm_stage = dml_ceil(
+								(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+								(double) (vm_group_bytes[k]), 1.0);
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = 2 + dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) +
+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
+							(double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = 1 + dml_ceil(
+							(double) (dpde0_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1) + dml_ceil(
+							(double) (meta_pte_bytes_per_frame_ub_l[k]) /
+							(double) (vm_group_bytes[k]), 1);
+					}
+				}
+			}
+
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 +
+							dpde0_bytes_per_frame_ub_c[k] / 64;
+				} else {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 +
+								meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
+								64 + dpde0_bytes_per_frame_ub_c[k] / 64 +
+								meta_pte_bytes_per_frame_ub_l[k] / 64 +
+								meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
+								64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				}
+			}
+
+			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
+					HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
+					HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
+					HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+
+			if (GPUVMMaxPageTableLevels > 2) {
+				TimePerVMGroupVBlank[k]    = TimePerVMGroupVBlank[k] / 2;
+				TimePerVMGroupFlip[k]      = TimePerVMGroupFlip[k] / 2;
+				TimePerVMRequestVBlank[k]  = TimePerVMRequestVBlank[k] / 2;
+				TimePerVMRequestFlip[k]    = TimePerVMRequestFlip[k] / 2;
+			}
+
+		} else {
+			TimePerVMGroupVBlank[k] = 0;
+			TimePerVMGroupFlip[k] = 0;
+			TimePerVMRequestVBlank[k] = 0;
+			TimePerVMRequestFlip[k] = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
+		dml_print("DML::%s: k=%0d, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
+#endif
+	}
+} // CalculateVMGroupAndRequestTimes
+
+void dml32_CalculateDCCConfiguration(
+		bool             DCCEnabled,
+		bool             DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int             SurfaceWidthLuma,
+		unsigned int             SurfaceWidthChroma,
+		unsigned int             SurfaceHeightLuma,
+		unsigned int             SurfaceHeightChroma,
+		unsigned int                nomDETInKByte,
+		unsigned int             RequestHeight256ByteLuma,
+		unsigned int             RequestHeight256ByteChroma,
+		enum dm_swizzle_mode     TilingFormat,
+		unsigned int             BytePerPixelY,
+		unsigned int             BytePerPixelC,
+		double              BytePerPixelDETY,
+		double              BytePerPixelDETC,
+		enum dm_rotation_angle   SourceRotation,
+		/* Output */
+		unsigned int        *MaxUncompressedBlockLuma,
+		unsigned int        *MaxUncompressedBlockChroma,
+		unsigned int        *MaxCompressedBlockLuma,
+		unsigned int        *MaxCompressedBlockChroma,
+		unsigned int        *IndependentBlockLuma,
+		unsigned int        *IndependentBlockChroma)
+{
+	typedef enum {
+		REQ_256Bytes,
+		REQ_128BytesNonContiguous,
+		REQ_128BytesContiguous,
+		REQ_NA
+	} RequestType;
+
+	RequestType   RequestLuma;
+	RequestType   RequestChroma;
+
+	unsigned int   segment_order_horz_contiguous_luma;
+	unsigned int   segment_order_horz_contiguous_chroma;
+	unsigned int   segment_order_vert_contiguous_luma;
+	unsigned int   segment_order_vert_contiguous_chroma;
+	unsigned int req128_horz_wc_l;
+	unsigned int req128_horz_wc_c;
+	unsigned int req128_vert_wc_l;
+	unsigned int req128_vert_wc_c;
+	unsigned int MAS_vp_horz_limit;
+	unsigned int MAS_vp_vert_limit;
+	unsigned int max_vp_horz_width;
+	unsigned int max_vp_vert_height;
+	unsigned int eff_surf_width_l;
+	unsigned int eff_surf_width_c;
+	unsigned int eff_surf_height_l;
+	unsigned int eff_surf_height_c;
+	unsigned int full_swath_bytes_horz_wc_l;
+	unsigned int full_swath_bytes_horz_wc_c;
+	unsigned int full_swath_bytes_vert_wc_l;
+	unsigned int full_swath_bytes_vert_wc_c;
+	unsigned int DETBufferSizeForDCC = nomDETInKByte * 1024;
+
+	unsigned int   yuv420;
+	unsigned int   horz_div_l;
+	unsigned int   horz_div_c;
+	unsigned int   vert_div_l;
+	unsigned int   vert_div_c;
+
+	unsigned int     swath_buf_size;
+	double   detile_buf_vp_horz_limit;
+	double   detile_buf_vp_vert_limit;
+
+	yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 ||
+			SourcePixelFormat == dm_420_12) ? 1 : 0);
+	horz_div_l = 1;
+	horz_div_c = 1;
+	vert_div_l = 1;
+	vert_div_c = 1;
+
+	if (BytePerPixelY == 1)
+		vert_div_l = 0;
+	if (BytePerPixelC == 1)
+		vert_div_c = 0;
+
+	if (BytePerPixelC == 0) {
+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma *
+				BytePerPixelY / (1 + horz_div_l));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma /
+				(1 + vert_div_l));
+	} else {
+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma *
+				BytePerPixelY / (1 + horz_div_l) + (double) RequestHeight256ByteChroma *
+				BytePerPixelC / (1 + horz_div_c) / (1 + yuv420));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma /
+				(1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma /
+				(1 + vert_div_c) / (1 + yuv420));
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit;
+		detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit;
+	}
+
+	detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16);
+	detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16);
+
+	MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 6144;
+	MAS_vp_vert_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144);
+	max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
+	max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
+	eff_surf_width_l =  (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+	eff_surf_width_c =  eff_surf_width_l / (1 + yuv420);
+	eff_surf_height_l =  (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma);
+	eff_surf_height_c =  eff_surf_height_l / (1 + yuv420);
+
+	full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
+	full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma;
+	if (BytePerPixelC > 0) {
+		full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC;
+		full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma;
+	} else {
+		full_swath_bytes_horz_wc_c = 0;
+		full_swath_bytes_vert_wc_c = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		full_swath_bytes_horz_wc_l = dml_ceil((double) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0);
+		full_swath_bytes_horz_wc_c = dml_ceil((double) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0);
+		full_swath_bytes_vert_wc_l = dml_ceil((double) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0);
+		full_swath_bytes_vert_wc_c = dml_ceil((double) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0);
+	}
+
+	if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 0;
+	} else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l +
+			full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 1;
+	} else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 *
+			full_swath_bytes_horz_wc_c <= DETBufferSizeForDCC) {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 0;
+	} else {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 1;
+	}
+
+	if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 0;
+	} else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 *
+			full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 1;
+	} else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c &&
+			full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSizeForDCC) {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 0;
+	} else {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 1;
+	}
+
+	if (BytePerPixelY == 2) {
+		segment_order_horz_contiguous_luma = 0;
+		segment_order_vert_contiguous_luma = 1;
+	} else {
+		segment_order_horz_contiguous_luma = 1;
+		segment_order_vert_contiguous_luma = 0;
+	}
+
+	if (BytePerPixelC == 2) {
+		segment_order_horz_contiguous_chroma = 0;
+		segment_order_vert_contiguous_chroma = 1;
+	} else {
+		segment_order_horz_contiguous_chroma = 1;
+		segment_order_vert_contiguous_chroma = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DCCEnabled = %d\n", __func__, DCCEnabled);
+	dml_print("DML::%s: nomDETInKByte = %d\n", __func__, nomDETInKByte);
+	dml_print("DML::%s: DETBufferSizeForDCC = %d\n", __func__, DETBufferSizeForDCC);
+	dml_print("DML::%s: req128_horz_wc_l = %d\n", __func__, req128_horz_wc_l);
+	dml_print("DML::%s: req128_horz_wc_c = %d\n", __func__, req128_horz_wc_c);
+	dml_print("DML::%s: full_swath_bytes_horz_wc_l = %d\n", __func__, full_swath_bytes_horz_wc_l);
+	dml_print("DML::%s: full_swath_bytes_vert_wc_c = %d\n", __func__, full_swath_bytes_vert_wc_c);
+	dml_print("DML::%s: segment_order_horz_contiguous_luma = %d\n", __func__, segment_order_horz_contiguous_luma);
+	dml_print("DML::%s: segment_order_horz_contiguous_chroma = %d\n",
+			__func__, segment_order_horz_contiguous_chroma);
+#endif
+
+	if (DCCProgrammingAssumesScanDirectionUnknown == true) {
+		if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) ||
+				(req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0))
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) ||
+				(req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0))
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+
+	} else if (!IsVertical(SourceRotation)) {
+		if (req128_horz_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if (segment_order_horz_contiguous_luma == 0)
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_horz_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if (segment_order_horz_contiguous_chroma == 0)
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+
+	} else {
+		if (req128_vert_wc_l == 0)
+			RequestLuma = REQ_256Bytes;
+		else if (segment_order_vert_contiguous_luma == 0)
+			RequestLuma = REQ_128BytesNonContiguous;
+		else
+			RequestLuma = REQ_128BytesContiguous;
+
+		if (req128_vert_wc_c == 0)
+			RequestChroma = REQ_256Bytes;
+		else if (segment_order_vert_contiguous_chroma == 0)
+			RequestChroma = REQ_128BytesNonContiguous;
+		else
+			RequestChroma = REQ_128BytesContiguous;
+	}
+
+	if (RequestLuma == REQ_256Bytes) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 256;
+		*IndependentBlockLuma = 0;
+	} else if (RequestLuma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 128;
+		*IndependentBlockLuma = 128;
+	} else {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 64;
+		*IndependentBlockLuma = 64;
+	}
+
+	if (RequestChroma == REQ_256Bytes) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 256;
+		*IndependentBlockChroma = 0;
+	} else if (RequestChroma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 128;
+		*IndependentBlockChroma = 128;
+	} else {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 64;
+		*IndependentBlockChroma = 64;
+	}
+
+	if (DCCEnabled != true || BytePerPixelC == 0) {
+		*MaxUncompressedBlockChroma = 0;
+		*MaxCompressedBlockChroma = 0;
+		*IndependentBlockChroma = 0;
+	}
+
+	if (DCCEnabled != true) {
+		*MaxUncompressedBlockLuma = 0;
+		*MaxCompressedBlockLuma = 0;
+		*IndependentBlockLuma = 0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MaxUncompressedBlockLuma = %d\n", __func__, *MaxUncompressedBlockLuma);
+	dml_print("DML::%s: MaxCompressedBlockLuma = %d\n", __func__, *MaxCompressedBlockLuma);
+	dml_print("DML::%s: IndependentBlockLuma = %d\n", __func__, *IndependentBlockLuma);
+	dml_print("DML::%s: MaxUncompressedBlockChroma = %d\n", __func__, *MaxUncompressedBlockChroma);
+	dml_print("DML::%s: MaxCompressedBlockChroma = %d\n", __func__, *MaxCompressedBlockChroma);
+	dml_print("DML::%s: IndependentBlockChroma = %d\n", __func__, *IndependentBlockChroma);
+#endif
+
+} // CalculateDCCConfiguration
+
+void dml32_CalculateStutterEfficiency(
+		unsigned int      CompressedBufferSizeInkByte,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool   UnboundedRequestEnabled,
+		unsigned int      MetaFIFOSizeInKEntries,
+		unsigned int      ZeroSizeBufferEntries,
+		unsigned int      PixelChunkSizeInKByte,
+		unsigned int   NumberOfActiveSurfaces,
+		unsigned int      ROBBufferSizeInKByte,
+		double    TotalDataReadBandwidth,
+		double    DCFCLK,
+		double    ReturnBW,
+		unsigned int      CompbufReservedSpace64B,
+		unsigned int      CompbufReservedSpaceZs,
+		double    SRExitTime,
+		double    SRExitZ8Time,
+		bool   SynchronizeTimingsFinal,
+		unsigned int   BlendingAndTiming[],
+		double    StutterEnterPlusExitWatermark,
+		double    Z8StutterEnterPlusExitWatermark,
+		bool   ProgressiveToInterlaceUnitInOPP,
+		bool   Interlace[],
+		double    MinTTUVBlank[],
+		unsigned int   DPPPerSurface[],
+		unsigned int      DETBufferSizeY[],
+		unsigned int   BytePerPixelY[],
+		double    BytePerPixelDETY[],
+		double      SwathWidthY[],
+		unsigned int   SwathHeightY[],
+		unsigned int   SwathHeightC[],
+		double    NetDCCRateLuma[],
+		double    NetDCCRateChroma[],
+		double    DCCFractionOfZeroSizeRequestsLuma[],
+		double    DCCFractionOfZeroSizeRequestsChroma[],
+		unsigned int      HTotal[],
+		unsigned int      VTotal[],
+		double    PixelClock[],
+		double    VRatio[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int   BlockHeight256BytesY[],
+		unsigned int   BlockWidth256BytesY[],
+		unsigned int   BlockHeight256BytesC[],
+		unsigned int   BlockWidth256BytesC[],
+		unsigned int   DCCYMaxUncompressedBlock[],
+		unsigned int   DCCCMaxUncompressedBlock[],
+		unsigned int      VActive[],
+		bool   DCCEnable[],
+		bool   WritebackEnable[],
+		double    ReadBandwidthSurfaceLuma[],
+		double    ReadBandwidthSurfaceChroma[],
+		double    meta_row_bw[],
+		double    dpte_row_bw[],
+
+		/* Output */
+		double   *StutterEfficiencyNotIncludingVBlank,
+		double   *StutterEfficiency,
+		unsigned int     *NumberOfStutterBurstsPerFrame,
+		double   *Z8StutterEfficiencyNotIncludingVBlank,
+		double   *Z8StutterEfficiency,
+		unsigned int     *Z8NumberOfStutterBurstsPerFrame,
+		double   *StutterPeriod,
+		bool  *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE)
+{
+
+	bool FoundCriticalSurface = false;
+	unsigned int SwathSizeCriticalSurface = 0;
+	unsigned int LastChunkOfSwathSize;
+	unsigned int MissingPartOfLastSwathOfDETSize;
+	double LastZ8StutterPeriod = 0.0;
+	double LastStutterPeriod = 0.0;
+	unsigned int TotalNumberOfActiveOTG = 0;
+	double doublePixelClock;
+	unsigned int doubleHTotal;
+	unsigned int doubleVTotal;
+	bool SameTiming = true;
+	double DETBufferingTimeY;
+	double SwathWidthYCriticalSurface = 0.0;
+	double SwathHeightYCriticalSurface = 0.0;
+	double VActiveTimeCriticalSurface = 0.0;
+	double FrameTimeCriticalSurface = 0.0;
+	unsigned int BytePerPixelYCriticalSurface = 0;
+	double LinesToFinishSwathTransferStutterCriticalSurface = 0.0;
+	unsigned int DETBufferSizeYCriticalSurface = 0;
+	double MinTTUVBlankCriticalSurface = 0.0;
+	unsigned int BlockWidth256BytesYCriticalSurface = 0;
+	bool doublePlaneCriticalSurface = 0;
+	bool doublePipeCriticalSurface = 0;
+	double TotalCompressedReadBandwidth;
+	double TotalRowReadBandwidth;
+	double AverageDCCCompressionRate;
+	double EffectiveCompressedBufferSize;
+	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
+	double StutterBurstTime;
+	unsigned int TotalActiveWriteback;
+	double LinesInDETY;
+	double LinesInDETYRoundedDownToSwath;
+	double MaximumEffectiveCompressionLuma;
+	double MaximumEffectiveCompressionChroma;
+	double TotalZeroSizeRequestReadBandwidth;
+	double TotalZeroSizeCompressedReadBandwidth;
+	double AverageDCCZeroSizeFraction;
+	double AverageZeroSizeCompressionRate;
+	unsigned int k;
+
+	TotalZeroSizeRequestReadBandwidth = 0;
+	TotalZeroSizeCompressedReadBandwidth = 0;
+	TotalRowReadBandwidth = 0;
+	TotalCompressedReadBandwidth = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			if (DCCEnable[k] == true) {
+				if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesY[k] > SwathHeightY[k])
+						|| (!IsVertical(SourceRotation[k])
+								&& BlockHeight256BytesY[k] > SwathHeightY[k])
+						|| DCCYMaxUncompressedBlock[k] < 256) {
+					MaximumEffectiveCompressionLuma = 2;
+				} else {
+					MaximumEffectiveCompressionLuma = 4;
+				}
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k]
+								/ dml_min(NetDCCRateLuma[k],
+										MaximumEffectiveCompressionLuma);
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n",
+						__func__, k, ReadBandwidthSurfaceLuma[k]);
+				dml_print("DML::%s: k=%0d, NetDCCRateLuma = %f\n",
+						__func__, k, NetDCCRateLuma[k]);
+				dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionLuma = %f\n",
+						__func__, k, MaximumEffectiveCompressionLuma);
+#endif
+				TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
+				TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]
+								/ MaximumEffectiveCompressionLuma;
+
+				if (ReadBandwidthSurfaceChroma[k] > 0) {
+					if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesC[k] > SwathHeightC[k])
+							|| (!IsVertical(SourceRotation[k])
+									&& BlockHeight256BytesC[k] > SwathHeightC[k])
+							|| DCCCMaxUncompressedBlock[k] < 256) {
+						MaximumEffectiveCompressionChroma = 2;
+					} else {
+						MaximumEffectiveCompressionChroma = 4;
+					}
+					TotalCompressedReadBandwidth =
+							TotalCompressedReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+							/ dml_min(NetDCCRateChroma[k],
+							MaximumEffectiveCompressionChroma);
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceChroma = %f\n",
+							__func__, k, ReadBandwidthSurfaceChroma[k]);
+					dml_print("DML::%s: k=%0d, NetDCCRateChroma = %f\n",
+							__func__, k, NetDCCRateChroma[k]);
+					dml_print("DML::%s: k=%0d, MaximumEffectiveCompressionChroma = %f\n",
+							__func__, k, MaximumEffectiveCompressionChroma);
+#endif
+					TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+									* DCCFractionOfZeroSizeRequestsChroma[k];
+					TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+							+ ReadBandwidthSurfaceChroma[k]
+									* DCCFractionOfZeroSizeRequestsChroma[k]
+									/ MaximumEffectiveCompressionChroma;
+				}
+			} else {
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthSurfaceLuma[k] + ReadBandwidthSurfaceChroma[k];
+			}
+			TotalRowReadBandwidth = TotalRowReadBandwidth
+					+ DPPPerSurface[k] * (meta_row_bw[k] + dpte_row_bw[k]);
+		}
+	}
+
+	AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth;
+	AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, UnboundedRequestEnabled);
+	dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n",
+			__func__, TotalZeroSizeCompressedReadBandwidth);
+	dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma);
+	dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction);
+	dml_print("DML::%s: CompbufReservedSpace64B = %d\n", __func__, CompbufReservedSpace64B);
+	dml_print("DML::%s: CompbufReservedSpaceZs = %d\n", __func__, CompbufReservedSpaceZs);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte);
+#endif
+	if (AverageDCCZeroSizeFraction == 1) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth
+				/ TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = (double) MetaFIFOSizeInKEntries * 1024 * 64
+				* AverageZeroSizeCompressionRate
+				+ ((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64
+						* AverageZeroSizeCompressionRate;
+	} else if (AverageDCCZeroSizeFraction > 0) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth
+				/ TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = dml_min(
+				(double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				(double) MetaFIFOSizeInKEntries * 1024 * 64
+					/ (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate
+					+ 1 / AverageDCCCompressionRate))
+					+ dml_min(((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64)
+					* AverageDCCCompressionRate,
+					((double) ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64
+					/ (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: min 1 = %f\n", __func__,
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 /
+				(AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 /
+						AverageDCCCompressionRate));
+		dml_print("DML::%s: min 3 = %f\n", __func__, (ROBBufferSizeInKByte * 1024 -
+				CompbufReservedSpace64B * 64) * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 4 = %f\n", __func__, (ZeroSizeBufferEntries - CompbufReservedSpaceZs) * 64 /
+				(AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+#endif
+	} else {
+		EffectiveCompressedBufferSize = dml_min(
+				(double) CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				(double) MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate)
+				+ ((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64)
+						* AverageDCCCompressionRate;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: min 1 = %f\n", __func__,
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__,
+				MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate);
+#endif
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries);
+	dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+#endif
+
+	*StutterPeriod = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			LinesInDETY = ((double) DETBufferSizeY[k]
+					+ (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0)
+							* ReadBandwidthSurfaceLuma[k] / TotalDataReadBandwidth)
+					/ BytePerPixelDETY[k] / SwathWidthY[k];
+			LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
+			DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((double) HTotal[k] / PixelClock[k])
+					/ VRatio[k];
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
+			dml_print("DML::%s: k=%0d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
+			dml_print("DML::%s: k=%0d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
+			dml_print("DML::%s: k=%0d, ReadBandwidthSurfaceLuma = %f\n",
+					__func__, k, ReadBandwidthSurfaceLuma[k]);
+			dml_print("DML::%s: k=%0d, TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
+			dml_print("DML::%s: k=%0d, LinesInDETY = %f\n", __func__, k, LinesInDETY);
+			dml_print("DML::%s: k=%0d, LinesInDETYRoundedDownToSwath = %f\n",
+					__func__, k, LinesInDETYRoundedDownToSwath);
+			dml_print("DML::%s: k=%0d, HTotal = %d\n", __func__, k, HTotal[k]);
+			dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+			dml_print("DML::%s: k=%0d, VRatio = %f\n", __func__, k, VRatio[k]);
+			dml_print("DML::%s: k=%0d, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
+			dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
+#endif
+
+			if (!FoundCriticalSurface || DETBufferingTimeY < *StutterPeriod) {
+				bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
+
+				FoundCriticalSurface = true;
+				*StutterPeriod = DETBufferingTimeY;
+				FrameTimeCriticalSurface = (
+						isInterlaceTiming ?
+								dml_floor((double) VTotal[k] / 2.0, 1.0) : VTotal[k])
+						* (double) HTotal[k] / PixelClock[k];
+				VActiveTimeCriticalSurface = (
+						isInterlaceTiming ?
+								dml_floor((double) VActive[k] / 2.0, 1.0) : VActive[k])
+						* (double) HTotal[k] / PixelClock[k];
+				BytePerPixelYCriticalSurface = BytePerPixelY[k];
+				SwathWidthYCriticalSurface = SwathWidthY[k];
+				SwathHeightYCriticalSurface = SwathHeightY[k];
+				BlockWidth256BytesYCriticalSurface = BlockWidth256BytesY[k];
+				LinesToFinishSwathTransferStutterCriticalSurface = SwathHeightY[k]
+						- (LinesInDETY - LinesInDETYRoundedDownToSwath);
+				DETBufferSizeYCriticalSurface = DETBufferSizeY[k];
+				MinTTUVBlankCriticalSurface = MinTTUVBlank[k];
+				doublePlaneCriticalSurface = (ReadBandwidthSurfaceChroma[k] == 0);
+				doublePipeCriticalSurface = (DPPPerSurface[k] == 1);
+
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: k=%0d, FoundCriticalSurface                = %d\n",
+						__func__, k, FoundCriticalSurface);
+				dml_print("DML::%s: k=%0d, StutterPeriod                       = %f\n",
+						__func__, k, *StutterPeriod);
+				dml_print("DML::%s: k=%0d, MinTTUVBlankCriticalSurface         = %f\n",
+						__func__, k, MinTTUVBlankCriticalSurface);
+				dml_print("DML::%s: k=%0d, FrameTimeCriticalSurface            = %f\n",
+						__func__, k, FrameTimeCriticalSurface);
+				dml_print("DML::%s: k=%0d, VActiveTimeCriticalSurface          = %f\n",
+						__func__, k, VActiveTimeCriticalSurface);
+				dml_print("DML::%s: k=%0d, BytePerPixelYCriticalSurface        = %d\n",
+						__func__, k, BytePerPixelYCriticalSurface);
+				dml_print("DML::%s: k=%0d, SwathWidthYCriticalSurface          = %f\n",
+						__func__, k, SwathWidthYCriticalSurface);
+				dml_print("DML::%s: k=%0d, SwathHeightYCriticalSurface         = %f\n",
+						__func__, k, SwathHeightYCriticalSurface);
+				dml_print("DML::%s: k=%0d, BlockWidth256BytesYCriticalSurface  = %d\n",
+						__func__, k, BlockWidth256BytesYCriticalSurface);
+				dml_print("DML::%s: k=%0d, doublePlaneCriticalSurface          = %d\n",
+						__func__, k, doublePlaneCriticalSurface);
+				dml_print("DML::%s: k=%0d, doublePipeCriticalSurface           = %d\n",
+						__func__, k, doublePipeCriticalSurface);
+				dml_print("DML::%s: k=%0d, LinesToFinishSwathTransferStutterCriticalSurface = %f\n",
+						__func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
+#endif
+			}
+		}
+	}
+
+	PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth,
+			EffectiveCompressedBufferSize);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n",
+			__func__, *StutterPeriod * TotalDataReadBandwidth);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+	dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__,
+			PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW);
+	dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth);
+	dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth);
+	dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
+#endif
+
+	StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate
+			/ ReturnBW
+			+ (*StutterPeriod * TotalDataReadBandwidth
+					- PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)
+			+ *StutterPeriod * TotalRowReadBandwidth / ReturnBW;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer /
+			AverageDCCCompressionRate / ReturnBW);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n",
+			__func__, (*StutterPeriod * TotalDataReadBandwidth));
+	dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth -
+			PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64));
+	dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+#endif
+	StutterBurstTime = dml_max(StutterBurstTime,
+			LinesToFinishSwathTransferStutterCriticalSurface * BytePerPixelYCriticalSurface
+					* SwathWidthYCriticalSurface / ReturnBW);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Time to finish residue swath=%f\n",
+			__func__,
+			LinesToFinishSwathTransferStutterCriticalSurface *
+			BytePerPixelYCriticalSurface * SwathWidthYCriticalSurface / ReturnBW);
+#endif
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (WritebackEnable[k])
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+	}
+
+	if (TotalActiveWriteback == 0) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime);
+		dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time);
+		dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime);
+		dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+#endif
+		*StutterEfficiencyNotIncludingVBlank = dml_max(0.,
+				1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
+		*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0.,
+				1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
+		*NumberOfStutterBurstsPerFrame = (
+				*StutterEfficiencyNotIncludingVBlank > 0 ?
+						dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0);
+		*Z8NumberOfStutterBurstsPerFrame = (
+				*Z8StutterEfficiencyNotIncludingVBlank > 0 ?
+						dml_ceil(VActiveTimeCriticalSurface / *StutterPeriod, 1) : 0);
+	} else {
+		*StutterEfficiencyNotIncludingVBlank = 0.;
+		*Z8StutterEfficiencyNotIncludingVBlank = 0.;
+		*NumberOfStutterBurstsPerFrame = 0;
+		*Z8NumberOfStutterBurstsPerFrame = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VActiveTimeCriticalSurface = %f\n", __func__, VActiveTimeCriticalSurface);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *Z8StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
+			if (BlendingAndTiming[k] == k) {
+				if (TotalNumberOfActiveOTG == 0) {
+					doublePixelClock = PixelClock[k];
+					doubleHTotal = HTotal[k];
+					doubleVTotal = VTotal[k];
+				} else if (doublePixelClock != PixelClock[k] || doubleHTotal != HTotal[k]
+						|| doubleVTotal != VTotal[k]) {
+					SameTiming = false;
+				}
+				TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+			}
+		}
+	}
+
+	if (*StutterEfficiencyNotIncludingVBlank > 0) {
+		LastStutterPeriod = VActiveTimeCriticalSurface - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+
+		if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming
+				&& LastStutterPeriod + MinTTUVBlankCriticalSurface > StutterEnterPlusExitWatermark) {
+			*StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime
+						+ StutterBurstTime * VActiveTimeCriticalSurface
+						/ *StutterPeriod) / FrameTimeCriticalSurface) * 100;
+		} else {
+			*StutterEfficiency = *StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*StutterEfficiency = 0;
+	}
+
+	if (*Z8StutterEfficiencyNotIncludingVBlank > 0) {
+		LastZ8StutterPeriod = VActiveTimeCriticalSurface
+				- (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+		if ((SynchronizeTimingsFinal || TotalNumberOfActiveOTG == 1) && SameTiming && LastZ8StutterPeriod +
+				MinTTUVBlankCriticalSurface > Z8StutterEnterPlusExitWatermark) {
+			*Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime
+				* VActiveTimeCriticalSurface / *StutterPeriod) / FrameTimeCriticalSurface) * 100;
+		} else {
+			*Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*Z8StutterEfficiency = 0.;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+	dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+	dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency);
+	dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n",
+			__func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	SwathSizeCriticalSurface = BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface
+			* dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface);
+	LastChunkOfSwathSize = SwathSizeCriticalSurface % (PixelChunkSizeInKByte * 1024);
+	MissingPartOfLastSwathOfDETSize = dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface)
+			- DETBufferSizeYCriticalSurface;
+
+	*DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!UnboundedRequestEnabled && (NumberOfActiveSurfaces == 1)
+			&& doublePlaneCriticalSurface && doublePipeCriticalSurface && (LastChunkOfSwathSize > 0)
+			&& (LastChunkOfSwathSize <= 4096) && (MissingPartOfLastSwathOfDETSize > 0)
+			&& (MissingPartOfLastSwathOfDETSize <= LastChunkOfSwathSize));
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: SwathSizeCriticalSurface = %d\n", __func__, SwathSizeCriticalSurface);
+	dml_print("DML::%s: LastChunkOfSwathSize = %d\n", __func__, LastChunkOfSwathSize);
+	dml_print("DML::%s: MissingPartOfLastSwathOfDETSize = %d\n", __func__, MissingPartOfLastSwathOfDETSize);
+	dml_print("DML::%s: DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = %d\n", __func__, *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+#endif
+} // CalculateStutterEfficiency
+
+void dml32_CalculateMaxDETAndMinCompressedBufferSize(
+		unsigned int    ConfigReturnBufferSizeInKByte,
+		unsigned int    ROBBufferSizeInKByte,
+		unsigned int MaxNumDPP,
+		bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
+		unsigned int nomDETInKByteOverrideValue,  // VBA_DELTA
+
+		/* Output */
+		unsigned int *MaxTotalDETInKByte,
+		unsigned int *nomDETInKByte,
+		unsigned int *MinCompressedBufferSizeInKByte)
+{
+	bool     det_buff_size_override_en  = nomDETInKByteOverrideEnable;
+	unsigned int        det_buff_size_override_val = nomDETInKByteOverrideValue;
+
+	*MaxTotalDETInKByte = dml_ceil(((double)ConfigReturnBufferSizeInKByte +
+			(double) ROBBufferSizeInKByte) * 4.0 / 5.0, 64);
+	*nomDETInKByte = dml_floor((double) *MaxTotalDETInKByte / (double) MaxNumDPP, 64);
+	*MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %0d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: ROBBufferSizeInKByte = %0d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: MaxNumDPP = %0d\n", __func__, MaxNumDPP);
+	dml_print("DML::%s: MaxTotalDETInKByte = %0d\n", __func__, *MaxTotalDETInKByte);
+	dml_print("DML::%s: nomDETInKByte = %0d\n", __func__, *nomDETInKByte);
+	dml_print("DML::%s: MinCompressedBufferSizeInKByte = %0d\n", __func__, *MinCompressedBufferSizeInKByte);
+#endif
+
+	if (det_buff_size_override_en) {
+		*nomDETInKByte = det_buff_size_override_val;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: nomDETInKByte = %0d (override)\n", __func__, *nomDETInKByte);
+#endif
+	}
+} // CalculateMaxDETAndMinCompressedBufferSize
+
+bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[])
+{
+	unsigned int k;
+	bool NotEnoughUrgentLatencyHiding = false;
+	bool CalculateVActiveBandwithSupport_val = false;
+	double VActiveBandwith = 0;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (NotUrgentLatencyHiding[k]) {
+			NotEnoughUrgentLatencyHiding = true;
+		}
+	}
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
+	}
+
+	CalculateVActiveBandwithSupport_val = (VActiveBandwith <= ReturnBW) && !NotEnoughUrgentLatencyHiding;
+
+#ifdef __DML_VBA_DEBUG__
+dml_print("DML::%s: NotEnoughUrgentLatencyHiding        = %d\n", __func__, NotEnoughUrgentLatencyHiding);
+dml_print("DML::%s: VActiveBandwith                     = %f\n", __func__, VActiveBandwith);
+dml_print("DML::%s: ReturnBW                            = %f\n", __func__, ReturnBW);
+dml_print("DML::%s: CalculateVActiveBandwithSupport_val = %d\n", __func__, CalculateVActiveBandwithSupport_val);
+#endif
+	return CalculateVActiveBandwithSupport_val;
+}
+
+void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *PrefetchBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *PrefetchBandwidthSupport)
+{
+	unsigned int k;
+	bool NotEnoughUrgentLatencyHiding = false;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (NotUrgentLatencyHiding[k]) {
+			NotEnoughUrgentLatencyHiding = true;
+		}
+	}
+
+	*PrefetchBandwidth = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		*PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+				ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
+				NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+	}
+
+	*PrefetchBandwidthSupport = (*PrefetchBandwidth <= ReturnBW) && !NotEnoughUrgentLatencyHiding;
+	*FractionOfUrgentBandwidth = *PrefetchBandwidth / ReturnBW;
+}
+
+double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double cursor_bw_pre[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[])
+{
+	unsigned int k;
+	double CalculateBandwidthAvailableForImmediateFlip_val = ReturnBW;
+
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+				NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+	}
+
+	return CalculateBandwidthAvailableForImmediateFlip_val;
+}
+
+void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		enum immediate_flip_requirement ImmediateFlipRequirement[],
+		double final_flip_bw[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *TotalBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *ImmediateFlipBandwidthSupport)
+{
+	unsigned int k;
+	*TotalBandwidth = 0;
+	for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+		if (ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
+			*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+					NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+					NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+		} else {
+			*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
+					NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
+					NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
+		}
+	}
+	*ImmediateFlipBandwidthSupport = (*TotalBandwidth <= ReturnBW);
+	*FractionOfUrgentBandwidth = *TotalBandwidth / ReturnBW;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
new file mode 100644
index 000000000000..72461b934ee0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -0,0 +1,1175 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__
+#define __DML_DCN32_DISPLAY_MODE_VBA_UTIL_32_H__
+
+#include "../display_mode_enums.h"
+#include "os_types.h"
+#include "../dc_features.h"
+#include "../display_mode_structs.h"
+
+unsigned int dml32_dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output);
+
+unsigned int dml32_dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output);
+
+bool IsVertical(enum dm_rotation_angle Scan);
+
+void dml32_CalculateBytePerPixelAndBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+
+		/*Output*/
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double           *BytePerPixelDETY,
+		double           *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC,
+		unsigned int *MacroTileHeightY,
+		unsigned int *MacroTileHeightC,
+		unsigned int *MacroTileWidthY,
+		unsigned int *MacroTileWidthC);
+
+void dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(
+		double HRatio,
+		double HRatioChroma,
+		double VRatio,
+		double VRatioChroma,
+		double MaxDCHUBToPSCLThroughput,
+		double MaxPSCLToLBThroughput,
+		double PixelClock,
+		enum source_format_class SourcePixelFormat,
+		unsigned int HTaps,
+		unsigned int HTapsChroma,
+		unsigned int VTaps,
+		unsigned int VTapsChroma,
+
+		/* output */
+		double *PSCL_THROUGHPUT,
+		double *PSCL_THROUGHPUT_CHROMA,
+		double *DPPCLKUsingSingleDPP);
+
+void dml32_CalculateSwathAndDETConfiguration(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		double ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int nomDETInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class Output[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum dm_rotation_angle SourceRotation[],
+		bool ViewportStationary[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BlendingAndTiming[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		unsigned int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool *UnboundedRequestEnabled,
+		unsigned int *CompressedBufferSizeInkByte,
+		bool ViewportSizeSupportPerSurface[],
+		bool *ViewportSizeSupport);
+
+void dml32_CalculateSwathWidth(
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		enum source_format_class SourcePixelFormat[],
+		enum dm_rotation_angle SourceScan[],
+		bool ViewportStationary[],
+		unsigned int ViewportWidth[],
+		unsigned int ViewportHeight[],
+		unsigned int ViewportXStart[],
+		unsigned int ViewportYStart[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		enum odm_combine_mode ODMMode[],
+		unsigned int BytePerPixY[],
+		unsigned int BytePerPixC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int BlendingAndTiming[],
+		unsigned int HActive[],
+		double HRatio[],
+		unsigned int DPPPerSurface[],
+
+		/* Output */
+		double SwathWidthdoubleDPPY[],
+		double SwathWidthdoubleDPPC[],
+		double SwathWidthY[], // per-pipe
+		double SwathWidthC[], // per-pipe
+		unsigned int MaximumSwathHeightY[],
+		unsigned int MaximumSwathHeightC[],
+		unsigned int swath_width_luma_ub[], // per-pipe
+		unsigned int swath_width_chroma_ub[]);
+
+bool dml32_UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		unsigned int TotalNumberOfActiveDPP,
+		bool NoChroma,
+		enum output_encoder_class Output);
+
+void dml32_CalculateDETBufferSize(
+		unsigned int DETSizeOverride[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool ForceSingleDPP,
+		unsigned int NumberOfActiveSurfaces,
+		bool UnboundedRequestEnabled,
+		unsigned int nomDETInKByte,
+		unsigned int MaxTotalDETInKByte,
+		unsigned int ConfigReturnBufferSizeInKByte,
+		unsigned int MinCompressedBufferSizeInKByte,
+		unsigned int CompressedBufferSegmentSizeInkByteFinal,
+		enum source_format_class SourcePixelFormat[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int RoundedUpMaxSwathSizeBytesY[],
+		unsigned int RoundedUpMaxSwathSizeBytesC[],
+		unsigned int DPPPerSurface[],
+		/* Output */
+		unsigned int DETBufferSizeInKByte[],
+		unsigned int *CompressedBufferSizeInkByte);
+
+void dml32_CalculateODMMode(
+		unsigned int MaximumPixelsPerLinePerDSCUnit,
+		unsigned int HActive,
+		enum output_encoder_class Output,
+		enum odm_combine_policy ODMUse,
+		double StateDispclk,
+		double MaxDispclk,
+		bool DSCEnable,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int MaxNumDPP,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+
+		/* Output */
+		bool *TotalAvailablePipesSupport,
+		unsigned int *NumberOfDPP,
+		enum odm_combine_mode *ODMMode,
+		double *RequiredDISPCLKPerSurface);
+
+double dml32_CalculateRequiredDispclk(
+		enum odm_combine_mode ODMMode,
+		double PixelClock,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKRampingMargin,
+		double DISPCLKDPPCLKVCOSpeed,
+		double MaxDispclk);
+
+double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed);
+
+void dml32_CalculateOutputLink(
+		double PHYCLKPerState,
+		double PHYCLKD18PerState,
+		double PHYCLKD32PerState,
+		double Downspreading,
+		bool IsMainSurfaceUsingTheIndicatedTiming,
+		enum output_encoder_class Output,
+		enum output_format_class OutputFormat,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClockBackEnd,
+		double ForcedOutputLinkBPP,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int NumberOfDSCSlices,
+		double AudioSampleRate,
+		unsigned int AudioSampleLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		bool DSCEnable,
+		unsigned int OutputLinkDPLanes,
+		enum dm_output_link_dp_rate OutputLinkDPRate,
+
+		/* Output */
+		bool *RequiresDSC,
+		double *RequiresFEC,
+		double  *OutBpp,
+		enum dm_output_type *OutputType,
+		enum dm_output_rate *OutputRate,
+		unsigned int *RequiredSlots);
+
+void dml32_CalculateDPPCLK(
+		unsigned int NumberOfActiveSurfaces,
+		double DISPCLKDPPCLKDSCCLKDownSpreading,
+		double DISPCLKDPPCLKVCOSpeed,
+		double DPPCLKUsingSingleDPP[],
+		unsigned int DPPPerSurface[],
+
+		/* output */
+		double *GlobalDPPCLK,
+		double Dppclk[]);
+
+double dml32_TruncToValidBPP(
+		double LinkBitRate,
+		unsigned int Lanes,
+		unsigned int HTotal,
+		unsigned int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		unsigned int DSCSlices,
+		unsigned int AudioRate,
+		unsigned int AudioLayout,
+		enum odm_combine_mode ODMModeNoDSC,
+		enum odm_combine_mode ODMModeDSC,
+		/* Output */
+		unsigned int *RequiredSlots);
+
+double dml32_RequiredDTBCLK(
+		bool              DSCEnable,
+		double               PixelClock,
+		enum output_format_class  OutputFormat,
+		double               OutputBpp,
+		unsigned int              DSCSlices,
+		unsigned int                 HTotal,
+		unsigned int                 HActive,
+		unsigned int              AudioRate,
+		unsigned int              AudioLayout);
+
+unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
+		enum odm_combine_mode ODMMode,
+		unsigned int DSCInputBitPerComponent,
+		double OutputBpp,
+		unsigned int HActive,
+		unsigned int HTotal,
+		unsigned int NumberOfDSCSlices,
+		enum output_format_class  OutputFormat,
+		enum output_encoder_class Output,
+		double PixelClock,
+		double PixelClockBackEnd);
+
+void dml32_CalculateSurfaceSizeInMall(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCN,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		bool DCCEnable[],
+		bool ViewportStationary[],
+		unsigned int ViewportXStartY[],
+		unsigned int ViewportYStartY[],
+		unsigned int ViewportXStartC[],
+		unsigned int ViewportYStartC[],
+		unsigned int ViewportWidthY[],
+		unsigned int ViewportHeightY[],
+		unsigned int BytesPerPixelY[],
+		unsigned int ViewportWidthC[],
+		unsigned int ViewportHeightC[],
+		unsigned int BytesPerPixelC[],
+		unsigned int SurfaceWidthY[],
+		unsigned int SurfaceWidthC[],
+		unsigned int SurfaceHeightY[],
+		unsigned int SurfaceHeightC[],
+		unsigned int Read256BytesBlockWidthY[],
+		unsigned int Read256BytesBlockWidthC[],
+		unsigned int Read256BytesBlockHeightY[],
+		unsigned int Read256BytesBlockHeightC[],
+		unsigned int ReadBlockWidthY[],
+		unsigned int ReadBlockWidthC[],
+		unsigned int ReadBlockHeightY[],
+		unsigned int ReadBlockHeightC[],
+
+		/* Output */
+		unsigned int    SurfaceSizeInMALL[],
+		bool *ExceededMALLSize);
+
+void dml32_CalculateVMRowAndSwath(
+		unsigned int NumberOfActiveSurfaces,
+		DmlPipe myPipe[],
+		unsigned int SurfaceSizeInMALL[],
+		unsigned int PTEBufferSizeInRequestsLuma,
+		unsigned int PTEBufferSizeInRequestsChroma,
+		unsigned int DCCMetaBufferSizeBytes,
+		enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[],
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int MALLAllocatedForDCN,
+		double SwathWidthY[],
+		double SwathWidthC[],
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes[],
+		unsigned int HostVMMinPageSize,
+
+		/* Output */
+		bool PTEBufferSizeNotExceeded[],
+		bool DCCMetaBufferSizeNotExceeded[],
+		unsigned int dpte_row_width_luma_ub[],
+		unsigned int dpte_row_width_chroma_ub[],
+		unsigned int dpte_row_height_luma[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int dpte_row_height_linear_luma[],     // VBA_DELTA
+		unsigned int dpte_row_height_linear_chroma[],   // VBA_DELTA
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int vm_group_bytes[],
+		unsigned int dpte_group_bytes[],
+		unsigned int PixelPTEReqWidthY[],
+		unsigned int PixelPTEReqHeightY[],
+		unsigned int PTERequestSizeY[],
+		unsigned int PixelPTEReqWidthC[],
+		unsigned int PixelPTEReqHeightC[],
+		unsigned int PTERequestSizeC[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int meta_pte_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		unsigned int meta_pte_bytes_per_frame_ub_c[],
+		double PrefetchSourceLinesY[],
+		double PrefetchSourceLinesC[],
+		double VInitPreFillY[],
+		double VInitPreFillC[],
+		unsigned int MaxNumSwathY[],
+		unsigned int MaxNumSwathC[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double PixelPTEBytesPerRow[],
+		double PDEAndMetaPTEBytesFrame[],
+		double MetaRowByte[],
+		bool use_one_row_for_frame[],
+		bool use_one_row_for_frame_flip[],
+		bool UsesMALLForStaticScreen[],
+		bool PTE_BUFFER_MODE[],
+		unsigned int BIGK_FRAGMENT_SIZE[]);
+
+unsigned int dml32_CalculateVMAndRowBytes(
+		bool ViewportStationary,
+		bool DCCEnable,
+		unsigned int NumberOfDPPs,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum dm_rotation_angle SourceScan,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int    ViewportXStart,
+		unsigned int    ViewportYStart,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int GPUVMMinPageSizeKBytes,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int MacroTileWidth,
+		unsigned int MacroTileHeight,
+
+		/* Output */
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		unsigned int    *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *dpte_row_height_linear,
+		unsigned int    *PixelPTEBytesPerRow_one_row_per_frame,
+		unsigned int    *dpte_row_width_ub_one_row_per_frame,
+		unsigned int    *dpte_row_height_one_row_per_frame,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		unsigned int    *DPDE0BytesFrame,
+		unsigned int    *MetaPTEBytesFrame);
+
+double dml32_CalculatePrefetchSourceLines(
+		double VRatio,
+		unsigned int VTaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		enum dm_rotation_angle SourceRotation,
+		bool ViewportStationary,
+		double SwathWidth,
+		unsigned int ViewportHeight,
+		unsigned int ViewportXStart,
+		unsigned int ViewportYStart,
+
+		/* Output */
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath);
+
+void dml32_CalculateMALLUseForStaticScreen(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MALLAllocatedForDCNFinal,
+		enum dm_use_mall_for_static_screen_mode *UseMALLForStaticScreen,
+		unsigned int SurfaceSizeInMALL[],
+		bool one_row_per_frame_fits_in_buffer[],
+
+		/* output */
+		bool UsesMALLForStaticScreen[]);
+
+void dml32_CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		/* Output */
+		double *meta_row_bw,
+		double *dpte_row_bw);
+
+double dml32_CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool   DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock);
+
+void dml32_CalculateUrgentBurstFactor(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		unsigned int    swath_width_luma_ub,
+		unsigned int    swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double  LineTime,
+		double  UrgentLatency,
+		double  CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double  VRatio,
+		double  VRatioC,
+		double  BytePerPixelInDETY,
+		double  BytePerPixelInDETC,
+		unsigned int    DETBufferSizeY,
+		unsigned int    DETBufferSizeC,
+		/* Output */
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool   *NotEnoughUrgentLatencyHiding);
+
+void dml32_CalculateDCFCLKDeepSleep(
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerSurface[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double Dppclk[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		unsigned int ReturnBusWidth,
+
+		/* Output */
+		double *DCFClkDeepSleep);
+
+double dml32_CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		unsigned int         WritebackDestinationWidth,
+		unsigned int         WritebackDestinationHeight,
+		unsigned int         WritebackSourceHeight,
+		unsigned int HTotal);
+
+void dml32_UseMinimumDCFCLK(
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool DRRDisplay[],
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int MaxPrefetchMode,
+		double DRAMClockChangeLatencyFinal,
+		double FCLKChangeLatency,
+		double SREnterPlusExitTime,
+		unsigned int ReturnBusWidth,
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		bool ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealSDPPortBWReceivedAfterUrgLatency,
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		unsigned int DynamicMetadataTransmittedBytes[],
+		unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFClkDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		unsigned int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		/* Output */
+		double DCFCLKState[][2]);
+
+unsigned int dml32_CalculateExtraLatencyBytes(unsigned int ReorderingBytes,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels);
+
+void dml32_CalculateVUpdateAndDynamicMetadataParameters(
+		unsigned int MaxInterDCNTileRepeaters,
+		double Dppclk,
+		double Dispclk,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		unsigned int HTotal,
+		unsigned int VBlank,
+		unsigned int DynamicMetadataTransmittedBytes,
+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		unsigned int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+
+double dml32_CalculateTWait(
+		unsigned int PrefetchMode,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay,
+		double DRAMClockChangeLatency,
+		double FCLKChangeLatency,
+		double UrgentLatency,
+		double SREnterPlusExitTime);
+
+double dml32_get_return_bw_mbps(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const bool HostVMEnable,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed);
+
+double dml32_get_return_bw_mbps_vm_only(const soc_bounding_box_st *soc,
+		const int VoltageLevel,
+		const double DCFCLK,
+		const double FabricClock,
+		const double DRAMSpeed);
+
+double dml32_CalculateExtraLatency(
+		unsigned int RoundTripPingLatencyCycles,
+		unsigned int ReorderingBytes,
+		double DCFCLK,
+		unsigned int TotalNumberOfActiveDPP,
+		unsigned int PixelChunkSizeInKByte,
+		unsigned int TotalNumberOfDCCActiveDPP,
+		unsigned int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int NumberOfDPP[],
+		unsigned int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		unsigned int HostVMMaxNonCachedPageTableLevels);
+
+bool dml32_CalculatePrefetchSchedule(
+		double HostVMInefficiencyFactor,
+		DmlPipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		unsigned int VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		unsigned int VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		unsigned int swath_width_luma_ub,
+		unsigned int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		/* Output */
+		double   *DSTXAfterScaler,
+		double   *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool   *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		unsigned int   *VUpdateOffsetPix,
+		double   *VUpdateWidthPix,
+		double   *VReadyOffsetPix);
+
+void dml32_CalculateFlipSchedule(
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		bool    use_one_row_for_frame_flip,
+
+		/* Output */
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe);
+
+void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
+		bool USRRetrainingRequiredFinal,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActiveSurfaces,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizeTimingsFinal,
+		bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
+		bool DRRDisplay[],
+		unsigned int dpte_group_bytes[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		SOCParametersList mmSOCParameters,
+		unsigned int WritebackChunkSize,
+		double SOCCLK,
+		double DCFClkDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int VTaps[],
+		unsigned int VTapsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		unsigned int VTotal[],
+		unsigned int VActive[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerSurface[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		unsigned int CompressedBufferSizeInkByte,
+
+		/* Output */
+		Watermarks *Watermark,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double MaxActiveDRAMClockChangeLatencySupported[],
+		unsigned int SubViewportLinesNeededInMALL[],
+		enum dm_fclock_change_support *FCLKChangeSupport,
+		double *MinActiveFCLKChangeLatencySupported,
+		bool *USRRetrainingSupport,
+		double ActiveDRAMClockChangeLatencyMargin[]);
+
+double dml32_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		unsigned int   WritebackSourceWidth,
+		unsigned int   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize,
+		double DISPCLKDPPCLKVCOSpeed);
+
+void dml32_CalculateMinAndMaxPrefetchMode(
+		enum dm_prefetch_modes   AllowForPStateChangeOrStutterInVBlankFinal,
+		unsigned int             *MinPrefetchMode,
+		unsigned int             *MaxPrefetchMode);
+
+void dml32_CalculatePixelDeliveryTimes(
+		unsigned int             NumberOfActiveSurfaces,
+		double              VRatio[],
+		double              VRatioChroma[],
+		double              VRatioPrefetchY[],
+		double              VRatioPrefetchC[],
+		unsigned int             swath_width_luma_ub[],
+		unsigned int             swath_width_chroma_ub[],
+		unsigned int             DPPPerSurface[],
+		double              HRatio[],
+		double              HRatioChroma[],
+		double              PixelClock[],
+		double              PSCL_THROUGHPUT[],
+		double              PSCL_THROUGHPUT_CHROMA[],
+		double              Dppclk[],
+		unsigned int             BytePerPixelC[],
+		enum dm_rotation_angle   SourceRotation[],
+		unsigned int             NumberOfCursors[],
+		unsigned int             CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int             CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int             BlockWidth256BytesY[],
+		unsigned int             BlockHeight256BytesY[],
+		unsigned int             BlockWidth256BytesC[],
+		unsigned int             BlockHeight256BytesC[],
+
+		/* Output */
+		double              DisplayPipeLineDeliveryTimeLuma[],
+		double              DisplayPipeLineDeliveryTimeChroma[],
+		double              DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeLuma[],
+		double              DisplayPipeRequestDeliveryTimeChroma[],
+		double              DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double              DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double              CursorRequestDeliveryTime[],
+		double              CursorRequestDeliveryTimePrefetch[]);
+
+void dml32_CalculateMetaAndPTETimes(
+		bool use_one_row_for_frame[],
+		unsigned int NumberOfActiveSurfaces,
+		bool GPUVMEnable,
+		unsigned int MetaChunkSize,
+		unsigned int MinMetaChunkSizeBytes,
+		unsigned int    HTotal[],
+		double  VRatio[],
+		double  VRatioChroma[],
+		double  DestinationLinesToRequestRowInVBlank[],
+		double  DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double  PixelClock[],
+		unsigned int BytePerPixelY[],
+		unsigned int BytePerPixelC[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int dpte_row_height[],
+		unsigned int dpte_row_height_chroma[],
+		unsigned int meta_row_width[],
+		unsigned int meta_row_width_chroma[],
+		unsigned int meta_row_height[],
+		unsigned int meta_row_height_chroma[],
+		unsigned int meta_req_width[],
+		unsigned int meta_req_width_chroma[],
+		unsigned int meta_req_height[],
+		unsigned int meta_req_height_chroma[],
+		unsigned int dpte_group_bytes[],
+		unsigned int    PTERequestSizeY[],
+		unsigned int    PTERequestSizeC[],
+		unsigned int    PixelPTEReqWidthY[],
+		unsigned int    PixelPTEReqHeightY[],
+		unsigned int    PixelPTEReqWidthC[],
+		unsigned int    PixelPTEReqHeightC[],
+		unsigned int    dpte_row_width_luma_ub[],
+		unsigned int    dpte_row_width_chroma_ub[],
+
+		/* Output */
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[]);
+
+void dml32_CalculateVMGroupAndRequestTimes(
+		unsigned int     NumberOfActiveSurfaces,
+		bool     GPUVMEnable,
+		unsigned int     GPUVMMaxPageTableLevels,
+		unsigned int     HTotal[],
+		unsigned int     BytePerPixelC[],
+		double      DestinationLinesToRequestVMInVBlank[],
+		double      DestinationLinesToRequestVMInImmediateFlip[],
+		bool     DCCEnable[],
+		double      PixelClock[],
+		unsigned int        dpte_row_width_luma_ub[],
+		unsigned int        dpte_row_width_chroma_ub[],
+		unsigned int     vm_group_bytes[],
+		unsigned int     dpde0_bytes_per_frame_ub_l[],
+		unsigned int     dpde0_bytes_per_frame_ub_c[],
+		unsigned int        meta_pte_bytes_per_frame_ub_l[],
+		unsigned int        meta_pte_bytes_per_frame_ub_c[],
+
+		/* Output */
+		double      TimePerVMGroupVBlank[],
+		double      TimePerVMGroupFlip[],
+		double      TimePerVMRequestVBlank[],
+		double      TimePerVMRequestFlip[]);
+
+void dml32_CalculateDCCConfiguration(
+		bool             DCCEnabled,
+		bool             DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int             SurfaceWidthLuma,
+		unsigned int             SurfaceWidthChroma,
+		unsigned int             SurfaceHeightLuma,
+		unsigned int             SurfaceHeightChroma,
+		unsigned int                nomDETInKByte,
+		unsigned int             RequestHeight256ByteLuma,
+		unsigned int             RequestHeight256ByteChroma,
+		enum dm_swizzle_mode     TilingFormat,
+		unsigned int             BytePerPixelY,
+		unsigned int             BytePerPixelC,
+		double              BytePerPixelDETY,
+		double              BytePerPixelDETC,
+		enum dm_rotation_angle   SourceRotation,
+		/* Output */
+		unsigned int        *MaxUncompressedBlockLuma,
+		unsigned int        *MaxUncompressedBlockChroma,
+		unsigned int        *MaxCompressedBlockLuma,
+		unsigned int        *MaxCompressedBlockChroma,
+		unsigned int        *IndependentBlockLuma,
+		unsigned int        *IndependentBlockChroma);
+
+void dml32_CalculateStutterEfficiency(
+		unsigned int      CompressedBufferSizeInkByte,
+		enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
+		bool   UnboundedRequestEnabled,
+		unsigned int      MetaFIFOSizeInKEntries,
+		unsigned int      ZeroSizeBufferEntries,
+		unsigned int      PixelChunkSizeInKByte,
+		unsigned int   NumberOfActiveSurfaces,
+		unsigned int      ROBBufferSizeInKByte,
+		double    TotalDataReadBandwidth,
+		double    DCFCLK,
+		double    ReturnBW,
+		unsigned int      CompbufReservedSpace64B,
+		unsigned int      CompbufReservedSpaceZs,
+		double    SRExitTime,
+		double    SRExitZ8Time,
+		bool   SynchronizeTimingsFinal,
+		unsigned int   BlendingAndTiming[],
+		double    StutterEnterPlusExitWatermark,
+		double    Z8StutterEnterPlusExitWatermark,
+		bool   ProgressiveToInterlaceUnitInOPP,
+		bool   Interlace[],
+		double    MinTTUVBlank[],
+		unsigned int   DPPPerSurface[],
+		unsigned int      DETBufferSizeY[],
+		unsigned int   BytePerPixelY[],
+		double    BytePerPixelDETY[],
+		double      SwathWidthY[],
+		unsigned int   SwathHeightY[],
+		unsigned int   SwathHeightC[],
+		double    NetDCCRateLuma[],
+		double    NetDCCRateChroma[],
+		double    DCCFractionOfZeroSizeRequestsLuma[],
+		double    DCCFractionOfZeroSizeRequestsChroma[],
+		unsigned int      HTotal[],
+		unsigned int      VTotal[],
+		double    PixelClock[],
+		double    VRatio[],
+		enum dm_rotation_angle SourceRotation[],
+		unsigned int   BlockHeight256BytesY[],
+		unsigned int   BlockWidth256BytesY[],
+		unsigned int   BlockHeight256BytesC[],
+		unsigned int   BlockWidth256BytesC[],
+		unsigned int   DCCYMaxUncompressedBlock[],
+		unsigned int   DCCCMaxUncompressedBlock[],
+		unsigned int      VActive[],
+		bool   DCCEnable[],
+		bool   WritebackEnable[],
+		double    ReadBandwidthSurfaceLuma[],
+		double    ReadBandwidthSurfaceChroma[],
+		double    meta_row_bw[],
+		double    dpte_row_bw[],
+
+		/* Output */
+		double   *StutterEfficiencyNotIncludingVBlank,
+		double   *StutterEfficiency,
+		unsigned int     *NumberOfStutterBurstsPerFrame,
+		double   *Z8StutterEfficiencyNotIncludingVBlank,
+		double   *Z8StutterEfficiency,
+		unsigned int     *Z8NumberOfStutterBurstsPerFrame,
+		double   *StutterPeriod,
+		bool  *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+
+void dml32_CalculateMaxDETAndMinCompressedBufferSize(
+		unsigned int    ConfigReturnBufferSizeInKByte,
+		unsigned int    ROBBufferSizeInKByte,
+		unsigned int MaxNumDPP,
+		bool nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
+		unsigned int nomDETInKByteOverrideValue,  // VBA_DELTA
+
+		/* Output */
+		unsigned int *MaxTotalDETInKByte,
+		unsigned int *nomDETInKByte,
+		unsigned int *MinCompressedBufferSizeInKByte);
+
+bool dml32_CalculateVActiveBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[]);
+
+void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		bool NotUrgentLatencyHiding[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *PrefetchBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *PrefetchBandwidthSupport);
+
+double dml32_CalculateBandwidthAvailableForImmediateFlip(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double cursor_bw_pre[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[]);
+
+void dml32_CalculateImmediateFlipBandwithSupport(unsigned int NumberOfActiveSurfaces,
+		double ReturnBW,
+		enum immediate_flip_requirement ImmediateFlipRequirement[],
+		double final_flip_bw[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double PrefetchBandwidthLuma[],
+		double PrefetchBandwidthChroma[],
+		double cursor_bw[],
+		double meta_row_bandwidth[],
+		double dpte_row_bandwidth[],
+		double cursor_bw_pre[],
+		double prefetch_vmrow_bw[],
+		unsigned int NumberOfDPP[],
+		double UrgentBurstFactorLuma[],
+		double UrgentBurstFactorChroma[],
+		double UrgentBurstFactorCursor[],
+		double UrgentBurstFactorLumaPre[],
+		double UrgentBurstFactorChromaPre[],
+		double UrgentBurstFactorCursorPre[],
+
+		/* output */
+		double  *TotalBandwidth,
+		double  *FractionOfUrgentBandwidth,
+		bool *ImmediateFlipBandwidthSupport);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
new file mode 100644
index 000000000000..269bdfc4bc40
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
@@ -0,0 +1,616 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "../display_mode_lib.h"
+#include "../display_mode_vba.h"
+#include "../dml_inline_defs.h"
+#include "display_rq_dlg_calc_32.h"
+
+static bool is_dual_plane(enum source_format_class source_format)
+{
+	bool ret_val = 0;
+
+	if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10)
+		|| (source_format == dm_rgbe_alpha))
+		ret_val = 1;
+
+	return ret_val;
+}
+
+void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+    double stored_swath_l_bytes;
+    double stored_swath_c_bytes;
+    bool is_phantom_pipe;
+	uint32_t pixel_chunk_bytes = 0;
+	uint32_t min_pixel_chunk_bytes = 0;
+	uint32_t meta_chunk_bytes = 0;
+	uint32_t min_meta_chunk_bytes = 0;
+	uint32_t dpte_group_bytes = 0;
+	uint32_t mpte_group_bytes = 0;
+
+	uint32_t p1_pixel_chunk_bytes = 0;
+	uint32_t p1_min_pixel_chunk_bytes = 0;
+	uint32_t p1_meta_chunk_bytes = 0;
+	uint32_t p1_min_meta_chunk_bytes = 0;
+	uint32_t p1_dpte_group_bytes = 0;
+	uint32_t p1_mpte_group_bytes = 0;
+
+    unsigned int detile_buf_size_in_bytes;
+    unsigned int detile_buf_plane1_addr;
+    unsigned int pte_row_height_linear;
+
+	memset(rq_regs, 0, sizeof(*rq_regs));
+
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+
+	pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA
+	min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA
+
+	if (pixel_chunk_bytes == 64 * 1024)
+		min_pixel_chunk_bytes = 0;
+
+	meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA
+	min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA
+
+	dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	p1_pixel_chunk_bytes = pixel_chunk_bytes;
+	p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes;
+	p1_meta_chunk_bytes = meta_chunk_bytes;
+	p1_min_meta_chunk_bytes = min_meta_chunk_bytes;
+	p1_dpte_group_bytes = dpte_group_bytes;
+	p1_mpte_group_bytes = mpte_group_bytes;
+
+	if ((enum source_format_class) src->source_format == dm_rgbe_alpha)
+		p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024;
+
+	rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10;
+	rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10;
+
+	if (min_pixel_chunk_bytes == 0)
+		rq_regs->rq_regs_l.min_chunk_size = 0;
+	else
+		rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1;
+
+	if (p1_min_pixel_chunk_bytes == 0)
+		rq_regs->rq_regs_c.min_chunk_size = 0;
+	else
+		rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1;
+
+	rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10;
+	rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10;
+
+	if (min_meta_chunk_bytes == 0)
+		rq_regs->rq_regs_l.min_meta_chunk_size = 0;
+	else
+		rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1;
+
+	if (min_meta_chunk_bytes == 0)
+		rq_regs->rq_regs_c.min_meta_chunk_size = 0;
+	else
+		rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1;
+
+	rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6;
+	rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6;
+	rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6;
+	rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6;
+
+	detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024;
+	detile_buf_plane1_addr = 0;
+	pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+
+	if (src->sw_mode == dm_sw_linear)
+		ASSERT(pte_row_height_linear >= 8);
+
+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3;
+
+	if (dual_plane) {
+		unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx);
+		;
+		if (src->sw_mode == dm_sw_linear)
+			ASSERT(p1_pte_row_height_linear >= 8);
+
+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3;
+	}
+
+	rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx));
+	rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx));
+
+	// FIXME: take the max between luma, chroma chunk size?
+	// okay for now, as we are setting pixel_chunk_bytes to 8kb anyways
+	if (pixel_chunk_bytes >= 32 * 1024 || (dual_plane && p1_pixel_chunk_bytes >= 32 * 1024)) { //32kb
+		rq_regs->drq_expansion_mode = 0;
+	} else {
+		rq_regs->drq_expansion_mode = 2;
+	}
+	rq_regs->prq_expansion_mode = 1;
+	rq_regs->mrq_expansion_mode = 1;
+	rq_regs->crq_expansion_mode = 1;
+
+	stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+	stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx);
+	is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	// Note: detile_buf_plane1_addr is in unit of 1KB
+	if (dual_plane) {
+		if (is_phantom_pipe) {
+			detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma
+		} else {
+			if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) {
+				detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n",
+						__func__, detile_buf_plane1_addr);
+#endif
+			} else {
+				detile_buf_plane1_addr =
+						dml_round_to_multiple(
+								(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
+								1024, 0) / 1024.0; // 2/3 to luma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n",
+						__func__, detile_buf_plane1_addr);
+#endif
+			}
+		}
+	}
+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe);
+	dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes);
+	dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes);
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes);
+	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr);
+	dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address);
+#endif
+	print__rq_regs_st(mode_lib, rq_regs);
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+}
+
+void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
+	double refcyc_per_req_delivery_pre_cur0 = 0.;
+	double refcyc_per_req_delivery_cur0 = 0.;
+	double refcyc_per_req_delivery_pre_c = 0.;
+	double refcyc_per_req_delivery_c = 0.;
+    double refcyc_per_req_delivery_pre_l;
+    double refcyc_per_req_delivery_l;
+	double refcyc_per_line_delivery_pre_c = 0.;
+	double refcyc_per_line_delivery_c = 0.;
+    double refcyc_per_line_delivery_pre_l;
+    double refcyc_per_line_delivery_l;
+    double min_ttu_vblank;
+    double vratio_pre_l;
+    double vratio_pre_c;
+    unsigned int min_dst_y_next_start;
+	unsigned int htotal = dst->htotal;
+	unsigned int hblank_end = dst->hblank_end;
+	unsigned int vblank_end = dst->vblank_end;
+	bool interlaced = dst->interlaced;
+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
+    unsigned int vready_after_vcount0;
+	double refclk_freq_in_mhz = clks->refclk_mhz;
+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
+	bool dual_plane = 0;
+	unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
+    int unsigned dst_x_after_scaler;
+    int unsigned dst_y_after_scaler;
+    double dst_y_prefetch;
+    double dst_y_per_vm_vblank;
+    double dst_y_per_row_vblank;
+    double dst_y_per_vm_flip;
+    double dst_y_per_row_flip;
+    double max_dst_y_per_vm_vblank = 32.0;
+    double max_dst_y_per_row_vblank = 16.0;
+
+    double dst_y_per_pte_row_nom_l;
+    double dst_y_per_pte_row_nom_c;
+    double dst_y_per_meta_row_nom_l;
+    double dst_y_per_meta_row_nom_c;
+    double refcyc_per_pte_group_nom_l;
+    double refcyc_per_pte_group_nom_c;
+    double refcyc_per_pte_group_vblank_l;
+    double refcyc_per_pte_group_vblank_c;
+    double refcyc_per_pte_group_flip_l; 
+    double refcyc_per_pte_group_flip_c; 
+    double refcyc_per_meta_chunk_nom_l;
+    double refcyc_per_meta_chunk_nom_c;
+    double refcyc_per_meta_chunk_vblank_l;
+    double refcyc_per_meta_chunk_vblank_c;
+    double refcyc_per_meta_chunk_flip_l;
+    double refcyc_per_meta_chunk_flip_c;
+
+	memset(dlg_regs, 0, sizeof(*dlg_regs));
+	memset(ttu_regs, 0, sizeof(*ttu_regs));
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] starts, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq   = %3.2f\n", __func__, ref_freq_to_pix_freq);
+	dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced);
+	ASSERT(ref_freq_to_pix_freq < 4.0);
+
+	dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
+	dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
+	dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
+
+	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	dml_print("DML_DLG: %s: min_ttu_vblank (us)    = %3.2f\n", __func__, min_ttu_vblank);
+	dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq   = %3.2f\n", __func__, ref_freq_to_pix_freq);
+
+	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+
+	vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx); // From VBA
+	dlg_regs->vready_after_vcount0 = vready_after_vcount0;
+
+	dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0);
+
+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	// do some adjustment on the dst_after scaler to account for odm combine mode
+	dml_print("DML_DLG: %s: input dst_x_after_scaler   = %d\n", __func__, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: input dst_y_after_scaler   = %d\n", __func__, dst_y_after_scaler);
+
+	// need to figure out which side of odm combine we're in
+	if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
+		// figure out which pipes go together
+		bool visited[DC__NUM_PIPES__MAX];
+		unsigned int i, j, k;
+
+		for (k = 0; k < num_pipes; ++k) {
+			visited[k] = false;
+			pipe_index_in_combine[k] = 0;
+		}
+
+		for (i = 0; i < num_pipes; i++) {
+			if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
+
+				unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
+				unsigned int grp_idx = 0;
+
+				for (j = i; j < num_pipes; j++) {
+					if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp
+						&& e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
+						pipe_index_in_combine[j] = grp_idx;
+						dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n",
+								__func__, j, grp, grp_idx);
+						grp_idx++;
+						visited[j] = true;
+					}
+				}
+			}
+		}
+	}
+
+	if (dst->odm_combine == dm_odm_combine_mode_disabled) {
+		// FIXME how about ODM split??
+		dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
+	} else {
+		if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
+			// TODO: We should really check that 4to1 is supported before setting it to 4
+			unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4);
+			unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
+
+			dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end
+				+ odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
+		}
+	}
+	ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
+
+	dml_print("DML_DLG: %s: htotal= %d\n", __func__, htotal);
+	dml_print("DML_DLG: %s: dst_x_after_scaler[%d]= %d\n", __func__, pipe_idx, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler);
+
+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	// From VBA
+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);  // From VBA
+
+	// magic!
+	if (htotal <= 75) {
+		max_dst_y_per_vm_vblank = 100.0;
+		max_dst_y_per_row_vblank = 100.0;
+	}
+
+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
+	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
+
+	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
+	ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
+
+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+
+	dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
+	dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
+
+	// Active
+	refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;   // From VBA
+	refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;       // From VBA
+
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n", __func__, refcyc_per_line_delivery_l);
+
+	if (dual_plane) {
+		refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+		refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
+				__func__, refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
+				__func__, refcyc_per_line_delivery_c);
+	}
+
+	if (src->dynamic_metadata_enable && src->gpuvm)
+		dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)
+		* refclk_freq_in_mhz; // From VBA
+
+	refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+	refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;     // From VBA
+
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n", __func__, refcyc_per_req_delivery_l);
+
+	if (dual_plane) {
+		refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+				pipe_idx) * refclk_freq_in_mhz;      // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
+				__func__, refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n", __func__, refcyc_per_req_delivery_c);
+	}
+
+	// TTU - Cursor
+	ASSERT(src->num_cursors <= 1);
+	if (src->num_cursors > 0) {
+		refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib,
+				e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param,
+				num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n",
+				__func__, refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0     = %3.2f\n",
+				__func__, refcyc_per_req_delivery_cur0);
+	}
+
+	// Assign to register structures
+	dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2);
+	ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
+
+	dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
+	dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
+	dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
+	dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
+	dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
+	dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
+	dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
+
+	dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
+	dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
+
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_row_vblank);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip);
+
+	dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;               // From VBA
+	dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;                 // From VBA
+	dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);                 // From VBA
+	dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);  // From VBA
+
+	// From VBA
+	dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_pte_row_nom_c = get_dst_y_per_pte_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_meta_row_nom_l = get_dst_y_per_meta_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+	// From VBA
+	dst_y_per_meta_row_nom_c = get_dst_y_per_meta_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
+
+	refcyc_per_pte_group_nom_l = get_refcyc_per_pte_group_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;         // From VBA
+	refcyc_per_pte_group_nom_c = get_refcyc_per_pte_group_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;         // From VBA
+	refcyc_per_pte_group_vblank_l = get_refcyc_per_pte_group_vblank_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+	refcyc_per_pte_group_vblank_c = get_refcyc_per_pte_group_vblank_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;      // From VBA
+	refcyc_per_pte_group_flip_l = get_refcyc_per_pte_group_flip_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_pte_group_flip_c = get_refcyc_per_pte_group_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+
+	refcyc_per_meta_chunk_nom_l = get_refcyc_per_meta_chunk_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_meta_chunk_nom_c = get_refcyc_per_meta_chunk_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes,
+			pipe_idx) * refclk_freq_in_mhz;        // From VBA
+	refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+	refcyc_per_meta_chunk_vblank_c = get_refcyc_per_meta_chunk_vblank_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;     // From VBA
+	refcyc_per_meta_chunk_flip_l = get_refcyc_per_meta_chunk_flip_l_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;       // From VBA
+	refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param,
+			num_pipes, pipe_idx) * refclk_freq_in_mhz;       // From VBA
+
+	dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2);
+	dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2);
+	dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2);
+	dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2);
+	dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l;
+	dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c;
+	dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l;
+	dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c;
+	dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l;
+	dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c;
+	dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l;
+	dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c;
+	dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l;
+	dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c;
+	dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l;
+	dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c;
+	dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
+	dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
+	dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
+	dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
+
+	dlg_regs->chunk_hdl_adjust_cur0 = 3;
+	dlg_regs->dst_y_offset_cur0 = 0;
+	dlg_regs->chunk_hdl_adjust_cur1 = 3;
+	dlg_regs->dst_y_offset_cur1 = 0;
+
+	dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
+
+	ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_cur0 =
+			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
+	ttu_regs->refcyc_per_req_delivery_pre_cur1 = 0;
+	ttu_regs->refcyc_per_req_delivery_cur1 = 0;
+	ttu_regs->qos_level_low_wm = 0;
+
+	ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
+
+	ttu_regs->qos_level_flip = 14;
+	ttu_regs->qos_level_fixed_l = 8;
+	ttu_regs->qos_level_fixed_c = 8;
+	ttu_regs->qos_level_fixed_cur0 = 8;
+	ttu_regs->qos_ramp_disable_l = 0;
+	ttu_regs->qos_ramp_disable_c = 0;
+	ttu_regs->qos_ramp_disable_cur0 = 0;
+	ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
+
+	// CHECK for HW registers' range, assert or clamp
+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
+	ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
+	if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
+
+	if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
+
+	ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8);
+	ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
+	if (dual_plane) {
+		if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
+			// FIXME what so special about chroma, can we just assert?
+			dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n",
+					__func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1);
+		}
+	}
+	ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
+	ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
+
+	if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
+	if (dual_plane) {
+		if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
+			dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
+	}
+	ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
+	if (dual_plane) {
+		ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
+	}
+
+	if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
+		dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
+	if (dual_plane) {
+		if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
+			dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
+	}
+	ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
+	ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14));
+	ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));
+	ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24));
+
+	print__ttu_regs_st(mode_lib, ttu_regs);
+	print__dlg_regs_st(mode_lib, dlg_regs);
+	dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
new file mode 100644
index 000000000000..ebee365293cd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__
+#define __DML32_DISPLAY_RQ_DLG_CALC_H__
+
+#include "../display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+/*
+* Function: dml_rq_dlg_get_rq_reg
+*  Main entry point for test to get the register values out of this DML class.
+*  This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
+*  and then populate the rq_regs struct
+* Input:
+*  pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
+* Output:
+*  rq_regs - struct that holds all the RQ registers field value.
+*            See also: <display_rq_regs_st>
+*/
+void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx);
+
+/*
+* Function: dml_rq_dlg_get_dlg_reg
+*   Calculate and return DLG and TTU register struct given the system setting
+* Output:
+*  dlg_regs - output DLG register struct
+*  ttu_regs - output DLG TTU register struct
+* Input:
+*  e2e_pipe_param - "compacted" array of e2e pipe param struct
+*  num_pipes - num of active "pipe" or "route"
+*  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+*  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+*           Added for legacy or unrealistic timing tests.
+*/
+void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index edb9f7567d6d..f394b3f3922a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -26,7 +26,11 @@
 #define __DISPLAY_MODE_ENUMS_H__
 
 enum output_encoder_class {
-	dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
+	dm_dp = 0,
+	dm_hdmi = 1,
+	dm_wb = 2,
+	dm_edp = 3,
+	dm_dp2p0 = 5,
 };
 enum output_format_class {
 	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
@@ -105,6 +109,10 @@ enum clock_change_support {
 	dm_dram_clock_change_uninitialized = 0,
 	dm_dram_clock_change_vactive,
 	dm_dram_clock_change_vblank,
+	dm_dram_clock_change_vactive_w_mall_full_frame,
+	dm_dram_clock_change_vactive_w_mall_sub_vp,
+	dm_dram_clock_change_vblank_w_mall_full_frame,
+	dm_dram_clock_change_vblank_w_mall_sub_vp,
 	dm_dram_clock_change_unsupported
 };
 
@@ -169,6 +177,9 @@ enum odm_combine_mode {
 	dm_odm_combine_mode_disabled,
 	dm_odm_combine_mode_2to1,
 	dm_odm_combine_mode_4to1,
+	dm_odm_split_mode_1to2,
+	dm_odm_mode_mso_1to2,
+	dm_odm_mode_mso_1to4
 };
 
 enum odm_combine_policy {
@@ -176,11 +187,15 @@ enum odm_combine_policy {
 	dm_odm_combine_policy_none,
 	dm_odm_combine_policy_2to1,
 	dm_odm_combine_policy_4to1,
+	dm_odm_split_policy_1to2,
+	dm_odm_mso_policy_1to2,
+	dm_odm_mso_policy_1to4,
 };
 
 enum immediate_flip_requirement {
 	dm_immediate_flip_not_required,
 	dm_immediate_flip_required,
+	dm_immediate_flip_opportunistic,
 };
 
 enum unbounded_requesting_policy {
@@ -189,4 +204,75 @@ enum unbounded_requesting_policy {
 	dm_unbounded_requesting_disable
 };
 
+enum dm_rotation_angle {
+	dm_rotation_0,
+	dm_rotation_90,
+	dm_rotation_180,
+	dm_rotation_270,
+	dm_rotation_0m,
+	dm_rotation_90m,
+	dm_rotation_180m,
+	dm_rotation_270m,
+};
+
+enum dm_use_mall_for_pstate_change_mode {
+	dm_use_mall_pstate_change_disable,
+	dm_use_mall_pstate_change_full_frame,
+	dm_use_mall_pstate_change_sub_viewport,
+	dm_use_mall_pstate_change_phantom_pipe
+};
+
+enum dm_use_mall_for_static_screen_mode {
+	dm_use_mall_static_screen_disable,
+	dm_use_mall_static_screen_optimize,
+	dm_use_mall_static_screen_enable,
+};
+
+enum dm_output_link_dp_rate {
+	dm_dp_rate_na,
+	dm_dp_rate_hbr,
+	dm_dp_rate_hbr2,
+	dm_dp_rate_hbr3,
+	dm_dp_rate_uhbr10,
+	dm_dp_rate_uhbr13p5,
+	dm_dp_rate_uhbr20,
+};
+
+enum dm_fclock_change_support {
+	dm_fclock_change_vactive,
+	dm_fclock_change_vblank,
+	dm_fclock_change_unsupported,
+};
+
+enum dm_prefetch_modes {
+	dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
+	dm_prefetch_support_uclk_fclk_and_stutter,
+	dm_prefetch_support_fclk_and_stutter,
+	dm_prefetch_support_stutter,
+	dm_prefetch_support_none,
+};
+enum dm_output_type {
+	dm_output_type_unknown,
+	dm_output_type_dp,
+	dm_output_type_edp,
+	dm_output_type_dp2p0,
+	dm_output_type_hdmi,
+	dm_output_type_hdmifrl,
+};
+
+enum dm_output_rate {
+	dm_output_rate_unknown,
+	dm_output_rate_dp_rate_hbr,
+	dm_output_rate_dp_rate_hbr2,
+	dm_output_rate_dp_rate_hbr3,
+	dm_output_rate_dp_rate_uhbr10,
+	dm_output_rate_dp_rate_uhbr13p5,
+	dm_output_rate_dp_rate_uhbr20,
+	dm_output_rate_hdmi_rate_3x3,
+	dm_output_rate_hdmi_rate_6x3,
+	dm_output_rate_hdmi_rate_6x4,
+	dm_output_rate_hdmi_rate_8x4,
+	dm_output_rate_hdmi_rate_10x4,
+	dm_output_rate_hdmi_rate_12x4,
+};
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 30db51fbd8cd..5d27ff0ebb5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -35,6 +35,8 @@
 #include "dcn30/display_rq_dlg_calc_30.h"
 #include "dcn31/display_mode_vba_31.h"
 #include "dcn31/display_rq_dlg_calc_31.h"
+#include "dcn32/display_mode_vba_32.h"
+#include "dcn32/display_rq_dlg_calc_32.h"
 #include "dml_logger.h"
 
 const struct dml_funcs dml20_funcs = {
@@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = {
 	.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
 };
 
+const struct dml_funcs dml32_funcs = {
+	.validate = dml32_ModeSupportAndSystemConfigurationFull,
+    .recalculate = dml32_recalculate,
+	.rq_dlg_get_dlg_reg_v2 = dml32_rq_dlg_get_dlg_reg,
+	.rq_dlg_get_rq_reg_v2 = dml32_rq_dlg_get_rq_reg
+};
+
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
 		const struct _vcs_dpi_ip_params_st *ip_params,
@@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib,
 	case DML_PROJECT_DCN31_FPGA:
 		lib->funcs = dml31_funcs;
 		break;
+	case DML_PROJECT_DCN32:
+		lib->funcs = dml32_funcs;
+		break;
 
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index d76251fd1566..2bdd6ed22611 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -41,6 +41,7 @@ enum dml_project {
 	DML_PROJECT_DCN30,
 	DML_PROJECT_DCN31,
 	DML_PROJECT_DCN31_FPGA,
+	DML_PROJECT_DCN32,
 };
 
 struct display_mode_lib;
@@ -62,6 +63,20 @@ struct dml_funcs {
 		struct display_mode_lib *mode_lib,
 		display_rq_regs_st *rq_regs,
 		const display_pipe_params_st *pipe_param);
+	// DLG interfaces have different function parameters in DCN32.
+	// Create new function pointers to address the changes
+	void (*rq_dlg_get_dlg_reg_v2)(
+			struct display_mode_lib *mode_lib,
+			display_dlg_regs_st *dlg_regs,
+			display_ttu_regs_st *ttu_regs,
+			display_e2e_pipe_params_st *e2e_pipe_param,
+			const unsigned int num_pipes,
+			const unsigned int pipe_idx);
+	void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
+			struct display_mode_lib *mode_lib,
+			const display_e2e_pipe_params_st *e2e_pipe_param,
+			const unsigned int num_pipes,
+			const unsigned int pipe_idx);
 	void (*recalculate)(struct display_mode_lib *mode_lib);
 	void (*validate)(struct display_mode_lib *mode_lib);
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 2df660cd8801..2bdf60846762 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
 
+typedef struct {
+	double UrgentWatermark;
+	double WritebackUrgentWatermark;
+	double DRAMClockChangeWatermark;
+	double FCLKChangeWatermark;
+	double WritebackDRAMClockChangeWatermark;
+	double WritebackFCLKChangeWatermark;
+	double StutterExitWatermark;
+	double StutterEnterPlusExitWatermark;
+	double Z8StutterExitWatermark;
+	double Z8StutterEnterPlusExitWatermark;
+	double USRRetrainingWatermark;
+} Watermarks;
+
+typedef struct {
+	double UrgentLatency;
+	double ExtraLatency;
+	double WritebackLatency;
+	double DRAMClockChangeLatency;
+	double FCLKChangeLatency;
+	double SRExitTime;
+	double SREnterPlusExitTime;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double USRRetrainingLatencyPlusSMNLatency;
+} Latencies;
+
+typedef struct {
+	double Dppclk;
+	double Dispclk;
+	double PixelClock;
+	double DCFClkDeepSleep;
+	unsigned int DPPPerSurface;
+	bool ScalerEnabled;
+	enum dm_rotation_angle SourceRotation;
+	unsigned int ViewportHeight;
+	unsigned int ViewportHeightChroma;
+	unsigned int BlockWidth256BytesY;
+	unsigned int BlockHeight256BytesY;
+	unsigned int BlockWidth256BytesC;
+	unsigned int BlockHeight256BytesC;
+	unsigned int BlockWidthY;
+	unsigned int BlockHeightY;
+	unsigned int BlockWidthC;
+	unsigned int BlockHeightC;
+	unsigned int InterlaceEnable;
+	unsigned int NumberOfCursors;
+	unsigned int VBlank;
+	unsigned int HTotal;
+	unsigned int HActive;
+	bool DCCEnable;
+	enum odm_combine_mode ODMMode;
+	enum source_format_class SourcePixelFormat;
+	enum dm_swizzle_mode SurfaceTiling;
+	unsigned int BytePerPixelY;
+	unsigned int BytePerPixelC;
+	bool ProgressiveToInterlaceUnitInOPP;
+	double VRatio;
+	double VRatioChroma;
+	unsigned int VTaps;
+	unsigned int VTapsChroma;
+	unsigned int PitchY;
+	unsigned int DCCMetaPitchY;
+	unsigned int PitchC;
+	unsigned int DCCMetaPitchC;
+	bool ViewportStationary;
+	unsigned int ViewportXStart;
+	unsigned int ViewportYStart;
+	unsigned int ViewportXStartC;
+	unsigned int ViewportYStartC;
+	bool FORCE_ONE_ROW_FOR_FRAME;
+	unsigned int SwathHeightY;
+	unsigned int SwathHeightC;
+} DmlPipe;
+
+typedef struct {
+	double UrgentLatency;
+	double ExtraLatency;
+	double WritebackLatency;
+	double DRAMClockChangeLatency;
+	double FCLKChangeLatency;
+	double SRExitTime;
+	double SREnterPlusExitTime;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double USRRetrainingLatency;
+	double SMNLatency;
+} SOCParametersList;
+
 struct _vcs_dpi_voltage_scaling_st {
 	int state;
 	double dscclk_mhz;
 	double dcfclk_mhz;
 	double socclk_mhz;
 	double phyclk_d18_mhz;
+	double phyclk_d32_mhz;
 	double dram_speed_mts;
 	double fabricclk_mhz;
 	double dispclk_mhz;
@@ -71,6 +161,11 @@ struct _vcs_dpi_voltage_scaling_st {
 
 struct _vcs_dpi_soc_bounding_box_st {
 	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+	/*
+	 * This is a temporary stash for updating @clock_limits with the PMFW
+	 * clock table. Do not use outside of *update_bw_boudning_box functions.
+	 */
+	struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES];
 	unsigned int num_states;
 	double sr_exit_time_us;
 	double sr_enter_plus_exit_time_us;
@@ -80,6 +175,15 @@ struct _vcs_dpi_soc_bounding_box_st {
 	double urgent_latency_pixel_data_only_us;
 	double urgent_latency_pixel_mixed_with_vm_data_us;
 	double urgent_latency_vm_data_only_us;
+	double usr_retraining_latency_us;
+	double smn_latency_us;
+	double fclk_change_latency_us;
+	double mall_allocated_for_dcn_mbytes;
+	double pct_ideal_fabric_bw_after_urgent;
+	double pct_ideal_dram_bw_after_urgent_strobe;
+	double max_avg_fabric_bw_use_normal_percent;
+	double max_avg_dram_bw_use_normal_strobe_percent;
+	enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
 	double writeback_latency_us;
 	double ideal_dram_bw_after_urgent_percent;
 	double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
@@ -148,6 +252,9 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int dpp_output_buffer_pixels;
 	unsigned int opp_output_buffer_lines;
 	unsigned int pixel_chunk_size_kbytes;
+	unsigned int alpha_pixel_chunk_size_kbytes;
+	unsigned int min_pixel_chunk_size_bytes;
+	unsigned int dcc_meta_buffer_size_bytes;
 	unsigned char pte_enable;
 	unsigned int pte_chunk_size_kbytes;
 	unsigned int meta_chunk_size_kbytes;
@@ -168,6 +275,7 @@ struct _vcs_dpi_ip_params_st {
 	double writeback_min_hscl_ratio;
 	double writeback_min_vscl_ratio;
 	unsigned int maximum_dsc_bits_per_component;
+	unsigned int maximum_pixels_per_line_per_dsc_unit;
 	unsigned int writeback_max_hscl_taps;
 	unsigned int writeback_max_vscl_taps;
 	unsigned int writeback_line_buffer_luma_buffer_size;
@@ -224,6 +332,9 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 	unsigned int bug_forcing_LC_req_same_size_fixed;
 	unsigned int number_of_cursors;
+	unsigned int max_num_dp2p0_outputs;
+	unsigned int max_num_dp2p0_streams;
+	unsigned int VBlankNomDefaultUS;
 };
 
 struct _vcs_dpi_display_xfc_params_st {
@@ -250,6 +361,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	bool hostvm_levels_force_en;
 	unsigned int hostvm_levels_force;
 	int source_scan;
+	int source_rotation; // new in dml32
 	int sw_mode;
 	int macro_tile_size;
 	unsigned int surface_width_y;
@@ -264,6 +376,15 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	unsigned int viewport_height_c;
 	unsigned int viewport_width_max;
 	unsigned int viewport_height_max;
+	unsigned int viewport_x_y;
+	unsigned int viewport_x_c;
+	bool viewport_stationary;
+	unsigned int dcc_rate_luma;
+	unsigned int gpuvm_min_page_size_kbytes;
+	unsigned int use_mall_for_pstate_change;
+	unsigned int use_mall_for_static_screen;
+	bool force_one_row_for_frame;
+	bool pte_buffer_mode;
 	unsigned int data_pitch;
 	unsigned int data_pitch_c;
 	unsigned int meta_pitch;
@@ -296,10 +417,17 @@ struct writeback_st {
 	int wb_vtaps_luma;
 	int wb_htaps_chroma;
 	int wb_vtaps_chroma;
+	unsigned int wb_htaps;
+	unsigned int wb_vtaps;
 	double wb_hratio;
 	double wb_vratio;
 };
 
+struct display_audio_params_st {
+	unsigned int   audio_sample_rate_khz;
+	int    		   audio_sample_layout;
+};
+
 struct _vcs_dpi_display_output_params_st {
 	int dp_lanes;
 	double output_bpp;
@@ -313,6 +441,11 @@ struct _vcs_dpi_display_output_params_st {
 	int dsc_slices;
 	int max_audio_sample_rate;
 	struct writeback_st wb;
+	struct display_audio_params_st audio;
+	unsigned int output_bpc;
+	int dp_rate;
+	unsigned int dp_multistream_id;
+	bool dp_multistream_en;
 };
 
 struct _vcs_dpi_scaler_ratio_depth_st {
@@ -361,6 +494,8 @@ struct _vcs_dpi_display_pipe_dest_params_st {
 	unsigned char use_maximum_vstartup;
 	unsigned int vtotal_max;
 	unsigned int vtotal_min;
+	unsigned int refresh_rate;
+	bool synchronize_timings;
 };
 
 struct _vcs_dpi_display_pipe_params_st {
@@ -558,6 +693,9 @@ struct _vcs_dpi_display_arb_params_st {
 	int max_req_outstanding;
 	int min_req_outstanding;
 	int sat_level_us;
+	int hvm_min_req_outstand_commit_threshold;
+	int hvm_max_qos_commit_threshold;
+	int compbuf_reserved_space_kbytes;
 };
 
 #endif /*__DISPLAY_MODE_STRUCTS_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index c0740dbdcc2e..2676710a5f2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -110,6 +110,15 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
 dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
 dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth);
 dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
+dml_get_attr_func(cstate_max_cap_mode, mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
+dml_get_attr_func(comp_buffer_size_kbytes, mode_lib->vba.CompressedBufferSizeInkByte);
+dml_get_attr_func(pixel_chunk_size_in_kbyte, mode_lib->vba.PixelChunkSizeInKByte);
+dml_get_attr_func(alpha_pixel_chunk_size_in_kbyte, mode_lib->vba.AlphaPixelChunkSizeInKByte);
+dml_get_attr_func(meta_chunk_size_in_kbyte, mode_lib->vba.MetaChunkSize);
+dml_get_attr_func(min_pixel_chunk_size_in_byte, mode_lib->vba.MinPixelChunkSizeBytes);
+dml_get_attr_func(min_meta_chunk_size_in_byte, mode_lib->vba.MinMetaChunkSizeBytes);
+dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
+dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark);
 
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
 {\
@@ -165,6 +174,27 @@ dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
 dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
 dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
+dml_get_pipe_attr_func(dst_y_per_pte_row_nom_l, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_L);
+dml_get_pipe_attr_func(dst_y_per_pte_row_nom_c, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_C);
+dml_get_pipe_attr_func(dst_y_per_meta_row_nom_l, mode_lib->vba.DST_Y_PER_META_ROW_NOM_L);
+dml_get_pipe_attr_func(dst_y_per_meta_row_nom_c, mode_lib->vba.DST_Y_PER_META_ROW_NOM_C);
+dml_get_pipe_attr_func(refcyc_per_pte_group_nom_l_in_us, mode_lib->vba.time_per_pte_group_nom_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_nom_c_in_us, mode_lib->vba.time_per_pte_group_nom_chroma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_l_in_us, mode_lib->vba.time_per_pte_group_vblank_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_c_in_us, mode_lib->vba.time_per_pte_group_vblank_chroma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_flip_l_in_us, mode_lib->vba.time_per_pte_group_flip_luma);
+dml_get_pipe_attr_func(refcyc_per_pte_group_flip_c_in_us, mode_lib->vba.time_per_pte_group_flip_chroma);
+dml_get_pipe_attr_func(vstartup_calculated, mode_lib->vba.VStartup);
+dml_get_pipe_attr_func(dpte_row_height_linear_c, mode_lib->vba.dpte_row_height_linear_chroma);
+dml_get_pipe_attr_func(swath_height_l, mode_lib->vba.SwathHeightY);
+dml_get_pipe_attr_func(swath_height_c, mode_lib->vba.SwathHeightC);
+dml_get_pipe_attr_func(det_stored_buffer_size_l_bytes, mode_lib->vba.DETBufferSizeY);
+dml_get_pipe_attr_func(det_stored_buffer_size_c_bytes, mode_lib->vba.DETBufferSizeC);
+dml_get_pipe_attr_func(dpte_group_size_in_bytes, mode_lib->vba.dpte_group_bytes);
+dml_get_pipe_attr_func(vm_group_size_in_bytes, mode_lib->vba.vm_group_bytes);
+dml_get_pipe_attr_func(dpte_row_height_linear_l, mode_lib->vba.dpte_row_height_linear);
+dml_get_pipe_attr_func(pte_buffer_mode, mode_lib->vba.PTE_BUFFER_MODE);
+dml_get_pipe_attr_func(subviewport_lines_needed_in_mall, mode_lib->vba.SubViewportLinesNeededInMALL);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -202,6 +232,67 @@ double get_total_prefetch_bw(
 	return total_prefetch_bw;
 }
 
+unsigned int get_total_surface_size_in_mall_bytes(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes)
+{
+	unsigned int k;
+	unsigned int size = 0.0;
+	recalculate_params(mode_lib, pipes, num_pipes);
+	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
+		size += mode_lib->vba.SurfaceSizeInMALL[k];
+	return size;
+}
+
+unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx)
+{
+	int pipe_idx = -1;
+	int i;
+
+	ASSERT(plane_idx < DC__NUM_DPP__MAX);
+
+	for (i = 0; i < DC__NUM_DPP__MAX ; i++) {
+		if (plane_idx == mode_lib->vba.pipe_plane[i]) {
+			pipe_idx = i;
+			break;
+		}
+	}
+	ASSERT(pipe_idx >= 0);
+
+	return pipe_idx;
+}
+
+
+double get_det_buffer_size_kbytes(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes, unsigned int pipe_idx)
+{
+	unsigned int plane_idx;
+	double det_buf_size_kbytes;
+
+	recalculate_params(mode_lib, pipes, num_pipes);
+	plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
+
+	dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plane_idx);
+	det_buf_size_kbytes = mode_lib->vba.DETBufferSizeInKByte[plane_idx]; // per hubp DET buffer size
+
+	dml_print("DML::%s: det_buf_size_kbytes=%3.2f\n", __func__, det_buf_size_kbytes);
+
+	return det_buf_size_kbytes;
+}
+
+bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes, unsigned int pipe_idx)
+{
+	unsigned int plane_idx;
+
+	recalculate_params(mode_lib, pipes, num_pipes);
+	plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
+	dml_print("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx,
+			mode_lib->vba.UsesMALLForPStateChange[plane_idx]);
+	return (mode_lib->vba.UsesMALLForPStateChange[plane_idx] == dm_use_mall_pstate_change_phantom_pipe);
+}
+
 static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 {
 	soc_bounding_box_st *soc = &mode_lib->vba.soc;
@@ -241,6 +332,22 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 			soc->max_avg_sdp_bw_use_normal_percent;
 	mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
 	mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
+	mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us;
+	mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us;
+	mode_lib->vba.SMNLatency = soc->smn_latency_us;
+	mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes;
+
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe;
+	mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation =
+			soc->max_avg_fabric_bw_use_normal_percent;
+	mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE =
+			soc->max_avg_dram_bw_use_normal_strobe_percent;
+
+	mode_lib->vba.DRAMClockChangeRequirementFinal = 1;
+	mode_lib->vba.FCLKChangeRequirementFinal = 1;
+	mode_lib->vba.USRRetrainingRequiredFinal = 1;
+	mode_lib->vba.ConfigurableDETSizeEnFinal = 0;
+	mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal = soc->allow_for_pstate_or_stutter_in_vblank_final;
 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
 	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
 	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
@@ -283,6 +390,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
 		mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
 		mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz;
+		mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz;
 		mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz;
 		mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz;
 		mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts;
@@ -325,6 +433,18 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
 	mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
 	mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
+    /* In DCN3.2, nomDETInKByte should be initialized correctly. */
+	mode_lib->vba.nomDETInKByte = ip->det_buffer_size_kbytes;
+	mode_lib->vba.CompbufReservedSpace64B  = ip->compbuf_reserved_space_64b;
+	mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs;
+	mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = ip->compressed_buffer_segment_size_in_kbytes;
+	mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits;
+	mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes; // not ysed
+	mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; // not used
+	mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = ip->maximum_pixels_per_line_per_dsc_unit;
+	mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs;
+	mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams;
+	mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes;
 
 	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
 	mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
@@ -399,6 +519,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		visited[k] = false;
 
 	mode_lib->vba.NumberOfActivePlanes = 0;
+	mode_lib->vba.NumberOfActiveSurfaces = 0;
 	mode_lib->vba.ImmediateFlipSupport = false;
 	for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {
 		display_pipe_source_params_st *src = &pipes[j].pipe.src;
@@ -429,6 +550,21 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 				src->viewport_y_y;
 		mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] =
 				src->viewport_y_c;
+		mode_lib->vba.SourceRotation[mode_lib->vba.NumberOfActiveSurfaces] = src->source_rotation;
+		mode_lib->vba.ViewportXStartY[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_y;
+		mode_lib->vba.ViewportXStartC[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_c;
+		// TODO: Assign correct value to viewport_stationary
+		mode_lib->vba.ViewportStationary[mode_lib->vba.NumberOfActivePlanes] =
+				src->viewport_stationary;
+		mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_pstate_change;
+		mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_static_screen;
+		mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = src->gpuvm_min_page_size_kbytes;
+		mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = dst->refresh_rate; //todo remove this
+		mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate;
+		mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = dst->odm_combine;
+		//TODO: Need to assign correct values to dp_multistream vars
+		mode_lib->vba.OutputMultistreamEn[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_en;
+		mode_lib->vba.OutputMultistreamId[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_id;
 		mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
 		mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->surface_width_y;
 		mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->surface_height_y;
@@ -677,6 +813,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 
 		mode_lib->vba.NumberOfActivePlanes++;
+		mode_lib->vba.NumberOfActiveSurfaces++;
 	}
 
 	// handle overlays through BlendingAndTiming
@@ -702,6 +839,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 	}
 
+	mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings;
+	mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
 	mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
 	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
 		if (pipes[k].pipe.src.unbounded_req_mode == 0)
@@ -745,6 +884,32 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 
 	mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable && !!ip->gpuvm_enable;
 	mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && !!ip->hostvm_enable;
+
+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
+		mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;
+		mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;
+
+		if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) {
+			if (mode_lib->vba.ForceOneRowForFrame[k] ||
+				(mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) ||
+				(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) ||
+				(mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: ERROR: Invalid PteBufferMode=%d for plane %0d!\n",
+						__func__, mode_lib->vba.PteBufferMode[k], k);
+				dml_print("DML::%s:  -  ForceOneRowForFrame     = %d\n",
+						__func__, mode_lib->vba.ForceOneRowForFrame[k]);
+				dml_print("DML::%s:  -  GPUVMMinPageSizeKBytes  = %d\n",
+						__func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]);
+				dml_print("DML::%s:  -  UseMALLForPStateChange  = %d\n",
+						__func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]);
+				dml_print("DML::%s:  -  UseMALLForStaticScreen  = %d\n",
+						__func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]);
+#endif
+				ASSERT(0);
+			}
+		}
+	}
 }
 
 /**
@@ -896,6 +1061,7 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
 	soc_bounding_box_st *soc = &mode_lib->vba.soc;
 	unsigned int k;
 	unsigned int total_pipes = 0;
+	unsigned int pipe_idx = 0;
 
 	mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
 	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
@@ -917,6 +1083,11 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
 	// Total Available Pipes Support Check
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		total_pipes += mode_lib->vba.DPPPerPlane[k];
+		pipe_idx = get_pipe_idx(mode_lib, k);
+		if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0)
+			mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
+		else
+			mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
 	}
 	ASSERT(total_pipes <= DC__NUM_DPP__MAX);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 0603b32971a6..10ff536ef2a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -58,6 +58,15 @@ dml_get_attr_decl(return_bw);
 dml_get_attr_decl(tcalc);
 dml_get_attr_decl(fraction_of_urgent_bandwidth);
 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
+dml_get_attr_decl(cstate_max_cap_mode);
+dml_get_attr_decl(comp_buffer_size_kbytes);
+dml_get_attr_decl(pixel_chunk_size_in_kbyte);
+dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
+dml_get_attr_decl(meta_chunk_size_in_kbyte);
+dml_get_attr_decl(min_pixel_chunk_size_in_byte);
+dml_get_attr_decl(min_meta_chunk_size_in_byte);
+dml_get_attr_decl(fclk_watermark);
+dml_get_attr_decl(usr_retraining_watermark);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
 
@@ -75,6 +84,26 @@ dml_get_pipe_attr_decl(dst_y_per_row_vblank);
 dml_get_pipe_attr_decl(dst_y_prefetch);
 dml_get_pipe_attr_decl(dst_y_per_vm_flip);
 dml_get_pipe_attr_decl(dst_y_per_row_flip);
+dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
+dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
+dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
+dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
+dml_get_pipe_attr_decl(dpte_row_height_linear_c);
+dml_get_pipe_attr_decl(swath_height_l);
+dml_get_pipe_attr_decl(swath_height_c);
+dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
+dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
+dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
+dml_get_pipe_attr_decl(vm_group_size_in_bytes);
+dml_get_pipe_attr_decl(det_buffer_size_kbytes);
+dml_get_pipe_attr_decl(dpte_row_height_linear_l);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
+dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
+dml_get_pipe_attr_decl(pte_buffer_mode);
 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
@@ -108,6 +137,8 @@ dml_get_pipe_attr_decl(vupdate_width);
 dml_get_pipe_attr_decl(vready_offset);
 dml_get_pipe_attr_decl(vready_at_or_after_vsync);
 dml_get_pipe_attr_decl(min_dst_y_next_start);
+dml_get_pipe_attr_decl(vstartup_calculated);
+dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -126,6 +157,16 @@ unsigned int dml_get_voltage_level(
 		const display_e2e_pipe_params_st *pipes,
 		unsigned int num_pipes);
 
+unsigned int get_total_surface_size_in_mall_bytes(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx);
+
+bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes,
+		unsigned int pipe_idx);
 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
 
 bool Calculate256BBlockSizes(
@@ -138,6 +179,43 @@ bool Calculate256BBlockSizes(
 		unsigned int *BlockWidth256BytesY,
 		unsigned int *BlockWidth256BytesC);
 
+struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
+	unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
+	double dummy_single_array[2][DC__NUM_DPP__MAX];
+	unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
+	double dummy_double_array[2][DC__NUM_DPP__MAX];
+	bool dummy_boolean_array[DC__NUM_DPP__MAX];
+	bool dummy_boolean;
+	bool dummy_boolean2;
+	enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
+	DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
+	bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
+	unsigned int ReorderBytes;
+	unsigned int VMDataOnlyReturnBW;
+	double HostVMInefficiencyFactor;
+};
+
+struct dml32_ModeSupportAndSystemConfigurationFull {
+	unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
+	double dummy_double_array[2][DC__NUM_DPP__MAX];
+	DmlPipe SurfParameters[DC__NUM_DPP__MAX];
+	double dummy_single[5];
+	double dummy_single2[5];
+	SOCParametersList mSOCParameters;
+	unsigned int MaximumSwathWidthSupportLuma;
+	unsigned int MaximumSwathWidthSupportChroma;
+	double DSTYAfterScaler[DC__NUM_DPP__MAX];
+	double DSTXAfterScaler[DC__NUM_DPP__MAX];
+	double MaxTotalVActiveRDBandwidth;
+	bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
+};
+
+struct dummy_vars {
+	struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
+	struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
+};
+
 struct vba_vars_st {
 	ip_params_st ip;
 	soc_bounding_box_st soc;
@@ -154,6 +232,7 @@ struct vba_vars_st {
 	double DISPCLKWithRampingRoundedToDFSGranularity;
 	double DISPCLKWithoutRampingRoundedToDFSGranularity;
 	double MaxDispclkRoundedToDFSGranularity;
+	double MaxDppclkRoundedToDFSGranularity;
 	bool DCCEnabledAnyPlane;
 	double ReturnBandwidthToDCN;
 	unsigned int TotalActiveDPP;
@@ -169,6 +248,8 @@ struct vba_vars_st {
 	double NextMaxVStartup;
 	double VBlankTime;
 	double SmallestVBlank;
+	enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
+	double DCFCLKDeepSleepPerSurface[DC__NUM_DPP__MAX];
 	double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
 	double EffectiveDETPlusLBLinesLuma;
 	double EffectiveDETPlusLBLinesChroma;
@@ -212,6 +293,14 @@ struct vba_vars_st {
 	double UrgentLatencyPixelMixedWithVMData;
 	double UrgentLatencyVMDataOnly;
 	double UrgentLatency; // max of the above three
+	double USRRetrainingLatency;
+	double SMNLatency;
+	double FCLKChangeLatency;
+	unsigned int MALLAllocatedForDCNFinal;
+	double DefaultGPUVMMinPageSizeKBytes; // Default for the project
+	double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
+	double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 	double WritebackLatency;
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
@@ -284,6 +373,14 @@ struct vba_vars_st {
 	double DPPCLKDelayCNVCCursor;
 	double DISPCLKDelaySubtotal;
 	bool ProgressiveToInterlaceUnitInOPP;
+	unsigned int CompressedBufferSegmentSizeInkByteFinal;
+	unsigned int CompbufReservedSpace64B;
+	unsigned int CompbufReservedSpaceZs;
+	unsigned int LineBufferSizeFinal;
+	unsigned int MaximumPixelsPerLinePerDSCUnit;
+	unsigned int AlphaPixelChunkSizeInKByte;
+	double MinPixelChunkSizeBytes;
+	unsigned int DCCMetaBufferSizeBytes;
 	// Pipe/Plane Parameters
 	int VoltageLevel;
 	double FabricClock;
@@ -291,6 +388,23 @@ struct vba_vars_st {
 	double DISPCLK;
 	double SOCCLK;
 	double DCFCLK;
+	unsigned int MaxTotalDETInKByte;
+	unsigned int MinCompressedBufferSizeInKByte;
+	unsigned int NumberOfActiveSurfaces;
+	bool ViewportStationary[DC__NUM_DPP__MAX];
+	unsigned int RefreshRate[DC__NUM_DPP__MAX];
+	double       OutputBPP[DC__NUM_DPP__MAX];
+	unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
+	bool SynchronizeTimingsFinal;
+	bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
+	bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
+	unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
+	unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
+	enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
+	bool DRRDisplay[DC__NUM_DPP__MAX];
+	bool PteBufferMode[DC__NUM_DPP__MAX];
+	enum dm_output_type OutputType[DC__NUM_DPP__MAX];
+	enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
 
 	unsigned int NumberOfActivePlanes;
 	unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
@@ -355,6 +469,7 @@ struct vba_vars_st {
 	unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
 	bool XFCEnabled[DC__NUM_DPP__MAX];
 	bool ScalerEnabled[DC__NUM_DPP__MAX];
+	unsigned int VBlankNom[DC__NUM_DPP__MAX];
 
 	// Intermediates/Informational
 	bool ImmediateFlipSupport;
@@ -392,6 +507,12 @@ struct vba_vars_st {
 	double StutterEfficiencyNotIncludingVBlank;
 	double NonUrgentLatencyTolerance;
 	double MinActiveDRAMClockChangeLatencySupported;
+	double Z8StutterEfficiencyBestCase;
+	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
+	double Z8StutterEfficiencyNotIncludingVBlankBestCase;
+	double StutterPeriodBestCase;
+	Watermarks      Watermark;
+	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 
 	// These are the clocks calcuated by the library but they are not actually
 	// used explicitly. They are fetched by tests and then possibly used. The
@@ -399,6 +520,10 @@ struct vba_vars_st {
 	double DISPCLK_calculated;
 	double DPPCLK_calculated[DC__NUM_DPP__MAX];
 
+	bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
+
+	bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
+	bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 	unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
 	double VUpdateWidthPix[DC__NUM_DPP__MAX];
 	double VReadyOffsetPix[DC__NUM_DPP__MAX];
@@ -429,6 +554,7 @@ struct vba_vars_st {
 	double DRAMSpeedPerState[DC__VOLTAGE_STATES];
 	double MaxDispclk[DC__VOLTAGE_STATES];
 	int VoltageOverrideLevel;
+	double PHYCLKD32PerState[DC__VOLTAGE_STATES];
 
 	/*outputs*/
 	bool ScaleRatioAndTapsSupport;
@@ -452,6 +578,51 @@ struct vba_vars_st {
 	bool PitchSupport;
 	enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
 
+	/* Mode Support Reason */
+	bool P2IWith420;
+	bool DSCOnlyIfNecessaryWithBPP;
+	bool DSC422NativeNotSupported;
+	bool LinkRateDoesNotMatchDPVersion;
+	bool LinkRateForMultistreamNotIndicated;
+	bool BPPForMultistreamNotIndicated;
+	bool MultistreamWithHDMIOreDP;
+	bool MSOOrODMSplitWithNonDPLink;
+	bool NotEnoughLanesForMSO;
+	bool ViewportExceedsSurface;
+
+	bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
+	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
+	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
+	bool InvalidCombinationOfMALLUseForPState;
+
+	enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
+	double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
+	double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
+	double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
+	double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
+	double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
+	double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
+	double MetaRowBytesThisState[DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
+	bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
+
+	unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
+	unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
+	unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
+	unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
+	bool ImmediateFlipRequiredFinal;
+	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
+	bool EnoughWritebackUnits;
+	bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
+	bool NumberOfDP2p0Support;
+	unsigned int MaxNumDP2p0Streams;
+	unsigned int MaxNumDP2p0Outputs;
+	enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 	double WritebackLineBufferLumaBufferSize;
 	double WritebackLineBufferChromaBufferSize;
 	double WritebackMinHSCLRatio;
@@ -647,6 +818,7 @@ struct vba_vars_st {
 	double         dummy7[DC__NUM_DPP__MAX];
 	double         dummy8[DC__NUM_DPP__MAX];
 	double         dummy13[DC__NUM_DPP__MAX];
+	double         dummy_double_array[2][DC__NUM_DPP__MAX];
 	unsigned int        dummyinteger1ms[DC__NUM_DPP__MAX];
 	double        dummyinteger2ms[DC__NUM_DPP__MAX];
 	unsigned int        dummyinteger3[DC__NUM_DPP__MAX];
@@ -666,6 +838,9 @@ struct vba_vars_st {
 	unsigned int        dummyintegerarr2[DC__NUM_DPP__MAX];
 	unsigned int        dummyintegerarr3[DC__NUM_DPP__MAX];
 	unsigned int        dummyintegerarr4[DC__NUM_DPP__MAX];
+	unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
+	unsigned int        dummy_integer_array22[22][DC__NUM_DPP__MAX];
+
 	bool           dummysinglestring;
 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
@@ -896,8 +1071,8 @@ struct vba_vars_st {
 	double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
 	unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
 	unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -972,6 +1147,74 @@ struct vba_vars_st {
 	int Z8NumberOfStutterBurstsPerFrame;
 	unsigned int MaximumDSCBitsPerComponent;
 	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
+	double UrgentLatencyWithUSRRetraining;
+	double UrgLatencyWithUSRRetraining[DC__VOLTAGE_STATES];
+	double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
+	double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
+	double SurfaceRequiredDISPCLKWithoutODMCombine;
+	double SurfaceRequiredDISPCLK;
+	double SurfaceRequiredDISPCLKWithODMCombine2To1;
+	double SurfaceRequiredDISPCLKWithODMCombine4To1;
+	double MinActiveFCLKChangeLatencySupported;
+	double dummy14;
+	double dummy15;
+	int MinVoltageLevel;
+	int MaxVoltageLevel;
+	unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
+	unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
+	unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
+	unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
+	unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
+	bool ExceededMALLSize;
+	bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
+	unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
+	unsigned int dummyinteger33;
+	unsigned int CompressedBufferSizeInkByteThisState;
+	enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
+	Latencies myLatency;
+	Latencies mLatency;
+	Watermarks DummyWatermark;
+	bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
+	bool dummyBooleanvector1[DC__NUM_DPP__MAX];
+	bool dummyBooleanvector2[DC__NUM_DPP__MAX];
+	enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
+	bool NotEnoughUrgentLatencyHiding_dml32[DC__VOLTAGE_STATES][2];
+	bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
+	bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
+	enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
+	bool UnboundedRequestEnabledThisState;
+	bool DRAMClockChangeRequirementFinal;
+	bool FCLKChangeRequirementFinal;
+	bool USRRetrainingRequiredFinal;
+	bool MALLUseFinal;
+	bool ConfigurableDETSizeEnFinal;
+	bool dummyboolean;
+	unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
+	unsigned int nomDETInKByte;
+	enum mpc_combine_affinity  MPCCombineUse[DC__NUM_DPP__MAX];
+	bool MPCCombineMethodIncompatible;
+	unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
+	bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
+	enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
+	unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
+	bool OutputMultistreamEn[DC__NUM_DPP__MAX];
+	bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
+	double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
+	double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
+	bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
+	bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
+	bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
+	bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
+	bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
+	unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
+	unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
+	unsigned int BlockHeightY[DC__NUM_DPP__MAX];
+	unsigned int BlockHeightC[DC__NUM_DPP__MAX];
+	unsigned int BlockWidthY[DC__NUM_DPP__MAX];
+	unsigned int BlockWidthC[DC__NUM_DPP__MAX];
+	unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
+	bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
+	struct dummy_vars dummy_vars;
 };
 
 bool CalculateMinAndMaxPrefetchMode(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index d2273674e872..b4b51e51fc25 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -23,7 +23,6 @@
  *
  */
 
-#include "dml_wrapper.h"
 #include "resource.h"
 #include "core_types.h"
 #include "dsc.h"
@@ -86,25 +85,6 @@ static void get_pixel_clock_parameters(
 
 }
 
-static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-{
-	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
-
-	if (pipe_ctx->clock_source)
-		pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-			pipe_ctx->clock_source,
-			&pipe_ctx->stream_res.pix_clk_params,
-			&pipe_ctx->pll_settings);
-
-	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
-
-	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
-					&pipe_ctx->stream->bit_depth_params);
-	build_clamping_params(pipe_ctx->stream);
-
-	return DC_OK;
-}
-
 static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
 		struct bit_depth_reduction_params *fmt_bit_depth)
 {
@@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st
 	fmt_bit_depth->pixel_encoding = pixel_encoding;
 }
 
+/* Move this after the above function as VS complains about
+ * declaration issues for resource_build_bit_depth_reduction_params.
+ */
+
+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+{
+
+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
+
+	if (pipe_ctx->clock_source)
+		pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
+			pipe_ctx->clock_source,
+			&pipe_ctx->stream_res.pix_clk_params,
+			&pipe_ctx->pll_settings);
+
+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
+
+	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+		&pipe_ctx->stream->bit_depth_params);
+	build_clamping_params(pipe_ctx->stream);
+
+	return DC_OK;
+}
+
 bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
 {
 	int i;
@@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context(
 {
 	int i, pipe_cnt;
 	struct resource_context *res_ctx = &context->res_ctx;
-	struct pipe_ctx *pipe;
+	struct pipe_ctx *pipe = NULL;	// Fix potentially uninitialized error from VS
 
 	populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate);
 
@@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
+		context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
 	}
 }
 
@@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params(
 		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
 	*/
 	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
-	/* TODO : Uncomment the below line and make changes
-	 * as per DML nomenclature once it is available.
-	 * context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = context->bw_ctx.dml.vba.fclk_pstate_support;
-	 */
-
+	context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support =
+		context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
 
@@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
+	//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
 
 	/* Set D:
 	 * All clocks min.
@@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
-
+	//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
 	/* Set C, for Dummy P-State:
 	 * All clocks min.
 	 * DCFCLK: Min, as reported by PM FW, when available
@@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg(
 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-	//context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 	//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 
 	/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
-	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 4;
-	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
-
+	//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
 	if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
 		/* The only difference between A and C is p-state latency, if p-state is not supported
 		 * with full p-state latency we want to calculate DLG based on dummy p-state latency,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index fa39a06eed1d..d52cbc0e9b67 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -619,7 +619,7 @@ static int get_max_dsc_slices(union dsc_enc_slice_caps slice_caps)
 }
 
 
-// Increment sice number in available sice numbers stops if possible, or just increment if not
+// Increment slice number in available slice numbers stops if possible, or just increment if not
 static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 {
 	// Get next bigger num slices available in common caps
@@ -650,7 +650,7 @@ static int inc_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 }
 
 
-// Decrement sice number in available sice numbers stops if possible, or just decrement if not. Stop at zero.
+// Decrement slice number in available slice numbers stops if possible, or just decrement if not. Stop at zero.
 static int dec_num_slices(union dsc_enc_slice_caps slice_caps, int num_slices)
 {
 	// Get next bigger num slices available in common caps
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 0f4a22be8c40..bc47481a158e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -115,10 +115,10 @@ AMD_DAL_GPIO_DCN315 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn315/,$(GPIO_DCN315))
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN315)
 
 ###############################################################################
-# Diagnostics on FPGA
+# DCN 3.2
 ###############################################################################
-GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o
+GPIO_DCN32 = hw_translate_dcn32.o hw_factory_dcn32.o
 
-AMD_DAL_GPIO_DIAG_FPGA = $(addprefix $(AMDDALPATH)/dc/gpio/diagnostics/,$(GPIO_DIAG_FPGA))
+AMD_DAL_GPIO_DCN32 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn32/,$(GPIO_DCN32))
 
-AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DIAG_FPGA)
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
index 52ba62b3b5e4..3005ee7751a0 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
@@ -150,7 +150,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exist */
 		ASSERT_CRITICAL(false);
 		return false;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
index 291966efe63d..d734e3a134d1 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
@@ -153,7 +153,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exista */
 #ifdef PALLADIUM_SUPPORTED
 		*id = GPIO_ID_HPD;
 		*en = GPIO_DDC_LINE_DDC1;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
index 3169c567475f..49d6250037a9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
@@ -155,7 +155,8 @@ static bool offset_to_id(
 	/* DDC */
 	/* we don't care about the GPIO_ID for DDC
 	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-	 * directly in the create method */
+	 * directly in the create method
+	 */
 	case REG(DC_GPIO_DDC1_A):
 		*en = GPIO_DDC_LINE_DDC1;
 		return true;
@@ -178,14 +179,16 @@ static bool offset_to_id(
 		*en = GPIO_DDC_LINE_DDC_VGA;
 		return true;
 
-//	case REG(DC_GPIO_I2CPAD_A): not exit
-//	case REG(DC_GPIO_PWRSEQ_A):
-//	case REG(DC_GPIO_PAD_STRENGTH_1):
-//	case REG(DC_GPIO_PAD_STRENGTH_2):
-//	case REG(DC_GPIO_DEBUG):
+/*
+ *	case REG(DC_GPIO_I2CPAD_A): not exit
+ *	case REG(DC_GPIO_PWRSEQ_A):
+ *	case REG(DC_GPIO_PAD_STRENGTH_1):
+ *	case REG(DC_GPIO_PAD_STRENGTH_2):
+ *	case REG(DC_GPIO_DEBUG):
+ */
 	/* UNEXPECTED */
 	default:
-//	case REG(DC_GPIO_SYNCA_A): not exist
+/*	case REG(DC_GPIO_SYNCA_A): not exist */
 		ASSERT_CRITICAL(false);
 		return false;
 	}
@@ -369,7 +372,7 @@ static const struct hw_translate_funcs funcs = {
 };
 
 /*
- * dal_hw_translate_dcn10_init
+ * dal_hw_translate_dcn30_init
  *
  * @brief
  * Initialize Hw translate function pointers.
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
new file mode 100644
index 000000000000..d635b73af46f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+#include "../hw_generic.h"
+
+#include "hw_factory_dcn32.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define block HPD
+#define reg_num 0
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+
+
+#define REG(reg_name)\
+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
+
+#define SF_HPD(reg_name, field_name, post_fix)\
+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+#define REGI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+				reg ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+
+
+#define hpd_regs(id) \
+{\
+	HPD_REG_LIST(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+	hpd_regs(0),
+	hpd_regs(1),
+	hpd_regs(2),
+	hpd_regs(3),
+	hpd_regs(4),
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+		HPD_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+		HPD_MASK_SH_LIST(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs_dcn[] = {
+	ddc_data_regs_dcn2(1),
+	ddc_data_regs_dcn2(2),
+	ddc_data_regs_dcn2(3),
+	ddc_data_regs_dcn2(4),
+	ddc_data_regs_dcn2(5),
+	{
+			DDC_GPIO_VGA_REG_LIST(DATA),
+			.ddc_setup = 0,
+			.phy_aux_cntl = 0,
+			.dc_gpio_aux_ctrl_5 = 0
+	}
+};
+
+static const struct ddc_registers ddc_clk_regs_dcn[] = {
+	ddc_clk_regs_dcn2(1),
+	ddc_clk_regs_dcn2(2),
+	ddc_clk_regs_dcn2(3),
+	ddc_clk_regs_dcn2(4),
+	ddc_clk_regs_dcn2(5),
+	{
+			DDC_GPIO_VGA_REG_LIST(CLK),
+			.ddc_setup = 0,
+			.phy_aux_cntl = 0,
+			.dc_gpio_aux_ctrl_5 = 0
+	}
+};
+
+static const struct ddc_sh_mask ddc_shift[] = {
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+};
+
+static const struct ddc_sh_mask ddc_mask[] = {
+	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
+	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+};
+
+#include "../generic_regs.h"
+
+/* set field name */
+#define SF_GENERIC(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+#define generic_regs(id) \
+{\
+	GENERIC_REG_LIST(id)\
+}
+
+static const struct generic_registers generic_regs[] = {
+	generic_regs(A),
+	generic_regs(B),
+};
+
+static const struct generic_sh_mask generic_shift[] = {
+	GENERIC_MASK_SH_LIST(__SHIFT, A),
+	GENERIC_MASK_SH_LIST(__SHIFT, B),
+};
+
+static const struct generic_sh_mask generic_mask[] = {
+	GENERIC_MASK_SH_LIST(_MASK, A),
+	GENERIC_MASK_SH_LIST(_MASK, B),
+};
+
+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
+
+	generic->regs = &generic_regs[en];
+	generic->shifts = &generic_shift[en];
+	generic->masks = &generic_mask[en];
+	generic->base.regs = &generic_regs[en].gpio;
+}
+
+static void define_ddc_registers(
+		struct hw_gpio_pin *pin,
+		uint32_t en)
+{
+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+	switch (pin->id) {
+	case GPIO_ID_DDC_DATA:
+		ddc->regs = &ddc_data_regs_dcn[en];
+		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
+		break;
+	case GPIO_ID_DDC_CLOCK:
+		ddc->regs = &ddc_clk_regs_dcn[en];
+		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
+		break;
+	default:
+		ASSERT_CRITICAL(false);
+		return;
+	}
+
+	ddc->shifts = &ddc_shift[en];
+	ddc->masks = &ddc_mask[en];
+
+}
+
+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
+
+	hpd->regs = &hpd_regs[en];
+	hpd->shifts = &hpd_shift;
+	hpd->masks = &hpd_mask;
+	hpd->base.regs = &hpd_regs[en].gpio;
+}
+
+
+/* fucntion table */
+static const struct hw_factory_funcs funcs = {
+	.init_ddc_data = dal_hw_ddc_init,
+	.init_generic = dal_hw_generic_init,
+	.init_hpd = dal_hw_hpd_init,
+	.get_ddc_pin = dal_hw_ddc_get_pin,
+	.get_hpd_pin = dal_hw_hpd_get_pin,
+	.get_generic_pin = dal_hw_generic_get_pin,
+	.define_hpd_registers = define_hpd_registers,
+	.define_ddc_registers = define_ddc_registers,
+	.define_generic_registers = define_generic_registers
+};
+/*
+ * dal_hw_factory_dcn32_init
+ *
+ * @brief
+ * Initialize HW factory function pointers and pin info
+ *
+ * @param
+ * struct hw_factory *factory - [out] struct of function pointers
+ */
+void dal_hw_factory_dcn32_init(struct hw_factory *factory)
+{
+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 6;
+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6;
+	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
+	factory->number_of_pins[GPIO_ID_HPD] = 5;
+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+	factory->number_of_pins[GPIO_ID_SYNC] = 0;
+	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
+
+	factory->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h
new file mode 100644
index 000000000000..71138d0e192b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DAL_HW_FACTORY_DCN32_H__
+#define __DAL_HW_FACTORY_DCN32_H__
+
+/* Initialize HW factory function pointers and pin info */
+void dal_hw_factory_dcn32_init(struct hw_factory *factory);
+
+#endif /* __DAL_HW_FACTORY_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
new file mode 100644
index 000000000000..8493b9981f9e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "hw_translate_dcn32.h"
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_translate.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define block HPD
+#define reg_num 0
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#undef REG
+#define REG(reg_name)\
+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
+#define SF_HPD(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+
+static bool offset_to_id(
+	uint32_t offset,
+	uint32_t mask,
+	enum gpio_id *id,
+	uint32_t *en)
+{
+	switch (offset) {
+	/* GENERIC */
+	case REG(DC_GPIO_GENERIC_A):
+		*id = GPIO_ID_GENERIC;
+		switch (mask) {
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+			*en = GPIO_GENERIC_A;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
+			*en = GPIO_GENERIC_B;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
+			*en = GPIO_GENERIC_C;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
+			*en = GPIO_GENERIC_D;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
+			*en = GPIO_GENERIC_E;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
+			*en = GPIO_GENERIC_F;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* HPD */
+	case REG(DC_GPIO_HPD_A):
+		*id = GPIO_ID_HPD;
+		switch (mask) {
+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
+			*en = GPIO_HPD_1;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
+			*en = GPIO_HPD_2;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
+			*en = GPIO_HPD_3;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
+			*en = GPIO_HPD_4;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
+			*en = GPIO_HPD_5;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* REG(DC_GPIO_GENLK_MASK */
+	case REG(DC_GPIO_GENLK_A):
+		*id = GPIO_ID_GSL;
+		switch (mask) {
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
+			*en = GPIO_GSL_GENLOCK_CLOCK;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
+			*en = GPIO_GSL_GENLOCK_VSYNC;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_A;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_B;
+			return true;
+		default:
+			ASSERT_CRITICAL(false);
+			return false;
+		}
+	break;
+	/* DDC */
+	/* we don't care about the GPIO_ID for DDC
+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
+	 * directly in the create method */
+	case REG(DC_GPIO_DDC1_A):
+		*en = GPIO_DDC_LINE_DDC1;
+		return true;
+	case REG(DC_GPIO_DDC2_A):
+		*en = GPIO_DDC_LINE_DDC2;
+		return true;
+	case REG(DC_GPIO_DDC3_A):
+		*en = GPIO_DDC_LINE_DDC3;
+		return true;
+	case REG(DC_GPIO_DDC4_A):
+		*en = GPIO_DDC_LINE_DDC4;
+		return true;
+	case REG(DC_GPIO_DDC5_A):
+		*en = GPIO_DDC_LINE_DDC5;
+		return true;
+	case REG(DC_GPIO_DDCVGA_A):
+		*en = GPIO_DDC_LINE_DDC_VGA;
+		return true;
+	default:
+		ASSERT_CRITICAL(false);
+		return false;
+	}
+}
+
+static bool id_to_offset(
+	enum gpio_id id,
+	uint32_t en,
+	struct gpio_pin_info *info)
+{
+	bool result = true;
+
+	switch (id) {
+	case GPIO_ID_DDC_DATA:
+		info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = REG(DC_GPIO_DDC1_A);
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = REG(DC_GPIO_DDC2_A);
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = REG(DC_GPIO_DDC3_A);
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = REG(DC_GPIO_DDC4_A);
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = REG(DC_GPIO_DDC5_A);
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = REG(DC_GPIO_DDCVGA_A);
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_DDC_CLOCK:
+		info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = REG(DC_GPIO_DDC1_A);
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = REG(DC_GPIO_DDC2_A);
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = REG(DC_GPIO_DDC3_A);
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = REG(DC_GPIO_DDC4_A);
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = REG(DC_GPIO_DDC5_A);
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = REG(DC_GPIO_DDCVGA_A);
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_GENERIC:
+		info->offset = REG(DC_GPIO_GENERIC_A);
+		switch (en) {
+		case GPIO_GENERIC_A:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
+		break;
+		case GPIO_GENERIC_B:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
+		break;
+		case GPIO_GENERIC_C:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
+		break;
+		case GPIO_GENERIC_D:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
+		break;
+		case GPIO_GENERIC_E:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
+		break;
+		case GPIO_GENERIC_F:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_HPD:
+		info->offset = REG(DC_GPIO_HPD_A);
+		switch (en) {
+		case GPIO_HPD_1:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
+		break;
+		case GPIO_HPD_2:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
+		break;
+		case GPIO_HPD_3:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
+		break;
+		case GPIO_HPD_4:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
+		break;
+		case GPIO_HPD_5:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_GSL:
+		switch (en) {
+		case GPIO_GSL_GENLOCK_CLOCK:
+				/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_GENLOCK_VSYNC:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_SWAPLOCK_A:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+		break;
+		case GPIO_GSL_SWAPLOCK_B:
+			/*not implmented*/
+			ASSERT_CRITICAL(false);
+			result = false;
+
+		break;
+		default:
+			ASSERT_CRITICAL(false);
+			result = false;
+		}
+	break;
+	case GPIO_ID_SYNC:
+	case GPIO_ID_VIP_PAD:
+	default:
+		ASSERT_CRITICAL(false);
+		result = false;
+	}
+
+	if (result) {
+		info->offset_y = info->offset + 2;
+		info->offset_en = info->offset + 1;
+		info->offset_mask = info->offset - 1;
+
+		info->mask_y = info->mask;
+		info->mask_en = info->mask;
+		info->mask_mask = info->mask;
+	}
+
+	return result;
+}
+
+/* function table */
+static const struct hw_translate_funcs funcs = {
+	.offset_to_id = offset_to_id,
+	.id_to_offset = id_to_offset,
+};
+
+/*
+ * dal_hw_translate_dcn32_init
+ *
+ * @brief
+ * Initialize Hw translate function pointers.
+ *
+ * @param
+ * struct hw_translate *tr - [out] struct of function pointers
+ *
+ */
+void dal_hw_translate_dcn32_init(struct hw_translate *tr)
+{
+	tr->funcs = &funcs;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h
new file mode 100644
index 000000000000..af64e104d84c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DAL_HW_TRANSLATE_DCN32_H__
+#define __DAL_HW_TRANSLATE_DCN32_H__
+
+struct hw_translate;
+
+/* Initialize Hw translate function pointers */
+void dal_hw_translate_dcn32_init(struct hw_translate *tr);
+
+#endif /* __DAL_HW_TRANSLATE_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
deleted file mode 100644
index c6e28f6bf1a2..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-
-#include "dm_services.h"
-#include "hw_factory_diag.h"
-#include "include/gpio_types.h"
-#include "../hw_factory.h"
-
-/*
- * Header of this unit
- */
-
-#include "../hw_gpio.h"
-#include "../hw_ddc.h"
-#include "../hw_hpd.h"
-#include "../hw_generic.h"
-
-/* function table */
-static const struct hw_factory_funcs funcs = {
-	.init_ddc_data = NULL,
-	.init_generic = NULL,
-	.init_hpd = NULL,
-};
-
-void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
-{
-	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-	factory->number_of_pins[GPIO_ID_HPD] = 6;
-	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-	factory->number_of_pins[GPIO_ID_GSL] = 4;
-	factory->funcs = &funcs;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h
deleted file mode 100644
index bf68eb1d9a1d..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_HW_FACTORY_DIAG_FPGA_H__
-#define __DAL_HW_FACTORY_DIAG_FPGA_H__
-
-struct hw_factory;
-
-/* Initialize HW factory function pointers and pin info */
-void dal_hw_factory_diag_fpga_init(struct hw_factory *factory);
-
-#endif /* __DAL_HW_FACTORY_DIAG_FPGA_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c
deleted file mode 100644
index e5138a5a8eb5..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "hw_translate_diag.h"
-#include "include/gpio_types.h"
-
-#include "../hw_translate.h"
-
-/* function table */
-static const struct hw_translate_funcs funcs = {
-	.offset_to_id = NULL,
-	.id_to_offset = NULL,
-};
-
-void dal_hw_translate_diag_fpga_init(struct hw_translate *tr)
-{
-	tr->funcs = &funcs;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h
deleted file mode 100644
index 4f053241fe96..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2013-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-#define __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-
-struct hw_translate;
-
-/* Initialize Hw translate function pointers */
-void dal_hw_translate_diag_fpga_init(struct hw_translate *tr);
-
-#endif /* __DAL_HW_TRANSLATE_DIAG_FPGA_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index ef4f69612097..9756640411b9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -53,23 +53,13 @@
 #include "dcn21/hw_factory_dcn21.h"
 #include "dcn30/hw_factory_dcn30.h"
 #include "dcn315/hw_factory_dcn315.h"
-
-#include "diagnostics/hw_factory_diag.h"
-
-/*
- * This unit
- */
+#include "dcn32/hw_factory_dcn32.h"
 
 bool dal_hw_factory_init(
 	struct hw_factory *factory,
 	enum dce_version dce_version,
 	enum dce_environment dce_environment)
 {
-	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-		dal_hw_factory_diag_fpga_init(factory);
-		return true;
-	}
-
 	switch (dce_version) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
 	case DCE_VERSION_6_0:
@@ -118,6 +108,10 @@ bool dal_hw_factory_init(
 	case DCN_VERSION_3_15:
 		dal_hw_factory_dcn315_init(factory);
 		return true;
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
+		dal_hw_factory_dcn32_init(factory);
+		return true;
 	default:
 		ASSERT_CRITICAL(false);
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 1db4f1414d7e..82aad7bc0300 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -51,8 +51,7 @@
 #include "dcn21/hw_translate_dcn21.h"
 #include "dcn30/hw_translate_dcn30.h"
 #include "dcn315/hw_translate_dcn315.h"
-
-#include "diagnostics/hw_translate_diag.h"
+#include "dcn32/hw_translate_dcn32.h"
 
 /*
  * This unit
@@ -63,11 +62,6 @@ bool dal_hw_translate_init(
 	enum dce_version dce_version,
 	enum dce_environment dce_environment)
 {
-	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-		dal_hw_translate_diag_fpga_init(translate);
-		return true;
-	}
-
 	switch (dce_version) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
 	case DCE_VERSION_6_0:
@@ -113,7 +107,10 @@ bool dal_hw_translate_init(
 	case DCN_VERSION_3_15:
 		dal_hw_translate_dcn315_init(translate);
 		return true;
-
+	case DCN_VERSION_3_2:
+	case DCN_VERSION_3_21:
+		dal_hw_translate_dcn32_init(translate);
+		return true;
 	default:
 		BREAK_TO_DEBUGGER();
 		return false;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 444182a97e6e..8eb8d4afa876 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -54,7 +54,7 @@ enum dc_status {
 	DC_UNSUPPORTED_VALUE = 25,
 
 	DC_NO_LINK_ENC_RESOURCE = 26,
-
+	DC_FAIL_DP_PAYLOAD_ALLOCATION = 27,
 	DC_ERROR_UNEXPECTED = -1
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 555d4d9e1454..0317af5bb8ca 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -195,6 +195,16 @@ struct resource_funcs {
 	enum dc_status (*add_dsc_to_stream_resource)(
 			struct dc *dc, struct dc_state *state,
 			struct dc_stream_state *stream);
+
+	void (*add_phantom_pipes)(
+            struct dc *dc,
+            struct dc_state *context,
+            display_e2e_pipe_params_st *pipes,
+			unsigned int pipe_cnt,
+            unsigned int index);
+	void (*remove_phantom_pipes)(
+            struct dc *dc,
+            struct dc_state *context);
 };
 
 struct audio_support{
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index b5570aa8e39d..9ae9439c8f7b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -125,6 +125,7 @@ struct nv_wm_range_entry {
 		double pstate_latency_us;
 		double sr_exit_time_us;
 		double sr_enter_plus_exit_time_us;
+		double fclk_change_latency_us;
 	} dml_input;
 };
 
@@ -142,6 +143,7 @@ struct clk_state_registers_and_bypass {
 	uint32_t dprefclk;
 	uint32_t dispclk;
 	uint32_t dppclk;
+	uint32_t dtbclk;
 
 	uint32_t dppclk_bypass;
 	uint32_t dcfclk_bypass;
@@ -243,6 +245,9 @@ struct clk_mgr_funcs {
 
 	void (*init_clocks)(struct clk_mgr *clk_mgr);
 
+	void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass,
+			struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
+
 	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
 	void (*get_clock)(struct clk_mgr *clk_mgr,
 			struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 1391c20f1852..68c2ed434d2c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -112,9 +112,10 @@ enum dentist_divider_range {
 	CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
 	CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
 
-// TODO:
 #define CLK_REG_LIST_DCN3()	  \
-	SR(DENTIST_DISPCLK_CNTL)
+	CLK_COMMON_REG_LIST_DCN_BASE(), \
+	CLK_SRI(CLK0_CLK_PLL_REQ,   CLK02, 0), \
+	CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
 
 #define CLK_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -155,6 +156,34 @@ enum dentist_divider_range {
 	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
 	CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
 
+#define CLK_REG_LIST_DCN32()	  \
+	SR(DENTIST_DISPCLK_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
+	CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
+	CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
+	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+	CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
+	CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
+#define CLK_REG_LIST_DCN321()	  \
+	SR(DENTIST_DISPCLK_CNTL), \
+	CLK_SR_DCN321(CLK0_CLK_PLL_REQ,   CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
+	CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
+	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
+	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
+
 #define CLK_REG_FIELD_LIST(type) \
 	type DPREFCLK_SRC_SEL; \
 	type DENTIST_DPREFCLK_WDIVIDER; \
@@ -199,6 +228,18 @@ struct clk_mgr_registers {
 	uint32_t CLK0_CLK2_DFS_CNTL;
 	uint32_t CLK0_CLK_PLL_REQ;
 
+	uint32_t CLK1_CLK_PLL_REQ;
+	uint32_t CLK1_CLK0_DFS_CNTL;
+	uint32_t CLK1_CLK1_DFS_CNTL;
+	uint32_t CLK1_CLK2_DFS_CNTL;
+	uint32_t CLK1_CLK3_DFS_CNTL;
+	uint32_t CLK1_CLK4_DFS_CNTL;
+
+	uint32_t CLK0_CLK0_DFS_CNTL;
+	uint32_t CLK0_CLK1_DFS_CNTL;
+	uint32_t CLK0_CLK3_DFS_CNTL;
+	uint32_t CLK0_CLK4_DFS_CNTL;
+
 	uint32_t MP1_SMN_C2PMSG_67;
 	uint32_t MP1_SMN_C2PMSG_83;
 	uint32_t MP1_SMN_C2PMSG_91;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c7021915bac8..c2d116cce119 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -45,9 +45,10 @@ enum physymclk_clock_source {
 	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
 };
 
-enum hdmistreamclk_source {
+enum streamclk_source {
 	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
 	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
+	DPREFCLK,                 // Selects DPREFCLK as source for hdmistreamclk
 };
 
 enum dentist_dispclk_change_mode {
@@ -55,6 +56,13 @@ enum dentist_dispclk_change_mode {
 	DISPCLK_CHANGE_MODE_RAMPING,
 };
 
+enum pixel_rate_div {
+   PIXEL_RATE_DIV_BY_1 = 0,
+   PIXEL_RATE_DIV_BY_2 = 1,
+   PIXEL_RATE_DIV_BY_4 = 3,
+   PIXEL_RATE_DIV_NA = 0xF
+};
+
 struct dccg {
 	struct dc_context *ctx;
 	const struct dccg_funcs *funcs;
@@ -62,7 +70,7 @@ struct dccg {
 	int ref_dppclk;
 	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
 	//int audio_dtbclk_khz;/* TODO needs to be removed */
-	int ref_dtbclk_khz;/* TODO needs to be removed */
+	//int ref_dtbclk_khz;/* TODO needs to be removed */
 };
 
 struct dtbclk_dto_params {
@@ -72,6 +80,7 @@ struct dtbclk_dto_params {
 	int req_audio_dtbclk_khz;
 	int num_odm_segments;
 	int ref_dtbclk_khz;
+	bool is_hdmi;
 };
 
 struct dccg_funcs {
@@ -91,7 +100,7 @@ struct dccg_funcs {
 
 	void (*set_dpstreamclk)(
 			struct dccg *dccg,
-			enum hdmistreamclk_source src,
+			enum streamclk_source src,
 			int otg_inst);
 
 	void (*enable_symclk32_se)(
@@ -120,11 +129,11 @@ struct dccg_funcs {
 
 	void (*set_dtbclk_dto)(
 			struct dccg *dccg,
-			struct dtbclk_dto_params *dto_params);
+			const struct dtbclk_dto_params *params);
 
 	void (*set_audio_dtbclk_dto)(
 			struct dccg *dccg,
-			uint32_t req_audio_dtbclk_khz);
+			const struct dtbclk_dto_params *params);
 
 	void (*set_dispclk_change_mode)(
 			struct dccg *dccg,
@@ -138,6 +147,18 @@ struct dccg_funcs {
 		struct dccg *dccg,
 		int inst);
 
+void (*set_pixel_rate_div)(
+        struct dccg *dccg,
+        uint32_t otg_inst,
+        enum pixel_rate_div k1,
+        enum pixel_rate_div k2);
+
+void (*set_valid_pixel_rate)(
+        struct dccg *dccg,
+	int ref_dtbclk_khz,
+        int otg_inst,
+        int pixclk_khz);
+
 };
 
 #endif //__DAL_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 9195dec294c2..e7571c6f5ead 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -47,6 +47,8 @@ struct dcn_hubbub_wm_set {
 	uint32_t sr_enter;
 	uint32_t sr_exit;
 	uint32_t dram_clk_chanage;
+	uint32_t usr_retrain;
+	uint32_t fclk_pstate_change;
 };
 
 struct dcn_hubbub_wm {
@@ -168,6 +170,7 @@ struct hubbub_funcs {
 	void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
 	void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
 	void (*init_crb)(struct hubbub *hubbub);
+	void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
 };
 
 struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index fd6572ba3fb2..b982be64c792 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -219,12 +219,6 @@ struct dwbc_funcs {
 		struct dwbc *dwbc,
 		const struct dc_transfer_func *in_transfer_func_dwb_ogam);
 
-	void (*get_privacy_mask)(
-		struct dwbc *dwbc, uint32_t *mask_id);
-
-	void (*set_privacy_mask)(
-		struct dwbc *dwbc, uint32_t mask_id);
-
 	//TODO: merge with output_transfer_func?
 	bool (*dwb_ogam_set_input_transfer_func)(
 		struct dwbc *dwbc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index ad69d78c4ac3..906818e792dd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -63,6 +63,7 @@ struct hubp {
 	int opp_id;
 	int mpcc_id;
 	struct dc_cursor_attributes curs_attr;
+	struct dc_cursor_position curs_pos;
 	bool power_gated;
 };
 
@@ -140,6 +141,9 @@ struct hubp_funcs {
 
 	void (*set_blank)(struct hubp *hubp, bool blank);
 	void (*set_blank_regs)(struct hubp *hubp, bool blank);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*phantom_hubp_post_enable)(struct hubp *hubp);
+#endif
 	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
 
 	void (*set_cursor_attributes)(
@@ -193,6 +197,10 @@ struct hubp_funcs {
 	bool (*hubp_in_blank)(struct hubp *hubp);
 	void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
 
+	void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);
+	void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel);
+	void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
+
 	void (*hubp_set_flip_int)(struct hubp *hubp);
 
 	void (*program_extended_blank)(struct hubp *hubp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 2013a70603ae..ec572a9e4054 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -85,7 +85,26 @@ union dpcd_psr_configuration {
 		unsigned char LINE_CAPTURE_INDICATION   : 1;
 		/* For eDP 1.4, PSR v2*/
 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
-		unsigned char RESERVED                  : 2;
+		unsigned char ENABLE_PSR2               : 1;
+		/* For eDP 1.5, PSR v2 w/ early transport */
+		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
+	} bits;
+	unsigned char raw;
+};
+
+union dpcd_alpm_configuration {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char IRQ_HPD_ENABLE            : 1;
+		unsigned char RESERVED                  : 6;
+	} bits;
+	unsigned char raw;
+};
+
+union dpcd_sink_active_vtotal_control_mode {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char RESERVED                  : 7;
 	} bits;
 	unsigned char raw;
 };
@@ -200,6 +219,8 @@ struct link_encoder_funcs {
 		struct link_encoder *enc,
 		enum encoder_type_select sel,
 		uint32_t hpo_inst);
+	void (*set_dig_output_mode)(
+			struct link_encoder *enc, uint8_t pix_per_container);
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 8798cfa11a4d..b72fb314d804 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -37,6 +37,7 @@ struct cstate_pstate_watermarks_st {
 	uint32_t cstate_enter_plus_exit_z8_ns;
 	uint32_t cstate_enter_plus_exit_ns;
 	uint32_t pstate_change_ns;
+	uint32_t fclk_pstate_change_ns;
 };
 
 struct dcn_watermarks {
@@ -46,6 +47,7 @@ struct dcn_watermarks {
 	uint32_t frac_urg_bw_flip;
 	int32_t urgent_latency_ns;
 	struct cstate_pstate_watermarks_st cstate_pstate;
+	uint32_t usr_retraining_ns;
 };
 
 struct dcn_watermark_set {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index f5fd2a067323..5097037e3962 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -346,6 +346,11 @@ struct mpc_funcs {
 			int mpcc_id,
 			const struct mpc_grph_gamut_adjustment *adjust);
 
+	bool (*program_1dlut)(
+			struct mpc *mpc,
+			const struct pwl_params *params,
+			uint32_t rmu_idx);
+
 	bool (*program_shaper)(
 			struct mpc *mpc,
 			const struct pwl_params *params,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 678c2065e5e8..e04a51a57c93 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -77,6 +77,7 @@ struct encoder_info_frame {
 	struct dc_info_packet gamut;
 	struct dc_info_packet vendor;
 	struct dc_info_packet hfvsif;
+	struct dc_info_packet vtem;
 	/* source product description */
 	struct dc_info_packet spd;
 	/* video stream configuration */
@@ -164,6 +165,10 @@ struct stream_encoder_funcs {
 	void (*stop_dp_info_packets)(
 		struct stream_encoder *enc);
 
+	void (*reset_fifo)(
+		struct stream_encoder *enc
+	);
+
 	void (*dp_blank)(
 		struct dc_link *link,
 		struct stream_encoder *enc);
@@ -243,6 +248,9 @@ struct stream_encoder_funcs {
 
 	uint32_t (*get_fifo_cal_average_level)(
 		struct stream_encoder *enc);
+
+	void (*set_input_mode)(
+		struct stream_encoder *enc, unsigned int pix_per_container);
 };
 
 struct hpo_dp_stream_encoder_state {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 554d2e33bd7f..62d4683f17a2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -174,6 +174,9 @@ struct timing_generator_funcs {
 
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*phantom_crtc_post_enable)(struct timing_generator *tg);
+#endif
 	bool (*immediate_disable_crtc)(struct timing_generator *tg);
 	bool (*is_counter_moving)(struct timing_generator *tg);
 	void (*get_position)(struct timing_generator *tg,
@@ -293,6 +296,7 @@ struct timing_generator_funcs {
 	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
 	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
 			struct dc_crtc_timing *timing);
+	void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 	void (*set_gsl_source_select)(struct timing_generator *optc,
 			int group_idx,
@@ -310,6 +314,10 @@ struct timing_generator_funcs {
 			uint32_t slave_pixel_clock_100Hz,
 			uint8_t master_clock_divider,
 			uint8_t slave_clock_divider);
+	bool (*validate_vmin_vmax)(struct timing_generator *optc,
+			int vmin, int vmax);
+	bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
+			uint32_t vtotal_change_limit);
 
 	void (*init_odm)(struct timing_generator *tg);
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 05053f3b4ab7..eb616a4ed508 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -244,6 +244,8 @@ struct hw_sequencer_funcs {
 			struct pipe_ctx *pipe_ctx,
 			struct tg_color *color,
 			int mpcc_id);
+
+	void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
 };
 
 void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index 8c2f190c4712..ded45f8f4b82 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -68,6 +68,7 @@ struct dce_hwseq;
 struct timing_generator;
 struct tg_color;
 struct output_pixel_processor;
+struct mpcc_blnd_cfg;
 
 struct hwseq_private_funcs {
 
@@ -140,9 +141,19 @@ struct hwseq_private_funcs {
 			const struct dc_plane_state *plane_state);
 	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
 			const struct dc_plane_state *plane_state);
+	bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
+			const struct dc_plane_state *plane_state);
 	void (*PLAT_58856_wa)(struct dc_state *context,
 			struct pipe_ctx *pipe_ctx);
 	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
+#ifdef CONFIG_DRM_AMD_DC_DCN
+	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
+	void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
+	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
+	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
+			unsigned int *k1_div,
+			unsigned int *k2_div);
+#endif
 };
 
 struct dce_hwseq {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index c6f6baa6e677..7beb14169f92 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -110,4 +110,11 @@ bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct
 /* Returns true if encoder assignments in supplied state pass validity checks. */
 bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
 
+/* Set the link encoder assignment mode for the current_state to LINK_ENC_CFG_TRANSIENT mode.
+ * This indicates that a new_state is in the process of being applied to hardware.
+ * During this transition, old and new encoder assignments should be accessible from the old_state.
+ * Only allow transition into transient mode if new encoder assignments are valid.
+ */
+void link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state);
+
 #endif /* DC_INC_LINK_ENC_CFG_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index e6c49ef8b584..3482a877b6af 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -62,9 +62,9 @@ struct link_hwss_ext {
 			const struct link_resource *link_res,
 			struct encoder_set_dp_phy_pattern_param *tp_params);
 	void (*set_dp_lane_settings)(struct dc_link *link,
-		const struct link_resource *link_res,
-		const struct dc_link_settings *link_settings,
-		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
+			const struct link_resource *link_res,
+			const struct dc_link_settings *link_settings,
+			const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
 	void (*update_stream_allocation_table)(struct dc_link *link,
 			const struct link_resource *link_res,
 			const struct link_mst_stream_allocation_table *table);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 2369f38ed06f..58158764adc0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -205,6 +205,13 @@ bool get_temp_dp_link_res(struct dc_link *link,
 		struct link_resource *link_res,
 		struct dc_link_settings *link_settings);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
+		const struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		const struct dc_link *link);
+#endif
+
 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
 	struct dc_state *context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 5f49048dde47..41da81c85fdc 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -135,7 +135,6 @@ IRQ_DCN31 = irq_service_dcn31.o
 AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
-
 ###############################################################################
 # DCN 315
 ###############################################################################
@@ -144,3 +143,12 @@ IRQ_DCN315 = irq_service_dcn315.o
 AMD_DAL_IRQ_DCN315= $(addprefix $(AMDDALPATH)/dc/irq/dcn315/,$(IRQ_DCN315))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN315)
+
+###############################################################################
+# DCN 32
+###############################################################################
+IRQ_DCN32 = irq_service_dcn32.o
+
+AMD_DAL_IRQ_DCN32= $(addprefix $(AMDDALPATH)/dc/irq/dcn32/,$(IRQ_DCN32))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN32)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
new file mode 100644
index 000000000000..3a213ca2f077
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#include "irq_service_dcn32.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+enum dc_irq_source to_dal_irq_source_dcn32(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC1_VLINE0;
+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC2_VLINE0;
+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC3_VLINE0;
+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC4_VLINE0;
+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC5_VLINE0;
+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC6_VLINE0;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP6;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD3_INT:
+			return DC_IRQ_SOURCE_HPD3;
+		case DCN_1_0__CTXID__DC_HPD4_INT:
+			return DC_IRQ_SOURCE_HPD4;
+		case DCN_1_0__CTXID__DC_HPD5_INT:
+			return DC_IRQ_SOURCE_HPD5;
+		case DCN_1_0__CTXID__DC_HPD6_INT:
+			return DC_IRQ_SOURCE_HPD6;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(
+	struct irq_service *irq_service,
+	const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status =
+		get_reg_field_value(
+			value,
+			HPD0_DC_HPD_INT_STATUS,
+			DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(
+		value,
+		current_status ? 0 : 1,
+		HPD0_DC_HPD_INT_CONTROL,
+		DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+	.set = NULL,
+	.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs outbox_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+			reg ## block ## id ## _ ## reg_name
+
+#define SRI_DMUB(reg_name)\
+	BASE(reg ## reg_name ## _BASE_IDX) + \
+			reg ## reg_name
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI(reg1, block, reg_num),\
+	.enable_mask = \
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI(reg2, block, reg_num),\
+	.ack_mask = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI_DMUB(reg1),\
+	.enable_mask = \
+		reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		reg1 ## __ ## mask1 ## _MASK,\
+		~reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI_DMUB(reg2),\
+	.ack_mask = \
+		reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_irq_info_funcs\
+	}
+
+#define hpd_rx_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_rx_irq_info_funcs\
+	}
+#define pflip_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+		.funcs = &pflip_irq_info_funcs\
+	}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+}
+
+#define vline0_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+		.funcs = &vline0_irq_info_funcs\
+	}
+#define dmub_outbox_int_entry()\
+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+		IRQ_REG_ENTRY_DMUB(\
+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+		.funcs = &outbox_irq_info_funcs\
+	}
+
+#define dummy_irq_entry() \
+	{\
+		.funcs = &dummy_irq_info_funcs\
+	}
+
+#define i2c_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+	.set = dal_irq_service_dummy_set,
+	.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+	hpd_int_entry(0),
+	hpd_int_entry(1),
+	hpd_int_entry(2),
+	hpd_int_entry(3),
+	hpd_int_entry(4),
+	hpd_rx_int_entry(0),
+	hpd_rx_int_entry(1),
+	hpd_rx_int_entry(2),
+	hpd_rx_int_entry(3),
+	hpd_rx_int_entry(4),
+	i2c_int_entry(1),
+	i2c_int_entry(2),
+	i2c_int_entry(3),
+	i2c_int_entry(4),
+	i2c_int_entry(5),
+	i2c_int_entry(6),
+	dp_sink_int_entry(1),
+	dp_sink_int_entry(2),
+	dp_sink_int_entry(3),
+	dp_sink_int_entry(4),
+	dp_sink_int_entry(5),
+	dp_sink_int_entry(6),
+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+	pflip_int_entry(0),
+	pflip_int_entry(1),
+	pflip_int_entry(2),
+	pflip_int_entry(3),
+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+	gpio_pad_int_entry(0),
+	gpio_pad_int_entry(1),
+	gpio_pad_int_entry(2),
+	gpio_pad_int_entry(3),
+	gpio_pad_int_entry(4),
+	gpio_pad_int_entry(5),
+	gpio_pad_int_entry(6),
+	gpio_pad_int_entry(7),
+	gpio_pad_int_entry(8),
+	gpio_pad_int_entry(9),
+	gpio_pad_int_entry(10),
+	gpio_pad_int_entry(11),
+	gpio_pad_int_entry(12),
+	gpio_pad_int_entry(13),
+	gpio_pad_int_entry(14),
+	gpio_pad_int_entry(15),
+	gpio_pad_int_entry(16),
+	gpio_pad_int_entry(17),
+	gpio_pad_int_entry(18),
+	gpio_pad_int_entry(19),
+	gpio_pad_int_entry(20),
+	gpio_pad_int_entry(21),
+	gpio_pad_int_entry(22),
+	gpio_pad_int_entry(23),
+	gpio_pad_int_entry(24),
+	gpio_pad_int_entry(25),
+	gpio_pad_int_entry(26),
+	gpio_pad_int_entry(27),
+	gpio_pad_int_entry(28),
+	gpio_pad_int_entry(29),
+	gpio_pad_int_entry(30),
+	dc_underflow_int_entry(1),
+	dc_underflow_int_entry(2),
+	dc_underflow_int_entry(3),
+	dc_underflow_int_entry(4),
+	dc_underflow_int_entry(5),
+	dc_underflow_int_entry(6),
+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+	vupdate_no_lock_int_entry(0),
+	vupdate_no_lock_int_entry(1),
+	vupdate_no_lock_int_entry(2),
+	vupdate_no_lock_int_entry(3),
+	vblank_int_entry(0),
+	vblank_int_entry(1),
+	vblank_int_entry(2),
+	vblank_int_entry(3),
+	vline0_int_entry(0),
+	vline0_int_entry(1),
+	vline0_int_entry(2),
+	vline0_int_entry(3),
+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+	dmub_outbox_int_entry(),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn32 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn32
+};
+
+static void dcn32_irq_construct(
+	struct irq_service *irq_service,
+	struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn32;
+	irq_service->funcs = &irq_service_funcs_dcn32;
+}
+
+struct irq_service *dal_irq_service_dcn32_create(
+	struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+						  GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn32_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h
new file mode 100644
index 000000000000..a0d9c9e4e17f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#ifndef __DAL_IRQ_SERVICE_DCN32_H__
+#define __DAL_IRQ_SERVICE_DCN32_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn32_create(
+	struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index f5cb8932bd5c..04049dc5d9df 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -100,6 +100,8 @@ enum dmub_asic {
 	DMUB_ASIC_DCN31B,
 	DMUB_ASIC_DCN315,
 	DMUB_ASIC_DCN316,
+	DMUB_ASIC_DCN32,
+	DMUB_ASIC_DCN321,
 	DMUB_ASIC_MAX,
 };
 
@@ -244,6 +246,7 @@ struct dmub_srv_hw_params {
 	bool dpia_supported;
 	bool disable_dpia;
 	bool usb4_cm_version;
+	bool fw_in_system_memory;
 };
 
 /**
@@ -308,6 +311,9 @@ struct dmub_srv_hw_funcs {
 			      const struct dmub_window *cw0,
 			      const struct dmub_window *cw1);
 
+	void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
 	void (*setup_windows)(struct dmub_srv *dmub,
 			      const struct dmub_window *cw2,
 			      const struct dmub_window *cw3,
@@ -363,6 +369,7 @@ struct dmub_srv_hw_funcs {
 
 	uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);
 
+	void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);
 	void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);
 	uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);
 	void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
@@ -410,6 +417,7 @@ struct dmub_srv {
 	/* private: internal use only */
 	const struct dmub_srv_common_regs *regs;
 	const struct dmub_srv_dcn31_regs *regs_dcn31;
+	const struct dmub_srv_dcn32_regs *regs_dcn32;
 
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 385c28238beb..bf6f017858a6 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -101,6 +101,11 @@
 /* Trace buffer offset for entry */
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
+/**
+ * Maximum number of dirty rects supported by FW.
+ */
+#define DMUB_MAX_DIRTY_RECTS 3
+
 /**
  *
  * PSR control version legacy
@@ -165,6 +170,31 @@ union dmub_addr {
 	uint64_t quad_part; /*<< 64 bit address */
 };
 
+/**
+ * Dirty rect definition.
+ */
+struct dmub_rect {
+	/**
+	 * Dirty rect x offset.
+	 */
+	uint32_t x;
+
+	/**
+	 * Dirty rect y offset.
+	 */
+	uint32_t y;
+
+	/**
+	 * Dirty rect width.
+	 */
+	uint32_t width;
+
+	/**
+	 * Dirty rect height.
+	 */
+	uint32_t height;
+};
+
 /**
  * Flags that can be set by driver to change some PSR behaviour.
  */
@@ -177,6 +207,12 @@ union dmub_psr_debug_flags {
 		 * Enable visual confirm in FW.
 		 */
 		uint32_t visual_confirm : 1;
+
+		/**
+		 * Force all selective updates to bw full frame updates.
+		 */
+		uint32_t force_full_frame_update : 1;
+
 		/**
 		 * Use HW Lock Mgr object to do HW locking in FW.
 		 */
@@ -616,6 +652,14 @@ enum dmub_cmd_type {
 	 * Command type used for all ABM commands.
 	 */
 	DMUB_CMD__ABM = 66,
+	/**
+	 * Command type used to update dirty rects in FW.
+	 */
+	DMUB_CMD__UPDATE_DIRTY_RECT = 67,
+	/**
+	 * Command type used to update cursor info in FW.
+	 */
+	DMUB_CMD__UPDATE_CURSOR_INFO = 68,
 	/**
 	 * Command type used for HW locking in FW.
 	 */
@@ -641,7 +685,10 @@ enum dmub_cmd_type {
 	 * Command type used for all panel control commands.
 	 */
 	DMUB_CMD__PANEL_CNTL = 74,
-
+	/**
+	 * Command type used for <TODO:description>
+	 */
+	DMUB_CMD__CAB_FOR_SS = 75,
 	/**
 	 * Command type used for interfacing with DPIA.
 	 */
@@ -878,6 +925,23 @@ struct dmub_rb_cmd_mall {
 	uint8_t reserved2; /**< Reserved bits */
 };
 
+/**
+ * enum dmub_cmd_cab_type - TODO:
+ */
+enum dmub_cmd_cab_type {
+	DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
+	DMUB_CMD__CAB_NO_DCN_REQ = 1,
+	DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
+};
+
+/**
+ * struct dmub_rb_cmd_cab_for_ss - TODO:
+ */
+struct dmub_rb_cmd_cab_for_ss {
+	struct dmub_cmd_header header;
+	uint8_t cab_alloc_ways; /* total number of ways */
+	uint8_t debug_bits;     /* debug bits */
+};
 /**
  * enum dmub_cmd_idle_opt_type - Idle optimization command type.
  */
@@ -1363,6 +1427,7 @@ struct dmub_rb_cmd_dp_set_config_reply {
 struct dmub_cmd_hpd_state_query_data {
 	uint8_t instance; /**< HPD instance or DPIA instance */
 	uint8_t result; /**< For returning HPD state */
+	uint16_t pad; /** < Alignment */
 	enum aux_channel_type ch_type; /**< enum aux_channel_type */
 	enum aux_return_code_type status; /**< for returning the status of command */
 };
@@ -1419,6 +1484,10 @@ enum dmub_cmd_psr_type {
 	 * Forces PSR enabled until an explicit PSR disable call.
 	 */
 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
+	/**
+	 * Set vtotal in psr active for FreeSync PSR.
+	 */
+	DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
 	/**
 	 * Set PSR power option
 	 */
@@ -1433,6 +1502,10 @@ enum psr_version {
 	 * PSR version 1.
 	 */
 	PSR_VERSION_1				= 0,
+	/**
+	 * Freesync PSR SU.
+	 */
+	PSR_VERSION_SU_1			= 1,
 	/**
 	 * PSR not supported.
 	 */
@@ -1600,9 +1673,15 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint8_t frame_cap_ind;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * Granularity of Y offset supported by sink.
 	 */
-	uint8_t pad[2];
+	uint8_t su_y_granularity;
+	/**
+	 * Indicates whether sink should start capturing
+	 * immediately following active scan line,
+	 * or starting with the 2nd active scan line.
+	 */
+	uint8_t line_capture_indication;
 	/**
 	 * Multi-display optimizations are implemented on certain ASICs.
 	 */
@@ -1613,9 +1692,13 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint16_t init_sdp_deadline;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
+	 */
+	uint8_t rate_control_caps ;
+	/*
+	 * Force PSRSU always doing full frame update
 	 */
-	uint16_t pad2;
+	uint8_t force_ffu_mode;
 	/**
 	 * Length of each horizontal line in us.
 	 */
@@ -1807,6 +1890,164 @@ struct dmub_rb_cmd_psr_force_static {
 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
 };
 
+/**
+ * PSR SU debug flags.
+ */
+union dmub_psr_su_debug_flags {
+	/**
+	 * PSR SU debug flags.
+	 */
+	struct {
+		/**
+		 * Update dirty rect in SW only.
+		 */
+		uint8_t update_dirty_rect_only : 1;
+		/**
+		 * Reset the cursor/plane state before processing the call.
+		 */
+		uint8_t reset_state : 1;
+	} bitfields;
+
+	/**
+	 * Union for debug flags.
+	 */
+	uint32_t u32All;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ * This triggers a selective update for PSR SU.
+ */
+struct dmub_cmd_update_dirty_rect_data {
+	/**
+	 * Dirty rects from OS.
+	 */
+	struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * Number of dirty rects.
+	 */
+	uint8_t dirty_rect_count;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+
+/**
+ * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ */
+struct dmub_rb_cmd_update_dirty_rect {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_cmd_update_cursor_info_data {
+	/**
+	 * Cursor dirty rects.
+	 */
+	struct dmub_rect cursor_rect;
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * Cursor enable/disable.
+	 */
+	uint8_t enable;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+/**
+ * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_rb_cmd_update_cursor_info {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_cmd_update_cursor_info_data update_cursor_info_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_cmd_psr_set_vtotal_data {
+	/**
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
+	 */
+	uint16_t psr_vtotal_idle;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/*
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
+	 */
+	uint16_t psr_vtotal_su;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad2[2];
+};
+
+/**
+ * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_rb_cmd_psr_set_vtotal {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
+};
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
  */
@@ -1917,6 +2158,10 @@ enum hw_lock_client {
 	 * Driver is the client of HW Lock Manager.
 	 */
 	HW_LOCK_CLIENT_DRIVER = 0,
+	/**
+	 * PSR SU is the client of HW Lock Manager.
+	 */
+	HW_LOCK_CLIENT_PSR_SU		= 1,
 	/**
 	 * Invalid client.
 	 */
@@ -2620,7 +2865,6 @@ struct dmub_rb_cmd_get_usbc_cable_id {
  * union dmub_rb_cmd - DMUB inbox command.
  */
 union dmub_rb_cmd {
-	struct dmub_rb_cmd_lock_hw lock_hw;
 	/**
 	 * Elements shared with all commands.
 	 */
@@ -2681,6 +2925,23 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
 	 */
 	struct dmub_rb_cmd_psr_force_static psr_force_static;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_rb_cmd_update_cursor_info update_cursor_info;
+	/**
+	 * Definition of a DMUB_CMD__HW_LOCK command.
+	 * Command is used by driver and FW.
+	 */
+	struct dmub_rb_cmd_lock_hw lock_hw;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
 	/**
 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
 	 */
@@ -2693,6 +2954,10 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__MALL command.
 	 */
 	struct dmub_rb_cmd_mall mall;
+	/**
+	 * Definition of a DMUB_CMD__CAB command.
+	 */
+	struct dmub_rb_cmd_cab_for_ss cab;
 	/**
 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
 	 */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 856c7f48de7a..0589ad4778ee 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -23,6 +23,7 @@
 DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
 DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
 DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o
+DMUB += dmub_dcn32.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
new file mode 100644
index 000000000000..a76da0131add
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -0,0 +1,493 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn32.h"
+
+#include "dcn/dcn_3_2_0_offset.h"
+#include "dcn/dcn_3_2_0_sh_mask.h"
+
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs_dcn32
+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
+
+const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
+#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
+	{
+		DMUB_DCN32_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+		{ DMUB_DCN32_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+		{ DMUB_DCN32_FIELDS() },
+#undef DMUB_SF
+};
+
+static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
+		uint64_t *fb_base,
+		uint64_t *fb_offset)
+{
+	uint32_t tmp;
+
+	if (dmub->fb_base || dmub->fb_offset) {
+		*fb_base = dmub->fb_base;
+		*fb_offset = dmub->fb_offset;
+		return;
+	}
+
+	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+	*fb_base = (uint64_t)tmp << 24;
+
+	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+	*fb_offset = (uint64_t)tmp << 24;
+}
+
+static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
+		uint64_t fb_base,
+		uint64_t fb_offset,
+		union dmub_addr *addr_out)
+{
+	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
+void dmub_dcn32_reset(struct dmub_srv *dmub)
+{
+	union dmub_gpint_data_register cmd;
+	const uint32_t timeout = 30;
+	uint32_t in_reset, scratch, i;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
+
+	if (in_reset == 0) {
+		cmd.bits.status = 1;
+		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+		cmd.bits.param = 0;
+
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/**
+		 * Timeout covers both the ACK and the wait
+		 * for remaining work to finish.
+		 *
+		 * This is mostly bound by the PHY disable sequence.
+		 * Each register check will be greater than 1us, so
+		 * don't bother using udelay.
+		 */
+
+		for (i = 0; i < timeout; ++i) {
+			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+				break;
+		}
+
+		for (i = 0; i < timeout; ++i) {
+			scratch = dmub->hw_funcs.get_gpint_response(dmub);
+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+				break;
+		}
+
+		/* Clear the GPINT command manually so we don't reset again. */
+		cmd.all = 0;
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/* Force reset in case we timed out, DMCUB is likely hung. */
+	}
+
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_SCRATCH0, 0);
+}
+
+void dmub_dcn32_reset_release(struct dmub_srv *dmub)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
+	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
+	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
+}
+
+void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
+		const struct dmub_window *cw0,
+		const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+	uint64_t fb_base, fb_offset;
+
+	dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+			DMCUB_REGION3_CW0_ENABLE, 1);
+
+	dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+			DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+			0x20);
+}
+
+void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
+		      const struct dmub_window *cw0,
+		      const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	offset = cw0->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+			DMCUB_REGION3_CW0_ENABLE, 1);
+
+	offset = cw1->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+			DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+			0x20);
+}
+
+void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
+		const struct dmub_window *cw2,
+		const struct dmub_window *cw3,
+		const struct dmub_window *cw4,
+		const struct dmub_window *cw5,
+		const struct dmub_window *cw6)
+{
+	union dmub_addr offset;
+
+	offset = cw3->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
+	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
+			DMCUB_REGION3_CW3_ENABLE, 1);
+
+	offset = cw4->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+			DMCUB_REGION3_CW4_ENABLE, 1);
+
+	offset = cw5->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
+	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+			DMCUB_REGION3_CW5_ENABLE, 1);
+
+	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
+	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
+			DMCUB_REGION5_TOP_ADDRESS,
+			cw5->region.top - cw5->region.base - 1,
+			DMCUB_REGION5_ENABLE, 1);
+
+	offset = cw6->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
+	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
+			DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+			DMCUB_REGION3_CW6_ENABLE, 1);
+}
+
+void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
+		const struct dmub_region *inbox1)
+{
+	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
+}
+
+uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_INBOX1_RPTR);
+}
+
+void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+{
+	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+}
+
+void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
+		const struct dmub_region *outbox1)
+{
+	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
+	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
+}
+
+uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
+{
+	/**
+	 * outbox1 wptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	return REG_READ(DMCUB_OUTBOX1_WPTR);
+}
+
+void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	/**
+	 * outbox1 rptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
+}
+
+bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+	uint32_t is_hw_init;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
+
+	return is_hw_init != 0 && status.bits.dal_fw;
+}
+
+bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
+{
+	uint32_t supported = 0;
+
+	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
+
+	return supported;
+}
+
+void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
+		union dmub_gpint_data_register reg)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
+}
+
+bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
+		union dmub_gpint_data_register reg)
+{
+	union dmub_gpint_data_register test;
+
+	reg.bits.status = 0;
+	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
+
+	return test.all == reg.all;
+}
+
+uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH7);
+}
+
+uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
+{
+	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
+
+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
+
+	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
+
+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
+
+	return dataout;
+}
+
+union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	return status;
+}
+
+void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
+{
+	union dmub_fw_boot_options boot_options = {0};
+
+	boot_options.bits.z10_disable = params->disable_z10;
+
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+	union dmub_fw_boot_options boot_options;
+	boot_options.all = REG_READ(DMCUB_SCRATCH14);
+	boot_options.bits.skip_phy_init_panel_sequence = skip;
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
+		const struct dmub_region *outbox0)
+{
+	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
+
+	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
+}
+
+uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_OUTBOX0_WPTR);
+}
+
+void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
+}
+
+uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
+
+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
+{
+	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
+	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
+
+	if (!dmub || !diag_data)
+		return;
+
+	memset(diag_data, 0, sizeof(*diag_data));
+
+	diag_data->dmcub_version = dmub->fw_version;
+
+	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
+	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
+	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
+	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
+	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
+	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
+	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
+	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
+	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
+	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
+	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
+	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
+	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
+	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
+	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
+	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
+
+	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
+	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
+	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
+
+	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
+	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
+	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
+
+	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
+	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
+	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
+	diag_data->is_dmcub_enabled = is_dmub_enabled;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
+	diag_data->is_dmcub_soft_reset = is_soft_reset;
+
+	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
+	diag_data->is_dmcub_secure_reset = is_sec_reset;
+
+	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
+	diag_data->is_traceport_en  = is_traceport_enabled;
+
+	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
+	diag_data->is_cw0_enabled = is_cw0_enabled;
+
+	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
+	diag_data->is_cw6_enabled = is_cw6_enabled;
+}
+void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
+{
+	/* DMCUB_REGION3_TMR_AXI_SPACE values:
+	 * 0b011 (0x3) - FB physical address
+	 * 0b100 (0x4) - GPU virtual address
+	 *
+	 * Default value is 0x3 (FB Physical address for TMR). When programming
+	 * DMUB to be in system memory, change to 0x4. The system memory allocated
+	 * is accessible by both GPU and CPU, so we use GPU virtual address.
+	 */
+	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
+}
+
+void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
+{
+	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
+}
+
+void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
+{
+	REG_WRITE(DMCUB_SCRATCH17, 0);
+}
+
+uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH17);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
new file mode 100644
index 000000000000..7d1a6eb4d665
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN32_H_
+#define _DMUB_DCN32_H_
+
+#include "dmub_dcn31.h"
+
+struct dmub_srv;
+
+/* DCN32 register definitions. */
+
+#define DMUB_DCN32_REGS() \
+	DMUB_SR(DMCUB_CNTL) \
+	DMUB_SR(DMCUB_CNTL2) \
+	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX0_SIZE) \
+	DMUB_SR(DMCUB_INBOX0_RPTR) \
+	DMUB_SR(DMCUB_INBOX0_WPTR) \
+	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_INBOX1_SIZE) \
+	DMUB_SR(DMCUB_INBOX1_RPTR) \
+	DMUB_SR(DMCUB_INBOX1_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION4_OFFSET) \
+	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION5_OFFSET) \
+	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_SCRATCH0) \
+	DMUB_SR(DMCUB_SCRATCH1) \
+	DMUB_SR(DMCUB_SCRATCH2) \
+	DMUB_SR(DMCUB_SCRATCH3) \
+	DMUB_SR(DMCUB_SCRATCH4) \
+	DMUB_SR(DMCUB_SCRATCH5) \
+	DMUB_SR(DMCUB_SCRATCH6) \
+	DMUB_SR(DMCUB_SCRATCH7) \
+	DMUB_SR(DMCUB_SCRATCH8) \
+	DMUB_SR(DMCUB_SCRATCH9) \
+	DMUB_SR(DMCUB_SCRATCH10) \
+	DMUB_SR(DMCUB_SCRATCH11) \
+	DMUB_SR(DMCUB_SCRATCH12) \
+	DMUB_SR(DMCUB_SCRATCH13) \
+	DMUB_SR(DMCUB_SCRATCH14) \
+	DMUB_SR(DMCUB_SCRATCH15) \
+	DMUB_SR(DMCUB_SCRATCH16) \
+	DMUB_SR(DMCUB_SCRATCH17) \
+	DMUB_SR(DMCUB_GPINT_DATAIN1) \
+	DMUB_SR(DMCUB_GPINT_DATAOUT) \
+	DMUB_SR(CC_DC_PIPE_DIS) \
+	DMUB_SR(MMHUBBUB_SOFT_RESET) \
+	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+	DMUB_SR(DCN_VM_FB_OFFSET) \
+	DMUB_SR(DMCUB_TIMER_CURRENT) \
+	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
+	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
+	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
+	DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
+	DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
+	DMUB_SR(DMCUB_INTERRUPT_ACK)
+
+#define DMUB_DCN32_FIELDS() \
+	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
+	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
+	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
+	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
+	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
+	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
+	DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
+	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
+	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK)
+
+struct dmub_srv_dcn32_reg_offset {
+#define DMUB_SR(reg) uint32_t reg;
+	DMUB_DCN32_REGS()
+	DMCUB_INTERNAL_REGS()
+#undef DMUB_SR
+};
+
+struct dmub_srv_dcn32_reg_shift {
+#define DMUB_SF(reg, field) uint8_t reg##__##field;
+	DMUB_DCN32_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn32_reg_mask {
+#define DMUB_SF(reg, field) uint32_t reg##__##field;
+	DMUB_DCN32_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn32_regs {
+	const struct dmub_srv_dcn32_reg_offset offset;
+	const struct dmub_srv_dcn32_reg_mask mask;
+	const struct dmub_srv_dcn32_reg_shift shift;
+};
+
+extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
+
+void dmub_dcn32_reset(struct dmub_srv *dmub);
+
+void dmub_dcn32_reset_release(struct dmub_srv *dmub);
+
+void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
+
+void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
+		      const struct dmub_window *cw0,
+		      const struct dmub_window *cw1);
+
+void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6);
+
+void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1);
+
+uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
+void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1);
+
+uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);
+
+bool dmub_dcn32_is_supported(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg);
+
+bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg);
+
+uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);
+
+uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);
+
+void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
+
+void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+
+union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub);
+
+void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0);
+
+uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);
+
+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
+
+void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);
+void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
+void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
+uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);
+
+#endif /* _DMUB_DCN32_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 66db5e538c7f..4c6a624f04a7 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -34,6 +34,7 @@
 #include "dmub_dcn31.h"
 #include "dmub_dcn315.h"
 #include "dmub_dcn316.h"
+#include "dmub_dcn32.h"
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -260,6 +261,43 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 
 		break;
 
+	case DMUB_ASIC_DCN32:
+	case DMUB_ASIC_DCN321:
+		dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
+		funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
+		funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
+		funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
+		funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
+		funcs->reset = dmub_dcn32_reset;
+		funcs->reset_release = dmub_dcn32_reset_release;
+		funcs->backdoor_load = dmub_dcn32_backdoor_load;
+		funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
+		funcs->setup_windows = dmub_dcn32_setup_windows;
+		funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
+		funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
+		funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
+		funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
+		funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
+		funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
+		funcs->is_supported = dmub_dcn32_is_supported;
+		funcs->is_hw_init = dmub_dcn32_is_hw_init;
+		funcs->set_gpint = dmub_dcn32_set_gpint;
+		funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
+		funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
+		funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
+		funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
+		funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
+		funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
+
+		/* outbox0 call stacks */
+		funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
+		funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
+		funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
+		funcs->get_current_time = dmub_dcn32_get_current_time;
+		funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
+
+		break;
+
 	default:
 		return false;
 	}
@@ -501,6 +539,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	cw1.region.base = DMUB_CW1_BASE;
 	cw1.region.top = cw1.region.base + stack_fb->size - 1;
 
+	if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
+		dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
+
 	if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
 		/**
 		 * Read back all the instruction memory so we don't hang the
@@ -508,7 +549,11 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 		 * flushed yet. This only occurs in backdoor loading.
 		 */
 		dmub_flush_buffer_mem(inst_fb);
-		dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+
+		if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
+			dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
+		else
+			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 	}
 
 	cw2.offset.quad_part = data_fb->gpu_addr;
@@ -583,6 +628,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	if (dmub->hw_funcs.enable_dmub_boot_options)
 		dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
 
+	if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
+		dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
+			params->skip_panel_power_sequence);
+
 	if (dmub->hw_funcs.reset_release)
 		dmub->hw_funcs.reset_release(dmub);
 
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index cf4027cc3f4c..812377d9e48f 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -335,4 +335,15 @@ struct bp_soc_bb_info {
 	uint32_t dram_sr_enter_exit_latency_100ns;
 };
 
+struct bp_connector_speed_cap_info {
+	uint32_t DP_HBR2_EN:1;
+	uint32_t DP_HBR3_EN:1;
+	uint32_t HDMI_6GB_EN:1;
+	uint32_t DP_UHBR10_EN:1;
+	uint32_t DP_UHBR13_5_EN:1;
+	uint32_t DP_UHBR20_EN:1;
+	uint32_t DP_IS_USB_C:1;
+	uint32_t RESERVED:28;
+};
+
 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 310f8779db67..a0dffe30b394 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -221,10 +221,6 @@ enum {
 #ifndef ASICREV_IS_VANGOGH
 #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
 #endif
-#define GREEN_SARDINE_A0 0xA1
-#ifndef ASICREV_IS_GREEN_SARDINE
-#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
-#endif
 
 #define FAMILY_YELLOW_CARP                     146
 #define YELLOW_CARP_A0 0x01
@@ -247,6 +243,14 @@ enum {
 
 #define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN))
 
+#define AMDGPU_FAMILY_GC_11_0_0 145
+#define GC_11_0_0_A0 0x1
+#define GC_11_0_2_A0 0x10
+#define GC_11_UNKNOWN 0xFF
+
+#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0)
+#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_UNKNOWN)
+
 /*
  * ASIC chip ID
  */
@@ -280,6 +284,4 @@ enum {
 
 #define	FAMILY_UNKNOWN 0xFF
 
-
-
 #endif /* __DAL_ASIC_ID_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index bf9085fc5105..775c640fc820 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -59,6 +59,8 @@ enum dce_version {
 	DCN_VERSION_3_1,
 	DCN_VERSION_3_15,
 	DCN_VERSION_3_16,
+	DCN_VERSION_3_2,
+	DCN_VERSION_3_21,
 	DCN_VERSION_MAX
 };
 
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 20a3d4e23f66..05096c644a60 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -41,6 +41,10 @@
 #define DP_DEVICE_ID_38EC11 0x38EC11
 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
 
+#define DP_SINK_PSR_ACTIVE_VTOTAL		0x373
+#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE	0x375
+#define DP_SOURCE_PSR_ACTIVE_VTOTAL		0x376
+
 enum ddc_result {
 	DDC_RESULT_UNKNOWN = 0,
 	DDC_RESULT_SUCESSFULL,
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 22053d7ea6ce..ece97ae0e826 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -322,7 +322,7 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg);
  */
 static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2)
 {
-	return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int(arg2).value);
+	return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int((int)arg2).value);
 }
 
 /*
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 447a56286dd0..79fabc51c991 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -67,6 +67,8 @@ enum link_training_result {
 	LINK_TRAINING_CR_FAIL_LANE23,
 	/* CR DONE bit is cleared during EQ step */
 	LINK_TRAINING_EQ_FAIL_CR,
+	/* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
+	LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
 	/* other failure during EQ step */
 	LINK_TRAINING_EQ_FAIL_EQ,
 	LINK_TRAINING_LQA_FAIL,
@@ -92,7 +94,6 @@ struct link_training_settings {
 	/* TODO: turn lane settings below into mandatory fields
 	 * as initial lane configuration
 	 */
-	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 	enum dc_voltage_swing *voltage_swing;
 	enum dc_pre_emphasis *pre_emphasis;
 	enum dc_post_cursor2 *post_cursor2;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 03fa63d56fa6..0686223034de 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1374,6 +1374,11 @@ unsigned long long mod_freesync_calc_field_rate_from_timing(
 	return field_rate_in_uhz;
 }
 
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
+{
+	return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
+}
+
 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
 		uint32_t max_refresh_cap_in_uhz,
 		uint32_t nominal_field_rate_in_uhz)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index 1f4095b26409..c5f6c11de7e5 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -524,7 +524,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
 			set_watchdog_in_ms(hdcp, 3000, output);
 			set_state_id(hdcp, output, D2_A6_WAIT_FOR_RX_ID_LIST);
 		} else {
-			callback_in_ms(0, output);
+			callback_in_ms(1, output);
 			set_state_id(hdcp, output, D2_SEND_CONTENT_STREAM_TYPE);
 		}
 		break;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index be61975f1470..ee67a35c2a8e 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -202,6 +202,10 @@ static enum mod_hdcp_status add_display_to_topology_v3(
 	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
 	dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx;
 	dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational;
+	dtm_cmd->dtm_in_message.topology_update_v3.dio_output_type = link->dp.usb4_enabled ?
+			TA_DTM_DIO_OUTPUT_TYPE__DPIA :
+			TA_DTM_DIO_OUTPUT_TYPE__DIRECT;
+	dtm_cmd->dtm_in_message.topology_update_v3.dio_output_id = link->dio_output_id;
 
 	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
 	mutex_unlock(&psp->dtm_context.mutex);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
index 2937b4b61461..5b71bc96b98c 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
@@ -94,6 +94,15 @@ enum ta_dtm_encoder_type {
 	TA_DTM_ENCODER_TYPE__DIG        = 0x10
 };
 
+/* @enum ta_dtm_dio_output_type
+ * This enum defines software value for dio_output_type
+ */
+typedef enum {
+    TA_DTM_DIO_OUTPUT_TYPE__INVALID,
+    TA_DTM_DIO_OUTPUT_TYPE__DIRECT,
+    TA_DTM_DIO_OUTPUT_TYPE__DPIA
+} ta_dtm_dio_output_type;
+
 struct ta_dtm_topology_update_input_v3 {
 	/* display handle is unique across the driver and is used to identify a display */
 	/* for all security interfaces which reference displays such as HDCP */
@@ -111,6 +120,8 @@ struct ta_dtm_topology_update_input_v3 {
 	enum ta_dtm_encoder_type encoder_type;
 	uint32_t phy_id;
 	uint32_t link_hdcp_cap;
+	ta_dtm_dio_output_type dio_output_type;
+	uint32_t dio_output_id;
 };
 
 struct ta_dtm_topology_assr_enable {
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index cf6bc9446244..afe1f6cce528 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -194,4 +194,7 @@ unsigned int mod_freesync_calc_v_total_from_refresh(
 		const struct dc_stream_state *stream,
 		unsigned int refresh_in_uhz);
 
+// Returns true when FreeSync is supported and enabled (even if it is inactive)
+bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index 79bc207415bc..27ceba9d6d65 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -145,8 +145,10 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 		stereo3dSupport = true;
 	}
 
-	/*VSC packet set to 2 when DP revision >= 1.2*/
-	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
+	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		vsc_packet_revision = vsc_packet_rev4;
+	else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
 		vsc_packet_revision = vsc_packet_rev2;
 
 	/* Update to revision 5 for extended colorimetry support */
@@ -159,6 +161,29 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 	if (vsc_packet_revision == vsc_packet_undefined)
 		return;
 
+	if (vsc_packet_revision == vsc_packet_rev4) {
+		/* Secondary-data Packet ID = 0*/
+		info_packet->hb0 = 0x00;
+		/* 07h - Packet Type Value indicating Video
+		 * Stream Configuration packet
+		 */
+		info_packet->hb1 = 0x07;
+		/* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate
+		 * (applies to eDP v1.4 or higher).
+		 */
+		info_packet->hb2 = 0x04;
+		/* 0Eh = VSC SDP supporting 3D stereo + PSR2
+		 * (HB2 = 04h), with Y-coordinate of first scan
+		 * line of the SU region
+		 */
+		info_packet->hb3 = 0x0E;
+
+		for (i = 0; i < 28; i++)
+			info_packet->sb[i] = 0;
+
+		info_packet->valid = true;
+	}
+
 	if (vsc_packet_revision == vsc_packet_rev2) {
 		/* Secondary-data Packet ID = 0*/
 		info_packet->hb0 = 0x00;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 97928d4c3b9a..bc239d38c3c7 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -822,3 +822,87 @@ bool is_psr_su_specific_panel(struct dc_link *link)
 
 	return false;
 }
+
+/**
+ * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields.
+ * @psr_config: [output], psr configuration structure to be updated
+ * @link: [input] dc link pointer
+ * @stream: [input] dc stream state pointer
+ *
+ * calculate and update the psr configuration fields that are not DM specific, i.e. such
+ * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW,
+ * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr().
+ *
+ * PSR config fields to be updated within the helper:
+ * - psr_rfb_setup_time
+ * - psr_sdp_transmit_line_num_deadline
+ * - line_time_in_us
+ * - su_y_granularity
+ * - su_granularity_required
+ * - psr_frame_capture_indication_req
+ * - psr_exit_link_training_required
+ *
+ * PSR config fields that are DM specific and NOT updated within the helper:
+ * - allow_smu_optimizations
+ * - allow_multi_disp_optimizations
+ */
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream)
+{
+	unsigned int num_vblank_lines = 0;
+	unsigned int vblank_time_in_us = 0;
+	unsigned int sdp_tx_deadline_in_us = 0;
+	unsigned int line_time_in_us = 0;
+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+	const int psr_setup_time_step_in_us = 55;	/* refer to eDP spec DPCD 0x071h */
+
+	/* timing parameters */
+	num_vblank_lines = stream->timing.v_total -
+			 stream->timing.v_addressable -
+			 stream->timing.v_border_top -
+			 stream->timing.v_border_bottom;
+
+	vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
+
+	line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
+
+	/**
+	 * psr configuration fields
+	 *
+	 * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below
+	 * 000b <--> 330 us (default)
+	 * 001b <--> 275 us
+	 * 010b <--> 220 us
+	 * 011b <--> 165 us
+	 * 100b <--> 110 us
+	 * 101b <--> 055 us
+	 * 110b <--> 000 us
+	 */
+	psr_config->psr_rfb_setup_time =
+		(6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;
+
+	if (psr_config->psr_rfb_setup_time > vblank_time_in_us) {
+		link->psr_settings.psr_frame_capture_indication_req = true;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines;
+	} else {
+		sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time;
+
+		/* Set the last possible line SDP may be transmitted without violating the RFB setup time */
+		link->psr_settings.psr_frame_capture_indication_req = false;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us;
+	}
+
+	psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline;
+	psr_config->line_time_in_us = line_time_in_us;
+	psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
+	psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
+	psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req;
+	psr_config->psr_exit_link_training_required =
+		!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
+}
+
+bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
+{
+	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 1a634d8c78c5..316452e9dbc9 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -27,6 +27,7 @@
 
 #include "dc/inc/hw/dmcu.h"
 #include "dc/inc/hw/abm.h"
+#include "dc/inc/core_types.h"
 
 struct resource_pool;
 
@@ -53,4 +54,9 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 		unsigned int inst);
 
 bool is_psr_su_specific_panel(struct dc_link *link);
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream);
+bool mod_power_only_edp(const struct dc_state *context,
+		const struct dc_stream_state *stream);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
index 61ee4be35d27..2c40212d86da 100644
--- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
+++ b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
@@ -66,7 +66,7 @@ static void evict_vmids(struct core_vmid *core_vmid)
 	}
 }
 
-// Return value of -1 indicates vmid table unitialized or ptb dne in the table
+// Return value of -1 indicates vmid table uninitialized or ptb dne in the table
 static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb)
 {
 	int i;
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
index 6df651a94b0a..581ba639b4ea 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
@@ -6981,6 +6981,7 @@
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                  0x27
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
index fa1f4374fafe..fd387c7363b6 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
@@ -13639,6 +13639,8 @@
 #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
 #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
 #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
new file mode 100644
index 000000000000..14c29ce4c7b3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h
@@ -0,0 +1,14677 @@
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_0_OFFSET_HEADER
+#define _dcn_3_2_0_OFFSET_HEADER
+
+
+
+// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dcn_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDSCCLK3_DTO_PARAM                                                                            0x0045
+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDTBCLK_P_CNTL                                                                                0x0068
+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDCCG_TEST_CLK_SEL                                                                            0x00be
+#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regHDMISTREAMCLK_CNTL                                                                           0x0059
+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+#define regDMCUBCLK_CNTL                                                                                0x0067
+#define regDMCUBCLK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dcn_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_CONFIG                                                                           0x008f
+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_STATUS                                                                           0x0090
+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x0091
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0092
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0093
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0094
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0095
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH16                                                                              0x01f3
+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH17                                                                              0x01f4
+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH18                                                                              0x01f5
+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
+#define regDMCUB_SCRATCH19                                                                              0x022e
+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH20                                                                              0x022f
+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH21                                                                              0x0230
+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH22                                                                              0x0231
+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH23                                                                              0x0232
+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regGENENB_BASE_IDX                                                                              1
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dcn_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dcn_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0503
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0504
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0506
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0507
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0509
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050c
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050d
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0510
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0512
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0515
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0516
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0518
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0519
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x051b
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051e
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051f
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0521
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0523
+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0524
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0525
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0527
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0529
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052b
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052d
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052e
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052f
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x0530
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0531
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0532
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0533
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0534
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0536
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0537
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0538
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053f
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0540
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0541
+#define regFMON_CTRL_BASE_IDX                                                                           2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0d8b
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0ef6
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x1061
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x1062
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x11cc
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000e
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc1_dispdec
+// base address: 0x54
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0018
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x0023
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc2_dispdec
+// base address: 0xa8
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x002d
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x0038
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpcc3_dispdec
+// base address: 0xfc
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0042
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x004d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0398
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0399
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x039a
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x039c
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x039d
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x039e
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_AR                                                                             0x03a2
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x03a3
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x03c6
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x178
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x2f0
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x468
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec
+// base address: 0x0
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec
+// base address: 0x240
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec
+// base address: 0x480
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec
+// base address: 0x6c0
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x03d8
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x03dc
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x03e0
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x03e4
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x040b
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x0418
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dcn_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dcn_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dcn_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_dscrm3_dispdec
+// base address: 0xc
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dcn_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b69
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6d
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6e
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6f
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b73
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b74
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b75
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b76
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b77
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b78
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b79
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7a
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b81
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b82
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b83
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b84
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b85
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b86
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b87
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b88
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b89
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8a
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8b
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8c
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8e
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8f
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b96
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b97
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b99
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9a
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba1
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be9
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bed
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bee
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bef
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf3
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf4
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf5
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf6
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf7
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf8
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf9
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfa
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c01
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c02
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c03
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c04
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c05
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c06
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c07
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c08
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c09
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0a
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0b
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0c
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0e
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0f
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c16
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c17
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c19
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1a
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c21
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c69
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6d
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6e
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6f
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c73
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c74
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c75
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c76
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c77
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c78
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c79
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7a
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c81
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c82
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c83
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c84
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c85
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c86
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c87
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c88
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c89
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8a
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8b
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8c
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8e
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8f
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c96
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c97
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c99
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9a
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca1
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce9
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1ced
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cee
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cef
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf3
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf4
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf5
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf6
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf7
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf8
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf9
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfa
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d01
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d02
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d03
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d04
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d05
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d06
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d07
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d08
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d09
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0a
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0b
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0c
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0e
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0f
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d16
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d17
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d19
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1a
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d21
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dcn_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dcn_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_DPIA_SPARE                                                                            0x214a
+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2163
+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x2164
+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x2165
+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x2166
+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x2167
+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x2091
+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x2092
+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2093
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2094
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2095
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2096
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2098
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x209a
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209d
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209e
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a6
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a7
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a9
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20ab
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ad
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20af
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20b0
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b1
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b2
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d8
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d9
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20da
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20db
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dd
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20df
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20e0
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e1
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e3
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e5
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_DPIA_SPARE                                                                            0x224a
+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x2263
+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x2264
+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x2265
+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x2266
+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x2267
+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x2191
+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x2192
+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2193
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2194
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2195
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2196
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2198
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x219a
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219d
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219e
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a6
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a7
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a9
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21ab
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ad
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21af
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21b0
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b1
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b2
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d8
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d9
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21da
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21db
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dd
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21df
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21e0
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e1
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e3
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e5
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_DPIA_SPARE                                                                            0x234a
+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x2363
+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x2364
+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x2365
+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x2366
+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x2367
+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x2291
+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x2292
+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2293
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2294
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2295
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2296
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2298
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x229a
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229d
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229e
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a6
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a7
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a9
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22ab
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ad
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22af
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22b0
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b1
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b2
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d8
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d9
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22da
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22db
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dd
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22df
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22e0
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e1
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e3
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e5
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_DPIA_SPARE                                                                            0x244a
+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x2463
+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x2464
+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x2465
+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x2466
+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x2467
+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2391
+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2392
+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2393
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2394
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2395
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2396
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2398
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x239a
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239d
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239e
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a6
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a7
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a9
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23ab
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ad
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23af
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23b0
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b1
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b2
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d8
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d9
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23da
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23db
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dd
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23df
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23e0
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e1
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e3
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e5
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_DPIA_SPARE                                                                            0x254a
+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2563
+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x2564
+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x2565
+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x2566
+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x2567
+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x2491
+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x2492
+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2493
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2494
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2495
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2496
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2498
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x249a
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249d
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249e
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a6
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a7
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a9
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24ab
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ad
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24af
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24b0
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b1
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b2
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d8
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d9
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24da
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24db
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dd
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24df
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24e0
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e1
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e3
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e5
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e6
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dcn_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dcn_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regDCIO_SPARE                                                                                   0x2882
+#define regDCIO_SPARE_BASE_IDX                                                                          2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886
+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2
+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887
+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dcn_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8
+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2
+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9
+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900
+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec
+// base address: 0x0
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2928
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2929
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x292a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x292b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x292c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x292d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x292e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x292f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2930
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2931
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2932
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2933
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2934
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2935
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2936
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2937
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2938
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2939
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x293a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x293b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x293c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x293d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x293e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x293f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2940
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2941
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2942
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2943
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2944
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2945
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2946
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2947
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2948
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2949
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x294a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x294b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x294c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x294d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x294e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x294f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2950
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2951
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2952
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2953
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2954
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2955
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2956
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2957
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2958
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2959
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x295a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x295b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x295c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x295d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x295e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x295f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2960
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2961
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regDC_GPIO_PWRSEQ_EN                                                                            0x2f10
+#define regDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_PWRSEQ_CTRL                                                                          0x2f11
+#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_MASK                                                                          0x2f12
+#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_A_Y                                                                           0x2f13
+#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_CNTL                                                                            0x2f14
+#define regPANEL_PWRSEQ_CNTL_BASE_IDX                                                                   2
+#define regPANEL_PWRSEQ_STATE                                                                           0x2f15
+#define regPANEL_PWRSEQ_STATE_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_DELAY1                                                                          0x2f16
+#define regPANEL_PWRSEQ_DELAY1_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_DELAY2                                                                          0x2f17
+#define regPANEL_PWRSEQ_DELAY2_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_REF_DIV1                                                                        0x2f18
+#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                               2
+#define regBL_PWM_CNTL                                                                                  0x2f19
+#define regBL_PWM_CNTL_BASE_IDX                                                                         2
+#define regBL_PWM_CNTL2                                                                                 0x2f1a
+#define regBL_PWM_CNTL2_BASE_IDX                                                                        2
+#define regBL_PWM_PERIOD_CNTL                                                                           0x2f1b
+#define regBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
+#define regBL_PWM_GRP1_REG_LOCK                                                                         0x2f1c
+#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
+#define regPANEL_PWRSEQ_REF_DIV2                                                                        0x2f1d
+#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                               2
+#define regPWRSEQ_SPARE                                                                                 0x2f21
+#define regPWRSEQ_SPARE_BASE_IDX                                                                        2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec
+// base address: 0x450
+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e
+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f
+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_STATUS                                                                            0x3120
+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec
+// base address: 0x450
+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec
+// base address: 0x450
+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dcn_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec
+// base address: 0x0
+#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6                                                               0x293b
+#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec
+// base address: 0x360
+#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6                                                               0x2a13
+#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec
+// base address: 0x6c0
+#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6                                                               0x2aeb
+#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec
+// base address: 0xa20
+#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6                                                               0x2bc3
+#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec
+// base address: 0xd80
+#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6                                                               0x2c9b
+#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX                                                      2
+
+
+// addressBlock: dcn_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regCORB_WRITE_POINTER                                                                           0x0000
+#define regCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regCORB_READ_POINTER                                                                            0x0000
+#define regCORB_READ_POINTER_BASE_IDX                                                                   0
+#define regCORB_CONTROL                                                                                 0x0001
+#define regCORB_CONTROL_BASE_IDX                                                                        0
+#define regCORB_STATUS                                                                                  0x0001
+#define regCORB_STATUS_BASE_IDX                                                                         0
+#define regCORB_SIZE                                                                                    0x0001
+#define regCORB_SIZE_BASE_IDX                                                                           0
+#define regRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_WRITE_POINTER                                                                           0x0004
+#define regRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define regRIRB_CONTROL                                                                                 0x0005
+#define regRIRB_CONTROL_BASE_IDX                                                                        0
+#define regRIRB_STATUS                                                                                  0x0005
+#define regRIRB_STATUS_BASE_IDX                                                                         0
+#define regRIRB_SIZE                                                                                    0x0005
+#define regRIRB_SIZE_BASE_IDX                                                                           0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define regDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dcn_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dcn_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+// addressBlock: dcn_dc_hda_azroot_azdec
+// base address: 0x0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                               0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                      0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                              0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                     0
+
+
+// addressBlock: dcn_dc_hda_azstream0_azdec
+// base address: 0x0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x000e
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x000f
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0010
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0011
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0014
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0015
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0761
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream1_azdec
+// base address: 0x20
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0016
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0017
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0018
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0019
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x001c
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x001d
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0769
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream2_azdec
+// base address: 0x40
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x001e
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x001f
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0020
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0021
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0024
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0025
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0771
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream3_azdec
+// base address: 0x60
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0026
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0027
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0028
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0029
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x002c
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x002d
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0779
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream4_azdec
+// base address: 0x80
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x002e
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x002f
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0030
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0031
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0034
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0035
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0781
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream5_azdec
+// base address: 0xa0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0036
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0037
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0038
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0039
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x003c
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x003d
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0789
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream6_azdec
+// base address: 0xc0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x003e
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x003f
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0040
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0041
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0044
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0045
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0791
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dcn_dc_hda_azstream7_azdec
+// base address: 0xe0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0046
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0047
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0048
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0049
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x004c
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x004d
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0799
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: c20_phy_cr0_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr1_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr2_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr3_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+// addressBlock: c20_phy_cr4_rdpcspipecrind
+// base address: 0x0
+#define ixC20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x10cc
+#define ixC20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x12cc
+#define ixC20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x14cc
+#define ixC20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x16cc
+#define ixC20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2021
+#define ixC20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x20c0
+#define ixC20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2221
+#define ixC20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x22c0
+#define ixC20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2421
+#define ixC20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x24c0
+#define ixC20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x2621
+#define ixC20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x26c0
+#define ixC20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x50cc
+#define ixC20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK                                                 0x6021
+#define ixC20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK                                                 0x60c0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
new file mode 100644
index 000000000000..0691e328d0f0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h
@@ -0,0 +1,222893 @@
+
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_0_SH_MASK_HEADER
+#define _dcn_3_2_0_SH_MASK_HEADER
+
+
+// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dcn_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DSCCLK3_DTO_PARAM
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//DCCG_GATE_DISABLE_CNTL4
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+//DPSTREAMCLK_CNTL
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
+//DCCG_GLOBAL_FGCG_REP_CNTL
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0
+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//SYMCLK32_SE_CNTL
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L
+//SYMCLK32_LE_CNTL
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L
+//DTBCLK_P_CNTL
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb
+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L
+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L
+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L
+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L
+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L
+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L
+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L
+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L
+//DCCG_GATE_DISABLE_CNTL5
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L
+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//OTG_PIXEL_RATE_DIV
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT                                                      0x0
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT                                                      0x1
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT                                                      0x3
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT                                                      0x4
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT                                                      0x6
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT                                                      0x7
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT                                                      0x9
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT                                                      0xa
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK                                                        0x00000001L
+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK                                                        0x00000006L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK                                                        0x00000008L
+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK                                                        0x00000030L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK                                                        0x00000040L
+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK                                                        0x00000180L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK                                                        0x00000200L
+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK                                                        0x00000C00L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00003000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//DCCG_TEST_CLK_SEL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT                                                  0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT                                                  0x1c
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK                                                    0x01FF0000L
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK                                                    0x10000000L
+//DTBCLK_DTO0_PHASE
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO1_PHASE
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO2_PHASE
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO3_PHASE
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO0_MODULO
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO1_MODULO
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO2_MODULO
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO3_MODULO
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL
+//HDMICHARCLK0_CLOCK_CNTL
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L
+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYESYMCLK_CLOCK_CNTL
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//HDMISTREAMCLK_CNTL
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT                                               0x4
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L
+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK                                                 0x00000010L
+//DCCG_GATE_DISABLE_CNTL3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//HDMISTREAMCLK0_DTO_PARAM
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L
+//DCCG_AUDIO_DTBCLK_DTO_PHASE
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
+//DCCG_AUDIO_DTBCLK_DTO_MODULO
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL
+//DTBCLK_DTO_DBUF_EN
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L
+//DMCUBCLK_CNTL
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL__SHIFT                                                                0x0
+#define DMCUBCLK_CNTL__DMCUBCLK_SRC_SEL_MASK                                                                  0x00000003L
+
+
+
+
+// addressBlock: dcn_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd
+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L
+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+//OPP_INTERRUPT_DEST
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4
+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+//HPO_INTERRUPT_DEST
+
+
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMCUB_SMU_INTERRUPT_CNTL
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L
+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+
+
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN19_PG_CONFIG
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN19_PG_STATUS
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dcn_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH16
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0
+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH17
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0
+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH18
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0
+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+//DMCUB_CNTL2
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L
+//DMCUB_GPINT_DATAIN2
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN3
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN4
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN5
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN6
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL
+//DMCUB_REGION3_TMR_AXI_SPACE
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0
+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L
+//DMCUB_SCRATCH19
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0
+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH20
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0
+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH21
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0
+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH22
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0
+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH23
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0
+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+
+
+// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT                                                                         0x5
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+#define ATTRX__ATTR_PAL_RW_ENB_MASK                                                                           0x20L
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+#define GENENB__BLK_IO_BASE__SHIFT                                                                            0x0
+#define GENENB__BLK_IO_BASE_MASK                                                                              0xFFL
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_SECURITY_LEVEL
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L
+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_PSTATE_CHANGE_DURATION_VBI
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL
+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//MMHUBBUB_CTRL
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dcn_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                           0x0
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__DRM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                             0x00000001L
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dcn_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dcn_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dcn_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xa
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000003FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x000FFC00L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L
+//DCHUBBUB_ARB_USR_RETRAINING_CNTL
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L
+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK                 0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0
+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L
+//DCHUBBUB_ARB_MALL_CNTL
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L
+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_NOALLOC
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x1
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x2
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x3
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000001L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x00000002L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000004L
+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x00000008L
+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x3
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x6
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0x9
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x00000E00L
+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x3
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x6
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0x9
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x00000007L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x00000038L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x000001C0L
+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x00000E00L
+//SDPIF_REQUEST_RATE_LIMIT
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0
+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_DCC_STAT_CNTL
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L
+//DCHUBBUB_DCC_STAT0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT1
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT2
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL
+//DCHUBBUB_COMPBUF_CTRL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L
+//DCHUBBUB_DET0_CTRL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET1_CTRL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET2_CTRL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_DET3_CTRL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L
+//DCHUBBUB_MEM_PWR_MODE_CTRL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L
+//COMPBUF_MEM_PWR_CTRL_1
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L
+//COMPBUF_MEM_PWR_CTRL_2
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL
+//DCHUBBUB_MEM_PWR_STATUS
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L
+//COMPBUF_RESERVED_SPACE
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
+
+//DCHUBBUB_DEBUG_CTRL_0
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L
+
+// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP0_DCHUBP_MALL_CONFIG
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP0_DCHUBP_MALL_SUB_VP
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP0_HUBP_MALL_STATUS
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ0_UCLK_PSTATE_FORCE
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ0_HUBPREQ_STATUS_REG0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG1
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ0_HUBPREQ_STATUS_REG2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP1_DCHUBP_MALL_CONFIG
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP1_DCHUBP_MALL_SUB_VP
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP1_HUBP_MALL_STATUS
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_DMDATA_VM_CNTL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ1_UCLK_PSTATE_FORCE
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ1_HUBPREQ_STATUS_REG0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG1
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ1_HUBPREQ_STATUS_REG2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP2_DCHUBP_MALL_CONFIG
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP2_DCHUBP_MALL_SUB_VP
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP2_HUBP_MALL_STATUS
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_DMDATA_VM_CNTL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ2_UCLK_PSTATE_FORCE
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ2_HUBPREQ_STATUS_REG0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG1
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ2_HUBPREQ_STATUS_REG2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L
+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL
+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L
+//HUBP3_DCHUBP_MALL_CONFIG
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L
+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L
+//HUBP3_DCHUBP_MALL_SUB_VP
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf
+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL
+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+//HUBP3_HUBP_MALL_STATUS
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L
+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L
+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L
+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L
+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L
+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L
+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L
+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L
+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L
+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L
+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L
+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_DMDATA_VM_CNTL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+//HUBPREQ3_UCLK_PSTATE_FORCE
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L
+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L
+//HUBPREQ3_HUBPREQ_STATUS_REG0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L
+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG1
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL
+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L
+//HUBPREQ3_HUBPREQ_STATUS_REG2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L
+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+
+
+// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dcn_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L
+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec
+//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec
+//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec
+//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec
+//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL
+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_MODE
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L
+//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2
+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL
+//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L
+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L
+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L
+//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L
+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L
+
+
+// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dcn_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_12
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_34
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_CNTL_MISC
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_12
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_34
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_CNTL_MISC
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dcn_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dcn_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dcn_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dcn_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_dscrm3_dispdec
+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dcn_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dcn_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_optc_optc_misc_dispdec
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dcn_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dcn_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_DPIA_SPARE
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP0_DP_AUXLESS_ALPM_CNTL1
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP0_DP_AUXLESS_ALPM_CNTL2
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL3
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_AUXLESS_ALPM_CNTL4
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP0_DP_AUXLESS_ALPM_CNTL5
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_CTRL0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG0_DIG_FIFO_CTRL1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_DPIA_SPARE
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP1_DP_AUXLESS_ALPM_CNTL1
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP1_DP_AUXLESS_ALPM_CNTL2
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL3
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_AUXLESS_ALPM_CNTL4
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP1_DP_AUXLESS_ALPM_CNTL5
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_CTRL0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG1_DIG_FIFO_CTRL1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_DPIA_SPARE
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP2_DP_AUXLESS_ALPM_CNTL1
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP2_DP_AUXLESS_ALPM_CNTL2
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL3
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_AUXLESS_ALPM_CNTL4
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP2_DP_AUXLESS_ALPM_CNTL5
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_CTRL0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG2_DIG_FIFO_CTRL1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_DPIA_SPARE
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP3_DP_AUXLESS_ALPM_CNTL1
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP3_DP_AUXLESS_ALPM_CNTL2
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL3
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_AUXLESS_ALPM_CNTL4
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP3_DP_AUXLESS_ALPM_CNTL5
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_CTRL0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG3_DIG_FIFO_CTRL1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP4_DP_DPHY_INTERNAL_CTRL
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP4_DP_DPIA_SPARE
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0
+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_GSP8_CNTL
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP9_CNTL
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP10_CNTL
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP11_CNTL
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP_EN_DB_STATUS
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+//DP4_DP_AUXLESS_ALPM_CNTL1
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L
+//DP4_DP_AUXLESS_ALPM_CNTL2
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE__SHIFT                                       0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0xf
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM__SHIFT                                              0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x16
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x17
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD__SHIFT                                              0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_SYMBOL_PER_CYCLE_MASK                                         0x00003F00L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00008000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_LFPS_CYCLE_NUM_MASK                                                0x000F0000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00400000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00800000L
+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_SILENCE_PERIOD_MASK                                                0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL3
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL
+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_AUXLESS_ALPM_CNTL4
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x9
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0xa
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0xb
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x0000007FL
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000100L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000200L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000400L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000800L
+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L
+//DP4_DP_AUXLESS_ALPM_CNTL5
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L
+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG4_DIG_FIFO_CTRL0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L
+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L
+//DIG4_DIG_FIFO_CTRL1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L
+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec
+//AFMT4_AFMT_VBI_PACKET_CONTROL
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT4_AFMT_AUDIO_INFO0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT4_AFMT_AUDIO_INFO1
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT4_AFMT_60958_0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT4_AFMT_60958_1
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_CONTROL
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT4_AFMT_RAMP_CONTROL0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT4_AFMT_RAMP_CONTROL1
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT4_AFMT_RAMP_CONTROL2
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_RAMP_CONTROL3
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_60958_2
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_RESULT
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT4_AFMT_STATUS
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT4_AFMT_INFOFRAME_CONTROL0
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT4_AFMT_INTERRUPT_STATUS
+//AFMT4_AFMT_AUDIO_SRC_CONTROL
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT4_AFMT_MEM_PWR
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec
+//DME4_DME_CONTROL
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME4_DME_MEMORY_CONTROL
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec
+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG4_VPG_GENERIC_PACKET_DATA
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG4_VPG_GENERIC_STATUS
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG4_VPG_MEM_PWR
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG4_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG4_VPG_ISRC1_2_DATA
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG4_VPG_MPEG_INFO0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG4_VPG_MPEG_INFO1
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dcn_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT                                                             0x1f
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK                                                               0x80000000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dcn_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L
+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_LINKA_CNTL
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKB_CNTL
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKC_CNTL
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKD_CNTL
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKE_CNTL
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKF_CNTL
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+
+
+// addressBlock: dcn_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//DCIO_SPARE
+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0
+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L
+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L
+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L
+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L
+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L
+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L
+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L
+//DCIO_PATTERN_GEN_PAT
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0
+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL
+//DCIO_PATTERN_GEN_EN
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0
+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dcn_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_DRIVE_STRENGTH_S0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L
+//DC_GPIO_DRIVE_STRENGTH_S1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L
+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_DRIVE_TXIMPSEL
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L
+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec
+//DC_GPIO_PWRSEQ_EN
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00010000L
+//DC_GPIO_PWRSEQ_CTRL
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                                  0x0
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                                    0x1
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                                     0x2
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                                      0x3
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                        0x4
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                         0x5
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                                     0x6
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                                       0x7
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                        0x10
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                        0x14
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                          0x15
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                           0x16
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                                    0x00000001L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                                      0x00000002L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                                       0x00000004L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                        0x00000008L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                          0x00000010L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                           0x00000020L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                                       0x00000040L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                         0x00000080L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                          0x00010000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                          0x00100000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                            0x00200000L
+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                             0x00400000L
+//DC_GPIO_PWRSEQ_MASK
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                                      0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                                    0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                                      0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                        0x00000001L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                                      0x00000010L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                        0x000000C0L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00010000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00100000L
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x00C00000L
+//DC_GPIO_PWRSEQ_A_Y
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                          0x0
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                          0x1
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                            0x8
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                            0x9
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                             0x10
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                             0x11
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                            0x00000001L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                            0x00000002L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                              0x00000100L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                              0x00000200L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                               0x00010000L
+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                               0x00020000L
+//PANEL_PWRSEQ_CNTL
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                             0x0
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                                0x8
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                           0x9
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                            0xa
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                                 0x10
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                            0x11
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                             0x12
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                                  0x18
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                             0x19
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                              0x1a
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                               0x00000001L
+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                                  0x00000100L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                             0x00000200L
+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                              0x00000400L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                                   0x00010000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                              0x00020000L
+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                               0x00040000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                                    0x01000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                               0x02000000L
+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                                0x04000000L
+//PANEL_PWRSEQ_STATE
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                         0x1
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                        0x2
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                          0x3
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                          0x4
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                         0x8
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                           0x00000002L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                            0x00000008L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                            0x00000010L
+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                           0x00000F00L
+//PANEL_PWRSEQ_DELAY1
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                        0x0
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                        0x18
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                          0x000000FFL
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                          0xFF000000L
+//PANEL_PWRSEQ_DELAY2
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                        0x8
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                        0x10
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                          0x0000FF00L
+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                          0x00FF0000L
+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
+//PANEL_PWRSEQ_REF_DIV1
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                          0x10
+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL
+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L
+//BL_PWM_CNTL
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                                 0x13
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                                      0x14
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                    0x15
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                                   0x00080000L
+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                        0x00100000L
+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                      0x00200000L
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
+//BL_PWM_CNTL2
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                                   0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                  0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                                     0x30000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                    0x80000000L
+//BL_PWM_PERIOD_CNTL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
+//BL_PWM_GRP1_REG_LOCK
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
+//PANEL_PWRSEQ_REF_DIV2
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                            0x0
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                               0x8
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                        0x10
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                              0x0000007FL
+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                                 0x00007F00L
+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                          0x00010000L
+//PWRSEQ_SPARE
+#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                                     0x0
+#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                                       0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec
+//DSCC3_DSCC_CONFIG0
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC3_DSCC_CONFIG1
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
+//DSCC3_DSCC_STATUS
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L
+//DSCC3_DSCC_PPS_CONFIG0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG1
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG2
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG3
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG4
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG5
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG6
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC3_DSCC_PPS_CONFIG7
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG8
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG9
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC3_DSCC_PPS_CONFIG11
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC3_DSCC_PPS_CONFIG12
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG13
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG14
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC3_DSCC_PPS_CONFIG15
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG16
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG17
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG18
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG19
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG20
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG21
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC3_DSCC_PPS_CONFIG22
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC3_DSCC_MEM_POWER_CONTROL
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC3_DSCC_MAX_ABS_ERROR0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC3_DSCC_MAX_ABS_ERROR1
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec
+//DSCCIF3_DSCCIF_CONFIG0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF3_DSCCIF_CONFIG1
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec
+//DSC_TOP3_DSC_TOP_CONTROL
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+
+
+// addressBlock: dcn_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L
+//HPO_TOP_HW_CONTROL
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec
+//DP_STREAM_MAPPER_CONTROL0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL1
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL2
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL3
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+//AFMT5_AFMT_VBI_PACKET_CONTROL
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT5_AFMT_AUDIO_INFO0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT5_AFMT_AUDIO_INFO1
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT5_AFMT_60958_0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT5_AFMT_60958_1
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_CONTROL
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT5_AFMT_RAMP_CONTROL0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT5_AFMT_RAMP_CONTROL1
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT5_AFMT_RAMP_CONTROL2
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_RAMP_CONTROL3
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_60958_2
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_RESULT
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT5_AFMT_STATUS
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L
+//AFMT5_AFMT_INFOFRAME_CONTROL0
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT5_AFMT_INTERRUPT_STATUS
+//AFMT5_AFMT_AUDIO_SRC_CONTROL
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT5_AFMT_MEM_PWR
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+//DME5_DME_CONTROL
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME5_DME_MEMORY_CONTROL
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG5_VPG_GENERIC_PACKET_DATA
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG5_VPG_GENERIC_STATUS
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG5_VPG_MEM_PWR
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG5_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG5_VPG_ISRC1_2_DATA
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG5_VPG_MPEG_INFO0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG5_VPG_MPEG_INFO1
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+//APG0_APG_CONTROL
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG0_APG_CONTROL2
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG0_APG_DBG_GEN_CONTROL
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG0_APG_PACKET_CONTROL
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG0_APG_AUDIO_CRC_CONTROL
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG0_APG_AUDIO_CRC_CONTROL2
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG0_APG_AUDIO_CRC_RESULT
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG0_APG_STATUS
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG0_APG_STATUS2
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG0_APG_MEM_PWR
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG0_APG_SPARE
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+//DME6_DME_CONTROL
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME6_DME_MEMORY_CONTROL
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG6_VPG_GENERIC_PACKET_DATA
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG6_VPG_GENERIC_STATUS
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG6_VPG_MEM_PWR
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG6_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG6_VPG_ISRC1_2_DATA
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG6_VPG_MPEG_INFO0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG6_VPG_MPEG_INFO1
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec
+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+//APG1_APG_CONTROL
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG1_APG_CONTROL2
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG1_APG_DBG_GEN_CONTROL
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG1_APG_PACKET_CONTROL
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG1_APG_AUDIO_CRC_CONTROL
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG1_APG_AUDIO_CRC_CONTROL2
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG1_APG_AUDIO_CRC_RESULT
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG1_APG_STATUS
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG1_APG_STATUS2
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG1_APG_MEM_PWR
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG1_APG_SPARE
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+//DME7_DME_CONTROL
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME7_DME_MEMORY_CONTROL
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG7_VPG_GENERIC_PACKET_DATA
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG7_VPG_GENERIC_STATUS
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG7_VPG_MEM_PWR
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG7_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG7_VPG_ISRC1_2_DATA
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG7_VPG_MPEG_INFO0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG7_VPG_MPEG_INFO1
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec
+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+//APG2_APG_CONTROL
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG2_APG_CONTROL2
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG2_APG_DBG_GEN_CONTROL
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG2_APG_PACKET_CONTROL
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG2_APG_AUDIO_CRC_CONTROL
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG2_APG_AUDIO_CRC_CONTROL2
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG2_APG_AUDIO_CRC_RESULT
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG2_APG_STATUS
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG2_APG_STATUS2
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG2_APG_MEM_PWR
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG2_APG_SPARE
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+//DME8_DME_CONTROL
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME8_DME_MEMORY_CONTROL
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG8_VPG_GENERIC_PACKET_DATA
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG8_VPG_GENERIC_STATUS
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG8_VPG_MEM_PWR
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG8_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG8_VPG_ISRC1_2_DATA
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG8_VPG_MPEG_INFO0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG8_VPG_MPEG_INFO1
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec
+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+//APG3_APG_CONTROL
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG3_APG_CONTROL2
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG3_APG_DBG_GEN_CONTROL
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG3_APG_PACKET_CONTROL
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L
+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG3_APG_AUDIO_CRC_CONTROL
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG3_APG_AUDIO_CRC_CONTROL2
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG3_APG_AUDIO_CRC_RESULT
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG3_APG_STATUS
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG3_APG_STATUS2
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG3_APG_MEM_PWR
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG3_APG_SPARE
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+//DME9_DME_CONTROL
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME9_DME_MEMORY_CONTROL
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG9_VPG_GENERIC_PACKET_DATA
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG9_VPG_GENERIC_STATUS
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG9_VPG_MEM_PWR
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG9_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG9_VPG_ISRC1_2_DATA
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG9_VPG_MPEG_INFO0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG9_VPG_MPEG_INFO1
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec
+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec
+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC0_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec
+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC1_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec
+//RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec
+//RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec
+//RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE2_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec
+//RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE3_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec
+//RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
+#define RDPCSPIPE4_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L
+
+
+// addressBlock: dcn_dc_hda_azcontroller_azdec
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                                         0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                                           0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                                           0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                                     0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK                                                             0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                                       0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                                           0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                                 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                                             0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                                      0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                                        0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT                                                                           0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define CORB_SIZE__CORB_SIZE_MASK                                                                             0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                                         0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                                   0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                                           0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                                     0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                                           0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                                             0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                                       0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                               0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                                         0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                                 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                                 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                                  0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                                   0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT                                                                           0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK                                                                             0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT                   0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT                      0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK                     0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK                        0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                               0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                                 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                              0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                                0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                                    0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                                      0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                               0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                               0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                                 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                                 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                                    0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                    0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                               0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                                      0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                      0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                                 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                               0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                                 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                                             0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                      0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                   0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                     0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                     0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                       0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                      0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azroot_azdec
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                        0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                          0xFFFFFFFFL
+//AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                       0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                         0x0001FFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream0_azdec
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream1_azdec
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream2_azdec
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream3_azdec
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream4_azdec
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream5_azdec
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream6_azdec
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: dcn_dc_hda_azstream7_azdec
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                            0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                              0x1
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT          0x2
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT             0x3
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT       0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                          0x10
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                        0x12
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                           0x14
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT      0x1a
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                              0x1b
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                        0x1c
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                              0x1d
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                              0x00000001L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                                0x00000002L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK            0x00000004L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK               0x00000008L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK         0x00000010L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                            0x00030000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                          0x00040000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                             0x00F00000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK        0x04000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                                0x08000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                          0x10000000L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                                0x20000000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT    0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK      0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                    0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                          0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                            0x000000FFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                        0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                          0xFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                     0x4
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                                 0x8
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                                0xb
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                    0xe
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                    0x000FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                       0x0070L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                   0x0700L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                  0x3800L
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                      0x4000L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL
+//AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0
+#define AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL
+
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: c20_phy_cr0_rdpcspipecrind
+//C20_PHY_CR0_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR0_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR0_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR0_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR0_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR0_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe0_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe0_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr1_rdpcspipecrind
+//C20_PHY_CR1_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR1_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR1_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR1_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR1_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR1_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe1_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe1_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr2_rdpcspipecrind
+//C20_PHY_CR2_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR2_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR2_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR2_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR2_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR2_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR2_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR2_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR2_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR2_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR2_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR2_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR2_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR2_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR2_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR2_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR2_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR2_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR2_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR2_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR2_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR2_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR2_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR2_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe2_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe2_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE2_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr3_rdpcspipecrind
+//C20_PHY_CR3_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR3_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR3_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR3_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR3_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR3_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR3_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR3_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR3_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR3_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR3_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR3_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR3_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR3_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR3_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR3_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR3_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR3_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR3_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR3_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR3_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR3_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR3_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR3_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe3_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe3_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE3_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_cr4_rdpcspipecrind
+//C20_PHY_CR4_SUP_DIG_IDCODE_LO
+#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR4_SUP_DIG_IDCODE_LO__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR4_SUP_DIG_IDCODE_HI
+#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
+#define C20_PHY_CR4_SUP_DIG_IDCODE_HI__VAL_MASK                                                               0xFFFFL
+//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_MASK                                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_MASK                                              0x01C0L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_MASK                                                      0x0400L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14_MASK                                             0xC000L
+//C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_MASK                                            0x0003L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_MASK                                             0x0018L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_MASK                                         0x0100L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                                       0x0003L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN_MASK                               0x0004L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_MASK                                                 0x0038L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN_MASK                                         0x0040L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_MASK                                                0x0080L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9_MASK                                                  0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x001CL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0E00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN_MASK                                               0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN_MASK                                            0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL_MASK                                            0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x001CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL_MASK                                 0x0060L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                   0x0700L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN_MASK                                               0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                              0xE000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_MASK                                            0x7F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN_MASK                                    0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_MASK                                           0x7F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN_MASK                                   0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN_MASK                                       0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_MASK                                          0x0018L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN_MASK                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ_MASK                                                     0x0001L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN_MASK                                                 0x0002L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN_MASK                                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN_MASK                                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN_MASK                                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7_MASK                                                 0xFF80L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_MASK                                                0x7C00L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_MASK                                              0x01FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10_MASK                                                0xFC00L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                                    0x0010L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0040L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0080L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0100L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0200L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_MASK                                             0x0400L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_MASK                                              0x1000L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x2000L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14_MASK                                                 0xC000L
+//C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x01C0L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN_MASK                                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV_MASK                                           0x000EL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0380L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS_MASK                                        0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD_MASK                                          0x3000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14_MASK                                              0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW_MASK                                           0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV_MASK                                           0x000EL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV_MASK                                          0x0030L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x01C0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9_MASK                                               0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS_MASK                                         0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_MASK                                            0x3F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS_MASK                                        0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_MASK                                           0x3F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I_MASK                                               0x0003L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO_MASK                                          0x000CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD_MASK                                     0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16_MASK                               0x00F8L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_MASK                                0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE_MASK                                  0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0_MASK                                0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16_MASK                                    0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                     0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT_MASK                                         0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM_MASK                                          0xFFFFL
+//C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                              0x0600L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                        0x3800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR4_SUP_DIG_ASIC_IN_0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__PHY_RESET_MASK                                                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_EN_MASK                                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN_MASK                                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_USE_PAD_MASK                                                       0x0008L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_BURNIN_MASK                                                       0x0010L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN_MASK                                                    0x0020L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RTUNE_REQ_MASK                                                         0x0040L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_REQ_IN_MASK                                                        0x0080L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RES_ACK_IN_MASK                                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__BG_EN_MASK                                                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL_MASK                                                0x0400L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__REF_RANGE_MASK                                                         0x3800L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE_MASK                                                   0x4000L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_0__RESERVED_15_15_MASK                                                    0x8000L
+//C20_PHY_CR4_SUP_DIG_ASIC_IN_1
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__SUP_MISC_MASK                                                          0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN_MASK                                                  0x0100L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN_MASK                                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL_MASK                                                   0x0C00L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL_MASK                                                    0x3000L
+#define C20_PHY_CR4_SUP_DIG_ASIC_IN_1__RESERVED_15_14_MASK                                                    0xC000L
+//C20_PHY_CR4_SUP_DIG_ASIC_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT_MASK                                                0x0001L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLA_STATE_MASK                                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__MPLLB_STATE_MASK                                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RTUNE_ACK_MASK                                                        0x0008L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT_MASK                                                      0x0010L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT_MASK                                                      0x0020L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__DTB_OUT_MASK                                                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ASIC_OUT_0__RESERVED_15_8_MASK                                                    0xFF00L
+//C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x001FL
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00E0L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN_MASK                                                   0x0100L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET_MASK                                                  0x3E00L
+#define C20_PHY_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14_MASK                                                  0xC000L
+//C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9_MASK                                                 0xFE00L
+//C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR4_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET_MASK                                   0x01FFL
+#define C20_PHY_CR4_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL_MASK                               0x01F0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY_MASK                                             0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE_MASK                                        0x007CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7_MASK                                             0xFF80L
+//C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_MASK                                                       0x0002L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL_MASK                                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7_MASK                                                  0xFF80L
+//C20_PHY_CR4_SUP_DIG_RTUNE_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_STATE_MASK                                                      0x1C00L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE_MASK                                                   0x6000L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_15_MASK                                                   0x8000L
+//C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG_MASK                                                    0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN_MASK                                                   0x03FFL
+#define C20_PHY_CR4_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10_MASK                                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE_MASK                                                 0x0001L
+#define C20_PHY_CR4_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER_MASK                                    0x0400L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11_MASK                                      0xF800L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE_MASK                                       0x0002L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE_MASK                                       0x000CL
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE_MASK                                        0x0030L
+#define C20_PHY_CR4_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6_MASK                                       0xFFC0L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT_MASK                                      0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL_MASK                                  0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE_MASK                               0x7F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE_MASK                                  0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE_MASK                                 0x3C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14_MASK                                0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                                         0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP_MASK                               0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME_MASK                 0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME_MASK                   0x3C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME_MASK             0x07FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME_MASK                           0xF800L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME_MASK                          0x001FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME_MASK                    0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME_MASK                 0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME_MASK                    0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME_MASK                  0x0F80L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK                       0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL_MASK                         0x0F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12_MASK                             0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK               0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP_MASK            0x0300L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG_MASK           0x0C00L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3_MASK                        0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3_MASK                        0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME_MASK           0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME_MASK                     0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME_MASK       0x07FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11_MASK                         0xF800L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME_MASK                0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME_MASK               0x03FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10_MASK                         0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2_MASK                                 0xFFFCL
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL_MASK                             0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE_MASK                                     0x007CL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC_MASK                                   0x2000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC_MASK                                   0x4000L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME_MASK                              0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME_MASK                            0x3F00L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14_MASK                         0xC000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME_MASK                         0x00FFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME_MASK                            0xFF00L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME_MASK                        0x003FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME_MASK                           0x0FC0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME_MASK                          0x003FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME_MASK                             0x0FC0L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12_MASK                         0xF000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS_MASK                  0x001FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME_MASK                 0x007FL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7_MASK                          0xFF80L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL_MASK                                        0x7FFFL
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN_MASK                                         0x8000L
+//C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL_MASK                                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT_MASK                                           0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT_MASK                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK_MASK                                               0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC_MASK                                                0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT_MASK                                            0x01F0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL_MASK                                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN_MASK                                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START_MASK                                      0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN_MASK                                              0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL_MASK                                        0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START_MASK                                     0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL_MASK                                           0x0380L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN_MASK                                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST_MASK                                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE_MASK                                                 0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST_MASK                                               0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL_MASK                                         0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST_MASK                                         0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN_MASK                              0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12_MASK                                        0xF000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_MASK                                         0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST_MASK                                         0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE_MASK                                   0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY_MASK                                     0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14_MASK                                        0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_MASK                                                    0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_MASK                                            0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN_MASK                                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_MASK                                            0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER_MASK                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP_MASK                                  0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                            0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_MASK                                        0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_MASK                                     0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                             0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE_MASK                                       0x0180L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE_MASK                                    0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL_MASK                                     0x0006L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL_MASK                                  0x0018L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_MASK                              0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN_MASK                              0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                           0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                           0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_MASK                                 0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN_MASK                        0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_MASK                              0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN_MASK                      0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_MASK                              0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN_MASK                           0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN_MASK                            0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_MASK                                0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                           0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                           0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_MASK                                     0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                       0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN_MASK                           0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                          0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN_MASK                           0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_MASK                               0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4_MASK                                  0xFFF0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC_MASK                                0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT_MASK                                 0xFFC0L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                        0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                            0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                           0x3FF0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_MASK                                            0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_MASK                              0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN_MASK                      0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_MASK                                0x1E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN_MASK                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT__SHIFT                            0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_MASK                                     0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1_MASK                                          0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT_MASK                                    0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START_MASK                               0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG_MASK                                0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST_MASK                                    0x0060L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG_REPEAT_MASK                              0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG_MASK                                     0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2_MASK                             0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_REPEAT_BOOST_MASK                             0x1800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT_MASK                                   0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0__SHIFT                              0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST_MASK                                      0x0003L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX_MASK                               0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0_MASK                           0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6_MASK                                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6_0_MASK                                0x7F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS_MASK                                     0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5__SHIFT                                        0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF_MASK                                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP_MASK                                   0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB_MASK                                        0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP_MASK                                   0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE_MASK                                   0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_5_MASK                                          0x0060L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON_MASK                                   0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_FRC_ATB_CAL_VGEN_MASK                              0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_MEAS_ATB_CAL_VGEN_MASK                             0xF000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE__SHIFT                                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM__SHIFT                                0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR__SHIFT                                0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF__SHIFT                                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_BIAS_CURR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_MODE_MASK                                      0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_CMP_TRIM_MASK                                  0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_RING_CTR_MASK                                  0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SEL_VPLL_REF_MASK                                          0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9_MASK                                         0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0_MASK                                      0x007FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF_MASK                                      0x0180L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR_MASK                             0x7E00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL_MASK                                  0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS_MASK                            0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC_MASK                              0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS_MASK                                 0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4_MASK                                        0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG_MASK                                  0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL_MASK                               0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE_MASK                               0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG_MASK                                0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL_MASK                                  0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG_MASK                                   0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG_MASK                             0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET_MASK                                0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG_MASK                                 0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_MASK                                   0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16__SHIFT                           0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22__SHIFT                           0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21_16_MASK                             0x003FL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT_MASK                                0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28_22_MASK                             0x3F80L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN__SHIFT                       0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG__SHIFT                            0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN_MASK                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN_MASK                             0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW_MASK                                0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW_MASK                                     0x0FF8L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_EN_RST_ALIGN_MASK                         0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_DLL_PRG_MASK                              0x6000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90_MASK                              0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0__SHIFT                                     0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_0_MASK                                       0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0_MASK                                    0x00FFL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT_MASK                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT_MASK                         0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV_MASK                             0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK_MASK                            0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6_MASK                                        0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS_MASK                            0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT_MASK                            0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG_MASK                             0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR_MASK                            0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO_MASK                                0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV_MASK                               0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90_MASK                              0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE_MASK                               0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG_MASK                                0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL_MASK                                  0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG_MASK                                   0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN_MASK                            0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG_MASK                             0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET_MASK                                0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP_MASK                              0x1F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13_MASK                                      0x6000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT_MASK                                0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV__SHIFT                         0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H__SHIFT                         0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ_MASK                         0x0006L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE_MASK                    0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED_MASK                         0x00F0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CP_DIV_MASK                           0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_MODE_H_MASK                           0x0600L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP_MASK                          0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP_MASK                        0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP_MASK                         0x4000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE_MASK                            0x8000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5__SHIFT                                      0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN_MASK                   0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_MASK                              0x001CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_7_5_MASK                                        0x00E0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8_MASK                                       0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START_MASK                       0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE_MASK                          0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH__SHIFT                       0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT_MASK                               0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW_MASK                           0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF_MASK                      0x0004L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS_MASK                                 0x0008L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_BYP_SPOLATCH_MASK                         0x0010L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN_MASK                             0x0020L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP_MASK                               0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO_MASK                              0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR_MASK                          0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING_MASK                             0x0600L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR_MASK                            0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF_MASK                      0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK_MASK                      0x2000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG_MASK                          0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2__SHIFT                     0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N__SHIFT                             0xb
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT_MASK                         0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING_MASK                          0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR_MASK                          0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2_MASK                      0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP_MASK                        0x0040L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_MASK                         0x0080L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED_2_MASK                       0x0100L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X_MASK                                 0x0200L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD_MASK                                   0x0400L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_DIV45_N_MASK                               0x0800L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC_MASK                             0x1000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER_MASK                              0xE000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2__SHIFT                          0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES__SHIFT                             0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF_MASK                            0x0007L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF_MASK                           0x0038L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL_MASK                            0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH_MASK                           0x0C00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM_2_MASK                            0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL_RES_MASK                               0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0_MASK                                        0x0001L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG_MASK                              0x0002L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC_MASK                               0x000CL
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL_MASK                           0x0030L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP_MASK                          0x00C0L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK_MASK                            0x0F00L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN_MASK                      0x3000L
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST_MASK                                0xC000L
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
+#define C20_PHY_CR4_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                   0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_MASK                                                   0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_MASK                                                   0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_MASK                                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_MASK                                                      0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE_MASK                                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME_MASK                                                0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME_MASK                                           0x03C0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10_MASK                                               0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE_MASK                                              0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4_MASK                                               0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ADDR__ADDR_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_DATA__DATA_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_ATE_ALU_ACCUM__VAL_MASK                                                        0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_IN
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE_MASK                                           0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN_MASK                                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_IN__RESERVED_15_4_MASK                                                    0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__DONE_MASK                                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1_MASK                                              0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE_MASK                                            0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2_MASK                                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL_MASK                       0x0180L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK                       0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK                        0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14_MASK                                      0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION
+#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION_MASK                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL_MASK                                                      0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID_MASK                                                    0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9_MASK                                            0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC_MASK                                                  0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL_MASK                                             0x0700L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11_MASK                                            0xF800L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET_MASK                                            0x001FL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET_MASK                                          0x3FE0L
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID_MASK                                                 0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10_MASK                                            0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN_MASK                                           0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV_MASK                                              0x0700L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x1800L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD_MASK                                            0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL_MASK                                              0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN_MASK                                                 0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER_MASK                                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN_MASK                                              0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV_MASK                                              0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV_MASK                                            0x0300L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE_MASK                                            0x7C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT_MASK                                                  0x007FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP_MASK                                                 0x3F80L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO_MASK                                                0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS_MASK                                               0x007FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS_MASK                                              0x3F80L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I_MASK                                                     0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB_MASK                                       0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB_MASK                                       0x01F0L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV_MASK                                       0x1C00L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN_MASK                                                 0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT_MASK                                               0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM_MASK                                                0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV_MASK                                               0x0007L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV_MASK                                     0x0018L
+#define C20_PHY_CR4_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN_MASK                                          0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3_MASK                                       0xFFF8L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3_MASK                                  0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3_MASK                             0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL_MASK                                0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE_MASK                                                0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12_MASK                                            0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                         0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6_MASK                                             0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO_MASK                                         0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                                0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                      0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                              0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12_MASK                                           0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN_MASK                                                  0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK_MASK                                                  0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6_MASK                                               0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL_MASK                                0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL_MASK                                0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL_MASK                                    0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL_MASK                                     0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK_MASK                                            0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4_MASK                                              0xFFF0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL_MASK                    0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT_MASK                                0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE_MASK                                0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                        0x003FL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                    0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7_MASK                                  0x03FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL_MASK                               0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN_MASK                                0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL_MASK                               0x000CL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL_MASK                           0x0060L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS_MASK                                         0x0018L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5_MASK                                                0xFFE0L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_0__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_FW_VERSION_1__VAL_MASK                                                     0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RAW_VERSION__VAL_MASK                                                      0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL_MASK                                       0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN_MASK                                        0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10_MASK                                             0xFC00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL_MASK                                            0xFFFFL
+//C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN_MASK                                              0x0008L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN_MASK                                              0x0010L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE_MASK                                          0x0020L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE_MASK                                          0x0040L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ_MASK                                           0x0100L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL_MASK                                              0x0200L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT_MASK                                           0x0400L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT_MASK                                           0x0800L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL_MASK                                          0x1000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF_MASK                                           0x2000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW_MASK                                            0x4000L
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL_MASK                              0x0FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION_MASK                                  0x7FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_MASK                           0x7FFFL
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN_MASK                   0x8000L
+//C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_MASK                                          0x0018L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6_MASK                                           0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL_MASK                                        0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN_MASK                                         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL_MASK                                          0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL_MASK                                         0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL_MASK                                          0x0070L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN_MASK                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL_MASK                                  0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN_MASK                                                      0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_MASK                                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN_MASK                                    0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_MASK                                          0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN_MASK                                  0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_MASK                                                0x0030L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE_MASK                                          0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x3800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                              0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x3F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14_MASK                                          0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4_MASK                                           0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS_MASK                                                0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN_MASK                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN_MASK                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x007FL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME_MASK                          0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME_MASK                                  0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME_MASK                             0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                                0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                              0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME_MASK                                   0x6000L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                                   0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME_MASK                         0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x07FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME_MASK                               0x7800L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME_MASK                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME_MASK                              0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4_MASK                                   0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL_MASK                                                  0x0038L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE_MASK                                   0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN_MASK                                        0x0200L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11_MASK                                           0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9_MASK                            0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9_MASK                              0xFE00L
+//C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE_MASK                                          0x0007L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE_MASK                                      0x0018L
+#define C20_PHY_CR4_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5_MASK                                             0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_MASK                                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE_MASK                     0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE_MASK                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT_MASK                                   0x007FL
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE_MASK                                   0x0380L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE_MASK                                0x0400L
+#define C20_PHY_CR4_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11_MASK                              0xF800L
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0_MASK                                                 0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32_MASK                                                0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32_MASK                                             0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN_MASK                                          0x000FL
+#define C20_PHY_CR4_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4_MASK                                            0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START_MASK                                          0x0003L
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS_MASK                                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3_MASK                                                 0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN_MASK                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_MASK                                         0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_MASK                                       0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN_MASK                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN_MASK                  0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN_MASK                            0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_MASK                                      0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN_MASK                              0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_MASK                                       0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN_MASK                               0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN_MASK                           0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_MASK                                     0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_MASK                             0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN_MASK                     0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11_MASK                               0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_MASK                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE_MASK         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL_MASK                                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN_MASK                                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN_MASK                         0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL_MASK                           0x00F8L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL_MASK                                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE_MASK                          0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL_MASK                                        0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3_MASK                              0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL_MASK                                  0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                        0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST_MASK                                      0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_MASK                                  0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE_MASK                 0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE_MASK                                       0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7_MASK                                    0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                         0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8_MASK                          0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN_MASK                                        0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN_MASK                                       0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_MASK                                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN_MASK                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL_MASK                                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN_MASK                                    0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST_MASK                                       0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11_MASK                                    0xF800L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE_MASK                                        0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7_MASK                                     0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0_MASK                          0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16_MASK                         0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0_MASK                            0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8_MASK                           0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT_MASK                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT_MASK                                 0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG_MASK                               0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG_MASK                                 0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN_MASK                                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG_MASK                                0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS_MASK                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH_MASK                                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN_MASK                                   0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD_MASK                                        0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX_MASK                          0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP_MASK                                  0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST_MASK                                    0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM_MASK                                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM_MASK                                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF_MASK                                  0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS_MASK                                     0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF_MASK                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_MASK                                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG_MASK                                 0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN_MASK                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2_MASK                             0x01FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM_MASK                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF_MASK                         0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX_MASK                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N_MASK                               0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST_MASK                                 0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS_MASK                                      0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX_MASK                            0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG_MASK                              0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN_MASK                                0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL_MASK                                0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG_MASK                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE_MASK                                  0x0006L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD_MASK                              0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG_MASK                               0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM_MASK                              0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE_MASK                                0x1800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL_MASK                             0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN_MASK                                          0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN_MASK                                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_MASK                                           0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_MASK                                              0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_MASK                                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN_MASK                                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_MASK                                                   0x7000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_MASK                                              0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                      0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_MASK                                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_MASK                                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_MASK                                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_MASK                                           0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL_MASK                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL_MASK                           0x0070L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL_MASK                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_MASK                                        0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_MASK                                          0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x3E00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_MASK                                          0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_MASK                                          0x0180L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_MASK                                          0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_MASK                                          0x7F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN_MASK                                  0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN_MASK                                          0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0380L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x8000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES_MASK                                         0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES_MASK                                         0x00E0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN_MASK                                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL_MASK                                           0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE_MASK                                       0x0780L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL_MASK                                           0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG_MASK                                 0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN_MASK                                          0x0078L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE_MASK                                          0x0700L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS_MASK                                          0x1800L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ_MASK                                       0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA_MASK                                      0x1F00L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                                          0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN_MASK                                         0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN_MASK                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_MASK                            0x1F80L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_MASK                                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9_MASK                                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_MASK                                     0x001FL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_MASK                                    0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN_MASK                             0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK                         0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN_MASK                                 0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN_MASK                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN_MASK                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME_MASK                                    0x0003L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME_MASK                                 0x01FCL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME_MASK                         0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME_MASK                                  0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME_MASK                                0x0060L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME_MASK                               0x0180L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                              0x7E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                              0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN_MASK                                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN_MASK                                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM_MASK                                          0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE_MASK                                        0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK                           0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK                           0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x0FF0L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13_MASK                                0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME_MASK                           0x03F8L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10_MASK                                0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__BER_SEL_MASK                                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6_MASK                                                0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x03C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10_MASK                                           0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
+//C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0300L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                                      0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x0F00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12_MASK                                      0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC_MASK                                        0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ_MASK                              0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2_MASK                                     0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO_MASK                            0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12_MASK                                    0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE_MASK                                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE_MASK                                          0x1E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE_MASK                                      0x6000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10_MASK                                      0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                     0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL_MASK                              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT_MASK                                         0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL_MASK                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN_MASK                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9_MASK                      0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL_MASK                                  0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9_MASK                        0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL_MASK                                   0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9_MASK                         0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL_MASK                               0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9_MASK                     0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL_MASK                                 0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9_MASK                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT_MASK                                       0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT_MASK                                       0x007FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7_MASK                                      0xFF80L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST_MASK                                      0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL_MASK                                      0x03F0L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM_MASK                                        0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS_MASK                                    0x01FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS_MASK                                    0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP_MASK                                         0x3000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14_MASK                                   0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP_MASK                                    0x0700L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH_MASK                                           0x7000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT_MASK                                    0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED_MASK                                         0x1000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN_MASK                                        0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN_MASK                                        0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_MASK                                       0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP_MASK                                0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE_MASK                                        0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE_MASK                                        0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ_MASK                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ_MASK                                 0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE_MASK                                       0x3800L
+#define C20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14_MASK                                  0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0006L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA_MASK                                       0x0180L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE_MASK                                   0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN_MASK                                      0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM_MASK                                        0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN_MASK                                       0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN_MASK                                      0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT_MASK                                         0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL_MASK                                     0x0380L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0_MASK                                     0x003EL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0_MASK                                         0x07C0L
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11_MASK                                         0xF800L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD_MASK                                     0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE_MASK                                     0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_MASK                                               0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE_MASK                                          0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0_MASK                                  0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15_MASK                                 0x7FFFL
+#define C20_PHY_CR4_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA_MASK                                              0xFF00L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE_MASK                                               0x0007L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1_MASK                                               0x0008L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2_MASK                                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN_MASK                                               0x0020L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS_MASK                                          0x0100L
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9_MASK                                           0xFE00L
+//C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE_MASK                                          0x000FL
+#define C20_PHY_CR4_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4_MASK                                             0xFFF0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                   0x001CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN_MASK                           0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                     0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN_MASK                         0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN_MASK                              0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN_MASK                           0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN_MASK                            0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_MASK                           0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN_MASK                   0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN_MASK                        0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_MASK                                    0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN_MASK                       0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_MASK                                      0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_MASK                           0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN_MASK                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN_MASK                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_MASK                         0x007FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN_MASK                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                               0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN_MASK                       0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_MASK                               0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN_MASK                       0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                               0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN_MASK                       0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                              0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN_MASK                      0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10_MASK                                   0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_MASK                            0x0FFFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN_MASK                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13_MASK                                   0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                         0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_MASK                             0x07FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12_MASK                                   0xF000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL_MASK                                       0x001FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL_MASK                                       0x03E0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN_MASK                                      0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN_MASK                                       0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE_MASK                                           0x6000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN_MASK                                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2_MASK                                             0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL_MASK                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                    0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8_MASK                                          0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH_MASK                                0x00FCL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R_MASK                                      0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                            0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_MASK            0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN_MASK    0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5_MASK                            0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_MASK                                0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN_MASK                        0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_MASK                               0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN_MASK                       0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_MASK                                   0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN_MASK                           0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13_MASK                                    0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_MASK                              0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_MASK                             0x00F8L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN_MASK                     0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_MASK                                0x0600L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN_MASK                        0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_MASK                                0x7000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN_MASK                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL_MASK                                      0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3_MASK                                             0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                0x00F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                          0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN_MASK                                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL_MASK                                                0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON_MASK                                         0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL_MASK                                0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN_MASK                                 0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7_MASK                                            0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL_MASK                                            0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN_MASK                                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9_MASK                                  0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                    0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2_MASK                         0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN_MASK                                            0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE_MASK                      0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2_MASK                           0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                      0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                 0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                               0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_MASK                                 0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN_MASK                            0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5_MASK                                 0xFFE0L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_MASK                          0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE_MASK                     0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN_MASK                  0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3_MASK                                 0xFFF8L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL_MASK                                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                 0x003FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                0xFF80L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK           0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                            0xFFFCL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN_MASK                                    0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS_MASK                               0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN_MASK                                    0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN_MASK                               0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN_MASK                                        0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN_MASK                                   0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE_MASK                                     0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST_MASK                              0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS_MASK                              0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG_MASK                                      0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN_MASK                                   0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                   0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP_MASK                                   0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START_MASK                               0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN_MASK                                    0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST_MASK                                     0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT_MASK                                     0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA_MASK                                     0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR_MASK                                       0x7FFCL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_MASK                              0x0007L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_MASK                               0x01F0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN_MASK                       0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0_MASK                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG_MASK                              0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL_MASK                             0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG_MASK                              0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL_MASK                             0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG_MASK                              0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL_MASK                             0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG_MASK                                  0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN_MASK                              0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN_MASK                             0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG_MASK                                    0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG_MASK                                   0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN_MASK                                   0x0004L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG_MASK                                    0x0008L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN_MASK                             0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG_MASK                              0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON_MASK                                    0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG_MASK                                     0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I_MASK                                 0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I_MASK                               0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG_MASK                             0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN_MASK                            0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12_MASK                                       0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I_MASK                            0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6_MASK                               0x000FL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O_MASK                                0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E_MASK                                0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG_MASK                                 0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG_MASK                                0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG_MASK                              0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG_MASK                                    0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN_MASK                                   0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN_MASK                              0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG_MASK                               0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN_MASK                       0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG_MASK                        0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG_MASK                          0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG_MASK                     0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN_MASK                                     0x0020L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG_MASK                                  0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN_MASK                                 0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0_MASK                          0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK_MASK                               0xFC00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2_MASK                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0_MASK                               0x007EL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS_MASK                                  0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0_MASK                           0xFF00L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG_MASK                               0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS_MASK                               0x0002L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3_MASK                          0x0030L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG_MASK                             0x0040L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN_MASK                            0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG_MASK                             0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN_MASK                            0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10_MASK                                       0x1C00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10_MASK                             0xE000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG_MASK                            0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0_MASK                          0x00FEL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG_MASK                           0x0100L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL_MASK                             0x0200L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10_MASK                                       0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8_MASK                             0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG_MASK                                0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START_MASK                               0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG_MASK                       0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I_MASK                         0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_MASK                                0x00FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL_MASK                             0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS_MASK                                 0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8_MASK                           0xF000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL_MASK                         0x0003L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG_MASK                            0x000CL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG_MASK                        0x0010L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG_MASK                          0x0060L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG_MASK                         0x0080L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG_MASK                              0x0300L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG_MASK                            0x0C00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG_MASK                      0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG_MASK                          0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE__SHIFT                                     0xf
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL_MASK                             0x0001L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL_MASK                                       0x0006L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_MASK                                   0x0038L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE_MASK                             0x01C0L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL_MASK                                        0x0E00L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB_MASK                               0x1000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE_MASK                             0x2000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH_MASK                                0x4000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_DISABLE_MASK                                       0x8000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0__SHIFT                                       0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_9_0_MASK                                         0x03FFL
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE_MASK                                        0x0400L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE_MASK                                      0x0800L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF_MASK                                        0x3000L
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14_MASK                                       0xC000L
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0_MASK                                        0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
+#define C20_PHY_CR4_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0_MASK                                    0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_MASK                                 0x00F0L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9_MASK                                 0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM_MASK                                      0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6_MASK                                      0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_MASK                                            0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_MASK                                            0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                    0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_MASK                                          0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                        0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                  0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14_MASK                                     0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN_MASK                                                 0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE_MASK                                        0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ_MASK                                               0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH_MASK                                             0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL_MASK                                        0x3C00L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR_MASK                                         0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT_MASK                                       0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE_MASK                                    0x0F00L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL_MASK                                         0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_MASK                                           0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN_MASK                                   0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_MASK                                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13_MASK                                      0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN_MASK                          0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN_MASK                           0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_MASK                                         0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9_MASK                                       0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER_MASK                                       0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3_MASK                                     0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2_MASK                                            0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK_MASK                                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN_MASK                                   0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN_MASK                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN_MASK                          0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR_MASK             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                       0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN_MASK                                     0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN_MASK                                    0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN_MASK                                0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN_MASK                                     0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN_MASK                                      0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL_MASK                                              0x001FL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5_MASK                                           0xFFE0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE_MASK                                          0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10_MASK                                        0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL_MASK                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN_MASK                      0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7_MASK                                 0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN_MASK                              0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3_MASK                                  0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_MASK                                             0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_MASK                                                0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                        0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_MASK                                            0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_MASK                                         0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_MASK                                      0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN_MASK                              0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_MASK                                          0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_MASK                                     0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN_MASK                             0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_MASK                                 0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN_MASK                         0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_MASK                                     0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN_MASK                             0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN_MASK                              0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_MASK                                        0x01FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_MASK                                     0x0C00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN_MASK                               0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15_MASK                                     0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET_MASK                                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ_MASK                                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2_MASK                                           0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE_MASK                                                  0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD_MASK                                                     0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT_MASK                                                  0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN_MASK                                              0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG_MASK                                           0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ_MASK                                               0x7F00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15_MASK                                          0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC_MASK                                             0x01FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR_MASK                                      0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL_MASK                                          0x1800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13_MASK                                          0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL_MASK                                                0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8_MASK                                           0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL_MASK                                        0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN_MASK                                       0x0078L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL_MASK                                  0x0180L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST_MASK                                     0x3E00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE_MASK                                      0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO_MASK                                      0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE_MASK                                       0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA_MASK                                   0x07C0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_MASK                                       0x1800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ_MASK                                    0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE_MASK                                        0x000CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC_MASK                                              0x0FF0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ_MASK                                          0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG_MASK                                    0x0FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE_MASK                                    0xF000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE_MASK                                              0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL_MASK                                        0x03F8L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN_MASK                                    0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX_MASK                                       0xF800L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH_MASK                                             0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL_MASK                                        0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD_MASK                               0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD_MASK                               0x0038L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN_MASK                             0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL_MASK                                         0x0380L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS_MASK                                        0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS_MASK                                   0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT_MASK                                        0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT_MASK                                       0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14_MASK                                    0xC000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID_MASK                                         0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10_MASK                                    0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN_MASK                                       0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_MASK                                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN_MASK                                         0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4_MASK                                       0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_MASK                                              0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_MASK                                                 0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_MASK                                                0x00E0L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN_MASK                                        0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_MASK                                               0x0E00L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN_MASK                                       0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_MASK                                          0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN_MASK                                  0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15_MASK                                      0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN_MASK                                   0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_MASK                                            0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN_MASK                                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7_MASK                                       0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET_MASK                                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ_MASK                                                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ_MASK                                                 0x003CL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6_MASK                                            0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN_MASK                                   0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1_MASK                                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR_MASK                                         0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST_MASK                                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST_MASK                              0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                  0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                               0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK_MASK                              0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK_MASK                         0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK_MASK                       0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK_MASK                      0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK_MASK                             0x0800L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK_MASK                           0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13_MASK                                     0xE000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN_MASK                                 0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN_MASK                        0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN_MASK                           0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN_MASK                      0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN_MASK                    0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN_MASK                   0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN_MASK                          0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN_MASK                        0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10_MASK                                 0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ_MASK                           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR_MASK       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR_MASK   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1_MASK                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ_MASK         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1_MASK                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR_MASK               0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR_MASK           0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ_MASK                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR_MASK                 0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE_MASK                                          0x003FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6_MASK                                         0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE_MASK                                           0x0003L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2_MASK                                        0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1_MASK                                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_MASK                                          0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD_MASK                                      0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE_MASK                                    0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3_MASK                                    0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN_MASK                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ_MASK                                   0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE_MASK                            0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4_MASK                                      0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN_MASK                      0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN_MASK                      0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN_MASK                          0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT_MASK                                 0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7_MASK                                   0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT_MASK                               0x007FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7_MASK                                  0xFF80L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL_MASK                                           0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL_MASK                                        0x03FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10_MASK                             0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL_MASK                                             0x003FL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6_MASK                                   0xFFC0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN_MASK                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN_MASK                                0x0010L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN_MASK                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN_MASK                                  0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN_MASK                                  0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN_MASK                                       0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN_MASK                                      0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10_MASK                                          0xFC00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE_MASK                                 0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9_MASK                                   0xFE00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4_MASK                                     0xFFF0L
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2_MASK                                      0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15_MASK                                        0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK_MASK                                                  0x0007L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3_MASK                                         0xFFF8L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1_MASK                                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR_MASK                                   0x3FFFL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN_MASK                                     0x4000L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15_MASK                                    0x8000L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE_MASK                                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE_MASK                                          0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2_MASK                                         0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT_MASK                      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL_MASK            0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1_MASK                          0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL_MASK                        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1_MASK                                0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL_MASK          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1_MASK                         0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL_MASK                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1_MASK                            0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD_MASK                          0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1_MASK                                 0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT_MASK  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1_MASK                     0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT_MASK      0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL_MASK              0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1_MASK                        0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL_MASK                  0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1_MASK                             0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL_MASK                    0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1_MASK                              0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING_MASK                                0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE_MASK                                         0x0001L
+#define C20_PHY_CR4_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0_MASK                                        0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2_MASK                                        0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3_MASK                                        0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4_MASK                                        0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR_MASK                                 0x3FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN_MASK                                   0x4000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15_MASK                                  0x8000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE_MASK                                           0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3_MASK                                      0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER_MASK                              0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5_MASK                                  0xFFE0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR_MASK                            0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR_MASK                                      0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER_MASK                                      0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1_MASK                                        0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL_MASK                                           0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL_MASK                                                 0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP_MASK                 0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE_MASK                          0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE_MASK                    0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4_MASK                                 0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT_MASK                             0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP_MASK                                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET_MASK                                       0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL_MASK                                 0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP_MASK                                       0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5_MASK                                       0xFFE0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN_MASK                      0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1_MASK                                   0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_MASK                            0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                    0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                 0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1_MASK                                    0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_MASK                                                0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN_MASK                                        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2_MASK                                          0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                             0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                             0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                              0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2_MASK                              0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1_MASK                                     0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE_MASK                                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE_MASK                                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE_MASK                                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1_MASK                                               0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP_MASK                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP_MASK               0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP_MASK               0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP_MASK                  0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP_MASK                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP_MASK                  0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP_MASK                   0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP_MASK               0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP_MASK                   0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP_MASK               0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP_MASK                 0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP_MASK                0x4000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15_MASK                            0x8000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP_MASK                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP_MASK                   0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP_MASK            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP_MASK                   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP_MASK                   0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP_MASK             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP_MASK             0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP_MASK             0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP_MASK              0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP_MASK             0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP_MASK            0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE_MASK                      0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE_MASK                0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE_MASK                      0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14_MASK                            0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP_MASK        0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP_MASK        0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP_MASK  0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP_MASK   0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP_MASK         0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP_MASK        0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP_MASK        0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP_MASK  0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP_MASK   0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP_MASK         0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD_MASK                    0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP_MASK              0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP_MASK                     0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING_MASK                       0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14_MASK                          0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT_MASK                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT_MASK                               0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT_MASK                               0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT_MASK                               0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT_MASK                          0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT_MASK                        0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT_MASK                       0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT_MASK                                   0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9_MASK                                      0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                   0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT_MASK                                         0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT_MASK                                0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT_MASK                                    0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP_MASK                                         0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                      0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7_MASK                                         0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE_MASK                                    0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9_MASK                                     0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL_MASK                                      0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL_MASK                                      0x1F80L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13_MASK                                        0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM_MASK                                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1_MASK                                          0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST_MASK                               0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST_MASK                               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL_MASK                                               0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2_MASK                                     0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST_MASK                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8_MASK                                  0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK            0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN_MASK                                          0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE_MASK                                             0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA_MASK                                                0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE_MASK                                   0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL_MASK                                   0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL_MASK                                   0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL_MASK                                   0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE_MASK                                    0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE_MASK                                    0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2_MASK                                    0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL_MASK                                   0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2_MASK                                       0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE_MASK                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4_MASK                                0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE_MASK                                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE_MASK                                  0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE_MASK                                0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE_MASK                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE_MASK                            0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE_MASK                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE_MASK                                       0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE_MASK                                        0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE_MASK                                        0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE_MASK                                    0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE_MASK                                      0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE_MASK                                      0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__VAL_MASK                                                       0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8_MASK                                             0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__VAL_MASK                                                     0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1_MASK                                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST_MASK                                            0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL_MASK                                       0x0070L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7_MASK                                           0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER_MASK                                      0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_MASK                                             0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT_MASK                                         0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT_MASK                                        0x03E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10_MASK                                     0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE_MASK                              0x0003L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2_MASK                                  0xFFFCL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL_MASK                                     0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8_MASK                                    0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL_MASK                                     0x01FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL_MASK                             0x03FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL_MASK                              0x0C00L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12_MASK                                  0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL_MASK                           0x1FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13_MASK                              0xE000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL_MASK                           0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12_MASK                              0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST_MASK                       0x003FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6_MASK                           0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD_MASK                       0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1_MASK                           0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_MASK                                        0x007FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD_MASK                                    0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8_MASK                                     0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD_MASK                          0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE_MASK                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1_MASK                                  0xFFFEL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3_MASK                             0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT_MASK                                       0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV_MASK                                     0x01E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9_MASK                                         0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD_MASK                  0x0007L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD_MASK                 0x0038L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6_MASK                              0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD_MASK                  0x000FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD_MASK                 0x00F0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8_MASK                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD_MASK              0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD_MASK             0x03E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10_MASK                           0xFC00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD_MASK                0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD_MASK               0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL_MASK                                                   0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL_MASK                                                  0xFFFFL
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN_MASK                                              0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX_MASK                                              0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN_MASK                              0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE_MASK                         0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT_MASK                                    0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3_MASK                                   0xFFF8L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL_MASK                                            0x0FFFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12_MASK                                 0xF000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_MASK                                             0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_MASK                                             0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN_MASK                                     0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_MASK                                           0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN_MASK                                   0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL_MASK                               0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN_MASK                                0x0080L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL_MASK                               0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN_MASK                                0x0200L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL_MASK                         0x0400L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN_MASK                          0x0800L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL_MASK                             0x1000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN_MASK                              0x2000L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14_MASK                                         0xC000L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT_MASK                         0x00FFL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8_MASK                                 0xFF00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT_MASK                            0x001FL
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT_MASK                            0x00E0L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD_MASK                                0x0100L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9_MASK                                    0xFE00L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL_MASK                                 0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN_MASK                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL_MASK                                 0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN_MASK                                  0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4_MASK                                         0xFFF0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL_MASK                            0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN_MASK                             0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL_MASK                            0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN_MASK                             0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL_MASK                            0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN_MASK                             0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6_MASK                                     0xFFC0L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE_MASK                                                  0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN_MASK                                                  0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC_MASK                                                0x0004L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN_MASK                                             0x0008L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN_MASK                                             0x0010L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS_MASK                                       0x0020L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER_MASK                                           0x0040L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7_MASK                                               0xFF80L
+//C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF_MASK                                               0x0001L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF_MASK                                               0x0002L
+#define C20_PHY_CR4_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2_MASK                                              0xFFFCL
+
+
+// addressBlock: c20_phy_lane0_pipe4_rdpcspipemsgbusind
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE0_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+
+// addressBlock: c20_phy_lane1_pipe4_rdpcspipemsgbusind
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING_MASK           0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET_MASK                  0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET_MASK                 0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING_MASK             0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED_MASK                           0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET_MASK                      0x7FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION_MASK                   0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL_MASK   0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY_MASK                               0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL_MASK                                  0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL_MASK                                 0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS_MASK                         0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST_MASK                           0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED_MASK                                  0xF8L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL_MASK                       0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL_MASK              0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED_MASK                                  0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                         0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED_MASK                                  0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6_MASK                            0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED_MASK                                  0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK             0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0_MASK                                    0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED_MASK                                  0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN_MASK                                 0x07L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING_MASK                                  0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED_MASK                                  0xF0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX_MASK                     0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED_MASK                              0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12_MASK                       0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0_MASK                0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED_MASK                              0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS_MASK         0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN_MASK                             0x07L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING_MASK                              0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED_MASK                              0xF0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS_MASK                  0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED_MASK                              0xFEL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H_MASK                     0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H_MASK                           0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE_MASK             0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES_MASK   0x1EL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE_MASK             0x20L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP_MASK                      0x40L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL_MASK                     0x80L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE_MASK                           0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED_MASK                            0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH_MASK                         0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED_MASK                             0xFCL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER_MASK                 0xFFL
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1_MASK                            0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2_MASK                                0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1_MASK                                0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED_MASK                                     0xF8L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1_MASK                             0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED_MASK                                 0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED_MASK                                0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2_MASK                           0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED_MASK                               0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2_MASK                         0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED_MASK                              0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE_MASK                        0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED_MASK                             0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST_MASK                      0x3FL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED_MASK                            0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x03L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x0CL
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL_MASK  0x30L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED_MASK                       0xC0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL_MASK  0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL_MASK  0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL_MASK    0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL_MASK    0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL_MASK     0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED_MASK                       0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL_MASK    0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL_MASK    0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL_MASK      0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL_MASK      0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL_MASK       0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED_MASK                        0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL_MASK          0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL_MASK          0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL_MASK          0x04L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL_MASK          0x08L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS_MASK                    0x10L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED_MASK                            0xE0L
+//C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN_MASK                      0x01L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN_MASK                     0x02L
+#define C20_PHY_LANE1_PIPE4_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED_MASK                           0xFCL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
new file mode 100644
index 000000000000..3bd8792fd7b3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
@@ -0,0 +1,14561 @@
+/*
+ * Copyright (C) 2022  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_2_1_OFFSET_HEADER
+#define _dcn_3_2_1_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDSCCLK3_DTO_PARAM                                                                            0x0045
+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050
+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDTBCLK_P_CNTL                                                                                0x0068
+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069
+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f
+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDCCG_TEST_CLK_SEL                                                                            0x00be
+#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a
+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regHDMISTREAMCLK_CNTL                                                                           0x0059
+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+#define regDMCUBCLK_CNTL                                                                                0x0067
+#define regDMCUBCLK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd
+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_CONFIG                                                                           0x008f
+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN19_PG_STATUS                                                                           0x0090
+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x0091
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0092
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0093
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0094
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0095
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH16                                                                              0x01f3
+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH17                                                                              0x01f4
+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH18                                                                              0x01f5
+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215
+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216
+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217
+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218
+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219
+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2
+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a
+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2
+#define regDMCUB_SCRATCH19                                                                              0x022e
+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH20                                                                              0x022f
+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH21                                                                              0x0230
+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH22                                                                              0x0231
+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH23                                                                              0x0232
+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regGENENB_BASE_IDX                                                                              1
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298
+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7
+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd
+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0503
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0504
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0506
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0507
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0509
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050c
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x050d
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0510
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0512
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0515
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x0516
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0518
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0519
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x051b
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051e
+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x051f
+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0521
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0523
+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0524
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0525
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0527
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0529
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052b
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052d
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052e
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052f
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x0530
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0531
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0532
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0533
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0534
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0536
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0537
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0538
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053f
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0540
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0541
+#define regFMON_CTRL_BASE_IDX                                                                           2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e
+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f
+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480
+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481
+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482
+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483
+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2
+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484
+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6
+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7
+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff
+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668
+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669
+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a
+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b
+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2
+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3
+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db
+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744
+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745
+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746
+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747
+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae
+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af
+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7
+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820
+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821
+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822
+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823
+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a
+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b
+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893
+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc
+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd
+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe
+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff
+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0d8b
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0ef6
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x1061
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x1062
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x11cc
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009
+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000e
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x54
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0018
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e
+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x0023
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0xa8
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x002d
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033
+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x0038
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0xfc
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0042
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048
+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x004d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0398
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0399
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x039a
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x039c
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x039d
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x039e
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_AR                                                                             0x03a2
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x03a3
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x03c6
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x178
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x2f0
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x468
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec
+// base address: 0x0
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489
+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492
+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc
+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd
+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec
+// base address: 0x240
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519
+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522
+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c
+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d
+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec
+// base address: 0x480
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9
+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2
+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc
+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd
+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec
+// base address: 0x6c0
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639
+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642
+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c
+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d
+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x03d8
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x03dc
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x03e0
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x03e4
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x040b
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x0418
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm3_dispdec
+// base address: 0xc
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b69
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6d
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6e
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6f
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b73
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b74
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b75
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b76
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b77
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b78
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b79
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7a
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b81
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b82
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b83
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b84
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b85
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b86
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b87
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b88
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b89
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8a
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8b
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8c
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8e
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8f
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b96
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b97
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b99
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9a
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba1
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be9
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bed
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bee
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bef
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf3
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf4
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf5
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf6
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf7
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf8
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf9
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfa
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c01
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c02
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c03
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c04
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c05
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c06
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c07
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c08
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c09
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0a
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0b
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0c
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0e
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0f
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c16
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c17
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c19
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1a
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c21
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c69
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6d
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6e
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6f
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c73
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c74
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c75
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c76
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c77
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c78
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c79
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7a
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c81
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c82
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c83
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c84
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c85
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c86
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c87
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c88
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c89
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8a
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8b
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8c
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8e
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8f
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c96
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c97
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c99
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9a
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca1
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce9
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1ced
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cee
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cef
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf3
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf4
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf5
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf6
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf7
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf8
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf9
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfa
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d01
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d02
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d03
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d04
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d05
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d06
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d07
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d08
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d09
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0a
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0b
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0c
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0e
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0f
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d16
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d17
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d19
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1a
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d21
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_DPIA_SPARE                                                                            0x214a
+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2163
+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x2164
+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x2165
+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x2166
+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x2167
+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x2091
+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x2092
+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2093
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2094
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2095
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2096
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2098
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x209a
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209d
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209e
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a6
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a7
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a9
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20ab
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ad
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20af
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20b0
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b1
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b2
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d8
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d9
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20da
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20db
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dd
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20df
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20e0
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e1
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e3
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e5
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_DPIA_SPARE                                                                            0x224a
+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x2263
+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x2264
+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x2265
+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x2266
+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x2267
+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x2191
+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x2192
+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2193
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2194
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2195
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2196
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2198
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x219a
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219d
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219e
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a6
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a7
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a9
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21ab
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ad
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21af
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21b0
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b1
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b2
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d8
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d9
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21da
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21db
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dd
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21df
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21e0
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e1
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e3
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e5
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_DPIA_SPARE                                                                            0x234a
+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x2363
+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x2364
+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x2365
+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x2366
+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x2367
+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x2291
+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x2292
+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2293
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2294
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2295
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2296
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2298
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x229a
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229d
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229e
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a6
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a7
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a9
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22ab
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ad
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22af
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22b0
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b1
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b2
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d8
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d9
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22da
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22db
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dd
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22df
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22e0
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e1
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e3
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e5
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_DPIA_SPARE                                                                            0x244a
+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x2463
+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x2464
+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x2465
+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x2466
+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x2467
+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2391
+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2392
+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2393
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2394
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2395
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2396
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2398
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x239a
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239d
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239e
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a6
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a7
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a9
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23ab
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ad
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23af
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23b0
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b1
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b2
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d8
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d9
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23da
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23db
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dd
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23df
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23e0
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e1
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e3
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e5
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_DPIA_SPARE                                                                            0x254a
+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2563
+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x2564
+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x2565
+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x2566
+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2
+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x2567
+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x2491
+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2
+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x2492
+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2493
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2494
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2495
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2496
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2498
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x249a
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249d
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249e
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a6
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a7
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a9
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24ab
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ad
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24af
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24b0
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b1
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b2
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d8
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d9
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24da
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24db
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dd
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24df
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24e0
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e1
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e3
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e5
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e6
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3
+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regDCIO_SPARE                                                                                   0x2882
+#define regDCIO_SPARE_BASE_IDX                                                                          2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886
+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2
+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887
+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8
+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2
+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9
+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900
+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+// base address: 0x0
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2928
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2929
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x292a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x292b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x292c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x292d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x292e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x292f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2930
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2931
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2932
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2933
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2934
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2935
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2936
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2937
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2938
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2939
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x293a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x293b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x293c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x293d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x293e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x293f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2940
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2941
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2942
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2943
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2944
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2945
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2946
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2947
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2948
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2949
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x294a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x294b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x294c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x294d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x294e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x294f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2950
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2951
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2952
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2953
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2954
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2955
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2956
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2957
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2958
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2959
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x295a
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x295b
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x295c
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x295d
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x295e
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x295f
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2960
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2961
+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regDC_GPIO_PWRSEQ_EN                                                                            0x2f10
+#define regDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_PWRSEQ_CTRL                                                                          0x2f11
+#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_MASK                                                                          0x2f12
+#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_PWRSEQ_A_Y                                                                           0x2f13
+#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_CNTL                                                                            0x2f14
+#define regPANEL_PWRSEQ_CNTL_BASE_IDX                                                                   2
+#define regPANEL_PWRSEQ_STATE                                                                           0x2f15
+#define regPANEL_PWRSEQ_STATE_BASE_IDX                                                                  2
+#define regPANEL_PWRSEQ_DELAY1                                                                          0x2f16
+#define regPANEL_PWRSEQ_DELAY1_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_DELAY2                                                                          0x2f17
+#define regPANEL_PWRSEQ_DELAY2_BASE_IDX                                                                 2
+#define regPANEL_PWRSEQ_REF_DIV1                                                                        0x2f18
+#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                               2
+#define regBL_PWM_CNTL                                                                                  0x2f19
+#define regBL_PWM_CNTL_BASE_IDX                                                                         2
+#define regBL_PWM_CNTL2                                                                                 0x2f1a
+#define regBL_PWM_CNTL2_BASE_IDX                                                                        2
+#define regBL_PWM_PERIOD_CNTL                                                                           0x2f1b
+#define regBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
+#define regBL_PWM_GRP1_REG_LOCK                                                                         0x2f1c
+#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
+#define regPANEL_PWRSEQ_REF_DIV2                                                                        0x2f1d
+#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                               2
+#define regPWRSEQ_SPARE                                                                                 0x2f21
+#define regPWRSEQ_SPARE_BASE_IDX                                                                        2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
+// base address: 0x450
+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e
+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f
+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC3_DSCC_STATUS                                                                            0x3120
+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
+// base address: 0x450
+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
+// base address: 0x450
+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regCORB_WRITE_POINTER                                                                           0x0000
+#define regCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regCORB_READ_POINTER                                                                            0x0000
+#define regCORB_READ_POINTER_BASE_IDX                                                                   0
+#define regCORB_CONTROL                                                                                 0x0001
+#define regCORB_CONTROL_BASE_IDX                                                                        0
+#define regCORB_STATUS                                                                                  0x0001
+#define regCORB_STATUS_BASE_IDX                                                                         0
+#define regCORB_SIZE                                                                                    0x0001
+#define regCORB_SIZE_BASE_IDX                                                                           0
+#define regRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define regRIRB_WRITE_POINTER                                                                           0x0004
+#define regRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define regRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define regRIRB_CONTROL                                                                                 0x0005
+#define regRIRB_CONTROL_BASE_IDX                                                                        0
+#define regRIRB_STATUS                                                                                  0x0005
+#define regRIRB_STATUS_BASE_IDX                                                                         0
+#define regRIRB_SIZE                                                                                    0x0005
+#define regRIRB_SIZE_BASE_IDX                                                                           0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define regIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define regDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define regWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+// addressBlock: dce_dc_hda_azroot_azdec
+// base address: 0x0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                               0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                      0
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                              0x0006
+#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                     0
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+// base address: 0x0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x000e
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x000f
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0010
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0011
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0012
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0014
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0015
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0761
+#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+// base address: 0x20
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0016
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0017
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0018
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0019
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x001a
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x001c
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x001d
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0769
+#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+// base address: 0x40
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x001e
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x001f
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0020
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0021
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0022
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0024
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0025
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0771
+#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+// base address: 0x60
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0026
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0027
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0028
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0029
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x002a
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x002c
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x002d
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0779
+#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+// base address: 0x80
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x002e
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x002f
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0030
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0031
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0032
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0034
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0035
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0781
+#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+// base address: 0xa0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0036
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0037
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0038
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0039
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x003a
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x003c
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x003d
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0789
+#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+// base address: 0xc0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x003e
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x003f
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0040
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0041
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0042
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0044
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0045
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0791
+#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+// base address: 0xe0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0046
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0047
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0048
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0049
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x004a
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x004c
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x004d
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0799
+#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#de